repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
pavel-demin/red-pitaya-notes | cores/axis_pps_counter_v1_0/axis_pps_counter.v | 1,359 | module MODULE1 #
(
parameter integer VAR5 = 32,
parameter integer VAR22 = 32
)
(
input wire VAR18,
input wire VAR2,
input wire VAR6,
output wire [VAR5-1:0] VAR21,
output wire VAR4
);
reg [VAR22-1:0] VAR3;
reg VAR20;
reg [1:0] VAR19;
wire VAR11, VAR14;
VAR8 #(
.VAR16(4),
.VAR10(0),
.VAR12(0),
.VAR17(0)
) VAR9 (
.VAR13(V... | mit |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/hps_design.v | 27,938 | module MODULE1 (
input wire VAR116, output wire [14:0] VAR35, output wire [2:0] VAR193, output wire VAR30, output wire VAR194, output wire VAR205, output wire VAR206, output wire VAR181, output wire VAR176, output wire VAR73, output wire VAR124, inout wire [31:0] VAR55, inout wire [3:0] VAR242, inout wire [3:0] VAR54, ... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_clk_pad.v | 4,671 | module MODULE1(
VAR14, VAR23,
VAR3,
VAR24, VAR19, VAR25, VAR9, VAR17, VAR5,
VAR20, VAR16, VAR8, VAR27, VAR15,
VAR4, clk, VAR7, VAR18, VAR12
);
input VAR12; input [8:1] VAR18; input [8:1] VAR7; input clk; input VAR4; input VAR15; input VAR27; input VAR8; input VAR16; input VAR20; input VAR5; input VAR17; input VAR9; inp... | gpl-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/dotp_wrapper.v | 2,342 | module MODULE1 (
VAR12,
VAR5,
VAR23,
VAR10,
VAR1,
VAR2,
VAR16, VAR7, VAR11, VAR18,
b0, b1, VAR19, VAR15,
VAR8
);
input VAR12;
input VAR5;
input VAR23;
input VAR10;
output VAR1;
output VAR2;
input [511:0] VAR16;
input [511:0] VAR7;
input [511:0] VAR11;
input [511:0] VAR18;
input [511:0] b0;
input [511:0] b1;
input [511:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3/sky130_fd_sc_hd__nand3.pp.blackbox.v | 1,293 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR8 ,
VAR4 ,
VAR2,
VAR7,
VAR1 ,
VAR6
);
output VAR5 ;
input VAR3 ;
input VAR8 ;
input VAR4 ;
input VAR2;
input VAR7;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/ctrl_transmemory.v | 3,471 | module MODULE1(
clk,
rst,
VAR6,
VAR4,
VAR3,
enable,
counter
);
input clk;
input rst;
input VAR6;
input [1:0] VAR4;
output reg VAR3;
output enable;
output reg [4:0] counter;
wire VAR7;
wire VAR2;
reg VAR8;
reg VAR1;
reg VAR5;
assign VAR7=VAR6; assign VAR2=VAR3||VAR8||VAR1;
assign enable= VAR7||VAR2;
always@(posedge clk ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3.functional.pp.v | 1,832 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR2,
VAR1,
VAR10 ,
VAR6
);
output VAR7 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR10 ;
input VAR6 ;
wire VAR4 ;
wire VAR12;
buf VAR11 (VAR4 , VAR5 );
VAR9 VAR3 (VAR12, VAR4, VAR2, VAR1);
buf VAR8 (VAR7 , VAR12 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_clk_gen/bsg_clk_gen_osc.v | 4,809 | module MODULE1
import VAR4::VAR6;
(
input VAR3
,input VAR6 VAR20
,output VAR27
);
wire VAR37, VAR9; wire VAR28 = ~VAR3;
VAR34 VAR13;
wire VAR1;
VAR35 #(.VAR23(VAR32(VAR34))
,.VAR10(1)
,.VAR8(0)
) VAR36
(.VAR20 (VAR20)
,.VAR7 (VAR9)
,.VAR33 (1'b0) ,.VAR22 (VAR1) ,.VAR5(VAR13)
);
wire VAR29, VAR26;
wire VAR18;
assign VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22o/sky130_fd_sc_hvl__a22o.functional.v | 1,515 | module MODULE1 (
VAR6 ,
VAR8,
VAR10,
VAR4,
VAR2
);
output VAR6 ;
input VAR8;
input VAR10;
input VAR4;
input VAR2;
wire VAR11 ;
wire VAR5 ;
wire VAR12;
and VAR1 (VAR11 , VAR4, VAR2 );
and VAR9 (VAR5 , VAR8, VAR10 );
or VAR7 (VAR12, VAR5, VAR11);
buf VAR3 (VAR6 , VAR12 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_dds_top.v | 14,104 | module MODULE1 (
VAR35,
VAR70,
VAR33,
VAR59,
VAR34,
VAR63,
VAR12,
VAR8,
VAR36,
VAR21,
VAR57,
VAR48,
VAR6,
VAR68,
VAR45,
VAR41,
VAR71,
VAR27,
VAR61, VAR10, VAR31, VAR25, VAR82, VAR4, VAR23, VAR22, VAR62, VAR80, VAR54, VAR64, VAR37, VAR67, VAR47, VAR9, VAR76, VAR14, VAR42, VAR13, VAR18, VAR40, VAR46,
VAR26,
VAR53,
VAR19,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv_1.v | 1,995 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR8,
VAR6,
VAR2 ,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR8;
input VAR6;
input VAR2 ;
input VAR5 ;
VAR7 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
supply1 VAR8;
supply0 VAR6;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2b/sky130_fd_sc_ms__nor2b_1.v | 2,173 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR2 ,
VAR3,
VAR1,
VAR7 ,
VAR9
);
output VAR4 ;
input VAR6 ;
input VAR2 ;
input VAR3;
input VAR1;
input VAR7 ;
input VAR9 ;
VAR5 VAR8 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR4 ,
VAR6 ,
VAR2
);
output VAR4... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9649_v1_00_a/hdl/verilog/cf_adc_if.v | 10,317 | module MODULE1 (
VAR77,
VAR26,
VAR4,
VAR46,
VAR73,
VAR80,
VAR86,
VAR42,
VAR71,
VAR32,
VAR38,
VAR55,
VAR60,
VAR39);
parameter VAR11 = 0;
parameter VAR33 = 0;
parameter VAR41 = 1;
input VAR77;
input [13:0] VAR26;
input VAR4;
output VAR46;
output [13:0] VAR73;
output VAR80;
input VAR86;
input VAR42;
input [ 3:0] VAR71;
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi.pp.blackbox.v | 1,370 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR4 ,
VAR2 ,
VAR3 ,
VAR6 ,
VAR7,
VAR8
);
output VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR7;
input VAR8;
endmodule | apache-2.0 |
dingzh/piplined-MIPS-CPU | src/LAB6/forwardUnit.v | 1,275 | module MODULE1(
input [4:0] VAR7,
input [4:0] VAR4,
input VAR1,
input [4:0] VAR2,
input VAR5,
input [4:0] VAR3,
output reg [1:0] VAR8,
output reg [1:0] VAR6,
input rst
);
always @(*) begin
if(rst) begin
VAR8 = 'b00;
VAR6 = 'b00;
end
else
begin
if(VAR1 & VAR2 != 0 & VAR2 == VAR7) VAR8 = 'b01;
end
else if(VAR5 & VAR3 != ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.functional.pp.v | 1,864 | module MODULE1( VAR25, VAR17, VAR23, VAR9, VAR22, VAR18, VAR21, VAR7, VAR24 );
input VAR22, VAR18, VAR21, VAR23, VAR25, VAR17;
inout VAR7, VAR24;
output VAR9;
wire VAR15;
not VAR14( VAR15, VAR22 );
wire VAR8;
not VAR3( VAR8, VAR18 );
wire VAR20;
not VAR6( VAR20, VAR21 );
wire VAR2;
and VAR12( VAR2, VAR15, VAR8, VAR20 )... | apache-2.0 |
manu3193/GatoTDD | Sincronizador.v | 7,313 | module MODULE1( clk, VAR10, VAR27, VAR5, VAR13, VAR9,
VAR23, VAR7, VAR20, VAR16, VAR24);
input VAR10, VAR27, VAR5, VAR13, VAR9, clk;
output reg VAR23, VAR7, VAR20, VAR16, VAR24;
localparam VAR14= 20'd1000000;
reg VAR21;
reg VAR8;
reg VAR2;
reg VAR17;
reg VAR6;
always @(posedge clk)
begin
VAR21 <= VAR10;
VAR8 <= VAR27;
... | mit |
hoglet67/CoPro6502 | src/m32632/CACHE_LOGIK.v | 28,732 | module MODULE2 ( VAR28, VAR195, VAR131, VAR8, VAR139, VAR133, VAR2, VAR173, VAR41, VAR154 );
input [40:2] VAR28;
input VAR195,VAR131;
input VAR8;
input VAR139;
input VAR133;
input [31:2] VAR2;
input [19:0] VAR173;
input [3:0] VAR41;
output VAR154;
wire VAR174,VAR65,VAR134,VAR194,VAR44;
wire VAR68;
wire VAR72,VAR176,VAR... | gpl-3.0 |
finnball/igloo | projects/uart_echo/hdl/top.v | 1,223 | module MODULE1(
input VAR37,
input VAR9,
input VAR6,
output [7:0] VAR22,
output VAR25
);
reg VAR26 = 0, VAR30 = 0, VAR3 = 0, VAR7 = 0;
reg [VAR28 - 1 : 0] VAR14 = 0, VAR16 = 0;
wire VAR32, VAR17;
wire VAR21, VAR29, VAR12;
wire [VAR28 - 1 : 0] VAR31, VAR34;
VAR2 VAR2 (
.VAR24 (VAR37),
.VAR35(VAR32),
.VAR27(VAR17),
.VAR5... | gpl-3.0 |
lvd2/zxevo | fpga/base_trdemu/trunk/z80/zdos.v | 2,243 | module MODULE1(
input wire VAR3,
input wire VAR5,
input wire VAR7,
input wire VAR11,
input wire VAR14,
output reg VAR2,
input wire VAR16,
input wire VAR12,
output reg VAR4,
input wire VAR13, input wire VAR1,
input wire [ 3:0] VAR8,
input wire [ 1:0] VAR15,
input wire VAR6,
output reg VAR10
);
wire VAR9 = VAR1 && VAR8[V... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sd_host/rtl/phy/sd_spi_phy.v | 3,488 | module MODULE1 (
input clk,
input rst,
input VAR22,
input VAR28,
input VAR7,
input VAR9,
input VAR2,
input [39:0] VAR11,
input VAR26,
output reg VAR18,
output [135:0] VAR21,
input VAR6,
output reg VAR20,
input VAR13,
output VAR19,
input [23:0] VAR5,
output VAR17,
input [31:0] VAR23,
input [1:0] VAR14,
output [1:0] VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probe_p/sky130_fd_sc_hdll__probe_p.symbol.v | 1,285 | module MODULE1 (
input VAR2,
output VAR3
);
supply1 VAR6;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
donnaware/AGC | rtl/de0/modules/vji_dsky.v | 3,623 | module MODULE1(
input clk, input [7:0] VAR3, output reg [3:0] VAR25, output reg [4:0] VAR1, output VAR11, output reg VAR6 );
wire VAR21; wire VAR27; wire VAR15; wire VAR5; wire VAR8; wire VAR23; wire VAR2; VAR24 VAR14(
.VAR27 ( VAR27 ), .VAR15 ( VAR15 ), .VAR21 ( VAR21 ), .VAR22 ( VAR20 ), .VAR17 ( 3'b000 ), .VAR12 ( V... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_ctrl.v | 29,418 | module MODULE1(
clk, rst,
VAR18, VAR56, VAR91, VAR68, VAR99, VAR100, VAR11, VAR45,
VAR98, VAR78, VAR3, VAR57, VAR92, VAR83, VAR8, VAR14, VAR6, VAR20,
VAR60, VAR86, VAR25, VAR84, VAR17, VAR67, VAR49,
VAR105, VAR36,
VAR4, VAR1, VAR101, VAR44, VAR64, VAR72,
VAR52, VAR31, VAR23, VAR80, VAR26, VAR19, VAR15
);
input clk;
inp... | gpl-2.0 |
asicguy/gplgpu | hdl/de_temp/dex_reg.v | 47,659 | module MODULE1
(
input VAR56,
input VAR25,
input [159:0] VAR48,
input VAR141,
input VAR20,
input VAR234,
input VAR153,
input VAR198,
input VAR227,
input VAR88,
input [4:0] VAR90,
input [4:0] VAR174,
input [3:0] VAR83,
input [1:0] VAR134,
input VAR95,
input VAR102,
input VAR42,
input VAR188,
input VAR23,
input [3:0] VAR... | gpl-3.0 |
kyzhai/NUNY | src/hardware/city.v | 6,353 | module MODULE1 (
address,
VAR3,
VAR6);
input [14:0] address;
input VAR3;
output [15:0] VAR6;
tri1 VAR3;
wire [15:0] VAR11;
wire [15:0] VAR6 = VAR11[15:0];
VAR23 VAR35 (
.VAR15 (address),
.VAR51 (VAR3),
.VAR40 (VAR11),
.VAR16 (1'b0),
.VAR4 (1'b0),
.VAR38 (1'b1),
.VAR12 (1'b0),
.VAR45 (1'b0),
.VAR48 (1'b1),
.VAR29 (1'b1)... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/SHDCluster.v | 1,859 | module MODULE1 #(parameter VAR3 = 128, VAR25 = 8) (
input clk,
input rst,
input[VAR3 - 1:0] VAR26,
input[VAR3*VAR25 - 1:0] VAR24,
input VAR9,
output VAR23,
input VAR29,
input VAR21,
output[VAR25 - 1:0] VAR15,
output VAR12
);
reg[VAR3 - 1:0] VAR18;
reg VAR30;
wire VAR6, VAR5;
always@(posedge clk) begin
if(rst) begin
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2.pp.symbol.v | 1,271 | module MODULE1 (
input VAR4 ,
input VAR7 ,
output VAR2 ,
input VAR1 ,
input VAR6,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd/sky130_fd_sc_hd__tapvgnd.pp.symbol.v | 1,258 | module MODULE1 (
input VAR1 ,
input VAR2,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/whoosh_new.v | 6,419 | module MODULE1 (
address,
VAR38,
VAR41);
input [12:0] address;
input VAR38;
output [11:0] VAR41;
tri1 VAR38;
wire [11:0] VAR30;
wire [11:0] VAR41 = VAR30[11:0];
VAR4 VAR33 (
.VAR24 (address),
.VAR1 (VAR38),
.VAR44 (VAR30),
.VAR15 (1'b0),
.VAR20 (1'b0),
.VAR42 (1'b1),
.VAR3 (1'b0),
.VAR34 (1'b0),
.VAR25 (1'b1),
.VAR40 (... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.v | 2,162 | module MODULE1 (
VAR6,
VAR3,
VAR9 ,
VAR5,
VAR4,
VAR8 ,
VAR7
);
output VAR6;
input VAR3;
input VAR9 ;
input VAR5;
input VAR4;
input VAR8 ;
input VAR7 ;
VAR2 VAR1 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR6,
VAR3,
VAR9
);
output VAR6;
inpu... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w.v | 2,048 | module MODULE1 #(parameter VAR19(VAR30)
, parameter VAR19(VAR10)
, parameter VAR9=0
, parameter VAR20=VAR28(VAR10)
)
(input VAR5
, input VAR23
, input VAR27
, input [VAR20-1:0] VAR14
, input [VAR30-1:0] VAR11
, input VAR16
, input [VAR20-1:0] VAR6
, output logic [VAR21(VAR30, 1):0] VAR17
, input VAR8
, input [VAR20-1:0... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_arb_round_robin.v | 2,415 | module MODULE1 #(parameter VAR16(VAR14))
(input VAR11
, input VAR19
, input [VAR14-1:0] VAR3 , output logic [VAR14-1:0] VAR5 , input VAR21 );
if (VAR14 == 1)
begin: VAR18
assign VAR5 = VAR3;
end
else
begin: VAR6
logic [VAR14-1-1:0] VAR4, VAR9;
VAR2 @(posedge VAR11)
if (VAR19)
end
VAR4 <= '0; else
if (VAR21)
VAR4 <= VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3.functional.v | 1,309 | module MODULE1 (
VAR2,
VAR7,
VAR6,
VAR3
);
output VAR2;
input VAR7;
input VAR6;
input VAR3;
wire VAR4;
nor VAR1 (VAR4, VAR3, VAR7, VAR6 );
buf VAR5 (VAR2 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_4.v | 2,262 | module MODULE1 (
VAR2,
VAR10 ,
VAR9,
VAR4 ,
VAR1,
VAR7,
VAR6 ,
VAR3
);
output VAR2;
input VAR10 ;
input VAR9;
input VAR4 ;
input VAR1;
input VAR7;
input VAR6 ;
input VAR3 ;
VAR8 VAR5 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_dff.v | 5,292 | if (VAR1 && (VAR5==VAR8) && (VAR4==VAR2)) \
begin: VAR10 \
VAR3 VAR11(.*); \
end
module MODULE1 #(VAR5=-1, VAR1=1, VAR4=1)
(input VAR13
,input [VAR5-1:0] VAR12
,output [VAR5-1:0] VAR7
);
else
else
begin: VAR6
reg [VAR5-1:0] VAR9;
assign VAR7 = VAR9;
always @(posedge VAR13)
VAR9 <= VAR12;
end
endmodule | bsd-3-clause |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_nh_lcd/rtl/wb_nh_lcd.v | 14,718 | module MODULE1 #(
parameter VAR53 = 12
)(
input clk,
input rst,
output [31:0] VAR79,
input VAR132,
input VAR13,
input VAR110,
input [3:0] VAR87,
input [31:0] VAR23,
input [31:0] VAR3,
output reg [31:0] VAR10,
output reg VAR46,
output reg VAR40,
output VAR51,
output VAR22,
output VAR107,
output [3:0] VAR124,
output [31:... | mit |
secworks/vndecorrelator | src/rtl/vndecorrelator.v | 5,331 | module MODULE1(
input wire clk,
input wire VAR2,
input wire VAR5,
input wire VAR4,
output wire VAR16,
output wire VAR10
);
parameter VAR3 = 1'b0;
parameter VAR11 = 1'b1;
reg VAR13;
reg VAR7;
reg VAR8;
reg VAR15;
reg VAR12;
reg VAR1;
reg VAR17;
reg VAR9;
reg VAR14;
assign VAR16 = VAR8;
assign VAR10 = VAR12;
always @ (po... | bsd-2-clause |
AngelTerrones/Antares | Hardware/verilog/antares_reg_file.v | 1,551 | module MODULE1 (
input clk,
input [4:0] VAR6,
input [4:0] VAR7,
input [4:0] VAR5,
input [31:0] VAR3,
input VAR8,
output [31:0] VAR4,
output [31:0] VAR1
);
reg [31:0] VAR2 [1:31];
always @ ( posedge clk ) begin
if(VAR5 != 5'b0)
VAR2[VAR5] <= (VAR8) ? VAR3 : VAR2[VAR5];
end
assign VAR4 = (VAR6 == 5'b0) ? 32'b0 : VAR2[VAR... | mit |
kyzhai/NUNY | src/hardware/nine_new2.v | 6,400 | module MODULE1 (
address,
VAR39,
VAR31);
input [9:0] address;
input VAR39;
output [11:0] VAR31;
tri1 VAR39;
wire [11:0] VAR15;
wire [11:0] VAR31 = VAR15[11:0];
VAR22 VAR48 (
.VAR6 (address),
.VAR24 (VAR39),
.VAR26 (VAR15),
.VAR18 (1'b0),
.VAR40 (1'b0),
.VAR41 (1'b1),
.VAR27 (1'b0),
.VAR33 (1'b0),
.VAR11 (1'b1),
.VAR32 ... | gpl-2.0 |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_mesh_network.v | 5,736 | module MODULE1 (din, dout,
VAR24,
VAR38,
clk, VAR42);
parameter VAR41=VAR18;
parameter VAR27=VAR44;
parameter VAR47=VAR34;
parameter VAR10=VAR5;
input clk, VAR42;
input [VAR41*VAR27*VAR23(VAR21) - 1 : 0] VAR38;
input [VAR41*VAR27*VAR23(VAR32) - 1 : 0] din;
output [VAR41*VAR27*VAR15*VAR23(VAR32) - 1 : 0] dout;
output [V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai.pp.symbol.v | 1,391 | module MODULE1 (
input VAR5 ,
input VAR3 ,
input VAR1,
output VAR6 ,
input VAR4 ,
input VAR8,
input VAR2,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.functional.pp.v | 2,036 | module MODULE1 (
VAR11 ,
VAR8 ,
VAR9 ,
VAR6 ,
VAR17 ,
VAR13,
VAR5,
VAR7 ,
VAR3
);
output VAR11 ;
input VAR8 ;
input VAR9 ;
input VAR6 ;
input VAR17 ;
input VAR13;
input VAR5;
input VAR7 ;
input VAR3 ;
wire VAR10 ;
wire VAR12 ;
wire VAR1;
or VAR15 (VAR10 , VAR9, VAR8 );
and VAR16 (VAR12 , VAR10, VAR6, VAR17 );
VAR14 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111oi/sky130_fd_sc_ms__a2111oi.functional.pp.v | 2,082 | module MODULE1 (
VAR14 ,
VAR9 ,
VAR2 ,
VAR17 ,
VAR3 ,
VAR11 ,
VAR15,
VAR7,
VAR1 ,
VAR5
);
output VAR14 ;
input VAR9 ;
input VAR2 ;
input VAR17 ;
input VAR3 ;
input VAR11 ;
input VAR15;
input VAR7;
input VAR1 ;
input VAR5 ;
wire VAR12 ;
wire VAR4 ;
wire VAR6;
and VAR13 (VAR12 , VAR9, VAR2 );
nor VAR16 (VAR4 , VAR17, VAR... | apache-2.0 |
omicronns/studies-sys-rek | de1-soc-template/src/image_processor.v | 6,007 | module MODULE1 (
input [7:0] VAR32,
input [7:0] VAR8,
input [7:0] VAR3,
input VAR10,
input VAR5,
input VAR18,
input VAR12,
input VAR7,
input VAR9,
input [23:0] VAR33,
output [7:0] VAR2,
output [7:0] VAR20,
output [7:0] VAR14,
output VAR19,
output VAR17,
output VAR28,
output VAR26,
output [23:0] VAR4
);
reg [23:0] VAR22... | mit |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_camera_decoder.v | 5,620 | module MODULE1 (
clk,
reset,
VAR15,
VAR4,
VAR8,
ready,
VAR14,
VAR2,
VAR10,
valid
);
parameter VAR16 = 9;
input clk;
input reset;
input [VAR16: 0] VAR15;
input VAR4;
input VAR8;
input ready;
output reg [VAR16: 0] VAR14;
output reg VAR2;
output reg VAR10;
output reg valid;
wire VAR3;
reg [VAR16: 0] VAR12;
reg VAR13;
reg ... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_pipe_clock.v | 19,459 | module MODULE1 #
(
parameter VAR140 = "1.1", parameter VAR63 = "VAR68", parameter VAR26 = "VAR68", parameter VAR15 = 1, parameter VAR138 = 2, parameter VAR137 = 0, parameter VAR1 = 2, parameter VAR24 = 2, parameter VAR130 = 0
)
(
input VAR125,
input VAR96,
input [VAR15-1:0] VAR11,
input VAR16,
input [VAR15-1:0] VAR86,
... | lgpl-3.0 |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_usr_top.v | 6,910 | module MODULE1 #
(
parameter VAR18 = 2,
parameter VAR43 = 0,
parameter VAR12 = 10,
parameter VAR19 = 72,
parameter VAR31 = 8,
parameter VAR10 = 144,
parameter VAR25 = 0,
parameter VAR5 = 9,
parameter VAR26 = 14
)
(
input VAR6,
input VAR4,
input VAR11,
input [VAR19-1:0] VAR35,
input [VAR19-1:0] VAR7,
input [VAR5-1:0] VA... | mit |
dailypips/miaow | src/verilog/rtl/issue/issue.v | 20,191 | module MODULE1
(
VAR112, VAR121, VAR179,
VAR32, VAR164, VAR156,
VAR66, VAR194, VAR60,
VAR162, VAR153, VAR11,
VAR110, VAR72, VAR63,
VAR197, VAR117,
VAR199, VAR36, VAR7,
VAR35, VAR113, VAR3, VAR64,
VAR195, VAR4, VAR84, VAR149,
VAR130, VAR98, VAR101, VAR68,
VAR59, VAR120, VAR150, VAR161, VAR23,
VAR148, VAR126,
VAR189, VAR... | bsd-3-clause |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/L1/System_Memory.v | 5,859 | module MODULE1(
input VAR59,
input reset,
input VAR48,
input [3:0] VAR81,
input [29:0] VAR5,
input [31:0] VAR22,
output [31:0] VAR71,
output VAR8,
input VAR12,
output VAR31,
input VAR66,
input [3:0] VAR52,
input [29:0] VAR78,
input [31:0] VAR68,
output [31:0] VAR51,
output VAR44,
output VAR80,
input VAR72,
input VAR60,... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xnor2/sky130_fd_sc_hvl__xnor2.functional.pp.v | 1,836 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR6 ,
VAR11,
VAR5,
VAR7 ,
VAR12
);
output VAR1 ;
input VAR9 ;
input VAR6 ;
input VAR11;
input VAR5;
input VAR7 ;
input VAR12 ;
wire VAR8 ;
wire VAR2;
xnor VAR10 (VAR8 , VAR9, VAR6 );
VAR13 VAR4 (VAR2, VAR8, VAR11, VAR5);
buf VAR3 (VAR1 , VAR2 );
endmodule | apache-2.0 |
mda-ut/Tempest | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_epcs.v | 16,641 | module MODULE2 (
VAR16,
clk,
VAR20,
VAR38,
VAR59,
VAR80,
VAR53,
VAR56,
VAR90,
VAR12,
VAR83,
VAR48,
VAR27,
VAR35,
irq,
VAR33
)
;
output VAR90;
output VAR12;
output VAR83;
output [ 15: 0] VAR48;
output VAR27;
output VAR35;
output irq;
output VAR33;
input VAR16;
input clk;
input [ 15: 0] VAR20;
input VAR38;
input [ 2: 0] ... | mit |
alexforencich/xfcp | rtl/xfcp_interface_uart.v | 5,680 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR11,
output wire VAR9,
input wire [7:0] VAR40,
input wire VAR33,
output wire VAR34,
input wire VAR55,
input wire VAR62,
output wire [7:0] VAR49,
output wire VAR52,
input wire VAR6,
output wire VAR4,
output wire VAR65,
input wire [15:0] VAR21
);
wire [7:0] VA... | mit |
civol/HDLRuby | lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v | 13,672 | module MODULE1(
module 00003aT0( );
reg rst;
reg VAR2;
reg VAR9;
reg VAR8;
reg [7:0] VAR4;
reg [7:0] VAR6;
wire [7:0] VAR7;
reg [3:0] counter;
wire 00003a4;
reg 00003a5;
reg [7:0] 00003a6;
wire 00003a1;
wire [7:0] 00003a2;
reg 00003a3;
wire [7:0] VAR5;
wire VAR1;
wire VAR3;
assign 00003a4 = VAR1;
assign 00003a5 = VAR3;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrbp/sky130_fd_sc_ls__dfrbp.behavioral.pp.v | 2,354 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR20 ,
VAR8 ,
VAR23,
VAR9 ,
VAR19 ,
VAR22 ,
VAR11
);
output VAR1 ;
output VAR3 ;
input VAR20 ;
input VAR8 ;
input VAR23;
input VAR9 ;
input VAR19 ;
input VAR22 ;
input VAR11 ;
wire VAR4 ;
wire VAR2 ;
reg VAR18 ;
wire VAR7 ;
wire VAR5;
wire VAR13 ;
wire VAR15 ;
wire VAR6 ;
wire VAR21 ;
no... | apache-2.0 |
Blunk-electronic/M-1 | HW/ise/trc_mini/src/tap_state_machine.v | 3,353 | module MODULE1 (VAR1, VAR4, VAR15, state);
input VAR1;
input VAR4;
input VAR15;
output reg [VAR5-1:0] state;
always @(posedge VAR1 or negedge VAR15) begin
if (~VAR15)
begin
state <= #VAR6 VAR17;
end
else
begin
case (state) VAR17:
if (VAR4 == 0)
begin
state <= #VAR6 VAR12;
end
else
begin
state <= #VAR6 VAR17;
end
VAR12:... | gpl-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/sdr_lib/master_control.v | 9,766 | module MODULE1
( input VAR72, input VAR129,
input wire [6:0] VAR27, input wire [31:0] VAR14, input wire VAR49,
output VAR53, output VAR16,
output wire VAR61, output wire VAR82,
output wire VAR4, output wire VAR95,
output wire [7:0] VAR87, output wire [7:0] VAR105,
output VAR62, output VAR1,
output VAR115, output VAR103... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2b/sky130_fd_sc_ls__and2b_1.v | 2,136 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR5 ,
VAR4,
VAR7,
VAR1 ,
VAR9
);
output VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR4;
input VAR7;
input VAR1 ;
input VAR9 ;
VAR8 VAR6 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR3 ,
VAR2,
VAR5
);
output VAR3 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcin/sky130_fd_sc_ls__fahcin.symbol.v | 1,330 | module MODULE1 (
input VAR2 ,
input VAR7 ,
input VAR3 ,
output VAR9,
output VAR5
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.v | 1,907 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR3,
VAR6
);
output VAR2 ;
input VAR4 ;
input VAR3;
input VAR6;
VAR5 VAR1 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
supply1 VAR3;
supply0 VAR6;
VAR5 VAR1 (
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_mul_pipelined.v | 32,808 | function automatic [0:0] VAR45([2:0] VAR17, VAR82, VAR81);
return ((VAR17[2] & VAR82) | (VAR17[1] & VAR81)) ^ VAR17[0];
endfunction
module MODULE8 #(parameter VAR115(VAR112)
, parameter VAR77=1
, parameter VAR7 =1
)
( input VAR70
, input VAR33
, input [VAR112-1:0] VAR35
, input [VAR112-1:0] VAR87
, input VAR97 , output... | bsd-3-clause |
asicguy/gplgpu | hdl/de_temp/dex_smblt.v | 19,617 | module MODULE1
(
input VAR94,
input VAR34,
input [1:0] VAR134,
input VAR105,
input VAR42,
input VAR31,
input VAR120,
input VAR149,
input VAR98,
input VAR10,
input VAR145,
input VAR14,
input VAR92,
input VAR35,
input VAR53,
input VAR148,
input VAR77,
input VAR60,
input VAR6,
input VAR59,
input VAR41,
input VAR17,
input ... | gpl-3.0 |
amrmorsey/Digital-Design-Project | plaintext_ip.v | 2,860 | module MODULE1(
VAR1,
VAR4,
VAR3,
select
);
input [64:1] VAR1;
output [32:1] VAR4;
output [32:1] VAR3;
input select;
reg [64:1] VAR5;
assign VAR3= VAR5[32:1] ; assign VAR4= VAR5[64:33]; always@(select)
begin
if(select ==1)
begin
VAR5[1]<= VAR1[58];
VAR5[2]<= VAR1[50];
VAR5[3]<= VAR1[42];
VAR5[4]<= VAR1[34];
VAR5[5]<= V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3/sky130_fd_sc_hs__or3.functional.v | 1,690 | module MODULE1 (
VAR5,
VAR8,
VAR7 ,
VAR6 ,
VAR10 ,
VAR11
);
input VAR5;
input VAR8;
output VAR7 ;
input VAR6 ;
input VAR10 ;
input VAR11 ;
wire VAR2 ;
wire VAR12;
or VAR1 (VAR2 , VAR10, VAR6, VAR11 );
VAR3 VAR9 (VAR12, VAR2, VAR5, VAR8);
buf VAR4 (VAR7 , VAR12 );
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_convert_from_long.v | 9,216 | module MODULE1(VAR46, VAR56, VAR18, VAR27, enable, VAR4, VAR54, VAR2, VAR57);
parameter VAR52 = 0;
parameter VAR26 = 1;
parameter VAR48 = 0;
input VAR46, VAR56;
input [63:0] VAR18;
output [31:0] VAR27;
input enable, VAR4, VAR2;
output VAR54, VAR57;
reg VAR22;
wire VAR31;
wire VAR1;
reg VAR38;
wire VAR15;
wire VAR39;
re... | mit |
DSDL2016/project2 | source/synthesizer/adio_codec.v | 3,147 | module MODULE1 (
output VAR30,
output VAR4,
output reg VAR25,
input VAR10,
input [1:0] VAR23,
input VAR33,
input VAR7,
input [15:0] VAR8
);
parameter VAR16 = 18432000; parameter VAR29 = 48000; parameter VAR21 = 16; parameter VAR11 = 2;
parameter VAR32 = 48;
parameter VAR31 = 0;
reg [3:0] VAR9;
reg [8:0] VAR3;
reg [7:0]... | mit |
catompiler/fpgalibs | spi_master/spi_master.v | 12,747 | module MODULE1
(input wire VAR11,
input wire VAR6,
output wire VAR5,
output wire VAR7,
output wire VAR14,
output wire VAR4,
output wire VAR9);
localparam VAR10 = VAR13;
localparam VAR8 = VAR3(VAR10+1);
reg[VAR8-1:0] VAR12;
wire VAR2 = VAR12 == 0;
wire VAR1 = VAR12 == VAR10;
reg period;
assign VAR9 = period; | gpl-3.0 |
jeichenhofer/chuck-light | SoC/ghrd_top.v | 23,132 | module MODULE1(
inout VAR162,
output VAR71,
input VAR146,
output VAR120,
input VAR167,
inout VAR245,
inout VAR177,
output VAR205,
inout VAR185,
output VAR196,
input VAR216,
input VAR109,
input VAR3,
input VAR56,
output [12:0] VAR29,
output [1:0] VAR106,
output VAR92,
output VAR130,
output VAR108,
output VAR97,
inout [1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3.behavioral.pp.v | 1,850 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR6,
VAR5,
VAR7 ,
VAR8
);
output VAR10 ;
input VAR9 ;
input VAR6;
input VAR5;
input VAR7 ;
input VAR8 ;
wire VAR4 ;
wire VAR1;
buf VAR12 (VAR4 , VAR9 );
VAR3 VAR2 (VAR1, VAR4, VAR6, VAR5);
buf VAR11 (VAR10 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31o/sky130_fd_sc_hs__a31o.blackbox.v | 1,318 | module MODULE1 (
VAR5 ,
VAR6,
VAR3,
VAR4,
VAR7
);
output VAR5 ;
input VAR6;
input VAR3;
input VAR4;
input VAR7;
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/sine_table_11x16.v | 62,482 | module MODULE1
(input VAR1,
input [10:0] VAR3,
output reg [15:0] VAR4);
VAR2 VAR4 = 16'h0;
always @(posedge VAR1) begin
case (VAR3)
11'd0: VAR4 = 16'h0;
11'd1: VAR4 = 16'h64;
11'd2: VAR4 = 16'hc9;
11'd3: VAR4 = 16'h12d;
11'd4: VAR4 = 16'h192;
11'd5: VAR4 = 16'h1f6;
11'd6: VAR4 = 16'h25b;
11'd7: VAR4 = 16'h2bf;
11'd8: V... | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/SMAdapter.v | 14,688 | module MODULE1 # (
parameter integer VAR9 = 32,
parameter integer VAR33 = 32,
parameter integer VAR38 = 32,
parameter integer VAR13 = 1,
parameter integer VAR36 = 1 )
(
input VAR21,
input VAR8,
input [ 2:0] VAR12,
input VAR1,
input [ 3:0] VAR27,
input [31:0] VAR52,
input [31:0] VAR37,
output [ 1:0] VAR16,
output [31:0]... | lgpl-3.0 |
aj-michael/Digital-Systems | Lab6-Part1/ClockedOneShot.v | 1,189 | module MODULE2(VAR8, VAR3, VAR6, VAR4) ;
input VAR8, VAR6, VAR4;
output reg VAR3;
parameter VAR2=0, VAR9=1, VAR5=2, VAR7=3;
reg [1:0] VAR1;
always@(VAR1)
if(VAR1==VAR9) VAR3<=1;
else VAR3<=0;
always @ (posedge VAR4)
if(VAR6==1) VAR1 <= 0; else
case (VAR1)
0: if (VAR8==0) VAR1<=VAR2; else VAR1<=VAR9;
1: if (VAR8==0) VAR... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Integrador/inter_tst.v | 1,172 | module MODULE1;
reg [15:0] VAR2;
reg [15:0] VAR4;
reg enable;
reg rst;
reg clk;
wire [15:0] VAR6;
wire VAR1;
VAR5 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.enable(enable),
.rst(rst),
.clk(clk),
.VAR6(VAR6),
.VAR1(VAR1)
); | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_fifo.v | 5,787 | module MODULE1
(clk, reset, VAR40, VAR11, VAR16, VAR29, VAR43, VAR37,
VAR33, VAR44, VAR41, VAR20);
parameter VAR7 = 4;
parameter VAR18 = 8;
parameter VAR22 = VAR2;
parameter VAR1 = 0;
parameter VAR28 = VAR15;
localparam VAR19 = VAR12(VAR7);
input clk;
input reset;
input VAR40;
input VAR11;
input VAR16;
input VAR29;
inp... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController4L/src/s_axi_reg.v | 36,160 | module MODULE1 # (
parameter VAR232 = 32,
parameter VAR158 = 32,
parameter VAR134 = 32'h80000000,
parameter VAR11 = 32'h80010000,
parameter VAR145 = 36
)
(
input VAR224,
input VAR34,
input VAR37,
output VAR190,
input [VAR232-1:0] VAR239,
input [2:0] VAR204,
input VAR240,
output VAR207,
input [VAR158-1:0] VAR131,
input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b_4.v | 2,302 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR10 ,
VAR9 ,
VAR4 ,
VAR3,
VAR7,
VAR8 ,
VAR2
);
output VAR6 ;
input VAR1 ;
input VAR10 ;
input VAR9 ;
input VAR4 ;
input VAR3;
input VAR7;
input VAR8 ;
input VAR2 ;
VAR5 VAR11 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR... | apache-2.0 |
jhoward321/pacman | usb_system/synthesis/submodules/usb_system_sdram.v | 23,762 | module MODULE1 (
clk,
rd,
VAR78,
wr,
VAR3,
VAR52,
VAR70,
VAR76,
VAR64,
VAR9
)
;
output VAR52;
output VAR70;
output VAR76;
output VAR64;
output [ 61: 0] VAR9;
input clk;
input rd;
input VAR78;
input wr;
input [ 61: 0] VAR3;
wire VAR52;
wire VAR70;
wire VAR76;
reg [ 1: 0] VAR48;
reg [ 61: 0] VAR58;
reg [ 61: 0] VAR63;
wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4b/sky130_fd_sc_hd__and4b_2.v | 2,300 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR8 ,
VAR11 ,
VAR3 ,
VAR10,
VAR1,
VAR6 ,
VAR2
);
output VAR4 ;
input VAR7 ;
input VAR8 ;
input VAR11 ;
input VAR3 ;
input VAR10;
input VAR1;
input VAR6 ;
input VAR2 ;
VAR9 VAR5 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR6(VAR6),
.... | apache-2.0 |
jotego/jt12 | hdl/jt12_sh.v | 1,208 | module MODULE1 #(parameter VAR4=5, VAR7=24 )
(
input clk,
input VAR1 ,
input [VAR4-1:0] din,
output [VAR4-1:0] VAR5
);
reg [VAR7-1:0] VAR3[VAR4-1:0];
genvar VAR2;
generate
for (VAR2=0; VAR2 < VAR4; VAR2=VAR2+1) begin: VAR6
always @(posedge clk) if(VAR1) begin
VAR3[VAR2] <= {VAR3[VAR2][VAR7-2:0], din[VAR2]};
end
assign ... | gpl-3.0 |
secworks/trng | src/rtl/trng_csprng.v | 20,346 | module MODULE1(
input wire clk,
input wire VAR8,
input wire VAR41,
input wire VAR57,
input wire [7 : 0] address,
input wire [31 : 0] VAR5,
output wire [31 : 0] VAR17,
output wire VAR92,
input wire VAR19,
input VAR79,
output wire VAR70,
output wire VAR69,
input [511 : 0] VAR71,
input wire VAR10,
output wire VAR85,
outpu... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2.behavioral.v | 1,350 | module MODULE1 (
VAR2,
VAR5,
VAR4
);
output VAR2;
input VAR5;
input VAR4;
supply1 VAR8;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR1 ;
wire VAR10;
and VAR7 (VAR10, VAR5, VAR4 );
buf VAR3 (VAR2 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn.functional.pp.v | 1,890 | module MODULE1 (
VAR6 ,
VAR13 ,
VAR7,
VAR3,
VAR10,
VAR2 ,
VAR9
);
output VAR6 ;
input VAR13 ;
input VAR7;
input VAR3;
input VAR10;
input VAR2 ;
input VAR9 ;
wire VAR12 ;
wire VAR8;
VAR4 VAR11 (VAR12 , VAR13, VAR3, VAR10 );
VAR4 VAR1 (VAR8, VAR7, VAR3, VAR10 );
notif0 VAR5 (VAR6 , VAR12, VAR8);
endmodule | apache-2.0 |
jncronin/jca | cpu/soc.v | 4,687 | module MODULE1(VAR9, rst, addr, VAR4, VAR16, VAR33, VAR23, VAR15, VAR21, VAR42, VAR58, VAR35, VAR60, VAR12, VAR44, VAR32, VAR26, VAR29, VAR18);
parameter VAR49 = 7;
input VAR9;
input rst;
inout [7:0] VAR4;
output [31:0] addr;
output [VAR49:0] VAR16;
output VAR21;
output VAR33;
output VAR23;
output VAR15;
output VAR42;
... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_0/zynq_design_1_axi_bram_ctrl_0_0_stub.v | 4,125 | module MODULE1(VAR32, VAR31, VAR13,
VAR10, VAR42, VAR6, VAR43, VAR25, VAR24,
VAR40, VAR48, VAR39, VAR16, VAR37, VAR30,
VAR23, VAR29, VAR44, VAR33, VAR41, VAR35, VAR49,
VAR9, VAR50, VAR27, VAR21, VAR5, VAR28,
VAR7, VAR3, VAR12, VAR46, VAR22, VAR15, VAR34,
VAR20, VAR2, VAR4, VAR18, VAR47, VAR38, VAR17,
VAR8, VAR51, VAR14... | mit |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/rd_gray_ctr.v | 3,943 | module MODULE1( clk,
reset,
VAR4,
VAR11 );
input clk;
input reset;
input VAR4;
output [3:0] VAR11;
wire [3:0]VAR2 ;
reg [3:0]din ;
assign VAR11 = VAR2;
always@(VAR2)
begin
case (VAR2)
4'b0000: din <= 4'b0001; 4'b0001: din <= 4'b0011; 4'b0010: din <= 4'b0110; 4'b0011: din <= 4'b0010; 4'b0100: din <= 4'b1100; 4'b0101: di... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux2/sky130_fd_sc_hvl__mux2.behavioral.v | 1,612 | module MODULE1 (
VAR4 ,
VAR1,
VAR12,
VAR2
);
output VAR4 ;
input VAR1;
input VAR12;
input VAR2 ;
supply1 VAR5;
supply0 VAR11;
supply1 VAR8 ;
supply0 VAR7 ;
wire VAR6;
VAR3 VAR10 (VAR6, VAR1, VAR12, VAR2 );
buf VAR9 (VAR4 , VAR6);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.functional.pp.v | 1,404 | module MODULE1( VAR8, VAR10, VAR14, VAR13, VAR11, VAR9, VAR7 );
input VAR11, VAR13, VAR10, VAR8;
inout VAR9, VAR7;
output VAR14;
wire VAR3;
not VAR2( VAR3, VAR11 );
wire VAR6;
not VAR12( VAR6, VAR13 );
wire VAR4;
not VAR1( VAR4, VAR10 );
wire VAR15;
not VAR16( VAR15, VAR8 );
and VAR5( VAR14, VAR3, VAR6, VAR4, VAR15 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai.blackbox.v | 1,347 | module MODULE1 (
VAR4 ,
VAR2,
VAR6,
VAR1,
VAR5
);
output VAR4 ;
input VAR2;
input VAR6;
input VAR1;
input VAR5;
supply1 VAR9;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/uart_rx.v | 2,887 | module MODULE1(
input wire VAR12, input wire VAR2, output reg [7:0] VAR1, output reg VAR8 = 1'b0, input wire ack );
parameter VAR13 = 178;
reg [9:0] VAR6 = 0;
parameter VAR4 = 0, VAR10 = 1, VAR11 = 2;
reg [1:0] state = 0;
reg [7:0] VAR5;
reg [2:0] VAR3;
reg [2:0] VAR9;
reg [2:0] VAR7;
always @(posedge VAR12) begin
if (... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_dds.v | 3,688 | module MODULE1 (
clk,
VAR12,
VAR6,
VAR4,
VAR2,
VAR13,
VAR14);
input clk;
input VAR12;
input [15:0] VAR6;
input [15:0] VAR4;
input [15:0] VAR2;
input [15:0] VAR13;
output [15:0] VAR14;
reg [15:0] VAR3 = 'd0;
reg [15:0] VAR14 = 'd0;
wire [15:0] VAR11;
wire [15:0] VAR9;
always @(posedge clk) begin
VAR3 <= VAR11 + VAR9;
VA... | gpl-3.0 |
binary-logic/vj-uart | rtl/vjtag_bb.v | 5,394 | module MODULE1 (
VAR11,
VAR1,
VAR6,
VAR12,
VAR7,
VAR10,
VAR3,
VAR8,
VAR13,
VAR4,
VAR9,
VAR2,
VAR5);
input [1:0] VAR11;
input VAR1;
output [1:0] VAR6;
output VAR12;
output VAR7;
output VAR10;
output VAR3;
output VAR8;
output VAR13;
output VAR4;
output VAR9;
output VAR2;
output VAR5;
endmodule | gpl-3.0 |
KestrelComputer/gpia3 | bench/verilog/GPIA_BIT.v | 8,487 | module MODULE1();
reg VAR4;
reg VAR8;
reg [7:0] VAR3;
reg [1:0] VAR7;
reg do;
reg VAR13;
wire VAR14;
VAR5 VAR9 (
.VAR6(VAR4),
.VAR10(VAR8),
.VAR11(VAR7),
.VAR2(do),
.VAR15(VAR13),
.VAR12(VAR14)
);
always begin
VAR4 <= ~VAR4;
end
task VAR16;
begin @(negedge VAR4); @(posedge VAR4);
end
endtask
task VAR1;
begin
VAR8 <= 0;... | mpl-2.0 |
xcthulhu/periphondemand | src/library/components/uart16550/hdl/uart_rfifo.v | 11,274 | module MODULE1 (clk,
VAR20, VAR28, VAR38,
VAR14, VAR23, VAR21,
VAR45,
VAR31,
VAR39,
VAR24
);
parameter VAR32 = VAR13;
parameter VAR2 = VAR27;
parameter VAR46 = VAR6;
parameter VAR36 = VAR17;
input clk;
input VAR20;
input VAR14;
input VAR23;
input [VAR32-1:0] VAR28;
input VAR39;
input VAR24;
output [VAR32-1:0] VAR38;
ou... | lgpl-2.1 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/rank_mach.v | 11,024 | module MODULE1 #
(
parameter VAR35 = "8",
parameter VAR24 = 4,
parameter VAR43 = "VAR6",
parameter VAR11 = 40,
parameter VAR9 = 4,
parameter VAR39 = 2,
parameter VAR33 = 5,
parameter VAR10 = 30,
parameter VAR40 = 8,
parameter VAR17 = 4,
parameter VAR49 = 4,
parameter VAR51 = 20,
parameter VAR41 = 16,
parameter VAR25 = ... | mit |
makers-ie/pov-globe | src/shader.v | 1,163 | module MODULE1(input clk,
input VAR2,
input [(32*5-1):0] VAR4,
output reg [31:0] VAR1
);
reg [4:0] VAR3;
always @(posedge clk) begin
if (!VAR2)
VAR3 = 0;
VAR3 = VAR3+1;
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrbp/sky130_fd_sc_lp__sdfrbp.pp.blackbox.v | 1,515 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR9 ,
VAR6 ,
VAR11 ,
VAR7 ,
VAR10,
VAR5 ,
VAR2 ,
VAR3 ,
VAR1
);
output VAR4 ;
output VAR8 ;
input VAR9 ;
input VAR6 ;
input VAR11 ;
input VAR7 ;
input VAR10;
input VAR5 ;
input VAR2 ;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/synthesis/submodules/tracking_camera_system_jtag_uart_0.v | 24,578 | module MODULE2 (
clk,
VAR16,
VAR75,
valid
)
;
input clk;
input [ 7: 0] VAR16;
input VAR75;
input valid;
reg [31:0] VAR57; VAR35 VAR57 =
always @(posedge clk) begin
if (valid && VAR75) begin
VAR32 (VAR57);
end
end
endmodule
module MODULE4 (
clk,
VAR37,
VAR19,
VAR73,
VAR53,
VAR43,
VAR61
)
;
output VAR73;
output [ 7: 0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probe_p/sky130_fd_sc_hdll__probe_p_8.v | 2,070 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR5,
VAR1,
VAR4 ,
VAR6
);
output VAR8 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR4 ;
input VAR6 ;
VAR2 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR5;
supply0 VAR1;... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/regbank.v | 2,801 | module MODULE1(clk, VAR19, VAR16, VAR28, VAR17, VAR5, VAR12, VAR29);
input wire clk;
input wire [22:0] VAR19;
input wire [232:0] VAR16, VAR28;
output wire [232:0] VAR17, VAR5, VAR12, VAR29;
wire VAR22;
wire [3:0] VAR31, VAR20, VAR23;
wire [3:0] VAR15, VAR1, VAR2;
wire [232:0] VAR25, VAR32, VAR26;
wire [232:0] VAR4, VAR... | gpl-3.0 |
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