repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
jmt329/PitchShifter | project_top.v | 1,942 | module MODULE1();
reg rst, clk;
wire [31:0] VAR9; wire [3:0] VAR7; wire VAR8; wire VAR3; wire [31:0] VAR1; reg VAR4; reg [31:0] VAR10; reg [31:0] counter;
wire [31:0] VAR5 = 32'h00003044; wire [31:0] VAR6 = 32'h00003048; wire [31:0] VAR2 = 32'h0000304c; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor3/sky130_fd_sc_hd__xor3.symbol.v | 1,309 | module MODULE1 (
input VAR4,
input VAR1,
input VAR7,
output VAR2
);
supply1 VAR5;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
queq/just-stuff | pov/TopFixed/Create.v | 1,166 | module MODULE1 (VAR5, VAR2, VAR8, rst, VAR6, VAR3, VAR1, VAR4, clk, VAR7);
input VAR5;
input VAR2;
input clk;
input [2:0] VAR7;
input [6:0] VAR8;
input rst;
output reg VAR4;
output reg [6:0] VAR1;
output reg VAR6;
output reg VAR3;
always @(negedge clk) begin
if(rst) begin
VAR4=0;
VAR1=7'b0;
end
else begin
case (VAR7)
3... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_binari_cre.v | 19,142 | module MODULE1(
clk ,
VAR35 ,
VAR36 ,
VAR24 ,
VAR15 ,
VAR43 ,
VAR54 ,
VAR53 ,
VAR50 ,
VAR16
);
input clk ;
input VAR35 ;
input VAR36 ;
input [ 15:0 ] VAR24 ;
input [ 2:0 ] VAR15 ;
output [ 10:0 ] VAR43 ; output [ 10:0 ] VAR54 ; output [ 10:0 ] VAR53 ; output [ 10:0 ] VAR50 ; output [ 2:0 ] VAR16 ;
reg [ 10:0 ] VAR43 ;
... | gpl-3.0 |
kyzhai/NUNY | src/hardware/thesis_new.v | 6,431 | module MODULE1 (
address,
VAR18,
VAR1);
input [11:0] address;
input VAR18;
output [11:0] VAR1;
tri1 VAR18;
wire [11:0] VAR50;
wire [11:0] VAR1 = VAR50[11:0];
VAR24 VAR41 (
.VAR51 (address),
.VAR31 (VAR18),
.VAR25 (VAR50),
.VAR32 (1'b0),
.VAR42 (1'b0),
.VAR39 (1'b1),
.VAR2 (1'b0),
.VAR35 (1'b0),
.VAR27 (1'b1),
.VAR21 (1... | gpl-2.0 |
ShepardSiegel/ocpi | scripts/auguste/td7051/rtl/mkFTop_kc705.v | 2,987 | module MODULE1(VAR18,
VAR3,
VAR16,
VAR15,
VAR13,
VAR19,
VAR8,
VAR1,
VAR11,
VAR6,
VAR9,
VAR10);
input VAR18;
input VAR3;
input [7 : 0] VAR16;
input VAR15;
output VAR13;
output [7 : 0] VAR19;
output VAR8;
output [31 : 0] VAR1;
output VAR11;
output VAR6;
output VAR9;
output VAR10;
wire [31 : 0] VAR1;
wire [7 : 0] VAR19;
w... | lgpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/altera_jtag_dc_streaming.v | 8,642 | module MODULE2 (
clk,
VAR29,
VAR56,
VAR48,
VAR30
);
input clk;
input VAR29;
input VAR56;
input VAR48;
output VAR30;
parameter VAR54 = 3;
reg VAR30;
wire VAR31;
reg VAR62;
VAR61 #(.VAR23(VAR54)) VAR19 (
.clk(clk),
.VAR29(VAR29),
.din(VAR56),
.dout(VAR31)
);
always @ (posedge clk or negedge VAR29)
if (~VAR29)
VAR62 <= 1'... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111oi/sky130_fd_sc_hd__a2111oi_4.v | 2,461 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR8 ,
VAR11 ,
VAR3 ,
VAR4 ,
VAR10,
VAR9,
VAR12 ,
VAR2
);
output VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR11 ;
input VAR3 ;
input VAR4 ;
input VAR10;
input VAR9;
input VAR12 ;
input VAR2 ;
VAR6 VAR5 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR10(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3/sky130_fd_sc_ls__or3_1.v | 2,153 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3 ,
VAR7 ,
VAR10,
VAR2,
VAR6 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR10;
input VAR2;
input VAR6 ;
input VAR5 ;
VAR9 VAR8 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
unsignedzero/verilogLabs | labs/lab11/crossclock/crossclock.v | 3,374 | module MODULE1(VAR24,
VAR29,
VAR26,
VAR31,
VAR9,
rst);
parameter VAR17 = 8;
parameter VAR18 = 2;
parameter VAR8 = 1<<VAR18;
parameter [2:0] VAR32 = 3'b000;
parameter [2:0] VAR19 = 3'b001;
parameter [2:0] VAR22 = 3'b011;
parameter [2:0] VAR11 = 3'b010;
parameter [2:0] VAR28 = 3'b110;
parameter [2:0] VAR7 = 3'b111;
param... | mit |
bluespec/Flute | src_bsc_lib_RTL/BRAM2.v | 3,754 | module MODULE1(VAR17,
VAR16,
VAR14,
VAR22,
VAR11,
VAR13,
VAR2,
VAR8,
VAR20,
VAR1,
VAR10,
VAR6
);
parameter VAR12 = 0;
parameter VAR3 = 1;
parameter VAR5 = 1;
parameter VAR15 = 1;
input VAR17;
input VAR16;
input VAR14;
input [VAR3-1:0] VAR22;
input [VAR5-1:0] VAR11;
output [VAR5-1:0] VAR13;
input VAR2;
input VAR8;
input... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/SSDS_spoof_modified.v | 4,349 | module MODULE1(
clk,
VAR23,
VAR6,
VAR13,
VAR15,
VAR3,
VAR22,
VAR17,
reset
);
input clk;
input VAR23;
input VAR6;
input VAR13;
input reset;
input VAR17;
output [31:0] VAR15;
output [31:0] VAR3;
output [31:0] VAR22;
wire clk;
wire VAR23;
wire VAR6;
wire VAR13;
wire VAR17; wire reset;
wire [31:0] VAR3;
wire [31:0] VAR15;
... | gpl-3.0 |
Feuerwerk/fpgaNES | vga_pll/vga_pll_0002.v | 2,159 | module MODULE1(
input wire VAR52,
input wire rst,
output wire VAR48,
output wire VAR65
);
VAR44 #(
.VAR9("true"),
.VAR2("50.0 VAR1"),
.VAR56("VAR7"),
.VAR3(1),
.VAR45("25.175000 VAR1"),
.VAR55("0 VAR40"),
.VAR63(50),
.VAR36("0 VAR1"),
.VAR64("0 VAR40"),
.VAR29(50),
.VAR22("0 VAR1"),
.VAR47("0 VAR40"),
.VAR13(50),
.VAR3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtn/sky130_fd_sc_hs__dfrtn.behavioral.v | 2,320 | module MODULE1 (
VAR1,
VAR10 ,
VAR21 ,
VAR19 ,
VAR12 ,
VAR4
);
input VAR1;
input VAR10 ;
input VAR21 ;
output VAR19 ;
input VAR12 ;
input VAR4 ;
wire VAR3 ;
wire VAR2 ;
wire VAR16 ;
reg VAR20 ;
wire VAR9 ;
wire VAR13;
wire VAR15 ;
wire VAR7 ;
wire VAR8 ;
wire VAR5 ;
not VAR18 (VAR2 , VAR13 );
not VAR11 (VAR16, VAR15 );... | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encoder_ip_prj/encoder_ip_prj.runs/synth_1/encoder_top_X99.v | 4,664 | module MODULE1(VAR1,VAR2);
input[5:0] VAR1;
output reg[13:0] VAR2;
always @(VAR1)
begin
case(VAR1)
6'b000000: VAR2 = 14'b00000000000000;
6'b000001: VAR2 = 14'b00000110010000;
6'b000010: VAR2 = 14'b00010001110010;
6'b000011: VAR2 = 14'b00011000000010;
6'b000100: VAR2 = 14'b00011010100111;
6'b000101: VAR2 = 14'b001000001... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311oi/sky130_fd_sc_hs__a311oi_4.v | 2,323 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR10 ,
VAR8 ,
VAR3 ,
VAR6 ,
VAR4,
VAR9
);
output VAR2 ;
input VAR1 ;
input VAR10 ;
input VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR4;
input VAR9;
VAR7 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule
module MODUL... | apache-2.0 |
dingzh/piplined-MIPS-CPU | src/LAB6/Top.v | 12,348 | module MODULE1(
input VAR52,
input VAR154,
input [2:0] VAR49,
output [7:0] VAR11,
input VAR98
);
wire VAR89;
reg [26:0] VAR110 = 0;
always@ (posedge VAR52) VAR110 = VAR110 + 1;
assign VAR89 = VAR98 ? VAR52 : VAR110[26];
wire [31:0] VAR101;
assign VAR11[7] = VAR154;
assign VAR11[6] = VAR89;
wire [5:0] VAR53;
assign VAR1... | gpl-3.0 |
8l/beri | cheri/trunk/FPU/QuartusProject/floatAddWrapper.v | 1,637 | module MODULE1 (
VAR7,
VAR4,
VAR6,
VAR1,
VAR5);
input VAR7;
input [31:0] VAR4;
input [31:0] VAR6;
output [31:0] VAR1;
input VAR5;
VAR2 VAR3 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/cmm_errman_cor.v | 16,702 | module MODULE1 (
VAR4, VAR14,
VAR18,
VAR10, VAR11,
VAR6,
VAR17,
VAR3,
VAR5,
VAR16,
rst,
clk
);
output [2:0] VAR4;
output VAR14; output VAR18;
input VAR10;
input VAR11;
input VAR6;
input VAR17;
input VAR3;
input VAR5;
input VAR16;
input rst;
input clk;
parameter VAR2 = 1;
reg [2:0] VAR15 ;
reg VAR1 ;
reg VAR20;
reg VAR7... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3b/sky130_fd_sc_ls__nand3b.functional.pp.v | 1,971 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR11 ,
VAR7 ,
VAR15,
VAR9,
VAR2 ,
VAR12
);
output VAR10 ;
input VAR6 ;
input VAR11 ;
input VAR7 ;
input VAR15;
input VAR9;
input VAR2 ;
input VAR12 ;
wire VAR16 ;
wire VAR8 ;
wire VAR3;
not VAR13 (VAR16 , VAR6 );
nand VAR14 (VAR8 , VAR11, VAR16, VAR7 );
VAR5 VAR1 (VAR3, VAR8, VAR15, VAR... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Prueba4/fifo.v | 3,734 | module MODULE1 # (parameter VAR5 = 20, VAR16 = 8)(
input reset, VAR12,
input rd, wr,
input [VAR16-1:0] din,
output [VAR16-1:0] dout,
output VAR4,
output VAR22,
output reg VAR13
);
wire VAR1;
wire VAR18;
reg VAR10, VAR24;
reg [VAR16-1:0] out;
VAR14 VAR13 = 0;
reg [1:0] VAR3;
reg [1:0] VAR9;
assign VAR1 = VAR10;
assign V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_2.v | 2,631 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR5 ,
VAR2 ,
VAR13 ,
VAR1 ,
VAR3,
VAR6 ,
VAR11 ,
VAR9 ,
VAR10
);
output VAR7 ;
output VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR13 ;
input VAR1 ;
input VAR3;
input VAR6 ;
input VAR11 ;
input VAR9 ;
input VAR10 ;
VAR8 VAR12 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR13(VAR1... | apache-2.0 |
lbl-cal/StanfordNoC | router/src/rtr_channel_output.v | 7,789 | module MODULE1
(clk, reset, VAR39, VAR11, VAR35, VAR5, VAR7,
VAR14, VAR2);
parameter VAR30 = 4;
parameter VAR28 = VAR25;
parameter VAR21 = 1;
parameter VAR9 = 64;
parameter VAR38 = VAR27;
localparam VAR24 = VAR15(VAR30);
localparam VAR3 = VAR21 ? 1 : 0;
localparam VAR13
= (VAR28 == VAR17) ?
(1 + VAR24 + 1 + 1) :
(VAR28... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp.pp.blackbox.v | 1,301 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR7,
VAR6,
VAR4,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR2 ;
input VAR7;
input VAR6;
input VAR4;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s.pp.blackbox.v | 1,342 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR4,
VAR3,
VAR1 ,
VAR5
);
output VAR2 ;
input VAR6 ;
input VAR4;
input VAR3;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/ram_controller.v | 31,517 | module MODULE1 (
VAR42,
VAR67,
VAR63,
VAR93,
VAR65,
VAR71,
VAR10,
VAR78,
VAR105,
VAR55,
VAR95,
VAR76,
VAR101,
VAR97,
VAR81,
VAR35,
VAR25,
VAR72,
VAR62,
VAR11,
VAR30,
VAR79,
VAR54,
VAR13,
VAR70,
VAR74,
VAR86,
VAR89,
VAR75,
VAR56,
VAR69,
VAR6,
VAR73);
input [24:0] VAR42;
input VAR67;
input VAR63;
input VAR93;
input [31:0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4b/sky130_fd_sc_hdll__or4b_2.v | 2,307 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR2 ,
VAR8 ,
VAR4 ,
VAR9,
VAR10,
VAR1 ,
VAR11
);
output VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR9;
input VAR10;
input VAR1 ;
input VAR11 ;
VAR5 VAR7 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1),
.VA... | apache-2.0 |
AmeerAbdelhadi/Switched-Multiported-RAM | dpram_bbs.v | 5,921 | module MODULE1
wire [VAR7-1:0] VAR27; wire [VAR7-1:0] VAR22; VAR20 #( .VAR23 (VAR23 ), .VAR7 (VAR7 ), .VAR16 (VAR16 ), .VAR28 (VAR28 )) VAR5 ( .clk (clk ), .VAR8 (VAR8 ), .VAR4 (VAR4 ), .VAR18 (VAR18 ), .VAR19 (VAR19 ), .VAR15(VAR15 ), .VAR21(VAR21 ), .VAR1(VAR27), .VAR14(VAR22));
reg VAR13;
reg VAR24;
reg [VAR26(VAR23... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/buf/sky130_fd_sc_hs__buf.blackbox.v | 1,166 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR4;
supply0 VAR1;
endmodule | apache-2.0 |
fzyz999/5-stage-MIPS | control/ctldefine.v | 5,033 | module MODULE2 (input [31:0] VAR89,
output VAR22);
wire VAR45,VAR103,VAR7;
wire [5:0] VAR113;
wire [5:0] VAR132;
assign VAR113=VAR89[VAR125];
assign VAR132=VAR89[VAR107];
assign VAR45=(VAR113==VAR79);
assign VAR31=VAR45&(VAR132==VAR50);
assign VAR67=VAR45&(VAR132==VAR62);
assign VAR8=VAR45&(VAR132==VAR52);
assign VAR19... | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_bram_7vx.v | 10,483 | module MODULE1 #(
parameter VAR40 = "VAR71", parameter VAR74 = "VAR81", parameter VAR39 = "500 VAR48", parameter VAR7 = "16KB"
) (
input VAR30, input VAR70,
input [8:0] VAR91,
input [127:0] VAR17, input [15:0] VAR78, input VAR64, input VAR72,
output [127:0] VAR16, output [15:0] VAR63,
input [8:0] VAR93, input [8:0] VAR... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_video_clipper_counters.v | 8,298 | module MODULE1 (
clk,
reset,
VAR17,
VAR7,
VAR4,
VAR18,
VAR14,
VAR2
);
parameter VAR16 = 640; parameter VAR6 = 480; parameter VAR11 = 9; parameter VAR3 = 8;
parameter VAR1 = 0;
parameter VAR15 = 0;
parameter VAR13 = 0;
parameter VAR5 = 0;
input clk;
input reset;
input VAR17;
output VAR7;
output VAR4;
output VAR18;
outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o.functional.pp.v | 2,246 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR16 ,
VAR8 ,
VAR11 ,
VAR6 ,
VAR20,
VAR18,
VAR5 ,
VAR19
);
output VAR10 ;
input VAR2 ;
input VAR16 ;
input VAR8 ;
input VAR11 ;
input VAR6 ;
input VAR20;
input VAR18;
input VAR5 ;
input VAR19 ;
wire VAR3 ;
wire VAR4 ;
wire VAR13 ;
wire VAR12;
and VAR9 (VAR3 , VAR8, VAR2, VAR16 );
and VA... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_clk_cl_ddr_ddr.v | 5,287 | module MODULE1 (
VAR7, VAR15, VAR4, VAR14,
VAR6, VAR5, VAR3, VAR11, VAR9, VAR12, VAR10, VAR13,
VAR2, VAR16
);
output VAR14; output VAR4; output VAR15; output VAR7;
input VAR16 ;
input VAR2; input VAR10; input VAR13; input VAR12; input [1:0] VAR9; input VAR11; input VAR3; input VAR5; input VAR6;
VAR8 VAR17
(
.VAR4 (VAR4... | gpl-2.0 |
fpgasystems/caribou | hw/src/net/ddr3_dual_inf.v | 101,005 | module MODULE1 #
(
parameter VAR31 = 3,
parameter VAR196 = 1,
parameter VAR28 = 10,
parameter VAR313 = 1,
parameter VAR433 = 1,
parameter VAR237 = 1,
parameter VAR142 = 5,
parameter VAR296 = 6,
parameter VAR20 = 8,
parameter VAR395 = 8,
parameter VAR383 = 64,
parameter VAR242 = 8,
parameter VAR190 = 3,
parameter VAR423... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/apu/apu_div.v | 3,010 | module MODULE1
parameter VAR6 = 16
)
(
input VAR5, input VAR2, input VAR7, input VAR3, input [VAR6-1:0] VAR4, output VAR8 );
reg [VAR6-1:0] VAR1;
wire [VAR6-1:0] VAR9;
always @(posedge VAR5)
begin
if (VAR2)
VAR1 <= 0;
end
else
VAR1 <= VAR9;
end
assign VAR9 = (VAR3 || (VAR7 && (VAR1 == 0))) ? VAR4 :
(VAR7) ? VAR1 - 1'h1... | mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/routing_buffer.v | 1,866 | module MODULE1(VAR8, VAR4,
VAR6, VAR1, VAR7,
VAR3, VAR5, VAR10);
parameter VAR11 = 32;
parameter VAR9 = 0;
input VAR8, VAR4;
input [VAR11-1:0] VAR6;
input VAR1;
output reg VAR7;
output reg [VAR11-1:0] VAR3;
input VAR5;
output reg VAR10;
generate
if (VAR9)
begin
always @ (negedge VAR4 or posedge VAR8)
begin
if (~VAR4)
b... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_015bits.v | 1,917 | module MODULE2 (
clk,
VAR12, VAR14, VAR6, VAR5, VAR17, VAR9, VAR8, VAR1,
sum,
);
input clk;
input [VAR30+0-1:0] VAR12, VAR14, VAR6, VAR5, VAR17, VAR9, VAR8, VAR1;
output [VAR30 :0] sum;
reg [VAR30 :0] sum;
wire [VAR30+3-1:0] VAR21;
wire [VAR30+2-1:0] VAR32, VAR3;
wire [VAR30+1-1:0] VAR18, VAR29, VAR20, VAR10;
reg [VAR3... | mit |
camsoupa/cc3000 | cc3000fpga/component/work/cc3000fpga_MSS/cc3000fpga_MSS.v | 23,981 | module MODULE1(
VAR154,
VAR167,
VAR214,
VAR82,
VAR229,
VAR187,
VAR225,
VAR90,
VAR139,
VAR89,
VAR300,
VAR122,
VAR344,
VAR355,
VAR30,
VAR320,
VAR239,
VAR292,
VAR98,
VAR39,
VAR200,
VAR72,
VAR343,
VAR171,
VAR145
);
input VAR154;
input [31:0] VAR167;
input VAR214;
input VAR82;
input VAR229;
input VAR187;
input VAR225;
input... | mit |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_wishbone.v | 73,003 | module MODULE1
(
VAR141, VAR98, VAR18,
VAR158, VAR265, VAR145,
VAR271,
VAR40,
VAR71, VAR164, VAR281,
VAR187, VAR213, VAR230,
VAR279, VAR84, VAR294,
VAR200, VAR119,
VAR159, VAR182, VAR20, VAR232, VAR69,
VAR100, VAR58, VAR292, VAR82, VAR152,
VAR221,
VAR12, VAR47, VAR140, VAR215, VAR60, VAR4, VAR240,
VAR206, VAR284, VAR68... | gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/FIFO_pixelq_op_img_data_stream_1_V.v | 2,997 | module MODULE2 (
clk,
VAR27,
VAR15,
VAR23,
VAR16);
parameter VAR7 = 32'd8;
parameter VAR21 = 32'd1;
parameter VAR24 = 32'd2;
input clk;
input [VAR7-1:0] VAR27;
input VAR15;
input [VAR21-1:0] VAR23;
output [VAR7-1:0] VAR16;
reg[VAR7-1:0] VAR1 [0:VAR24-1];
integer VAR2;
always @ (posedge clk)
begin
if (VAR15)
begin
for (... | gpl-2.0 |
medav/conware | prototype/hw/conware.v | 1,945 | module MODULE1 #(
parameter VAR26 = 32,
parameter VAR8 = 4,
parameter VAR4 = 1
)(
clk,
VAR27,
VAR5,
VAR24,
VAR17,
VAR15,
VAR16,
VAR19,
VAR21,
VAR18,
VAR30,
VAR25
);
input clk;
input VAR27;
input [VAR26-1:0] VAR5;
input [VAR26-1:0] VAR24;
input [VAR26-1:0] VAR16;
input VAR17;
input VAR19;
output VAR15;
output [VAR26-1:0... | mit |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_gtp_pipe_rate.v | 16,188 | module MODULE1 #
(
parameter VAR47 = "VAR15", parameter VAR34 = 4'd15
)
(
input VAR51,
input VAR24,
input [ 1:0] VAR4,
input VAR43,
input VAR26,
input VAR5,
input VAR42,
input VAR29,
input VAR41,
output VAR49,
output VAR11,
output VAR14,
output [ 2:0] VAR7,
output VAR9,
output VAR45,
output VAR54,
output [ 4:0] VAR50
)... | mit |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/axi_ipif/axi_lite_ipif.v | 11,704 | module MODULE1
parameter VAR44 = 32,
parameter VAR5 = 32,
parameter [31:0] VAR12 = 32'h000001FF,
parameter VAR25 = 0,
parameter VAR10 = 0,
parameter VAR1 = 1,
parameter VAR33 = 1,
parameter [0:32*2*VAR1-1] VAR41 =
{2*VAR1
{32'h00000000}
},
parameter [0:8*VAR1-1] VAR46 =
{
VAR1{8'd1}
},
parameter VAR3 = "VAR29"
)
(
inpu... | lgpl-3.0 |
ipburbank/Raster-Laser-Projector | src/RasterLaserProjector.v | 16,272 | module MODULE1 (
VAR44,
VAR6,
VAR100,
VAR78,
VAR88,
VAR111,
VAR18,
VAR31,
VAR90,
VAR110,
VAR43,
VAR42,
VAR49,
VAR53,
VAR101,
VAR99,
VAR84,
VAR80,
VAR51,
VAR92,
VAR106,
VAR40,
VAR15,
VAR74,
VAR65,
VAR61,
VAR22,
VAR116,
VAR24,
VAR79,
VAR112,
VAR13,
VAR58,
VAR52,
VAR75,
VAR30,
VAR83,
VAR70,
VAR94,
VAR63,
VAR103,
VAR114,
V... | gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v | 3,593 | module MODULE1 (
input wire clk ,
input wire reset ,
output wire VAR8 ,
input wire VAR2 ,
output wire VAR1 ,
input wire VAR4 ,
output wire VAR13 ,
input wire VAR7 ,
output wire VAR10 ,
input wire VAR5 ,
output wire VAR6
);
localparam VAR3 = 2'b00;
localparam VAR9 = 2'b01;
localparam VAR14 = 2'b10;
localparam VAR12 = 2'... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/riffa/txr_engine_ultrascale.v | 26,113 | module MODULE3
parameter VAR141 = 1,
parameter VAR20 = 1,
parameter VAR53 = 10,
parameter VAR54 = 256)
( input VAR159,
input VAR158, input VAR48, output VAR27,
input [VAR31-1:0] VAR44,
input VAR28,
output VAR79,
output VAR130,
output [VAR86-1:0] VAR132,
output [(VAR86/32)-1:0] VAR144,
output [VAR188-1:0] VAR94,
input V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.blackbox.v | 1,252 | module MODULE1 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
supply1 VAR2;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
willianzocolau/Raiden | Datapath.v | 2,379 | module MODULE1(
VAR10,
reset,
VAR47,
VAR30,
);
input VAR10, reset;
output reg [31:0] VAR30, VAR47;
always @ (*) begin
VAR47 = VAR21;
VAR30 = VAR22;
end
wire [31:0] VAR21, VAR1, VAR9, VAR7, VAR45, VAR16, VAR50;
wire signed [31:0] VAR5, VAR12, VAR17, VAR55, VAR22;
wire signed [21:0] VAR32;
wire [4:0] VAR57, VAR31, VAR40,... | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkFlashWorker.v | 107,766 | module MODULE1(VAR253,
VAR235,
VAR287,
VAR177,
VAR188,
VAR15,
VAR243,
VAR64,
VAR128,
VAR249,
VAR172,
VAR49,
VAR375,
VAR341,
VAR199,
VAR337,
VAR153,
VAR56,
VAR259,
VAR359,
VAR158);
parameter [0 : 0] VAR384 = 1'b0;
input VAR253;
input VAR235;
inout [15 : 0] VAR287;
input [2 : 0] VAR177;
input VAR188;
input [3 : 0] VAR15;... | lgpl-3.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/vfabric_up_converter.v | 3,748 | module MODULE1(VAR6, VAR11, VAR7,
VAR14, VAR13, VAR8,
VAR12, VAR10, VAR16);
parameter VAR4 = 8;
parameter VAR17 = 32;
input VAR6, VAR11, VAR7;
input [VAR4-1:0] VAR14;
input VAR13;
output VAR8;
output [VAR17-1:0] VAR12;
input VAR10;
output VAR16;
parameter VAR19 = 2'b00;
parameter VAR15 = 2'b01;
parameter VAR18 = 2'b10;... | mit |
Darkin47/Zynq-TX-UTT | Vivado_HLS/convolution_2D/solution1/syn/verilog/doImgProc.v | 72,537 | module MODULE1 (
VAR328,
VAR375,
VAR109,
VAR346,
VAR213,
VAR304,
VAR395,
VAR307,
VAR221,
VAR39,
VAR362,
VAR116,
VAR369,
VAR8,
VAR246,
VAR148,
VAR171,
VAR151,
VAR302,
VAR231,
VAR47,
VAR131,
VAR112,
VAR71,
VAR52,
VAR54,
VAR260,
VAR230,
VAR85,
VAR117,
VAR251,
VAR3,
VAR98,
VAR324,
VAR296,
VAR394,
VAR282,
interrupt,
VAR317,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b_1.v | 2,046 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR1 ,
VAR5,
VAR7
);
output VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR5;
input VAR7;
VAR2 VAR3 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR6 ,
VAR4 ,
VAR1
);
output VAR6 ;
input VAR4 ;
input VAR1;
supply1 VAR5;
supply0 VAR7;
VAR2 VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50.behavioral.pp.v | 1,866 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR8,
VAR12,
VAR11 ,
VAR10
);
output VAR2 ;
input VAR4 ;
input VAR8;
input VAR12;
input VAR11 ;
input VAR10 ;
wire VAR3 ;
wire VAR7;
buf VAR9 (VAR3 , VAR4 );
VAR1 VAR6 (VAR7, VAR3, VAR8, VAR12);
buf VAR5 (VAR2 , VAR7 );
endmodule | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/fflop.v | 7,490 | module MODULE1
(input clk
,input reset
,input logic [VAR18-1:0] din
,input logic VAR2
,output logic VAR3
,output logic [VAR18-1:0] VAR15
,input logic VAR11
,output logic VAR13
);
logic [VAR18-1:0] VAR5;
logic VAR12;
logic VAR14;
logic VAR1;
logic VAR16;
VAR8 begin
VAR13 = VAR16;
end
logic VAR9;
VAR8 begin
VAR3 = VAR9;
... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_rf16x128d.v | 7,482 | module MODULE1(
dout, VAR12,
din, VAR16, VAR29, VAR7, VAR23, VAR24, VAR18, VAR2, VAR28,
VAR30, VAR19
);
input [127:0] din; input [15:0] VAR16; input [15:0] VAR29; input VAR7;
input VAR23; input VAR24 ; input VAR18;
input VAR2, VAR28 ;
input VAR30;
input VAR19;
output [127:0] dout;
output VAR12;
reg [127:0] dout;
reg [1... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_clock.v | 21,212 | module MODULE1 #
(
parameter VAR32 = "VAR3", parameter VAR113 = "VAR3", parameter VAR68= "VAR3", parameter VAR123 = 1, parameter VAR38 = 3, parameter VAR37 = 0, parameter VAR48 = 2, parameter VAR60 = 2, parameter VAR21 = 1, parameter VAR144 = 0
)
(
input VAR78,
input VAR17,
input [VAR123-1:0] VAR88,
input VAR143,
input... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/scripts/Shifter_DW_combinational.v | 2,980 | module MODULE3
(
input wire VAR43,
input wire [VAR9-1:0] VAR27,
input wire [VAR9-1:0] VAR20,
output reg [VAR9-1:0] VAR25
);
always @(VAR43, VAR27, VAR20)
case (VAR43)
1'b0: VAR25 <= VAR27;
1'b1: VAR25 <= VAR20;
endcase
endmodule
module MODULE4
(
input wire [VAR30-1:0] VAR8,
input wire VAR36,
output wire [VAR30-1:0] VAR... | gpl-3.0 |
aanunez/KeypadScanner | Source/KeyPadDecoder.v | 1,332 | module MODULE1(
input [3:0] VAR2,
output reg [3:0] VAR1
);
always @(VAR2) begin
case (VAR2)
4'b0000: VAR1 = 4'h1;
4'b0001: VAR1 = 4'h2;
4'b0010: VAR1 = 4'h3;
4'b0011: VAR1 = 4'hA;
4'b0100: VAR1 = 4'h4;
4'b0101: VAR1 = 4'h5;
4'b0110: VAR1 = 4'h6;
4'b0111: VAR1 = 4'hB;
4'b1000: VAR1 = 4'h7;
4'b1001: VAR1 = 4'h8;
4'b1010:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.v | 2,204 | module MODULE2 (
VAR9 ,
VAR4 ,
VAR6,
VAR7 ,
VAR5 ,
VAR2 ,
VAR8
);
output VAR9 ;
input VAR4 ;
input VAR6;
input VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR8 ;
VAR1 VAR3 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR9 ,
VAR4 ,
VAR6
);
output VA... | apache-2.0 |
Cognoscan/BoostLogic | verilog/src/transceivers/XcvrSpiMaster.v | 6,929 | module MODULE1 #(
parameter VAR14 = 4
)
(
input clk, input rst, input VAR6, input [7:0] VAR20, input write, input read, input VAR33, input VAR17, input VAR24, output wire VAR35, output wire VAR13, output reg VAR21, output wire VAR10, output wire VAR12, output wire VAR32, output wire VAR23, output wire VAR34, output wir... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/phy/circ_buffer.v | 7,193 | module MODULE1 #
(
parameter VAR16 = 100,
parameter VAR30 = 5, parameter VAR32 = 1
)
(
output[VAR32-1:0] VAR34,
input [VAR32-1:0] VAR19,
input VAR12,
input VAR18,
input rst
);
localparam VAR5 = (VAR30-1)/2;
reg VAR35;
reg [VAR5:0] VAR36;
reg [2:0] VAR21;
reg VAR33;
reg VAR20;
reg [2:0] VAR29;
always @(posedge VAR12 or ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxbp/sky130_fd_sc_lp__sdfxbp.pp.symbol.v | 1,434 | module MODULE1 (
input VAR8 ,
output VAR7 ,
output VAR10 ,
input VAR9 ,
input VAR5 ,
input VAR1 ,
input VAR4 ,
input VAR2,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp.functional.pp.v | 2,206 | module MODULE1 (
VAR11 ,
VAR20 ,
VAR9 ,
VAR17 ,
VAR13 ,
VAR16 ,
VAR18 ,
VAR14 ,
VAR6
);
input VAR11 ;
input VAR20 ;
output VAR9 ;
output VAR17 ;
input VAR13 ;
input VAR16 ;
input VAR18 ;
input VAR14 ;
input VAR6;
wire VAR2 ;
wire VAR19 ;
wire VAR15;
not VAR4 (VAR19 , VAR6 );
VAR12 VAR7 (VAR15, VAR16, VAR18, VAR14 );
VA... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/cabac_neighbour_1p_8xMB_X_TOTAL.v | 2,838 | module MODULE1(
clk ,
VAR14 ,
VAR4 ,
VAR13 ,
VAR5 ,
VAR8 ,
VAR1
);
input clk ; input VAR14 ; input [(VAR15)-1:0] VAR4 ; input VAR13 ; input [(VAR15)-1:0] VAR5 ; input [7:0] VAR8 ;
output [7:0] VAR1 ;
VAR10 #(.VAR12((VAR15)), .VAR9(8))
VAR3(
.clk ( clk ),
.VAR16 ( 1'b0 ),
.VAR7 ( ~VAR13 ),
.VAR6 ( VAR13 ? VAR5 : VAR4 ),... | gpl-3.0 |
ipcoregarfield/GEM_Project | Example_CORDIC/Verilog Design/Verilog Codes/CORDIC_Element.v | 2,697 | module MODULE1
parameter VAR6 = 8,
parameter[VAR12 - 1 : 0] VAR9 = 2**(VAR12 - 1),
parameter VAR11 = 0,
parameter VAR3 = 1)
(
input VAR10,
input VAR8,
input signed[VAR6 : 0] VAR5,
input signed[VAR6 : 0] VAR1,
input signed[VAR12 : 0] VAR4,
output reg signed[VAR6 : 0] VAR13,
output reg signed[VAR6 : 0] VAR7,
output reg s... | gpl-3.0 |
theapi/nand2tetris_fpga | hack/DE0_NANO/DE0_NANO.v | 1,742 | module MODULE1(
VAR14,
VAR10,
VAR6,
VAR13,
VAR12,
VAR11,
VAR9,
VAR15,
VAR4,
VAR7,
VAR1,
VAR8,
VAR5,
VAR2,
VAR3
);
input VAR14;
output [7:0] VAR10;
input [1:0] VAR6;
output [12:0] VAR13;
output [1:0] VAR12;
output VAR11;
output VAR9;
output VAR15;
output VAR4;
inout [15:0] VAR7;
output [1:0] VAR1;
output VAR8;
output VA... | mit |
liqimai/Assignment1-Calculator | Integer-Arithmetic/AdderAndSuuber64/pg_to_PG.v | 1,029 | module MODULE1(
input [15:0] VAR3,
input [15:0] VAR2,
output [3:0] VAR1,
output [3:0] VAR4
);
assign VAR4[0]=VAR2[3 ]|VAR3[3 ]&VAR2[2 ]|VAR3[3 ]&VAR3[2 ]&VAR2[1 ]|VAR3[3 ]&VAR3[2 ]&VAR3[1 ]&VAR2[0 ],
VAR4[1]=VAR2[7 ]|VAR3[7 ]&VAR2[6 ]|VAR3[7 ]&VAR3[6 ]&VAR2[5 ]|VAR3[7 ]&VAR3[6 ]&VAR3[5 ]&VAR2[4 ],
VAR4[2]=VAR2[11]|VAR3... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_merge_enc.v | 5,627 | module MODULE1
parameter VAR20 = 100,
parameter VAR21 = 64,
parameter VAR26 = 72,
parameter VAR6 = 4,
parameter VAR4 = 1,
parameter VAR10 = 64,
parameter VAR17 = 72,
parameter VAR12 = 8
)
(
VAR16, VAR15,
clk, rst, VAR19, VAR14, VAR2, VAR11, VAR9
);
input clk;
input rst;
input [4*VAR21-1:0] VAR19;
input [4*VAR10/8-1:0] ... | lgpl-3.0 |
neale/CS-program | 474-VLSI/UART/db/TX_PLL_altpll.v | 4,535 | module MODULE1
(
VAR5,
clk,
VAR7,
VAR4) ;
input VAR5;
output [4:0] clk;
input [1:0] VAR7;
output VAR4;
tri0 VAR5;
tri0 [1:0] VAR7;
reg VAR1;
wire [4:0] VAR2;
wire VAR6;
wire VAR3; | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b_2.v | 2,229 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR1,
VAR4,
VAR2 ,
VAR9
);
output VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR1;
input VAR4;
input VAR2 ;
input VAR9 ;
VAR10 VAR3 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE1 (... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v | 11,393 | module MODULE1(
VAR17,
VAR87,
VAR85,
VAR111,
VAR6,
VAR8,
VAR146,
VAR112,
VAR91,
VAR32,
VAR44,
VAR154,
VAR64,
VAR68,
VAR138,
VAR24,
VAR155,
VAR60,
VAR107,
VAR136,
VAR156,
VAR140,
VAR113,
VAR125,
VAR96,
VAR105,
VAR81,
VAR4,
VAR139,
VAR83,
VAR148,
VAR67,
VAR82,
VAR101,
VAR110,
VAR13,
VAR135,
VAR23,
VAR76,
VAR51,
VAR21,
VA... | gpl-3.0 |
defano/digital-design | microblaze/rtl/microblaze.v | 1,596 | module MODULE1 (clk, reset, VAR8);
input clk, reset;
output [7:0] VAR8;
wire reset;
wire [31:0] VAR16;
wire VAR19;
wire [31:0] VAR17;
wire VAR10;
wire [4:0] VAR21;
wire [14:0] VAR12;
wire [31:0] VAR15;
wire VAR22;
wire VAR24;
wire [31:0] VAR6;
wire VAR3;
wire VAR5;
wire VAR14;
wire [31:0] VAR18;
wire [3:0] VAR2;
wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/decap/sky130_fd_sc_hd__decap.pp.symbol.v | 1,200 | module MODULE1 (
input VAR2 ,
input VAR1,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
martinmiranda14/Digitales | Lab_6/new/templates.v | 2,757 | module MODULE1(
);
endmodule
module MODULE2(clk, hc, VAR14, VAR17, VAR23, VAR24);
input clk;
input [10:0] hc;
input [10:0] VAR14;
output reg[2:0]VAR17 = 3'd0; output reg[1:0]VAR23 = 2'd0; output reg VAR24;
parameter VAR22=8'b11001; parameter VAR2=7'b11001; parameter VAR9=2'd0;
parameter VAR19=2'd0;
reg [7:0]VAR7=VAR22;... | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_crosspoint.v | 6,238 | module MODULE1 #
(
parameter VAR33 = 4,
parameter VAR39 = 4,
parameter VAR12 = 8,
parameter VAR43 = (VAR12>8),
parameter VAR32 = (VAR12/8),
parameter VAR20 = 1,
parameter VAR9 = 0,
parameter VAR40 = 8,
parameter VAR15 = 0,
parameter VAR26 = 8,
parameter VAR24 = 1,
parameter VAR22 = 1
)
(
input wire clk,
input wire rst,... | mit |
kactus2/ipxactexamplelib | tut.fi/cpu.logic/memory_controller/1.0/memory_controller.v | 6,910 | module MODULE1 #(
parameter VAR4 = 16, parameter VAR33 = 8, parameter VAR2 = 16, parameter VAR20 = 256, parameter VAR28 = 128, parameter VAR11 = 8, parameter VAR30 = VAR4/VAR33, parameter VAR37 = 'h40 ) (
input VAR15, input VAR23,
input VAR7,
input [VAR2-1:0] VAR13,
input [VAR4-1:0] VAR31,
input VAR5,
output [VAR4-1:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi_1.v | 2,261 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR5 ,
VAR10 ,
VAR9,
VAR4,
VAR8 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR10 ;
input VAR9;
input VAR4;
input VAR8 ;
input VAR1 ;
VAR6 VAR7 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd.functional.pp.v | 1,200 | module MODULE1 (
VAR1,
VAR3,
VAR4 ,
VAR2
);
input VAR1;
input VAR3;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_ecc_decoder.v | 13,306 | module MODULE1 #
( parameter
VAR32 = 40,
VAR13 = 8,
VAR36 = 1,
VAR9 = 0,
VAR38 = 7,
VAR5 = 7,
VAR26 = 1
)
(
VAR15,
VAR12,
VAR39,
VAR2,
VAR14,
VAR16,
VAR17,
VAR49,
VAR20,
VAR46,
VAR27,
VAR50,
VAR41,
VAR3
);
localparam VAR37 = (VAR32 > 8) ? (VAR32 - VAR13) : (VAR32);
input VAR15;
input VAR12;
input [VAR38 - 1 : 0] VAR39;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.v | 2,162 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR9,
VAR5,
VAR2,
VAR1 ,
VAR8
);
output VAR7 ;
input VAR3 ;
input VAR9;
input VAR5;
input VAR2;
input VAR1 ;
input VAR8 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR7 ,
VAR3 ,
VAR9
);
output VAR7 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtp/sky130_fd_sc_ls__dlrtp.pp.blackbox.v | 1,399 | module MODULE1 (
VAR7 ,
VAR8,
VAR4 ,
VAR6 ,
VAR5 ,
VAR3 ,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR8;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/ece453.v | 3,285 | module MODULE1(
clk,
reset,
VAR15,
VAR17,
VAR3,
VAR10,
VAR13,
VAR9,
VAR12,
VAR14,
VAR11
);
input clk;
input reset;
input [3:0] VAR15;
input VAR17;
input VAR3;
output wire [31:0] VAR10;
input [31:0] VAR13;
input [3:0] VAR9;
input [31:0] VAR12;
output [31:0] VAR14;
output wire VAR11;
reg [31:0] VAR5;
reg [31:0] VAR7;
reg... | gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ip/block_design_m00_regslice_0/synth/block_design_m00_regslice_0.v | 10,722 | module MODULE1 (
VAR52,
VAR70,
VAR3,
VAR76,
VAR102,
VAR64,
VAR86,
VAR89,
VAR13,
VAR36,
VAR28,
VAR20,
VAR85,
VAR23,
VAR56,
VAR68,
VAR81,
VAR65,
VAR72,
VAR95,
VAR84,
VAR15,
VAR78,
VAR94,
VAR6,
VAR44,
VAR11,
VAR25,
VAR31,
VAR17,
VAR45,
VAR9,
VAR27,
VAR92,
VAR112,
VAR79,
VAR75,
VAR63,
VAR46,
VAR88
);
input wire VAR52;
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi_4.v | 2,499 | module MODULE2 (
VAR5 ,
VAR12 ,
VAR2 ,
VAR4 ,
VAR3 ,
VAR7 ,
VAR9,
VAR10,
VAR1 ,
VAR8
);
output VAR5 ;
input VAR12 ;
input VAR2 ;
input VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR9;
input VAR10;
input VAR1 ;
input VAR8 ;
VAR6 VAR11 (
.VAR5(VAR5),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VA... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/arbiter/arbiter_bytebus.v | 35,730 | module MODULE1
(
VAR41,
VAR14,
VAR1,
VAR124,
VAR29,
VAR16,
VAR110,
VAR75,
VAR83,
VAR27,
VAR127,
VAR39,
VAR24,
VAR45,
VAR48,
VAR36,
VAR47,
VAR115,
VAR74,
VAR35,
VAR82,
VAR17,
VAR81,
VAR120,
VAR61,
VAR44,
VAR118,
VAR59,
VAR49,
VAR62,
VAR11,
VAR64,
VAR56,
VAR46,
VAR77,
VAR13,
VAR97,
VAR3,
VAR122,
VAR53,
VAR31,
VAR10,
VAR4... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtn/sky130_fd_sc_hs__dlxtn.behavioral.v | 1,893 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR10,
VAR9 ,
VAR12
);
output VAR6 ;
input VAR2 ;
input VAR10;
input VAR9 ;
input VAR12 ;
wire VAR1 VAR8 ;
wire VAR1 VAR13;
wire VAR1 VAR3 ;
reg VAR7 ;
wire VAR14 ;
wire VAR4 ;
not VAR15 (VAR14 , VAR13 );
VAR11 VAR16 (VAR8 , VAR3, VAR14, VAR7, VAR9, VAR12);
buf VAR5 (VAR6 , VAR8 );
assign... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_auto_pc_0/synth/ip_design_auto_pc_0.v | 14,657 | module MODULE1 (
VAR39,
VAR36,
VAR37,
VAR52,
VAR71,
VAR45,
VAR10,
VAR58,
VAR93,
VAR50,
VAR22,
VAR89,
VAR102,
VAR14,
VAR23,
VAR64,
VAR44,
VAR27,
VAR73,
VAR72,
VAR46,
VAR42,
VAR25,
VAR2,
VAR82,
VAR85,
VAR99,
VAR62,
VAR111,
VAR6,
VAR104,
VAR91,
VAR97,
VAR34,
VAR20,
VAR16,
VAR38,
VAR31,
VAR94,
VAR28,
VAR84,
VAR3,
VAR49,
VA... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/synth/pr_region_alternate_mm_bridge_0.v | 4,532 | module MODULE1 #(
parameter VAR10 = 32,
parameter VAR27 = 8,
parameter VAR19 = 10,
parameter VAR9 = 1,
parameter VAR8 = 1,
parameter VAR7 = 1
) (
input wire clk, input wire VAR11, input wire [VAR10-1:0] VAR12, input wire VAR4, output wire [VAR9-1:0] VAR6, output wire [VAR10-1:0] VAR30, output wire [VAR19-1:0] VAR5, out... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb_1.v | 2,058 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR5,
VAR6,
VAR1 ,
VAR2
);
output VAR8 ;
output VAR4 ;
input VAR5;
input VAR6;
input VAR1 ;
input VAR2 ;
VAR3 VAR7 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8,
VAR4
);
output VAR8;
output VAR4;
supply1 VAR5;
supply0 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp.functional.pp.v | 2,233 | module MODULE1 (
VAR12 ,
VAR11 ,
VAR15 ,
VAR8 ,
VAR20 ,
VAR16,
VAR1 ,
VAR14 ,
VAR13 ,
VAR10
);
output VAR12 ;
input VAR11 ;
input VAR15 ;
input VAR8 ;
input VAR20 ;
input VAR16;
input VAR1 ;
input VAR14 ;
input VAR13 ;
input VAR10 ;
wire VAR7 ;
wire VAR5 ;
wire VAR2;
not VAR17 (VAR5 , VAR16 );
VAR19 VAR4 (VAR2, VAR15, ... | apache-2.0 |
gtaylormb/fpga_nes | hw/src/nes_top.v | 8,601 | module MODULE1
(
input wire VAR93, input wire VAR102, input wire VAR86, input wire VAR45, input wire [3:0] VAR129, input wire VAR7, input wire VAR84, output wire VAR99, output wire VAR137, output wire VAR74, output wire [2:0] VAR134, output wire [2:0] VAR113, output wire [1:0] VAR51, output wire VAR46, output wire VAR9... | bsd-2-clause |
benreynwar/fpga-sdrlib | verilog/flow/qa_buffer_AA_burst.v | 2,191 | module MODULE1
parameter VAR8 = 32
)
(
input wire clk,
input wire reset,
input wire [VAR8-1:0] VAR14,
input wire VAR3,
output reg [VAR8-1:0] VAR2,
output reg VAR6
);
wire VAR12;
assign VAR12 = ~reset;
reg VAR21;
wire VAR7;
wire [VAR8-1:0] VAR19;
wire VAR1;
wire VAR9;
reg [VAR15-1:0] VAR18;
VAR11 #(VAR8, VAR10, VAR13)
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3/sky130_fd_sc_hdll__nand3_2.v | 2,191 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR7 ,
VAR6 ,
VAR9,
VAR2,
VAR1 ,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR7 ;
input VAR6 ;
input VAR9;
input VAR2;
input VAR1 ;
input VAR4 ;
VAR10 VAR5 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE2 (... | apache-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/sd_data_phy.v | 9,946 | module MODULE1(
input VAR48,
input rst,
output reg VAR65,
output reg[3:0] VAR18,
input [3:0] VAR12,
output [1:0] VAR44,
input [7:0] VAR55,
output reg [7:0] VAR34,
output reg VAR16,
output reg VAR30,
input [3:4] VAR15,
input [3:4] VAR66,
input [1:0] VAR2,
input VAR70
);
reg [5:0] VAR10;
reg [5:0] VAR32;
reg VAR22;
reg [... | gpl-2.0 |
xcthulhu/periphondemand | src/library/components/uart16550/hdl/uart_transmitter.v | 12,545 | module MODULE1 (clk, VAR9, VAR20, VAR42, VAR7, enable, VAR19, VAR33, VAR37, VAR3, VAR18);
input clk;
input VAR9;
input [7:0] VAR20;
input VAR42;
input [7:0] VAR7;
input enable;
input VAR3;
input VAR18; output VAR19;
output [2:0] VAR33;
output [VAR17-1:0] VAR37;
reg [2:0] VAR33;
reg [4:0] counter;
reg [2:0] VAR35; reg [... | lgpl-2.1 |
qeedquan/fpga | de2-115/uart_echo/3_uart_rx.v | 1,944 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR11,
input wire VAR14,
output reg VAR1,
output wire [7:0] dout
);
parameter VAR13 = 8;
parameter VAR8 = 16;
localparam VAR3 = 0;
localparam VAR7 = 1;
localparam VAR10 = 2;
localparam VAR12 = 3;
reg [1:0] VAR16, VAR15;
reg [3:0] VAR4, VAR6;
reg [3:0] VAR2, ... | mit |
agnicol88/Gaussian_Num_Gen | Vivado/gng/gng.srcs/sources_1/new/urn_gen.v | 1,595 | module MODULE1(
input clk,
input rst,
output [63:0] VAR9
);
reg [63:0] VAR2 = 64'd1234;
reg [63:0] VAR8 = 64'd5678;
reg [63:0] VAR4 = 64'd9012;
reg [63:0] VAR5 = 64'd0;
wire [63:0] b1,VAR10,VAR6;
wire [63:0] VAR7,VAR3,VAR1;
assign VAR9 = VAR5;
assign b1 = (((VAR2 << 13) ^ VAR2) >> 19);
assign VAR7 = (((VAR2 & 64'hfffff... | gpl-3.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/usb_system_cpu_mult_cell.v | 6,429 | module MODULE1 (
VAR2,
VAR23,
clk,
VAR48,
VAR16
)
;
output [ 31: 0] VAR16;
input [ 31: 0] VAR2;
input [ 31: 0] VAR23;
input clk;
input VAR48;
wire [ 31: 0] VAR16;
wire [ 31: 0] VAR25;
wire [ 15: 0] VAR29;
wire VAR35;
assign VAR35 = ~VAR48;
VAR43 VAR8
(
.VAR56 (VAR35),
.VAR15 (clk),
.VAR14 (VAR2[15 : 0]),
.VAR47 (VAR23[... | apache-2.0 |
linuxbest/lzs | pcores/comp_unit_v1_00_a/hdl/verilog/codeout.v | 2,895 | module MODULE1 (
VAR15, VAR12, VAR6, VAR23,
VAR2, VAR5, VAR1, VAR25, VAR16,
VAR17, VAR11, VAR20, VAR21,
VAR3
);
input VAR2,
VAR5;
input [23:0] VAR1;
input [15:0] VAR25, VAR16;
input VAR17, VAR11;
input VAR20, VAR21;
input VAR3;
output [63:0] VAR15;
output VAR12;
output VAR6;
output VAR23;
reg [15:0] VAR13;
reg VAR24, V... | gpl-2.0 |
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