repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221a/sky130_fd_sc_ls__o221a.functional.v | 1,566 | module MODULE1 (
VAR3 ,
VAR2,
VAR1,
VAR10,
VAR12,
VAR9
);
output VAR3 ;
input VAR2;
input VAR1;
input VAR10;
input VAR12;
input VAR9;
wire VAR5 ;
wire VAR11 ;
wire VAR8;
or VAR4 (VAR5 , VAR12, VAR10 );
or VAR6 (VAR11 , VAR1, VAR2 );
and VAR13 (VAR8, VAR5, VAR11, VAR9);
buf VAR7 (VAR3 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap.symbol.v | 1,175 | module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_xfer_status.v | 5,067 | module MODULE1 (
VAR6,
VAR10,
VAR21,
VAR19,
VAR4,
VAR17);
parameter VAR8 = 8;
localparam VAR20 = VAR8 - 1;
input VAR6;
input VAR10;
output [VAR20:0] VAR21;
input VAR19;
input VAR4;
input [VAR20:0] VAR17;
reg VAR15 = 'd0;
reg VAR3 = 'd0;
reg VAR14 = 'd0;
reg [ 5:0] VAR16 = 'd0;
reg VAR2 = 'd0;
reg [VAR20:0] VAR9 = 'd0;
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.v | 2,648 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR4,
VAR1 ,
VAR6 ,
VAR5 ,
VAR7 ,
VAR2
);
output VAR8 ;
input VAR9 ;
input VAR4;
input VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
VAR3 VAR10 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai.pp.symbol.v | 1,380 | module MODULE1 (
input VAR5 ,
input VAR4 ,
input VAR8 ,
input VAR1 ,
output VAR2 ,
input VAR6 ,
input VAR7,
input VAR9,
input VAR3
);
endmodule | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v2_0_ui_top.v | 14,966 | module MODULE1 #
(
parameter VAR49 = 100,
parameter VAR46 = 256,
parameter VAR59 = 32,
parameter VAR22 = 3,
parameter VAR1 = 12,
parameter VAR61 = 5,
parameter VAR50 = 5,
parameter VAR24 = "VAR53",
parameter VAR72 = "VAR53",
parameter VAR6 = "VAR87",
parameter VAR79 = 2,
parameter VAR82 = 4,
parameter VAR17 = "VAR42", ... | bsd-2-clause |
davidkoltak/tawas-core | ip/tawas/rtl/tawas_regfile.v | 8,786 | module MODULE1
(
input clk,
input rst,
input VAR13,
input [4:0] VAR33,
output reg [31:0] VAR17,
output reg [31:0] VAR60,
output reg [31:0] VAR7,
output reg [31:0] VAR5,
output reg [31:0] VAR54,
output reg [31:0] VAR58,
output reg [31:0] VAR28,
output reg [31:0] VAR26,
output reg [7:0] VAR49,
input [4:0] VAR39,
input VA... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/bram_512x33M.v | 3,454 | module MODULE1 (
address,
VAR6,
VAR2,
clk,
VAR19,
reset,
write,
VAR23,
VAR25
)
;
parameter VAR34 = 33554432;
parameter VAR7 = 33554432;
parameter VAR20 = 25;
output [512: 0] VAR25;
input [ 24: 0] address;
input [ 63: 0] VAR6;
input VAR2;
input clk;
input VAR19;
input reset;
input write;
input [511: 0] VAR23;
reg [511: ... | mit |
CospanDesign/vivado-ip-cores | ip/axi_on_screen_display/axi_lite_slave.v | 6,511 | module MODULE1 #(
parameter VAR13 = 32,
parameter VAR24 = 32,
parameter VAR31 = (VAR24 / 8)
)(
input clk,
input rst,
input VAR5,
input [VAR13 - 1: 0] VAR23,
output reg VAR1,
input VAR17,
output reg VAR29,
input [VAR31 - 1:0] VAR25,
input [VAR24 - 1: 0] VAR35,
output reg VAR21,
input VAR8,
output reg [1:0] VAR7,
input V... | mit |
anderson1008/NOCulator | hring/hw/bless_mc/dstMgmt.v | 2,312 | module MODULE1(
VAR13,
VAR14,
VAR17
);
input [VAR9-1:0] VAR13;
input [VAR3-1:0] VAR14;
output [VAR3-1:0] VAR17;
parameter VAR2 = 0;
wire [VAR3-1:0] VAR1;
wire VAR5;
wire [VAR9-1:0] VAR4;
wire [VAR9-1:0] VAR8;
assign VAR4[0] = 1'b0;
assign VAR8[0] = 1'b1;
genvar VAR7;
generate
for (VAR7=0; VAR7<VAR9-1; VAR7=VAR7+1) begi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp.functional.v | 1,921 | module MODULE1 (
VAR12 ,
VAR13 ,
VAR14 ,
VAR15 ,
VAR10,
VAR2 ,
VAR11
);
input VAR12 ;
input VAR13 ;
output VAR14 ;
output VAR15 ;
input VAR10;
input VAR2 ;
input VAR11 ;
wire VAR5;
wire VAR3;
not VAR7 (VAR5 , VAR10 );
VAR4 VAR8 VAR9 (VAR3 , VAR2, VAR11, VAR5, VAR12, VAR13);
buf VAR6 (VAR14 , VAR3 );
not VAR1 (VAR15 , V... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/src/v/bsg_wormhole_to_cache_dma_fanout.v | 10,724 | module MODULE1
import VAR59::*;
import VAR7::*;
, parameter VAR63(VAR45) , parameter VAR63(VAR96)
, parameter VAR63(VAR24)
, parameter VAR63(VAR42)
, parameter VAR63(VAR23)
, parameter VAR63(VAR84)
, parameter VAR120=VAR90(VAR36)
, parameter VAR53=VAR90(VAR96)
, parameter VAR95=VAR79(VAR24)
, parameter VAR18=VAR4(VAR24... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ebufn/sky130_fd_sc_hd__ebufn_2.v | 2,148 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR2,
VAR7,
VAR4,
VAR1 ,
VAR6
);
output VAR9 ;
input VAR3 ;
input VAR2;
input VAR7;
input VAR4;
input VAR1 ;
input VAR6 ;
VAR8 VAR5 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR9 ,
VAR3 ,
VAR2
);
output VAR9 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a.functional.v | 1,511 | module MODULE1 (
VAR7 ,
VAR9,
VAR11,
VAR3,
VAR5
);
output VAR7 ;
input VAR9;
input VAR11;
input VAR3;
input VAR5;
wire VAR2 ;
wire VAR6 ;
wire VAR12;
or VAR1 (VAR2 , VAR11, VAR9 );
or VAR8 (VAR6 , VAR5, VAR3 );
and VAR10 (VAR12, VAR2, VAR6);
buf VAR4 (VAR7 , VAR12 );
endmodule | apache-2.0 |
ZipCPU/wbuart32 | rtl/txuartlite.v | 14,190 | module MODULE1 #(
parameter [4:0] VAR2 = 5'd24,
localparam VAR9 = VAR2,
parameter [(VAR9-1):0] VAR21 = 8 ) (
input wire VAR5,
input wire VAR17,
input wire [7:0] VAR24,
output reg VAR10,
output wire VAR23
);
localparam [3:0] VAR19 = 4'h0,
VAR3 = 4'h8,
VAR22 = 4'hf;
reg [(VAR9-1):0] VAR4;
reg [3:0] state;
reg [7:0] VAR1;... | gpl-3.0 |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/synth/design_1_xbar_1.v | 24,267 | module MODULE1 (
VAR118,
VAR104,
VAR75,
VAR126,
VAR42,
VAR110,
VAR115,
VAR93,
VAR36,
VAR133,
VAR7,
VAR64,
VAR87,
VAR98,
VAR26,
VAR4,
VAR46,
VAR112,
VAR86,
VAR56,
VAR129,
VAR50,
VAR79,
VAR90,
VAR80,
VAR128,
VAR47,
VAR17,
VAR59,
VAR41,
VAR57,
VAR77,
VAR20,
VAR29,
VAR125,
VAR116,
VAR30,
VAR107,
VAR3,
VAR45,
VAR108,
VAR76,... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/2d_transfer.v | 5,165 | module MODULE1 (
input VAR2,
input VAR1,
input VAR6,
output reg VAR13,
input [31:VAR30] VAR5,
input [31:VAR4] VAR3,
input [VAR28-1:0] VAR25,
input [VAR28-1:0] VAR21,
input [VAR28-1:0] VAR20,
input [VAR28-1:0] VAR8,
input VAR26,
output reg VAR19,
output reg VAR15,
input VAR11,
output [31:VAR30] VAR17,
output [31:VAR4] V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2b/sky130_fd_sc_lp__or2b.behavioral.pp.v | 1,924 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR2 ,
VAR6,
VAR15,
VAR4 ,
VAR10
);
output VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR6;
input VAR15;
input VAR4 ;
input VAR10 ;
wire VAR7 ;
wire VAR3 ;
wire VAR12;
not VAR9 (VAR7 , VAR2 );
or VAR14 (VAR3 , VAR7, VAR1 );
VAR11 VAR13 (VAR12, VAR3, VAR6, VAR15);
buf VAR8 (VAR5 , VAR12 );
end... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s.pp.symbol.v | 1,355 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR3 ,
input VAR2,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a.behavioral.v | 1,542 | module MODULE1 (
VAR4 ,
VAR12,
VAR14,
VAR11,
VAR3
);
output VAR4 ;
input VAR12;
input VAR14;
input VAR11;
input VAR3;
supply1 VAR5;
supply0 VAR13;
supply1 VAR10 ;
supply0 VAR9 ;
wire VAR7 ;
wire VAR1;
or VAR8 (VAR7 , VAR14, VAR12 );
and VAR6 (VAR1, VAR7, VAR11, VAR3);
buf VAR2 (VAR4 , VAR1 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_1c_v1_00_a/hdl/verilog/cf_pnmon.v | 10,217 | module MODULE1 (
VAR17,
VAR5,
VAR22,
VAR12,
VAR3);
input VAR17;
input [15:0] VAR5;
output VAR22;
output VAR12;
input VAR3;
reg VAR10 = 'd0;
reg VAR7 = 'd0;
reg VAR18 = 'd0;
reg VAR13 = 'd0;
reg [15:0] VAR23 = 'd0;
reg [31:0] VAR8 = 'd0;
reg VAR14 = 'd0;
reg VAR21 = 'd0;
reg [ 6:0] VAR11 = 'd0;
reg VAR22 = 'd0;
reg [ 4:... | mit |
zhangly/azpr_cpu | rtl/cpu/rtl/ctrl.v | 7,960 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR38] VAR29, output reg [VAR51] VAR15, output reg [VAR35] VAR5,
input wire [VAR32-1:0] irq, output reg VAR25,
input wire [VAR55] VAR17,
input wire [VAR55] VAR16, input wire VAR8, input wire VAR13, input wire [VAR11] VAR50, input wire [VAR38] VAR48, input w... | mit |
monotone-RK/FACE | MCSoC-15/4-way_2-parallel/src/lcdcon.v | 2,333 | module MODULE1 #(parameter VAR10 = 8)
(input wire VAR15,
input wire VAR13,
input wire [VAR10*4-1:0] VAR6,
input wire VAR5,
output reg VAR18,
output reg VAR9);
function [7:0] mux;
input [7:0] VAR17;
input [7:0] VAR12;
input sel;
begin
case (sel)
1'b0: mux = VAR17;
1'b1: mux = VAR12;
endcase
end
endfunction
reg [(VAR10+1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/decap/sky130_fd_sc_ms__decap.behavioral.v | 1,135 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
AngelTerrones/MUSB | Hardware/ram/ram.v | 1,977 | module MODULE1#(
parameter VAR6 = 8, parameter VAR4 = 8 )(
input clk,
input VAR9,
input [(VAR4-1):0] VAR5,
input [(VAR4-1):0] VAR8,
input [(VAR6-1):0] VAR1,
output [(VAR6-1):0] VAR10
);
localparam VAR7 = 1 << VAR4;
reg [(VAR6-1):0] VAR2 [0:(VAR7-1)];
reg [(VAR6-1):0] VAR3;
assign VAR10 = VAR3;
always @(posedge clk) beg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxbp/sky130_fd_sc_ms__sedfxbp.functional.pp.v | 2,257 | module MODULE1 (
VAR14 ,
VAR1 ,
VAR6 ,
VAR13 ,
VAR12 ,
VAR5 ,
VAR2 ,
VAR20,
VAR9,
VAR15 ,
VAR18
);
output VAR14 ;
output VAR1 ;
input VAR6 ;
input VAR13 ;
input VAR12 ;
input VAR5 ;
input VAR2 ;
input VAR20;
input VAR9;
input VAR15 ;
input VAR18 ;
wire VAR19 ;
wire VAR22;
wire VAR8 ;
VAR3 VAR10 (VAR22, VAR8, VAR5, VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3b/sky130_fd_sc_ms__and3b.behavioral.v | 1,477 | module MODULE1 (
VAR4 ,
VAR6,
VAR8 ,
VAR1
);
output VAR4 ;
input VAR6;
input VAR8 ;
input VAR1 ;
supply1 VAR2;
supply0 VAR3;
supply1 VAR13 ;
supply0 VAR5 ;
wire VAR12 ;
wire VAR11;
not VAR9 (VAR12 , VAR6 );
and VAR10 (VAR11, VAR1, VAR12, VAR8 );
buf VAR7 (VAR4 , VAR11 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_decoder.v | 12,545 | module MODULE1 #
( parameter
VAR46 = 40,
VAR26 = 8,
VAR1 = 1,
VAR31 = 0,
VAR38 = 7,
VAR19 = 7,
VAR13 = 1
)
(
VAR44,
VAR11,
VAR25,
VAR36,
VAR45,
VAR10,
VAR5,
VAR32,
VAR16,
VAR6,
VAR42,
VAR12,
VAR39
);
localparam VAR21 = (VAR46 > 8) ? (VAR46 - VAR26) : (VAR46);
input VAR44;
input VAR11;
input [VAR38 - 1 : 0] VAR25;
input... | lgpl-3.0 |
alexforencich/xfcp | example/VCU108/fpga/rtl/fpga_core.v | 18,352 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR18,
input wire VAR248,
input wire VAR96,
input wire VAR69,
input wire VAR27,
input wire [3:0] VAR232,
output wire [7:0] VAR97,
input wire VAR90,
output wire VAR219,
output wire VAR38,
input wire VAR26,
output wire VAR228,
output wire VAR16,
input wire VAR52... | mit |
itpcc/FPGA-IA-Journy-game | verilog/vgagame.v | 9,097 |
input clk;
output VAR19, VAR62, VAR150, VAR99, VAR16;
input VAR77, VAR146,VAR85,VAR116;
input VAR143;
input reset;
wire VAR134;
wire [9:0] VAR26;
wire [8:0] VAR89;
reg VAR153=0; wire VAR49;
wire VAR108;
wire VAR35;
wire VAR65;
wire VAR28;
wire VAR79;
wire VAR14;
wire VAR37;
wire VAR113;
wire VAR91;
wire VAR136;
VAR13... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ha/sky130_fd_sc_hs__ha.behavioral.v | 2,092 | module MODULE1 (
VAR4,
VAR3 ,
VAR7 ,
VAR6 ,
VAR1,
VAR15
);
output VAR4;
output VAR3 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR15;
wire VAR8 ;
wire VAR16;
wire VAR14 ;
wire VAR17 ;
and VAR2 (VAR8 , VAR7, VAR6 );
VAR12 VAR5 (VAR16, VAR8, VAR1, VAR15);
buf VAR13 (VAR4 , VAR16 );
xor VAR9 (VAR14 , VAR6, VAR7 );
VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fa/sky130_fd_sc_hd__fa.symbol.v | 1,291 | module MODULE1 (
input VAR5 ,
input VAR7 ,
input VAR4 ,
output VAR2,
output VAR3
);
supply1 VAR8;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_asynch_rst_ff.v | 2,985 | module MODULE1 (
VAR2 ,
clk ,
reset ,
VAR1
);
input VAR2, clk, reset ;
output VAR1;
reg VAR1;
always @ ( posedge clk or posedge reset) begin
if (reset) begin
VAR1 <= 1'b1;
end else begin
VAR1 <= VAR2;
end
end
endmodule | mit |
asicguy/gplgpu | hdl/altera_project/de_pll/de_PLL.v | 14,001 | module MODULE1 (
VAR3,
VAR38,
VAR60);
input VAR3;
input VAR38;
output VAR60;
wire [5:0] VAR1;
wire [0:0] VAR18 = 1'h0;
wire [0:0] VAR55 = VAR1[0:0];
wire VAR60 = VAR55;
wire VAR50 = VAR38;
wire [1:0] VAR77 = {VAR18, VAR50};
VAR41 VAR74 (
.VAR23 (VAR77),
.VAR3 (VAR3),
.clk (VAR1),
.VAR46 (),
.VAR35 (),
.VAR57 ({6{1'b1}}... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_mem_1r1w.v | 6,409 | if (VAR19 == VAR8 && VAR20 == VAR28) \
begin: VAR3 \
wire [VAR19-1:0] VAR27 = (VAR30 << VAR9); \
wire [VAR19-1:0] VAR29 = (VAR1 << VAR13); \
\
VAR22 VAR26 \
( .VAR12(VAR16) \
,.VAR7(VAR14) \
,.VAR24(VAR27) \
,.VAR17 (VAR29) \
,.VAR31(VAR11) \
); \
end
module MODULE1
, parameter VAR10(VAR19)
, parameter VAR18=0
, parame... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_div_frac_dp.v | 12,658 | module MODULE1 (
VAR58,
VAR20,
VAR88,
VAR30,
VAR69,
VAR51,
VAR24,
VAR13,
VAR26,
VAR74,
VAR31,
VAR17,
VAR39,
VAR71,
VAR12,
VAR83,
VAR10,
VAR66,
VAR16,
VAR28,
VAR94,
VAR78,
VAR56,
VAR90,
VAR23,
VAR42,
VAR43,
VAR5,
VAR4,
VAR45,
VAR59,
VAR14,
VAR81,
VAR85,
VAR37,
VAR62,
VAR57,
VAR91,
VAR67,
VAR77,
VAR29,
VAR61,
VAR1,
VAR49... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/qpsk/Raised_Cosine_Transmit_Filter.v | 1,933 | module MODULE1
(
clk,
reset,
VAR10,
VAR1,
VAR13,
VAR7,
VAR6
);
input clk;
input reset;
input VAR10;
input signed [15:0] VAR1; input signed [15:0] VAR13; output signed [15:0] VAR7; output signed [15:0] VAR6;
wire signed [15:0] VAR5; wire signed [15:0] VAR2;
VAR12 VAR9 (.clk(clk),
.VAR10(VAR10),
.reset(reset),
.VAR8(VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211oi/sky130_fd_sc_hs__a211oi.pp.blackbox.v | 1,344 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR4 ,
VAR6 ,
VAR3 ,
VAR7,
VAR2
);
output VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR7;
input VAR2;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/LOAGDA_St_N16_M4_P8.v | 3,158 | module MODULE1(
input [15:0] VAR98,
input [15:0] VAR72,
output [16:0] VAR64
);
wire [4:0] VAR17, VAR38, VAR106, VAR87;
wire VAR75,VAR25;
wire VAR101,VAR50,VAR113,VAR114,VAR73,VAR14,VAR47,VAR103;
wire VAR97,VAR99,VAR108,VAR82,VAR81;
wire VAR54, VAR18;
wire VAR28;
and VAR7(VAR114,VAR98[3],VAR72[3]);
and VAR19(VAR113,VAR9... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai.functional.pp.v | 2,174 | module MODULE1 (
VAR9 ,
VAR12 ,
VAR5 ,
VAR1,
VAR11,
VAR18,
VAR10 ,
VAR13
);
output VAR9 ;
input VAR12 ;
input VAR5 ;
input VAR1;
input VAR11;
input VAR18;
input VAR10 ;
input VAR13 ;
wire VAR8 ;
wire VAR15 ;
wire VAR4 ;
wire VAR3;
not VAR7 (VAR8 , VAR1 );
or VAR6 (VAR15 , VAR5, VAR12 );
nand VAR14 (VAR4 , VAR8, VAR15 )... | apache-2.0 |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_wbm_write.v | 2,901 | module MODULE1 (VAR1, VAR8,
VAR17, VAR6, VAR9, VAR13, VAR2, VAR10, VAR5, VAR15, VAR3, VAR4, VAR11,
VAR18, VAR14,
VAR12, VAR16, VAR7);
input VAR1; input VAR8; output reg VAR17; output VAR6; output [ 2:0] VAR9; output [ 1:0] VAR13; output VAR2; output [31:0] VAR10; output [ 3:0] VAR5; input VAR15; input VAR3; output [31:... | gpl-3.0 |
vad-rulezz/megabot | minsoc/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v | 10,980 | module MODULE1
(
VAR26,
VAR25,
VAR27,
VAR14,
VAR31,
VAR37
);
parameter VAR36 = 32;
parameter VAR16 = 8;
parameter VAR13 = 8;
parameter VAR18= 8;
input [VAR36-1:0] VAR26;
input [VAR36-1:0] VAR25;
output [VAR36-1:0] VAR27;
input [VAR16-1:0] VAR14;
output [VAR13-1:0] VAR31;
inout [VAR18-1:0] VAR37;
VAR22 #(
.VAR10(12), .V... | gpl-2.0 |
UA3MQJ/fpga-synth | modules/ds8dac1.v | 1,208 | module MODULE1(clk, VAR6, VAR2);
output VAR2; reg VAR2; input [7:0] VAR6; input clk;
reg [9:0] VAR1; reg [9:0] VAR4; reg [9:0] VAR5; reg [9:0] VAR3;
begin
begin | gpl-3.0 |
HFoxtail/Mu80 | trunk/pll.v | 4,560 | module MODULE1 (
VAR52,
VAR6,
VAR108, VAR20, VAR86 );
input VAR52;
output VAR108;
output VAR20;
output VAR86;
output VAR6;
wire VAR108 = VAR24[0];
wire VAR20 = VAR24[1];
wire VAR86 = VAR24[2];
wire VAR6 = VAR35;
wire [4:0] VAR24;
VAR70 VAR93 (
.VAR31 ({1'h0, VAR52}),
.clk (VAR24),
.VAR48 (),
.VAR12 (1'b0),
.VAR49 (),
.... | gpl-3.0 |
deepakcu/digital_design | synchronizer/single_bit_cdc_synchronizer/single_bit_cdc_synchronizer.v | 2,506 | module MODULE1 #(
parameter VAR3 = 3 ) (
input clk, input din,
output VAR4;
);
reg[VAR3-1:0] VAR5;
assign VAR4=VAR5[VAR3-1];
integer VAR2;
always@(posedge VAR1)
begin
for(VAR2=1; VAR2<VAR3; VAR2=VAR2+1) begin
VAR5[VAR2] <= VAR5[VAR2-1];
end
end
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/clip.v | 1,251 | module MODULE1
parameter VAR3=0)
(input [VAR2-1:0] in,
output [VAR3-1:0] out);
wire VAR1 = |in[VAR2-1:VAR3-1] & ~(&in[VAR2-1:VAR3-1]);
assign out = VAR1 ?
(in[VAR2-1] ? {1'b1,{(VAR3-1){1'b0}}} : {1'b0,{(VAR3-1){1'b1}}}) :
in[VAR3-1:0];
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b.functional.v | 1,346 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR1
);
output VAR4 ;
input VAR8 ;
input VAR1;
wire VAR7 ;
wire VAR3;
not VAR2 (VAR7 , VAR1 );
or VAR5 (VAR3, VAR7, VAR8 );
buf VAR6 (VAR4 , VAR3 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_eclcomp7.v | 1,817 | module MODULE1 (
out,
VAR2, VAR1
) ;
input [6:0] VAR2;
input [6:0] VAR1;
output out;
wire [6:0] VAR3;
wire VAR7;
wire VAR4;
wire VAR6;
wire VAR5;
assign VAR3 = VAR2 ^ VAR1;
assign VAR7 = ~(VAR3[0] | VAR3[1]);
assign VAR4 = ~(VAR3[2] | VAR3[3]);
assign VAR6 = ~(VAR3[4] | VAR3[5]);
assign VAR5 = ~(VAR7 & VAR4 & VAR6);
as... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_nsr/sky130_fd_sc_ms__udp_dff_nsr.blackbox.v | 1,345 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR5,
VAR1,
VAR2
);
output VAR4 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR2 ;
endmodule | apache-2.0 |
efabless/openlane | designs/151/src/riscv_top.v | 3,217 | module MODULE1
(
input clk,
input reset,
output VAR23,
input VAR14,
output VAR20,
output [VAR2-1:0] VAR6,
output [VAR5-1:0] VAR1,
output VAR4,
input VAR18,
output [VAR8-1:0] VAR11,
output [(VAR8/8)-1:0] VAR29,
input VAR16,
input [VAR5-1:0] VAR21,
input [VAR8-1:0] VAR3,
output [31:0] VAR12
);
wire [31:0] VAR10; wire [31... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrckapwr/sky130_fd_sc_hd__lpflow_isobufsrckapwr.symbol.v | 1,525 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR3
);
supply1 VAR7;
supply1 VAR4 ;
supply0 VAR8 ;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
bbrown1867/ObjectTracking | hw/common/sram_wrapper.v | 1,830 | module MODULE1
(
input wire clk,
input wire VAR13,
input wire VAR10,
input wire [19:0] addr,
input wire [15:0] din,
output wire [15:0] dout,
output wire [19:0] VAR11,
output wire VAR5,
inout wire [15:0] VAR12,
output wire VAR7,
output wire VAR9,
output wire VAR3,
output wire VAR2
);
reg [15:0] VAR15;
reg [15:0] VAR14;
... | mit |
ehab93/MIPS-Processor | lib/mux32bit_2to1.v | 2,134 | module MODULE1(input [31:0] VAR30, VAR19,
input VAR2,
output [31:0] VAR17);
VAR36 VAR37 (.VAR30(VAR30[0 ]), .VAR19(VAR19[0 ]), .VAR17(VAR17[0 ]), .VAR2(VAR2));
VAR36 VAR31 (.VAR30(VAR30[1 ]), .VAR19(VAR19[1 ]), .VAR17(VAR17[1 ]), .VAR2(VAR2));
VAR36 VAR16 (.VAR30(VAR30[2 ]), .VAR19(VAR19[2 ]), .VAR17(VAR17[2 ]), .VAR2(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311ai/sky130_fd_sc_hs__o311ai.pp.blackbox.v | 1,361 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR8 ,
VAR4 ,
VAR2 ,
VAR5 ,
VAR6,
VAR1
);
output VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR5 ;
input VAR6;
input VAR1;
endmodule | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/niosII_system_usb_0.v | 6,805 | module MODULE1 (
clk,
reset,
address,
VAR11,
read,
write,
VAR12,
VAR6,
VAR8,
VAR10,
VAR3,
irq,
VAR2,
VAR9,
VAR5,
VAR4,
VAR13
);
input clk;
input reset;
input [ 1: 0] address;
input VAR11;
input read;
input write;
input [15: 0] VAR12;
input VAR6;
input VAR8;
inout [15: 0] VAR10;
output reg [15: 0] VAR3;
output reg irq;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221ai/sky130_fd_sc_hd__o221ai.pp.symbol.v | 1,409 | module MODULE1 (
input VAR5 ,
input VAR4 ,
input VAR3 ,
input VAR1 ,
input VAR9 ,
output VAR8 ,
input VAR2 ,
input VAR6,
input VAR7,
input VAR10
);
endmodule | apache-2.0 |
jameshegarty/rigel | platform/verilator/RAMB16_RIGEL.v | 4,810 | module MODULE1(
VAR15,
VAR30,
VAR70,
VAR35,
VAR54,
VAR23,
VAR80,
VAR77,
VAR44,
VAR4,
VAR8,
VAR59,
VAR5,
VAR63,
VAR9,
VAR7);
parameter VAR86 = "VAR81";
parameter VAR26 = "VAR81";
parameter VAR11=256'd0;
parameter VAR32=256'd0;
parameter VAR82=256'd0;
parameter VAR42=256'd0;
parameter VAR48=256'd0;
parameter VAR38=256'd0... | mit |
jamieiles/80x86 | fpga/de0-cv/SysPLL.v | 2,259 | module MODULE1(
input wire VAR46,
input wire rst,
output wire VAR20,
output wire VAR33,
output wire VAR31,
output wire VAR30,
output wire VAR43
);
VAR6 #(
.VAR40("false"),
.VAR72("50.0 VAR49"),
.VAR68("VAR25"),
.VAR64(4),
.VAR21("50.000000 VAR49"),
.VAR60("-3864 VAR4"),
.VAR37(50),
.VAR7("50.000000 VAR49"),
.VAR52("0 V... | gpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_SLVT_SS_210930.v | 73,208 | module MODULE1 (VAR13, VAR12, VAR9, VAR6);
output VAR13;
input VAR12, VAR9, VAR6;
reg VAR5;
wire VAR11, VAR8;
wire VAR4, VAR3, VAR10;
wire VAR16;
not (VAR4, VAR11);
not (VAR10, VAR9);
VAR14 (VAR16, VAR8, VAR4, VAR10);
VAR1 (VAR3, VAR5, VAR8, VAR4, VAR10, VAR16);
buf (VAR13, VAR3);
wire VAR15, VAR7, VAR2;
and (VAR15, VA... | bsd-3-clause |
secworks/sha256 | src/interfaces/axi4/rtl/sha256_axi4_slave.v | 48,921 | module MODULE1 #
(
parameter integer VAR44 = 32,
parameter integer VAR93 = 8
)
(
input wire VAR77,
input wire VAR33,
input wire [VAR93-1 : 0] VAR104,
input wire [2 : 0] VAR47,
input wire VAR20,
output wire VAR88,
input wire [VAR44-1 : 0] VAR101,
input wire [(VAR44/8)-1 : 0] VAR11,
input wire VAR79,
output wire VAR22,
o... | bsd-2-clause |
pavel-demin/red-pitaya-notes | cores/axis_lfsr_v1_0/axis_lfsr.v | 1,664 | module MODULE1 #
(
parameter integer VAR5 = 64,
parameter VAR2 = "VAR12"
)
(
input wire VAR6,
input wire VAR3,
input wire VAR7,
output wire [VAR5-1:0] VAR13,
output wire VAR4
);
reg [VAR5-1:0] VAR10, VAR11;
reg VAR1, VAR9;
always @(posedge VAR6)
begin
if(~VAR3)
begin
VAR10 <= 64'h5555555555555555;
VAR1 <= 1'b0;
end
els... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp.behavioral.v | 2,922 | module MODULE1 (
VAR30 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR5 ,
VAR20 ,
VAR2
);
output VAR30 ;
output VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR20 ;
input VAR2;
supply1 VAR21;
supply0 VAR33;
supply1 VAR16 ;
supply0 VAR12 ;
wire VAR6 ;
wire VAR4 ;
wire VAR9 ;
reg VAR8 ;
wire VAR18 ;
wire VAR11 ;
wire VAR24 ;
wire VAR2... | apache-2.0 |
freecores/zet86 | rtl-model/exec.v | 4,046 | module MODULE1 (
output [15:0] VAR13,
output [15:0] VAR8,
output [15:0] VAR47,
output [15:0] VAR55,
output [15:0] VAR12,
output [15:0] VAR19,
output [15:0] VAR34,
output [15:0] VAR30,
output [15:0] VAR14,
output [ 3:0] VAR49,
output [15:0] VAR58,
output [ 3:0] VAR39,
output [ 8:0] VAR28,
input [VAR46-1:0] VAR11,
input ... | gpl-3.0 |
fpgasystems/caribou | hw/src/regex/rem_top_ff.v | 10,220 | module MODULE1 #(parameter VAR12=32, VAR50=0, VAR2=4)
(
clk,
rst, VAR61,
VAR23,
VAR54,
VAR35,
VAR14,
VAR57,
VAR33
);
input clk;
input rst;
input VAR61;
input VAR23;
input [511:0] VAR54;
output reg VAR35;
output reg VAR14;
output reg VAR57;
output reg [15:0] VAR33;
reg VAR42;
reg VAR47;
reg VAR59;
reg VAR9;
reg [511:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlxtp/sky130_fd_sc_hvl__dlxtp.pp.symbol.v | 1,337 | module MODULE1 (
input VAR7 ,
output VAR6 ,
input VAR4,
input VAR1 ,
input VAR2,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
jouyang3/FMCW | DSP/Radar_DSP/FPGA/SerialInterface.v | 3,330 | module MODULE1(
input clk,
input VAR25,
input VAR22,
input [11:0] VAR2,
input [11:0] VAR6,
output reg VAR21,
output reg VAR19
);
localparam VAR18 = 3'b000;
localparam VAR29 = 3'b001;
localparam VAR17 = 3'b010;
localparam VAR4 = 3'b011;
localparam VAR14 = 3'b100;
localparam VAR10 = 3'b101;
localparam VAR33 = 3'b110;
loc... | gpl-3.0 |
dcsun88/ntpserver-fpga | vhd/ip/ocxo_clk_pll/ocxo_clk_pll_stub.v | 1,183 | module MODULE1(VAR3, VAR4, VAR1, VAR2)
;
input VAR3;
output VAR4;
input VAR1;
output VAR2;
endmodule | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/edk_bee3/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_pcore.v | 9,036 | module MODULE2 #
(
parameter VAR56= 0, parameter VAR73 = 0
)
(
VAR15,
VAR30,
VAR67,
VAR24,
VAR68,
VAR75,
VAR36,
VAR18,
VAR12,
VAR23,
VAR47,
VAR71,
VAR3,
VAR65,
VAR1,
VAR45,
VAR22,
VAR69,
VAR8
);
input VAR15;
output VAR30;
input VAR36;
input VAR18;
output VAR67;
output VAR24;
output VAR68;
output VAR75;
input [0:15] VAR... | gpl-2.0 |
gbraad/minimig-de1 | lib/altera/sgate.v | 30,160 | module MODULE1 ( VAR3, VAR7, VAR1, VAR8, VAR5 );
parameter VAR6 = 32;
parameter VAR9 = 32;
parameter VAR4 = 32;
parameter VAR2 = 1;
input [VAR6-1:0] VAR3;
input [VAR9-1:0] VAR7;
input VAR1;
output VAR8;
output [VAR4-1:0] VAR5;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
b... | gpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_rank_timer.v | 119,540 | module MODULE1 #
( parameter
VAR208 = 2,
VAR178 = 4,
VAR92 = "VAR175",
VAR105 = 1,
VAR22 = 1,
VAR97 = 4,
VAR54 = 2,
VAR242 = 0,
VAR173 = 0,
VAR87 = 5,
VAR40 = 0,
VAR37 = 0,
VAR142 = 0,
VAR96 = 0,
VAR160 = 0,
VAR233 = 0,
VAR127 = 0,
VAR115 = 0,
VAR71 = 0,
VAR72 = 0,
VAR185 = 0,
VAR201 = 0
)
(
VAR25,
VAR239,
VAR192,
VAR1... | gpl-2.0 |
csturton/wirepatch | system/hardware/cores/ethmac/eth_register.v | 4,460 | module MODULE1(VAR5, VAR8, VAR2, VAR1, VAR4, VAR6);
parameter VAR3 = 8; parameter VAR7 = 0;
input [VAR3-1:0] VAR5;
input VAR2;
input VAR1;
input VAR4;
input VAR6;
output [VAR3-1:0] VAR8;
reg [VAR3-1:0] VAR8;
always @ (posedge VAR1 or posedge VAR4)
begin
if(VAR4)
VAR8<= VAR7;
end
else
if(VAR6)
VAR8<= VAR7;
else
if(VAR2)... | mit |
ShepardSiegel/ocpi | rtl/mkWsiAdapter4B16B.v | 32,816 | module MODULE1(VAR57,
VAR40,
VAR88,
VAR39,
VAR101,
VAR36,
VAR110,
VAR144,
VAR52,
VAR125,
VAR139,
VAR41,
VAR153,
VAR162,
VAR177,
VAR213,
VAR217,
VAR114,
VAR12,
VAR119,
VAR72,
VAR121);
input VAR57;
input VAR40;
input [2 : 0] VAR88;
input VAR39;
input VAR101;
input [11 : 0] VAR36;
input [31 : 0] VAR110;
input [3 : 0] VAR1... | lgpl-3.0 |
briburrell/amica | device/bitstream/ztex_ufm1_15y1.v | 10,868 | module MODULE1 (VAR47, reset, select, VAR23, VAR103, VAR105, VAR87, VAR16, VAR60, VAR40, VAR101, read, write);
input VAR47, select, reset, VAR23, VAR103, VAR105, VAR87, VAR16, VAR60, VAR40, VAR101;
input [7:0] read;
output [7:0] write;
function integer VAR112; input integer VAR35;
begin
VAR35 = VAR35-1;
for (VAR112=0; ... | gpl-3.0 |
jas0n1ee/THU-DSD | FB/cpu_mult_cell.v | 6,050 | module MODULE1 (
VAR35,
VAR49,
clk,
VAR5,
VAR41
)
;
output [ 31: 0] VAR41;
input [ 31: 0] VAR35;
input [ 31: 0] VAR49;
input clk;
input VAR5;
wire [ 31: 0] VAR41;
wire [ 31: 0] VAR40;
wire [ 15: 0] VAR30;
wire VAR46;
assign VAR46 = ~VAR5;
VAR24 VAR54
(
.VAR31 (VAR46),
.VAR29 (clk),
.VAR18 (VAR35[15 : 0]),
.VAR26 (VAR49... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp.pp.symbol.v | 1,579 | module MODULE1 (
input VAR2 ,
output VAR9 ,
input VAR12,
input VAR11 ,
input VAR8 ,
input VAR5 ,
input VAR10,
input VAR3 ,
input VAR1 ,
input VAR4 ,
input VAR7 ,
input VAR6
);
endmodule | apache-2.0 |
lvd2/ngs | cpld/cpld5_buf/GS_cpld.v | 6,871 | module MODULE1(
output reg VAR16, input wire VAR26, input wire VAR54, output wire VAR69, input wire VAR52,
input wire VAR32, input wire VAR22, input wire VAR79, input wire VAR61, output wire VAR33,
input wire VAR42,
input wire VAR8, output reg VAR29,
input wire VAR49, input wire VAR57,
input wire VAR36,
input wire VAR5... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bushold/sky130_fd_sc_lp__bushold.blackbox.v | 1,329 | module MODULE1 (
VAR5 ,
VAR2
);
inout VAR5 ;
input VAR2;
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp.pp.blackbox.v | 1,399 | module MODULE1 (
VAR4 ,
VAR8,
VAR6 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR5 ,
VAR1
);
output VAR4 ;
input VAR8;
input VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build1/alu.v | 168,961 | module MODULE1 (VAR8,VAR6,VAR7,VAR5,VAR3,VAR4,VAR1);
output [0:127] VAR4;
input [0:127] VAR8;
input [0:127] VAR6;
input [0:2] VAR7;
input [0:1] VAR5;
input [0:4] VAR3;
input [15:0] VAR1;
parameter VAR2 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR4;
always @(VAR8 or VAR6 or VAR7 or VAR5 or VAR3 or VAR1)
begi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.v | 2,290 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR5 ,
VAR7 ,
VAR3,
VAR6 ,
VAR9
);
output VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR3;
input VAR6 ;
input VAR9 ;
VAR4 VAR2 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR1,
VAR8
);
output VAR1;
inpu... | apache-2.0 |
alexforencich/xfcp | lib/wb/rtl/axis_wb_master.v | 22,149 | module MODULE1 #
(
parameter VAR4 = 0, parameter VAR21 = 16, parameter VAR1 = 8, parameter VAR15 = (VAR1/8), parameter VAR16 = 32, parameter VAR9 = 32, parameter VAR8 = (VAR16/8), parameter VAR14 = 8'hA1, parameter VAR40 = 8'hA2, parameter VAR12 = 8'hA3, parameter VAR42 = 8'hA4 )
(
input wire clk,
input wire rst,
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf.functional.pp.v | 1,772 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR3,
VAR6,
VAR9 ,
VAR10
);
output VAR1 ;
input VAR2 ;
input VAR3;
input VAR6;
input VAR9 ;
input VAR10 ;
wire VAR7 ;
wire VAR4;
buf VAR5 (VAR7 , VAR2 );
VAR11 VAR12 (VAR4, VAR7, VAR3, VAR6);
buf VAR8 (VAR1 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.v | 2,001 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR4 ,
VAR1,
VAR5
);
input VAR2 ;
input VAR7 ;
output VAR4 ;
input VAR1;
input VAR5;
VAR3 VAR6 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR2,
VAR7 ,
VAR4
);
input VAR2;
input VAR7 ;
output VAR4 ;
supply1 VAR1;
supply0 VAR5;
VAR3 VAR6 ... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v | 25,791 | module MODULE1 #(
parameter VAR41 = 0,
parameter integer VAR126 = 4,
parameter integer VAR71 = 30,
parameter integer VAR119 = 32,
parameter integer VAR104 = 1,
parameter integer VAR66 = 1
)
(
input wire VAR2 ,
input wire VAR107 ,
input wire [VAR126-1:0] VAR62 ,
input wire [VAR71-1:0] VAR124 ,
input wire [((VAR41 == 1) ... | gpl-3.0 |
m-labs/milkymist | cores/minimac2/rtl/minimac2.v | 3,949 | module MODULE1 #(
parameter VAR49 = 4'h0
) (
input VAR16,
input VAR5,
input [13:0] VAR25,
input VAR45,
input [31:0] VAR26,
output [31:0] VAR42,
output VAR31,
output VAR47,
input [31:0] VAR17,
output [31:0] VAR66,
input [31:0] VAR3,
input [3:0] VAR60,
input VAR7,
input VAR61,
output VAR2,
input VAR35,
input VAR20,
outpu... | lgpl-3.0 |
cmos3511/cmos_linux | python/pj/proj/rtl/LP/addpp32.v | 7,895 | module MODULE1(VAR38,VAR24,VAR41,VAR47,VAR56,VAR55,VAR28,VAR31,VAR13,VAR62,
VAR48,VAR45,VAR43,VAR63,VAR22,VAR4,VAR25,VAR15,VAR64,VAR49);
output VAR38; output [31:0] VAR24; input [32:0] VAR41; input [32:0] VAR47; input [32:0] VAR56; input [32:0] VAR55; input [32:0] VAR28; input [32:0] VAR31; input [32:0] VAR13; input [3... | gpl-3.0 |
aap/pdp6 | verilog/wcsl420.v | 1,377 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR16,
input wire VAR4,
input wire VAR10,
input wire VAR18,
input wire VAR3,
input wire VAR14,
input wire VAR19,
input wire VAR12,
input wire VAR17, input wire [3:9] VAR6,
input wire [0:35] VAR1,
output wire [1:7] VAR7,
output wire [0:35] VAR20,
output wire V... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.behavioral.pp.v | 18,378 | module MODULE1( VAR123, VAR88, VAR289, VAR29, VAR66, VAR111, VAR182, VAR141 );
input VAR29, VAR289, VAR66, VAR123, VAR88;
inout VAR182, VAR141;
output VAR111;
reg VAR117;
VAR32 VAR55(.VAR123(VAR123),.VAR88(VAR88),.VAR289(VAR289),.VAR29(VAR29),.VAR66(VAR66),.VAR111(VAR111),.VAR182(VAR182),.VAR141(VAR141),.VAR117(VAR117)... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/rec_tlb.v | 14,418 | module MODULE1 (
clk ,
VAR17 ,
VAR3 ,
VAR32 ,
VAR49 ,
VAR55 ,
VAR50 ,
VAR39 ,
VAR45 ,
VAR51 ,
VAR46 ,
VAR13 ,
VAR7 ,
VAR47 ,
VAR33 ,
VAR54 ,
VAR30 ,
VAR52 ,
VAR12
);
localparam VAR34 = 2'b00 ,
VAR11 = 2'b01 ,
VAR53 = 2'b10 ,
VAR21 = 2'b11 ;
localparam VAR56 = 0 ,
VAR10 = 1 ;
input clk ;
input VAR17 ;
input VAR3 ;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai.behavioral.pp.v | 2,010 | module MODULE1 (
VAR11 ,
VAR15 ,
VAR12 ,
VAR16 ,
VAR14,
VAR5,
VAR3 ,
VAR13
);
output VAR11 ;
input VAR15 ;
input VAR12 ;
input VAR16 ;
input VAR14;
input VAR5;
input VAR3 ;
input VAR13 ;
wire VAR4 ;
wire VAR9 ;
wire VAR2;
or VAR7 (VAR4 , VAR12, VAR15 );
nand VAR6 (VAR9 , VAR16, VAR4 );
VAR10 VAR1 (VAR2, VAR9, VAR14, VA... | apache-2.0 |
davidlee80/miaow | src/verilog/rtl/salu/salu_controller.v | 8,855 | module MODULE1(
VAR25,
VAR23,
VAR2,
VAR24,
VAR6,
VAR22,
VAR19,
VAR15,
VAR26,
VAR13,
VAR7,
VAR21,
VAR12,
VAR4,
VAR17,
rst
);
input [11:0] VAR23;
input [31:0] VAR2;
input VAR25, rst;
output VAR22, VAR19, VAR15, VAR26, VAR12,
VAR4, VAR17;
output [1:0] VAR7, VAR21, VAR13;
output [5:0] VAR6;
output [31:0] VAR24;
reg VAR8, V... | bsd-3-clause |
alexandruioanp/Open-Logic-Analyzer | src/AssembledLogicAnalyzer.v | 1,067 | module MODULE1(input VAR1, input VAR7, input [7:0] VAR11, input VAR19, input [15:0] VAR18, output VAR15,
output [15:0] VAR32);
wire VAR9, VAR12;
wire [9:0] VAR31;
wire [15:0] VAR5;
wire [15:0] VAR23;
wire [9:0] VAR4;
wire VAR8;
wire [31:0] VAR17;
wire VAR3, VAR16;
VAR24 VAR10(
.VAR1(VAR1),
.VAR9(VAR9),
.VAR12(VAR12),
.... | gpl-2.0 |
rkrajnc/minimig-de1 | lib/altera/max_atoms.v | 102,169 | module MODULE1 (VAR4, VAR10, VAR5, VAR9);
parameter VAR3 = "input";
parameter VAR2 = "false";
parameter VAR12 = "false";
parameter VAR15 = "false";
input VAR4, VAR10;
output VAR9;
inout VAR5;
reg VAR7;
reg VAR8, VAR6;
reg VAR1;
wire VAR13;
wire VAR11;
buf(VAR13, VAR4);
buf(VAR11, VAR10);
tri VAR14;
begin
begin
begin
be... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s.functional.v | 1,345 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
wire VAR5;
buf VAR3 (VAR5, VAR4 );
buf VAR2 (VAR1 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbn/sky130_fd_sc_hs__dlxbn.functional.v | 1,865 | module MODULE1 (
VAR1 ,
VAR13 ,
VAR11 ,
VAR15 ,
VAR7 ,
VAR14
);
input VAR1 ;
input VAR13 ;
output VAR11 ;
output VAR15 ;
input VAR7 ;
input VAR14;
wire VAR9 ;
wire VAR8 ;
wire VAR3;
wire VAR12 ;
not VAR2 (VAR9 , VAR14 );
VAR4 VAR5 VAR6 (VAR8 , VAR7, VAR9, VAR1, VAR13);
buf VAR16 (VAR11 , VAR8 );
not VAR10 (VAR15 , VAR8... | apache-2.0 |
horia141/mv-parser | common/dcm.v | 1,368 | module MODULE1(VAR19,reset,VAR21,VAR17,VAR44,VAR41,VAR37,VAR28,VAR30);
input wire [('b1) - ('b1):0] VAR19;
input wire [('b1) - ('b1):0] reset;
output wire [('b1) - ('b1):0] VAR21;
output wire [('b1) - ('b1):0] VAR17;
output wire [('b1) - ('b1):0] VAR44;
output wire [('b1) - ('b1):0] VAR41;
output wire [('b1) - ('b1):0]... | mit |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/mor1kx.v | 16,944 | module MODULE1
parameter VAR42 = 32,
parameter VAR113 = "VAR132",
parameter VAR134 = "VAR63",
parameter VAR7 = 5,
parameter VAR139 = 9,
parameter VAR99 = 2,
parameter VAR121 = 32,
parameter VAR80 = "VAR63",
parameter VAR152 = "VAR63",
parameter VAR136 = "VAR63",
parameter VAR53 = 6,
parameter VAR96 = 1,
parameter VAR12... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/mem_if/sram_top.v | 13,112 | module MODULE1 (
VAR27, VAR15,
VAR23, VAR10, VAR30, VAR11, VAR20, VAR12,
VAR13, VAR25, VAR24,
VAR1, VAR29, VAR2, VAR6, VAR17, VAR7, VAR32, VAR14,
VAR33, VAR4, VAR9, VAR26, VAR21, VAR31, VAR28
);
parameter VAR8 = 19;
input VAR27;
input VAR15;
input [31:0] VAR23;
output [31:0] VAR10;
input [31:0] VAR30;
input [3:0] VAR11... | gpl-3.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/SpecialMult.v | 4,153 | module MODULE1(
input [31:0] VAR13,
input [31:0] VAR3,
input reset,
input VAR10,
output reg VAR4 = 1'b0,
output reg [32:0] VAR7,
output reg [32:0] VAR9,
output reg [32:0] VAR5
);
wire VAR1;
wire [7:0] VAR6;
wire [23:0] VAR14;
wire VAR12;
wire [7:0] VAR2;
wire [23:0] VAR8;
assign VAR1 = VAR13[31];
assign VAR6 = {VAR13[3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputisolatch/sky130_fd_sc_lp__inputisolatch.behavioral.pp.v | 1,874 | module MODULE1 (
VAR4 ,
VAR12 ,
VAR7,
VAR14 ,
VAR2 ,
VAR11 ,
VAR1
);
output VAR4 ;
input VAR12 ;
input VAR7;
input VAR14 ;
input VAR2 ;
input VAR11 ;
input VAR1 ;
wire VAR9 ;
wire VAR5;
wire VAR3 ;
reg VAR13 ;
VAR10 VAR6 (VAR9 , VAR3, VAR5, VAR13, VAR14, VAR2);
buf VAR8 (VAR4 , VAR9 );
endmodule | apache-2.0 |
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