repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn.pp.blackbox.v | 1,297 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR2,
VAR4,
VAR1,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR6 ;
input VAR2;
input VAR4;
input VAR1;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/582af9791eb33514/ip_design_lms_pcore_0_0_stub.v | 2,559 | module MODULE1(VAR13, VAR11, VAR6,
VAR2, VAR8, VAR18, VAR4, VAR21,
VAR5, VAR14, VAR3, VAR7,
VAR20, VAR16, VAR9, VAR17, VAR15,
VAR12, VAR10, VAR19, VAR1)
;
input VAR13;
input VAR11;
input VAR6;
input VAR2;
input [15:0]VAR8;
input VAR18;
input [31:0]VAR4;
input [3:0]VAR21;
input VAR5;
input VAR14;
input [15:0]VAR3;
input... | mit |
sam-falvo/kestrel | cores/MGIA/rtl/verilog/timebase.v | 2,295 | module MODULE1(
input VAR9,
input VAR24,
output VAR25,
output VAR22,
output VAR12,
output VAR10,
output VAR23,
output VAR26
);
reg VAR20;
reg VAR27;
reg VAR14;
reg VAR15;
reg VAR2;
reg VAR1;
reg [9:0] VAR7;
reg [9:0] VAR18;
reg [9:0] VAR28;
reg [9:0] VAR3;
wire VAR13 = VAR7 == 794;
wire VAR4 = VAR9 | VAR13;
wire VAR11 ... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai.symbol.v | 1,391 | module MODULE1 (
input VAR4,
input VAR6,
input VAR5,
input VAR9,
input VAR8,
output VAR3
);
supply1 VAR2;
supply0 VAR10;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/spare/build1/prog_counter2a.v | 1,203 | module MODULE1 (VAR1,rst,clk);
output [0:31] VAR1;
input clk;
input rst;
reg [0:31] VAR1;
always @(posedge clk)
begin
if(rst)
begin
VAR1<=32'd0;
end
else
begin
VAR1<=VAR1+32'd4;
end
end
endmodule | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Pruebas/Pruebabitcont/fifo.v | 3,735 | module MODULE1 # (parameter VAR2 = 400, VAR16 = 1)(
input reset, VAR13,
input rd, wr,
input [VAR16-1:0] din,
output [VAR16-1:0] dout,
output VAR6,
output VAR17,
output reg VAR12
);
wire VAR8;
wire VAR7;
reg VAR18, VAR22;
reg [VAR16-1:0] out;
VAR9 VAR12 = 0;
reg [1:0] VAR5;
reg [1:0] VAR4;
assign VAR8 = VAR18;
assign VA... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/FIFO_OPENFLOW/ram_128_11.v | 9,593 | module MODULE1 (
VAR17,
VAR9,
VAR11,
VAR21,
VAR31,
VAR6,
VAR16,
VAR20);
input VAR17;
input VAR9;
input [10:0] VAR11;
input [6:0] VAR21;
input VAR31;
input [6:0] VAR6;
input VAR16;
output [10:0] VAR20;
tri0 VAR17;
tri1 VAR9;
tri1 VAR31;
tri0 VAR16;
wire [10:0] VAR52;
wire [10:0] VAR20 = VAR52[10:0];
VAR40 VAR12 (
.VAR50... | apache-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/pixelq_op_CONTROL_BUS_if.v | 8,776 | module MODULE1
VAR18 = 5,
VAR53 = 32
)(
input wire VAR38,
input wire VAR59,
input wire [VAR18-1:0] VAR15,
input wire VAR51,
output wire VAR24,
input wire [VAR53-1:0] VAR25,
input wire [VAR53/8-1:0] VAR57,
input wire VAR19,
output wire VAR30,
output wire [1:0] VAR43,
output wire VAR29,
input wire VAR16,
input wire [VAR1... | gpl-2.0 |
ncos/Xilinx-Verilog | INTERFACES/src/CAN/can.v | 1,336 | module MODULE1
(
input wire VAR8,
inout wire VAR17,
inout wire VAR12,
input wire VAR5,
input wire [107:0] VAR22,
input wire VAR16,
output wire VAR11,
output reg [107:0] VAR3,
input wire VAR6,
output wire VAR21
);
assign VAR12 = ~VAR17;
reg [107:0] VAR1;
reg [107:0] VAR15;
wire VAR19;
wire VAR14;
VAR4 VAR18 (
.VAR8(VAR8... | mit |
revaldinho/opc | opc8/opc8cpu.v | 4,360 | module MODULE1(input[23:0] din,input clk,input VAR28,input[1:0] VAR53,input VAR10,output VAR11,output VAR16,output[23:0] dout,output[23:0] address,output VAR62);
parameter VAR9=5'h00,VAR46=5'h01,VAR23=5'h02,VAR2=5'h03,VAR24=5'h04,VAR68=5'h05,VAR57=5'h06,VAR1=5'h07,VAR37=5'h08,VAR45=5'h09,VAR34=5'h0A,VAR60=5'h0B;
parame... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/altera_up_YCrCb_to_RGB_converter.v | 14,139 | module MODULE1 (
clk,
VAR19,
reset,
VAR47,
VAR45,
VAR6,
VAR32,
VAR13,
VAR48,
VAR46,
VAR38,
VAR43,
VAR7,
VAR9,
VAR39,
VAR10,
VAR57
);
input clk;
input VAR19;
input reset;
input [ 7: 0] VAR47;
input [ 7: 0] VAR45;
input [ 7: 0] VAR6;
input VAR32;
input VAR13;
input VAR48;
input VAR46;
output reg [ 7: 0] VAR38;
output reg... | gpl-2.0 |
lvd2/zxevo | fpga/base_trdemu/trunk/video/video_palframe.v | 6,550 | module MODULE1(
input wire clk,
input wire VAR33,
input wire VAR21,
input wire VAR45,
input wire VAR20,
input wire VAR2,
input wire VAR50,
input wire [ 3:0] VAR34,
input wire [ 3:0] VAR19,
input wire VAR28,
input wire VAR36,
input wire [ 1:0] VAR11,
input wire [ 2:0] VAR31,
input wire [ 2:0] VAR5,
input wire VAR16,
inp... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ip_top/mem_intfc.v | 39,254 | module MODULE1 #
(
parameter VAR109 = 100,
parameter VAR86 = 64,
parameter VAR230 = "VAR262",
parameter VAR74 = "0", parameter VAR194 = 3, parameter VAR252 = 2, parameter VAR254 = "8", parameter VAR212 = "VAR198", parameter VAR39 = 1, parameter VAR72 = 5,
parameter VAR190 = 12, parameter VAR218 = "VAR79", parameter VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41o/sky130_fd_sc_ms__a41o.pp.symbol.v | 1,388 | module MODULE1 (
input VAR6 ,
input VAR7 ,
input VAR10 ,
input VAR2 ,
input VAR1 ,
output VAR5 ,
input VAR3 ,
input VAR4,
input VAR9,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32oi/sky130_fd_sc_hd__a32oi.symbol.v | 1,433 | module MODULE1 (
input VAR1,
input VAR10,
input VAR5,
input VAR2,
input VAR9,
output VAR7
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
calee0219/Course | DLAB/Lab08/Lab08_0416037.v | 5,082 | module MODULE1(
input clk,
input rst,
input VAR31,
input VAR15,
input VAR39,
input [3:0] VAR42,
output reg [7:0] VAR21,
output [11:8] VAR35,
output VAR22,
output VAR8,
output VAR24
);
integer VAR20=2000000;
integer VAR19=1000;
parameter VAR30=0;
parameter VAR13=1;
parameter VAR27=2;
parameter VAR23=0;
parameter VAR41=1... | mit |
acarrer/altera-de1-mp3-recorder-vhdl | RegistratorePortatile.v | 12,326 | module MODULE1(
inout [15:0] VAR78, output [11:0] VAR63, output VAR75, output VAR40, output VAR87, output VAR10, output VAR68, output VAR17, output VAR84, output VAR35, output VAR134, output VAR105,
input VAR73,
input [3:0] VAR22, input [9:0] VAR59, output [6:0] VAR94, output [6:0] VAR15, output [6:0] VAR55, output [6:... | mit |
eda-globetrotter/MarcheProcessor | processor/syn/netlist/program_counter2.syn.v | 10,427 | module MODULE1 ( VAR106, VAR42, VAR154, VAR51, VAR45 );
input [31:0] VAR106;
input [31:0] VAR42;
output [31:0] VAR51;
input VAR154;
output VAR45;
wire VAR121, VAR6, VAR13, VAR99, VAR61, VAR151, VAR22,
VAR20, VAR177, VAR57, VAR113, VAR164, VAR97,
VAR221, VAR206, VAR67, VAR108, VAR86, VAR53,
VAR155, VAR103, VAR220, VAR11... | mit |
zuloloxi/mecrisp-ice | nandland/icestorm/uart.v | 4,551 | module MODULE5(
input wire clk,
output wire VAR2
);
localparam VAR9 = (VAR21 / VAR1) - 1;
localparam VAR27 = VAR26(VAR9);
wire [VAR27-1:0] VAR30 = VAR9;
reg [VAR27-1:0] counter;
assign VAR2 = (counter == VAR30);
always @(posedge clk)
counter <= VAR2 ? 0 : (counter + 1);
endmodule
module MODULE2(
input wire clk,
input w... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcin/sky130_fd_sc_hs__fahcin.behavioral.v | 2,648 | module MODULE1 (
VAR14,
VAR8 ,
VAR18 ,
VAR25 ,
VAR1 ,
VAR6,
VAR24
);
output VAR14;
output VAR8 ;
input VAR18 ;
input VAR25 ;
input VAR1 ;
input VAR6;
input VAR24;
wire VAR26 ;
wire VAR9 ;
wire VAR16 ;
wire VAR22 ;
wire VAR2 ;
wire VAR15 ;
wire VAR17 ;
wire VAR21;
not VAR20 (VAR26 , VAR1 );
xor VAR4 (VAR9 , VAR18, VAR25... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp.symbol.v | 1,518 | module MODULE1 (
input VAR6 ,
output VAR2 ,
input VAR1,
input VAR10 ,
input VAR4 ,
input VAR8
);
supply1 VAR9;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_axis_dma_tx.v | 8,820 | module MODULE1 (
VAR23,
VAR37,
VAR14,
VAR46,
VAR26,
VAR32,
VAR49,
VAR4,
VAR44,
VAR28,
VAR41,
VAR21,
VAR7,
VAR34,
VAR9);
parameter VAR36 = 32'h00050062;
parameter VAR39 = 0;
input VAR23;
output VAR37;
input VAR14;
output VAR46;
output [31:0] VAR26;
input VAR32;
input VAR49;
input VAR4;
input VAR44;
input VAR28;
input VA... | mit |
8l/beri | cheri/trunk/FPU/QuartusProject/floatMulWrapper.v | 1,637 | module MODULE1 (
VAR3,
VAR7,
VAR2,
VAR5,
VAR4);
input VAR3;
input [31:0] VAR7;
input [31:0] VAR2;
output [31:0] VAR5;
input VAR4;
VAR6 VAR1 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.symbol.v | 1,530 | module MODULE1 (
input VAR5,
output VAR6
);
wire VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
supply1 VAR1 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v | 4,551 | module MODULE1
,parameter VAR4(VAR60)
,parameter VAR4(VAR71)
,parameter VAR56=VAR30
,parameter VAR4(VAR23)
,parameter VAR4(VAR25)
,parameter VAR4(VAR28)
,parameter VAR4(VAR48)
,parameter VAR29=VAR70(VAR30)
,parameter VAR33=(VAR28/VAR60)
)
(
input VAR43
,input VAR65
,input VAR58
,output logic VAR9
,input [VAR29-1:0] VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv.pp.blackbox.v | 1,332 | module MODULE1 (
VAR5,
VAR1 ,
VAR4 ,
VAR2 ,
VAR3
);
output VAR5;
input VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai.pp.symbol.v | 1,376 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR8 ,
input VAR5 ,
output VAR3 ,
input VAR7 ,
input VAR2,
input VAR1,
input VAR9
);
endmodule | apache-2.0 |
idgaf/Verilog_codes | Submit Folder/EX9/FramesyncFSM.v | 1,538 | module MODULE1(clk,rst,VAR5,VAR4,VAR9,VAR10,VAR1,VAR12);
input wire clk,rst,VAR5;
output reg VAR4,VAR9;
output reg [1:0]VAR10;
output wire VAR12;
output reg VAR1;
reg [1:0]VAR3;
reg [1:0]VAR11;
reg [7:0]VAR7;
reg VAR8;
VAR2 VAR6(VAR5,VAR12,clk);
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
end
begin
en... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4/sky130_fd_sc_ls__nand4_4.v | 2,253 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR4 ,
VAR10 ,
VAR7 ,
VAR9,
VAR5,
VAR6 ,
VAR11
);
output VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR10 ;
input VAR7 ;
input VAR9;
input VAR5;
input VAR6 ;
input VAR11 ;
VAR8 VAR3 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VA... | apache-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_Pipistrello/src/cog_alu.v | 7,092 | module MODULE1
(
input [5:0] VAR21,
input [31:0] VAR9,
input [31:0] VAR8,
input [8:0] VAR10,
input VAR28,
input VAR16,
input VAR26,
input [31:0] VAR7,
input VAR20,
output wr,
output [31:0] VAR25,
output VAR31,
output VAR13
);
wire [31:0] VAR23 = { VAR8[0], VAR8[1], VAR8[2], VAR8[3], VAR8[4], VAR8[5], VAR8[6], VAR8[7],
... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/Debounce_Index.v | 1,428 | module MODULE1
(
VAR6,
reset,
VAR7,
VAR2,
VAR9
);
input VAR6;
input reset;
input VAR7;
input VAR2;
output VAR9;
wire [7:0] VAR8; wire VAR3;
assign VAR8 = 8'd25;
VAR10 VAR1 (.VAR6(VAR6),
.reset(reset),
.VAR7(VAR7),
.VAR5(VAR2),
.VAR11(VAR8), .VAR4(VAR3)
);
assign VAR9 = VAR3;
endmodule | gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/verilog/feedforward_fptrunc_64ns_32_1.v | 1,127 | module MODULE1
VAR16 = 3,
VAR8 = 1,
VAR4 = 64,
VAR9 = 32
)(
input wire [VAR4-1:0] VAR12,
output wire [VAR9-1:0] dout
);
wire VAR6;
wire [63:0] VAR10;
wire VAR3;
wire [31:0] VAR11;
VAR2 VAR13 (
.VAR14 ( VAR6 ),
.VAR7 ( VAR10 ),
.VAR15 ( VAR3 ),
.VAR1 ( VAR11 )
);
assign VAR6 = 1'b1;
assign VAR10 = VAR12==='VAR5 ? 'b0 : ... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/loacal_sw.v | 2,138 | module MODULE1(
input clk,
input reset,
output reg [31:0] VAR24,
input [64:0] VAR9,
input VAR17,
output reg VAR10,
output reg VAR7,
output reg VAR6,
output reg [31:0] VAR20,
input VAR22,
input [31:0] VAR29
);
reg VAR16;
reg [64:0] VAR21;
wire [64:0] VAR23;
wire VAR13;
reg [7:0] VAR5;
reg [2:0] VAR4;
localparam
VAR26 = ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211oi/sky130_fd_sc_ms__a211oi.behavioral.pp.v | 2,044 | module MODULE1 (
VAR14 ,
VAR17 ,
VAR11 ,
VAR5 ,
VAR9 ,
VAR13,
VAR12,
VAR8 ,
VAR1
);
output VAR14 ;
input VAR17 ;
input VAR11 ;
input VAR5 ;
input VAR9 ;
input VAR13;
input VAR12;
input VAR8 ;
input VAR1 ;
wire VAR16 ;
wire VAR10 ;
wire VAR2;
and VAR4 (VAR16 , VAR17, VAR11 );
nor VAR6 (VAR10 , VAR16, VAR5, VAR9 );
VAR7 ... | apache-2.0 |
tgiv014/ECE441_Proj3 | bcd_ctr.v | 2,076 | module MODULE1(clk, en, VAR2, VAR7, VAR3, VAR5);
input clk, VAR2, en;
output reg [3:0] VAR7, VAR3, VAR5;
wire VAR6, VAR1, VAR4;
assign VAR6 = (VAR7 == 4'd9); assign VAR1 = VAR6&(VAR3 == 4'd9); assign VAR4 = VAR1&(VAR5 == 4'd9);
always @ (posedge clk or negedge VAR2)
begin
if(~VAR2) begin
VAR7 <= 4'd0;
VAR3 <= 4'd0;
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o_4.v | 2,212 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR4,
VAR2
);
output VAR8 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR4;
input VAR2;
VAR9 VAR5 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8 ,
VAR6,
VAR7,
VAR1,
VAR3
);... | apache-2.0 |
mashanz/FinalProject | Code/module/alu_8bit_min.v | 1,180 | module MODULE1( reset, VAR4, enable, VAR8, VAR7, VAR3, VAR6, VAR9, VAR2);
input reset, VAR4, enable;
output VAR2;
input [1:0]VAR8;
input [7:0]VAR3,VAR6;
input [7:0]VAR9;
output [7:0]VAR7;
reg [7:0]VAR7;
integer VAR1;
begin
case(VAR9)
8'b00000000:
begin
end
8'b00000001: VAR7 <= VAR3-VAR6;
8'b00000010:
begin
VAR5=VAR3;
... | gpl-3.0 |
lvd2/zxevo | fpga/sdload/trunk/common/resetter.v | 1,976 | module MODULE1(
clk,
VAR1,
VAR4 );
parameter VAR3 = 4;
input clk;
input VAR1;
output VAR4; reg VAR4;
reg [VAR3:0] VAR5;
reg VAR2,VAR6;
begin
begin
begin | gpl-3.0 |
bunnie/novena-gpbb-fpga | novena-gpbb.srcs/sources_1/ip/dcm_delay/dcm_delay/example_design/dcm_delay_exdes.v | 6,762 | module MODULE1
parameter VAR36 = 100
)
( input VAR37,
input VAR5,
output [4:1] VAR11,
output [4:1] VAR19,
input VAR27,
output VAR2
);
localparam VAR7 = 16;
localparam VAR9 = 4;
genvar VAR41;
wire VAR16 = !VAR2 || VAR27 || VAR5;
reg [VAR9:1] VAR32;
reg [VAR9:1] VAR23;
reg [VAR9:1] VAR26;
reg [VAR9:1] VAR6;
wire VAR34;
w... | apache-2.0 |
airabinovich/finalArquitectura | ALU/ALU/ALU.v | 1,471 | module MODULE1 #(parameter VAR1=32)(
input [3:0] VAR4,
input signed [VAR1-1:0] VAR5,
input signed [VAR1-1:0] VAR7,
output reg signed [VAR1-1:0] VAR3,
output reg VAR6,
output reg VAR2
);
always @(*) begin
case(VAR4)
0: {VAR2,VAR3} = VAR5 << VAR7[4:0]; 1: {VAR2,VAR3} = VAR5 >> VAR7[4:0]; 2: {VAR2,VAR3} = VAR5 >>> VAR7[4:... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbn/sky130_fd_sc_ls__dfbbn.symbol.v | 1,485 | module MODULE1 (
input VAR5 ,
output VAR4 ,
output VAR10 ,
input VAR3,
input VAR2 ,
input VAR8
);
supply1 VAR9;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv_2.v | 2,003 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR7,
VAR5,
VAR2 ,
VAR3
);
output VAR6 ;
input VAR1 ;
input VAR7;
input VAR5;
input VAR2 ;
input VAR3 ;
VAR8 VAR4 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR7;
supply0 VAR5;... | apache-2.0 |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_altpll_0.v | 10,927 | module MODULE1
(
VAR7,
VAR10,
VAR5,
VAR2) ;
input VAR7;
input VAR10;
input [0:0] VAR5;
output [0:0] VAR2;
tri0 VAR7;
tri1 VAR10;
reg [0:0] VAR6;
reg [0:0] VAR1;
reg [0:0] VAR8;
wire VAR4;
wire VAR9;
wire VAR3; | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv_4.v | 2,036 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR3,
VAR8,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR6 ;
input VAR3;
input VAR8;
input VAR2 ;
input VAR4 ;
VAR7 VAR5 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR1,
VAR6
);
output VAR1;
input VAR6;
supply1 VAR3;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a.behavioral.v | 1,555 | module MODULE1 (
VAR3 ,
VAR10,
VAR7,
VAR13,
VAR2,
VAR6
);
output VAR3 ;
input VAR10;
input VAR7;
input VAR13;
input VAR2;
input VAR6;
supply1 VAR12;
supply0 VAR9;
supply1 VAR15 ;
supply0 VAR11 ;
wire VAR1 ;
wire VAR8;
or VAR5 (VAR1 , VAR7, VAR10, VAR13 );
and VAR4 (VAR8, VAR1, VAR2, VAR6);
buf VAR14 (VAR3 , VAR8 );
end... | apache-2.0 |
Rmin1995/NoC | priority_vc_inputs.v | 3,200 | module MODULE1(
output [0:VAR25-1] VAR21,
output [0:VAR25-1] VAR11,
output [1:VAR6 * VAR25] VAR29,
output [0:VAR25-1] VAR18,
output [0:VAR16*VAR25-1] VAR30,
input [0:VAR25-1] VAR27,
input [0:VAR25-1] VAR19,
input [0:VAR25-1] VAR7,
input [0:VAR25 - 1] VAR4,
input [1:VAR6 * VAR25] VAR26,
input [0:VAR6 * VAR25 - 1] VAR9,
... | gpl-3.0 |
drichmond/riffa | fpga/riffa_hdl/tx_port_channel_gate_128.v | 8,562 | module MODULE1
parameter VAR11 = 8,
parameter VAR18 = VAR4 + 1)
(input VAR1,
input VAR2, output [VAR18-1:0] VAR30, output VAR34, input VAR31,
input VAR20, input VAR24, output VAR6, input VAR41, input [31:0] VAR16, input [30:0] VAR42, input [VAR4-1:0] VAR10, input VAR15, output VAR12);
reg [1:0] VAR7=VAR36, VAR7=VAR36;
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3.behavioral.pp.v | 1,733 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR4,
VAR1
);
output VAR7 ;
input VAR8 ;
input VAR4;
input VAR1;
wire VAR3 ;
wire VAR6;
buf VAR5 (VAR3 , VAR8 );
VAR10 VAR9 (VAR6, VAR3, VAR4, VAR1);
buf VAR2 (VAR7 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111oi/sky130_fd_sc_hd__a2111oi_2.v | 2,461 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR8 ,
VAR2 ,
VAR11 ,
VAR7 ,
VAR9,
VAR10,
VAR5 ,
VAR6
);
output VAR1 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR11 ;
input VAR7 ;
input VAR9;
input VAR10;
input VAR5 ;
input VAR6 ;
VAR3 VAR12 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR9(VA... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_mini/address.v | 1,660 | module MODULE1(
input VAR10,
input [23:0] VAR3, input VAR7, output [23:0] VAR9, output VAR1, output VAR8, output VAR2, input [23:0] VAR6,
input [23:0] VAR5
);
wire [23:0] VAR4;
assign VAR2 = ~VAR7;
assign VAR8 = (!VAR3[22]
& &VAR3[21:20]
& &VAR3[14:13]
& !VAR3[15]
);
assign VAR4 = (VAR8
? 24'hFF0000 + ((VAR3[14:0] - 15... | gpl-2.0 |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkD_MMU_Cache.v | 87,078 | module MODULE1(VAR124,
VAR267,
VAR299,
VAR18,
VAR318,
VAR191,
VAR287,
VAR322,
VAR59,
VAR306,
VAR154,
VAR425,
valid,
addr,
VAR439,
VAR339,
VAR360,
VAR442,
VAR54,
VAR263,
VAR254,
VAR117,
VAR157,
VAR176,
VAR435,
VAR123,
VAR101,
VAR349,
VAR232,
VAR363,
VAR209,
VAR405,
VAR95,
VAR172,
VAR245,
VAR481,
VAR37,
VAR21,
VAR169,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai_4.v | 2,457 | module MODULE2 (
VAR1 ,
VAR10 ,
VAR7 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR9,
VAR2,
VAR12 ,
VAR4
);
output VAR1 ;
input VAR10 ;
input VAR7 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR9;
input VAR2;
input VAR12 ;
input VAR4 ;
VAR3 VAR11 (
.VAR1(VAR1),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR9(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.v | 2,358 | module MODULE2 (
VAR7 ,
VAR9,
VAR1 ,
VAR3 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR9;
input VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR4 ;
input VAR6 ;
VAR8 VAR10 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_charReceived.v | 3,575 | module MODULE1 (
address,
VAR15,
clk,
VAR11,
VAR8,
VAR13,
VAR12,
irq,
VAR3
)
;
output irq;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR15;
input clk;
input VAR11;
input VAR8;
input VAR13;
input [ 31: 0] VAR12;
wire VAR5;
reg VAR2;
reg VAR4;
wire VAR9;
reg VAR14;
wire VAR6;
wire VAR7;
wire irq;
reg VAR10;
wire... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/axi_ipif/counter_f.v | 6,839 | module MODULE1 (VAR9, VAR2, VAR4, VAR5, VAR14, VAR3,
VAR12, VAR7);
parameter VAR8 = 9;
parameter VAR10 = "VAR15";
input VAR9;
input VAR2;
input[VAR8 - 1:0] VAR4;
input VAR5;
input VAR14;
input VAR3;
output[VAR8 - 1:0] VAR12;
wire[VAR8 - 1:0] VAR12;
output VAR7;
wire VAR7;
reg[VAR8:0] VAR1;
wire[VAR8:0] VAR13;
wire[VAR8... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai_4.v | 2,424 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR5 ,
VAR9 ,
VAR10 ,
VAR2 ,
VAR3,
VAR7,
VAR12 ,
VAR8
);
output VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR2 ;
input VAR3;
input VAR7;
input VAR12 ;
input VAR8 ;
VAR1 VAR11 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.functional.v | 1,585 | module MODULE1( VAR8, VAR13, VAR14, VAR9, VAR6 );
input VAR14, VAR13, VAR9, VAR6;
output VAR8;
wire VAR18;
not VAR11( VAR18, VAR14 );
wire VAR17;
not VAR16( VAR17, VAR9 );
wire VAR2;
not VAR7( VAR2, VAR6 );
wire VAR12;
and VAR4( VAR12, VAR18, VAR17, VAR2 );
wire VAR5;
not VAR10( VAR5, VAR13 );
wire VAR1;
and VAR15( VAR... | apache-2.0 |
sirchuckalot/zet | cores/fmlbrg/rtl/fmlbrg_tagmem.v | 1,525 | module MODULE1 #(
parameter VAR9 = 2,
parameter VAR6 = 2
) (
input VAR5,
input [VAR9-1:0] VAR1,
input VAR7,
input [VAR6-1:0] VAR11,
output [VAR6-1:0] dout,
input [VAR9-1:0] VAR2,
output [VAR6-1:0] VAR3
);
reg [VAR6-1:0] VAR12[0:(1 << VAR9)-1];
reg [VAR9-1:0] VAR4;
reg [VAR9-1:0] VAR10;
always @(posedge VAR5) begin
VAR4... | gpl-3.0 |
jotego/jt51 | hdl/jt51_reg.v | 8,365 | module MODULE1(
input rst,
input clk,
input VAR46, input [7:0] din,
input VAR66,
input VAR69,
input VAR34,
input VAR51,
input VAR89,
input VAR16,
input VAR79,
input VAR29,
input VAR124,
input VAR115,
input VAR127,
input [1:0] VAR98, input [2:0] VAR106,
input VAR48,
input VAR81,
output [1:0] VAR104,
output [2:0] VAR117,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4b/sky130_fd_sc_lp__nor4b.functional.v | 1,414 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR10 ,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR4;
wire VAR7 ;
wire VAR9;
not VAR8 (VAR7 , VAR4 );
nor VAR2 (VAR9, VAR6, VAR10, VAR1, VAR7);
buf VAR3 (VAR5 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp.functional.v | 1,642 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR10 ,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR10 ;
input VAR6;
wire VAR2;
wire VAR9;
not VAR5 (VAR9 , VAR6 );
VAR11 VAR7 VAR8 (VAR2 , VAR10, VAR3, VAR9 );
buf VAR1 (VAR4 , VAR2 );
endmodule | apache-2.0 |
theapi/de0-nano | text/text2_export.v | 1,950 | module MODULE1(
VAR19,
VAR22,
VAR2,
VAR18,
VAR10,
VAR23,
VAR8
);
input wire VAR19;
input wire VAR22;
output wire VAR2;
output wire VAR18;
output wire VAR10;
output wire VAR23;
output wire VAR8;
wire [10:0] VAR20;
wire [10:0] VAR11;
wire VAR7;
wire VAR5;
wire [2:0] VAR25;
assign VAR7 = ~VAR19;
VAR3 VAR6(
.clk(VAR22),
.V... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_INVBUF_LVT_FF_210930.v | 14,913 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
buf (VAR2, VAR1); | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.functional.v | 1,494 | module MODULE1( VAR12, VAR2, VAR3, VAR1, VAR8 );
input VAR8, VAR1, VAR3, VAR12;
output VAR2;
wire VAR14;
not VAR10( VAR14, VAR8 );
wire VAR9;
not VAR4( VAR9, VAR1 );
wire VAR7;
and VAR15( VAR7, VAR14, VAR9 );
wire VAR11;
not VAR18( VAR11, VAR3 );
wire VAR17;
not VAR16( VAR17, VAR12 );
wire VAR5;
and VAR6( VAR5, VAR11, ... | apache-2.0 |
lvd2/ngs | fpga/obsolete/fpgaE_dma/zxbus/zxbus.v | 10,782 | module MODULE1(
VAR52, VAR62, VAR9,VAR53, VAR36,VAR55, VAR25,VAR28, VAR31, VAR15, VAR27, VAR2, VAR30, VAR58,
VAR45,
VAR42, VAR24,
VAR10, VAR61,
VAR17, VAR32,
VAR7, VAR49,
VAR33,
VAR12,
VAR40, VAR26,
VAR34, VAR43,
VAR19, VAR1,
VAR23,
VAR18,
VAR14
);
parameter VAR5 = 2;
localparam VAR51 = 8'hBB;
localparam VAR3 = VAR51;
... | gpl-3.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/hpdmc_mgmt.v | 9,127 | module MODULE1 #(
parameter VAR29 = 26,
parameter VAR20 = 9
) (
input VAR52,
input VAR7,
input [2:0] VAR26,
input [2:0] VAR48,
input [10:0] VAR32,
input [3:0] VAR44,
input VAR31,
input VAR14,
input [VAR29-3-1:0] address,
output reg ack,
output reg read,
output reg write,
output [3:0] VAR4,
input VAR25,
input VAR22,
inp... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbp/sky130_fd_sc_lp__dfbbp.behavioral.pp.v | 2,712 | module MODULE1 (
VAR7 ,
VAR22 ,
VAR8 ,
VAR4 ,
VAR1 ,
VAR28,
VAR14 ,
VAR15 ,
VAR16 ,
VAR11
);
output VAR7 ;
output VAR22 ;
input VAR8 ;
input VAR4 ;
input VAR1 ;
input VAR28;
input VAR14 ;
input VAR15 ;
input VAR16 ;
input VAR11 ;
wire VAR13 ;
wire VAR5 ;
wire VAR24 ;
wire VAR25 ;
wire VAR9;
wire VAR21 ;
reg VAR26 ;
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_mux_2to1/sky130_fd_sc_hs__udp_mux_2to1.blackbox.v | 1,204 | module MODULE1 (
VAR1 ,
VAR3,
VAR2,
VAR4
);
output VAR1 ;
input VAR3;
input VAR2;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf.functional.v | 1,249 | module MODULE1 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
wire VAR1;
buf VAR4 (VAR1, VAR2 );
buf VAR5 (VAR3 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ebufn/sky130_fd_sc_hd__ebufn.symbol.v | 1,333 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR7
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_dc_tag.v | 4,447 | module MODULE1(
clk, rst,
VAR13, VAR17, VAR1,
addr, en, VAR12, VAR5, VAR6, VAR7, VAR9
);
parameter VAR18 = VAR16+1;
parameter VAR10 = VAR14;
input clk;
input rst;
input [VAR10-1:0] addr;
input en;
input VAR12;
input [VAR18-1:0] VAR5;
output VAR6;
output [VAR18-3:0] VAR7;
output VAR9;
input VAR13;
input [VAR3 - 1:0] VAR... | mit |
nliu96/openHMC_Altera | src/rx_lane_logic.v | 5,404 | module MODULE1 #(
parameter VAR8 = 512,
parameter VAR3 = 8,
parameter VAR1 = (VAR8/VAR3),
parameter VAR10 = 1,
parameter VAR6= 1
) (
input wire clk,
input wire VAR18,
input wire [VAR1-1:0] VAR2,
input wire VAR11, input wire VAR17,
output wire [VAR1-1:0] VAR21,
output wire VAR14,
input wire VAR16
);
wire [VAR1-1:0] VAR1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2.behavioral.pp.v | 1,867 | module MODULE1 (
VAR12 ,
VAR10 ,
VAR1,
VAR8,
VAR3 ,
VAR6
);
output VAR12 ;
input VAR10 ;
input VAR1;
input VAR8;
input VAR3 ;
input VAR6 ;
wire VAR4 ;
wire VAR7;
not VAR5 (VAR4 , VAR10 );
VAR11 VAR9 (VAR7, VAR4, VAR1, VAR8);
buf VAR2 (VAR12 , VAR7 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/tlu/rtl/tlu_pib.v | 66,225 | module MODULE1 (
VAR18, VAR68, VAR47,
VAR205, VAR92, VAR115, VAR33, VAR67,
VAR132, VAR302,
VAR88, VAR303, VAR272,
VAR51, VAR173, VAR243, VAR254, VAR169,
VAR187, VAR171, VAR178,
VAR210, VAR190, VAR12,
VAR239, VAR294, VAR125, VAR193, VAR184,
VAR52, VAR172, VAR310, VAR110,
VAR281, VAR36, VAR240,
VAR288, VAR195, VAR11, VAR... | gpl-2.0 |
bigeagle/riffa | fpga/altera/de5_qsys/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v | 18,177 | module MODULE1
parameter VAR20 = 8,
parameter VAR90 = 64,
parameter VAR140 = 256,
parameter VAR163 = 5
)
(
output [7:0] VAR39,
input VAR43,
input VAR197,
input [VAR20-1:0] VAR170,
output [VAR20-1:0] VAR95,
input VAR27
);
wire VAR136;
wire VAR74;
wire [3:0] VAR40;
wire [31:0] VAR12;
wire [52:0] VAR19;
wire [0:0] VAR50;
... | bsd-3-clause |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/niosii/synthesis/submodules/niosii_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,143 | module MODULE1 (
clk,
VAR11,
VAR15,
VAR10,
VAR19,
VAR28,
VAR8,
VAR22,
VAR14,
VAR16,
VAR2,
VAR25,
VAR30,
VAR24,
VAR27,
VAR20
)
;
output [ 37: 0] VAR28;
output VAR8;
output VAR22;
output VAR14;
output VAR16;
output VAR2;
output VAR25;
output VAR30;
output VAR24;
output VAR27;
output VAR20;
input clk;
input [ 1: 0] VAR11;... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_03_a/hdl/verilog/spi_shift.v | 5,993 | module MODULE1 (clk, rst, VAR4, VAR1, VAR11,
posedge, negedge, VAR9, VAR18,
VAR10, VAR13,
VAR16, VAR5, VAR17, VAR15);
parameter VAR19 = 1;
input clk; input rst; input [VAR8-1:0] VAR4; input VAR1; input VAR11; input posedge; input negedge; input VAR9; input VAR18; output VAR10; output VAR13; input [17:0] VAR16; output [... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv.behavioral.v | 1,321 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR8;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR9 ;
wire VAR2;
not VAR5 (VAR2, VAR3 );
buf VAR7 (VAR1 , VAR2 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_impctl_ddr_dnrcn.v | 3,088 | module MODULE1(VAR7 ,VAR41 ,VAR30 ,VAR2 ,VAR47 ,VAR42 ,VAR24 ,VAR9 ,
clk ,VAR22 ,VAR21 );
input [8:1] VAR30 ;
output VAR2 ;
output VAR47 ;
output VAR9 ;
input VAR7 ;
input VAR41 ;
input VAR42 ;
input VAR24 ;
input clk ;
input VAR22 ;
input VAR21 ;
supply0 VAR10 ;
wire VAR20 ;
wire VAR14 ;
wire VAR28 ;
wire VAR38 ;
wire... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah.pp.blackbox.v | 1,308 | module MODULE1 (
VAR6,
VAR2 ,
VAR9 ,
VAR8 ,
VAR3 ,
VAR4,
VAR1,
VAR5 ,
VAR7
);
output VAR6;
output VAR2 ;
input VAR9 ;
input VAR8 ;
input VAR3 ;
input VAR4;
input VAR1;
input VAR5 ;
input VAR7 ;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/hls_saturation_enhance.v | 38,537 | module MODULE1 (
VAR302,
VAR135,
VAR290,
VAR12,
VAR365,
VAR295,
VAR361,
VAR415,
VAR372,
VAR54,
VAR142,
VAR264,
VAR433,
VAR348,
VAR106,
VAR153,
VAR235,
VAR226,
VAR18,
VAR210,
VAR218,
VAR63,
VAR434,
VAR187,
VAR94,
VAR170,
VAR397,
VAR113,
VAR241,
VAR378,
VAR57,
VAR122,
VAR197,
VAR150,
VAR141,
VAR303,
VAR337
);
parameter V... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_011.v | 1,496 | module MODULE2 (
VAR6,
VAR9
);
input [31:0] VAR6;
output [31:0]
VAR9;
wire [31:0]
VAR2,
VAR8,
VAR10,
VAR11,
VAR13,
VAR3,
VAR5,
VAR1;
assign VAR2 = VAR6;
assign VAR3 = VAR13 << 2;
assign VAR11 = VAR2 << 11;
assign VAR13 = VAR10 + VAR11;
assign VAR1 = VAR5 << 2;
assign VAR10 = VAR8 - VAR2;
assign VAR8 = VAR2 << 9;
assign... | mit |
jedimatt42/pi-messaging | hardware/tipi-speech/ise/crubits.v | 1,304 | module MODULE1(
input [0:3]VAR4,
input VAR5,
input VAR10,
input VAR2,
input [0:14]addr,
input VAR8,
output VAR6,
output [0:3]VAR3
);
reg [0:3] VAR7;
always @(negedge VAR5) begin
if ((addr[0:3] == 4'b0001) && (addr[4:7] == VAR4)) begin
if (addr[8:14] == 7'h00) VAR7[0] <= VAR8;
end
else if (addr[8:14] == 7'h01) VAR7[1] <... | gpl-3.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/ovl_always_on_edge.v | 2,569 | module MODULE1 (VAR27, reset, enable, VAR24, VAR26, VAR14, VAR19);
parameter VAR4 = VAR7;
parameter VAR5 = VAR9;
parameter VAR13 = VAR20;
parameter VAR23 = VAR17;
parameter VAR6 = VAR1;
parameter VAR16 = VAR21;
parameter VAR10 = VAR11;
parameter VAR15 = VAR25;
input VAR27, reset, enable;
input VAR24, VAR26;
output [VAR... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ecc_gen.v | 7,915 | module MODULE1
parameter VAR2 = 72,
parameter VAR8 = 8,
parameter VAR1 = 64
)
(
VAR22
);
function integer VAR20 (input integer VAR7);
integer VAR6;
if (VAR7 == 1) VAR20 = 1;
else begin
VAR20 = 1;
for (VAR6=2; VAR6<=VAR7; VAR6=VAR6+1)
VAR20 = VAR20 * VAR6;
end
endfunction
function integer VAR16 (input integer VAR13, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.v | 2,312 | module MODULE2 (
VAR9 ,
VAR8 ,
VAR4 ,
VAR2,
VAR1 ,
VAR3 ,
VAR6 ,
VAR10
);
output VAR9 ;
output VAR8 ;
input VAR4 ;
input VAR2;
input VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR10 ;
VAR5 VAR7 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10)
);
endmodule
module MOD... | apache-2.0 |
johngtimms/parallel-accumulator | accumulator_processor.v | 2,840 | module MODULE1 (clk, reset, VAR3, VAR6, read, write, req, VAR22, state);
input clk, reset, VAR6, VAR22;
input [1:0] VAR3;
input [31:0] read;
output [31:0] write;
output req;
output [6:0] state;
reg req = 0;
reg [6:0] state;
reg [1:0] VAR8;
reg [31:0] VAR10;
reg [31:0] VAR7;
reg [31:0] VAR16;
integer VAR15 = 0;
integer ... | mit |
titorgalaxy/Titor | rtl/verilog/core/Butterfly_Unit.v | 7,303 | module MODULE2 (
VAR43,
VAR11,
VAR18,
VAR4,
VAR3
);
output reg [VAR17-1:0] VAR43;
input [VAR17-1:0] VAR11;
input [VAR17-1:0] VAR18;
input [VAR17-1:0] VAR4;
input [VAR17-1:0] VAR3;
wire [((VAR17/2)*VAR10)-1:0] VAR2;
wire [((VAR17/2)*VAR10)-1:0] VAR33;
wire [(VAR17/2)-1:0] VAR13 [VAR10-1:0]; wire [(VAR17/2)-1:0] VAR8 [VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_hl_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1.v | 2,501 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR4,
VAR6 ,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR7 ;
input VAR4;
input VAR6 ;
input VAR1 ;
input VAR3 ;
VAR2 VAR8 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR5,
VAR7
);
output VAR5;
input VAR7;
wire VAR4;
supply1 VAR6 ;... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_48.v | 33,176 | module MODULE1 (
clk,
reset,
VAR68,
VAR214,
VAR161,
VAR70,
VAR171
);
parameter VAR194 = 18;
parameter VAR239 = 48;
parameter VAR276 = 24;
localparam VAR138 = 55;
input clk;
input reset;
input VAR68;
input VAR214;
input [VAR194-1:0] VAR161; output VAR70;
output [VAR194-1:0] VAR171;
localparam VAR127 = 18; localparam VAR... | mit |
rurume/openrisc_vision_hardware | ISE/or1200_sopc.v | 2,305 | module MODULE1
(
VAR2, VAR6,
VAR22, VAR18, VAR25, VAR11,
VAR17,
VAR3,
VAR12,
VAR21,
VAR14,
VAR9,
VAR7,
VAR10,
VAR4,
VAR26
);
input [1:0] VAR26;
output [7:0] VAR4;
output VAR7;
output [7:0] VAR10;
input VAR2; input VAR6;
input [17:0] VAR22; output [17:0] VAR18; output VAR25; input VAR11;
input VAR17;
output [31:0] VAR3;... | gpl-2.0 |
bunnie/novena-afe-hs-fpga | novena-afe-hs.srcs/sources_1/imports/imports/adc_rx.v | 3,248 | module MODULE1(
input wire [7:0] VAR20,
input wire [7:0] VAR39,
input wire [7:0] VAR28,
input wire [7:0] VAR15,
input wire VAR31,
input wire VAR13,
output reg [63:0] VAR36,
output reg [63:0] VAR27,
output wire VAR7,
output wire VAR26,
input wire reset
);
wire VAR12;
wire VAR8;
wire VAR6;
wire VAR35;
wire VAR29;
wire [6... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/sfp/triple_speed_ethernet-library/altera_tse_pma_lvds_tx.v | 6,646 | module MODULE1 (
VAR8,
VAR17,
VAR4);
input [9:0] VAR8;
input VAR17;
output [0:0] VAR4;
wire [0:0] VAR24;
wire [0:0] VAR4 = VAR24[0:0];
VAR28 VAR18 (
.VAR8 (VAR8),
.VAR17 (VAR17),
.VAR4 (VAR24),
.VAR13 (1'b0),
.VAR21 (1'b0),
.VAR30 (),
.VAR9 (1'b1),
.VAR15 (),
.VAR3 (),
.VAR6 (1'b1),
.VAR20 (1'b0));
VAR18.VAR22 = "VAR3... | apache-2.0 |
hcabrera-/lancetfish | RTL/processing_element/des_engine/verif/harness.v | 2,491 | module MODULE1();
parameter VAR15 = 100,
VAR8 = 15,
VAR18 = 5;
reg clk;
reg reset;
wire VAR13;
wire [0:63] VAR20;
wire [0:63] VAR7;
wire VAR2;
wire VAR11;
wire [0:63] VAR3;
VAR5 VAR19
(
.clk(clk),
.reset(reset),
.VAR13 (VAR13),
.VAR20 (VAR20),
.VAR7 (VAR7),
.VAR2 (VAR2),
.VAR11 (VAR11),
.VAR3 (VAR3)
);
VAR12
.VAR18(VAR... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9649_v1_00_a/hdl/verilog/cf_dma_wr.v | 16,119 | module MODULE1 (
VAR57,
VAR54,
VAR91,
VAR22,
VAR73,
VAR77,
VAR6,
VAR41,
VAR68,
VAR16,
VAR11,
VAR27,
VAR44,
VAR84,
VAR72,
VAR8,
VAR3,
VAR38);
input VAR57;
input VAR54;
input [63:0] VAR91;
input VAR22;
input VAR73;
output VAR77;
output [63:0] VAR6;
output [ 7:0] VAR41;
output VAR68;
input VAR16;
output VAR11;
output VAR2... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.functional.v | 1,778 | module MODULE1( VAR16, VAR9, VAR11, VAR18, VAR12 );
input VAR12, VAR18, VAR11, VAR16;
output VAR9;
wire VAR8;
not VAR17( VAR8, VAR12 );
wire VAR14;
not VAR10( VAR14, VAR11 );
wire VAR7;
and VAR5( VAR7, VAR8, VAR14 );
wire VAR3;
not VAR22( VAR3, VAR16 );
wire VAR20;
and VAR1( VAR20, VAR8, VAR3 );
wire VAR2;
not VAR13( V... | apache-2.0 |
mwswartwout/EECS318 | hw2/problem2/freecellPlayer.v | 9,846 | module MODULE1(VAR1, VAR7, VAR11, VAR2);
input [3:0] VAR7, VAR11;
input VAR1;
output reg VAR2;
reg [5:0] VAR10[7:0][51:0];
reg [5:0] VAR14[3:0];
reg [5:0] VAR5[3:0][12:0];
reg [5:0] VAR6, VAR3;
reg VAR8, VAR12, VAR16, VAR15, VAR13;
integer VAR9, VAR4;
begin
begin
begin
begin
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.symbol.v | 1,482 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR7 ,
input VAR3 ,
input VAR6,
input VAR1 ,
input VAR4
);
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v | 35,319 | module MODULE1 (
output wire VAR162, input wire VAR164, output wire VAR254, output wire [31:0] VAR216, output wire VAR52, input wire [0:0] VAR132, input wire [31:0] VAR192, input wire [10:0] VAR98, input wire VAR65, input wire VAR59, input wire [3:0] VAR256, input wire VAR118, output wire VAR57, output wire VAR29, inpu... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_2.behavioral.v | 2,754 | module MODULE1( VAR5, VAR17, VAR1, VAR19 );
input VAR1, VAR17, VAR5;
output VAR19;
reg VAR7;
VAR23 VAR9(.VAR5(VAR5),.VAR17(VAR17),.VAR1(VAR1),.VAR19(VAR19),.VAR7(VAR7));
VAR23 VAR3(.VAR5(VAR5),.VAR17(VAR17),.VAR1(VAR1),.VAR19(VAR19),.VAR7(VAR7));
not VAR13(VAR20,VAR17);
not VAR16(VAR15,VAR5);
and VAR2(VAR18,VAR15,VAR20... | apache-2.0 |
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