repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor2/sky130_fd_sc_hd__xor2_1.v | 2,117 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR8 ,
VAR9,
VAR2,
VAR4 ,
VAR7
);
output VAR3 ;
input VAR6 ;
input VAR8 ;
input VAR9;
input VAR2;
input VAR4 ;
input VAR7 ;
VAR1 VAR5 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR6,
VAR8
);
output VAR3;
... | apache-2.0 |
grantae/uart | src/uart_rx.v | 3,720 | module MODULE1(
input VAR17,
input reset,
input VAR10,
input VAR12,
output reg [7:0] VAR4 = 0,
output VAR19
);
reg [1:0] VAR1 = 2'b11;
always @(posedge VAR17) begin
VAR1 <= (VAR10) ? {VAR1[0], VAR12} : VAR1;
end
reg [1:0] VAR3 = 2'b00;
reg VAR22 = 1'b1;
always @(posedge VAR17) begin
if (VAR10) begin
case (VAR1[1])
1'b0... | mit |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/cpc_core.v | 10,802 | module MODULE1 (
input VAR124,
input VAR10,
input VAR22,
input VAR43,
output VAR36,
input VAR178,
input VAR177,
input [15:0] VAR65,
output [7:0] VAR114,
output [15:0] VAR128,
input [79:0] VAR171,
output [7:0] VAR134,
input [7:0] VAR153,
output [7:0] VAR70,
output [23:0] VAR39,
output VAR141,
output VAR77,
output VAR182... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o.pp.blackbox.v | 1,383 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR1 ,
VAR2 ,
VAR8 ,
VAR7,
VAR9,
VAR4 ,
VAR6
);
output VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR8 ;
input VAR7;
input VAR9;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ai/sky130_fd_sc_hdll__o21ai_2.v | 2,277 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR10 ,
VAR6 ,
VAR5,
VAR4,
VAR7 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR10 ;
input VAR6 ;
input VAR5;
input VAR4;
input VAR7 ;
input VAR1 ;
VAR8 VAR9 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/dac_buf.v | 9,127 | module MODULE1 (
VAR43,
VAR14,
VAR34,
VAR33,
VAR23,
VAR52);
input VAR43;
input [7:0] VAR14;
input [8:0] VAR34;
input [10:0] VAR33;
input VAR23;
output [31:0] VAR52;
tri1 VAR43;
tri0 VAR23;
wire [31:0] VAR38;
wire [31:0] VAR52 = VAR38[31:0];
VAR47 VAR46 (
.VAR37 (VAR33),
.VAR4 (VAR34),
.VAR31 (VAR43),
.VAR45 (VAR14),
.V... | gpl-2.0 |
545/Atari7800 | core/ag_6502/trunk/agat7/ag_video.v | 4,565 | module MODULE1(input[10:0] VAR1, input VAR5, output[7:0] VAR4);
reg[7:0] VAR2[0:2047];
assign VAR4 = VAR5?VAR2[VAR1]:8'VAR3; | gpl-2.0 |
theapi/de1-soc | vga/rtl/verilog/vga_controller.v | 2,109 | module MODULE1(
input reset,
input VAR11,
input VAR22,
output VAR13,
output VAR30,
output VAR15,
output [7:0] VAR21,
output [7:0] VAR3,
output [7:0] VAR23
);
wire [10:0] VAR2;
wire [10:0] VAR4;
reg [7:0] VAR27;
reg [7:0] VAR9;
reg [7:0] VAR24;
wire [7:0] VAR5;
wire [23:0] VAR17;
reg [18:0] VAR28;
wire [31:0] VAR25;
VAR... | mit |
JohnDMcMaster/proxmark3 | fpga/fpga.v | 7,821 | module MODULE1(
VAR39, VAR27, VAR65, VAR105,
VAR57, VAR12, VAR93,
VAR111, VAR96, VAR70, VAR125, VAR13, VAR58,
VAR22, VAR43, VAR86,
VAR36, VAR44, VAR2, VAR24,
VAR67, VAR107,
VAR55
);
input VAR39, VAR65, VAR105;
output VAR27;
input VAR57, VAR12, VAR93;
output VAR111, VAR96, VAR70, VAR125, VAR13, VAR58;
input [7:0] VAR22;... | gpl-2.0 |
Rod2693rm/netfpga-firewal-ddos | src/tcam/tcam_usr.v | 4,031 | module MODULE1(
clk,
VAR22,
VAR40,
VAR36,
din,
VAR32,
VAR38,
VAR24,
VAR25,
VAR26);
input clk;
input [31 : 0] VAR22;
input [31 : 0] VAR40;
input [31 : 0] VAR36;
input [31 : 0] din;
input VAR32;
input [10 : 0] VAR38;
output VAR24;
output VAR25;
output [2047 : 0] VAR26;
VAR11 #(
.VAR18(2),
.VAR14(32),
.VAR45(32),
.VAR12(3... | gpl-3.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/altera_up_video_alpha_blender_normal.v | 9,997 | module MODULE1 (
VAR13,
VAR20,
VAR21,
VAR7,
VAR4
);
input [29: 0] VAR13;
input [39: 0] VAR20;
output [ 9: 0] VAR21;
output [ 9: 0] VAR7;
output [ 9: 0] VAR4;
wire [ 9: 0] VAR30;
wire [17: 0] VAR27;
wire [17: 0] VAR2;
wire [17: 0] VAR33;
wire [17: 0] VAR23;
wire [17: 0] VAR17;
wire [17: 0] VAR28;
assign VAR21 = {1'b0, V... | gpl-2.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkAXI4_Deburster_A.v | 48,625 | module MODULE1(VAR219,
VAR128,
VAR183,
VAR276,
VAR251,
VAR226,
VAR123,
VAR184,
VAR281,
VAR234,
VAR102,
VAR6,
VAR38,
VAR268,
VAR31,
VAR107,
VAR127,
VAR28,
VAR255,
VAR34,
VAR8,
VAR51,
VAR267,
VAR296,
VAR273,
VAR87,
VAR86,
VAR242,
VAR35,
VAR54,
VAR64,
VAR129,
VAR101,
VAR149,
VAR118,
VAR282,
VAR230,
VAR178,
VAR142,
VAR252,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2b/sky130_fd_sc_ms__nor2b_2.v | 2,173 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR5 ,
VAR2,
VAR1,
VAR9 ,
VAR6
);
output VAR4 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR9 ;
input VAR6 ;
VAR3 VAR7 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR4 ,
VAR8 ,
VAR5
);
output VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlxtn/sky130_fd_sc_hdll__dlxtn_1.v | 2,220 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR9,
VAR7 ,
VAR3 ,
VAR4 ,
VAR6
);
output VAR5 ;
input VAR8 ;
input VAR9;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR6 ;
VAR2 VAR1 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR5 ,
VAR8 ,
VAR9
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor3/sky130_fd_sc_lp__xnor3.blackbox.v | 1,269 | module MODULE1 (
VAR4,
VAR6,
VAR7,
VAR1
);
output VAR4;
input VAR6;
input VAR7;
input VAR1;
supply1 VAR3;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
c4puter/bridge-hdl | modules/flipflop/flipflop.v | 2,096 | module MODULE1 (
input VAR5,
input VAR1,
input clk,
output VAR2,
input VAR3
);
parameter VAR6 = 0;
reg VAR4;
assign VAR2 = VAR4;
always @(VAR3 or posedge clk)
if (VAR3)
VAR4 <= 0;
else if (VAR1)
VAR4 <= VAR5; | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/mux4.v | 1,036 | module MODULE1
(input en,
input [1:0] sel,
input [VAR3-1:0] VAR7,
input [VAR3-1:0] VAR1,
input [VAR3-1:0] VAR4,
input [VAR3-1:0] VAR2,
output [VAR3-1:0] VAR6);
assign VAR6 = en ? (sel[1] ? (sel[0] ? VAR2 : VAR4) : (sel[0] ? VAR1 : VAR7)) :
VAR5;
endmodule | gpl-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_ceil.v | 7,842 | module MODULE1(VAR19, VAR5, enable, VAR10, VAR8);
input VAR19, VAR5, enable;
input [31:0] VAR10;
output [31:0] VAR8;
reg VAR11;
reg [7:0] VAR12;
reg [22:0] VAR13;
always@(posedge VAR19 or negedge VAR5)
begin
if (~VAR5)
begin
VAR11 <= 1'b0;
VAR12 <= 8'd0;
VAR13 <= 23'd0;
end
else if (enable)
begin
VAR11 <= VAR10[31];
VA... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/sg_list_reader_32.v | 5,594 | module MODULE1 #(
parameter VAR12 = 9'd32
)
(
input VAR19,
input VAR4,
input [VAR12-1:0] VAR17, input VAR2, output VAR23,
output VAR15, output VAR11, input VAR9, output [63:0] VAR6, output [31:0] VAR5 );
reg [2:0] VAR16=VAR3, VAR16=VAR3;
reg [2:0] VAR10=VAR27, VAR10=VAR27;
reg [VAR12-1:0] VAR25={VAR12{1'd0}}, VAR25={VA... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/synth/OpenSSD2_Tiger4NSC_1_0.v | 14,564 | module MODULE1 (
VAR27,
VAR36,
VAR69,
VAR5,
VAR23,
VAR80,
VAR14,
VAR85,
VAR29,
VAR76,
VAR63,
VAR48,
VAR37,
VAR67,
VAR28,
VAR38,
VAR65,
VAR79,
VAR20,
VAR25,
VAR51,
VAR77,
VAR32,
VAR52,
VAR55,
VAR88,
VAR50,
VAR53,
VAR47,
VAR61,
VAR56,
VAR72,
VAR71,
VAR58,
VAR8,
VAR39,
VAR4,
VAR92,
VAR68,
VAR91,
VAR35,
VAR89,
VAR33,
VAR7,... | gpl-3.0 |
wamgoo/FPGA-Imaging-Library | Geometry/Crop/HDL/Crop.srcs/sources_1/new/Crop.v | 4,862 | module MODULE1(
clk,
VAR22,
VAR3,
VAR9,
VAR20,
VAR10,
VAR12,
VAR6,
VAR24,
VAR21,
VAR11,
VAR19,
VAR2,
VAR7);
parameter VAR25 = 0;
parameter VAR8 = 8;
parameter VAR5 = 320;
parameter VAR16 = 240;
parameter VAR4 = 9;
input clk;
input VAR22;
input[VAR4 - 1 : 0] VAR3;
input[VAR4 - 1 : 0] VAR9;
input[VAR4 - 1 : 0] VAR20;
inp... | lgpl-2.1 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostController/sendpacketarbiter.v | 6,359 | module MODULE1 (VAR14, VAR22, VAR7, VAR5, VAR9, VAR4, VAR1, clk, rst, VAR3, VAR19);
input VAR22;
input [3:0] VAR7;
input VAR5;
input VAR4;
input VAR1;
input clk;
input rst;
output VAR14;
output VAR9;
output [3:0] VAR3;
output VAR19;
reg VAR14, VAR10;
wire VAR22;
wire [3:0] VAR7;
wire VAR5;
reg VAR9, VAR15;
wire VAR4;
w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi_2.v | 2,352 | module MODULE1 (
VAR11 ,
VAR1 ,
VAR4 ,
VAR10 ,
VAR7 ,
VAR5,
VAR6,
VAR3 ,
VAR9
);
output VAR11 ;
input VAR1 ;
input VAR4 ;
input VAR10 ;
input VAR7 ;
input VAR5;
input VAR6;
input VAR3 ;
input VAR9 ;
VAR2 VAR8 (
.VAR11(VAR11),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/up_adc_channel.v | 15,826 | module MODULE1 #(
parameter VAR96 = 6'h01,
parameter VAR74 = 4'h0,
parameter VAR73 = 0,
parameter VAR5 = 0,
parameter VAR15 = 0,
parameter VAR42 = 0) (
input VAR84,
input VAR33,
output VAR79,
output VAR63,
output VAR35,
output VAR91,
output VAR45,
output VAR72,
output [15:0] VAR18,
output [15:0] VAR95,
output [15:0] VA... | mit |
asicguy/gplgpu | hdl/altera_ddr3/alt_ddrx_cmd_queue.v | 37,635 | module MODULE1
VAR14 = 5,
VAR10 = 2,
VAR93 = 2,
VAR73 = 4,
VAR69 = 4,
VAR122 = 16,
VAR85 = 12,
VAR83 = 3,
VAR123 = 2,
VAR11 = 33,
VAR23 = 4,
VAR6 = 1,
VAR43 = 8,
VAR138 = 12,
VAR18 = 2,
VAR16 = 1
)
(
VAR63 ,
VAR44 ,
VAR12 ,
VAR30 ,
VAR1 ,
VAR62 ,
VAR99 ,
VAR132 ,
VAR71 ,
VAR37 ,
VAR127 ,
VAR59,
VAR29,
VAR54,
VAR2,
VAR5... | gpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_LVT_FF_210930.v | 242,182 | module MODULE1 (VAR2, VAR6, VAR4, VAR7, VAR10, VAR11);
output VAR2;
input VAR6, VAR4, VAR7, VAR10, VAR11;
wire VAR12, VAR1, VAR5;
wire VAR13, VAR8, VAR9;
wire VAR3;
not (VAR8, VAR11);
not (VAR13, VAR10);
not (VAR5, VAR7);
and (VAR9, VAR5, VAR13);
not (VAR1, VAR4);
not (VAR12, VAR6);
and (VAR3, VAR12, VAR1, VAR13);
or (... | bsd-3-clause |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Ultrasonico/peripheral.v | 1,467 | module MODULE1(
input clk,
input rst,
input [15:0] din, input VAR3, input [3:0] addr, input rd, input wr, input VAR1,
output reg [15:0] dout );
reg [1:0] VAR6;
wire VAR2 = ~rst ;
wire [15:0] VAR4 ;
wire VAR7 ;
always @(*) begin case (addr)
4'h0: VAR6 = (VAR3 && rd) ? 2'b01 : 2'b00 ; 4'h2: VAR6 = (VAR3 && rd) ? 2'b10 : ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai.behavioral.v | 1,643 | module MODULE1 (
VAR15 ,
VAR16,
VAR8,
VAR6,
VAR17,
VAR12
);
output VAR15 ;
input VAR16;
input VAR8;
input VAR6;
input VAR17;
input VAR12;
supply1 VAR13;
supply0 VAR10;
supply1 VAR1 ;
supply0 VAR3 ;
wire VAR2 ;
wire VAR5 ;
wire VAR7;
nor VAR4 (VAR2 , VAR6, VAR16, VAR8 );
nor VAR14 (VAR5 , VAR17, VAR12 );
or VAR9 (VAR7, ... | apache-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/sdr_lib/rx_chain.v | 3,224 | module MODULE1
(input VAR16,
input reset,
input enable,
input wire [7:0] VAR39,
input VAR43,
input VAR31,
output wire VAR27,
input [6:0] VAR18, input [31:0] VAR6, input VAR1,
input wire [15:0] VAR10,
input wire [15:0] VAR23,
output wire [15:0] VAR13,
output wire [15:0] VAR7,
output wire [15:0] VAR30,output wire [15:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.v | 2,583 | module MODULE2 (
VAR11 ,
VAR12 ,
VAR4 ,
VAR2 ,
VAR8 ,
VAR9,
VAR1 ,
VAR7 ,
VAR5 ,
VAR10
);
output VAR11 ;
input VAR12 ;
input VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR9;
input VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR10 ;
VAR6 VAR3 (
.VAR11(VAR11),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.VA... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | mem/memory_fsm.v | 36,658 | module MODULE1( clk,
rst,
VAR96,
VAR112,
VAR49,
VAR111,
VAR80,
VAR87,
VAR48,
VAR72,
VAR88,
VAR70,
VAR51,
VAR120,
VAR43,
VAR75,
VAR128,
VAR22,
VAR92,
VAR81,
VAR69,
VAR23,
VAR16,
VAR114,
VAR66,
VAR54,
VAR126,
VAR118,
VAR40,
VAR113,
VAR83,
VAR11,
VAR94,
VAR102,
VAR63,
VAR12,
VAR109,
VAR108,
VAR117,
VAR116,
VAR8,
VAR24,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbn/sky130_fd_sc_hs__dfbbn.pp.blackbox.v | 1,416 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR6 ,
VAR5 ,
VAR2,
VAR7 ,
VAR8
);
output VAR4 ;
output VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR5 ;
input VAR2;
input VAR7 ;
input VAR8 ;
endmodule | apache-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/sdr_lib/cordic.v | 4,017 | module MODULE1(VAR1, reset, enable, VAR7, VAR34, VAR4, VAR67, VAR36, VAR29 );
parameter VAR65 = 16;
parameter VAR51 = 16;
input VAR1;
input reset;
input enable;
input [VAR65-1:0] VAR7, VAR34;
output [VAR65-1:0] VAR67, VAR36;
input [VAR51-1:0] VAR4;
output [VAR51-1:0] VAR29;
reg [VAR65+1:0] VAR30,VAR31;
reg [VAR51-2:0] ... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/syn/verilog/image_filter_mul_8ns_6ns_13_3.v | 1,405 | module MODULE2(clk, VAR10, VAR2, VAR13, VAR15);
input clk;
input VAR10;
input[8 - 1 : 0] VAR2; input[6 - 1 : 0] VAR13; output[13 - 1 : 0] VAR15;
reg [8 - 1 : 0] VAR4;
reg [6 - 1 : 0] VAR9;
wire [13 - 1 : 0] VAR11;
reg [13 - 1 : 0] VAR3;
assign VAR15 = VAR3;
assign VAR11 = VAR4 * VAR9;
always @ (posedge clk) begin
if (V... | gpl-3.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/vga_text.v | 1,582 | module MODULE1(
VAR11,
hc,
VAR8,
VAR21,
VAR3,
VAR13,
VAR6,
VAR2,
VAR19
);
input VAR11;
input [9:0] hc;
input [9:0] VAR8;
input [15:0] VAR21;
input [7:0] VAR3;
output [3:0] VAR13;
output [7:0] VAR6;
output [7:0] VAR2;
output [7:0] VAR19;
localparam VAR17 = 144 , VAR20 = 31 , VAR15 = 16, VAR14 = 16;
reg [10:0] VAR10, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18.blackbox.v | 1,288 | module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a_1.v | 2,195 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR2 ,
VAR9 ,
VAR3 ,
VAR7,
VAR8
);
output VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR9 ;
input VAR3 ;
input VAR7;
input VAR8;
VAR6 VAR4 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR5 ,
VAR1,
VAR2,
VAR9,
VAR3
);... | apache-2.0 |
bluespec/Flute | builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkTLB.v | 25,752 | module MODULE1(VAR68,
VAR65,
VAR84,
VAR81,
VAR140,
VAR64,
VAR100,
VAR18,
VAR72,
VAR9,
VAR54,
VAR19,
VAR143,
VAR168,
VAR165);
parameter [0 : 0] VAR149 = 1'b0;
input VAR68;
input VAR65;
input VAR84;
output VAR81;
input [8 : 0] VAR140;
input [19 : 0] VAR64;
output [68 : 0] VAR100;
output VAR18;
input [8 : 0] VAR72;
input ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp_1.v | 2,837 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR14 ,
VAR8 ,
VAR6 ,
VAR12 ,
VAR13 ,
VAR9,
VAR10 ,
VAR2 ,
VAR11 ,
VAR3
);
output VAR1 ;
output VAR7 ;
input VAR14 ;
input VAR8 ;
input VAR6 ;
input VAR12 ;
input VAR13 ;
input VAR9;
input VAR10 ;
input VAR2 ;
input VAR11 ;
input VAR3 ;
VAR4 VAR5 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR14(VAR14),... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/board/SGDMA_dispatcher/csr_block.v | 14,484 | module MODULE1 (
clk,
reset,
VAR4,
VAR18,
VAR12,
VAR32,
VAR37,
VAR28,
VAR17,
VAR8,
VAR19,
VAR36,
VAR20,
VAR16,
VAR45,
VAR46,
VAR2,
VAR22,
VAR3,
VAR48,
VAR47,
VAR44,
VAR33,
VAR7,
VAR14,
VAR41,
VAR35,
VAR15,
VAR34,
VAR31,
VAR29,
VAR5
);
parameter VAR10 = 3;
localparam VAR38 = 3'b001;
input clk;
input reset;
input [31:0] ... | mit |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_sram.v | 29,034 | module MODULE1 #(
parameter VAR70 = 19,
parameter VAR24 = 16,
parameter VAR1 = 2,
parameter VAR37 = 10,
parameter VAR11 = 10,
parameter VAR64 = 10,
parameter VAR13 = 10,
parameter VAR56 = 2,
parameter VAR9 = 0,
parameter VAR52 = 2,
parameter VAR22 = 2,
parameter VAR53 = 1,
parameter VAR59 = 1,
parameter VAR65 = 0,
para... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlxtp/sky130_fd_sc_lp__srdlxtp.functional.v | 1,749 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR7 ,
VAR3
);
output VAR4 ;
input VAR11 ;
input VAR7 ;
input VAR3;
wire VAR10 ;
wire VAR9;
wire VAR6 ;
wire VAR5 ;
wire VAR1 ;
wire VAR13 ;
VAR8 VAR2 VAR14 (VAR10 , VAR11, VAR7, VAR3, VAR5, VAR1, VAR13);
bufif1 VAR12 (VAR4 , VAR10, VAR13 );
endmodule | apache-2.0 |
unihd-cag/openhmc | rtl/hmc_controller/tx/tx_run_length_limiter.v | 6,767 | module MODULE1 #(
parameter VAR4 =64,
parameter VAR12 =4,
parameter VAR16 =85
)
(
input wire clk,
input wire VAR26,
input wire enable,
input wire [VAR4-1:0] VAR21,
output reg [VAR4-1:0] VAR20,
output reg VAR25
);
localparam VAR19 = (VAR4 + VAR12-1)/(VAR12);
localparam VAR18 = VAR4 - (VAR12 * (VAR4/VAR12));
localparam V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4/sky130_fd_sc_hs__or4.functional.pp.v | 1,726 | module MODULE1 (
VAR6,
VAR4,
VAR5 ,
VAR2 ,
VAR12 ,
VAR8 ,
VAR1
);
input VAR6;
input VAR4;
output VAR5 ;
input VAR2 ;
input VAR12 ;
input VAR8 ;
input VAR1 ;
wire VAR11 ;
wire VAR7;
or VAR3 (VAR11 , VAR1, VAR8, VAR12, VAR2 );
VAR10 VAR9 (VAR7, VAR11, VAR6, VAR4);
buf VAR13 (VAR5 , VAR7 );
endmodule | apache-2.0 |
Franderg/CE-4301-Arqui1 | Processor/ControlUnit.v | 4,086 | module MODULE1 (clk,VAR8,VAR2,VAR17,VAR10,VAR25,VAR31,VAR30,VAR1,VAR24,VAR6,VAR14,VAR7,VAR27);
input wire clk;
input [4:0] VAR8;
input [0:0] VAR17;
input [4:0] VAR2;
output reg[0:0] VAR10;
output reg[0:0] VAR25;
output reg[0:0] VAR31;
output reg[0:0] VAR30;
output reg[1:0] VAR1;
output reg[0:0] VAR24;
output reg[0:0] V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlclkp/sky130_fd_sc_hvl__dlclkp.functional.v | 1,547 | module MODULE1 (
VAR8,
VAR7,
VAR2
);
output VAR8;
input VAR7;
input VAR2 ;
wire VAR6 ;
wire VAR9;
not VAR4 (VAR9 , VAR2 );
VAR1 VAR3 (VAR6 , VAR7, VAR9 );
and VAR5 (VAR8 , VAR6, VAR2 );
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v | 13,487 | module MODULE1 (
VAR109,
VAR19,
VAR107,
VAR30,
VAR5,
VAR101,
VAR10,
VAR108,
VAR59,
VAR20,
VAR77,
VAR23,
VAR69,
VAR95,
VAR105,
VAR21,
VAR51,
VAR71,
VAR114,
VAR104,
VAR67,
VAR34,
VAR106,
VAR102,
VAR17,
VAR2,
VAR31,
VAR36,
VAR78,
VAR98,
VAR75,
VAR89,
VAR14,
VAR56,
VAR61,
VAR85,
VAR43,
VAR38,
VAR8,
VAR81,
VAR96,
VAR62,
VAR... | mit |
zeldin/logic16_bitstream | src/normal_clock_domain.v | 4,076 | module MODULE1(
input clk,
input rst,
output VAR7,
input VAR10,
input VAR26,
input VAR13,
output VAR22,
output VAR17,
output VAR35,
output VAR43,
output [7:0] VAR40,
output [15:0] VAR39,
input VAR38,
input VAR24
);
wire [6:0] VAR30;
wire VAR31;
reg [7:0] VAR49;
wire [7:0] VAR46;
VAR29 VAR21
(
.clk(clk),
.rst(rst),
.VAR... | gpl-3.0 |
cr88192/bgbtech_bjx1core | bwjx1c64a/DcTile3.v | 13,227 | module MODULE1(
VAR2, reset,
VAR62, VAR59,
VAR54, VAR12,
VAR31, VAR35,
VAR16,
VAR22, VAR1,
VAR64, VAR25,
VAR11, VAR57,
VAR26
);
input VAR2;
input reset;
input[63:0] VAR54; input[63:0] VAR62; input VAR31; input VAR35; input[4:0] VAR16;
output[63:0] VAR59; output[1:0] VAR12;
input[127:0] VAR22; output[127:0] VAR1; output... | mit |
disaderp/automatic-chainsaw | GPU/VGA.v | 2,628 | module MODULE1 (
input clk,
output reg VAR5, output reg VAR6,
output reg[9:0] VAR8, output reg[9:0] VAR1 );
localparam VAR2 = 1'b0; localparam VAR4 = 1'b1;
reg[9:0] VAR7 = 0; reg[9:0] VAR3 = 0;
always @( posedge clk)
begin
VAR3 <= VAR3 + 1;
case (VAR3)
0: VAR5 <= VAR4;
16: VAR5 <= VAR2;
112: VAR5 <= VAR4;
800: begin
VA... | gpl-3.0 |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_ovc_ctrl.v | 20,888 | module MODULE1
(clk, reset, VAR56, VAR72, VAR86, VAR33, VAR24, VAR51,
VAR41, VAR102, VAR115, VAR35, VAR3, VAR77);
parameter VAR113 = 8;
localparam VAR111 = VAR20(VAR113);
parameter VAR91 = 4;
parameter VAR100 = 2;
parameter VAR69 = 2;
localparam VAR112 = VAR100 * VAR69;
parameter VAR83 = 1;
localparam VAR59 = VAR112 * ... | mit |
asicguy/gplgpu | hdl/altera_project/dpram_64_32x32/dpram_64_32x32.v | 8,708 | module MODULE1 (
VAR46,
VAR21,
VAR50,
VAR30,
VAR41,
VAR18,
VAR19);
input [31:0] VAR46;
input VAR21;
input [4:0] VAR50;
input [3:0] VAR30;
input VAR41;
input VAR18;
output [63:0] VAR19;
wire [63:0] VAR35;
wire [63:0] VAR19 = VAR35[63:0];
VAR32 VAR44 (
.VAR27 (VAR21),
.VAR4 (VAR41),
.VAR8 (VAR18),
.VAR54 (VAR50),
.VAR51 ... | gpl-3.0 |
gr0bi42/BTCMiner | fpga/miner253.v | 2,141 | module MODULE1 (clk, reset, VAR13, VAR8, VAR17, VAR10, VAR11);
parameter VAR16 = 32'd0;
parameter VAR19 = 32'd1;
parameter VAR4 = 32'd0;
input clk, reset;
input [255:0] VAR13;
input [95:0] VAR8;
output reg [31:0] VAR17, VAR11, VAR10;
reg [31:0] VAR15;
wire [255:0] VAR21;
wire [31:0] VAR9;
reg VAR3, VAR5, VAR14, VAR20;
... | gpl-3.0 |
r2apu/Labo_Digitales | L2/codigo/IMUL.v | 1,117 | module MODULE2
(
input wire [3:0] VAR9,
input wire [3:0] VAR4,
output reg [7:0] out
);
reg VAR11, VAR5, VAR1; reg [2:0] VAR7, VAR6;
always @ (*) begin
out[0] =VAR9[0] & VAR4[0];
{VAR11, out[1]} = (VAR9[0] & VAR4[1]) + (VAR9[1] & VAR4[0]);
{VAR11, VAR7[0]} = (VAR9[2] & VAR4[0]) + (VAR9[1] & VAR4[1]) + VAR11;
{VAR5, out[... | gpl-3.0 |
jairov4/accel-oil | solution_virtex5_plb/syn/verilog/sample_iterator_get_offset.v | 5,579 | module MODULE1 (
VAR12,
VAR32,
VAR43,
VAR3,
VAR45,
VAR27,
VAR17,
VAR16,
VAR22,
VAR30,
VAR44,
VAR7,
VAR5,
VAR1,
VAR35,
VAR21,
VAR2,
VAR33,
VAR42,
VAR37
);
parameter VAR19 = 1'b1;
parameter VAR38 = 1'b0;
parameter VAR41 = 2'b00;
parameter VAR9 = 2'b1;
parameter VAR24 = 2'b10;
parameter VAR36 = 2'b11;
parameter VAR29 = 32... | lgpl-3.0 |
cpulabs/mist1032isa | src/core/decode/decode_function.v | 189,467 | module MODULE1(
input wire [31:0] VAR2,
output wire VAR5,
output wire VAR8,
output wire VAR24,
output wire VAR33,
output wire VAR9,
output wire VAR23,
output wire VAR13,
output wire VAR34,
output wire VAR16,
output wire VAR21,
output wire VAR32,
output wire VAR35,
output wire VAR28,
output wire [4:0] VAR17,
output wire... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp.pp.symbol.v | 1,332 | module MODULE1 (
input VAR6 ,
input VAR5 ,
input VAR3,
output VAR1,
input VAR7 ,
input VAR4,
input VAR8,
input VAR2
);
endmodule | apache-2.0 |
superibk/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_sha256/rtl/verilog/sha256_K.v | 2,775 | module MODULE1 (
input [5:0] VAR1,
output reg [31:0] VAR2
);
always @*
begin
case(VAR1)
0: VAR2 = 32'h428a2f98;
1: VAR2 = 32'h71374491;
2: VAR2 = 32'hb5c0fbcf;
3: VAR2 = 32'he9b5dba5;
4: VAR2 = 32'h3956c25b;
5: VAR2 = 32'h59f111f1;
6: VAR2 = 32'h923f82a4;
7: VAR2 = 32'hab1c5ed5;
8: VAR2 = 32'hd807aa98;
9: VAR2 = 32'h12... | apache-2.0 |
Ribeiro/sd2snes | verilog/sd2snes/rtc.v | 10,743 | module MODULE1 (
input VAR15,
input VAR14,
input [55:0] VAR41,
input VAR18,
input [59:0] VAR24,
output [59:0] VAR35
);
reg [59:0] VAR10;
reg [59:0] VAR43;
reg [1:0] VAR36;
always @(posedge VAR15) VAR36 <= {VAR36[0], VAR14};
wire VAR12 = (VAR36[1:0] == 2'b01);
reg [2:0] VAR29;
always @(posedge VAR15) VAR29 <= {VAR29[1:0... | gpl-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_convert_to_internal_double.v | 2,459 | module MODULE1( VAR13, VAR17, VAR20,
VAR21, VAR8, VAR19,
VAR7, VAR12, VAR10, VAR5,
enable);
parameter VAR18 = 1;
parameter VAR4 = 1;
parameter VAR22 = 0;
parameter VAR6 = 1;
input VAR13, VAR17;
input [63:0] VAR20;
output [55:0] VAR21;
output [11:0] VAR8;
output VAR19;
input enable, VAR7, VAR10;
output VAR12, VAR5;
reg ... | mit |
jairov4/accel-oil | solution_spartan3/impl/verilog/nfa_accept_samples_generic_hw_add_32ns_32ns_32_8.v | 11,362 | module MODULE2(clk, reset, VAR74, VAR53, VAR27, VAR81);
input clk;
input reset;
input VAR74;
input [32 - 1 : 0] VAR53;
input [32 - 1 : 0] VAR27;
output [32 - 1 : 0] VAR81;
wire [32 - 1 : 0] VAR32;
wire [32 - 1 : 0] VAR52;
wire [4 - 1 : 0] VAR6;
wire [4 - 1 : 0] VAR51;
wire [8 - 1 : 4] VAR61;
wire [8 - 1 : 4] VAR34;
wir... | lgpl-3.0 |
rqou/openfpga | hdl/common/JtagMaster.v | 7,755 | module MODULE1(
clk,
VAR15,
VAR12, VAR31, VAR7, VAR16,
VAR22, VAR19,
VAR8, VAR20, VAR13, din, dout,
VAR5
);
input wire clk;
input wire[7:0] VAR15;
output reg VAR12 = 0;
output reg VAR31 = 0;
output reg VAR7 = 0;
input wire VAR16;
input wire VAR22;
input wire[2:0] VAR19;
input wire[5:0] VAR8;
input wire VAR20;
input wir... | lgpl-2.1 |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v | 7,697 | module MODULE1 (
VAR38,
VAR17, VAR26, VAR12, VAR5, VAR31, VAR11 );
output [15:0] VAR38;
input VAR17; input [13:0] VAR26; input [15:0] VAR12; input VAR5; input [1:0] VAR31; input VAR11;
parameter [14:0] VAR27 = 15'h0090;
parameter VAR32 = 2;
parameter [VAR32-1:0] VAR44 = 'h0,
VAR35 = 'h1,
VAR29 = 'h2,
VAR8 = 'h3;
parame... | bsd-3-clause |
anderson1008/NOCulator | hring/hw/bless_mc/router.v | 24,477 | module MODULE1(
clk,
VAR69,
VAR43,
VAR115,
VAR159,
VAR99,
VAR75,
VAR74,
VAR89,
VAR187,
VAR54,
VAR94
);
input clk, VAR69;
input [VAR79-1:0] VAR43, VAR115, VAR159, VAR99, VAR75;
output [VAR79-1:0] VAR74, VAR89, VAR187, VAR54, VAR94;
wire [VAR79-1:0] VAR47 [0:VAR103-1];
VAR171 #(VAR79) VAR5(VAR43, clk, VAR69, VAR47[0]);
V... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_4.functional.v | 1,664 | module MODULE1( VAR22, VAR15, VAR10, VAR8, VAR6, VAR2 );
input VAR8, VAR10, VAR22, VAR15, VAR2;
output VAR6;
wire VAR14;
not VAR16( VAR14, VAR10 );
wire VAR17;
not VAR21( VAR17, VAR22 );
wire VAR3;
and VAR18( VAR3, VAR14, VAR17 );
wire VAR5;
not VAR12( VAR5, VAR15 );
wire VAR7;
and VAR1( VAR7, VAR14, VAR5 );
wire VAR4;... | apache-2.0 |
anguslin/RISC | decoder.v | 1,280 | module MODULE1(VAR9, VAR2, VAR14, VAR10, VAR15, VAR8, VAR5, VAR12, VAR1, VAR4);
input[15:0] VAR9;
input [1:0] VAR2;
output [2:0] VAR14, VAR10, VAR15;
output [1:0] VAR8, VAR5, VAR12;
output [15:0] VAR1, VAR4;
reg [2:0] VAR11;
wire [2:0] VAR6, VAR13, VAR7;
assign VAR14 = VAR9[15:13];
assign VAR5 = VAR9[12:11];
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.v | 2,313 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR3,
VAR5 ,
VAR2 ,
VAR4 ,
VAR8
);
output VAR1 ;
input VAR6 ;
input VAR3;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR8 ;
VAR7 VAR9 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR1 ,
VAR6 ,
VAR3
);
output VA... | apache-2.0 |
titorgalaxy/Titor | rtl/verilog/chardev/block_Character_Screen.v | 4,616 | module MODULE1 (
dout,
din,
address,
VAR39,
VAR59,
enable,
VAR67,
VAR57,
VAR8,
clk,
reset
);
output wire [VAR24-1:0] dout;
input wire [VAR24-1:0] din;
input wire [VAR24-1:0] address;
input wire [VAR10-1:0] VAR39;
input wire VAR59;
input wire enable;
output reg VAR67;
output reg VAR57;
output reg VAR8;
input wire clk;
i... | gpl-3.0 |
jeffkub/n64-cart-reader | old/hdl/ftdi_wb_bridge/ftdi_sync_fifo.v | 2,829 | module MODULE1 (VAR18, VAR33, VAR14, VAR8, VAR53, VAR40,
VAR72, VAR11, VAR3, VAR35, VAR66, VAR54);
input wire [7:0] VAR18;
input wire VAR33;
input wire VAR14;
input wire VAR8;
input wire VAR53;
input wire VAR40;
input wire VAR72;
output wire [7:0] VAR11;
output wire VAR3;
output wire VAR35;
output wire VAR66;
output wi... | mit |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pll/niosii/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,579 | module MODULE1 (
clk,
reset,
VAR7,
VAR4,
VAR14,
VAR10,
VAR15,
VAR13
);
parameter VAR8 = 1;
parameter VAR9 = 8;
parameter VAR3 = 1;
localparam VAR16 = VAR8 * VAR9;
input clk;
input reset;
output VAR7;
input VAR4;
input [VAR16-1:0] VAR14;
input VAR10;
output VAR15;
output [VAR16-1:0] VAR13;
reg VAR12;
reg VAR11;
reg [VAR... | mit |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_VCU118/mkMMIO_AXI4_Adapter_2.v | 75,496 | module MODULE1(VAR263,
VAR340,
VAR295,
VAR268,
VAR5,
VAR12,
VAR177,
VAR274,
VAR214,
VAR218,
VAR152,
VAR211,
VAR76,
VAR155,
VAR261,
VAR292,
VAR354,
VAR53,
VAR265,
VAR22,
VAR294,
VAR137,
VAR293,
VAR333,
VAR125,
VAR193,
VAR10,
VAR3,
VAR123,
VAR54,
VAR112,
VAR162,
VAR59,
VAR4,
VAR206,
VAR270,
VAR341,
VAR124,
VAR74,
VAR242,... | apache-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_leds.v | 2,094 | module MODULE1 (
address,
VAR3,
clk,
VAR2,
VAR8,
VAR5,
VAR1,
VAR9
)
;
output [ 3: 0] VAR1;
output [ 31: 0] VAR9;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR2;
input VAR8;
input [ 31: 0] VAR5;
wire VAR4;
reg [ 3: 0] VAR6;
wire [ 3: 0] VAR1;
wire [ 3: 0] VAR7;
wire [ 31: 0] VAR9;
assign VAR4 = 1;
assign VAR7 ... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_tagdp.v | 10,955 | module MODULE1(
VAR49, VAR11, VAR27,
VAR68, VAR73, VAR86,
VAR58, VAR55, VAR89, VAR8,
VAR52, VAR78,
VAR28, VAR30, VAR77,
VAR88, VAR42, VAR38,
VAR3,
VAR45, VAR7, VAR66, VAR14,
VAR31, VAR69, VAR64, VAR1,
VAR20, VAR12, VAR67,
VAR54, VAR90, VAR84,
VAR23, VAR22, VAR70,
VAR65, VAR4, VAR62, VAR18, VAR50, VAR19
);
input [39:8] ... | gpl-2.0 |
alexforencich/xfcp | rtl/xfcp_mod_wb.v | 25,726 | module MODULE1 #
(
parameter VAR17 = 16'h0001,
parameter VAR34 = "VAR28 VAR20",
parameter VAR2 = 0,
parameter VAR23 = "",
parameter VAR35 = 16, parameter VAR30 = 32, parameter VAR5 = 32, parameter VAR19 = (VAR30/8) )
(
input wire clk,
input wire rst,
input wire [7:0] VAR31,
input wire VAR8,
output wire VAR18,
input wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill/sky130_fd_sc_hs__fill.functional.pp.v | 1,147 | module MODULE1 (
VAR1,
VAR3,
VAR4 ,
VAR2
);
input VAR1;
input VAR3;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
ehab93/MIPS-Processor | control/control.v | 1,035 | module MODULE1 (
input [5:0] VAR9,
output [1:0] VAR14,
output VAR8, VAR2, VAR3, VAR7,
output VAR1, VAR11, VAR16
);
wire VAR13, VAR6, VAR4, VAR15, VAR12, VAR5, VAR10;
not (VAR6, VAR9[0]);
not (VAR4, VAR9[1]);
not (VAR15, VAR9[2]);
not (VAR12, VAR9[3]);
not (VAR5, VAR9[4]);
not (VAR10, VAR9[5]);
and (VAR14[0], VAR10, VAR... | mit |
olofk/oh | emailbox/hdl/emailbox.v | 5,363 | module MODULE1 (
VAR25, VAR14, VAR5,
reset, VAR6, VAR12, VAR23, VAR4, VAR2, VAR29,
VAR31, VAR34
);
parameter VAR1 = 32; parameter VAR15 = 32; parameter VAR35 = 104; parameter VAR27 = 6; parameter VAR33 = 12'h000;
parameter VAR17 = 104;
parameter VAR11 = 16;
input reset; input VAR6; input VAR12;
input VAR23;
input [VAR3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfsbp/sky130_fd_sc_hs__dfsbp.blackbox.v | 1,320 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR5
);
input VAR1 ;
input VAR2 ;
output VAR6 ;
output VAR7 ;
input VAR5;
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.v | 2,825 | module MODULE1 (
VAR11 ,
VAR5 ,
VAR13 ,
VAR4 ,
VAR9 ,
VAR2 ,
VAR3 ,
VAR8,
VAR12 ,
VAR1 ,
VAR14 ,
VAR7
);
output VAR11 ;
output VAR5 ;
input VAR13 ;
input VAR4 ;
input VAR9 ;
input VAR2 ;
input VAR3 ;
input VAR8;
input VAR12 ;
input VAR1 ;
input VAR14 ;
input VAR7 ;
VAR6 VAR10 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR13(VAR13)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21bai/sky130_fd_sc_ls__o21bai.pp.symbol.v | 1,391 | module MODULE1 (
input VAR5 ,
input VAR3 ,
input VAR4,
output VAR1 ,
input VAR8 ,
input VAR2,
input VAR6,
input VAR7
);
endmodule | apache-2.0 |
strigeus/fpganes | src/NES_Nexys4.v | 12,277 | module MODULE3(
input clk,
input VAR52, input VAR42, input write, input [23:0] addr, input [7:0] din, output reg [7:0] VAR6, output reg [7:0] VAR41, output reg VAR51,
output reg VAR33, output reg VAR57, output VAR32, output VAR63, output reg VAR74, output VAR28, output reg VAR54, output reg VAR34, output reg [22:0] VAR... | gpl-3.0 |
parallella/oh | common/hdl/oh_mux12.v | 1,659 | module MODULE1 #(parameter VAR8 = 1 ) (
input VAR6,
input VAR20,
input VAR2,
input VAR10,
input VAR13,
input VAR16,
input VAR7,
input VAR4,
input VAR24,
input VAR1,
input VAR12,
input VAR19,
input [VAR8-1:0] VAR5,
input [VAR8-1:0] VAR22,
input [VAR8-1:0] VAR17,
input [VAR8-1:0] VAR23,
input [VAR8-1:0] VAR21,
input [VAR... | mit |
zKarp/Karpentium-Processor | src/verilog/alu_with_acc.v | 1,319 | module MODULE1(clk,in,out,select,enable);
parameter VAR2 = 16; parameter VAR3 = 3;
input clk, enable;
input [VAR2-1:0] in;
input [VAR3-1:0] select;
output [VAR2-1:0] out;
reg [VAR2-1:0] VAR4;
reg VAR1;
begin | gpl-2.0 |
TheMadSocrates/vercpu-project | rtl/core/clock_divider.v | 1,547 | module MODULE1(
input wire clk,
input wire VAR2,
input wire [ 1 : 0] VAR1,
output wire VAR5
);
reg VAR4;
reg [ 2**16 - 1 : 0 ] counter;
reg [ 2**16 - 1 : 0 ] VAR3;
assign VAR5 = VAR4;
always @(VAR1 or clk or counter or VAR3) begin
case(VAR1)
2'b00: VAR4 = clk;
2'b01: VAR4 = counter[0];
2'b10: VAR4 = counter[2**16 - 1];... | gpl-3.0 |
parallella/oh | spi/dv/dut_spi.v | 3,663 | module MODULE1(
VAR37, VAR24, VAR31, VAR30, VAR9,
VAR7, VAR35, VAR41, VAR18, VAR11, VAR36, VAR17, VAR22, VAR26
);
parameter VAR38 = 13;
parameter VAR5 = 32;
parameter VAR25 = 32;
parameter VAR14 = 2;
parameter VAR16 = 12;
parameter VAR33 = 6;
parameter VAR29 = 12;
parameter VAR4 = 104;
parameter VAR12 = 1;
input VAR35;... | mit |
zhaishaomin/ring_network-based-multicore- | communication_assist/ic_req_upload.v | 2,689 | module MODULE1( clk,
rst,
VAR8,
VAR7,
VAR9,
VAR14,
VAR5,
VAR16,
VAR6
);
input clk;
input rst;
input [47:0] VAR8;
input VAR7;
input VAR9;
output [15:0] VAR14;
output VAR5;
output [1:0] VAR16;
output VAR6;
parameter VAR12=1'b0;
parameter VAR13=1'b1;
reg VAR2;
reg [47:0] VAR1;
reg [1:0] VAR3;
reg VAR5;
reg VAR10;
reg VAR4... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/DataDriver.v | 4,421 | module MODULE1
(
parameter VAR6 = 32 ,
parameter VAR4 = 16
)
(
VAR9 ,
VAR2 ,
VAR1 ,
VAR20 ,
VAR12 ,
VAR13 ,
VAR8 ,
VAR14 ,
VAR17 ,
VAR18 ,
VAR16 ,
VAR3
);
input VAR9 ;
input VAR2 ;
input [VAR4 - 1:0] VAR1 ;
input VAR20 ;
output VAR12 ;
input [VAR6 - 1:0] VAR13 ;
input VAR8 ;
output VAR14 ;
output [VAR6 - 1:0] VAR17 ;
o... | gpl-3.0 |
elegabriel/myzju | junior1/CA/LAB/lab6/lab6_gxl_3120102146/code/pc0.v | 1,890 | module MODULE1(
clk,rst,VAR4,VAR8,VAR2,VAR9,VAR3,VAR5,VAR1,VAR7
);
input clk,rst;
input [1:0] VAR4;
input [1:0] VAR8; input [4:0] VAR2; input [31:0] VAR9,VAR3; output VAR5; output [31:0] VAR1; output [31:0] VAR7;
reg [31:0] VAR10 [31:0];
wire VAR6;
assign VAR6=|VAR4;
always @(negedge clk or posedge rst or posedge VAR6)... | gpl-2.0 |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/RAT_ControlUnit_0_0_stub.v | 2,674 | module MODULE1(VAR10, VAR8, VAR32, VAR5, VAR21, VAR16, VAR18, VAR25,
VAR23, VAR17, VAR37, VAR13, VAR15, VAR30, VAR1, VAR11, VAR31, VAR14,
VAR26, VAR19, VAR3, VAR28, VAR24, VAR4, VAR6, VAR22,
VAR29, VAR36, VAR2, VAR9, VAR33, VAR27, VAR7, VAR34,
VAR12, VAR35, VAR20)
;
input VAR10;
input VAR8;
input VAR32;
input VAR5;
inp... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_fr_cycle_shifter.v | 3,689 | module MODULE1(
clk,
VAR11,
VAR10,
VAR2,
VAR7
);
parameter VAR9 = "";
parameter VAR1 = "false";
localparam VAR12 = 2;
localparam VAR3 = VAR9*VAR12;
input clk;
input VAR11;
input [1:0] VAR10;
input [VAR3-1:0] VAR2;
output [VAR3-1:0] VAR7;
reg [VAR3-1:0] VAR8;
always @(posedge clk or negedge VAR11)
begin
if (~VAR11) begi... | lgpl-3.0 |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/lights.v | 26,189 | module MODULE1 (
input wire VAR110, output wire [7:0] VAR23, input wire VAR60, input wire [7:0] VAR67 );
wire [31:0] VAR8; wire VAR70; wire VAR102; wire [13:0] VAR61; wire [3:0] VAR137; wire VAR65; wire VAR49; wire [31:0] VAR123; wire [31:0] VAR58; wire VAR103; wire [12:0] VAR168; wire VAR75; wire VAR117; wire [31:0] V... | mit |
pwwu/FPGA | VGAbased/vga_game_top_final.v | 6,151 | module MODULE1
(
input wire clk, reset,
input wire [1:0] VAR1,
input wire [1:0] VAR27,
output wire VAR3, VAR11,
output wire [2:0] VAR15
);
localparam [1:0]
VAR46 = 2'b00,
VAR34 = 2'b01,
VAR23 = 2'b10,
VAR48 = 2'b11;
reg [1:0] VAR29, VAR40;
wire [9:0] VAR16, VAR42;
wire VAR8, VAR21, VAR13, VAR18, VAR10, VAR50;
wire [3:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp.functional.pp.v | 2,360 | module MODULE1 (
VAR22 ,
VAR12 ,
VAR10 ,
VAR18 ,
VAR15 ,
VAR14 ,
VAR20,
VAR9 ,
VAR7 ,
VAR8 ,
VAR11
);
output VAR22 ;
output VAR12 ;
input VAR10 ;
input VAR18 ;
input VAR15 ;
input VAR14 ;
input VAR20;
input VAR9 ;
input VAR7 ;
input VAR8 ;
input VAR11 ;
wire VAR13 ;
wire VAR21 ;
wire VAR16;
not VAR6 (VAR21 , VAR20 );
V... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_burst_gen.v | 62,666 | module MODULE1 #
( parameter
VAR127 = 4,
VAR144 = "VAR102",
VAR148 = 0,
VAR67 = 1,
VAR89 = 1,
VAR75 = 3,
VAR96 = 13,
VAR64 = 10,
VAR29 = 10,
VAR119 = 10,
VAR16 = 4,
VAR43 = 2,
VAR123 = 0,
VAR54 = 0,
VAR86 = 3,
VAR58 = 5,
VAR88 = 4,
VAR36 = 0
)
(
VAR105,
VAR147,
VAR92,
VAR106,
VAR130,
VAR122,
VAR6,
VAR118,
VAR28,
VAR98,... | lgpl-3.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/num_2.v | 1,109 | module MODULE1(
input [2:0] VAR5,
output reg [4:0] VAR2
);
parameter [4:0] VAR6 = 5'b01110; parameter [4:0] VAR7 = 5'b10001; parameter [4:0] VAR3 = 5'b01000; parameter [4:0] VAR8 = 5'b00100; parameter [4:0] VAR1 = 5'b00010; parameter [4:0] VAR4 = 5'b11111;
always @ *
begin
case (VAR5)
3'b000:
VAR2 = VAR6;
3'b001:
VAR2 ... | mit |
bluespec/Flute | builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkBoot_ROM.v | 58,304 | module MODULE1(VAR142,
VAR88,
VAR169,
VAR52,
VAR82,
VAR138,
VAR38,
VAR23,
VAR51,
VAR28,
VAR93,
VAR139,
VAR11,
VAR50,
VAR157,
VAR123,
VAR33,
VAR2,
VAR129,
VAR12,
VAR61,
VAR25,
VAR19,
VAR109,
VAR7,
VAR64,
VAR145,
VAR43,
VAR75,
VAR167,
VAR149,
VAR151,
VAR126,
VAR99,
VAR90,
VAR141,
VAR147,
VAR114,
VAR96,
VAR178,
VAR173,
VA... | apache-2.0 |
omicronns/studies-sys-rek | de1-soc-proc/ip/progmem.v | 6,420 | module MODULE1 (
address,
VAR39,
VAR1);
input [7:0] address;
input VAR39;
output [31:0] VAR1;
tri1 VAR39;
wire [31:0] VAR25;
wire [31:0] VAR1 = VAR25[31:0];
VAR9 VAR50 (
.VAR35 (address),
.VAR33 (VAR39),
.VAR49 (VAR25),
.VAR46 (1'b0),
.VAR48 (1'b0),
.VAR29 (1'b1),
.VAR27 (1'b0),
.VAR52 (1'b0),
.VAR3 (1'b1),
.VAR20 (1'b... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3.blackbox.v | 1,248 | module MODULE1 (
VAR5,
VAR4,
VAR1,
VAR7
);
output VAR5;
input VAR4;
input VAR1;
input VAR7;
supply1 VAR3;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
ultraembedded/riscv | top_tcm_axi/src_v/riscv_tcm_top.v | 12,211 | module MODULE1
parameter VAR221 = 32'h00002000
,parameter VAR233 = 0
,parameter VAR154 = 0
,parameter VAR231 = 0
,parameter VAR212 = 32'hffffffff
)
(
input VAR134
,input VAR63
,input VAR155
,input VAR160
,input VAR204
,input VAR179
,input [ 1:0] VAR113
,input VAR192
,input VAR156
,input [ 31:0] VAR108
,input [ 1:0] VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.v | 2,262 | module MODULE1 (
VAR6,
VAR9 ,
VAR5,
VAR10 ,
VAR1,
VAR3,
VAR7 ,
VAR4
);
output VAR6;
input VAR9 ;
input VAR5;
input VAR10 ;
input VAR1;
input VAR3;
input VAR7 ;
input VAR4 ;
VAR8 VAR2 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
... | apache-2.0 |
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