repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
SymbiFlow/fpga-tool-perf | src/ibex/top_artya7.v | 3,573 | module MODULE1 (
VAR12,
VAR74,
VAR26
);
input VAR12;
input VAR74;
output [3:0] VAR26;
parameter signed [31:0] VAR33 = 65536;
parameter [31:0] VAR1 = 32'h00000000;
parameter [31:0] VAR42 = (VAR33 - 1);
wire VAR43;
wire VAR17;
wire VAR25;
reg VAR9;
wire VAR32;
wire [31:0] VAR55;
wire [31:0] VAR34;
wire VAR75;
reg VAR4;
r... | isc |
hhuang25/uwaterloo_ece224 | Lab1/seven_seg_right_pio.v | 2,194 | module MODULE1 (
address,
VAR6,
clk,
VAR2,
VAR3,
VAR7,
VAR9,
VAR1
)
;
output [ 31: 0] VAR9;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR2;
input VAR3;
input [ 31: 0] VAR7;
wire VAR8;
reg [ 31: 0] VAR4;
wire [ 31: 0] VAR9;
wire [ 31: 0] VAR5;
wire [ 31: 0] VAR1;
assign VAR8 = 1;
assign V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd/sky130_fd_sc_ls__tapvgnd_1.v | 1,938 | module MODULE1 (
VAR4,
VAR1,
VAR3 ,
VAR2
);
input VAR4;
input VAR1;
input VAR3 ;
input VAR2 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
VAR6 VAR5 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/conb/sky130_fd_sc_ms__conb.functional.v | 1,183 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
output VAR2;
pullup VAR4 (VAR1 );
pulldown VAR3 (VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221oi/sky130_fd_sc_ms__a221oi.symbol.v | 1,402 | module MODULE1 (
input VAR2,
input VAR9,
input VAR3,
input VAR5,
input VAR6,
output VAR4
);
supply1 VAR7;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.functional.pp.v | 1,702 | module MODULE1( VAR5, VAR3, VAR22, VAR1, VAR11, VAR15, VAR7, VAR13 );
input VAR11, VAR15, VAR1, VAR22, VAR3;
inout VAR7, VAR13;
output VAR5;
wire VAR14;
not VAR10( VAR14, VAR11 );
wire VAR16;
not VAR4( VAR16, VAR15 );
wire VAR20;
and VAR19( VAR20, VAR14, VAR16 );
wire VAR8;
not VAR2( VAR8, VAR1 );
wire VAR21;
not VAR23... | apache-2.0 |
YosysHQ/yosys | techlibs/anlogic/brams_map.v | 12,152 | module MODULE3 (...);
parameter VAR129 = 0;
parameter VAR166 = "VAR72";
parameter VAR80 = 9;
parameter VAR81 = 1;
parameter VAR2 = "VAR216";
input VAR61;
input VAR219;
input VAR43;
input VAR14;
input VAR188;
input [12:0] VAR20;
input [VAR80-1:0] VAR132;
output [VAR80-1:0] VAR214;
parameter VAR124 = 9;
parameter VAR156 ... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3.pp.symbol.v | 1,280 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR3 ,
output VAR5 ,
input VAR1 ,
input VAR2,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
ViniciusLambardozzi/quanta | Hardware/quanta/db/pll128_altpll.v | 4,091 | module MODULE1
(
clk,
VAR35,
VAR13) ;
output [4:0] clk;
input [1:0] VAR35;
output VAR13;
tri0 [1:0] VAR35;
wire [4:0] VAR12;
wire VAR16;
wire VAR41;
VAR3 VAR18
(
.VAR38(),
.clk(VAR12),
.VAR8(),
.VAR24(VAR16),
.VAR5(VAR16),
.VAR35(VAR35),
.VAR13(VAR41),
.VAR9(),
.VAR37(),
.VAR6(),
.VAR25(),
.VAR30()
,
.VAR33(1'b0),
.VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn.symbol.v | 1,333 | module MODULE1 (
input VAR5 ,
output VAR4 ,
input VAR1
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
titorgalaxy/Titor | rtl/verilog/ps2/PS2Wrapper.v | 3,450 | module MODULE1(
dout,
din,
address,
VAR4,
VAR17,
enable,
interrupt,
VAR6,
VAR1,
reset,
clk
);
output reg [VAR7-1:0] dout;
input wire [VAR7-1:0] din;
input wire [VAR7-1:0] address;
input wire [VAR24-1:0] VAR4;
input wire VAR17;
input wire enable;
output reg interrupt;
inout VAR6;
inout VAR1;
wire [VAR10-1:0] VAR22;
inpu... | gpl-3.0 |
jakubfi/mera400f | src/pp.v | 5,784 | module MODULE1(
input VAR4,
input VAR72,
input VAR11,
input VAR8,
input VAR69,
input VAR37,
input VAR91,
input VAR43,
input VAR35,
input VAR24,
input VAR46,
input VAR74,
input VAR28,
input VAR62,
output VAR52,
output irq,
input VAR21,
input VAR75,
input VAR59,
input VAR1,
input VAR88,
input VAR92,
input VAR27,
input VA... | gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_pa.v | 13,194 | module MODULE1( clk, rst,
VAR42, VAR31, VAR3, VAR51,
VAR35,
VAR43, VAR26,
VAR36, VAR33,
VAR53,
VAR17, VAR19
);
input clk, rst;
output [7:0] VAR42;
output VAR31;
output VAR3;
input VAR51;
output VAR35;
input VAR43;
input [1:0] VAR26;
input VAR36;
input [1:0] VAR33;
input VAR53;
input [7:0] VAR17;
output VAR19;
parameter... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2.blackbox.v | 1,323 | module MODULE1 (
VAR6,
VAR3
);
output VAR6;
input VAR3;
supply1 VAR5;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
forrestv/myhdl | example/manual/FramerCtrl.v | 1,588 | module MODULE1 (
VAR3,
state,
VAR6,
clk,
VAR1
);
output VAR3;
reg VAR3;
output [2:0] state;
reg [2:0] state;
input VAR6;
input clk;
input VAR1;
reg [7:0] VAR5;
always @(posedge clk, negedge VAR1) begin: VAR2
if ((VAR1 == 0)) begin
VAR3 <= 0;
VAR5 <= 0;
state <= 3'b001;
end
else begin
VAR5 <= ((VAR5 + 1) % 8);
VAR3 <= 0... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbn/sky130_fd_sc_hs__dfbbn.behavioral.v | 2,882 | module MODULE1 (
VAR20 ,
VAR21 ,
VAR24 ,
VAR4 ,
VAR16 ,
VAR3,
VAR1 ,
VAR27
);
output VAR20 ;
output VAR21 ;
input VAR24 ;
input VAR4 ;
input VAR16 ;
input VAR3;
input VAR1 ;
input VAR27 ;
wire VAR7 ;
wire VAR28 ;
wire VAR14 ;
wire VAR15 ;
wire VAR13 ;
wire VAR26;
wire VAR12 ;
reg VAR19 ;
wire VAR6 ;
wire VAR22 ;
wire V... | apache-2.0 |
Aetas/nbit-comparator | Quartus 2 proj/nbitcomparator.v | 5,355 | module MODULE1(VAR7, VAR8, VAR2, VAR9, VAR6, VAR1, VAR10, VAR4, VAR5, VAR3);
input VAR7, VAR8, VAR2, VAR9; input VAR6, VAR1, VAR10; output VAR4, VAR5, VAR3;
assign VAR4 = VAR6 & (VAR7 ~^ VAR2) & (VAR8 ~^ VAR9);
assign VAR5 = (VAR1 | (VAR7 & ~VAR2) | (VAR8 & ~VAR2 & ~VAR9) | (VAR7 & VAR8 & VAR2 & ~VAR9)) & ~VAR10;
assig... | mit |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.v | 3,951 | module MODULE1(
addr,
clk,
din,
dout,
en,
VAR18);
input [8 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input VAR18;
VAR37 #(
.VAR15(9),
.VAR46("0"),
.VAR35(512),
.VAR42(0),
.VAR7(1),
.VAR13(1),
.VAR40(1),
.VAR22(0),
.VAR21(0),
.VAR19(0),
.VAR45(0),
.VAR33(0),
.VAR6(1),
.VAR39(18),
.VAR5("VAR... | bsd-3-clause |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/dpram.v | 1,328 | module MODULE1(VAR3,VAR1,VAR4,VAR10,VAR8,VAR9,VAR7);
parameter VAR2 = 4;
parameter VAR11 = 16;
parameter VAR5 = 16;
input VAR3;
input [VAR11-1:0] VAR1;
input [VAR2-1:0] VAR4;
input VAR10;
input VAR8;
output reg [VAR11-1:0] VAR9;
input [VAR2-1:0] VAR7;
reg [VAR11-1:0] VAR6 [0:VAR5-1];
always @(posedge VAR3)
if(VAR10)
VA... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_multiplexer_64.v | 16,288 | module MODULE1
parameter VAR78 = 128,
parameter VAR43 = 12,
parameter VAR97 = 5, parameter VAR29 = "VAR66"
)
(
input VAR68,
input VAR96,
input [VAR43-1:0] VAR91, input [(VAR43*VAR74)-1:0] VAR46, input [(VAR43*VAR26)-1:0] VAR12, input [(VAR43*VAR78)-1:0] VAR106, output [VAR43-1:0] VAR105, output [VAR43-1:0] VAR60,
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o.symbol.v | 1,327 | module MODULE1 (
input VAR7,
input VAR2,
input VAR3,
input VAR6,
output VAR5
);
supply1 VAR4;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/inv/sky130_fd_sc_hs__inv.pp.blackbox.v | 1,172 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR2;
input VAR1;
endmodule | apache-2.0 |
dries007/Basys3 | FPGA-Z/FPGA-Z.srcs/sources_1/ip/ClockDivider/ClockDivider.v | 4,164 | module MODULE1
(
input VAR5,
output VAR3,
output VAR6,
output VAR7,
output VAR1
);
VAR2 VAR4
(
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3.behavioral.v | 1,365 | module MODULE1 (
VAR2,
VAR1,
VAR10,
VAR6
);
output VAR2;
input VAR1;
input VAR10;
input VAR6;
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR9 ;
wire VAR8;
or VAR7 (VAR8, VAR10, VAR1, VAR6 );
buf VAR11 (VAR2 , VAR8 );
endmodule | apache-2.0 |
cybero/Verilog | src/Parameterized Frequency Divider/Freq_Divider.v | 1,093 | module MODULE1#(
parameter VAR6 = 50000000, VAR1 = 1 )
(VAR5, VAR9);
input wire VAR5;
output reg VAR9;
parameter VAR7 = VAR6 / (2*VAR1);
localparam VAR2=VAR3(VAR7);
reg [VAR2-1:0]counter = 0;
always@(posedge VAR5) begin
if (counter == VAR7-1)
begin
counter <= 0;
VAR9 <= ~VAR9;
end
else
begin
counter <= counter + 1'd1;
... | mit |
kielfriedt/ece472 | lab4/mem32.v | 2,292 | module MODULE1(clk, VAR1, VAR7, address, VAR5, VAR9);
input clk, VAR1, VAR7;
input [31:0] address, VAR5;
output [31:0] VAR9;
reg [31:0] VAR9;
parameter VAR8 = 25'd0;
reg [31:0] VAR3 [0:31];
wire [4:0] VAR2;
wire VAR6;
assign VAR2 = address[6:2];
assign VAR6 = (address[31:7] == VAR8);
always @(VAR1 or VAR6 or VAR2 or VA... | gpl-3.0 |
sh-chris110/chris | FPGA/chris.convolution.ok/Qsys/soc_design/synthesis/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR2,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR2;
input VAR3;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1500859667 : 255;
endmodule | gpl-2.0 |
stevenokm/mor1kx | rtl/verilog/mor1kx_lsu_cappuccino.v | 26,804 | module MODULE1
parameter VAR30 = "VAR61",
parameter VAR37 = 32,
parameter VAR128 = 5,
parameter VAR12 = 9,
parameter VAR72 = 2,
parameter VAR125 = 32,
parameter VAR5 = "VAR61",
parameter VAR71 = "VAR61",
parameter VAR116 = "VAR61",
parameter VAR4 = 6,
parameter VAR127 = 1,
parameter VAR34 = "VAR126",
parameter VAR10 = ... | mpl-2.0 |
fpgasystems/caribou | hw/src/regex/kvs_vs_RegexTop_fc.v | 6,837 | module MODULE1
(
input clk,
input VAR12,
input rst,
input VAR58,
input [511:0] VAR46,
input VAR28,
input VAR19,
output VAR38,
input [511:0] VAR20,
input VAR23,
output VAR45,
output VAR18,
output VAR11,
input VAR41
);
parameter VAR47 = 4;
parameter VAR40 = 16;
wire [511:0] VAR14 [VAR40-1:0];
reg [511:0] VAR29 [VAR40-1:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41ai/sky130_fd_sc_hd__o41ai.behavioral.pp.v | 2,059 | module MODULE1 (
VAR12 ,
VAR16 ,
VAR4 ,
VAR9 ,
VAR17 ,
VAR2 ,
VAR15,
VAR18,
VAR3 ,
VAR1
);
output VAR12 ;
input VAR16 ;
input VAR4 ;
input VAR9 ;
input VAR17 ;
input VAR2 ;
input VAR15;
input VAR18;
input VAR3 ;
input VAR1 ;
wire VAR8 ;
wire VAR5 ;
wire VAR13;
or VAR7 (VAR8 , VAR17, VAR9, VAR4, VAR16 );
nand VAR6 (VAR5... | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/ctrl.v | 7,960 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR18] VAR50, output reg [VAR32] VAR45, output reg [VAR39] VAR29,
input wire [VAR25-1:0] irq, output reg VAR11,
input wire [VAR27] VAR22,
input wire [VAR27] VAR30, input wire VAR55, input wire VAR23, input wire [VAR35] VAR40, input wire [VAR18] VAR9, input ... | apache-2.0 |
Iuliiapl/schoolMIPS | board/nexys4/nexys4.v | 1,956 | module MODULE1
(
input clk,
input VAR6,
input VAR35,
input VAR14,
input VAR31,
input VAR25,
input VAR2,
input [15:0] VAR27,
output [15:0] VAR17,
output VAR19,
output VAR29,
output VAR26,
output VAR12,
output VAR16,
output VAR10,
output [ 6:0] VAR39,
output VAR8,
output [ 7:0] VAR28,
inout [ 7:0] VAR22,
inout [ 7:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufinv/sky130_fd_sc_ls__bufinv.behavioral.pp.v | 1,782 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR12,
VAR2,
VAR8 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR12;
input VAR2;
input VAR8 ;
input VAR5 ;
wire VAR6 ;
wire VAR11;
not VAR10 (VAR6 , VAR4 );
VAR3 VAR9 (VAR11, VAR6, VAR12, VAR2);
buf VAR7 (VAR1 , VAR11 );
endmodule | apache-2.0 |
r2apu/Labo_Digitales | L3/LCD.v | 19,840 | module MODULE1
(
input wire VAR19,
input wire VAR29,
output wire VAR40,
output reg VAR43, output wire VAR45,
output wire VAR9,
input wire VAR39;
input wire[7:0] VAR34;
output reg VAR11;
output reg VAR3;
output reg[3:0] VAR33
);
reg VAR48 ;
assign VAR40 = VAR48 ;
assign VAR9 = 0; assign VAR45 = 1; reg [7:0] VAR37,VAR23;... | gpl-3.0 |
shangdawei/proxmark3-lcd | fpga/hi_iso14443a.v | 8,618 | module MODULE1(
VAR5, VAR46, VAR26,
VAR22, VAR27, VAR47, VAR4, VAR55, VAR40,
VAR7, VAR30,
VAR21, VAR6, VAR49, VAR52,
VAR44, VAR45,
VAR8,
VAR53
);
input VAR5, VAR46, VAR26;
output VAR22, VAR27, VAR47, VAR4, VAR55, VAR40;
input [7:0] VAR7;
output VAR30;
input VAR49;
output VAR21, VAR6, VAR52;
input VAR44, VAR45;
output V... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.behavioral.v | 1,093 | module MODULE1( VAR1, VAR5 );
input VAR1;
output VAR5;
VAR4 VAR2(.VAR1(VAR1),.VAR5(VAR5));
VAR4 VAR3(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_approximate/integracion_fisica/front_end/source/GDA_dyn_N16_M4.v | 3,795 | module MODULE1(
input [15:0] VAR57,
input [15:0] VAR105,
input [ 2:0] VAR47,
input VAR113,
input [ 1:0] VAR29,
input [ 2:0] VAR64,
output [16:0] VAR108
);
wire [4:0] VAR31, VAR102, VAR55, VAR17;
wire VAR98,VAR92,VAR87;
wire VAR70,VAR100,VAR49,VAR94,VAR19,VAR95,VAR74,VAR82;
wire VAR30,VAR91,VAR35,VAR41,VAR20;
wire VAR45... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/src/stubs/hdl/fifo_async_103x16.v | 1,617 | module MODULE1(rst, VAR3, VAR1, din, VAR7, VAR4, dout, VAR5, VAR2, VAR6)
;
input rst;
input VAR3;
input VAR1;
input [102:0]din;
input VAR7;
input VAR4;
output [102:0]dout;
output VAR5;
output VAR2;
output VAR6;
assign VAR2 =1'b0;
assign VAR6 =1'b0;
assign dout[102:0] =103'b0;
assign VAR5 =1'b0;
endmodule | gpl-3.0 |
Digilent/vivado-library | ip/Pmods/PmodCOLOR_v1_0/src/PmodCOLOR.v | 13,693 | module MODULE1
(VAR16,
VAR210,
VAR47,
VAR175,
VAR108,
VAR7,
VAR67,
VAR54,
VAR115,
VAR198,
VAR202,
VAR134,
VAR129,
VAR152,
VAR144,
VAR43,
VAR133,
VAR156,
VAR45,
VAR85,
VAR80,
VAR71,
VAR170,
VAR189,
VAR94,
VAR121,
VAR27,
VAR102,
VAR35,
VAR125,
VAR169,
VAR68,
VAR3,
VAR128,
VAR10,
VAR95,
VAR163,
VAR58,
VAR52,
VAR4,
VAR188,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21bai/sky130_fd_sc_ls__o21bai.blackbox.v | 1,389 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR7 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR5;
supply1 VAR8;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111oi/sky130_fd_sc_ls__a2111oi.pp.symbol.v | 1,408 | module MODULE1 (
input VAR1 ,
input VAR7 ,
input VAR3 ,
input VAR6 ,
input VAR10 ,
output VAR5 ,
input VAR2 ,
input VAR8,
input VAR4,
input VAR9
);
endmodule | apache-2.0 |
andykarpov/radio-86rk-wxeda | src/dma/k580wt57.v | 3,779 | module MODULE1(
input clk,
input VAR23,
input reset,
input[3:0] VAR7,
input[7:0] VAR5,
input[3:0] VAR17,
input VAR19,
input VAR6,
input VAR18,
output VAR20,
output reg[3:0] VAR3,
output[7:0] VAR26,
output[15:0] VAR12,
output VAR14,
output VAR25,
output VAR32,
output VAR16 );
parameter VAR13 = 3'b000;
parameter VAR21 = ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo.symbol.v | 1,388 | module MODULE1 (
input VAR8 ,
input VAR5 ,
input VAR4,
output VAR6
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Elphel/x353 | control/control_regs.v | 6,670 | module MODULE1 (VAR22, VAR8, VAR33, VAR11, VAR21, VAR29,
VAR50,
VAR2, VAR54,
VAR16,
VAR13,
VAR32,
VAR5,
VAR37,
VAR44,
VAR53,
VAR15, VAR36, VAR28,
VAR56,
VAR19, VAR6, VAR49, VAR24, VAR23 ); input VAR22;
input VAR8;
input [ 1:0] VAR33;
input [15:0] VAR11;
output [ 1:0] VAR21; output VAR29;
output VAR50;
output VAR2; outp... | gpl-3.0 |
mbus/mbus | mbus/verilog/mbus_int_ctrl.v | 3,135 | module MODULE1
(
input VAR3,
input VAR17,
input VAR11, input VAR16,
input VAR19,
input VAR10,
input VAR8, input VAR4, output reg VAR13,
output reg VAR12,
input VAR9
);
reg VAR6;
reg VAR2;
always @ * begin
if (VAR11 ==VAR1)
VAR6 = 0;
end
else
VAR6 = VAR19;
end
wire VAR5 = ((~VAR6) & (~VAR16));
always @ (negedge VAR3 or ... | apache-2.0 |
ptracton/pmodacl2 | soc/picoblaze/cpu.v | 2,818 | module MODULE1 (
VAR14, VAR2, VAR21, VAR3, VAR1,
VAR13, VAR6, interrupt, VAR4, VAR11
) ;
input VAR13;
input [7:0] VAR6;
output [7:0] VAR14;
output [7:0] VAR2;
output VAR21;
output VAR3;
input interrupt; output VAR1;
input VAR4;
input VAR11;
wire [11:0] address;
wire [17:0] VAR10;
wire [7:0] VAR2;
wire [7:0] VAR14;
wire... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i_2.v | 2,214 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR8 ,
VAR2 ,
VAR3,
VAR10,
VAR9 ,
VAR1
);
output VAR7 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR3;
input VAR10;
input VAR9 ;
input VAR1 ;
VAR5 VAR6 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/cfg.v | 4,781 | module MODULE1 ( VAR6 );
output [255:0] VAR6;
assign VAR6[151:120] = 32'h0001FEED ;
assign VAR6[183:152] = 32'h02000000 ;
assign VAR6[215:184] = 32'h0000FEED ;
assign VAR6[114] = VAR1 ;
assign VAR6[0] = VAR5 ;
assign VAR6[32:1] = VAR4 ;
assign VAR6[33] = VAR8 ;
assign VAR6[35:34] = VAR7 ;
assign VAR6[36] = VAR2 ;
assig... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2i/sky130_fd_sc_hdll__mux2i.functional.pp.v | 1,954 | module MODULE1 (
VAR13 ,
VAR12 ,
VAR3 ,
VAR4 ,
VAR8,
VAR9,
VAR1 ,
VAR11
);
output VAR13 ;
input VAR12 ;
input VAR3 ;
input VAR4 ;
input VAR8;
input VAR9;
input VAR1 ;
input VAR11 ;
wire VAR2;
wire VAR10;
VAR5 VAR14 (VAR2, VAR12, VAR3, VAR4 );
VAR6 VAR7 (VAR10, VAR2, VAR8, VAR9);
buf VAR15 (VAR13 , VAR10 );
endmodule | apache-2.0 |
AngelTerrones/MUSB | Hardware/uart/uart_rx.v | 5,810 | module MODULE1(
input clk,
input rst,
input VAR17, input VAR4, output reg [7:0] VAR22 = 0, output ready );
localparam [3:0] VAR19=0; localparam [3:0] VAR15=1; localparam [3:0] VAR2=2; localparam [3:0] VAR10=3; localparam [3:0] VAR20=4; localparam [3:0] VAR12=5; localparam [3:0] VAR18=6; localparam [3:0] VAR14=7; localp... | mit |
fabianmcg/usbc_tcpc | src/cmos_cells.v | 2,555 | module MODULE1(VAR3, VAR9);
input VAR3;
output VAR9;
assign VAR9 = VAR3;
parameter VAR5=VAR6;
wire [31:0] VAR2;
reg VAR7;
VAR1 VAR8(VAR2,VAR7,VAR3);
integer VAR4;
begin
begin
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o.functional.pp.v | 2,199 | module MODULE1 (
VAR14 ,
VAR11 ,
VAR15 ,
VAR12 ,
VAR3 ,
VAR7 ,
VAR2,
VAR17,
VAR4 ,
VAR16
);
output VAR14 ;
input VAR11 ;
input VAR15 ;
input VAR12 ;
input VAR3 ;
input VAR7 ;
input VAR2;
input VAR17;
input VAR4 ;
input VAR16 ;
wire VAR5 ;
wire VAR9 ;
wire VAR6 ;
wire VAR13;
and VAR20 (VAR5 , VAR12, VAR3 );
and VAR1 (VA... | apache-2.0 |
fbalakirev/red-pitaya-notes | projects/red_pitaya_0_92/red_pitaya_asg_ch.v | 6,637 | module MODULE1
parameter VAR16 = 14
)
(
output reg [ 14-1: 0] VAR2 , input VAR12 , input VAR26 ,
input VAR22 , input VAR7 , input [ 3-1: 0] VAR9 , output VAR6 ,
input VAR32 , input [ 14-1: 0] VAR31 , input [ 14-1: 0] VAR3 , output reg [ 14-1: 0] VAR14 ,
input [VAR16+15: 0] VAR15 , input [VAR16+15: 0] VAR38 , input [VAR... | mit |
alan4186/Hardware-CNN | Hardware/v/window_selector.v | 4,832 | module MODULE1(
input VAR22,
input reset,
input [VAR20:0] VAR14,
input [VAR13:0] VAR8,
input [VAR6:0] VAR4,
output reg[VAR17:0] VAR15
);
wire [VAR17:0] VAR21 [VAR9:0][VAR5:0];
reg[VAR17:0] VAR7 [VAR5:0];
genvar VAR12;
genvar VAR11;
generate
for (VAR12=0; VAR12<VAR19; VAR12=VAR12+1) begin : VAR1
for(VAR11=0; VAR11<VAR16... | mit |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v | 14,534 | module MODULE1 (
VAR12, VAR59, VAR107, VAR69, VAR82, VAR54, VAR99,
VAR83, VAR44 );
output [8*32-1:0] VAR12; output [8*32-1:0] VAR59; output [31:0] VAR107; output [8*32-1:0] VAR69; output [31:0] VAR82; output [15:0] VAR54; output [8*32-1:0] VAR99;
input VAR83; input VAR44;
function [64*8-1:0] VAR79;
input [32*8-1:0] VAR... | bsd-3-clause |
vipinkmenon/scas | hw/fpga/ipcore_dir/tx_fifo_blank.v | 3,009 | module MODULE1(
rst,
VAR7,
VAR4,
din,
VAR3,
VAR5,
dout,
VAR8,
VAR1,
VAR6,
VAR2
);
input rst;
input VAR7;
input VAR4;
input [63 : 0] din;
input VAR3;
input VAR5;
output [7 : 0] dout;
output VAR8;
output VAR1;
output [13 : 0] VAR6;
output [10 : 0] VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b.blackbox.v | 1,271 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR4
);
output VAR1 ;
input VAR3 ;
input VAR4;
supply1 VAR5;
supply0 VAR2;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/ucore/syscop.v | 15,187 | module MODULE1
(
VAR31,VAR3,
VAR41,VAR12,VAR30,VAR55,VAR38,VAR45,
VAR48,VAR10,
VAR68,VAR35,VAR34,
VAR1,VAR66,VAR11,
VAR39,VAR15,VAR24,
VAR17,VAR40,VAR54
);
parameter VAR19 = VAR59;
parameter VAR18 = 26'b10000000000000000000011000;
parameter VAR57 = 26'b10000000000000000000011111;
parameter VAR9 = 26'VAR13;
parameter VA... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_mem_2r1w.v | 2,831 | if (VAR10 == VAR31 && VAR39 == VAR14) \
begin: VAR43 \
wire [VAR10-1:0] VAR32 = (VAR34 << VAR11); \
wire [VAR10-1:0] VAR25 = (VAR36 << VAR37); \
wire [VAR10-1:0] VAR15 = (VAR21 << VAR35); \
\
VAR40 VAR42 \
( .VAR26(VAR3) \
,.VAR18(VAR27) \
,.VAR19(VAR32) \
,.VAR6 ({VAR15,VAR25}) \
,.VAR9({VAR4,VAR30}) \
); \
end
module... | bsd-3-clause |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/usb_system_sdram_clk.v | 10,949 | module MODULE1
(
VAR10,
VAR9,
VAR8,
VAR1) ;
input VAR10;
input VAR9;
input [0:0] VAR8;
output [0:0] VAR1;
tri0 VAR10;
tri1 VAR9;
reg [0:0] VAR5;
reg [0:0] VAR4;
reg [0:0] VAR3;
wire VAR2;
wire VAR7;
wire VAR6; | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o.functional.pp.v | 2,125 | module MODULE1 (
VAR15,
VAR12,
VAR16 ,
VAR17 ,
VAR3 ,
VAR14 ,
VAR18 ,
VAR5
);
input VAR15;
input VAR12;
output VAR16 ;
input VAR17 ;
input VAR3 ;
input VAR14 ;
input VAR18 ;
input VAR5 ;
wire VAR18 VAR7 ;
wire VAR18 VAR13 ;
wire VAR2 ;
wire VAR8;
and VAR11 (VAR7 , VAR14, VAR17, VAR3 );
and VAR4 (VAR13 , VAR18, VAR5 );
... | apache-2.0 |
asicguy/gplgpu | hdl/vga/vga_top.v | 5,912 | module MODULE1
(
input VAR64, input VAR13, input VAR21, input VAR62, input VAR23, input VAR6, input VAR36, input VAR54, input [3:0] VAR10, input [22:0] VAR59, input [31:0] VAR66, input [31:0] VAR47, input VAR43, input VAR55, input VAR38, input VAR11,
output [31:0] VAR71, output [2:0] VAR40,
output VAR58, output VAR7, o... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.behavioral.pp.v | 2,375 | module MODULE1( VAR10, VAR6, VAR8, VAR1, VAR5, VAR2, VAR7 );
input VAR1, VAR5, VAR6, VAR10;
inout VAR2, VAR7;
output VAR8;
VAR3 VAR9(.VAR10(VAR10),.VAR6(VAR6),.VAR8(VAR8),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7));
VAR3 VAR4(.VAR10(VAR10),.VAR6(VAR6),.VAR8(VAR8),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/dat_i_arbiter.v | 2,209 | module MODULE1(
input wire VAR5,
output wire [7:0] VAR2,
input [7:0] VAR12,
input VAR7,
input [7:0] VAR11,
input VAR3,
input [7:0] VAR6,
input VAR10,
input [7:0] VAR8,
input VAR16,
input [7:0] VAR9,
input VAR4,
input [7:0] VAR14,
input VAR15,
input [7:0] VAR13,
input VAR1
);
assign VAR2 = (VAR7) ? VAR12 :
(VAR3) ? VAR1... | gpl-3.0 |
jmacneal/Design-Project | Display/VGA_Audio_PLL.v | 17,782 | module MODULE1 (
VAR95,
VAR6,
VAR87,
VAR81,
VAR14);
input VAR95;
input VAR6;
output VAR87;
output VAR81;
output VAR14;
tri0 VAR95;
wire [5:0] VAR52;
wire [0:0] VAR73 = 1'h0;
wire [2:2] VAR77 = VAR52[2:2];
wire [0:0] VAR43 = VAR52[0:0];
wire [1:1] VAR11 = VAR52[1:1];
wire VAR81 = VAR11;
wire VAR87 = VAR43;
wire VAR14 = ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux4/sky130_fd_sc_hd__mux4.blackbox.v | 1,339 | module MODULE1 (
VAR6 ,
VAR4,
VAR3,
VAR7,
VAR10,
VAR2,
VAR5
);
output VAR6 ;
input VAR4;
input VAR3;
input VAR7;
input VAR10;
input VAR2;
input VAR5;
supply1 VAR9;
supply0 VAR1;
supply1 VAR11 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/01BLUETOOTH/Version_02/02 verilog/periferico_BT/transmision.v | 1,666 | module MODULE1 (input enable,
input VAR5,
input reset,
input wire [7:0] din,
output VAR2,
output reg VAR3,
output reg VAR4);
parameter VAR1 = 8; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi.behavioral.pp.v | 2,164 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR11 ,
VAR17 ,
VAR18 ,
VAR9,
VAR1,
VAR15 ,
VAR14
);
output VAR13 ;
input VAR8 ;
input VAR11 ;
input VAR17 ;
input VAR18 ;
input VAR9;
input VAR1;
input VAR15 ;
input VAR14 ;
wire VAR12 ;
wire VAR7 ;
wire VAR5 ;
wire VAR19;
nand VAR2 (VAR12 , VAR11, VAR8 );
nand VAR10 (VAR7 , VAR18, VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s.behavioral.pp.v | 1,766 | module MODULE1 (
VAR4,
VAR10,
VAR6 ,
VAR8
);
input VAR4;
input VAR10;
output VAR6 ;
input VAR8 ;
wire VAR5 ;
wire VAR1;
buf VAR7 (VAR5 , VAR8 );
VAR9 VAR2 (VAR1, VAR5, VAR4, VAR10);
buf VAR3 (VAR6 , VAR1 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.behavioral.v | 1,180 | module MODULE1( VAR2, VAR1, VAR3 );
input VAR2, VAR3;
output VAR1;
VAR5 VAR4(.VAR2(VAR2),.VAR1(VAR1),.VAR3(VAR3));
VAR5 VAR6(.VAR2(VAR2),.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
jotego/jt12 | hdl/adpcm/jt10_adpcmb.v | 3,929 | module MODULE1(
input VAR12,
input clk, input VAR5, input [3:0] VAR7,
input VAR6, input VAR24,
input VAR2,
output signed [15:0] VAR23
);
localparam VAR11 = 15, VAR20=16;
reg signed [VAR20-1:0] VAR19, VAR18;
reg [VAR11-1:0] VAR17;
reg [VAR11+1:0] VAR9;
assign VAR23 = VAR19[VAR20-1:VAR20-16];
wire [VAR20-1:0] VAR4 = {1'b... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2.blackbox.v | 1,227 | module MODULE1 (
VAR7,
VAR1,
VAR5
);
output VAR7;
input VAR1;
input VAR5;
supply1 VAR6;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.functional.pp.v | 1,027 | module MODULE1( VAR18, VAR11, VAR16, VAR8, VAR14, VAR13, VAR10, VAR6 );
input VAR18, VAR11, VAR8, VAR16, VAR13, VAR10, VAR6;
output VAR14;
not VAR12( VAR4, VAR18 );
not VAR17( VAR5, VAR8 );
not VAR19( VAR9, VAR16 );
not VAR15( VAR3, VAR11 );
VAR1( VAR2, VAR9, VAR5, VAR4, VAR3, VAR6 );
not VAR7( VAR14, VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb.pp.blackbox.v | 1,357 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR4 ,
VAR7 ,
VAR2,
VAR3,
VAR5 ,
VAR8
);
output VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR2;
input VAR3;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v | 5,482 | module MODULE1(
clk, rst,
VAR9, VAR3, VAR1,
addr, en, VAR2, VAR17, VAR6
);
parameter VAR4 = VAR5;
parameter VAR19 = VAR7;
input clk;
input rst;
input [VAR19-1:0] addr;
input en;
input [3:0] VAR2;
input [VAR4-1:0] VAR17;
output [VAR4-1:0] VAR6;
input VAR9;
input [VAR8 - 1:0] VAR1;
output VAR3;
assign VAR6 = {VAR4{1'b0}}... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b.symbol.v | 1,285 | module MODULE1 (
input VAR1 ,
input VAR4,
output VAR7
);
supply1 VAR6;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/slaveController/sctxportarbiter.v | 7,275 | module MODULE1 (VAR14, VAR22, VAR13, VAR32, VAR1, clk, VAR29, VAR9, VAR5, VAR12, VAR31, rst, VAR30, VAR23, VAR3, VAR25, VAR4);
input VAR13;
input clk;
input [7:0] VAR29;
input [7:0] VAR9;
input VAR12;
input VAR31;
input rst;
input [7:0] VAR30;
input [7:0] VAR23;
input VAR25;
input VAR4;
output [7:0] VAR14;
output [7:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o.functional.v | 1,566 | module MODULE1 (
VAR9 ,
VAR10,
VAR12,
VAR5,
VAR4,
VAR6
);
output VAR9 ;
input VAR10;
input VAR12;
input VAR5;
input VAR4;
input VAR6;
wire VAR3 ;
wire VAR7 ;
wire VAR1;
and VAR2 (VAR3 , VAR5, VAR4 );
and VAR13 (VAR7 , VAR10, VAR12 );
or VAR8 (VAR1, VAR7, VAR3, VAR6);
buf VAR11 (VAR9 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22oi/sky130_fd_sc_hs__a22oi.pp.blackbox.v | 1,340 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR1,
VAR5
);
output VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR1;
input VAR5;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf_2.v | 1,993 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR6,
VAR3,
VAR7 ,
VAR8
);
output VAR1 ;
input VAR5 ;
input VAR6;
input VAR3;
input VAR7 ;
input VAR8 ;
VAR4 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR6;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o.functional.pp.v | 2,224 | module MODULE1 (
VAR19 ,
VAR12 ,
VAR20 ,
VAR5 ,
VAR18 ,
VAR13 ,
VAR11,
VAR8,
VAR10 ,
VAR15
);
output VAR19 ;
input VAR12 ;
input VAR20 ;
input VAR5 ;
input VAR18 ;
input VAR13 ;
input VAR11;
input VAR8;
input VAR10 ;
input VAR15 ;
wire VAR9 ;
wire VAR14 ;
wire VAR6 ;
wire VAR3;
and VAR2 (VAR9 , VAR5, VAR12, VAR20 );
an... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.symbol.v | 1,467 | module MODULE1 (
input VAR7 ,
output VAR6 ,
input VAR1 ,
input VAR3 ,
input VAR8 ,
input VAR5,
input VAR4 ,
input VAR2
);
endmodule | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ip/cdn_axi_bfm_1/hdl/src/verilog/cdn_axi_bfm_1.v | 7,427 | module MODULE1 (VAR9, VAR15,
VAR19, VAR6, VAR1,
VAR41,VAR12,VAR39,VAR27, VAR38);
parameter VAR31 = "MODULE1";
parameter VAR2 = 24;
parameter VAR30 = 8;
parameter VAR20 = 4;
parameter VAR22 = 8;
parameter VAR13 = 10;
parameter VAR37 = 8;
parameter VAR3 = 8;
parameter VAR8 = 1;
parameter VAR21 = 0;
input wire VAR9;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a.pp.blackbox.v | 1,368 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR1,
VAR6,
VAR7 ,
VAR4
);
output VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR1;
input VAR6;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/amber23/a23_multiply.v | 7,545 | module MODULE1 (
input VAR11,
input VAR21,
input [31:0] VAR23, input [31:0] VAR26, input [1:0] VAR17,
input VAR3,
output [31:0] VAR18,
output [1:0] VAR7, output reg VAR12 = 'd0 );
wire enable;
wire VAR20;
wire [33:0] VAR8;
wire [33:0] VAR4;
wire [33:0] sum;
wire [33:0] VAR5;
reg [5:0] VAR16 = 'd0;
reg [5:0] VAR24;
reg ... | lgpl-3.0 |
UviDTE-UviSpace/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/camera_capture.v | 4,922 | module MODULE1 #(
parameter VAR20 = 12
) (
input VAR17,
input VAR16,
input [11:0] VAR25,
input [11:0] VAR9,
input VAR15,
input VAR22,
input VAR24,
input [VAR20-1:0] VAR4,
output [31:0] VAR8,
output VAR21,
output [VAR20-1:0] VAR2,
output [11:0] VAR18,
output [11:0] VAR13,
output VAR14
);
reg [11:0] VAR19;
reg [11:0] VAR... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_impctl_sclk.v | 4,228 | module MODULE1(VAR28 ,VAR19 ,VAR29 ,VAR33 ,VAR36 ,VAR30 ,
VAR41 );
output VAR19 ;
output VAR29 ;
output VAR33 ;
input VAR28 ;
input VAR36 ;
input VAR30 ;
input VAR41 ;
wire [2:0] VAR49 ;
wire [3:0] VAR38 ;
wire [3:0] VAR32 ;
wire VAR46 ;
wire VAR52 ;
wire VAR14 ;
wire VAR22 ;
wire VAR7 ;
wire VAR27 ;
wire VAR4 ;
wire V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe_3.v | 1,910 | module MODULE1 (
VAR3,
VAR2,
VAR6 ,
VAR4
);
input VAR3;
input VAR2;
input VAR6 ;
input VAR4 ;
VAR1 VAR5 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR4 ;
VAR1 VAR5 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb.functional.v | 1,068 | module MODULE1 ();
endmodule | apache-2.0 |
DreamSourceLab/DSLogic-hdl | src/loopback.v | 9,675 | module MODULE1(
input VAR42,
input VAR82,
input VAR46,
input VAR37,
input VAR60,
input VAR16,
input VAR36,
input mux,
input VAR68,
input VAR26,
output reg VAR81,
output reg VAR55,
output reg VAR10,
output [31:0] VAR53,
output VAR52,
output reg VAR72,
output reg [15:0] VAR54,
input VAR14,
input VAR59,
output reg VAR17,
... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_fpext.v | 11,328 | module MODULE1
(
VAR37,
VAR25,
VAR44,
VAR29) ;
input VAR37;
input VAR25;
input [31:0] VAR44;
output [63:0] VAR29;
tri1 VAR37;
reg [10:0] VAR34;
reg [34:0] VAR8;
reg VAR26;
reg VAR30;
reg VAR43;
reg [22:0] VAR23;
reg VAR12;
wire [10:0] VAR18;
wire VAR20;
wire [10:0] VAR16;
wire [10:0] VAR38;
wire VAR15;
wire [33:0] VAR7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2.symbol.v | 1,321 | module MODULE1 (
input VAR2,
output VAR3
);
supply1 VAR1;
supply0 VAR4;
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/dbg_interface/dbg_trace.v | 21,600 | module MODULE1 (VAR56, VAR100, VAR2, VAR68, VAR18, VAR95, VAR73,
VAR86, VAR9, VAR33, VAR97, VAR1,
VAR25, VAR77, VAR16, VAR96, VAR82, VAR34,
VAR49, VAR24, VAR50, VAR79, VAR21, VAR40,
VAR45, VAR63, VAR93, VAR58,
VAR91,
VAR7, VAR65, VAR87, VAR71,
VAR64, VAR10, VAR83, VAR35, VAR75,
VAR47, VAR29, VAR15, VAR37, VAR3, VAR13, ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp.pp.symbol.v | 1,333 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR4,
input VAR7 ,
input VAR5,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
davidkoltak/tawas-core | ip/enet/rtl/sgmii_autoneg.v | 9,273 | module MODULE1
(
input rst,
input VAR3,
input [7:0] VAR5,
input VAR13,
input VAR6,
output VAR10,
output VAR11,
output VAR21,
output VAR19,
output [15:0] VAR20
);
parameter VAR8 = 16'd40000;
reg [5:0] VAR2;
wire [5:0] VAR9 = (VAR2 + 6'd1);
reg VAR1;
reg VAR7;
reg VAR12;
reg VAR18;
reg [15:0] VAR15;
reg [15:0] VAR17;
reg... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.behavioral.v | 2,510 | module MODULE1( VAR2, VAR7, VAR4, VAR3 );
input VAR7, VAR2, VAR4;
output VAR3;
VAR6 VAR5(.VAR2(VAR2),.VAR7(VAR7),.VAR4(VAR4),.VAR3(VAR3));
VAR6 VAR1(.VAR2(VAR2),.VAR7(VAR7),.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
swallat/yosys | techlibs/achronix/speedster22i/cells_map.v | 3,682 | module \VAR24 (input VAR26, VAR15, output VAR17);
parameter VAR23="VAR20";
VAR45 #(.VAR39(VAR23)) VAR19 (.VAR16(VAR26), .VAR35(VAR17), .clk(VAR15), .VAR28(1'b1), .VAR42(1'b1), .VAR18(1'b1), .VAR37(1'b0), .VAR12(1'b0), .VAR27(1'b0), .VAR6(1'b0));
endmodule
module \VAR41 (input VAR26, VAR15, output VAR17);
parameter VAR2... | isc |
8l/beri | cherilibs/trunk/peripherals/TERASIC_ISP1761/ISP1761_IF.v | 2,682 | module MODULE1(
VAR6,
VAR16,
VAR3,
VAR1,
VAR17,
VAR18,
VAR21,
VAR23,
VAR20,
VAR15,
VAR7,
VAR9,
VAR10,
VAR11,
VAR4,
VAR5,
VAR2,
VAR13,
VAR14,
VAR19,
VAR8,
VAR12
);
input VAR6;
input VAR16;
input VAR3;
input [15:0] VAR1;
input VAR17;
input [31:0] VAR18;
input VAR21;
output [31:0] VAR23;
output VAR20;
output VAR15;
output... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o.behavioral.v | 1,676 | module MODULE1 (
VAR12 ,
VAR6,
VAR2,
VAR8,
VAR10,
VAR9
);
output VAR12 ;
input VAR6;
input VAR2;
input VAR8;
input VAR10;
input VAR9;
supply1 VAR4;
supply0 VAR17;
supply1 VAR16 ;
supply0 VAR5 ;
wire VAR15 ;
wire VAR13 ;
wire VAR7;
and VAR1 (VAR15 , VAR8, VAR6, VAR2 );
and VAR14 (VAR13 , VAR10, VAR9 );
or VAR11 (VAR7, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv_lp.v | 2,003 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR6,
VAR8,
VAR7 ,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR6;
input VAR8;
input VAR7 ;
input VAR4 ;
VAR3 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR6;
supply0 VAR8;... | apache-2.0 |
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