repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.behavioral.pp.v | 1,561 | module MODULE1( VAR8, VAR6, VAR4, VAR9, VAR5, VAR2 );
input VAR4, VAR8, VAR9;
inout VAR5, VAR2;
output VAR6;
VAR1 VAR3(.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR9(VAR9),.VAR5(VAR5),.VAR2(VAR2));
VAR1 VAR7(.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR9(VAR9),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvn/sky130_fd_sc_hs__einvn.pp.symbol.v | 1,296 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR3,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/trace_cntrl_1_2/hdl/verilog/trace_cntrl_trace_cntrl_s_axi.v | 11,592 | module MODULE1
VAR32 = 6,
VAR24 = 32
)(
input wire VAR51,
input wire VAR19,
input wire VAR17,
input wire [VAR32-1:0] VAR44,
input wire VAR64,
output wire VAR36,
input wire [VAR24-1:0] VAR10,
input wire [VAR24/8-1:0] VAR14,
input wire VAR46,
output wire VAR41,
output wire [1:0] VAR42,
output wire VAR56,
input wire VAR37... | bsd-3-clause |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/213bdb6c5f83bd6a/zqynq_lab_1_design_processing_system7_0_0_stub.v | 5,396 | module MODULE1(VAR5, VAR60,
VAR28, VAR55, VAR64, VAR50,
VAR24, VAR1, VAR15, VAR54,
VAR44, VAR20, VAR58, VAR39, VAR21,
VAR49, VAR13, VAR65, VAR29,
VAR7, VAR26, VAR51, VAR37, VAR45,
VAR10, VAR6, VAR66, VAR42, VAR34,
VAR25, VAR16, VAR40, VAR35, VAR31,
VAR9, VAR68, VAR67, VAR33,
VAR41, VAR17, VAR46, VAR63, VAR23,
VAR32, VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a_m.v | 2,445 | module MODULE1 (
VAR9 ,
VAR12 ,
VAR2 ,
VAR8 ,
VAR3 ,
VAR1 ,
VAR4,
VAR6,
VAR5 ,
VAR10
);
output VAR9 ;
input VAR12 ;
input VAR2 ;
input VAR8 ;
input VAR3 ;
input VAR1 ;
input VAR4;
input VAR6;
input VAR5 ;
input VAR10 ;
VAR7 VAR11 (
.VAR9(VAR9),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VA... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_mrqq_ctl.v | 14,272 | module MODULE1(
VAR40, VAR42, VAR55,
VAR61, VAR100, VAR17, VAR97, VAR89,
VAR47, VAR107, VAR22, VAR21, VAR8,
VAR84, VAR76,
clk, VAR62, VAR24, VAR20,
VAR27, VAR95, VAR28,
VAR5, VAR37, VAR68, VAR104
);
input clk;
input VAR62;
input VAR24;
input [127:0] VAR20; input VAR27;
input VAR95;
input VAR28;
input VAR5;
input VAR37;... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.functional.pp.v | 1,404 | module MODULE1( VAR12, VAR11, VAR2, VAR6, VAR14, VAR7, VAR9 );
input VAR14, VAR6, VAR2, VAR12;
inout VAR7, VAR9;
output VAR11;
wire VAR1;
not VAR16( VAR1, VAR14 );
wire VAR15;
not VAR4( VAR15, VAR6 );
wire VAR13;
not VAR5( VAR13, VAR2 );
wire VAR3;
not VAR10( VAR3, VAR12 );
and VAR8( VAR11, VAR1, VAR15, VAR13, VAR3 );
... | apache-2.0 |
dk00/old-stuff | csie/09computer-architecture/CPU1/code/Control.v | 1,376 | module MODULE1(VAR1,VAR3,VAR15,VAR16,VAR4,VAR13,VAR2,VAR10,VAR7,VAR14);
parameter VAR12=6'b100011,VAR9=6'b101011,VAR8=6'b000100,VAR11=6'b000000,VAR5=6'b000010,VAR6=6'b001000;
input [5:0] VAR1;
output VAR3,VAR15,VAR16,VAR4,VAR13,VAR10,VAR7,VAR14;
output [1:0] VAR2;
assign VAR3=(VAR1==0 || (VAR1&6'b111110)==6'b000010 ||
... | unlicense |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/verilog/processing_system7_v5_3_b_atc.v | 14,642 | module MODULE1 #
(
parameter VAR43 = "VAR21",
parameter integer VAR31 = 4,
parameter integer VAR41 = 1,
parameter integer VAR40 = 4
)
(
input wire VAR39,
input wire VAR20,
input wire VAR42,
input wire VAR30,
input wire [VAR31-1:0] VAR14,
output wire VAR22,
output wire [VAR40-1:0] VAR36,
output reg VAR6,
output wire [VA... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_core/altera_tse_rgmii_in4.v | 4,986 | module MODULE1 (
VAR7,
VAR16,
VAR5,
VAR1,
VAR10);
input VAR7;
input [3:0] VAR16;
input VAR5;
output [3:0] VAR1;
output [3:0] VAR10;
wire [3:0] VAR11;
wire [3:0] VAR4;
wire [3:0] VAR1 = VAR11[3:0];
wire [3:0] VAR10 = VAR4[3:0];
VAR17 VAR9 (
.VAR16 (VAR16),
.VAR5 (VAR5),
.VAR7 (VAR7),
.VAR1 (VAR11),
.VAR10 (VAR4),
.VAR12... | apache-2.0 |
juan199/Lab_Digitales | exp3/MiniAlu.v | 7,593 | module MODULE1
(
input wire VAR28,
input wire VAR72,
output wire [7:0] VAR37,
output wire [3:0] VAR52,
output wire VAR78,
output wire VAR58,
output wire VAR66,
output wire VAR31
);
reg VAR76; reg VAR35; reg [3:0] VAR12; wire VAR69;
wire [15:0] VAR41,VAR19,VAR10;
wire [7:0] VAR21;
reg VAR70;
reg VAR6;
wire [15:0] VAR54;... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n.behavioral.pp.v | 1,875 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR7,
VAR2 ,
VAR3 ,
VAR6 ,
VAR10
);
output VAR13 ;
input VAR4 ;
input VAR7;
input VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR10 ;
wire VAR11 ;
wire VAR12;
not VAR9 (VAR11 , VAR7 );
or VAR1 (VAR12, VAR4, VAR11 );
VAR5 VAR8 (VAR13 , VAR12, VAR2, VAR3);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd.blackbox.v | 1,257 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
dailypips/miaow | src/verilog/rtl/vgpr/wfid_mux_9to1.v | 2,269 | module MODULE1 (
VAR14,
VAR11,
VAR19,
VAR3,
VAR9,
VAR16,
VAR5,
VAR2,
VAR7,
VAR10,
VAR18,
VAR15,
VAR17,
VAR8,
VAR20,
VAR13,
VAR4,
VAR12,
VAR6
);
output [5:0] VAR12;
output VAR6;
input [15:0] VAR14;
input VAR11;
input [5:0] VAR19;
input VAR3;
input [5:0] VAR9;
input VAR16;
input [5:0] VAR5;
input VAR2;
input [5:0] VAR7;
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi_2.v | 2,350 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR5 ,
VAR7 ,
VAR9 ,
VAR10,
VAR8,
VAR3 ,
VAR11
);
output VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR10;
input VAR8;
input VAR3 ;
input VAR11 ;
VAR2 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VA... | apache-2.0 |
gralco/FPGA-Elevator-Project | Mojo V3 - Xilinx Spartan 6 Project/Elevator IO Shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top.v | 1,947 | module MODULE1(
input clk,
input VAR21,
input VAR10,
output[7:0]VAR22,
output VAR29,
input VAR19,
input VAR3,
input VAR7,
output [3:0] VAR28,
input VAR16, output VAR18, input VAR23, output [23:0] VAR12, output [7:0] VAR6, output [3:0] VAR14, input [3:0] VAR8,
input en,
input [23:0] VAR24,
output [3:0] VAR9,
output [3:0... | gpl-2.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/cyclone4gx_dmem.v | 7,661 | module MODULE1 (
address,
VAR20,
VAR1,
VAR30,
VAR24,
VAR50,
VAR32);
input [9:0] address;
input [1:0] VAR20;
input VAR1;
input VAR30;
input [15:0] VAR24;
input VAR50;
output [15:0] VAR32;
tri1 [1:0] VAR20;
tri1 VAR1;
tri1 VAR30;
wire [15:0] VAR25;
wire [15:0] VAR32 = VAR25[15:0];
VAR9 VAR10 (
.VAR34 (VAR1),
.VAR31 (VAR5... | bsd-3-clause |
firedom/combin-for-FPGA | src/priorityEncoders83.v | 2,806 | module MODULE1(in, VAR32, out, VAR8, VAR16);
input [0:7]in;
input VAR32;
output [0:2]out;
output VAR8;
output VAR16;
wire VAR5, VAR26, VAR6, VAR23, VAR27, VAR7, VAR31, VAR2, VAR24, VAR28, VAR10, VAR21;
nand
VAR14(VAR16, in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7], ~VAR32), VAR4(VAR8, VAR16, ~VAR32);
and
VAR2... | gpl-3.0 |
mammenx/pegasus | wxp/dgn/rtl/common/gry_cntr.v | 3,786 | module MODULE1 #(VAR9 = 8)
(
clk,
VAR7,
VAR1,
en,
VAR2,
VAR5
);
input clk;
input VAR7;
input [VAR9-1:0] VAR1;
input en;
output [VAR9-1:0] VAR2;
output [VAR9-1:0] VAR5;
reg [VAR9-1:0] VAR2;
reg [VAR9-1:0] VAR5;
reg [VAR9-1:0] VAR8;
reg [VAR9-1:0] VAR4;
reg [VAR9-1:0] VAR6;
genvar VAR10;
generate
for(VAR10=VAR9-1; VAR10>... | gpl-3.0 |
chriz2600/DreamcastHDMI | Core/source/video2ram.v | 4,781 | module MODULE1(
input VAR19,
input VAR7,
input [7:0] VAR45,
input [7:0] VAR29,
input [7:0] VAR48,
input [11:0] VAR12,
input [11:0] VAR54,
input VAR46,
input VAR44,
output [23:0] VAR13,
output [VAR37-1:0] VAR41,
output VAR9,
output VAR2,
input VAR8 VAR34,
input [7:0] VAR47
);
reg [9:0] VAR43;
reg [9:0] VAR32;
reg [9:0] ... | mit |
zhangly/azpr_cpu | rtl/top/rtl/chip.v | 12,068 | module MODULE1 (
input wire clk, input wire clk, input wire reset
);
wire [VAR94] VAR39; wire VAR60; wire VAR74; wire [VAR10] VAR27; wire VAR92; wire VAR86; wire [VAR94] VAR5; wire VAR13; wire VAR23; wire [VAR10] VAR14; wire VAR25; wire VAR91; wire [VAR94] VAR96; wire VAR35; wire VAR12; wire [VAR10] VAR24; wire VAR78; ... | mit |
anguslin/RISC | controller.v | 14,549 | module MODULE1(clk, VAR16, VAR38, VAR2, VAR32, VAR47, VAR4, VAR49, VAR22, write, VAR30, VAR13, VAR37, VAR41, reset, VAR29, VAR1, VAR50, VAR3, VAR52, VAR31 );
input clk, reset;
input [1:0] VAR16, VAR38, VAR2;
input [2:0] VAR32, VAR47, VAR4;
output VAR49, VAR22, write, VAR30, VAR13, VAR37, VAR41, VAR29, VAR1, VAR50, VAR3... | mit |
SWORDfpga/ComputerOrganizationDesign | labs/lab05/lab05/ipcore_dir/ROM_D.v | 3,815 | module MODULE1(
VAR47,
VAR42
);
input [9 : 0] VAR47;
output [31 : 0] VAR42;
VAR52 #(
.VAR9(10),
.VAR44("0"),
.VAR26(1024),
.VAR30("VAR41"),
.VAR34(0),
.VAR29(0),
.VAR18(0),
.VAR22(0),
.VAR8(0),
.VAR3(0),
.VAR1(0),
.VAR40(0),
.VAR20(0),
.VAR25(0),
.VAR35(0),
.VAR27(0),
.VAR10(0),
.VAR43(0),
.VAR54(1),
.VAR6(0),
.VAR37(0... | gpl-3.0 |
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner | projects/X5000_ztexmerge/hdl/sha256_pipes2.v | 5,478 | module MODULE1 ( clk, VAR21, VAR14, out );
parameter VAR24 = 64;
input clk;
input [255:0] VAR21;
input [511:0] VAR14;
output [255:0] out;
localparam VAR10 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550... | gpl-3.0 |
James534/SubZero | SubZero/fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_jtag_uart.v | 17,138 | module MODULE3 (
clk,
VAR35,
VAR30,
VAR14,
VAR49,
VAR2,
VAR5
)
;
output VAR14;
output [ 7: 0] VAR49;
output VAR2;
output [ 5: 0] VAR5;
input clk;
input [ 7: 0] VAR35;
input VAR30;
wire VAR14;
wire [ 7: 0] VAR49;
wire VAR2;
wire [ 5: 0] VAR5;
always @(posedge clk)
begin
if (VAR30)
("%VAR20", VAR35);
end
assign VAR5 = {6... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2.functional.pp.v | 1,774 | module MODULE1 (
VAR9 ,
VAR13 ,
VAR7 ,
VAR6,
VAR10,
VAR2 ,
VAR5
);
output VAR9 ;
input VAR13 ;
input VAR7 ;
input VAR6;
input VAR10;
input VAR2 ;
input VAR5 ;
wire VAR3 ;
wire VAR12;
or VAR4 (VAR3 , VAR7, VAR13 );
VAR1 VAR11 (VAR12, VAR3, VAR6, VAR10);
buf VAR8 (VAR9 , VAR12 );
endmodule | apache-2.0 |
secworks/aes | src/rtl/aes.v | 8,503 | module MODULE1(
input wire clk,
input wire VAR33,
input wire VAR31,
input wire VAR27,
input wire [7 : 0] address,
input wire [31 : 0] VAR39,
output wire [31 : 0] VAR62
);
localparam VAR10 = 8'h00;
localparam VAR42 = 8'h01;
localparam VAR2 = 8'h02;
localparam VAR57 = 8'h08;
localparam VAR52 = 0;
localparam VAR19 = 1;
lo... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_l_pp_pg_s/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg_s.blackbox.v | 1,361 | module MODULE1 (
VAR4,
VAR3 ,
VAR1 ,
VAR5 ,
VAR2
);
output VAR4;
input VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
chebykinn/university | circuitry/lab3/src/hdl/id_stage.v | 6,269 | module MODULE1( input clk, rst,
input VAR60,
input [4:0] VAR55, input [31:0] VAR26, input [31:0] VAR12, VAR56,
input [1:0] VAR46, VAR48, input [31:0] VAR8, VAR29,
input VAR49,
input VAR37,
output [4:0] VAR51,
output [4:0] VAR1,
output [5:0] VAR18,
output reg [31:0] VAR57,
output reg [31:0] VAR3,
output reg [4:0] VAR17,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4b/sky130_fd_sc_hd__nor4b_1.v | 2,302 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR11 ,
VAR9 ,
VAR1 ,
VAR8,
VAR10,
VAR2 ,
VAR3
);
output VAR6 ;
input VAR4 ;
input VAR11 ;
input VAR9 ;
input VAR1 ;
input VAR8;
input VAR10;
input VAR2 ;
input VAR3 ;
VAR7 VAR5 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.... | apache-2.0 |
mbus/mbus | releases/mbus_example-v1.2/verilog/mbus_swapper.v | 3,042 | module MODULE1
(
input VAR5,
input VAR2,
input VAR4,
input VAR12,
output reg VAR7,
output reg VAR14
);
wire VAR6;
wire VAR16;
reg VAR3; reg VAR11; reg VAR1;
reg VAR9;
reg VAR13;
reg VAR10;
wire VAR15; wire VAR8;
assign VAR6 = ~( VAR5 && VAR2);
always @(posedge VAR4 or posedge VAR6) begin
if (VAR6) begin
VAR3 = 0;
VAR1 ... | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_ll_fifo.v | 3,467 | module MODULE1(clk, reset, VAR17, write, VAR2, read, VAR14, VAR4, VAR18);
parameter VAR16 = 32;
parameter VAR12 = 32;
parameter VAR8 = 0;
input clk;
input reset;
input [VAR16-1:0] VAR17;
input write;
output [VAR16-1:0] VAR2;
input read;
output VAR14;
output VAR4;
output VAR18;
reg [VAR12:0] VAR7;
reg [VAR12:0] VAR5 ;
r... | mit |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/write_burst_control.v | 12,555 | module MODULE1 (
clk,
reset,
VAR32,
VAR25,
VAR16,
VAR22,
VAR48,
ready,
valid,
VAR10,
VAR42,
VAR38,
VAR43,
VAR34,
VAR30,
VAR19,
VAR4,
VAR23,
VAR24,
VAR44,
VAR14,
VAR5,
VAR31,
VAR6
);
parameter VAR2 = 1; parameter VAR11 = 3;
parameter VAR39 = 4;
parameter VAR33 = 2;
parameter VAR29 = 32;
parameter VAR8 = 32;
parameter VA... | gpl-3.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/iface/ip/mem_window/mem_window.v | 2,467 | module MODULE1 (
clk,
reset,
VAR22,
VAR9,
VAR12,
VAR4,
VAR30,
VAR1,
VAR26,
VAR11,
VAR6,
VAR33,
VAR10,
VAR8,
VAR23,
VAR7,
VAR25,
VAR20,
VAR17,
VAR19,
VAR18,
VAR13,
VAR3
);
parameter VAR16 = 20;
parameter VAR28 = 32;
parameter VAR14 = 32;
parameter VAR27 = 1;
parameter VAR31 = 32;
localparam VAR5 = VAR21(VAR14);
localpar... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap.functional.pp.v | 1,121 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_bae_stage2.v | 6,876 | module MODULE1(
VAR13 ,
VAR15 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR14 ,
VAR10 ,
VAR1 ,
VAR2 ,
VAR8
);
input [31:0] VAR13 ;
input [15:0] VAR15 ;
input [ 8:0] VAR4 ;
input VAR5 ; input [2:0] VAR7 ; input [35:0] VAR14 ;
output [ 8:0] VAR10 ;
output [ 8:0] VAR1 ;
output VAR2 ;
output [ 3:0] VAR8 ;
reg [ 8:0] VAR10 ;
reg [ 8:0] VAR1 ;... | gpl-3.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_mul_ll_s5.v | 25,278 | module MODULE1
(
VAR44,
VAR17,
VAR23,
VAR4,
VAR14) ;
input VAR44;
input VAR17;
input [31:0] VAR23;
input [31:0] VAR4;
output [31:0] VAR14;
tri1 VAR44;
reg VAR45;
reg VAR40;
reg VAR12;
reg VAR47;
reg VAR43;
reg VAR10;
reg VAR55;
reg VAR26;
reg [9:0] VAR46;
reg [9:0] VAR48;
reg [9:0] VAR16;
reg VAR56;
reg VAR20;
reg [8:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi.functional.pp.v | 2,044 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR2 ,
VAR1 ,
VAR12 ,
VAR14,
VAR6,
VAR3 ,
VAR9
);
output VAR8 ;
input VAR11 ;
input VAR2 ;
input VAR1 ;
input VAR12 ;
input VAR14;
input VAR6;
input VAR3 ;
input VAR9 ;
wire VAR16 ;
wire VAR5 ;
wire VAR4;
and VAR17 (VAR16 , VAR11, VAR2 );
nor VAR15 (VAR5 , VAR16, VAR1, VAR12 );
VAR7 VAR1... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_tx_status.v | 1,994 | module MODULE1 (
address,
clk,
VAR4,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input VAR4;
input VAR1;
wire VAR2;
wire VAR6;
wire VAR5;
reg [ 31: 0] VAR3;
assign VAR2 = 1;
assign VAR5 = {1 {(address == 0)}} & VAR6;
always @(posedge clk or negedge VAR1)
begin
if (VAR1 == 0)
VAR3 <= 0;
end
el... | gpl-3.0 |
UA3MQJ/fpga-synth | modules/note2dds_4st_gen.v | 1,411 | module MODULE1(clk, VAR2, VAR3);
input wire clk;
input wire [6:0] VAR2;
output [31:0] VAR3;
reg [31:0] VAR4 [15:0];
reg [3:0] addr;
reg [3:0] VAR1; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr.blackbox.v | 1,277 | module MODULE1 (
VAR7,
VAR5
);
output VAR7;
input VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
supply1 VAR1;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Leer/fifo.v | 3,280 | module MODULE1 # (parameter VAR6 = 5, VAR19 = 1)(
input reset, VAR17,
input rd, wr,
input [VAR19-1:0] din,
output [VAR19-1:0] dout,
output VAR3,
output VAR8
);
wire VAR5, VAR11;
reg [VAR19-1:0] out;
assign VAR5 = wr;
assign VAR11 = rd;
reg [VAR19-1:0] VAR10[2**VAR6-1:0]; reg [VAR6-1:0] VAR13, VAR15, VAR1; reg [VAR6-1:0... | gpl-3.0 |
q3k/q3kmips | rtl/verilog/qm_control.v | 6,289 | module MODULE1(
input wire [5:0] VAR7,
input wire [5:0] VAR8,
output reg VAR6,
output reg VAR1,
output reg [3:0] VAR4,
output reg VAR2,
output reg VAR5,
output reg VAR9,
output reg VAR3
);
always @(VAR7, VAR8) begin
case (VAR7)
VAR6 = 1;
VAR1 = 0;
VAR2 = 0;
VAR5 = 0;
VAR9 = 1;
VAR3 = 0;
case (VAR8)
endcase
end
VAR6 = 0... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b_lp.v | 2,155 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3 ,
VAR4,
VAR5,
VAR7 ,
VAR8
);
output VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR4;
input VAR5;
input VAR7 ;
input VAR8 ;
VAR9 VAR1 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR2 ,
VAR6,
VAR3
);
output VAR2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand2/sky130_fd_sc_hvl__nand2.functional.v | 1,274 | module MODULE1 (
VAR4,
VAR5,
VAR6
);
output VAR4;
input VAR5;
input VAR6;
wire VAR3;
nand VAR1 (VAR3, VAR6, VAR5 );
buf VAR2 (VAR4 , VAR3 );
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp1/inband_lib/rx_buffer_inband.v | 5,365 | module MODULE1
( input VAR3,
input VAR62,
input reset, input VAR58, output [15:0] VAR2,
input VAR17,
output wire VAR15,
output reg VAR13,
input wire [3:0] VAR69,
input wire [15:0] VAR37,
input wire [15:0] VAR24,
input wire [15:0] VAR36,
input wire [15:0] VAR35,
input wire [15:0] VAR75,
input wire [15:0] VAR6,
input wir... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf_2.v | 1,993 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR1,
VAR3,
VAR7 ,
VAR5
);
output VAR6 ;
input VAR2 ;
input VAR1;
input VAR3;
input VAR7 ;
input VAR5 ;
VAR4 VAR8 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR6,
VAR2
);
output VAR6;
input VAR2;
supply1 VAR1;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o.blackbox.v | 1,389 | module MODULE1 (
VAR3 ,
VAR6,
VAR1,
VAR2,
VAR8,
VAR5
);
output VAR3 ;
input VAR6;
input VAR1;
input VAR2;
input VAR8;
input VAR5;
supply1 VAR4;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o_1.v | 2,463 | module MODULE1 (
VAR9 ,
VAR7,
VAR4,
VAR8 ,
VAR3 ,
VAR11,
VAR1,
VAR10 ,
VAR6
);
output VAR9 ;
input VAR7;
input VAR4;
input VAR8 ;
input VAR3 ;
input VAR11;
input VAR1;
input VAR10 ;
input VAR6 ;
VAR2 VAR5 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR6... | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_ic_fsm.v | 11,549 | module MODULE1(
clk, rst,
VAR6, VAR5, VAR20,
VAR15, VAR18, VAR11, VAR21, VAR17,
VAR4, VAR19, VAR14, VAR3, VAR7,
VAR16, VAR10
);
input clk;
input rst;
input VAR6;
input VAR5;
input VAR20;
input VAR15;
input VAR18;
input VAR11;
input [31:0] VAR21;
output [31:0] VAR17;
output [3:0] VAR4;
output VAR19;
output VAR14;
output... | gpl-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/io/uart/rtl/uart.v | 3,604 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR7, input wire VAR21, input wire VAR15, input wire [VAR17] addr, input wire [VAR3] VAR9, output wire [VAR3] VAR6, output wire VAR23,
output wire VAR10, output wire VAR13,
input wire VAR2, output wire VAR5 );
wire VAR22; wire VAR11; wire [VAR16] VAR20; wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen_new/sky130_fd_io__top_refgen_new.functional.v | 7,124 | module MODULE1 (VAR45, VAR27, VAR30,
VAR5, VAR29, VAR20, VAR36, VAR9, VAR10, VAR4, VAR8, VAR24,
VAR33, VAR3, VAR38, VAR35, VAR13);
output VAR45;
output VAR27;
inout VAR30;
supply1 VAR25;
supply1 VAR32;
supply1 VAR43;
supply1 VAR42;
supply1 VAR7;
supply0 VAR19;
supply0 VAR17;
supply0 VAR34;
supply1 VAR6;
supply0 VAR12;
... | apache-2.0 |
Ribeiro/sd2snes | verilog/sd2snes_obc1/main.v | 17,255 | module MODULE1(
input VAR105,
input [23:0] VAR187,
input VAR62,
input VAR218,
input VAR212,
inout [7:0] VAR208,
input VAR210,
input VAR155,
output VAR280,
output VAR167,
output VAR130,
input VAR171,
input [7:0] VAR250,
input VAR147,
input VAR188,
inout [15:0] VAR5,
output [22:0] VAR84,
output VAR256,
output VAR34,
outp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbn/sky130_fd_sc_ms__sdfbbn.behavioral.pp.v | 3,448 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR21 ,
VAR3 ,
VAR14 ,
VAR16 ,
VAR23 ,
VAR38,
VAR19 ,
VAR26 ,
VAR1 ,
VAR27
);
output VAR8 ;
output VAR11 ;
input VAR21 ;
input VAR3 ;
input VAR14 ;
input VAR16 ;
input VAR23 ;
input VAR38;
input VAR19 ;
input VAR26 ;
input VAR1 ;
input VAR27 ;
wire VAR37 ;
wire VAR17 ;
wire VAR9 ;
wire V... | apache-2.0 |
hoglet67/CoPro6502 | src/CoPro80186.v | 11,514 | module MODULE1 (
input VAR166,
output [8:2] VAR190,
input [2:1] VAR137,
output VAR78,
input VAR227,
input [2:0] VAR146,
inout [7:0] VAR219,
input VAR19,
input VAR238,
input VAR34,
output VAR45,
output VAR206,
output VAR88,
output VAR168,
output [18:0] VAR57,
inout [7:0] VAR40
);
wire clk;
wire VAR50;
wire [15:0] VAR42... | gpl-3.0 |
asicguy/gplgpu | hdl/vga/crt_fifo_logic.v | 13,705 | module MODULE1
(
input VAR97,
input VAR4,
input VAR1,
input VAR89,
input VAR12,
input VAR38,
input VAR45,
input VAR13,
input VAR39,
input VAR53,
input VAR36,
input VAR99,
input VAR96,
input VAR100,
input VAR6,
input VAR62,
input VAR10,
input VAR60,
input VAR91,
input VAR83,
input [4:0] VAR33,
input VAR95,
input [31:0] ... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/EncWidthConverter16to32.v | 7,330 | module MODULE1
(
parameter VAR24 = 16,
parameter VAR27 = 32
)
(
VAR4 ,
VAR8 ,
VAR3 ,
VAR17 ,
VAR2 ,
VAR18 ,
VAR5 ,
VAR22 ,
VAR10 ,
VAR6 ,
VAR12 ,
VAR19,
VAR11 ,
VAR20
);
input VAR4 ;
input VAR8 ;
input VAR3 ;
input [1:0] VAR17 ;
input VAR2 ;
input VAR18 ;
input VAR5 ;
input [VAR24 - 1:0] VAR22 ;
output VAR10 ;
output V... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution5/syn/verilog/matrix_mult_mac_mdEe.v | 1,805 | module MODULE1(
input clk,
input rst,
input VAR13,
input [8 - 1:0] VAR20,
input [8 - 1:0] VAR2,
input [16 - 1:0] VAR10,
output [16 - 1:0] dout);
wire signed [25 - 1:0] VAR1;
wire signed [18 - 1:0] VAR16;
wire signed [48 - 1:0] VAR4;
wire signed [43 - 1:0] VAR14;
wire signed [48 - 1:0] VAR3;
reg signed [43 - 1:0] VAR12;... | mit |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/mod_fsm_barra.v | 1,621 | module MODULE1(clk, VAR6, VAR8, VAR5, VAR11, VAR4, VAR9);
input clk, VAR6, VAR4, VAR9;
input [4:0] VAR11; output VAR8;
output reg [9:0] VAR5;
reg VAR3;
reg [2:0]state;
parameter VAR1 = 0;
parameter VAR7 = 1;
parameter VAR2 = 2;
parameter VAR10 = 429;
begin
begin
begin
begin
begin
begin
begin
end
begin | mit |
TUM-LIS/faultify | hardware/base_system/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/pDFlipFlops.v | 23,199 | module MODULE31 (VAR33,VAR30,VAR14,VAR23);
parameter VAR26=1'b0;
output VAR33;
input VAR30;
input VAR14;
input VAR23;
wire VAR10;
VAR27 VAR4 (.VAR33(VAR33),.VAR30(VAR10),.VAR14(VAR14));
xor (VAR10,VAR30,VAR23);
endmodule
module MODULE47 (VAR33,VAR30,VAR14,VAR23);
parameter VAR26 = 1'b0;
output VAR33;
input VAR30;
inpu... | gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/clk_wiz_v3_3/example_design/clk_wiz_v3_3_exdes.v | 4,761 | module MODULE1
parameter VAR11 = 100
)
( input VAR5,
input VAR3,
output VAR1,
input VAR2,
output VAR13
);
localparam VAR10 = 16;
wire VAR7 = !VAR13 || VAR2 || VAR3;
reg VAR8;
reg VAR6;
reg VAR4;
reg VAR14;
wire VAR16;
wire clk;
reg [VAR10-1:0] counter;
VAR9 VAR12
( .VAR5 (VAR5),
.VAR15 (VAR16),
.VAR2 (VAR2),
.VAR13 (VA... | gpl-2.0 |
abjordan/RECON2014 | wishbone_uart_tx/tx_port2.v | 1,629 | module MODULE1(
input wire VAR23,
input wire VAR12,
output reg VAR1,
input wire [7:0] VAR8,
input wire [3:0] VAR11,
output reg [7:0] VAR13,
input wire VAR7,
input wire VAR5,
input wire [5:0] VAR14,
output wire [5:0] VAR22,
output wire [5:0] VAR19,
input wire VAR21,
input wire VAR20,
input wire VAR17,
input wire VAR9);
... | apache-2.0 |
sh-chris110/chris | FPGA/HPS.bak/db/ip/hps_design/hps_design.v | 30,035 | module MODULE1 (
input wire VAR28, output wire [14:0] VAR55, output wire [2:0] VAR73, output wire VAR13, output wire VAR167, output wire VAR166, output wire VAR193, output wire VAR182, output wire VAR196, output wire VAR106, output wire VAR89, inout wire [31:0] VAR34, inout wire [3:0] VAR129, inout wire [3:0] VAR122, o... | gpl-2.0 |
hoglet67/CoPro6502 | src/m32632/ALIGNER.v | 12,120 | module MODULE1 ( VAR7, VAR47, VAR24, VAR8, VAR57 );
input [3:0] VAR7; input [63:0] VAR47;
input [1:0] VAR24;
output [31:0] VAR8;
output [3:0] VAR57;
reg [3:0] VAR57;
reg [7:0] VAR27,VAR51,VAR54,VAR31;
wire VAR42;
assign VAR42 = (VAR24 == 2'b11) & (VAR7[3:2] == 2'b00);
always @(VAR47 or VAR42 or VAR7)
case (VAR7[1:0])
2... | gpl-3.0 |
fpgasystems/caribou | hw/src/regex/rem_decoder.v | 3,981 | module MODULE1 #(parameter VAR30=16, VAR20=0)
(
clk,
rst, VAR33,
VAR10, VAR26, VAR25, VAR24,
VAR21,
VAR27,
VAR16,
VAR19,
VAR9, VAR31, VAR22 );
input clk;
input rst;
input VAR33;
input [VAR30*8-1:0] VAR10;
input [(VAR30/2)-1:0] VAR26;
input [VAR30-1:0] VAR25;
input VAR24;
input VAR21;
input [7:0] VAR27;
input VAR16;
out... | gpl-3.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodGPIO_v1_0/src/PmodGPIO.v | 9,725 | module MODULE1
(VAR34,
VAR102,
VAR148,
VAR61,
VAR37,
VAR93,
VAR57,
VAR160,
VAR15,
VAR88,
VAR96,
VAR147,
VAR30,
VAR46,
VAR69,
VAR91,
VAR104,
VAR131,
VAR47,
VAR162,
VAR27,
VAR78,
VAR33,
VAR2,
VAR156,
VAR25,
VAR116,
VAR13,
VAR64,
VAR111,
VAR142,
VAR146,
VAR143,
VAR41,
VAR77,
VAR100,
VAR109,
VAR87,
VAR39,
VAR95,
VAR1,
VAR8... | bsd-3-clause |
Murailab-arch/magukara | cores/fifo72togmii/rtl/fifo72togmii.v | 1,908 | module MODULE1 (
input VAR7,
input [71:0] dout,
input VAR6,
output reg VAR5,
output VAR4,
input VAR1,
output VAR2,
output [7:0] VAR3
);
assign VAR4 = VAR1;
reg [2:0] VAR9 = 3'h0;
reg [7:0] VAR8;
reg VAR10;
always @(posedge VAR1) begin
if (VAR7) begin
VAR9 <= 3'h0;
end else begin
VAR10 <= 1'b0;
if (VAR5 == 1'b1 || VAR9 ... | gpl-3.0 |
tloinuy/opencpi-opencv | opencpi/components/wbr.hdl/mkRcvrWorker.v | 46,269 | module MODULE1(VAR189,
VAR346,
VAR3,
VAR153,
VAR311,
VAR179,
VAR15,
VAR23,
VAR2,
VAR350,
VAR300,
VAR36,
VAR320);
input VAR189;
input VAR346;
input VAR3;
input VAR153;
input [52 : 0] VAR311;
output [33 : 0] VAR179;
output VAR15;
output [1 : 0] VAR23;
input [1 : 0] VAR2;
input [35 : 0] VAR350;
output VAR300;
output [49 :... | gpl-2.0 |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/verilog/bitset_next.v | 19,747 | module MODULE1 (
VAR40,
VAR7,
VAR6,
VAR51,
VAR23,
VAR83,
VAR59,
VAR70,
VAR61,
VAR25,
VAR18,
VAR46,
VAR67,
VAR24,
VAR34
);
parameter VAR36 = 1'b1;
parameter VAR3 = 1'b0;
parameter VAR30 = 1'b0;
parameter VAR62 = 1'b0;
parameter VAR37 = 32'b00000000000000000000000000000000;
parameter VAR49 = 1'b1;
parameter VAR63 = 2'b1;... | lgpl-3.0 |
johan92/yafpgatetris | ip_cores/ps2_keyboard/Altera_UP_PS2_Command_Out.v | 9,820 | module MODULE1 (
clk,
reset,
VAR30,
VAR20,
VAR4,
VAR14,
VAR16,
VAR26,
VAR5,
VAR23
);
parameter VAR25 = 5050;
parameter VAR6 = 13;
parameter VAR21 = 13'h0001;
parameter VAR9 = 750000;
parameter VAR31 = 20;
parameter VAR33 = 20'h00001;
parameter VAR10 = 100000;
parameter VAR2 = 17;
parameter VAR27 = 17'h00001;
input clk;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211a/sky130_fd_sc_hd__o211a.blackbox.v | 1,360 | module MODULE1 (
VAR7 ,
VAR2,
VAR8,
VAR5,
VAR1
);
output VAR7 ;
input VAR2;
input VAR8;
input VAR5;
input VAR1;
supply1 VAR3;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/decoder_ip_export/src/decoder_axi_s_v1_0.v | 2,523 | module MODULE1 #
(
parameter integer VAR24 = 32,
parameter integer VAR1 = 5
)
(
output wire [VAR24-1:0] VAR41,
output wire [VAR24-1:0] VAR39,
output wire VAR25,
input wire VAR23,
input wire VAR9,
input wire VAR32,
input wire [VAR1-1 : 0] VAR38,
input wire [2 : 0] VAR33,
input wire VAR18,
output wire VAR49,
input wire [... | gpl-3.0 |
iAklis/teoca | EXPR4_ALU_REGISTERS/MAIN.v | 3,450 | module MODULE2(
input clk,
input wire [4:0] VAR19,
input wire [4:0] VAR8,
input wire [4:0] VAR2,
input VAR20,
input VAR11,
input [2:0] VAR18,
output wire [31:0] VAR6,VAR15,
output wire [31:0] VAR3,
output VAR7, VAR12
);
wire [31:0] VAR1;
MODULE1 VAR5 (
.clk(clk),
.VAR20(VAR20),
.VAR19(VAR19),
.VAR8(VAR8),
.VAR2(VAR2),
... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/pulse_synchronizer.v | 3,190 | module MODULE1
( input VAR8,
input VAR6,
output VAR15,
input VAR13,
input VAR3,
input VAR10
);
reg VAR5;
reg VAR12;
reg VAR4;
reg VAR7;
reg VAR1;
reg VAR2;
reg VAR14;
reg VAR11;
reg VAR9;
always @(posedge VAR6) begin
if(VAR3) begin
VAR5 <= 0;
end
else if(!VAR14 & VAR8) begin
VAR5 <= 1;
end
else if(VAR2) begin
VAR5 <= 0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o.behavioral.v | 1,662 | module MODULE1 (
VAR17 ,
VAR8,
VAR10,
VAR3,
VAR5,
VAR12
);
output VAR17 ;
input VAR8;
input VAR10;
input VAR3;
input VAR5;
input VAR12;
supply1 VAR15;
supply0 VAR9;
supply1 VAR13 ;
supply0 VAR2 ;
wire VAR7 ;
wire VAR1 ;
wire VAR4;
and VAR11 (VAR7 , VAR3, VAR5 );
and VAR6 (VAR1 , VAR8, VAR10 );
or VAR14 (VAR4, VAR1, VAR... | apache-2.0 |
skarpenko/ultiparc | rtl/src/dbus2ocp.v | 2,537 | module MODULE1(
VAR14,
VAR10,
VAR17,
VAR24,
VAR8,
VAR13,
VAR1,
VAR15,
VAR6,
VAR12,
VAR20,
VAR18,
VAR2,
VAR3,
VAR21
);
input wire [VAR23-1:0] VAR14;
input wire VAR10;
input wire VAR17;
input wire [VAR22-1:0] VAR24;
input wire [VAR9-1:0] VAR8;
output reg [VAR9-1:0] VAR13;
output reg VAR1;
output reg VAR15;
output reg [VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfstp/sky130_fd_sc_hs__sdfstp.functional.pp.v | 2,021 | module MODULE1 (
VAR12 ,
VAR17 ,
VAR10 ,
VAR14 ,
VAR9 ,
VAR1 ,
VAR8 ,
VAR4
);
input VAR12 ;
input VAR17 ;
output VAR10 ;
input VAR14 ;
input VAR9 ;
input VAR1 ;
input VAR8 ;
input VAR4;
wire VAR2 ;
wire VAR15 ;
wire VAR5;
not VAR16 (VAR15 , VAR4 );
VAR18 VAR7 (VAR5, VAR9, VAR1, VAR8 );
VAR13 VAR3 VAR6 (VAR2 , VAR5, VAR... | apache-2.0 |
jz0229/open-ephys-pcie | kc705-host-firmware/Sources/Verilog/pcie_k7_vivado_pipe_clock.v | 21,845 | module MODULE1 #
(
parameter VAR40 = "VAR106", parameter VAR38 = "VAR106", parameter VAR72= "VAR106", parameter VAR115 = 1, parameter VAR149 = 3, parameter VAR137 = 0, parameter VAR4 = 2, parameter VAR21 = 2, parameter VAR46 = 1, parameter VAR1 = 0
)
(
input VAR28,
input VAR142,
input [VAR115-1:0] VAR70,
input VAR87,
i... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/mem_reg.v | 5,190 | module MODULE1 (
input wire clk,
input wire reset,
input wire [VAR32] out,
input wire VAR26,
input wire VAR22,
input wire VAR21,
input wire [VAR28] VAR25,
input wire VAR27,
input wire VAR8,
input wire [VAR12] VAR23,
input wire [VAR15] VAR11,
input wire VAR18,
input wire [VAR33] VAR3,
output reg [VAR28] VAR13,
output re... | apache-2.0 |
ptracton/wb_soc_template | rtl/ALTERA/wb_ram_32x8192.v | 7,402 | module MODULE1 (
address,
VAR23,
VAR42,
VAR5,
VAR40,
VAR21);
input [12:0] address;
input [3:0] VAR23;
input VAR42;
input [31:0] VAR5;
input VAR40;
output [31:0] VAR21;
tri1 [3:0] VAR23;
tri1 VAR42;
wire [31:0] VAR7;
wire [31:0] VAR21 = VAR7[31:0];
VAR25 VAR27 (
.VAR54 (address),
.VAR47 (VAR23),
.VAR39 (VAR42),
.VAR15 (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep.pp.symbol.v | 1,510 | module MODULE1 (
input VAR3 ,
output VAR9 ,
input VAR8 ,
input VAR6,
input VAR2,
input VAR5 ,
input VAR7 ,
input VAR4 ,
input VAR1
);
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_mem_asym.v | 5,185 | module MODULE1 (
VAR14,
VAR10,
VAR7,
VAR11,
VAR6,
VAR4,
VAR2);
parameter VAR12 = 10;
parameter VAR9 = 256;
parameter VAR3 = 8;
parameter VAR1 = 64;
localparam VAR13 = 2**VAR12;
localparam VAR8 = 2**VAR3;
localparam VAR5 = (VAR13 > VAR8) ? VAR13 : VAR8;
localparam VAR16 = VAR9/VAR1;
input VAR14;
input VAR10;
input [VAR1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai.behavioral.pp.v | 2,086 | module MODULE1 (
VAR13 ,
VAR2 ,
VAR16 ,
VAR3 ,
VAR1 ,
VAR18 ,
VAR4,
VAR14,
VAR7 ,
VAR15
);
output VAR13 ;
input VAR2 ;
input VAR16 ;
input VAR3 ;
input VAR1 ;
input VAR18 ;
input VAR4;
input VAR14;
input VAR7 ;
input VAR15 ;
wire VAR8 ;
wire VAR11 ;
wire VAR17;
or VAR9 (VAR8 , VAR16, VAR2 );
nand VAR10 (VAR11 , VAR1, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp.blackbox.v | 1,312 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR9 ,
VAR5 ,
VAR1
);
output VAR8 ;
input VAR7 ;
input VAR9 ;
input VAR5 ;
input VAR1;
supply1 VAR6;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2b/sky130_fd_sc_hdll__or2b.blackbox.v | 1,274 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR4;
supply1 VAR1;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3b/sky130_fd_sc_hs__nor3b.pp.symbol.v | 1,308 | module MODULE1 (
input VAR3 ,
input VAR5 ,
input VAR1 ,
output VAR2 ,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3/sky130_fd_sc_hdll__nor3.behavioral.pp.v | 1,862 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR2 ,
VAR14 ,
VAR9,
VAR8,
VAR12 ,
VAR3
);
output VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR14 ;
input VAR9;
input VAR8;
input VAR12 ;
input VAR3 ;
wire VAR13 ;
wire VAR7;
nor VAR1 (VAR13 , VAR14, VAR5, VAR2 );
VAR6 VAR11 (VAR7, VAR13, VAR9, VAR8);
buf VAR10 (VAR4 , VAR7 );
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ddr3_source/phy/mig_7series_v1_9_ddr_phy_top.v | 66,896 | module MODULE1 #
(
parameter VAR138 = 100, parameter VAR293 = "0", parameter VAR27 = 3, parameter VAR17 = "8", parameter VAR140 = "VAR167", parameter VAR124 = "VAR40", parameter VAR387 = 1, parameter VAR297 = 5,
parameter VAR303 = 12, parameter VAR68 = 1, parameter VAR102 = 1, parameter VAR137 = 5,
parameter VAR286 = 8... | gpl-2.0 |
ptracton/Picoblaze | projects/basic/rtl/system_controller.v | 7,033 | module MODULE1(
input VAR44,
input VAR15,
output VAR48,
output VAR38
);
reg [4:0] VAR58 = 4'h00;
wire VAR18;
VAR39 VAR4(.VAR11(VAR44), .VAR34(VAR18));
wire VAR55;
assign VAR38 = VAR15;
VAR6 VAR56 (
.VAR34(VAR48), .VAR11(VAR62) );
VAR45 #(
.VAR43("VAR60"),
.VAR61(6.0),
.VAR59(0.0),
.VAR21(10.0),
.VAR2(1),
.VAR49(1),
.VA... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Lundgren FPU/branches/avendor/fpu_exceptions.v | 9,224 | module MODULE1( clk, rst, enable, VAR3, VAR21, VAR23, VAR5,
VAR14, VAR55, VAR1, out, VAR56, VAR12, VAR9,
VAR43, VAR68, VAR52);
input clk;
input rst;
input enable;
input [1:0] VAR3;
input [63:0] VAR21;
input [63:0] VAR23;
input [63:0] VAR5;
input [11:0] VAR14;
input [1:0] VAR55;
input [2:0] VAR1;
output [63:0] out;
outp... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/packet_buffer.v | 5,794 | module MODULE1(
input clk,
input reset,
output [239:0] VAR8,
input [63:0] VAR16,
input [15:0] VAR9,
input VAR23,
output reg VAR10,
input VAR24,
output reg VAR13,
output reg [63:0] VAR12,
output reg [15:0] VAR4,
output reg VAR28,
output reg VAR25,
input VAR30,
output reg [1:0] VAR7,
output reg VAR41,
output reg VAR27,
i... | mit |
cliffordwolf/picorv32 | picosoc/ice40up5k_spram.v | 2,290 | module MODULE1 #(
parameter integer VAR17 = 32768
) (
input clk,
input [3:0] VAR10,
input [21:0] addr,
input [31:0] VAR4,
output [31:0] VAR1
);
wire VAR21, VAR12;
wire [31:0] VAR23, VAR5;
assign VAR21 = !addr[14];
assign VAR12 = addr[14];
assign VAR1 = addr[14] ? VAR5 : VAR23;
VAR8 VAR14 (
.VAR15(addr[13:0]),
.VAR11(VA... | isc |
TonyBrewer/OpenHT | ht_lib/platform/convey/verilog/dispatch.v | 5,203 | module MODULE1 #(parameter
VAR56 = 0,
VAR51 = 0
)(
input clk,
input VAR41,
input reset,
input VAR59,
input [4:0] VAR18,
input [17:0] VAR21,
input VAR44,
input VAR57,
input [63:0] VAR3,
output [17:0] VAR23,
output [15:0] VAR38,
output [63:0] VAR49,
output VAR61,
output VAR22,
output VAR63,
input [3:0] VAR10,
input [7:0]... | bsd-3-clause |
sudov/options-accel | final_design/fifo.prj/sol/impl/pcores/dut_top_v1_04_a/synhdl/verilog/dut_top.v | 1,160 | module MODULE1 (
VAR3,
VAR1,
VAR10,
VAR16,
VAR6,
VAR2,
VAR14,
VAR15
);
parameter VAR4 = 1;
input VAR3 ;
input VAR1 ;
input [32 - 1:0] VAR10 ;
input VAR16 ;
output VAR6 ;
output [32 - 1:0] VAR2 ;
input VAR14 ;
output VAR15 ;
wire VAR3;
wire VAR9;
VAR5 VAR11(
.VAR7(VAR9),
.VAR8(VAR1),
.VAR10(VAR10),
.VAR16(VAR16),
.VAR6(... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/global_reset.v | 1,746 | module MODULE1(
input VAR1,
input VAR3, output VAR2, output VAR5 );
reg [7:0] VAR4 = 1;
assign VAR2 = (VAR4 <= 1) & !VAR3;
assign VAR5 = (VAR4 <= 1);
always @(negedge VAR1)
if( VAR4 != 0 )
VAR4 <= VAR4 + 1'd1;
endmodule | gpl-3.0 |
ptracton/pmodacl2 | soc/display/pb_display.v | 3,312 | module MODULE1 (
VAR20, VAR19, VAR15,
clk, reset, VAR1, VAR12, VAR3, VAR18,
VAR9, VAR11
) ;
parameter VAR22 = 8'h00;
input clk;
input reset;
input [7:0] VAR1;
input [7:0] VAR12;
output [7:0] VAR20;
input VAR3;
input VAR18;
output [3:0] VAR19;
output [7:0] VAR15;
input wire [15:0] VAR9;
input wire VAR11;
wire [7:0] VAR5... | mit |
jhol/butterflylogic | rtl/spi_slave.v | 4,010 | module MODULE1 (
input wire clk,
input wire rst,
input wire VAR10,
input wire [31:0] VAR27,
input wire [3:0] VAR18,
input wire [31:0] VAR14,
output wire [39:0] VAR23,
output wire VAR22,
output wire VAR4,
input wire VAR28,
input wire VAR12,
input wire VAR29,
output wire VAR9
);
reg VAR21;
reg VAR13;
reg VAR8;
reg VAR11;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcon/sky130_fd_sc_lp__fahcon_1.v | 2,412 | module MODULE1 (
VAR11,
VAR4 ,
VAR3 ,
VAR8 ,
VAR1 ,
VAR2 ,
VAR9 ,
VAR6 ,
VAR5
);
output VAR11;
output VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR9 ;
input VAR6 ;
input VAR5 ;
VAR10 VAR7 (
.VAR11(VAR11),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.... | apache-2.0 |
srjet/mips-verilog | instruction_mem/instr_mem.v | 1,378 | module MODULE1 ( input [31:0] address,
output [31:0] VAR1 );
reg [31:0] memory [249:0];
integer VAR2;
begin | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_INVBUF_RVT_TT_210930.v | 14,915 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
buf (VAR2, VAR1); | bsd-3-clause |
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