text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/pm/pm.h>
#include <zephyr/pm/policy.h>
#include <driverlib/pwr_ctrl.h>
#include <driverlib/sys_ctrl.h>
#include <ti/drivers/Power.h>
#include <ti/drivers/power/PowerCC26X2.h>
#include <ti/drivers/dpl/ClockP.h>
#include <ti/devices/c... | /content/code_sandbox/soc/ti/simplelink/cc13x2_cc26x2/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,247 |
```linker script
/*
* Organisation (CSIRO) ABN 41 687 119 230.
*
*/
GROUP_START(FLASH_CCFG)
SECTION_PROLOGUE(.ti_ccfg,,)
{
KEEP(*(_TI_CCFG_SECTION_NAME))
} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(ti_ccfg_partition)))
GROUP_END(FLASH_CCFG)
``` | /content/code_sandbox/soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
# Texas Instruments SimpleLink CC13x2 / CC26x2
config SOC_SERIES_CC13X2X7_CC26X2X7
bool
select SOC_FAMILY_TI_SIMPLELINK
help
Enable support for TI SimpleLink CC13x2x7 / CC26x2x7 SoCs
config SOC_CC1352P7
bool
select SOC_SERIES_CC13X2X7_CC26X2X7
help
CC1352P7
config SOC_CC1352R7
bool
select SO... | /content/code_sandbox/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 315 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <driverlib/setup.h>
static int ti_cc13x7_cc26x7_init(void)
{
/* Performs necessary trim of the device. */
SetupTrimDevice();
return 0;
}
SYS_INIT(ti_cc13x7_cc26x7_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```objective-c
/*
*
*/
#include "../cc13x2_cc26x2/pinctrl_soc.h"
``` | /content/code_sandbox/soc/ti/simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```c
/*
*
*/
#ifdef CONFIG_CC13X2_CC26X2_BOOST_MODE
#define CCFG_FORCE_VDDR_HH 1
#endif
#ifdef CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE
#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5
#else
#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00
#endif /* CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE */
#ifdef CONFIG_CC13X2_CC... | /content/code_sandbox/soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 349 |
```objective-c
/*
*
*/
#include "../cc13x2_cc26x2/soc.h"
``` | /content/code_sandbox/soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 18 |
```unknown
# Texas Instruments SimpleLink CC13x2 / CC26x2
if SOC_SERIES_CC13X2X7_CC26X2X7
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
# Note that when using the RTC as system clock, this needs to be 32768
# to reduce truncation errors from accumulating due to conversion to/from
# time, ticks, and HW cycles
con... | /content/code_sandbox/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 265 |
```unknown
# Texas Instruments SimpleLink CC13x2 / CC26x2
config SOC_SERIES_CC13X2X7_CC26X2X7
bool
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select DYNAMIC_INTERRUPTS
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select HAS_CC13X2X7_CC26X2X7_SDK
select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT
select ... | /content/code_sandbox/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 563 |
```unknown
# TI SimpleLink CC32xx
config SOC_SERIES_CC32XX
bool
select SOC_FAMILY_TI_SIMPLELINK
help
Enable support for TI SimpleLink CC32xx
config SOC_CC3220SF
bool
select SOC_SERIES_CC32XX
help
CC3220SF
config SOC_CC3235SF
bool
select SOC_SERIES_CC32XX
help
CC3235SF
config SOC_SERIES
default "c... | /content/code_sandbox/soc/ti/simplelink/cc32xx/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```linker script
/*
*
*/
/* Add CC32xx flash header to disable flash verification */
. = 0x0;
KEEP(*(.dbghdr))
KEEP(*(".dbghdr.*"))
``` | /content/code_sandbox/soc/ti/simplelink/cc32xx/cc32xx_debug.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
# TI SimpleLink CC3235SF SoC
if SOC_CC3235SF
config NUM_IRQS
# must be >= the highest interrupt number used
# This includes the NWP interrupt
default 179
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 80000000
config ROM_START_OFFSET
default 0x800 if XIP
default 0x0 if !XIP
endif # SOC_CC3235SF
``` | /content/code_sandbox/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3235sf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```unknown
# TI SimpleLink CC3220SF SoC
if SOC_CC3220SF
config NUM_IRQS
# must be >= the highest interrupt number used
# This includes the NWP interrupt
default 178
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 80000000
config ROM_START_OFFSET
default 0x800 if XIP
default 0x0 if !XIP
endif # SOC_CC3220SF
``` | /content/code_sandbox/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3220sf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/pm/pm.h>
#include <zephyr/pm/policy.h>
#include <driverlib/pwr_ctrl.h>
#include <driverlib/sys_ctrl.h>
#include <ti/drivers/Power.h>
#include <ti/drivers/power/PowerCC26X2.h>
#include <ti/drivers/dpl/ClockP.h>
#include <ti/devices/c... | /content/code_sandbox/soc/ti/simplelink/cc13x2x7_cc26x2x7/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,323 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <driverlib/rom.h>
#include <driverlib/rom_map.h>
#include <driverlib/prcm.h>
/* Overrides the weak ARM implementation */
void sys_arch_reboot(int type)
{
MAP_PRCMMCUReset(!!type);
}
static int ti_... | /content/code_sandbox/soc/ti/simplelink/cc32xx/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 212 |
```objective-c
/*
*
*/
#ifndef TI_SIMPLELINK_CC32XX_SOC_H_
#define TI_SIMPLELINK_CC32XX_SOC_H_
#include <zephyr/arch/arm/cortex_m/nvic.h>
#include <inc/hw_types.h>
#include <driverlib/prcm.h>
/*
* CMSIS IRQn_Type enum is broken relative to ARM GNU compiler.
*
* So redefine the IRQn_Type enum to a unsigned int ... | /content/code_sandbox/soc/ti/simplelink/cc32xx/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 326 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_ARM_TI_SIMPLELINK_CC32XX_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_TI_SIMPLELINK_CC32XX_PINCTRL_SOC_H_
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
/** Type for TI CC32XX pin... | /content/code_sandbox/soc/ti/simplelink/cc32xx/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 533 |
```unknown
# TI SimpleLink Family
if SOC_SERIES_CC32XX
rsource "Kconfig.defconfig.cc32*"
endif # SOC_SERIES_CC32XX
``` | /content/code_sandbox/soc/ti/simplelink/cc32xx/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
# Texas Instruments CC32XX
config SOC_SERIES_CC32XX
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select DYNAMIC_INTERRUPTS
config SOC_CC3220SF
select HAS_CC3220SDK
config SOC_CC3235SF
select HAS_CC3220SDK
config CC3220SF_DEBUG
bool "Prepend debug header, disabling flash verification... | /content/code_sandbox/soc/ti/simplelink/cc32xx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```unknown
CC3220 Info taken from:
* path_to_url
CC3235 Info taken from:
* path_to_url
Notes for CC32XXSF:
* Text must start at 0x800 offset in flash. The first 0x800 bytes are
reserved for the flash header.
* See CONFIG_ROM_START_OFFSET.
``` | /content/code_sandbox/soc/ti/simplelink/cc32xx/README | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
config SOC_ARC_HSDK
bool
config SOC
default "arc_hsdk" if SOC_ARC_HSDK
``` | /content/code_sandbox/soc/snps/hsdk/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```yaml
series:
- name: arc_hsdk
socs:
- name: arc_hsdk
``` | /content/code_sandbox/soc/snps/hsdk/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
config SOC_ARC_HSDK
select ARC
select CPU_HAS_FPU
``` | /content/code_sandbox/soc/snps/hsdk/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 18 |
```linker script
/*
*
*/
/**
* @brief Linker script for the HS Development Kit
*/
#include <zephyr/devicetree.h>
/*
* SRAM base address and size
*/
#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
#define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#defin... | /content/code_sandbox/soc/snps/hsdk/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```unknown
config SOC_ARC_IOT
bool
help
Synopsys ARC IoT SoC
config SOC
default "arc_iot" if SOC_ARC_IOT
``` | /content/code_sandbox/soc/snps/arc_iot/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
if SOC_ARC_HSDK
config CPU_HS3X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 2 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default 88
config RGF_NUM_BANKS
default 2
... | /content/code_sandbox/soc/snps/hsdk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 193 |
```yaml
series:
- name: arc_iot
socs:
- name: arc_iot
``` | /content/code_sandbox/soc/snps/arc_iot/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```objective-c
/*
*
*/
#ifndef _ARC_IOT_SYSCONF_H_
#define _ARC_IOT_SYSCONF_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct sysconf_reg {
volatile uint32_t reserved1; /* 0x0 */
volatile uint32_t AHBCLKDIV; /* AHB clock divisor */
volatile uint32_t APBCLKDIV; /* APB clock divisor ... | /content/code_sandbox/soc/snps/arc_iot/sysconf.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,763 |
```c
/*
*
*/
/**
* This module provides routines to initialize and support soc-level hardware
* for the IoT Development Kit board.
*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include "sysconf.h"
#define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
static int arc_iot_init(void)
{
if (... | /content/code_sandbox/soc/snps/arc_iot/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```unknown
if SOC_ARC_IOT
config CPU_EM4_FPUS
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
config ARC_MPU_VER
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default ... | /content/code_sandbox/soc/snps/arc_iot/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 146 |
```unknown
config SOC_ARC_IOT
select ARC
select CPU_HAS_MPU
select CPU_HAS_FPU
``` | /content/code_sandbox/soc/snps/arc_iot/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```c
/*
*
*/
#include <zephyr/devicetree.h>
#include "sysconf.h"
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
#define PLL_CLK_IN (SYSCLK_DEFAULT_IOSC_HZ / 1000000) /* PLL clock in */
#define sysconf_reg_ptr ((sysconf_reg_t *)(DT_REG_ADDR(DT_NODELABEL(sysconf))))
typedef struct pll_conf ... | /content/code_sandbox/soc/snps/arc_iot/sysconf.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,566 |
```unknown
config SOC_EMSK
bool
help
Synopsys ARC EM Starter Kit SoC
config SOC_EMSK_EM7D
bool
select SOC_EMSK
help
Synopsys ARC EM7D of EMSK
config SOC_EMSK_EM9D
bool
select SOC_EMSK
help
Synopsys ARC EM9D of EMSK
config SOC_EMSK_EM11D
bool
select SOC_EMSK
help
Synopsys ARC EM11D of EMSK
co... | /content/code_sandbox/soc/snps/emsk/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 186 |
```linker script
/*
*
*/
/**
* @brief Linker script for the Synopsys ARC IoT Development Kit
*/
#include <zephyr/devicetree.h>
/*
* SRAM base address and size
*
*/
#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
#define SRAM_START DT_REG_ADDR(DT_CHOSEN(zep... | /content/code_sandbox/soc/snps/arc_iot/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 421 |
```yaml
series:
- name: emsk
socs:
- name: emsk_em7d
- name: emsk_em9d
- name: emsk_em11d
``` | /content/code_sandbox/soc/snps/emsk/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```unknown
if SOC_EMSK_EM7D
config CPU_EM4_DMIPS
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 38 if "$(BOARD_REVISION)" = ... | /content/code_sandbox/soc/snps/emsk/Kconfig.defconfig.em7d | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 320 |
```unknown
if SOC_EMSK_EM11D
config CPU_EM4_FPUDA
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 38 if "$(BOARD_REVISION)" =... | /content/code_sandbox/soc/snps/emsk/Kconfig.defconfig.em11d | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 177 |
```unknown
if SOC_EMSK_EM9D
config CPU_EM4_FPUS
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 38 if "$(BOARD_REVISION)" = "... | /content/code_sandbox/soc/snps/emsk/Kconfig.defconfig.em9d | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 160 |
```unknown
if SOC_EMSK
rsource "Kconfig.defconfig.*"
endif # SOC_EMSK
``` | /content/code_sandbox/soc/snps/emsk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```unknown
config SOC_EMSK
select ARC
config SOC_EMSK_EM7D
select CPU_HAS_MPU
config SOC_EMSK_EM9D
select CPU_HAS_FPU
config SOC_EMSK_EM11D
select CPU_HAS_FPU
``` | /content/code_sandbox/soc/snps/emsk/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```c
/*
*
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#ifdef CONFIG_UART_NS16550
static int uart_ns16550_init(void)
{
/* On ARC EM Starter kit board,
* send the UART the command to clear the interrupt
*/
#if DT_NODE_HAS_STATUS(DT_INST(0, ns16550), okay)
sys_write... | /content/code_sandbox/soc/snps/emsk/soc_config.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 269 |
```linker script
/*
*
*/
/**
* @brief Linker script for the Synopsys EM Starterkit platform.
*/
#include <zephyr/devicetree.h>
/*
* DRAM base address and size
*
* DRAM includes the exception vector table at reset, which is at
* the beginning of the region.
*/
#if DT_NODE_HAS_PROP(DT_NODELABEL(ddr0), reg) &&... | /content/code_sandbox/soc/snps/emsk/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 381 |
```unknown
if SOC_EMSDP_EM6
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 50000000
config CPU_EM6
default y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_MANAGEMENT
default y
config FP_FPU_DA
default n
config MAIN_STACK_SIZE
d... | /content/code_sandbox/soc/snps/emsdp/Kconfig.defconfig.em6 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```unknown
config SOC_ARC_EMSDP
bool
config SOC_EMSDP_EM4
bool
select SOC_ARC_EMSDP
help
Synopsys ARC EM4 of EMSDP
config SOC_EMSDP_EM5D
bool
select SOC_ARC_EMSDP
help
Synopsys ARC EM5D of EMSDP
config SOC_EMSDP_EM6
bool
select SOC_ARC_EMSDP
help
Synopsys ARC EM6 of EMSDP
config SOC_EMSDP_EM7D
... | /content/code_sandbox/soc/snps/emsdp/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 383 |
```unknown
if SOC_EMSDP_EM7D
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 40000000
config CPU_EM4_FPUDA
default y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_MANAGEMENT
default y
config FP_FPU_DA
default y
config MAIN_STACK_... | /content/code_sandbox/soc/snps/emsdp/Kconfig.defconfig.em7d | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 148 |
```unknown
if SOC_EMSDP_EM7D_ESP
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 50000000
config CPU_EM4_FPUDA
default y
config ARC_MPU_VER
default 4
config RGF_NUM_BANKS
default 1
config HARVARD
default y
config ARC_FIRQ
default n
config CACHE_MANAGEMENT
default y
config FP_FPU_DA
default y
config NUM_IRQ... | /content/code_sandbox/soc/snps/emsdp/Kconfig.defconfig.em7d_esp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```unknown
if SOC_EMSDP_EM4
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 50000000
config CPU_EM4
default y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_MANAGEMENT
default n
config FP_FPU_DA
default n
config MAIN_STACK_SIZE
d... | /content/code_sandbox/soc/snps/emsdp/Kconfig.defconfig.em4 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```yaml
series:
- name: emsdp
socs:
- name: emsdp_em4
- name: emsdp_em5d
- name: emsdp_em6
- name: emsdp_em7d
- name: emsdp_em7d_esp
- name: emsdp_em9d
- name: emsdp_em11d
``` | /content/code_sandbox/soc/snps/emsdp/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```unknown
if SOC_EMSDP_EM11D
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 40000000
config CPU_EM4_FPUDA
default y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_MANAGEMENT
default y
config FP_FPU_DA
default y
config MAIN_STACK... | /content/code_sandbox/soc/snps/emsdp/Kconfig.defconfig.em11d | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 148 |
```unknown
if SOC_EMSDP_EM9D
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 40000000
config CPU_EM4_FPUDA
default y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_MANAGEMENT
default n
config FP_FPU_DA
default y
config MAIN_STACK_... | /content/code_sandbox/soc/snps/emsdp/Kconfig.defconfig.em9d | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 148 |
```unknown
if SOC_EMSDP_EM5D
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 40000000
config CPU_EM4_FPUDA
default y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_MANAGEMENT
default n
config FP_FPU_DA
default y
config MAIN_STACK_... | /content/code_sandbox/soc/snps/emsdp/Kconfig.defconfig.em5d | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 148 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARC_SNPS_EMSDP_PINCTRL_H_
#define ZEPHYR_SOC_ARC_SNPS_EMSDP_PINCTRL_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
typedef struct pinctrl_soc_pin_t {
uint8_t pin;
uint8_t type;
} pinctrl_soc_pin_t;
#define EMSDP_DT_PIN(node_id) \
{ \
.pin = DT_... | /content/code_sandbox/soc/snps/emsdp/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 229 |
```unknown
if SOC_ARC_EMSDP
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
rsource "Kconfig.defconfig.*"
endif # SOC_ARC_EMSDP
``` | /content/code_sandbox/soc/snps/emsdp/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
config SOC_ARC_EMSDP
select ARC
config SOC_EMSDP_EM4
select CPU_HAS_MPU
config SOC_EMSDP_EM5D
select CPU_HAS_MPU
select CPU_HAS_FPU
config SOC_EMSDP_EM6
select CPU_HAS_MPU
config SOC_EMSDP_EM7D
select CPU_HAS_MPU
select CPU_HAS_FPU
config SOC_EMSDP_EM7D_ESP
select CPU_HAS_MPU
select CPU_HAS_FP... | /content/code_sandbox/soc/snps/emsdp/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```linker script
/*
*
*/
/**
* @brief Linker script for the Synopsys ARC IoT Development Kit
*/
#include <zephyr/devicetree.h>
/*
* SRAM base address and size
*
*/
#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
#define SRAM_START DT_REG_ADDR(DT_CHOSEN(zep... | /content/code_sandbox/soc/snps/emsdp/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 367 |
```unknown
config SOC_QEMU_ARC
bool
config SOC_QEMU_ARC_EM
bool
select SOC_QEMU_ARC
config SOC_QEMU_ARC_HS
bool
select SOC_QEMU_ARC
config SOC_QEMU_ARC_HS5X
bool
select SOC_QEMU_ARC
config SOC_QEMU_ARC_HS6X
bool
select SOC_QEMU_ARC
config SOC_SERIES
default "qemu_arc" if SOC_QEMU_ARC
config SOC
defaul... | /content/code_sandbox/soc/snps/qemu_arc/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 172 |
```yaml
series:
- name: qemu_arc
socs:
- name: qemu_arc_em
- name: qemu_arc_hs
- name: qemu_arc_hs5x
- name: qemu_arc_hs6x
``` | /content/code_sandbox/soc/snps/qemu_arc/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
config SOC_QEMU_ARC
select ARC
select CPU_HAS_MPU
config SOC_QEMU_ARC_EM
select CPU_EM4
config SOC_QEMU_ARC_HS
select CPU_HS3X
config SOC_QEMU_ARC_HS5X
select CPU_HS5X
config SOC_QEMU_ARC_HS6X
select CPU_HS6X
``` | /content/code_sandbox/soc/snps/qemu_arc/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
if SOC_QEMU_ARC
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 10000000
config RGF_NUM_BANKS
default 1
config ARC_FIRQ
default n
config NUM_IRQ_PRIO_LEVELS
default 15
config NUM_IRQS
default 26
# Technically ARC HS supports MPUv3, but not v2. But given MPUv3
# is the same as v2 but with minimal ... | /content/code_sandbox/soc/snps/qemu_arc/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```unknown
config SOC_ARC_HSDK4XD
bool
help
Synopsys ARC HSDK4XD SoC
config SOC
default "arc_hsdk4xd" if SOC_ARC_HSDK4XD
``` | /content/code_sandbox/soc/snps/hsdk4xd/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```linker script
/*
*
*/
#include <zephyr/devicetree.h>
/*
* SRAM base address and size
*/
#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
#define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
#endif
/*
... | /content/code_sandbox/soc/snps/qemu_arc/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 198 |
```objective-c
/*
*
*/
#ifndef _ARC_HSDK4XD_SOC_CTRL_H_
#define _ARC_HSDK4XD_SOC_CTRL_H_
#ifdef _ASMLANGUAGE
.macro soc_early_asm_init_percpu
mov r0, 1 /* disable LPB for HS4XD */
sr r0, [_ARC_V2_LPB_CTRL]
.endm
#endif /* _ASMLANGUAGE */
#endif /* _ARC_HSDK4XD_SOC_CTRL_H_ */
``` | /content/code_sandbox/soc/snps/hsdk4xd/soc_ctrl.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```yaml
series:
- name: arc_hsdk4xd
socs:
- name: arc_hsdk4xd
``` | /content/code_sandbox/soc/snps/hsdk4xd/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```cmake
set(GCC_ARC_TUNED_CPU hs4xd)
``` | /content/code_sandbox/soc/snps/hsdk4xd/tune_build_ops.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 14 |
```unknown
config SOC_ARC_HSDK4XD
select ARC
select CPU_HAS_FPU
select CPU_HAS_DSP
``` | /content/code_sandbox/soc/snps/hsdk4xd/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25 |
```unknown
if SOC_ARC_HSDK4XD
config CPU_HS4X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 2 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default 88
config RGF_NUM_BANKS
# Actua... | /content/code_sandbox/soc/snps/hsdk4xd/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 238 |
```linker script
/*
*
*/
/**
* @brief Linker script for the HSDK4XD Development Kit
*/
#include <zephyr/devicetree.h>
/*
* SRAM base address and size
*/
#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
#define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define... | /content/code_sandbox/soc/snps/hsdk4xd/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 132 |
```unknown
config SOC_FAMILY_NSIM_ARC_CLASSIC
bool
config SOC_FAMILY
default "nsim_arc_classic" if SOC_FAMILY_NSIM_ARC_CLASSIC
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
if SOC_FAMILY_NSIM_ARC_CLASSIC
config XIP
default n
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_NSIM_ARC_CLASSIC
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```yaml
family:
- name: nsim_arc_classic
series:
- name: nsim_em
socs:
- name: nsim_em
- name: nsim_em7d_v22
- name: nsim_em11d
- name: nsim_hs
socs:
- name: nsim_hs
- name: nsim_hs_smp
- name: nsim_hs_mpuv6
- name: ... | /content/code_sandbox/soc/snps/nsim/arc_classic/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 188 |
```unknown
if SOC_FAMILY_NSIM_ARC_CLASSIC
rsource "*/Kconfig"
endif # SOC_FAMILY_NSIM_ARC_CLASSIC
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
if SOC_NSIM_HS6X
config CPU_HS6X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 50000000
config CACHE_MANAGEMENT
default y
endif # SO... | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig.defconfig.hs6x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```linker script
/*
*
*/
/**
* @brief Linker script for the Synopsys EM Starterkit platform.
*/
#include <zephyr/devicetree.h>
/* Instruction Closely Coupled Memory (ICCM) base address and size */
#if DT_NODE_HAS_PROP(DT_INST(0, arc_iccm), reg) && \
(DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
#define ICCM_START ... | /content/code_sandbox/soc/snps/nsim/arc_classic/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 455 |
```unknown
config SOC_SERIES_NSIM_HS
bool
select SOC_FAMILY_NSIM_ARC_CLASSIC
config SOC_SERIES
default "nsim_hs" if SOC_SERIES_NSIM_HS
config SOC_NSIM_HS
bool
select SOC_SERIES_NSIM_HS
config SOC_NSIM_HS_SMP
bool
select SOC_SERIES_NSIM_HS
config SOC_NSIM_HS_MPUV6
bool
select SOC_SERIES_NSIM_HS
config SOC... | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 294 |
```unknown
if SOC_NSIM_HS_MPUV6
config CPU_HS3X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config ARC_MPU_VER
def... | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig.defconfig.hs_mpuv6 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 174 |
```unknown
if SOC_NSIM_HS5X_SMP
config CPU_HS5X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
config CACHE_MANAGEMENT
default y
config ... | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig.defconfig.hs5x_smp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 116 |
```unknown
if SOC_NSIM_HS_SMP
config CPU_HS3X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default 88
config RGF_NUM_BANKS
def... | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig.defconfig.hs_smp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 178 |
```unknown
if SOC_NSIM_HS6X_SMP
config CPU_HS6X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config SYS_CLOCK_HW_CYCLES_PER_SEC
# SMP simulation is slower than single core, 1 Mhz seems rea... | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig.defconfig.hs6x_smp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```unknown
if SOC_SERIES_NSIM_HS
rsource "Kconfig.defconfig.hs*"
endif # SOC_SERIES_NSIM_HS
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```unknown
config SOC_SERIES_NSIM_HS
select ARC
select CPU_HAS_FPU
select CPU_HAS_MPU if !SMP
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```haskell
if SOC_NSIM_HS
config CPU_HS3X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config RGF_NUM_BANKS
default... | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig.defconfig.hs | haskell | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```unknown
config SOC_SERIES_NSIM_VPX5
bool
select SOC_FAMILY_NSIM_ARC_CLASSIC
config SOC_SERIES
default "nsim_vpx5" if SOC_SERIES_NSIM_VPX5
config SOC_NSIM_VPX5
bool
select SOC_SERIES_NSIM_VPX5
help
Synopsys ARC VPX5 in nSIM
config SOC
default "nsim_vpx5" if SOC_NSIM_VPX5
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/vpx5/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```unknown
if SOC_NSIM_HS5X
config CPU_HS5X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
default 2
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 5000000
config CACHE_MANAGEMENT
default y
endif # SOC... | /content/code_sandbox/soc/snps/nsim/arc_classic/hs/Kconfig.defconfig.hs5x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
config SOC_SERIES_NSIM_VPX5
select ARC
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/vpx5/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```unknown
if SOC_NSIM_VPX5
config CPU_HS3X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 24
config RGF_NUM_BANKS
defau... | /content/code_sandbox/soc/snps/nsim/arc_classic/vpx5/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 147 |
```unknown
config SOC_SERIES_NSIM_EM
bool
select SOC_FAMILY_NSIM_ARC_CLASSIC
config SOC_SERIES
default "nsim_em" if SOC_SERIES_NSIM_EM
config SOC_NSIM_EM
bool
select SOC_SERIES_NSIM_EM
config SOC_NSIM_EM7D_V22
bool
select SOC_SERIES_NSIM_EM
config SOC_NSIM_EM11D
bool
select SOC_SERIES_NSIM_EM
config SOC
... | /content/code_sandbox/soc/snps/nsim/arc_classic/em/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 146 |
```unknown
if SOC_NSIM_EM7D_V22
config CPU_EM4_FPUDA
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config ARC_MPU_VER
... | /content/code_sandbox/soc/snps/nsim/arc_classic/em/Kconfig.defconfig.em7d_v22 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 223 |
```emberscript
if SOC_NSIM_EM
config CPU_EM4_FPUDA
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config ARC_MPU_VER
de... | /content/code_sandbox/soc/snps/nsim/arc_classic/em/Kconfig.defconfig.em | emberscript | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 228 |
```unknown
if SOC_SERIES_NSIM_EM
rsource "Kconfig.defconfig.em*"
endif # SOC_SERIES_NSIM_EM
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/em/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```unknown
config SOC_SERIES_NSIM_EM
select ARC
select CPU_HAS_MPU
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/em/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```unknown
if SOC_NSIM_EM11D
config CPU_EM6
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config ARC_MPU_VER
default 2... | /content/code_sandbox/soc/snps/nsim/arc_classic/em/Kconfig.defconfig.em11d | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 248 |
```unknown
config SOC_SERIES_NSIM_SEM
bool
select SOC_FAMILY_NSIM_ARC_CLASSIC
config SOC_SERIES
default "nsim_sem" if SOC_SERIES_NSIM_SEM
config SOC_NSIM_SEM
bool
select SOC_SERIES_NSIM_SEM
config SOC
default "nsim_sem" if SOC_NSIM_SEM
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/sem/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
config SOC_SERIES_NSIM_SEM
select ARC
select CPU_HAS_MPU
select CPU_HAS_FPU
select ARC_HAS_SECURE
``` | /content/code_sandbox/soc/snps/nsim/arc_classic/sem/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
if SOC_NSIM_SEM
config CPU_EM4_FPUDA
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 30
config ARC_MPU_VER
defau... | /content/code_sandbox/soc/snps/nsim/arc_classic/sem/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 166 |
```yaml
family:
- name: nsim_arc_v
series:
- name: rmx
socs:
- name: rmx100
``` | /content/code_sandbox/soc/snps/nsim/arc_v/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
config SOC_FAMILY_NSIM_ARC_V
bool
config SOC_FAMILY
default "nsim_arc_v" if SOC_FAMILY_NSIM_ARC_V
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/snps/nsim/arc_v/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```unknown
if SOC_FAMILY_NSIM_ARC_V
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_NSIM_ARC_V
``` | /content/code_sandbox/soc/snps/nsim/arc_v/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
if SOC_FAMILY_NSIM_ARC_V
rsource "*/Kconfig"
endif # SOC_FAMILY_NSIM_ARC_V
``` | /content/code_sandbox/soc/snps/nsim/arc_v/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
if SOC_SERIES_RMX
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config MULTI_LEVEL_INTERRUPTS
default n
config NUM_IRQS
default 18
config RISCV_PMP
default y
config PMP_SLOTS
default 16
endif # SOC_SERIES_RMX
``` | /content/code_sandbox/soc/snps/nsim/arc_v/rmx/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
config SOC_SERIES_RMX
bool
select SOC_FAMILY_NSIM_ARC_V
config SOC_SERIES
default "rmx" if SOC_SERIES_RMX
config SOC_RMX100
bool
select SOC_SERIES_RMX
config SOC
default "rmx100" if SOC_RMX100
``` | /content/code_sandbox/soc/snps/nsim/arc_v/rmx/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
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