text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
config SOC_SERIES_RMX
bool
select RISCV
select RISCV_PRIVILEGED
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select INCLUDE_RESET_VECTOR
select ATOMIC_OPERATIONS_BUILTIN
``` | /content/code_sandbox/soc/snps/nsim/arc_v/rmx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```unknown
# Analog Devices MAX32xxx MCU family
config SOC_FAMILY_MAX32
bool
config SOC_FAMILY
default "max32" if SOC_FAMILY_MAX32
config SOC_MAX32655
bool
select SOC_FAMILY_MAX32
config SOC_MAX32655_M4
bool
select SOC_MAX32655
config SOC_MAX32662
bool
select SOC_FAMILY_MAX32
config SOC_MAX32666
bool
s... | /content/code_sandbox/soc/adi/max32/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 308 |
```unknown
# Analog Devices MAX32662 MCU
if SOC_MAX32662
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
config NUM_IRQS
default 108
endif # SOC_MAX32662
``` | /content/code_sandbox/soc/adi/max32/Kconfig.defconfig.max32662 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
# Analog Devices MAX32655 MCU
if SOC_MAX32655
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
config NUM_IRQS
default 110
endif # SOC_MAX32655
``` | /content/code_sandbox/soc/adi/max32/Kconfig.defconfig.max32655 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
# Analog Devices MAX32672 MCU
if SOC_MAX32672
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
config NUM_IRQS
default 108
endif # SOC_MAX32672
``` | /content/code_sandbox/soc/adi/max32/Kconfig.defconfig.max32672 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
# Analog Devices MAX32680 MCU
if SOC_MAX32680
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
config NUM_IRQS
default 104
endif # SOC_MAX32680
``` | /content/code_sandbox/soc/adi/max32/Kconfig.defconfig.max32680 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
# Analog Devices MAX32675 MCU
if SOC_MAX32675
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
config NUM_IRQS
default 100
endif # SOC_MAX32675
``` | /content/code_sandbox/soc/adi/max32/Kconfig.defconfig.max32675 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```yaml
family:
- name: max32
socs:
- name: max32655
cpuclusters:
- name: m4
- name: max32662
- name: max32666
cpuclusters:
- name: cpu0
- name: max32670
- name: max32672
- name: max32675
- name: max32680
cpuclusters:
- name: m4
- name: max32690
cpuclusters:
- name: m4... | /content/code_sandbox/soc/adi/max32/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```unknown
# Analog Devices MAX32690 MCU
if SOC_MAX32690
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
config NUM_IRQS
default 112
endif # SOC_MAX32690
``` | /content/code_sandbox/soc/adi/max32/Kconfig.defconfig.max32690 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for MAX32xxx MCUs
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <wrap_max32_sys.h>
#if defined(CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK)
bool z_arm_on_enter_cpu_idle(void)
{
/* Returning false prevent device goes to sleep mode */
return fa... | /content/code_sandbox/soc/adi/max32/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 174 |
```unknown
# Analog Devices MAX32666 MCU
if SOC_MAX32666
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
config NUM_IRQS
default 95
endif # SOC_MAX32666
``` | /content/code_sandbox/soc/adi/max32/Kconfig.defconfig.max32666 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the MAX32xxx family processors.
*
*/
#ifndef _MAX32_SOC_H_
#define _MAX32_SOC_H_
#include <wrap_max32xxx.h>
#endif /* _MAX32_SOC_H_ */
``` | /content/code_sandbox/soc/adi/max32/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
# Analog Devices MAX32xxx MCU family
if SOC_FAMILY_MAX32
rsource "Kconfig.defconfig.max32*"
config SRAM_VECTOR_TABLE
default y
endif # SOC_FAMILY_MAX32
``` | /content/code_sandbox/soc/adi/max32/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```unknown
# Analog Devices MAX32670 MCU
if SOC_MAX32670
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
config NUM_IRQS
default 100
endif # SOC_MAX32670
``` | /content/code_sandbox/soc/adi/max32/Kconfig.defconfig.max32670 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
# Analog Devices MAX32xxx MCU family
config SOC_FAMILY_MAX32
select ARM
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select CPU_CORTEX_M_HAS_SYSTICK
select CLOCK_CONTROL
select BUILD_OUTPUT_HEX
config SOC_MAX32655
select CPU_CORTEX_M4
config SOC_MAX32662
select CPU_CORTEX_M4
config SOC_MAX32666
se... | /content/code_sandbox/soc/adi/max32/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 262 |
```unknown
config SOC_FAMILY_GD_GD32
bool
config SOC_FAMILY
default "gd_gd32" if SOC_FAMILY_GD_GD32
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/gd/gd32/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```yaml
family:
- name: gd_gd32
series:
- name: gd32a50x
socs:
- name: gd32a503
- name: gd32e10x
socs:
- name: gd32e103
- name: gd32e50x
socs:
- name: gd32e507
- name: gd32f3x0
socs:
- name: gd32f350
- name: gd32f4xx
socs:
- name: gd32f405
- name: gd32f407
- n... | /content/code_sandbox/soc/gd/gd32/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 224 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_ADI_MAX32_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_ADI_MAX32_COMMON_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct pinctrl_soc_pin... | /content/code_sandbox/soc/adi/max32/common/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 457 |
```unknown
if SOC_FAMILY_GD_GD32
rsource "*/Kconfig.defconfig.series"
config PINCTRL
default y
config RESET
default y
config CLOCK_CONTROL
default y
endif # SOC_FAMILY_GD_GD32
``` | /content/code_sandbox/soc/gd/gd32/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config SOC_FAMILY_GD_GD32
select HAS_GD32_HAL
select BUILD_OUTPUT_HEX
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
if SOC_FAMILY_GD_GD32
rsource "*/Kconfig"
endif # SOC_FAMILY_GD_GD32
``` | /content/code_sandbox/soc/gd/gd32/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
if SOC_SERIES_GD32F4XX
config SOC_SERIES
default "gd32f4xx"
rsource "Kconfig.defconfig.gd32*"
endif # SOC_SERIES_GD32F4XX
``` | /content/code_sandbox/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
config SOC_SERIES_GD32F4XX
bool
select SOC_FAMILY_GD_GD32
help
Enable support for GigaDevice GD32F4XX MCU series
config SOC_SERIES
default "gd32f4xx" if SOC_SERIES_GD32F4XX
config SOC_GD32F405
bool
select SOC_SERIES_GD32F4XX
config SOC_GD32F407
bool
select SOC_SERIES_GD32F4XX
config SOC_GD32F... | /content/code_sandbox/soc/gd/gd32/gd32f4xx/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 212 |
```unknown
if SOC_GD32F407
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 91
endif # SOC_GD32F407
``` | /content/code_sandbox/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f407 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
if SOC_GD32F405
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 82
endif # SOC_GD32F405
``` | /content/code_sandbox/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f405 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
if SOC_GD32F450
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 91
endif # SOC_GD32F450
``` | /content/code_sandbox/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f450 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```c
/*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
static int gd32f4xx_soc_init(void)
{
SystemInit();
return 0;
}
SYS_INIT(gd32f4xx_soc_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/soc/gd/gd32/gd32f4xx/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```objective-c
/*
*/
#ifndef SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_
#define SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_
#include <zephyr/sys/util_macro.h>
/* RCU */
#define RCU_CFG0_OFFSET 0x08U
#define RCU_AHB1EN_OFFSET 0x30U
#define RCU_AHB2EN_OFFSET 0x34U
#define RCU_AHB3EN_OFFSET 0x38U
#define RCU_... | /content/code_sandbox/soc/gd/gd32/gd32f4xx/gd32_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 347 |
```objective-c
/*
*/
#ifndef _SOC_ARM_GIGADEVICE_GD32F4XX_SOC_H_
#define _SOC_ARM_GIGADEVICE_GD32F4XX_SOC_H_
#ifndef _ASMLANGUAGE
#include <gd32f4xx.h>
/* The GigaDevice HAL headers define this, but it conflicts with the Zephyr can.h */
#undef CAN_MODE_NORMAL
#endif /* _ASMLANGUAGE */
#endif /* _SOC_ARM_GIGADEVI... | /content/code_sandbox/soc/gd/gd32/gd32f4xx/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
config SOC_SERIES_GD32F4XX
select ARM
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select CPU_CORTEX_M4
select GD32_HAS_AF_PINMUX
select GD32_HAS_IRC_32K
``` | /content/code_sandbox/soc/gd/gd32/gd32f4xx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
if SOC_GD32F470
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 91
endif # SOC_GD32F470
``` | /content/code_sandbox/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f470 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
if SOC_SERIES_GD32VF103
rsource "Kconfig.defconfig.gd32*"
endif # SOC_SERIES_GD32VF103
``` | /content/code_sandbox/soc/gd/gd32/gd32vf103/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
# GD32VF103 SOC configuration options
config SOC_SERIES_GD32VF103
bool
select SOC_FAMILY_GD_GD32
help
Enable support for GigaDevice GD32VF103 MCU series
config SOC_SERIES
default "gd32vf103" if SOC_SERIES_GD32VF103
config SOC_GD32VF103
bool
select SOC_SERIES_GD32VF103
config SOC
default "gd32v... | /content/code_sandbox/soc/gd/gd32/gd32vf103/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```linker script
/*
*
*/
KEEP(*(.init.*))
``` | /content/code_sandbox/soc/gd/gd32/gd32vf103/init.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10 |
```objective-c
/*
*/
#ifndef SOC_ARM_GIGADEVICE_GD32VF103_GD32_REGS_H_
#define SOC_ARM_GIGADEVICE_GD32VF103_GD32_REGS_H_
#include <zephyr/sys/util_macro.h>
/* RCU */
#define RCU_CFG0_OFFSET 0x04U
#define RCU_AHBEN_OFFSET 0x14U
#define RCU_APB2EN_OFFSET 0x18U
#define RCU_APB1EN_OFFSET 0x1CU
#define RC... | /content/code_sandbox/soc/gd/gd32/gd32vf103/gd32_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 268 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <gd32vf103.h>
static int gigadevice_gd32v_soc_init(void)
{
uint32_t key;
key = irq_lock();
SystemInit();
irq_unlock(key);
return 0;
}
SYS_INIT(gigadevice_gd32v_soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
``` | /content/code_sandbox/soc/gd/gd32/gd32vf103/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
if SOC_GD32VF103
config KERNEL_ENTRY
default "__nuclei_start"
config SYS_CLOCK_HW_CYCLES_PER_SEC
# This value should be the CPU frequency divided by 4.
# The CPU frequency is set to the maximum value of 108MHz by default.
default 27000000
config RISCV_MCAUSE_EXCEPTION_MASK
default 0xFFF
config RISC... | /content/code_sandbox/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 190 |
```unknown
/*
*
*/
#include "nuclei_csr.h"
#include <zephyr/toolchain.h>
#include <zephyr/arch/riscv/csr.h>
GTEXT(__nuclei_start)
SECTION_FUNC(init, __nuclei_start)
/* Disable Global Interrupt */
csrc mstatus, MSTATUS_MIE
/* Jump to logical address first to ensure correct operation of RAM region */
la a0, __n... | /content/code_sandbox/soc/gd/gd32/gd32vf103/entry.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 274 |
```unknown
# GD32VF103 SOC implementation
config SOC_SERIES_GD32VF103
select RISCV
select RISCV_PRIVILEGED
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_HAS_CLIC
select ATOMIC_OPERATIONS_C
se... | /content/code_sandbox/soc/gd/gd32/gd32vf103/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 136 |
```objective-c
/*
*
*/
/**
* @file
* @brief Define Nuclei specific CSR and related definitions.
*
* This header contains Nuclei specific definitions.
* Use arch/riscv/csr.h for RISC-V standard CSR and definitions.
*/
#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_COMMON_NUCLEI_NUCLEI_CSR_H_
#define ZEPHYR_SOC_RISC... | /content/code_sandbox/soc/gd/gd32/gd32vf103/nuclei_csr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,869 |
```unknown
config SOC_SERIES_GD32L23X
bool
select SOC_FAMILY_GD_GD32
help
Enable support for GigaDevice GD32L23X MCU series
config SOC_SERIES
default "gd32l23x" if SOC_SERIES_GD32L23X
config SOC_GD32L233
bool
select SOC_SERIES_GD32L23X
config SOC
default "gd32l233" if SOC_GD32L233
``` | /content/code_sandbox/soc/gd/gd32/gd32l23x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
if SOC_SERIES_GD32L23X
config SOC_SERIES
default "gd32l23x"
rsource "Kconfig.defconfig.gd32*"
endif # SOC_SERIES_GD32L23X
``` | /content/code_sandbox/soc/gd/gd32/gd32l23x/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```objective-c
/*
*
*/
/**
* @file
* Gigadevice SoC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef CONFIG_PINCTRL_GD32_AF
#... | /content/code_sandbox/soc/gd/gd32/common/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,377 |
```objective-c
/*
*/
#ifndef SOC_ARM_GIGADEVICE_GD32L23X_GD32_REGS_H_
#define SOC_ARM_GIGADEVICE_GD32L23X_GD32_REGS_H_
#include <zephyr/sys/util_macro.h>
/* RCU */
#define RCU_CFG0_OFFSET 0x04U
#define RCU_AHBEN_OFFSET 0x14U
#define RCU_APB2EN_OFFSET 0x18U
#define RCU_APB1EN_OFFSET 0x1CU
#define RCU... | /content/code_sandbox/soc/gd/gd32/gd32l23x/gd32_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 255 |
```c
/*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
static int gd32l23x_init(void)
{
SystemInit();
return 0;
}
SYS_INIT(gd32l23x_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/soc/gd/gd32/gd32l23x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```objective-c
/*
*/
#ifndef _SOC_ARM_GIGADEVICE_GD32L23X_SOC_H_
#define _SOC_ARM_GIGADEVICE_GD32L23X_SOC_H_
#ifndef _ASMLANGUAGE
#include <gd32l23x.h>
#endif /* _ASMLANGUAGE */
#endif /* _SOC_ARM_GIGADEVICE_GD32L23X_SOC_H_ */
``` | /content/code_sandbox/soc/gd/gd32/gd32l23x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
config SOC_SERIES_GD32L23X
select ARM
select CPU_CORTEX_M23
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select GD32_HAS_AF_PINMUX
select GD32_HAS_IRC_32K
``` | /content/code_sandbox/soc/gd/gd32/gd32l23x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```unknown
if SOC_GD32L233
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 69
endif # SOC_GD32L233
``` | /content/code_sandbox/soc/gd/gd32/gd32l23x/Kconfig.defconfig.gd32l233 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config SOC_SERIES_GD32E10X
bool
select SOC_FAMILY_GD_GD32
help
Enable support for GigaDevice GD32E10X MCU series
config SOC_SERIES
default "gd32e10x" if SOC_SERIES_GD32E10X
config SOC_GD32E103
bool
select SOC_SERIES_GD32E10X
config SOC
default "gd32e103" if SOC_GD32E103
``` | /content/code_sandbox/soc/gd/gd32/gd32e10x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
if SOC_SERIES_GD32E10X
config SOC_SERIES
default "gd32e10x"
rsource "Kconfig.defconfig.gd32*"
endif # SOC_SERIES_GD32E10X
``` | /content/code_sandbox/soc/gd/gd32/gd32e10x/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```objective-c
/*
*/
#ifndef SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_
#define SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_
#include <zephyr/sys/util_macro.h>
/* RCU */
#define RCU_CFG0_OFFSET 0x04U
#define RCU_AHBEN_OFFSET 0x14U
#define RCU_APB2EN_OFFSET 0x18U
#define RCU_APB1EN_OFFSET 0x1CU
#define RCU_... | /content/code_sandbox/soc/gd/gd32/gd32e10x/gd32_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 270 |
```c
/*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
static int gd32e10x_soc_init(void)
{
SystemInit();
return 0;
}
SYS_INIT(gd32e10x_soc_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/soc/gd/gd32/gd32e10x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
if SOC_GD32E103
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 83
endif # SOC_GD32E103
``` | /content/code_sandbox/soc/gd/gd32/gd32e10x/Kconfig.defconfig.gd32e103 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config SOC_SERIES_GD32E10X
select ARM
select CPU_HAS_FPU
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select GD32_HAS_AFIO_PINMUX
select GD32_HAS_IRC_40K
``` | /content/code_sandbox/soc/gd/gd32/gd32e10x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```objective-c
/*
*/
#ifndef _SOC_ARM_GIGADEVICE_GD32E10X_SOC_H_
#define _SOC_ARM_GIGADEVICE_GD32E10X_SOC_H_
#ifndef _ASMLANGUAGE
#include <gd32e10x.h>
#endif /* _ASMLANGUAGE */
#endif /* _SOC_ARM_GIGADEVICE_GD32E10X_SOC_H_ */
``` | /content/code_sandbox/soc/gd/gd32/gd32e10x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
if SOC_SERIES_GD32E50X
config SOC_SERIES
default "gd32e50x"
rsource "Kconfig.defconfig.gd32*"
endif # SOC_SERIES_GD32E50X
``` | /content/code_sandbox/soc/gd/gd32/gd32e50x/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
config SOC_SERIES_GD32E50X
bool
select SOC_FAMILY_GD_GD32
help
Enable support for GigaDevice GD32E50X MCU series
config SOC_SERIES
default "gd32e50x" if SOC_SERIES_GD32E50X
config SOC_GD32E507
bool
select SOC_SERIES_GD32E50X
config SOC
default "gd32e507" if SOC_GD32E507
``` | /content/code_sandbox/soc/gd/gd32/gd32e50x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```objective-c
/*
*/
#ifndef SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_
#define SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_
#include <zephyr/sys/util_macro.h>
/* RCU */
#define RCU_CFG0_OFFSET 0x04U
#define RCU_AHBEN_OFFSET 0x14U
#define RCU_APB2EN_OFFSET 0x18U
#define RCU_APB1EN_OFFSET 0x1CU
#define RCU_... | /content/code_sandbox/soc/gd/gd32/gd32e50x/gd32_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 270 |
```c
/*
*/
#include <zephyr/init.h>
#include <soc.h>
static int gd32e50x_soc_init(void)
{
SystemInit();
return 0;
}
SYS_INIT(gd32e50x_soc_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/soc/gd/gd32/gd32e50x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```objective-c
/*
*/
#ifndef _SOC_ARM_GIGADEVICE_GD32E50X_SOC_H_
#define _SOC_ARM_GIGADEVICE_GD32E50X_SOC_H_
#ifndef _ASMLANGUAGE
#include <gd32e50x.h>
#endif /* _ASMLANGUAGE */
#endif /* _SOC_ARM_GIGADEVICE_GD32E50X_SOC_H_ */
``` | /content/code_sandbox/soc/gd/gd32/gd32e50x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
if SOC_GD32E507
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 88
endif # SOC_GD32E507
``` | /content/code_sandbox/soc/gd/gd32/gd32e50x/Kconfig.defconfig.gd32e507 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config SOC_SERIES_GD32E50X
select ARM
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select CPU_CORTEX_M33
select ARMV8_M_DSP
select GD32_HAS_AFIO_PINMUX
select GD32_HAS_IRC_40K
``` | /content/code_sandbox/soc/gd/gd32/gd32e50x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```unknown
if SOC_SERIES_GD32F403
rsource "Kconfig.defconfig.gd32*"
endif # SOC_SERIES_GD32F403
``` | /content/code_sandbox/soc/gd/gd32/gd32f403/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
config SOC_SERIES_GD32F403
bool
select SOC_FAMILY_GD_GD32
help
Enable support for GigaDevice GD32F403 MCU series
config SOC_SERIES
default "gd32f403" if SOC_SERIES_GD32F403
config SOC_GD32F403
bool
select SOC_SERIES_GD32F403
config SOC
default "gd32f403" if SOC_GD32F403
``` | /content/code_sandbox/soc/gd/gd32/gd32f403/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 99 |
```c
/*
*/
/**
* @file
* @brief GD32 MCU series initialization code
*
* This module provides routines to initialize and support board-level
* hardware for the GigaDevice GD32 SoC.
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
/**
* @brief Perform basic hardware initialization at boo... | /content/code_sandbox/soc/gd/gd32/gd32f403/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```objective-c
/*
*/
#ifndef SOC_ARM_GIGADEVICE_GD32F403_GD32_REGS_H_
#define SOC_ARM_GIGADEVICE_GD32F403_GD32_REGS_H_
#include <zephyr/sys/util_macro.h>
/* RCU */
#define RCU_CFG0_OFFSET 0x04U
#define RCU_AHBEN_OFFSET 0x14U
#define RCU_APB2EN_OFFSET 0x18U
#define RCU_APB1EN_OFFSET 0x1CU
#define RCU_... | /content/code_sandbox/soc/gd/gd32/gd32f403/gd32_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 267 |
```unknown
config SOC_SERIES_GD32F403
select ARM
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select GD32_HAS_AFIO_PINMUX
select GD32_HAS_IRC_40K
``` | /content/code_sandbox/soc/gd/gd32/gd32f403/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```objective-c
/*
*/
/**
* @file SoC configuration header for the GD32F403 SoC series.
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <gd32f403.h>
/* The GigaDevice HAL headers define this, but it conflicts with the Zephyr can.h */
#undef CAN_MODE_NORMAL
#endif ... | /content/code_sandbox/soc/gd/gd32/gd32f403/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```unknown
if SOC_GD32F403
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 68
endif # SOC_GD32F403
``` | /content/code_sandbox/soc/gd/gd32/gd32f403/Kconfig.defconfig.gd32f403 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config SOC_SERIES_GD32A50X
bool
select SOC_FAMILY_GD_GD32
help
Enable support for GigaDevice GD32A50X MCU series
config SOC_SERIES
default "gd32a50x" if SOC_SERIES_GD32A50X
config SOC_GD32A503
bool
select SOC_SERIES_GD32A50X
config SOC
default "gd32a503" if SOC_GD32A503
``` | /content/code_sandbox/soc/gd/gd32/gd32a50x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
if SOC_SERIES_GD32A50X
config SOC_SERIES
default "gd32a50x"
rsource "Kconfig.defconfig.gd32*"
endif # SOC_SERIES_GD32A50X
``` | /content/code_sandbox/soc/gd/gd32/gd32a50x/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
if SOC_GD32A503
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 82
endif # SOC_GD32A503
``` | /content/code_sandbox/soc/gd/gd32/gd32a50x/Kconfig.defconfig.gd32a503 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```objective-c
/*
*/
#ifndef SOC_ARM_GIGADEVICE_GD32A50X_GD32_REGS_H_
#define SOC_ARM_GIGADEVICE_GD32A50X_GD32_REGS_H_
#include <zephyr/sys/util_macro.h>
/* RCU */
#define RCU_CFG0_OFFSET 0x04U
#define RCU_AHBEN_OFFSET 0x14U
#define RCU_APB1EN_OFFSET 0x1CU
#define RCU_APB2EN_OFFSET 0x18U
#define RCU_... | /content/code_sandbox/soc/gd/gd32/gd32a50x/gd32_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 281 |
```objective-c
/*
*/
#ifndef _SOC_ARM_GIGADEVICE_GD32A50X_SOC_H_
#define _SOC_ARM_GIGADEVICE_GD32A50X_SOC_H_
#ifndef _ASMLANGUAGE
#include <gd32a50x.h>
#endif /* _ASMLANGUAGE */
#endif /* _SOC_ARM_GIGADEVICE_GD32A50X_SOC_H_ */
``` | /content/code_sandbox/soc/gd/gd32/gd32a50x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```c
/*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
/* initial ecc memory */
void z_arm_platform_init(void)
{
register unsigned r0 __asm("r0") = DT_REG_ADDR(DT_CHOSEN(zephyr_sram));
register unsigned r1 __asm("r1") =
DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) + DT_REG_SIZE(DT_CHOSEN(zephyr_s... | /content/code_sandbox/soc/gd/gd32/gd32a50x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 170 |
```unknown
config SOC_SERIES_GD32A50X
select ARM
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select ARMV8_M_DSP
select CPU_CORTEX_M33
select GD32_HAS_AF_PINMUX
select GD32_HAS_IRC_40K
select PLATFORM_SPECIFIC_INIT
``` | /content/code_sandbox/soc/gd/gd32/gd32a50x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
config SOC_SERIES_GD32F3X0
bool
select SOC_FAMILY_GD_GD32
help
Enable support for GigaDevice GD32F3X0 MCU series
config SOC_SERIES
default "gd32f3x0" if SOC_SERIES_GD32F3X0
config SOC_GD32F350
bool
select SOC_SERIES_GD32F3X0
config SOC
default "gd32f350" if SOC_GD32F350
``` | /content/code_sandbox/soc/gd/gd32/gd32f3x0/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```unknown
if SOC_SERIES_GD32F3X0
config SOC_SERIES
default "gd32f3x0"
rsource "Kconfig.defconfig.gd32*"
endif # SOC_SERIES_GD32F3X0
``` | /content/code_sandbox/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```c
/*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
static int gd32f3x0_init(void)
{
SystemInit();
return 0;
}
SYS_INIT(gd32f3x0_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/soc/gd/gd32/gd32f3x0/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```objective-c
/*
*/
#ifndef SOC_ARM_GIGADEVICE_GD32F3X0_GD32_REGS_H_
#define SOC_ARM_GIGADEVICE_GD32F3X0_GD32_REGS_H_
#include <zephyr/sys/util_macro.h>
/* RCU */
#define RCU_CFG0_OFFSET 0x04U
#define RCU_AHBEN_OFFSET 0x14U
#define RCU_APB2EN_OFFSET 0x18U
#define RCU_APB1EN_OFFSET 0x1CU
#define RCU_... | /content/code_sandbox/soc/gd/gd32/gd32f3x0/gd32_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 273 |
```objective-c
/*
*/
#ifndef _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_
#define _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_
#ifndef _ASMLANGUAGE
#include <gd32f3x0.h>
#endif /* _ASMLANGUAGE */
#endif /* _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_ */
``` | /content/code_sandbox/soc/gd/gd32/gd32f3x0/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```unknown
if SOC_GD32F350
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 68
endif # SOC_GD32F350
``` | /content/code_sandbox/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.gd32f350 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config SOC_SPARC_LEON
bool
``` | /content/code_sandbox/soc/gaisler/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 12 |
```unknown
config SPARC_CASA
bool
default y if SPARC
``` | /content/code_sandbox/soc/gaisler/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```unknown
config SOC_SERIES_GD32F3X0
select ARM
select CPU_HAS_FPU
select CPU_CORTEX_M4
select GD32_HAS_AF_PINMUX
select GD32_HAS_IRC_40K
``` | /content/code_sandbox/soc/gd/gd32/gd32f3x0/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
config SOC_LEON3
bool
config SOC
default "leon3" if SOC_LEON3
rsource "../Kconfig.soc"
``` | /content/code_sandbox/soc/gaisler/leon3/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
socs:
- name: leon3
``` | /content/code_sandbox/soc/gaisler/leon3/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 12 |
```objective-c
/*
*
*/
#ifndef __SOC_H__
#define __SOC_H__
#endif /* __SOC_H__ */
``` | /content/code_sandbox/soc/gaisler/leon3/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
config SOC_LEON3
select SPARC
select SOC_SPARC_LEON
rsource "../Kconfig"
``` | /content/code_sandbox/soc/gaisler/leon3/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
if SOC_LEON3
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 40000000
endif
``` | /content/code_sandbox/soc/gaisler/leon3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/tracing/tracing.h>
static void leon_idle(unsigned int key)
{
sys_trace_idle();
irq_unlock(key);
__asm__ volatile ("wr %g0, %asr19");
}
void arch_cpu_idle(void)
{
leon_idle(0);
}
void arch_cpu_atomic_idle(unsigned int key)
{
leon_idle(key);
}
``` | /content/code_sandbox/soc/gaisler/leon3/idle.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
config SOC_GR716A
bool
config SOC
default "gr716a" if SOC_GR716A
rsource "../Kconfig.soc"
``` | /content/code_sandbox/soc/gaisler/gr716a/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```yaml
socs:
- name: gr716a
``` | /content/code_sandbox/soc/gaisler/gr716a/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 12 |
```linker script
/*
*
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for LEON3
*/
#include <zephyr/devicetree.h>
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 512M
RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
/* refer to include/linker... | /content/code_sandbox/soc/gaisler/leon3/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 200 |
```objective-c
/*
*
*/
#ifndef __SOC_H__
#define __SOC_H__
#endif /* __SOC_H__ */
``` | /content/code_sandbox/soc/gaisler/gr716a/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
config SOC_GR716A
select SPARC
select SOC_SPARC_LEON
select CPU_HAS_FPU
rsource "../Kconfig"
``` | /content/code_sandbox/soc/gaisler/gr716a/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
if SOC_GR716A
config SPARC_NWIN
default 31
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 50000000
if FLASH
config SPI
default y
config SPI_NOR
default y
config SPI_GRLIB_SPIMCTRL
default y
endif
endif
``` | /content/code_sandbox/soc/gaisler/gr716a/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```linker script
/*
*
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for GR716A
*/
/*
* GR716A memory map
*
* LENGTH values represent the maximum possible. All memory regions may not be
* available on all systems. bootprom, RAM and SRAM are always available.
*/
MEMORY
{
bootprom (r... | /content/code_sandbox/soc/gaisler/gr716a/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 356 |
```unknown
# This file contains Zephyr hw module v2 Kconfig description for
# Nordic Semiconductor SoCs.
# The hw model v2 is generic and contains no Kconfig references outside its own
# tree structure and is therefore reusable in Kconfig trees outside a Zephyr build.
config SOC_SERIES
default "nrf51" if SOC_SERIES... | /content/code_sandbox/soc/nordic/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 379 |
```cmake
if(SB_CONFIG_VPR_LAUNCHER)
set(launcher_core "cpuapp")
string(REPLACE "/" ";" launcher_quals ${BOARD_QUALIFIERS})
list(LENGTH launcher_quals launcher_quals_len)
list(GET launcher_quals 1 launcher_soc)
list(GET launcher_quals 2 launcher_vpr)
string(REPLACE "cpu" "" launcher_vpr ${launcher_vpr})
... | /content/code_sandbox/soc/nordic/sysbuild.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 235 |
```unknown
rsource "common/vpr/Kconfig.sysbuild"
``` | /content/code_sandbox/soc/nordic/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.