text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```ini
# Explicitly for the STM32L475 Pandora board:
# path_to_url
# but perfectly functional for any other STM32L4 board connected via
# an stlink-v2-1 interface.
# This is for STM32L4 boards that are connected via stlink-v2-1.
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32l4x... | /content/code_sandbox/boards/alientek/pandora_stm32l475/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```unknown
/*
*
* Based on stm32l475_pandora:
*
*
*/
/dts-v1/;
#include <st/l4/stm32l475Xe.dtsi>
#include <st/l4/stm32l475v(c-e-g)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STM32L475 Pandora Development Board";
compatible = "alientek,pandora_stm32l475";
aliases {
... | /content/code_sandbox/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 926 |
```restructuredtext
.. _boards-efinix:
Efinix, Inc.
############
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/efinix/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
config BOARD_TITANIUM_TI60_F225
select SOC_EFINIX_SAPPHIRE
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/Kconfig.titanium_ti60_f225 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
/*
*
*/
/dts-v1/;
#include <efinix/sapphire_soc.dtsi>
/ {
model = "Efinix Titanium Ti60 F225";
compatible = "efinix,titanium-ti60-f225";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram0;
};
aliases {
led0 = &green_led;
};
leds {
compatible = "gpio-led... | /content/code_sandbox/boards/efinix/titanium_ti60_f225/titanium_ti60_f225.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 254 |
```yaml
identifier: titanium_ti60_f225
name: titanium_ti60_f225 FPGA development kit with Efinix Sapphire riscv SoC
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 196608
supported:
- gpio
- uart
vendor: efinix
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/titanium_ti60_f225.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
board:
name: titanium_ti60_f225
vendor: efinix
socs:
- name: efinix_sapphire
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL=n
CONFIG_XIP=n
CONFIG_HEAP_MEM_POOL_SIZE=16384
CONFIG_INIT_STACKS=n
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/titanium_ti60_f225_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```restructuredtext
.. _pandora_stm32l475_board:
Alientek STM32L475 Pandora
##########################
Overview
********
The STM32L475 Pandora board features an ARM Cortex-M4 based STM32L475VE MCU
with a wide range of connectivity support and configurations. Here are
some highlights of the STM32L475 Pandora board:
... | /content/code_sandbox/boards/alientek/pandora_stm32l475/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,950 |
```restructuredtext
.. _boards-seagate:
Seagate Technology PLC
######################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/seagate/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```restructuredtext
.. _titanium_ti60_f225:
Efinix Titanium Ti60 F225
#########################
Overview
********
The Efinix Titanium Ti60 F225 development kit contains a Ti60 FPGA, which is fabricated on a 16nm process and deliver
high performance with the lowest possible power on a small physical size. In addition... | /content/code_sandbox/boards/efinix/titanium_ti60_f225/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 412 |
```cmake
set(LEGEND_REVISIONS "25hdd" "25ssd" "35")
if (NOT DEFINED BOARD_REVISION)
set(BOARD_REVISION "25hdd")
else()
if (NOT BOARD_REVISION IN_LIST LEGEND_REVISIONS)
message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for Legend. Accepted revisions: ${LEGEND_REVISIONS}")
endif()
endif()
``` | /content/code_sandbox/boards/seagate/legend/revision.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```yaml
identifier: legend@25ssd
name: Legend (25sdd)
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- i2c
- pwm
- spi
testing:
ignore_tags:
- net
- bluetooth
vendor: seagate
``` | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```cmake
board_runner_args(jlink "--device=STM32F070CB" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/seagate/legend/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
/*
*
*/
/ {
model = "Seagate Legend 2.5 SSD board";
compatible = "legend25_ssd", "seagate,legend25_ssd";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>; /* 24MHz external clock */
status = "okay";
};
&pll {
clocks = <&clk_hse>;
prediv = <1>;
mul = <2>;
status = "okay";
};
&rcc {
clocks = <&pl... | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_25ssd.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 164 |
```yaml
identifier: legend@25hdd
name: Legend (25hdd)
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- i2c
- pwm
- spi
testing:
ignore_tags:
- net
- bluetooth
vendor: seagate
``` | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```yaml
board:
name: legend
vendor: seagate
revision:
format: custom
socs:
- name: stm32f070xb
``` | /content/code_sandbox/boards/seagate/legend/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```yaml
identifier: legend@35
name: Legend (35)
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- i2c
- pwm
- spi
testing:
ignore_tags:
- net
- bluetooth
vendor: seagate
``` | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_35.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
/*
*
*/
/ {
model = "Seagate Legend 3.5 board";
compatible = "legend35", "seagate,legend35";
aliases {
pwm-led0 = &pwm_led0;
};
led_pwm: pwmleds {
compatible = "pwm-leds";
label = "LED PWM";
pwm_led0: pwm_led_0 {
label = "Activity LED";
pwms = <&pwm3 3 PWM_MSEC(20) PWM_POLARITY_NORMA... | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_35.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 268 |
```unknown
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# GPIO Controller
CONFIG_GPIO=y
# Clock Control
CONFIG_CLOCK_CONTROL=y
# Enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/seagate/legend/legend_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
/*
*
*/
/ {
model = "Seagate Legend 2.5 HDD board";
compatible = "legend25_hdd", "seagate,legend25_hdd";
aliases {
pwm-led0 = &pwm_led0;
};
led_pwm: pwmleds {
compatible = "pwm-leds";
label = "LED PWM";
pwm_led0: pwm_led_0 {
label = "Activity LED";
pwms = <&pwm3 3 PWM_MSEC(20) PWM_PO... | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_25hdd.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 246 |
```unknown
# Legend board family configuration
if BOARD_LEGEND
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_LEGEND
``` | /content/code_sandbox/boards/seagate/legend/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
config BOARD_LEGEND
select SOC_STM32F070XB
``` | /content/code_sandbox/boards/seagate/legend/Kconfig.legend | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f0/stm32f070Xb.dtsi>
#include <st/f0/stm32f070cbtx-pinctrl.dtsi>
#include <zephyr/dt-bindings/led/led.h>
#include <zephyr/dt-bindings/led/seagate_legend_b1414.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
chosen {
zephyr,console = &usart1;
zephyr,shell... | /content/code_sandbox/boards/seagate/legend/legend.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,513 |
```ini
source [find board/st_nucleo_f0.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/seagate/legend/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```cmake
#
#
#
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/seagate/faze/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
config BOARD_FAZE
select SOC_LPC11U67
``` | /content/code_sandbox/boards/seagate/faze/Kconfig.faze | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```cmake
# Suppress DTC warnings due to all GPIO nodes sharing the same register address.
list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg")
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - /soc/flash@0 & /soc/gpio@0
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
... | /content/code_sandbox/boards/seagate/faze/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```yaml
#
# Seagate FireCuda Gaming SSD (FaZe) board
#
#
identifier: faze
name: Seagate FireCuda Gaming SSD (FaZe)
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
supported:
- clock_controller
- eeprom
- gpio
- i2c
- serial
vendor: seagate
``` | /content/code_sandbox/boards/seagate/faze/faze.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 95 |
```unknown
/*
*/
#include <zephyr/dt-bindings/pinctrl/lpc11u6x-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group0 {
pinmux = <U0_RXD_PIO0_18>,
<U0_TXD_PIO0_19>;
nxp,disable-analog-filter;
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PIO0_4>,
<I2C0_SDA_PIO0_5>;
... | /content/code_sandbox/boards/seagate/faze/faze-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 472 |
```restructuredtext
.. _legend:
Legend
######
Overview
********
The Legend board family contains three revisions: 25hdd, 25ssd, and 35.
The Legend 2.5" HDD board (revision 25hdd) can be found in the Seagate FireCuda
Gaming Hard Drive, Gaming Drive for Xbox and Gaming Drive for PlayStation
devices. A 2.5" drive and t... | /content/code_sandbox/boards/seagate/legend/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,259 |
```yaml
board:
name: faze
vendor: seagate
socs:
- name: lpc11u67
``` | /content/code_sandbox/boards/seagate/faze/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```unknown
#
# Seagate FireCuda Gaming SSD (FaZe) board
#
#
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_MAIN_STACK_SIZE=512
CONFIG_ISR_STACK_SIZE=768
CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_SRAM1=y
CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_USB_RAM=y
CONFIG_CLOCK_CONTROL_LPC11U6X_... | /content/code_sandbox/boards/seagate/faze/faze_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_lpc11u67.dtsi>
#include <zephyr/dt-bindings/led/led.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "faze-pinctrl.dtsi"
/ {
model = "Seagate FireCuda Gaming SSD (FaZe)";
compatible = "faze", "seagate,faze";
chosen {
zephyr,sram = &sram0;
z... | /content/code_sandbox/boards/seagate/faze/faze.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 985 |
```ini
#
# Seagate FireCuda Gaming SSD (FaZe) board
#
# An external debug probe must be connected to the SWD port (4-pins J2 header).
# Here we assume that a ST-LINK in-circuit debugger/programmer is used. You may
# have to replace it with your own interface here.
source [find interface/stlink.cfg]
# NXP LPC11U24 Cor... | /content/code_sandbox/boards/seagate/faze/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 368 |
```restructuredtext
.. _boards-cdns:
Cadence Design Systems Inc.
###########################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/cdns/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```cmake
board_set_debugger_ifnset(xtensa)
``` | /content/code_sandbox/boards/cdns/xt-sim/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_SIMULATOR_XTENSA=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=2000000
``` | /content/code_sandbox/boards/cdns/xt-sim/xt-sim_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
# XTENSA board configuration
config BOARD_XT_SIM
select SOC_XTENSA_SAMPLE_CONTROLLER
``` | /content/code_sandbox/boards/cdns/xt-sim/Kconfig.xt-sim | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```yaml
board:
name: xt-sim
vendor: cdns
socs:
- name: xtensa_sample_controller
``` | /content/code_sandbox/boards/cdns/xt-sim/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```yaml
identifier: xt-sim
name: XT Simulator
type: sim
arch: xtensa
toolchain:
- xcc
testing:
default: true
``` | /content/code_sandbox/boards/cdns/xt-sim/xt-sim.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
config IPM_CONSOLE_STACK_SIZE
default 2048 if IPM_CONSOLE_RECEIVER
``` | /content/code_sandbox/boards/cdns/xt-sim/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
/*
*
*/
/dts-v1/;
#include "sample_controller.dtsi"
/ {
model = "xt-sim";
compatible = "cdns,xtensa-sample-controller";
chosen {
zephyr,sram = &sram0;
};
};
&cpu0 {
clock-frequency = <10000000>;
};
``` | /content/code_sandbox/boards/cdns/xt-sim/xt-sim.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```restructuredtext
.. _faze:
Seagate FireCuda Gaming SSD (FaZe) board
########################################
Overview
********
The FaZe board can be found in the Seagate FireCuda Gaming SSD devices. A NVMe
SSD and two chips are embedded: an ASMedia ASM2364 USB-to-PCIe bridge controller
and a NXP LPC11U67 MCU. The... | /content/code_sandbox/boards/seagate/faze/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,138 |
```restructuredtext
.. _boards-cypress:
Cypress
#######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/cypress/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*
*/
/dts-v1/;
#include <infineon/cat1a/legacy/psoc6_cm4.dtsi>
#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi"
/ {
model = "cy8ckit_062_wifi_bt_m4 with a Cypress PSoC6 SoC";
compatible = "cypress,cy8ckit_062_wifi_bt_m4", "cypress,PSoC6";
aliases {
uart-5 = &uart5;
};
chosen {
zephyr,s... | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 225 |
```cmake
#
#
#
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
set(CY8C6247BZI_D54)
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```yaml
#
#
#
identifier: cy8ckit_062_wifi_bt/cy8c6247/m0
name: Cypress PSoC6 WiFi-BT Pioneer Kit (M0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```yaml
#
#
#
identifier: cy8ckit_062_wifi_bt/cy8c6247/m4
name: Cypress PSoC6 WiFi-BT Pioneer Kit (M4)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```yaml
board:
name: cy8ckit_062_wifi_bt
vendor: cypress
socs:
- name: cy8c6247
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
# UART driver
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
# UART driver
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```restructuredtext
.. _xt-sim:
Xtensa simulator
################
Overview
********
The Xtensa processor architecture is a configurable, extensible, and
synthesizable 32-bit RISC processor core. Processor and SOC vendors can select
from various processor options and even create customized instructions in
addition to... | /content/code_sandbox/boards/cdns/xt-sim/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,427 |
```unknown
/*
*
*/
/dts-v1/;
#include <infineon/cat1a/legacy/psoc6_cm0.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi"
/ {
model = "cy8ckit_062_wifi_bt_m0 with a Cypress PSoC6 SoC";
compatible = "cypress,cy8ckit_062_wifi_bt_m0", "cypress,PSoC6";
... | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 421 |
```unknown
# PSoC6 WiFi-BT Pioneer Kit configuration
config BOARD_CY8CKIT_062_WIFI_BT
select SOC_PART_NUMBER_CY8C6247BZI_D54
select SOC_CY8C6247_M0 if BOARD_CY8CKIT_062_WIFI_BT_CY8C6247_M0
select SOC_CY8C6247_M4 if BOARD_CY8CKIT_062_WIFI_BT_CY8C6247_M4
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```ini
#
#
if {[info exists env(OPENOCD_INTERFACE)]} {
set INTERFACE $env(OPENOCD_INTERFACE)
} else {
# By default connect over Debug USB port
set INTERFACE "cmsis-dap"
}
source [find interface/$INTERFACE.cfg]
transport select swd
source [find target/psoc6.cfg]
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
/*
* an affiliate of Cypress Semiconductor Corporation
*/
#include <infineon/cat1a/legacy/psoc6-pinctrl.dtsi>
/* Configure pin control bias mode for uart5 pins */
&p5_1_scb5_uart_tx {
drive-push-pull;
};
&p5_0_scb5_uart_rx {
input-enable;
};
&p9_1_scb2_uart_tx {
drive-push-pull;
};
&p9_0_scb2_uart_... | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```cmake
#
#
#
if(CONFIG_BOARD_CY8CKIT_062_BLE_CY8C6347_M0)
board_runner_args(jlink "--device=CY8C6xx7_CM0p" "--speed=2000")
elseif(CONFIG_BOARD_CY8CKIT_062_BLE_CY8C6347_M4)
board_runner_args(jlink "--device=CY8C6xx7_CM4" "--speed=2000")
endif()
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${... | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```unknown
/*
*
*/
#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
/ {
aliases {
uart-2 = &uart2;
};
chosen {
zephyr,console = &uart2;
zephyr,shell-uart = &uart2;
};
};
&uart2 {
status = "okay";
current-speed = <115200>;
interrupt-parent = <&intmux_ch21>;
pinctrl-0 = <&p9_0_scb2_uart_rx &p9_1_scb... | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 208 |
```yaml
#
#
#
identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m4
name: Cypress PSoC6 BLE Pioneer Kit (M4, rev. 0.0.0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- gpio
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```unknown
/*
*
*/
#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
/ {
aliases {
uart-6 = &uart6;
};
chosen {
zephyr,console = &uart6;
zephyr,shell-uart = &uart6;
};
};
&uart6 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>;
pinctrl-names = "defau... | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 126 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
# UART driver
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
# PSoC6 BLE Pioneer Kit configuration
config BOARD_CY8CKIT_062_BLE
select SOC_PART_NUMBER_CY8C6347BZI_BLD53
select SOC_CY8C6347_M0 if BOARD_CY8CKIT_062_BLE_CY8C6347_M0
select SOC_CY8C6347_M4 if BOARD_CY8CKIT_062_BLE_CY8C6347_M4
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 89 |
```unknown
/*
*
*/
/dts-v1/;
#include <infineon/cat1a/legacy/psoc6_cm0.dtsi>
#include "cy8ckit_062_ble_common.dtsi"
/ {
model = "Cypress PSoC6 BLE Pioneer Kit";
compatible = "cypress,cy8c6xx7_cm0p", "cypress,psoc6";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
};
&gpio_prt0 {
interrupt-pare... | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 159 |
```unknown
/*
*
*/
/dts-v1/;
#include <infineon/cat1a/legacy/psoc6_cm4.dtsi>
#include "cy8ckit_062_ble_common.dtsi"
/ {
model = "Cypress PSoC6 BLE Pioneer Kit";
compatible = "cypress,cy8c6xx7_cm4", "cypress,psoc6";
chosen {
zephyr,sram = &sram2;
zephyr,flash = &flash1;
};
};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```yaml
#
#
#
identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m0
name: Cypress PSoC6 BLE Pioneer Kit (M0, rev. 0.0.0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- arduino_spi
- gpio
- spi
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```yaml
board:
name: cy8ckit_062_ble
vendor: cypress
revision:
format: "major.minor.patch"
default: "0.0.0"
revisions:
- name: "0.0.0"
- name: "1.0.0"
socs:
- name: cy8c6347
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```restructuredtext
.. _cy8ckit_062_wifi_bt:
INFINEON PSoC6 WiFi-BT Pioneer Kit
##################################
Overview
********
The PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFi-BT) is a low-cost hardware
platform that enables design and debug of the PSoC 62 MCU and the Murata
LBEE5KL1DX Module (CYW4343W WiFi + ... | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,228 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
# UART driver
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
/*
* an affiliate of Cypress Semiconductor Corporation
*/
#include <infineon/cat1a/legacy/psoc6-pinctrl.dtsi>
/* Configure pin control bias mode for uart5 pins */
&p5_1_scb5_uart_tx {
drive-push-pull;
};
&p5_0_scb5_uart_rx {
input-enable;
};
&p9_1_scb2_uart_tx {
drive-push-pull;
};
&p9_0_scb2_uart_... | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```yaml
#
#
#
identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m0
name: Cypress PSoC6 BLE Pioneer Kit (M0, rev. 1.0.0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- arduino_spi
- gpio
- spi
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```yaml
#
#
#
identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m4
name: Cypress PSoC6 BLE Pioneer Kit (M4, rev. 1.0.0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- gpio
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases {
led0 = &user_led;
sw0 = &user_bt;
};
leds {
compatible = "gpio-leds";
user_led: led_0 {
label = "LED_0";
gpios = <&gpio_prt13 7 GPIO_ACTIVE_HIGH>;
};
};
gpio_keys {
compatible = "gpio-keys";
user_bt:... | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 974 |
```unknown
/*
*
*/
#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
/ {
aliases {
uart-5 = &uart5;
};
chosen {
zephyr,console = &uart5;
zephyr,shell-uart = &uart5;
};
};
&uart5 {
status = "okay";
current-speed = <115200>;
interrupt-parent = <&intmux_ch21>;
pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5... | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```ini
#
#
if {[info exists env(OPENOCD_INTERFACE)]} {
set INTERFACE $env(OPENOCD_INTERFACE)
} else {
# By default connect over Debug USB port
set INTERFACE "cmsis-dap"
}
source [find interface/$INTERFACE.cfg]
transport select swd
source [find target/psoc6.cfg]
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```restructuredtext
.. _boards-seeed:
Seeed Technology Co., Ltd
#########################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/seeed/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
/*
*
*/
/dts-v1/;
#include "xiao_ble_common.dtsi"
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/gpio/nordic-nrf-gpio.h>
/ {
model = "Seeed XIAO BLE Sense";
compatible = "seeed,xiao-ble", "seeed,xiao-ble-sense";
msm261d3526hicpm-c-en {
compatible = "regulator-fixed";
enable-... | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 441 |
```cmake
board_runner_args(nrfjprog "--nrf-family=NRF52")
board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000")
board_runner_args(uf2 "--board-id=Seeed_XIAO_nRF52840_Sense")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(... | /content/code_sandbox/boards/seeed/xiao_ble/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 181 |
```unknown
# XIAO BLE board configuration
config BOARD_XIAO_BLE
select SOC_NRF52840_QIAA
``` | /content/code_sandbox/boards/seeed/xiao_ble/Kconfig.xiao_ble | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/seeed/xiao_ble/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
# Logger cannot use itself to log
CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y
# Enable USB
CONFIG_USB_DEVICE_STACK=y
... | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
# Logger cannot use itself to log
CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y
# Enable USB
CONFIG_USB_DEVICE_STACK=y
... | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 129 |
```unknown
/*
*
*/
/ {
xiao_d: connector {
compatible = "seeed,xiao-gpio";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map
= <0 0 &gpio0 2 0> /* D0 */
, <1 0 &gpio0 3 0> /* D1 */
, <2 0 &gpio0 28 0> /* D2 */
, <3 0 &gpio0 29 0> /* D3 */
... | /content/code_sandbox/boards/seeed/xiao_ble/seeed_xiao_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 339 |
```yaml
identifier: xiao_ble
name: XIAO BLE
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- ble
- counter
- gpio
- i2c
- i2s
- pwm
- spi
- usb_device
- watchdog
- netif:openthread
vendor: seeed
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 116 |
```yaml
board:
name: xiao_ble
vendor: seeed
socs:
- name: nrf52840
variants:
- name: 'sense'
``` | /content/code_sandbox/boards/seeed/xiao_ble/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
# XIAO BLE board configuration
if BOARD_XIAO_BLE
config BT_CTLR
default BT
if USB_DEVICE_STACK
config UART_CONSOLE
default CONSOLE
config USB_DEVICE_INITIALIZE_AT_BOOT
default y
endif # USB_DEVICE_STACK
endif # BOARD_XIAO_BLE
``` | /content/code_sandbox/boards/seeed/xiao_ble/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```restructuredtext
.. _cy8ckit_062_ble:
INFINEON PSoC63 BLE Pioneer Kit
###############################
Overview
********
The PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that
enables design and debug of the Cypress PSoC 63 BLE MCU.
The PSoC 6 BLE Pioneer Kit features the PSoC 63 MCU: a dual-cor... | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,097 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 11)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 1, 12)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 11)>,
<NRF_PSEL(UART_RX, 1, 12)>;
low-power-ena... | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,186 |
```unknown
/*
*
*/
#include <nordic/nrf52840_qiaa.dtsi>
#include "xiao_ble-pinctrl.dtsi"
#include "seeed_xiao_connector.dtsi"
/ {
chosen {
zephyr,console = &usb_cdc_acm_uart;
zephyr,shell-uart = &usb_cdc_acm_uart;
zephyr,uart-mcumgr = &usb_cdc_acm_uart;
zephyr,bt-mon-uart = &usb_cdc_acm_uart;
zephyr,bt-c... | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,322 |
```unknown
/*
*
*/
/dts-v1/;
#include "xiao_ble_common.dtsi"
/ {
model = "Seeed XIAO BLE";
compatible = "seeed,xiao-ble";
};
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```yaml
identifier: xiao_ble/nrf52840/sense
name: XIAO BLE Sense
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- ble
- counter
- gpio
- i2c
- i2s
- pwm
- spi
- usb_device
- watchdog
- netif:openthread
vendor: seeed
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```cmake
board_runner_args(pyocd "--target=stm32wle5jcix")
board_runner_args(pyocd "--flash-opt=-O reset_type=hw")
board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset")
board_runner_args(jlink "--device=STM32WLE5JC" "--speed=4000" "--reset-after-load")
board_runner_args(stm32cubeprogrammer "--port=swd" "-... | /content/code_sandbox/boards/seeed/lora_e5_dev_board/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 202 |
```unknown
# Enable UART driver
CONFIG_SERIAL=y
# Enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable regulator for the power-rails
CONFIG_REGULATOR=y
# ... | /content/code_sandbox/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```yaml
identifier: lora_e5_dev_board
name: Seeedstudio LoRa-E5 Dev Board
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 256
supported:
- counter
- gpio
- i2c
- nvs
- spi
- uart
- watchdog
- lora
vendor: seeed studio
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```unknown
config BOARD_LORA_E5_DEV_BOARD
select SOC_STM32WLE5XX
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/Kconfig.lora_e5_dev_board | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```yaml
board:
name: lora_e5_dev_board
vendor: seeed
socs:
- name: stm32wle5xx
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```restructuredtext
.. _xiao_ble:
XIAO BLE (Sense)
################
Overview
********
The Seeed XIAO BLE (Sense) is a tiny (21 mm x 17.5 mm) Nordic Semiconductor
nRF52840 ARM Cortex-M4F development board with onboard LEDs, USB port, QSPI
flash, battery charger, and range of I/O broken out into 14 pins.
.. figure:: ... | /content/code_sandbox/boards/seeed/xiao_ble/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,736 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32wlx.cfg]
reset_config srst_only
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <seeed_studio/lora-e5.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Seeed Studio LoRa-E5 Dev Board";
compatible = "seeed,lora-e5-dev-board";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,fla... | /content/code_sandbox/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,451 |
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