text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```ini
# Explicitly for the STM32L475 Pandora board:
# path_to_url
# but perfectly functional for any other STM32L4 board connected via
# an stlink-v2-1 interface.
# This is for STM32L4 boards that are connected via stlink-v2-1.
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32l4x.cfg]
reset_config srst_only
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/alientek/pandora_stm32l475/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```unknown
/*
*
* Based on stm32l475_pandora:
*
*
*/
/dts-v1/;
#include <st/l4/stm32l475Xe.dtsi>
#include <st/l4/stm32l475v(c-e-g)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STM32L475 Pandora Development Board";
compatible = "alientek,pandora_stm32l475";
aliases {
led0 = &red_led;
sw0 = &joy_up;
};
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpioe 7 GPIO_ACTIVE_HIGH>;
label = "User LED_R";
};
green_led: led_1 {
gpios = <&gpioe 8 GPIO_ACTIVE_HIGH>;
label = "User LED_G";
};
blue_led: led_2 {
gpios = <&gpioe 9 GPIO_ACTIVE_HIGH>;
label = "User LED_B";
};
};
gpio_keys {
compatible = "gpio-keys";
joy_up: joystick_up {
label = "joystick up";
gpios = <&gpioc 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
zephyr,code = <INPUT_KEY_UP>;
};
joy_down: joystick_down {
label = "joystick down";
gpios = <&gpiod 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_DOWN>;
};
joy_left: joystick_left {
label = "joystick left";
gpios = <&gpiod 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_LEFT>;
};
joy_right: joystick_right {
label = "joystick right";
gpios = <&gpiod 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_RIGHT>;
};
};
};
&quadspi {
pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
&quadspi_bk1_io0_pe12 &quadspi_bk1_io1_pe13
&quadspi_bk1_io2_pe14 &quadspi_bk1_io3_pe15>;
pinctrl-names = "default";
status = "okay";
w25q128jv: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
qspi-max-frequency = <80000000>;
jedec-id = [ef 40 18];
spi-bus-width = <4>;
status = "okay";
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <20>;
div-p = <7>;
div-q = <2>;
div-r = <4>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(80)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
backup_regs {
status = "okay";
};
};
``` | /content/code_sandbox/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 926 |
```restructuredtext
.. _boards-efinix:
Efinix, Inc.
############
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/efinix/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
config BOARD_TITANIUM_TI60_F225
select SOC_EFINIX_SAPPHIRE
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/Kconfig.titanium_ti60_f225 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
/*
*
*/
/dts-v1/;
#include <efinix/sapphire_soc.dtsi>
/ {
model = "Efinix Titanium Ti60 F225";
compatible = "efinix,titanium-ti60-f225";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram0;
};
aliases {
led0 = &green_led;
};
leds {
compatible = "gpio-leds";
green_led: led_0 {
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
label = "Green LED 3";
};
red_led: led_1 {
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
label = "Red LED 2";
};
blue_led: led_2 {
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
label = "Blue LED 1";
};
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
&gpio0 {
status = "okay";
};
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/titanium_ti60_f225.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 254 |
```yaml
identifier: titanium_ti60_f225
name: titanium_ti60_f225 FPGA development kit with Efinix Sapphire riscv SoC
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 196608
supported:
- gpio
- uart
vendor: efinix
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/titanium_ti60_f225.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
board:
name: titanium_ti60_f225
vendor: efinix
socs:
- name: efinix_sapphire
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL=n
CONFIG_XIP=n
CONFIG_HEAP_MEM_POOL_SIZE=16384
CONFIG_INIT_STACKS=n
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/titanium_ti60_f225_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```restructuredtext
.. _pandora_stm32l475_board:
Alientek STM32L475 Pandora
##########################
Overview
********
The STM32L475 Pandora board features an ARM Cortex-M4 based STM32L475VE MCU
with a wide range of connectivity support and configurations. Here are
some highlights of the STM32L475 Pandora board:
- STM32L475Vx microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 package
- On-board ST-LINK/V2-1 supporting USB re-enumeration capability
- Three different interfaces supported on USB:
- Virtual com port
- Mass storage
- Debug port
- Pushbutton (reset)
- Four directions Joystick with selection
- USB OTG FS with micro-AB connector
- SAI Audio DAC, Stereo with output jack
- Digital microphone, accelerometer, magnetometer and gyroscope MEMS
- 128-Mbit Quad-SPI Flash memory
- MCU current ammeter with 4 ranges and auto-calibration
- Connector for external board or RF-EEPROM
- Four power supply options:
- ST-LINK/V2-1
- USB FS connector
- External 5 V
- CR2032 battery (not provided)
.. image:: img/pandora_stm32l475.jpg
:align: center
:alt: STM32L475 Pandora
More information about the board can be found at the `STM32L475 Pandora website`_.
Hardware
********
The STM32L475VE SoC provides the following hardware features:
- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode)
- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
- Clock Sources:
- 4 to 48 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
- Internal low-power 32 kHz RC ( |plusminus| 5%)
- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
LSE (better than |plusminus| 0.25 % accuracy)
- 3 PLLs for system clock, USB, audio, ADC
- RTC with HW calendar, alarms and calibration
- 16x timers:
- 2x 16-bit advanced motor-control
- 2x 32-bit and 7x 16-bit general purpose
- 2x 16-bit basic
- 2x low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- SysTick timer
- Up to 82 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
- Memories
- Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection
- Up to 128 KB of SRAM including 32 KB with hardware parity check
- External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories
- Quad SPI memory interface
- 4x digital filters for sigma delta modulator
- Rich analog peripherals (independent supply)
- 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
- 2x 12-bit DAC, low-power sample and hold
- 2x operational amplifiers with built-in PGA
- 2x ultra-low-power comparators
- 18x communication interfaces
- USB OTG 2.0 full-speed, LPM and BCD
- 2x SAIs (serial audio interface)
- 3x I2C FM+(1 Mbit/s), SMBus/PMBus
- 6x USARTs (ISO 7816, LIN, IrDA, modem)
- 3x SPIs (4x SPIs with the Quad SPI)
- CAN (2.0B Active) and SDMMC interface
- SWPMI single wire protocol master I/F
- 14-channel DMA controller
- True random number generator
- CRC calculation unit, 96-bit unique ID
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
Supported Features
==================
The Zephyr stm32l475ve_pandora board configuration supports the following hardware features:
+-----------+------------+----------------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+==============================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+----------------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+----------------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+----------------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------------------------------+
| I2C | on-chip | I2C-AHT10(Temperature and humidity sensor) |
| | | I2C-ICM2068(light environment sensor) |
+-----------+------------+----------------------------------------------+
| I2S | on-chip | I2S-ES8388(Audio Decoder) |
+-----------+------------+----------------------------------------------+
| USB | on-chip | I2S-OTG |
+-----------+------------+----------------------------------------------+
| SDIO | on-chip | SDIO-AP6181(WIFI) |
+-----------+------------+----------------------------------------------+
| SPI | on-chip | LCD-TFT |
+-----------+------------+----------------------------------------------+
| QSPI NOR | on-chip | flash |
+-----------+------------+----------------------------------------------+
| IR-RX/TX | on-board | Infrared Receiver(38Khz)/Transmitter |
+-----------+------------+----------------------------------------------+
| STLINK-V2 | on-board | STLINK-V2 Debugger |
+-----------+------------+----------------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig`
Connections and IOs
===================
STM32L475 Pandora Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
For more details please refer to `STM32L475 Pandora board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1_TX : PA9
- UART_1_RX : PA10
- LED_R : PE7
- LED_G : PE8
- LED_B : PE9
System Clock
------------
STM32L475 Pandora System Clock could be driven by an internal or external oscillator,
as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz,
driven by 16MHz high speed internal oscillator.
Serial Port
-----------
STM32L475 Pandora board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2.
Default settings are 115200 8N1.
Programming and Debugging
*************************
Flashing
========
STM32L475 Pandora board includes an ST-LINK/V2-1 embedded debug tool interface.
This interface is supported by the openocd version included in Zephyr SDK.
Flashing an application to STM32L475 Pandora
--------------------------------------------
Connect the STM32L475 Pandora to your host computer using the USB
port, then run a serial host program to connect with your Discovery
board. For example:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then, build and flash in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32l475ve_pandora
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! arm
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32l475ve_pandora
:maybe-skip-config:
:goals: debug
.. _STM32L475 Pandora website:
path_to_url
.. _STM32L475 Pandora board User Manual:
path_to_url
``` | /content/code_sandbox/boards/alientek/pandora_stm32l475/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,950 |
```restructuredtext
.. _boards-seagate:
Seagate Technology PLC
######################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/seagate/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```restructuredtext
.. _titanium_ti60_f225:
Efinix Titanium Ti60 F225
#########################
Overview
********
The Efinix Titanium Ti60 F225 development kit contains a Ti60 FPGA, which is fabricated on a 16nm process and deliver
high performance with the lowest possible power on a small physical size. In addition, Efinix offers Sapphire SoC IP,
which is a user-configurable RISC-V SoC based on the VexRiscv core with configurable feature set and extension.
Using the Efinity IP Manager, you can configure the SoC to include only the peripherals that you require.
.. figure:: img/ti60f225-board-top.jpg
:align: center
:alt: titanium_ti60_f225_board
Figure is the development board
Board block diagram
*******************
.. figure:: img/Ti60-BGA225-board-block-diagram.jpg
:align: center
:alt: titanium_ti60_f225_board-block-diagram
More information can be found on `Ti60F225`_ website.
Sapphire SoC setup on the FPGA guide
*************************************
Guide to setup the SoC found at `Efinix-Zephyr`_
Building
********
Build applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: titanium_ti60_f225
:goals: build
Flashing
********
Flashing the binary into SPI NOR flash requires Efinity programmer, Please find the guide at `Efinix-Zephyr`_
.. note::
The Zephyr RTOS has been verified using the SoC bitstream generated by Efinity IDE v2022.2.322.
References
**********
.. target-notes::
.. _Ti60F225: path_to_url
.. _Efinix-Zephyr: path_to_url
``` | /content/code_sandbox/boards/efinix/titanium_ti60_f225/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 412 |
```cmake
set(LEGEND_REVISIONS "25hdd" "25ssd" "35")
if (NOT DEFINED BOARD_REVISION)
set(BOARD_REVISION "25hdd")
else()
if (NOT BOARD_REVISION IN_LIST LEGEND_REVISIONS)
message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for Legend. Accepted revisions: ${LEGEND_REVISIONS}")
endif()
endif()
``` | /content/code_sandbox/boards/seagate/legend/revision.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```yaml
identifier: legend@25ssd
name: Legend (25sdd)
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- i2c
- pwm
- spi
testing:
ignore_tags:
- net
- bluetooth
vendor: seagate
``` | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```cmake
board_runner_args(jlink "--device=STM32F070CB" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/seagate/legend/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
/*
*
*/
/ {
model = "Seagate Legend 2.5 SSD board";
compatible = "legend25_ssd", "seagate,legend25_ssd";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>; /* 24MHz external clock */
status = "okay";
};
&pll {
clocks = <&clk_hse>;
prediv = <1>;
mul = <2>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
&led_strip_spi {
chain-length = <4>;
status = "okay";
};
&usb {
status = "okay";
};
``` | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_25ssd.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 164 |
```yaml
identifier: legend@25hdd
name: Legend (25hdd)
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- i2c
- pwm
- spi
testing:
ignore_tags:
- net
- bluetooth
vendor: seagate
``` | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```yaml
board:
name: legend
vendor: seagate
revision:
format: custom
socs:
- name: stm32f070xb
``` | /content/code_sandbox/boards/seagate/legend/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```yaml
identifier: legend@35
name: Legend (35)
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- i2c
- pwm
- spi
testing:
ignore_tags:
- net
- bluetooth
vendor: seagate
``` | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_35.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
/*
*
*/
/ {
model = "Seagate Legend 3.5 board";
compatible = "legend35", "seagate,legend35";
aliases {
pwm-led0 = &pwm_led0;
};
led_pwm: pwmleds {
compatible = "pwm-leds";
label = "LED PWM";
pwm_led0: pwm_led_0 {
label = "Activity LED";
pwms = <&pwm3 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>; /* 24MHz external clock */
status = "okay";
};
&pll {
clocks = <&clk_hse>;
prediv = <1>;
mul = <2>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
&led_strip_spi {
chain-length = <12>;
status = "okay";
};
&timers3 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&usb {
status = "okay";
};
``` | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_35.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 268 |
```unknown
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# GPIO Controller
CONFIG_GPIO=y
# Clock Control
CONFIG_CLOCK_CONTROL=y
# Enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/seagate/legend/legend_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
/*
*
*/
/ {
model = "Seagate Legend 2.5 HDD board";
compatible = "legend25_hdd", "seagate,legend25_hdd";
aliases {
pwm-led0 = &pwm_led0;
};
led_pwm: pwmleds {
compatible = "pwm-leds";
label = "LED PWM";
pwm_led0: pwm_led_0 {
label = "Activity LED";
pwms = <&pwm3 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
};
&clk_hsi {
status = "okay";
};
&pll {
clocks = <&clk_hsi>;
prediv = <1>;
mul = <6>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
&led_strip_spi {
chain-length = <6>;
status = "okay";
};
&timers3 {
status = "okay";
};
&pwm3 {
status = "okay";
};
``` | /content/code_sandbox/boards/seagate/legend/legend_stm32f070xb_25hdd.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 246 |
```unknown
# Legend board family configuration
if BOARD_LEGEND
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_LEGEND
``` | /content/code_sandbox/boards/seagate/legend/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
config BOARD_LEGEND
select SOC_STM32F070XB
``` | /content/code_sandbox/boards/seagate/legend/Kconfig.legend | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f0/stm32f070Xb.dtsi>
#include <st/f0/stm32f070cbtx-pinctrl.dtsi>
#include <zephyr/dt-bindings/led/led.h>
#include <zephyr/dt-bindings/led/seagate_legend_b1414.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
aliases {
watchdog0 = &iwdg;
led-strip = &led_strip_spi;
};
board_id: brd-id {
compatible = "gpio-keys";
brd_id0: brd_id_0 {
label = "BRD_ID_0";
gpios = <&gpioc 13 0>;
zephyr,code = <INPUT_KEY_0>;
};
brd_id1: brd_id_1 {
label = "BRD_ID_1";
gpios = <&gpioc 14 0>;
zephyr,code = <INPUT_KEY_1>;
};
brd_id2: brd_id_2 {
label = "BRD_ID_2";
gpios = <&gpioc 15 0>;
zephyr,code = <INPUT_KEY_2>;
};
};
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
dmas = <&dma1 3 0x20440>, <&dma1 2 0x20480>;
dma-names = "tx", "rx";
status = "okay";
led_strip_spi: b1414@0 {
compatible = "everlight,b1414", "worldsemi,ws2812-spi";
/* SPI */
reg = <0>; /* ignored, but necessary for SPI bindings */
spi-max-frequency = <SPI_FREQ>;
/* B1414 */
spi-one-frame = <ONE_FRAME>;
spi-zero-frame = <ZERO_FRAME>;
color-mapping = <LED_COLOR_ID_RED>,
<LED_COLOR_ID_GREEN>,
<LED_COLOR_ID_BLUE>;
reset-delay = <250>;
};
};
&spi2 {
pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
cs-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>;
status = "okay";
spi_nor: spi_nor@0 {
status = "okay";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <8000000>;
size = <1048576>;
/*
* Main flash source
*
* Vendor : Puya
* Model : P25Q21H
* Total size : 256 KB
* Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors,
* 256 B pages
* Write size : up to 256 B (page size)
* Lifetime : 100K erase/program cycles on each sector/block
*/
jedec-id = [85 40 12];
/*
* Alternate flash source
*
* Vendor : Fudan
* Model : FM25F01B
* Total size : 128 KB
* Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
* Write size : up to 256 B (page size)
* Lifetime : 100K erase/program cycles on each sector/block
*
* jedec-id = [a1 31 11];
*
* Model only found in first Jordan (2"5) EVT revision
*
* Vendor : Fudan
* Model : FM25F005
* Total size : 64 KB
* Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
*
* jedec-id = [a1 31 10];
*/
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
product_info: partition@0 {
label = "product-info";
reg = <0x00000000 DT_SIZE_K(4)>;
};
led_das: partition@10000 {
label = "led-das";
reg = <0x00001000 DT_SIZE_K(60)>;
};
};
};
};
&spi_nor {
status = "okay";
};
&dma1 {
status = "okay";
};
&timers3 {
/*
* The maximum period needed on Legend devices for activity LED
* hardware blinking is 250ms (i.e. "error" fast blink at 4 Hz).
*
* We can use the following equation to compute the
* corresponding prescaler value:
*
* period_max = counter_size / cycles_per_second
*
* With:
*
* cycles_per_second = 48 MHz / (prescaler + 1)
* counter_size = 2^16
* period_max = 0.25
*
* Which gives:
*
* prescaler = 48 MHz * 0.25 / 2^16 + 1 = 182
*
* So any prescaler value above 182 is good for a 4 Hz hardware
* blinking. In addition the PWM frequency must be as high as
* possible to fool eyes and cameras with steady brightness
* levels.
*/
st,prescaler = <200>;
pwm3: pwm {
pinctrl-0 = <&tim3_ch3_pb0>;
pinctrl-names = "default";
status = "disabled";
};
};
&gpiod {
status = "disabled";
};
&gpiof {
status = "disabled";
};
&iwdg {
status = "okay";
};
``` | /content/code_sandbox/boards/seagate/legend/legend.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,513 |
```ini
source [find board/st_nucleo_f0.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/seagate/legend/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```cmake
#
#
#
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/seagate/faze/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
config BOARD_FAZE
select SOC_LPC11U67
``` | /content/code_sandbox/boards/seagate/faze/Kconfig.faze | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```cmake
# Suppress DTC warnings due to all GPIO nodes sharing the same register address.
list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg")
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - /soc/flash@0 & /soc/gpio@0
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/seagate/faze/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```yaml
#
# Seagate FireCuda Gaming SSD (FaZe) board
#
#
identifier: faze
name: Seagate FireCuda Gaming SSD (FaZe)
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
supported:
- clock_controller
- eeprom
- gpio
- i2c
- serial
vendor: seagate
``` | /content/code_sandbox/boards/seagate/faze/faze.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 95 |
```unknown
/*
*/
#include <zephyr/dt-bindings/pinctrl/lpc11u6x-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group0 {
pinmux = <U0_RXD_PIO0_18>,
<U0_TXD_PIO0_19>;
nxp,disable-analog-filter;
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PIO0_4>,
<I2C0_SDA_PIO0_5>;
nxp,i2c-mode;
nxp,i2c-filter = "slow";
nxp,disable-analog-filter;
};
};
i2c0_fast: i2c0_fast {
group0 {
pinmux = <I2C0_SCL_PIO0_4>,
<I2C0_SDA_PIO0_5>;
nxp,i2c-mode;
nxp,i2c-filter = "fast";
nxp,disable-analog-filter;
};
};
i2c1_default: i2c1_default {
group0 {
pinmux = <I2C1_SCL_PIO0_7>,
<I2C1_SDA_PIO1_24>;
drive-open-drain;
nxp,i2c-mode;
nxp,i2c-filter = "slow";
nxp,disable-analog-filter;
};
};
i2c1_fast: i2c1_fast {
group0 {
pinmux = <I2C1_SCL_PIO0_7>,
<I2C1_SDA_PIO1_24>;
drive-open-drain;
nxp,i2c-mode;
nxp,i2c-filter = "fast";
nxp,disable-analog-filter;
};
};
syscon_default: syscon_default {
group0 {
pinmux = <XTALOUT_PIO2_1>,
<XTALIN_PIO2_0>;
nxp,analog-mode;
};
};
};
``` | /content/code_sandbox/boards/seagate/faze/faze-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 472 |
```restructuredtext
.. _legend:
Legend
######
Overview
********
The Legend board family contains three revisions: 25hdd, 25ssd, and 35.
The Legend 2.5" HDD board (revision 25hdd) can be found in the Seagate FireCuda
Gaming Hard Drive, Gaming Drive for Xbox and Gaming Drive for PlayStation
devices. A 2.5" drive and two chips are embedded: an ASMedia ASM1153 USB-to-SATA
bridge controller and a STM32F070 MCU. The former is handling the USB to HDD I/Os
while the latter is dedicated to the LED effects. The two chips are connected
together through I2C.
The Legend 2.5" SSD board (revision 25ssd) is found in the Seagate SSD Gaming
Drive for Xbox. A Realtek RTS5411S USB hub is embedded and connected to a Phison
U17 2.5" SSD, as well as a STM32F070 MCU.
The Legend 3.5" board (revision 35) can be found in the Seagate FireCuda Gaming
Hub and Gaming Drive Hub for Xbox devices. A Genesys Logic GL3523-S USB hub is
connected to an ASMedia ASM1153 USB-to-SATA bridge controller and a STM32F070
MCU. The two chips are connected together using I2C.
On all boards, the Zephyr port is running on the STM32F070 MCU.
.. image:: img/firecuda_gaming_hard_drive.jpg
:align: center
:alt: Seagate FireCuda Gaming Hard Drive
.. image:: img/firecuda_gaming_hub.jpg
:align: center
:alt: Seagate FireCuda Gaming Hub
Hardware
********
- STM32F070cb MCU:
- ARM Cortex-M0+
- 16KB SRAM
- 128KB on-chip flash
- External devices connected to the STM32F070cb MCU:
- ASMedia ASM1153 USB-to-SATA bridge (I2C master on port 1) (HDD only)
- 6 (hdd) or 4 (ssd) Everlight B1414 LEDs connected on SPI1 MOSI
- 1 white LED (HDD only)
- 64KB external SPI flash connected on SPI2
Supported Features
==================
All the hardware features available on the Legend boards are supported by
Zephyr.
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock and reset control |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c master/slave controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial |
+-----------+------------+-------------------------------------+
| SPI flash | on-chip | spi_nor |
+-----------+------------+-------------------------------------+
| LED strip | on-chip | ws2812 |
+-----------+------------+-------------------------------------+
| USB | on-chip | usb |
+-----------+------------+-------------------------------------+
Connections and IOs
===================
+---------+-----------------+----------------------------+
| Name | Function | Usage |
+=========+=================+============================+
| PB6 | I2C1 | I2C1 SCL (HDD only) |
+---------+-----------------+----------------------------+
| PB7 | I2C1 | I2C1 SDA (HDD only) |
+---------+-----------------+----------------------------+
| PA10 | UART | USART0 RX |
+---------+-----------------+----------------------------+
| PA9 | UART | USART0 TX |
+---------+-----------------+----------------------------+
| PB0 | PWM | Activity LED (HDD only) |
+---------+-----------------+----------------------------+
| PB12 | SPI2 | SPI2 Enable |
+---------+-----------------+----------------------------+
| PB13 | SPI2 | SPI2 Clock |
+---------+-----------------+----------------------------+
| PB14 | SPI2 | SPI2 MISO |
+---------+-----------------+----------------------------+
| PB15 | SPI2 | SPI2 MOSI |
+---------+-----------------+----------------------------+
| PA7 | LED strip | SPI1 MOSI |
+---------+-----------------+----------------------------+
| PA12 | USB | USB DM (25ssd and 35 only) |
+---------+-----------------+----------------------------+
| PA13 | USB | USB DP (25ssd and 35 only) |
+---------+-----------------+----------------------------+
Programming and Debugging
*************************
Flashing
========
The STM32F070cb MCU can be flashed by connecting an external debug probe to the
SWD port (on-board 4-pin header). In the default OpenOCD configuration, the
ST Link interface is selected. You may need to replace it with the interface of
your debug probe.
Once the debug probe is connected to both the Legend board and your host
computer, then you can simply run the ``west flash`` command to write a firmware
image into flash.
Debugging
=========
Please refer to the `Flashing`_ section and run the ``west debug`` command
instead of ``west flash``.
References
**********
- `STM32F070 reference manual`_
.. _STM32F070 reference manual:
path_to_url
``` | /content/code_sandbox/boards/seagate/legend/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,259 |
```yaml
board:
name: faze
vendor: seagate
socs:
- name: lpc11u67
``` | /content/code_sandbox/boards/seagate/faze/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```unknown
#
# Seagate FireCuda Gaming SSD (FaZe) board
#
#
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_MAIN_STACK_SIZE=512
CONFIG_ISR_STACK_SIZE=768
CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_SRAM1=y
CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_USB_RAM=y
CONFIG_CLOCK_CONTROL_LPC11U6X_PLL_SRC_SYSOSC=y
``` | /content/code_sandbox/boards/seagate/faze/faze_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_lpc11u67.dtsi>
#include <zephyr/dt-bindings/led/led.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "faze-pinctrl.dtsi"
/ {
model = "Seagate FireCuda Gaming SSD (FaZe)";
compatible = "faze", "seagate,faze";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
/* These aliases are provided for compatibility with samples. */
aliases {
led0 = &sata_led;
sw0 = &usb_sleep_button;
eeprom-0 = &eeprom0;
led-controller-0 = &led_controller_0;
};
gpio_keys {
compatible = "gpio-keys";
/* Handle the USB_SLEEP GPIO as a button. */
usb_sleep_button: button_0 {
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
label = "USB sleep button";
zephyr,code = <INPUT_KEY_SLEEP>;
};
};
leds {
compatible = "gpio-leds";
sata_led: led_0 {
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
label = "SSD activity LED";
};
};
};
&uart0 {
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_fast>;
pinctrl-names = "default", "fast-plus";
status = "okay";
asm2364: asm2364@30 {
compatible = "asmedia,asm2364";
int-gpios = <&gpio0 2 0>;
reg = <0x30>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_fast>;
pinctrl-names = "default", "fast-plus";
status = "okay";
/* TI LP5030 LED controller connected to I2C1. */
led_controller_0: lp5030@30 {
compatible = "ti,lp5030";
reg = <0x30>;
led0: led_0 {
label = "LED LP5030 0";
index = <0>;
color-mapping =
<LED_COLOR_ID_RED>,
<LED_COLOR_ID_GREEN>,
<LED_COLOR_ID_BLUE>;
};
led1: led_1 {
label = "LED LP5030 1";
index = <1>;
color-mapping =
<LED_COLOR_ID_RED>,
<LED_COLOR_ID_GREEN>,
<LED_COLOR_ID_BLUE>;
};
led2: led_2 {
label = "LED LP5030 2";
index = <2>;
color-mapping =
<LED_COLOR_ID_RED>,
<LED_COLOR_ID_GREEN>,
<LED_COLOR_ID_BLUE>;
};
led3: led_3 {
label = "LED LP5030 3";
index = <3>;
color-mapping =
<LED_COLOR_ID_RED>,
<LED_COLOR_ID_GREEN>,
<LED_COLOR_ID_BLUE>;
};
led4: led_4 {
label = "LED LP5030 4";
index = <4>;
color-mapping =
<LED_COLOR_ID_RED>,
<LED_COLOR_ID_GREEN>,
<LED_COLOR_ID_BLUE>;
};
led5: led_5 {
label = "LED LP5030 5";
index = <5>;
color-mapping =
<LED_COLOR_ID_RED>,
<LED_COLOR_ID_GREEN>,
<LED_COLOR_ID_BLUE>;
};
};
};
&syscon {
pinctrl-0 = <&syscon_default>;
pinctrl-names = "default";
};
&cpu0 {
clock-frequency = <48000000>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
``` | /content/code_sandbox/boards/seagate/faze/faze.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 985 |
```ini
#
# Seagate FireCuda Gaming SSD (FaZe) board
#
# An external debug probe must be connected to the SWD port (4-pins J2 header).
# Here we assume that a ST-LINK in-circuit debugger/programmer is used. You may
# have to replace it with your own interface here.
source [find interface/stlink.cfg]
# NXP LPC11U24 Cortex-M0 with 128KB Flash and 20KB + 4KB SRAM
set WORKAREASIZE 0x5000
set CPUTAPID 0x0bc11477
source [find target/lpc11xx.cfg]
# This ensures that the interrupt vectors (0x0000-0x0200) are re-mapped to
# flash after the "reset halt" command. Else the load/verify functions won't
# work correctly.
#
# Table 8. System memory remap register (SYSMEMREMAP, address 0x40048000) bit
# description
# Bit Symbol Value Description
# 1:0 MAP System memory remap
# 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to
# Boot ROM.
# 0x1 User RAM Mode. Interrupt vectors are re-mapped to
# Static RAM.
# 0x2 User Flash Mode. Interrupt vectors are not re-mapped
# and reside in Flash.
# 31:2 - - Reserved.
$_TARGETNAME configure -event reset-end {
mww 0x40048000 0x02
}
# Enable Zephyr thread awareness.
$_TARGETNAME configure -rtos Zephyr
adapter speed 100
``` | /content/code_sandbox/boards/seagate/faze/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 368 |
```restructuredtext
.. _boards-cdns:
Cadence Design Systems Inc.
###########################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/cdns/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```cmake
board_set_debugger_ifnset(xtensa)
``` | /content/code_sandbox/boards/cdns/xt-sim/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_SIMULATOR_XTENSA=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=2000000
``` | /content/code_sandbox/boards/cdns/xt-sim/xt-sim_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
# XTENSA board configuration
config BOARD_XT_SIM
select SOC_XTENSA_SAMPLE_CONTROLLER
``` | /content/code_sandbox/boards/cdns/xt-sim/Kconfig.xt-sim | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```yaml
board:
name: xt-sim
vendor: cdns
socs:
- name: xtensa_sample_controller
``` | /content/code_sandbox/boards/cdns/xt-sim/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```yaml
identifier: xt-sim
name: XT Simulator
type: sim
arch: xtensa
toolchain:
- xcc
testing:
default: true
``` | /content/code_sandbox/boards/cdns/xt-sim/xt-sim.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
config IPM_CONSOLE_STACK_SIZE
default 2048 if IPM_CONSOLE_RECEIVER
``` | /content/code_sandbox/boards/cdns/xt-sim/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
/*
*
*/
/dts-v1/;
#include "sample_controller.dtsi"
/ {
model = "xt-sim";
compatible = "cdns,xtensa-sample-controller";
chosen {
zephyr,sram = &sram0;
};
};
&cpu0 {
clock-frequency = <10000000>;
};
``` | /content/code_sandbox/boards/cdns/xt-sim/xt-sim.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```restructuredtext
.. _faze:
Seagate FireCuda Gaming SSD (FaZe) board
########################################
Overview
********
The FaZe board can be found in the Seagate FireCuda Gaming SSD devices. A NVMe
SSD and two chips are embedded: an ASMedia ASM2364 USB-to-PCIe bridge controller
and a NXP LPC11U67 MCU. The former is handling the USB type-C to SSD I/Os while
the latter is dedicated to the LED effects. The two chips are connected together
through I2C and GPIOs.
This Zephyr port is running on the NXP LPC11U67 MCU.
.. image:: firecuda-gaming-ssd.jpg
:align: center
:alt: Seagate FireCuda Gaming SSD
Hardware
********
- NXP LPC11U67 MCU (LQFP48 package):
- ARM Cortex-M0+
- 20 KB SRAM: 16 KB (SRAM0) + 2 KB (SRAM1) + 2KB (USB SRAM)
- 128 KB on-chip flash
- 4 KB on-chip EEPROM
- External devices connected to the NXP LPC11U67 MCU:
- ASMedia ASM2364 USB-to-PCIe bridge (I2C master on port O).
- 6 RGB LEDs connected to a TI LP5030 LED controller (I2C device on
port 1).
- 1 white LED (SSD activity blinking).
More information can be found here:
- `LPC11UXX SoC Website`_
- `LPC11U6X Datasheet`_
- `LPC11U6X Reference Manual`_
Supported Features
==================
All the hardware features available on the FaZe board are supported in Zephyr.
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| IOCON | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock and reset control |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c master/slave controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port interrupt |
+-----------+------------+-------------------------------------+
| EEPROM | on-chip | eeprom |
+-----------+------------+-------------------------------------+
Connections and IOs
===================
The IOCON controller can be used to configure the LPC11U67 pins.
+---------+-----------------+----------------------------+
| Name | Function | Usage |
+=========+=================+============================+
| PIO0_2 | GPIO | ASM2364 interrupt |
+---------+-----------------+----------------------------+
| PIO0_4 | I2C0 | I2C0 SCL |
+---------+-----------------+----------------------------+
| PIO0_5 | I2C0 | I2C0 SDA |
+---------+-----------------+----------------------------+
| PIO0_7 | I2C1 | I2C1 SCL |
+---------+-----------------+----------------------------+
| PIO0_18 | UART | USART0 RX |
+---------+-----------------+----------------------------+
| PIO0_19 | UART | USART0 TX |
+---------+-----------------+----------------------------+
| PIO0_20 | GPIO | USB sleep |
+---------+-----------------+----------------------------+
| PIO1_23 | GPIO | SSD activity white LED |
+---------+-----------------+----------------------------+
| PIO1_24 | I2C1 | I2C1 SDA |
+---------+-----------------+----------------------------+
Programming and Debugging
*************************
Flashing
========
The NXP LPC11U67 MCU can be flashed by connecting an external debug probe to
the SWD port (on-board 4-pins J2 header). In the default OpenOCD configuration
(:zephyr_file:`boards/seagate/faze/support/openocd.cfg`) the ST Link interface is selected.
You may need to replace it with the interface of your debug probe.
Once the debug probe is connected to both the FaZe board and your host computer
then you can simply run the ``west flash`` command to write a firmware image you
built into flash.
Debugging
=========
Please refer to the `Flashing`_ section and run the ``west debug`` command
instead of ``west flash``.
References
**********
- `LPC11UXX SoC Website`_
- `LPC11U6X Datasheet`_
- `LPC11U6X Reference Manual`_
.. _LPC11UXX SoC Website:
path_to_url
.. _LPC11U6X Datasheet:
path_to_url
.. _LPC11U6x Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/seagate/faze/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,138 |
```restructuredtext
.. _boards-cypress:
Cypress
#######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/cypress/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*
*/
/dts-v1/;
#include <infineon/cat1a/legacy/psoc6_cm4.dtsi>
#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi"
/ {
model = "cy8ckit_062_wifi_bt_m4 with a Cypress PSoC6 SoC";
compatible = "cypress,cy8ckit_062_wifi_bt_m4", "cypress,PSoC6";
aliases {
uart-5 = &uart5;
};
chosen {
zephyr,sram = &sram2;
zephyr,flash = &flash1;
zephyr,console = &uart5;
zephyr,shell-uart = &uart5;
};
};
&uart5 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 225 |
```cmake
#
#
#
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
set(CY8C6247BZI_D54)
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```yaml
#
#
#
identifier: cy8ckit_062_wifi_bt/cy8c6247/m0
name: Cypress PSoC6 WiFi-BT Pioneer Kit (M0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```yaml
#
#
#
identifier: cy8ckit_062_wifi_bt/cy8c6247/m4
name: Cypress PSoC6 WiFi-BT Pioneer Kit (M4)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```yaml
board:
name: cy8ckit_062_wifi_bt
vendor: cypress
socs:
- name: cy8c6247
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
# UART driver
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
# UART driver
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```restructuredtext
.. _xt-sim:
Xtensa simulator
################
Overview
********
The Xtensa processor architecture is a configurable, extensible, and
synthesizable 32-bit RISC processor core. Processor and SOC vendors can select
from various processor options and even create customized instructions in
addition to a base ISA to tailor the processor for a particular application.
For more information, see path_to_url
.. figure:: img/xt-sim.jpg
:align: center
:alt: Xtensa Xplorer (Eclipse base frontend for xt-sim)
Xtensa Xplorer
Hardware
********
The following Xtensa cores are officially supported:
- sample_controller
System Clock
============
Xtensa cores can be configured to use either internal or external timers.
The frequency of the clock under simulation is set to 25MHz.
System requirements
*******************
Prerequisites
=============
A Linux host system is required for Xtensa development work.
We recommend using a __``Debian 9.x (Stretch)``__ or recent __``Ubuntu``__
releases (with multilib support).
Only Xtensa tools version ``RF-2016.4-linux`` or later are officially
supported. Other versions may work but are not supported by Cadence Systems Inc.
In order to set up the Zephyr OS build system, a Linux 32-bit GCC compiler must
be installed on the building linux box. Install GCC if needed either by
downloading ``Zephyr SDK`` or by using your distribution package manager.
On Debian/Ubuntu systems, you can install ``gcc-multilib`` package as follows:
.. code-block:: console
#aptitude install gcc-multilib # Or what ever package manager (apt, apt-get, ...)
Set up build environment
========================
We recommend you create a ``~/.zephyrrc`` file, a shell script that shall be
sourced each time before you start working on Zephyr.
You can use the following code to create that file:
.. code-block:: console
$ cat > ~/.zephyrrc
if test "${CROSS}" = xcc
then
export ARCH=xtensa
export BOARD=xt-sim
export ZEPHYR_TOOLCHAIN_VARIANT=xcc
export XTENSA_TOOLS_PATH=/opt/xtensa/XtDevTools/install/tools/RG-2016.4-linux/XtensaTools
export XTENSA_BUILDS_PATH=/opt/xtensa/XtDevTools/install/builds/RG-2016.4-linux
#export XTENSA_BUILD_DIR= #Keep empty to use default directory
export EMU_PLATFORM=xt-run
elif test "${CROSS}" = zephyr-xtensa
then
export ARCH=xtensa
export BOARD=qemu
export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
export ZEPHYR_SDK_INSTALL_DIR=/opt/xtensa/zephyr-sdk-64-INTERNAL-11-22-2016
elif test "${CROSS}" = zephyr-x86
then
export ARCH=x86
export BOARD=qemu_x86
export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
export ZEPHYR_SDK_INSTALL_DIR=/opt/xtensa/zephyr-sdk-64-INTERNAL-11-22-2016
else
echo "Unsupported compiler '${CROSS}' defined by environment variable CROSS"
fi
Once the ``~/.zephyrrc`` file is created, you can start working. However, each
time you start a new shell you will need to execute the following commands
before you can compile anything:
.. code-block:: console
$ cd path/to/zephyr # replace path/to by a real path
$ CROSS=xcc source zephyr-env.sh # Select xcc as compiler
Adding a user-defined Xtensa core
=================================
Add your own core to the list of supported cores as follows:
.. code-block:: console
$ XTENSA_CORE=myCore
$ $(which echo) -e "config ${XTENSA_CORE}\n\tbool \"${XTENSA_CORE} core\"\n" >> "soc/xtensa/Kconfig.cores"
Create a folder for that core:
.. code-block:: console
$ mkdir soc/xtensa/${XTENSA_CORE}
Create and copy to that folder a custom linker script (more on linker script in next section):
.. code-block:: console
$ cp linker.ld soc/xtensa/${XTENSA_CORE}/linker.ld
Add a Makefile:
.. code-block:: console
$ echo "obj-y = soc.o" > soc/xtensa/${XTENSA_CORE}/Makefile
Add Zephyr specific sections to the linker script.
The file "soc/xtensa/linker_more.ld" contains Zephyr-specific linker
sections that should be added to the default linker script linker.ld (inside
SECTIONS region). If you are not using a linker script, you must create one
and add these sections. The memory segment and PHDR should be replaced by
appropriate values.
The linker script should be named ``linker.ld`` and placed in the directory
``soc/xtensa/${XTENSA_CORE}``.
Configuring build
=================
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:goals: menuconfig
Below is an example of usage for typical configuration:
1. Select ``Architecture``
a. Select ``Xtensa architecture``
2. Select ``XTENSA core Selection``
a. Select appropriate core (example ``hifi3_bd5 core``)
3. Select ``XTENSA Options``
a. Set ``Hardware clock cycles per second`` to appropriate value
b. Set ``The path to Xtensa tool`` to appropriate value
c. Set ``The version of Xtensa tool`` to appropriate version
d. Set ``Xtensa build directory`` to appropriate value
4. Select ``Board Selection``
a. Select ``Xtensa Development ISS``
5. Select ``Device Drivers``
a. Uncheck ``Serial Drivers``
6. Select ``Compile and Link Features``
a. Set compiler configuration and build options correctly to project requirements
7. Hit ``Exit`` and confirm saving the changes.
You may need to change other options in menuconfig depending on his project
specific needs.
Compiling and running
=====================
The Xtensa executable can be run in the simulator either with a standalone core,
or with a core connected to simulated peripherals.
Build and run as follows:
.. zephyr-app-commands::
:goals: run
References
**********
.. _Xtensa tools: path_to_url
``` | /content/code_sandbox/boards/cdns/xt-sim/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,427 |
```unknown
/*
*
*/
/dts-v1/;
#include <infineon/cat1a/legacy/psoc6_cm0.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi"
/ {
model = "cy8ckit_062_wifi_bt_m0 with a Cypress PSoC6 SoC";
compatible = "cypress,cy8ckit_062_wifi_bt_m0", "cypress,PSoC6";
aliases {
sw0 = &user_bt;
led0 = &user_led;
uart-6 = &uart6;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart6;
zephyr,shell-uart = &uart6;
};
leds {
compatible = "gpio-leds";
user_led: led_0 {
label = "LED_0";
gpios = <&gpio_prt13 7 GPIO_ACTIVE_HIGH>;
};
};
gpio_keys {
compatible = "gpio-keys";
user_bt: button_0 {
label = "SW_0";
gpios = <&gpio_prt0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
};
};
&gpio_prt0 {
status = "okay";
interrupt-parent = <&intmux_ch20>;
};
&gpio_prt13 {
status = "okay";
};
&uart6 {
status = "okay";
current-speed = <115200>;
interrupt-parent = <&intmux_ch21>;
pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 421 |
```unknown
# PSoC6 WiFi-BT Pioneer Kit configuration
config BOARD_CY8CKIT_062_WIFI_BT
select SOC_PART_NUMBER_CY8C6247BZI_D54
select SOC_CY8C6247_M0 if BOARD_CY8CKIT_062_WIFI_BT_CY8C6247_M0
select SOC_CY8C6247_M4 if BOARD_CY8CKIT_062_WIFI_BT_CY8C6247_M4
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```ini
#
#
if {[info exists env(OPENOCD_INTERFACE)]} {
set INTERFACE $env(OPENOCD_INTERFACE)
} else {
# By default connect over Debug USB port
set INTERFACE "cmsis-dap"
}
source [find interface/$INTERFACE.cfg]
transport select swd
source [find target/psoc6.cfg]
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
/*
* an affiliate of Cypress Semiconductor Corporation
*/
#include <infineon/cat1a/legacy/psoc6-pinctrl.dtsi>
/* Configure pin control bias mode for uart5 pins */
&p5_1_scb5_uart_tx {
drive-push-pull;
};
&p5_0_scb5_uart_rx {
input-enable;
};
&p9_1_scb2_uart_tx {
drive-push-pull;
};
&p9_0_scb2_uart_rx {
input-enable;
};
&p13_1_scb6_uart_tx {
drive-push-pull;
};
&p13_0_scb6_uart_rx {
input-enable;
};
/* Configure pin control bias mode for SPI pins */
&p12_0_scb6_spi_m_mosi {
drive-push-pull;
};
&p12_1_scb6_spi_m_miso {
input-enable;
};
&p12_2_scb6_spi_m_clk {
drive-push-pull;
};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```cmake
#
#
#
if(CONFIG_BOARD_CY8CKIT_062_BLE_CY8C6347_M0)
board_runner_args(jlink "--device=CY8C6xx7_CM0p" "--speed=2000")
elseif(CONFIG_BOARD_CY8CKIT_062_BLE_CY8C6347_M4)
board_runner_args(jlink "--device=CY8C6xx7_CM4" "--speed=2000")
endif()
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```unknown
/*
*
*/
#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
/ {
aliases {
uart-2 = &uart2;
};
chosen {
zephyr,console = &uart2;
zephyr,shell-uart = &uart2;
};
};
&uart2 {
status = "okay";
current-speed = <115200>;
interrupt-parent = <&intmux_ch21>;
pinctrl-0 = <&p9_0_scb2_uart_rx &p9_1_scb2_uart_tx>;
pinctrl-names = "default";
};
&uart5 {
status = "okay";
current-speed = <115200>;
interrupt-parent = <&intmux_ch22>;
pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>;
pinctrl-names = "default";
};
arduino_serial: &uart5 {};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 208 |
```yaml
#
#
#
identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m4
name: Cypress PSoC6 BLE Pioneer Kit (M4, rev. 0.0.0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- gpio
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```unknown
/*
*
*/
#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
/ {
aliases {
uart-6 = &uart6;
};
chosen {
zephyr,console = &uart6;
zephyr,shell-uart = &uart6;
};
};
&uart6 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 126 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
# UART driver
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
# PSoC6 BLE Pioneer Kit configuration
config BOARD_CY8CKIT_062_BLE
select SOC_PART_NUMBER_CY8C6347BZI_BLD53
select SOC_CY8C6347_M0 if BOARD_CY8CKIT_062_BLE_CY8C6347_M0
select SOC_CY8C6347_M4 if BOARD_CY8CKIT_062_BLE_CY8C6347_M4
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 89 |
```unknown
/*
*
*/
/dts-v1/;
#include <infineon/cat1a/legacy/psoc6_cm0.dtsi>
#include "cy8ckit_062_ble_common.dtsi"
/ {
model = "Cypress PSoC6 BLE Pioneer Kit";
compatible = "cypress,cy8c6xx7_cm0p", "cypress,psoc6";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
};
&gpio_prt0 {
interrupt-parent = <&intmux_ch20>;
};
&spi6 {
status = "okay";
interrupt-parent = <&intmux_ch16>;
};
arduino_spi: &spi6 {};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 159 |
```unknown
/*
*
*/
/dts-v1/;
#include <infineon/cat1a/legacy/psoc6_cm4.dtsi>
#include "cy8ckit_062_ble_common.dtsi"
/ {
model = "Cypress PSoC6 BLE Pioneer Kit";
compatible = "cypress,cy8c6xx7_cm4", "cypress,psoc6";
chosen {
zephyr,sram = &sram2;
zephyr,flash = &flash1;
};
};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```yaml
#
#
#
identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m0
name: Cypress PSoC6 BLE Pioneer Kit (M0, rev. 0.0.0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- arduino_spi
- gpio
- spi
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```yaml
board:
name: cy8ckit_062_ble
vendor: cypress
revision:
format: "major.minor.patch"
default: "0.0.0"
revisions:
- name: "0.0.0"
- name: "1.0.0"
socs:
- name: cy8c6347
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```restructuredtext
.. _cy8ckit_062_wifi_bt:
INFINEON PSoC6 WiFi-BT Pioneer Kit
##################################
Overview
********
The PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFi-BT) is a low-cost hardware
platform that enables design and debug of the PSoC 62 MCU and the Murata
LBEE5KL1DX Module (CYW4343W WiFi + Bluetooth Combo Chip).
The PSoC 6 WiFi-BT Pioneer Kit features the PSoC 62 MCU: a
dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application
processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations,
1MB of Flash, 288KB of SRAM, 104 GPIO, 7 programmable analog blocks,
56 programmable digital blocks, Full-Speed USB, a serial memory interface,
a PDM-PCM digital microphone interface, and industry-leading capacitive-sensing
with CapSense.
The PSoC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields.
The Cortex-M0+ is a primary core on the board's SoC. It starts first and
enables the CM4 core.
.. image:: img/cy8ckit_062_wifi_bt_m0.jpg
:align: center
:alt: CY8CKIT_062_WIFI_BT
1. USB PD output voltage availability indicator (LED7)
2. Battery charging indicator (LED6)
3. KitProg2 USB Type-C connector (J10)
4. Cypress EZ-PD CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3)
5. KitProg2 programming mode selection button (SW3)
6. KitProg2 I/O header (J6)1
7. KitProg2 programming/custom application header (J7)1
8. External power supply connector (J9)
9. PSoC 6 user button (SW2)
10. KitProg2 application selection button (SW4)
11. Digilent Pmod compatible I/O header (J14)1
12. Power LED (LED4)
13. KitProg2 status LEDs (LED1, LED2, and LED3)
14. PSoC 6 reset button (SW1)
15. PSoC 6 I/O header (J18, J19 and J20)
16. Arduino Uno R3 compatible power header (J1)
17. PSoC 6 debug and trace header (J12)
18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4)
19. PSoC 6 program and debug header (J11)
20. CapSense proximity header (J13)
21. CapSense slider and buttons
22. PSoC 6 VDD selection switch (SW5)
23. Cypress 512-Mbit serial NOR Flash memory (S25-FL512S, U4)
24. PSoC 6 user LEDs (LED8 and LED9)
25. RGB LED (LED5)
26. WiFi/BT module (LBEE5KL 1DX, U6)
27. Cypress serial Ferroelectric RAM (U5)1
28. WiFi-BT Antenna
29. VBACKUP and PMIC control selection switch (SW7)2
30. PSoC 6 USB device Type-C connector (J28)
31. Cypress PSoC 6 (CY8C6247BZI-D54, U1)
32. PSoC 6 USB Host Type-A connector (J27)
33. Arduino Uno R3 compatible ICSP header (J5)1
34. PSoC 6 power monitoring jumper (J8)2
35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2)
36. Battery connector (J15)1,2
37. USB PD output voltage (9V/12V) connector (J16)
Hardware
********
For more information about the PSoC 62 MCU SoC and CY8CKIT-062-WiFi-BT board:
- `PSoC 62 MCU SoC Website`_
- `PSoC 62 MCU Datasheet`_
- `PSoC 62 MCU Architecture Reference Manual`_
- `PSoC 62 MCU Register Reference Manual`_
- `CY8CKIT-062-WiFi-BT Website`_
- `CY8CKIT-062-WiFi-BT User Guide`_
- `CY8CKIT-062-WiFi-BT Schematics`_
Supported Features
==================
The board configuration supports the following hardware features:
+-----------+------------+-----------------------+
| Interface | Controller | Driver/Component |
+===========+============+=======================+
| NVIC | on-chip | nested vectored |
| | | interrupt controller |
+-----------+------------+-----------------------+
| SYSTICK | on-chip | system clock |
+-----------+------------+-----------------------+
| PINCTRL | on-chip | pin control |
+-----------+------------+-----------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-----------------------+
The default configuration can be found in the Kconfig
:zephyr_file:`boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig`.
System Clock
============
The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for
the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the
system clock are provided in the SOC, depending on your system requirements.
Serial Port
===========
The PSoC 62 MCU SoC has 9 SCB blocks 8 of each can be configured as UART
interfaces for serial communication. At the moment UART5 on SCB5 and UART6 on
SCB6 are configured. SCB5 is connected to the onboard KitProg2's USB-UART
Bridge, SCB6 to P12_0, P12_1 pins on the J3 of the Arduino Uno R3 compatible
PSoC6 I/O header.
OpenOCD Installation
====================
To get the OpenOCD package, it is required that you
1. Download the software ModusToolbox 3.1. path_to_url
2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox
export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts
3. Add the OpenOCD executable file's path to west flash/debug.
4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd
5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd
Programming and Debugging
*************************
The CY8CKIT-062-WiFi-BT includes an onboard programmer/debugger (KitProg2) with
mass storage programming to provide debugging, flash programming, and serial
communication over USB. There are also PSoC 6 program and debug headers J11
and J12 that can be used with Segger J-Link.
A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and
Cy_WDT_Disable().
Only the CM0+ core starts by default after the MCU reset. In order to have
CM4 core working FW for both cores should be written into Flash. CM0+ FW
should starts the CM4 core at one point using
Cy_SysEnableCM4(CM4_START_ADDRESS); call. CM4_START_ADDRESS is 0x10060000 in
the current configuration. The CM0+/CM4 Flash/SRAM areas are defined in
:zephyr_file:`dts/arm/cypress/psoc6.dtsi`.
Build the project for CM0+
.. zephyr-app-commands::
:board: cy8ckit_062_wifi_bt/cy8c6247/m0
:goals: build
Switch the DevKit into CMSIS-DAP mode using SW3 (LED2 should blink) and flash
the board:
.. code-block:: console
$<openocd_path>\bin\openocd -c "source [find interface/cmsis-dap.cfg]" \
-c "transport select swd" -c "source [find target/psoc6.cfg]" \
-c "if [catch {program {<zephyr_path>\samples\hello_world\build\zephyr\zephyr.elf}} ] \
{ echo {** Program operation failed **} } \
else { echo {** Program operation completed successfully **} }" \
-c "reset_config srst_only;reset run;psoc6.dap dpreg 0x04 0x00;shutdown"
Switch the DevKit back using SW3. Open a serial terminal (minicom, putty,
etc.) and connect to the board with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Reset the board and the following message will appear on the corresponding
serial port:
.. code-block:: console
***** Booting Zephyr OS zephyr-v1.13.0-1877-g9d14874db1 *****
Hello World! cy8ckit_062_wifi_bt
References
**********
.. _PSoC 62 MCU SoC Website:
path_to_url
.. _PSoC 62 MCU Datasheet:
path_to_url
.. _PSoC 62 MCU Architecture Reference Manual:
path_to_url
.. _PSoC 62 MCU Register Reference Manual:
path_to_url
.. _CY8CKIT-062-WiFi-BT Website:
path_to_url
.. _CY8CKIT-062-WiFi-BT User Guide:
path_to_url
.. _CY8CKIT-062-WiFi-BT Schematics:
path_to_url
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,228 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
# UART driver
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
/*
* an affiliate of Cypress Semiconductor Corporation
*/
#include <infineon/cat1a/legacy/psoc6-pinctrl.dtsi>
/* Configure pin control bias mode for uart5 pins */
&p5_1_scb5_uart_tx {
drive-push-pull;
};
&p5_0_scb5_uart_rx {
input-enable;
};
&p9_1_scb2_uart_tx {
drive-push-pull;
};
&p9_0_scb2_uart_rx {
input-enable;
};
&p13_1_scb6_uart_tx {
drive-push-pull;
};
&p13_0_scb6_uart_rx {
input-enable;
};
/* Configure pin control bias mode for SPI pins */
&p12_0_scb6_spi_m_mosi {
drive-push-pull;
};
&p12_1_scb6_spi_m_miso {
input-enable;
};
&p12_2_scb6_spi_m_clk {
drive-push-pull;
};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```yaml
#
#
#
identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m0
name: Cypress PSoC6 BLE Pioneer Kit (M0, rev. 1.0.0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- arduino_spi
- gpio
- spi
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```yaml
#
#
#
identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m4
name: Cypress PSoC6 BLE Pioneer Kit (M4, rev. 1.0.0)
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- gpio
vendor: cypress
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases {
led0 = &user_led;
sw0 = &user_bt;
};
leds {
compatible = "gpio-leds";
user_led: led_0 {
label = "LED_0";
gpios = <&gpio_prt13 7 GPIO_ACTIVE_HIGH>;
};
};
gpio_keys {
compatible = "gpio-keys";
user_bt: button_0 {
label = "SW_0";
gpios = <&gpio_prt0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>; /* shared */
gpio-map = <0 0 &gpio_prt9 0 0>, /* A0- */
<1 0 &gpio_prt9 1 0>, /* A1- */
<2 0 &gpio_prt9 2 0>, /* A2- */
<3 0 &gpio_prt9 3 0>, /* A3- */
<4 0 &gpio_prt9 4 0>, /* A4- */
<5 0 &gpio_prt9 5 0>, /* A5- */
<6 0 &gpio_prt5 0 0>, /* D0-RX-5 */
<7 0 &gpio_prt5 1 0>, /* D1-TX-5 */
<8 0 &gpio_prt5 2 0>, /* D2-RTS-5 */
<9 0 &gpio_prt5 3 0>, /* D3-CTS-5 */
<10 0 &gpio_prt5 4 0>, /* D4- */
<11 0 &gpio_prt5 5 0>, /* D5- */
<12 0 &gpio_prt5 6 0>, /* D6- */
<13 0 &gpio_prt0 2 0>, /* D7- */
<14 0 &gpio_prt13 0 0>, /* D8-RX-6 y */
<15 0 &gpio_prt13 1 0>, /* D9-TX-6 y */
<16 0 &gpio_prt12 3 0>, /* D10-SPI6_SEL0 y */
<17 0 &gpio_prt12 0 0>, /* D11-SPI6_MOSI y */
<18 0 &gpio_prt12 1 0>, /* D12-SPI6_MISO y */
<19 0 &gpio_prt12 2 0>, /* D13-SPI6_CLK y */
<20 0 &gpio_prt6 1 0>, /* D14-SDAx */
<21 0 &gpio_prt6 0 0>; /* D15-SCLx */
};
};
&gpio_prt0 {
status = "okay";
};
&gpio_prt5 {
status = "okay";
};
&gpio_prt6 {
status = "okay";
};
&gpio_prt9 {
status = "okay";
};
&gpio_prt12 {
status = "okay";
};
&gpio_prt13 {
status = "okay";
};
&spi6 {
cs-gpios = <&gpio_prt12 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>,
<&gpio_prt13 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
pinctrl-0 = <&p12_0_scb6_spi_m_mosi &p12_1_scb6_spi_m_miso &p12_2_scb6_spi_m_clk>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 974 |
```unknown
/*
*
*/
#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
/ {
aliases {
uart-5 = &uart5;
};
chosen {
zephyr,console = &uart5;
zephyr,shell-uart = &uart5;
};
};
&uart5 {
status = "okay";
current-speed = <115200>;
interrupt-parent = <&intmux_ch21>;
pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>;
pinctrl-names = "default";
};
arduino_serial: &uart5 {};
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```ini
#
#
if {[info exists env(OPENOCD_INTERFACE)]} {
set INTERFACE $env(OPENOCD_INTERFACE)
} else {
# By default connect over Debug USB port
set INTERFACE "cmsis-dap"
}
source [find interface/$INTERFACE.cfg]
transport select swd
source [find target/psoc6.cfg]
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```restructuredtext
.. _boards-seeed:
Seeed Technology Co., Ltd
#########################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/seeed/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
/*
*
*/
/dts-v1/;
#include "xiao_ble_common.dtsi"
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/gpio/nordic-nrf-gpio.h>
/ {
model = "Seeed XIAO BLE Sense";
compatible = "seeed,xiao-ble", "seeed,xiao-ble-sense";
msm261d3526hicpm-c-en {
compatible = "regulator-fixed";
enable-gpios = <&gpio1 10 (NRF_GPIO_DRIVE_S0H1 | GPIO_ACTIVE_HIGH)>;
regulator-name = "MSM261D3526HICPM-C-EN";
};
lsm6ds3tr-c-en {
compatible = "regulator-fixed-sync", "regulator-fixed";
enable-gpios = <&gpio1 8 (NRF_GPIO_DRIVE_S0H1 | GPIO_ACTIVE_HIGH)>;
regulator-name = "LSM6DS3TR_C_EN";
regulator-boot-on;
startup-delay-us = <3000>;
};
};
&i2c0 {
compatible = "nordic,nrf-twim";
/* Cannot be used together with spi0. */
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
clock-frequency = <I2C_BITRATE_FAST>;
lsm6ds3tr_c: lsm6ds3tr-c@6a {
compatible = "st,lsm6dsl";
reg = <0x6a>;
irq-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&pdm0 {
pinctrl-0 = <&pdm0_default>;
pinctrl-1 = <&pdm0_sleep>;
pinctrl-names = "default", "sleep";
clock-source = "PCLK32M";
};
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 441 |
```cmake
board_runner_args(nrfjprog "--nrf-family=NRF52")
board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000")
board_runner_args(uf2 "--board-id=Seeed_XIAO_nRF52840_Sense")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake)
include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake)
``` | /content/code_sandbox/boards/seeed/xiao_ble/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 181 |
```unknown
# XIAO BLE board configuration
config BOARD_XIAO_BLE
select SOC_NRF52840_QIAA
``` | /content/code_sandbox/boards/seeed/xiao_ble/Kconfig.xiao_ble | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/seeed/xiao_ble/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
# Logger cannot use itself to log
CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y
# Enable USB
CONFIG_USB_DEVICE_STACK=y
# Build UF2 by default, supported by the Adafruit nRF52 Bootloader
CONFIG_BUILD_OUTPUT_UF2=y
CONFIG_USE_DT_CODE_PARTITION=y
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
# Logger cannot use itself to log
CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y
# Enable USB
CONFIG_USB_DEVICE_STACK=y
# Build UF2 by default, supported by the Adafruit nRF52 Bootloader
CONFIG_BUILD_OUTPUT_UF2=y
CONFIG_USE_DT_CODE_PARTITION=y
# Required to enable LSM6DS3TR-C power
CONFIG_REGULATOR=y
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 129 |
```unknown
/*
*
*/
/ {
xiao_d: connector {
compatible = "seeed,xiao-gpio";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map
= <0 0 &gpio0 2 0> /* D0 */
, <1 0 &gpio0 3 0> /* D1 */
, <2 0 &gpio0 28 0> /* D2 */
, <3 0 &gpio0 29 0> /* D3 */
, <4 0 &gpio0 4 0> /* D4 */
, <5 0 &gpio0 5 0> /* D5 */
, <6 0 &gpio1 11 0> /* D6 */
, <7 0 &gpio1 12 0> /* D7 */
, <8 0 &gpio1 13 0> /* D8 */
, <9 0 &gpio1 14 0> /* D9 */
, <10 0 &gpio1 15 0> /* D10 */
;
};
};
xiao_spi: &spi2 {};
xiao_i2c: &i2c1 {};
xiao_serial: &uart0 {};
xiao_adc: &adc {};
``` | /content/code_sandbox/boards/seeed/xiao_ble/seeed_xiao_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 339 |
```yaml
identifier: xiao_ble
name: XIAO BLE
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- ble
- counter
- gpio
- i2c
- i2s
- pwm
- spi
- usb_device
- watchdog
- netif:openthread
vendor: seeed
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 116 |
```yaml
board:
name: xiao_ble
vendor: seeed
socs:
- name: nrf52840
variants:
- name: 'sense'
``` | /content/code_sandbox/boards/seeed/xiao_ble/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
# XIAO BLE board configuration
if BOARD_XIAO_BLE
config BT_CTLR
default BT
if USB_DEVICE_STACK
config UART_CONSOLE
default CONSOLE
config USB_DEVICE_INITIALIZE_AT_BOOT
default y
endif # USB_DEVICE_STACK
endif # BOARD_XIAO_BLE
``` | /content/code_sandbox/boards/seeed/xiao_ble/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```restructuredtext
.. _cy8ckit_062_ble:
INFINEON PSoC63 BLE Pioneer Kit
###############################
Overview
********
The PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that
enables design and debug of the Cypress PSoC 63 BLE MCU.
The PSoC 6 BLE Pioneer Kit features the PSoC 63 MCU: a dual-core MCU, with a
150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm
Cortex-M0+ that supports low-power operations, 1MB of Flash, 288KB of SRAM,
an integrated BLE 4.2 radio, 78 GPIO, 7 programmable analog blocks, 12
programmable digital blocks, and capacitive-sensing with CapSense.
The PSoC 6 BLE Pioneer board offers compatibility with Arduino shields, a
512-Mb NOR flash, onboard programmer/debugger (KitProg2), USB Type-C power
delivery system (EZ-PD CCG3), 5-segment CapSense slider, two CapSense
buttons, one CapSense proximity sensing header, an RGB LED, two user LEDs,
and one push button.
The CY8CKIT-062-BLE package includes a CY8CKIT-028-EPD E-INK Display Shield
that contains a 2.7-inch E-INK display, a motion sensor, a thermistor, and a
PDM microphone. The kit package also contains a CY5677 CySmart BLE 4.2 USB
Dongle that is factory-programmed to emulate a BLE GAP Central device,
enabling you to emulate a BLE host on your computer.
The Cortex-M0+ is a primary core on the board's SoC. It starts first and
enables the CM4 core.
.. image:: img/cy8ckit-062-ble.jpg
:align: center
:alt: CY8CKIT_062_BLE
1. Battery charging indicator (LED6)
2. USB PD output voltage availability indicator (LED7)
3. KitProg2 USB Type-C connector (J10)
4. Cypress EZ-PD CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3)
5. KitProg2 programming mode selection button (SW3)
6. KitProg2 I/O header (J6)1
7. KitProg2 programming/custom application header (J7)1
8. External power supply connector (J9)
9. PSoC 6 BLE user button (SW2)
10. KitProg2 application selection button (SW4)
11. Digilent Pmod compatible I/O header (J14)1
12. Power LED (LED4)
13. KitProg2 status LEDs (LED1, LED2, and LED3)
14. PSoC 6 reset button (SW1)
15. PSoC 6 I/O header (J18, J19 and J20)
16. Arduino Uno R3 compatible power header (J1)
17. PSoC 6 debug and trace header (J12)
18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4)
19. PSoC 6 program and debug header (J11)
20. KitProg2 programming target selection switch (SW6)
21. CapSense slider and buttons
22. CapSense proximity header (J13)
23. PSoC 6 BLE VDD selection switch (SW5)
24. PSoC 6 BLE power monitoring jumper (J8)2
25. Arduino Uno R3 compatible ICSP header (J5)1
26. PSoC 6 user LEDs (LED8 and LED9)
27. RGB LED (LED5)
28. Cypress 512-Mbit serial NOR Flash memory (S25FL512S, U4)
29. Cypress serial Ferroelectric RAM (U5)1
30. VBACKUP and PMIC control selection switch (SW7)2
31. Cypress PSoC 6 BLE (CY8C6347BZI-BLD53, U1)
32. BLE Antenna
33. U.FL connector for external antenna (J17)1
34. Cypress main voltage regulator (MB39C022G, U6)
35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2)
36. Battery connector (J15)1,2
37. USB PD output voltage (9V/12V) connector (J16)
Hardware
********
For more information about the PSoC 63 BLE MCU SoC and CY8CKIT-062-BLE board:
- `PSoC 63 BLE MCU SoC Website`_
- `PSoC 63 BLE MCU Datasheet`_
- `PSoC 63 BLE MCU Architecture Reference Manual`_
- `PSoC 63 BLE MCU Register Reference Manual`_
- `CY8CKIT-062-BLE Website`_
- `CY8CKIT-062-BLE User Guide`_
- `CY8CKIT-062-BLE Schematics`_
Supported Features
==================
The board configuration supports the following hardware features:
+-----------+------------+-----------------------+
| Interface | Controller | Driver/Component |
+===========+============+=======================+
| NVIC | on-chip | nested vectored |
| | | interrupt controller |
+-----------+------------+-----------------------+
| SYSTICK | on-chip | system clock |
+-----------+------------+-----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-----------------------+
| PINCTRL | on-chip | pin control |
+-----------+------------+-----------------------+
| SPI | on-chip | spi |
+-----------+------------+-----------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-----------------------+
The default configurations can be found in the Kconfig
:zephyr_file:`boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig` for
Cortex-M0+ and on the Kconfig
:zephyr_file:`boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig` for
Cortex-M4
System Clock
============
The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for
the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the
system clock are provided in the SOC, depending on your system requirements.
Serial Port
===========
The PSoC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as
UART/SPI/I2C interfaces for serial communication. At the moment UART5 on SCB5
and UART6 on SCB6 are configured. SCB5 is connected to the onboard KitProg2's
USB-UART Bridge working as a serial console interface. SCB6 to P13_0, P13_1
pins on the J3 of the Arduino Uno R3 compatible PSoC6 I/O header for general
purposes.
OpenOCD Installation
====================
To get the OpenOCD package, it is required that you
1. Download the software ModusToolbox 3.1. path_to_url
2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox
export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts
3. Add the OpenOCD executable file's path to west flash/debug.
4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd
5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd
Programming and Debugging
*************************
The CY8CKIT-062-BLE includes an onboard programmer/debugger (KitProg2) with
mass storage programming to provide debugging, flash programming, and serial
communication over USB. There are also PSoC 6 program and debug headers J11
and J12 that can be used with Segger J-Link [default].
A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and
Cy_WDT_Disable().
#. Build the Zephyr kernel and the :ref:`hello_world` sample application:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: cy8ckit_062_ble/cy8c6347/m0
:goals: build
:compact:
#. Run your favorite terminal program to listen for output. Under Linux the
terminal should be :code:`/dev/ttyACM0`. For example:
.. code-block:: console
$ minicom -D /dev/ttyACM0 -o
The -o option tells minicom not to send the modem initialization
string. Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
#. To flash an image:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: cy8ckit_062_ble/cy8c6347/m0
:goals: flash
:compact:
You should see "Hello World! cy8ckit_062_ble" in your terminal.
Running on Dual Core
********************
#. Build the Zephyr kernel and the :zephyr:code-sample:`button` sample application:
.. zephyr-app-commands::
:zephyr-app: samples/basic/button
:board: cy8ckit_062_ble/cy8c6347/m4
:goals: build
:compact:
#. If you have a USB-Serial adapter, you can connect SBC[UART]-6 on Arduino
header. Schematic should be checked for connections. Run your favorite
terminal program again now listen for another output. Under Linux the
terminal should be :code:`/dev/ttyUSB0`. For example:
.. code-block:: console
$ minicom -D /dev/ttyUSB0 -o
The -o option tells minicom not to send the modem initialization
string. Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
#. To flash an image:
.. zephyr-app-commands::
:zephyr-app: samples/basic/button
:board: cy8ckit_062_ble/cy8c6347/m4
:goals: flash
:compact:
#. Configure Cortex-M0+ to enable Cortex-M4:
The last step flash the M4 image on the flash. However, Cortex-M0 by default
doesn't start the M4 and nothing will happen. To enable Cortex-M4 CPU,
repeat the steps on programming and debug and add the following parameter
when performing the build process.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: cy8ckit_062_ble/cy8c6347/m0
:goals: build flash
:gen-args: -DCONFIG_SOC_PSOC6_M0_ENABLES_M4=y
:compact:
Now you can press button SW-2 and see LED-9 blink at same time you have the
"Hello World! cy8ckit_062_ble" in the your terminal.
Board Revision
**************
The CY8CKIT-062-BLE KitProg2 shares connections with Arduino-R3 header. This
connections may not allow the correct use of shields. The default board
revision (0.0.0) allows use of default connections. The use of Arduino headers
are only possible after rework the board and using the revision 1.0.0.
#. Build the Zephyr kernel and the :ref:`hello_world` sample application for
board revision 1.0.0:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: cy8ckit_062_ble@1.0.0/cy8c6347/m0
:goals: build
:compact:
#. The differences from version 0.0.0 to 1.0.0:
+-------------+------------+------------+
| Connection | 0.0.0 | 1.0.0 |
+=============+============+============+
| CDC-COM RX | P5_0 | P9_0 |
+-------------+------------+------------+
| CDC-COM TX | P5_1 | P9_1 |
+-------------+------------+------------+
| R77 | X | |
+-------------+------------+------------+
| R78 | | X |
+-------------+------------+------------+
The P9 pins are available at J2. Those signals should be routed to J6.
J2-2 to J6-14
J2-4 to J6-13
The most complex part is short circuit pins 14 and 15 from U13. That connect
UART_RTS with UART_CTS from KitProg2.
References
**********
.. _PSoC 63 BLE MCU SoC Website:
path_to_url
.. _PSoC 63 BLE MCU Datasheet:
path_to_url
.. _PSoC 63 BLE MCU Architecture Reference Manual:
path_to_url
.. _PSoC 63 BLE MCU Register Reference Manual:
path_to_url
.. _CY8CKIT-062-BLE Website:
path_to_url
.. _CY8CKIT-062-BLE User Guide:
path_to_url
.. _CY8CKIT-062-BLE Schematics:
path_to_url
``` | /content/code_sandbox/boards/cypress/cy8ckit_062_ble/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,097 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 11)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 1, 12)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 11)>,
<NRF_PSEL(UART_RX, 1, 12)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 7)>,
<NRF_PSEL(TWIM_SCL, 0, 27)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 7)>,
<NRF_PSEL(TWIM_SCL, 0, 27)>;
low-power-enable;
};
};
i2c1_default: i2c1_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 4)>,
<NRF_PSEL(TWIM_SCL, 0, 5)>;
};
};
i2c1_sleep: i2c1_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 4)>,
<NRF_PSEL(TWIM_SCL, 0, 5)>;
low-power-enable;
};
};
pdm0_default: pdm0_default {
group1 {
psels = <NRF_PSEL(PDM_CLK, 1, 00)>,
<NRF_PSEL(PDM_DIN, 0, 16)>;
};
};
pdm0_sleep: pdm0_sleep {
group1 {
psels = <NRF_PSEL(PDM_CLK, 1, 00)>,
<NRF_PSEL(PDM_DIN, 0, 16)>;
low-power-enable;
};
};
pwm0_default: pwm0_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
nordic,invert;
};
};
pwm0_sleep: pwm0_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
low-power-enable;
};
};
spi2_default: spi2_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
<NRF_PSEL(SPIM_MOSI, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>;
};
};
spi2_sleep: spi2_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
<NRF_PSEL(SPIM_MOSI, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>;
low-power-enable;
};
};
spi3_default: spi3_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
<NRF_PSEL(SPIM_MOSI, 0, 20)>,
<NRF_PSEL(SPIM_MISO, 0, 24)>;
};
};
spi3_sleep: spi3_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
<NRF_PSEL(SPIM_MOSI, 0, 20)>,
<NRF_PSEL(SPIM_MISO, 0, 24)>;
low-power-enable;
};
};
qspi_default: qspi_default {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 21)>,
<NRF_PSEL(QSPI_IO0, 0, 20)>,
<NRF_PSEL(QSPI_IO1, 0, 24)>,
<NRF_PSEL(QSPI_IO2, 0, 22)>,
<NRF_PSEL(QSPI_IO3, 0, 23)>,
<NRF_PSEL(QSPI_CSN, 0, 25)>;
};
};
qspi_sleep: qspi_sleep {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 21)>,
<NRF_PSEL(QSPI_IO0, 0, 20)>,
<NRF_PSEL(QSPI_IO1, 0, 24)>,
<NRF_PSEL(QSPI_IO2, 0, 22)>,
<NRF_PSEL(QSPI_IO3, 0, 23)>,
<NRF_PSEL(QSPI_CSN, 0, 25)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,186 |
```unknown
/*
*
*/
#include <nordic/nrf52840_qiaa.dtsi>
#include "xiao_ble-pinctrl.dtsi"
#include "seeed_xiao_connector.dtsi"
/ {
chosen {
zephyr,console = &usb_cdc_acm_uart;
zephyr,shell-uart = &usb_cdc_acm_uart;
zephyr,uart-mcumgr = &usb_cdc_acm_uart;
zephyr,bt-mon-uart = &usb_cdc_acm_uart;
zephyr,bt-c2h-uart = &usb_cdc_acm_uart;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &code_partition;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
label = "Red LED";
};
led1: led_1 {
gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
label = "Green LED";
};
led2: led_2 {
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
label = "Blue LED";
};
};
pwmleds {
compatible = "pwm-leds";
pwm_led0: pwm_led_0 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
pwm-led0 = &pwm_led0;
bootloader-led0 = &led0;
mcuboot-led0 = &led0;
watchdog0 = &wdt0;
};
};
®0 {
status = "okay";
};
®1 {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&adc {
status = "okay";
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c1 {
compatible = "nordic,nrf-twi";
/* Cannot be used together with spi1. */
status = "okay";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
&spi2 {
compatible = "nordic,nrf-spi";
status = "okay";
pinctrl-0 = <&spi2_default>;
pinctrl-1 = <&spi2_sleep>;
pinctrl-names = "default", "sleep";
};
&qspi {
status = "okay";
pinctrl-0 = <&qspi_default>;
pinctrl-1 = <&qspi_sleep>;
pinctrl-names = "default", "sleep";
p25q16h: p25q16h@0 {
compatible = "nordic,qspi-nor";
reg = <0>;
sck-frequency = <104000000>;
quad-enable-requirements = "S2B1v1";
jedec-id = [85 60 15];
sfdp-bfp = [
e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 80 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 08 81
];
size = <16777216>;
has-dpd;
t-enter-dpd = <3000>;
t-exit-dpd = <8000>;
};
};
&ieee802154 {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
sd_partition: partition@0 {
label = "softdevice";
reg = <0x00000000 0x00027000>;
};
code_partition: partition@27000 {
label = "code_partition";
reg = <0x00027000 0x000c5000>;
};
/*
* The flash starting at 0x000ec000 and ending at
* 0x000f3fff is reserved for use by the application.
*
* Storage partition will be used by FCB/LittleFS/NVS
* if enabled.
*/
storage_partition: partition@ec000 {
label = "storage";
reg = <0x000ec000 0x00008000>;
};
boot_partition: partition@f4000 {
label = "adafruit_boot";
reg = <0x000f4000 0x0000c000>;
};
};
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
usb_cdc_acm_uart: cdc-acm-uart {
compatible = "zephyr,cdc-acm-uart";
};
};
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,322 |
```unknown
/*
*
*/
/dts-v1/;
#include "xiao_ble_common.dtsi"
/ {
model = "Seeed XIAO BLE";
compatible = "seeed,xiao-ble";
};
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```yaml
identifier: xiao_ble/nrf52840/sense
name: XIAO BLE Sense
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- ble
- counter
- gpio
- i2c
- i2s
- pwm
- spi
- usb_device
- watchdog
- netif:openthread
vendor: seeed
``` | /content/code_sandbox/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```cmake
board_runner_args(pyocd "--target=stm32wle5jcix")
board_runner_args(pyocd "--flash-opt=-O reset_type=hw")
board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset")
board_runner_args(jlink "--device=STM32WLE5JC" "--speed=4000" "--reset-after-load")
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(blackmagicprobe "--connect-rst")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake)
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 202 |
```unknown
# Enable UART driver
CONFIG_SERIAL=y
# Enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable regulator for the power-rails
CONFIG_REGULATOR=y
# Enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```yaml
identifier: lora_e5_dev_board
name: Seeedstudio LoRa-E5 Dev Board
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 256
supported:
- counter
- gpio
- i2c
- nvs
- spi
- uart
- watchdog
- lora
vendor: seeed studio
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```unknown
config BOARD_LORA_E5_DEV_BOARD
select SOC_STM32WLE5XX
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/Kconfig.lora_e5_dev_board | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```yaml
board:
name: lora_e5_dev_board
vendor: seeed
socs:
- name: stm32wle5xx
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```restructuredtext
.. _xiao_ble:
XIAO BLE (Sense)
################
Overview
********
The Seeed XIAO BLE (Sense) is a tiny (21 mm x 17.5 mm) Nordic Semiconductor
nRF52840 ARM Cortex-M4F development board with onboard LEDs, USB port, QSPI
flash, battery charger, and range of I/O broken out into 14 pins.
.. figure:: img/xiao_ble.jpg
:align: center
:alt: XIAO BLE
Hardware
********
- Nordic nRF52840 Cortex-M4F processor at 64MHz
- 2MB QSPI Flash
- RGB LED
- USB Type-C Connector, nRF52840 acting as USB device
- Battery charger BQ25101
- Reset button
- Bluetooth antenna
- LSM6DS3TR-C 6D IMU (3D accelerometer and 3D gyroscope) (XIAO BLE Sense only)
- PDM microphone (XIAO BLE Sense only)
Supported Features
==================
The xiao_ble board configuration supports the following hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| ADC | on-chip | adc |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+----------------------+
| FLASH | on-chip | flash, QSPI flash |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
| RADIO | on-chip | Bluetooth, |
| | | ieee802154 |
+-----------+------------+----------------------+
| RTC | on-chip | system clock |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| USB | on-chip | usb |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
Connections and IOs
===================
The `XIAO BLE wiki`_ has detailed information about the board including
`pinouts`_ and the `schematic`_.
LED
---
* LED1 (red) = P0.26
* LED2 (green) = P0.30
* LED3 (blue) = P0.06
Programming and Debugging
*************************
The XIAO BLE ships with the `Adafruit nRF52 Bootloader`_ which supports flashing
using `UF2`_. Doing so allows easy flashing of new images, but does not support
debugging the device. For debugging please use `External Debugger`_.
UF2 Flashing
============
To enter the bootloader, connect the USB port of the XIAO BLE to your host, and
double tap the reset botton to the left of the USB connector. A mass storage
device named `XIAO BLE` should appear on the host. Using the command line, or
your file manager copy the `zephyr/zephyr.uf2` file from your build to the base
of the `XIAO BLE` mass storage device. The XIAO BLE will automatically reset
and launch the newly flashed application.
External Debugger
=================
In order to support debugging the device, instead of using the bootloader, you
can use an :ref:`External Debug Probe <debug-probes>`. To flash and debug Zephyr
applications you need to use `Seeeduino XIAO Expansion Board`_ or solder an SWD
header onto the back side of the board.
For Segger J-Link debug probes, follow the instructions in the
:ref:`jlink-external-debug-probe` page to install and configure all the
necessary software.
Flashing
--------
Setup and connect a supported debug probe (JLink, instructions at :ref:`jlink-external-debug-probe` or
BlackMagic Probe). Then build and flash applications as
usual (see :ref:`build_an_application` and :ref:`application_run` for more
details).
Here is an example for the :ref:`hello_world` application.
First, run your favorite terminal program to listen for output.
.. code-block:: console
$ minicom -D <tty_device> -b 115200
Replace :code:`<tty_device>` with the port where the board XIAO BLE
can be found. For example, under Linux, :code:`/dev/ttyACM0`.
Then build and flash the application in the usual way. Just add
``CONFIG_BOOT_DELAY=5000`` to the configuration, so that USB CDC ACM is
initialized before any text is printed, as below:
.. tabs::
.. group-tab:: XIAO BLE
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: xiao_ble
:goals: build flash
:gen-args: -DCONFIG_BOOT_DELAY=5000
.. group-tab:: XIAO BLE Sense
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: xiao_ble/nrf52840/sense
:goals: build flash
:gen-args: -DCONFIG_BOOT_DELAY=5000
Debugging
---------
Refer to the :ref:`jlink-external-debug-probe` page to learn about debugging
boards with a Segger IC.
Debugging using a BlackMagic Probe is also supported.
Testing the LEDs in the XIAO BLE (Sense)
****************************************
There is a sample that allows to test that LEDs on the board are working
properly with Zephyr:
.. tabs::
.. group-tab:: XIAO BLE
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: xiao_ble
:goals: build flash
.. group-tab:: XIAO BLE Sense
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: xiao_ble/nrf52840/sense
:goals: build flash
You can build and flash the examples to make sure Zephyr is running correctly on
your board. The LED definitions can be found in
:zephyr_file:`boards/seeed/xiao_ble/xiao_ble_common.dtsi`.
Testing shell over USB in the XIAO BLE (Sense)
**********************************************
There is a sample that allows to test shell interface over USB CDC ACM interface
with Zephyr:
.. tabs::
.. group-tab:: XIAO BLE
.. zephyr-app-commands::
:zephyr-app: samples/subsys/shell/shell_module
:board: xiao_ble
:goals: build flash
.. group-tab:: XIAO BLE Sense
.. zephyr-app-commands::
:zephyr-app: samples/subsys/shell/shell_module
:board: xiao_ble/nrf52840/sense
:goals: build flash
References
**********
.. target-notes::
.. _XIAO BLE wiki: path_to_url
.. _pinouts: path_to_url#hardware-overview
.. _schematic: path_to_url#resources
.. _Seeeduino XIAO Expansion Board: path_to_url
.. _Adafruit nRF52 Bootloader: path_to_url
.. _UF2: path_to_url
``` | /content/code_sandbox/boards/seeed/xiao_ble/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,736 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32wlx.cfg]
reset_config srst_only
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <seeed_studio/lora-e5.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Seeed Studio LoRa-E5 Dev Board";
compatible = "seeed,lora-e5-dev-board";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds {
compatible = "gpio-leds";
red_led_1: led_0 {
gpios = <&gpiob 5 GPIO_ACTIVE_LOW>;
label = "User LED1";
/* the led can be disconnected, using J16 (D5) */
};
};
gpio_keys {
compatible = "gpio-keys";
boot_button: button_0 {
label = "SW1";
gpios = <&gpiob 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_0>;
};
user_button: button_1 {
label = "SW2";
gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
/* user_button can be disconnected, using J14 (D0) */
zephyr,code = <INPUT_KEY_1>;
};
};
aliases {
led0 = &red_led_1;
sw0 = &boot_button;
sw1 = &user_button;
lora0 = &lora;
watchdog0 = &iwdg;
};
pwr_3v3: pwr-3v3-ctrl {
/*
* PWR rail for SPI-flash, Temp-Sensor, RS-485 Transceiver,
* and for external devices(Grove, header).
* Requires closed J15 (D9)
*/
compatible = "regulator-fixed";
regulator-name = "pwr-3v3-ctrl";
enable-gpios = <&gpioa 9 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
status = "okay";
};
pwr_5v: pwr-5v-ctrl {
/*
* Available for external devices on header J2
* Requires closed J6 (D10)
*/
compatible = "regulator-fixed";
regulator-name = "pwr-5v-ctrl";
enable-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
status = "okay";
};
};
stm32_lp_tick_source: &lptim1 {
status = "okay";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
};
&clk_lsi {
status = "okay";
};
&clk_msi {
status = "okay";
msi-range = <11>;
};
&rcc {
clocks = <&clk_msi>;
clock-frequency = <DT_FREQ_M(48)>;
cpu1-prescaler = <1>;
ahb3-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pc1 &lpuart1_rx_pc0>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
/* PB4 can select RS-485 TX, when J17 (A4) is closed */
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb15 &i2c2_sda_pa15>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
/* LM75ADP temperature sensor on addr 0x48 */
};
/* Attention!: the spi-sck pin is in conflict with the boot_button on pb13 */
&spi2 {
pinctrl-0 = <&spi2_nss_pb9 &spi2_sck_pb13
&spi2_miso_pb14 &spi2_mosi_pa10>;
pinctrl-names = "default";
status = "okay";
/* unpopulated footprint for spi flash */
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&iwdg {
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc_in2_pb3>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&aes {
status = "okay";
};
/* connectors: */
grove_serial: &usart1 {};
grove_i2c: &i2c2 {};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(32)>;
read-only;
};
slot0_partition: partition@8000 {
label = "image-0";
reg = <0x00008000 DT_SIZE_K(104)>;
};
slot1_partition: partition@22000 {
label = "image-1";
reg = <0x00022000 DT_SIZE_K(104)>;
};
/* 16KB (8x2kB pages) of storage at the end of the flash */
storage_partition: partition@3c000 {
label = "storage";
reg = <0x0003c000 DT_SIZE_K(16)>;
};
};
};
/*
* Other Pins:
* Not assigned: None
* Debug: PA13(swdio), PA14(swclk)
*/
``` | /content/code_sandbox/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,451 |
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