text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52832_qfaa.dtsi>
#include "feather_connector.dtsi"
#include "nrf52_adafruit_feather-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "nRF52 Adafruit Feather";
compatible = "adafruit,nrf52_adafruit_feather";
aliases {
pwm-led0 = &red_pwm_led;
};
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
led1 = &led1;
sw0 = &button0;
watchdog0 = &wdt0;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 17 0>;
label = "Red LED";
};
led1: led_1 {
gpios = <&gpio0 19 0>;
label = "Blue LED";
};
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: pwm_led_0 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
blue_pwm_led: pwm_led_1 {
pwms = <&pwm0 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 20 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Button";
zephyr,code = <INPUT_KEY_0>;
};
};
};
® {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uart";
current-speed = <115200>;
status = "okay";
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c0 {
compatible = "nordic,nrf-twi";
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0xc000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x32000>;
};
slot1_partition: partition@3e000 {
label = "image-1";
reg = <0x0003E000 0x32000>;
};
scratch_partition: partition@70000 {
label = "image-scratch";
reg = <0x00070000 0xa000>;
};
storage_partition: partition@7a000 {
label = "storage";
reg = <0x0007a000 0x00006000>;
};
};
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 945 |
```unknown
# nRF52 ADAFRUIT FEATHER board configuration
config BOARD_NRF52_ADAFRUIT_FEATHER
select SOC_NRF52832_QFAA
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/Kconfig.nrf52_adafruit_feather | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```yaml
board:
name: nrf52_adafruit_feather
vendor: adafruit
socs:
- name: nrf52832
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
# nRF52 ADAFRUIT FEATHER board configuration
if BOARD_NRF52_ADAFRUIT_FEATHER
config BT_CTLR
default BT
endif # BOARD_NRF52_ADAFRUIT_FEATHER
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```objective-c
/*
*
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
/* External edge connector pin mappings to nRF52 GPIO pin numbers.
* More information:
* path_to_url#device-pinout
* path_to_url
*/
#define EXT_A0_GPIO_PIN 2 /* P2, Analog in */
#define EXT_A1_GPIO_PIN 3 /* P3, Analog in */
#define EXT_A2_GPIO_PIN 4 /* P4, Analog in */
#define EXT_A3_GPIO_PIN 5 /* P5, Analog in */
#define EXT_A4_GPIO_PIN 28 /* P28, Analog in */
#define EXT_A5_GPIO_PIN 29 /* P29, Analog in */
#define EXT_A6_GPIO_PIN 30 /* P30, Analog in */
#define EXT_A7_GPIO_PIN 31 /* P31, Analog in */
#define EXT_SCK_GPIO_PIN 12 /* P12 */
#define EXT_MOSI_GPIO_PIN 13 /* P13 */
#define EXT_MISO_GPIO_PIN 14 /* P14 */
#define EXT_RXD_GPIO_PIN 8 /* P8 */
#define EXT_TXD_GPIO_PIN 6 /* P6 */
#define EXT_P16_GPIO_PIN 16 /* P16 */
#define EXT_P15_GPIO_PIN 15 /* P15 */
#define EXT_P7_GPIO_PIN 7 /* P7 */
#define EXT_P11_GPIO_PIN 11 /* P11 */
#define EXT_P27_GPIO_PIN 27 /* P27 */
#define EXT_SCL_GPIO_PIN 26 /* P26 */
#define EXT_SDA_GPIO_PIN 25 /* P25 */
#endif /* __INC_BOARD_H */
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/board.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 360 |
```yaml
identifier: nrf52_adafruit_feather
name: nRF52 Adafruit Feather
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 512
supported:
- feather_serial
- feather_i2c
vendor: adafruit
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```unknown
/*
*
*/
/ {
feather_header: connector {
compatible = "adafruit-feather-header";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 2 0>, /* A0 */
<1 0 &gpio0 3 0>, /* A1 */
<2 0 &gpio0 4 0>, /* A2 */
<3 0 &gpio0 5 0>, /* A3 */
<4 0 &gpio0 28 0>, /* A4 */
<5 0 &gpio0 29 0>, /* A5 */
<6 0 &gpio0 12 0>, /* SCK */
<7 0 &gpio0 13 0>, /* MOSI */
<8 0 &gpio0 14 0>, /* MISO */
<9 0 &gpio0 8 0>, /* TXD */
<10 0 &gpio0 6 0>, /* RXD */
<11 0 &gpio0 20 0>, /* PIN_DFU */
<12 0 &gpio0 25 0>, /* SDA */
<13 0 &gpio0 26 0>, /* SCL */
<14 0 &gpio0 27 0>, /* P0.27 */
<15 0 &gpio0 30 0>, /* A6 */
<16 0 &gpio0 31 0>, /* A7 (VBAT ADC) */
<17 0 &gpio0 11 0>, /* P0.11 */
<18 0 &gpio0 7 0>, /* P0.07 */
<19 0 &gpio0 15 0>, /* P0.15 */
<20 0 &gpio0 16 0>; /* P0.16 */
};
};
feather_serial: &uart0 {};
feather_i2c: &i2c0 {};
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/feather_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 483 |
```restructuredtext
.. _boards-qorvo:
Qorvo, Inc.
###########
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/qorvo/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```restructuredtext
.. _nrf52_adafruit_feather:
nRF52 Adafruit Feather
######################
Overview
********
The nRF52 Adafruit Bluefruit Feather hardware provides
support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and
the following devices:
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`RTC (nRF RTC System Clock)`
* UART
* GPIO
* FLASH
* RADIO (Bluetooth Low Energy)
* Segger RTT (RTT Console)
.. figure:: img/nrf52_adafruit_feather.jpg
:align: center
:alt: nRF52 Adafruit Feather Board
nRF52 Adafruit Feather Board (Credit: Adafruit)
More information about the board and its features can be found at the
`Adafruit Feather nRF52 Bluefruit Learning Guide`_. The `Nordic Semiconductor Infocenter`_
contains the processor's information and the datasheet.
Hardware
********
- nRF52832 ARM Cortex-M4F processor at 64 MHz
- 32.768 kHz crystal oscillator
- 512 KiB flash memory and 64 KiB of SRAM
- Battery connector and charger for 3.7 V lithium polymer batteries
- Charging indicator LED
- 2 User LEDs
- Reset button
- SWD connector
- USB serial converter
Supported Features
==================
The nRF52 Adafruit Feather board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| NVIC | on-chip | nested vectored |
| | | interrupt controller |
+-----------+------------+----------------------+
| RTC | on-chip | system clock |
+-----------+------------+----------------------+
| UART | on-chip | serial port |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
| RADIO | on-chip | Bluetooth |
+-----------+------------+----------------------+
| RTT | on-chip | console |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
Connections and IOs
===================
The `Adafruit Feather nRF52 Bluefruit Learning Guide`_ has detailed
information about the board including `pinouts`_ and the `schematic`_.
LED
---
* LED0 (red) = P0.17
* LED1 (blue) = P0.19
Push buttons
------------
* DFU = SW0 = P0.20
* RESET = SW1 = P0.21/reset
Programming and Debugging
*************************
The ``nrf52_adafruit_feather`` board is available in two different versions:
- `Adafruit Feather nRF52 Pro with myNewt Bootloader`_
This board version is the recommended one to use. It has the SWD header
already populated and comes with the Mynewt serial bootloader installed by
default.
- `Adafruit Feather nRF52 Bluefruit LE`_
This board is identical to the board above, but the SWD header is not
populated and ships with an Arduino friendly bootloader. To be able to work
with this version a 2*5pin 0.5" SWD header (e.g. `Adafruit SWD connector`_)
needs to be soldered.
Applications for the ``nrf52_adafruit_feather`` board configuration can be
built, flashed, and debugged in the usual way. See :ref:`build_an_application`
and :ref:`application_run` for more details on building and running.
Flashing
========
Flashing Zephyr onto the ``nrf52_adafruit_feather`` board requires an external
J-Link programmer. The programmer is attached to the X1 SWD header.
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`. Then build and flash
applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Here is an example for the :ref:`hello_world` application.
#. Build the Zephyr kernel and the :ref:`hello_world` sample application:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nrf52_adafruit_feather
:goals: build
:compact:
#. Connect the Adafruit nRF52 Feather to your host computer using USB
#. Run your favorite terminal program to listen for output.
.. code-block:: console
$ minicom -D <tty_device> -b 115200
Replace :code:`<tty_device>` with the port where the nRF52 Adafruit Feather
board can be found. For example, under Linux, :code:`/dev/ttyUSB0`.
#. Flash the image:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nrf52_adafruit_feather
:goals: flash
:compact:
You should see "Hello World! nrf52_adafruit_feather" in your terminal.
Debugging
=========
The ``nrf52_adafruit_feather`` board does not have an on-board J-Link debug IC
as some nRF5x development boards, however, instructions from the
:ref:`nordic_segger` page also apply to this board, with the additional step
of connecting an external debugger.
Testing the LEDs and buttons on the nRF52 Adafruit Feather
**********************************************************
There are several samples that allow you to test that the buttons (switches) and LEDs on
the board are working properly with Zephyr:
- :zephyr:code-sample:`blinky`
- :zephyr:code-sample:`button`
- :zephyr:code-sample:`fade-led`
- :zephyr:code-sample:`pwm-blinky`
- :zephyr:code-sample:`multi-thread-blinky`
You can build and flash the examples to make sure Zephyr is running correctly on
your board. The button and LED definitions can be found in
:zephyr_file:`boards/adafruit/nrf52_adafruit_feather/board.h`.
References
**********
.. target-notes::
.. _Adafruit Feather nRF52 Bluefruit Learning Guide: path_to_url
.. _schematic: path_to_url
.. _pinouts: path_to_url
.. _Nordic Semiconductor Infocenter: path_to_url
.. _J-Link Software and documentation pack: path_to_url
.. _Adafruit Feather nRF52 Bluefruit LE: path_to_url
.. _Adafruit Feather nRF52 Pro with myNewt Bootloader: path_to_url
.. _Adafruit SWD connector: path_to_url
``` | /content/code_sandbox/boards/adafruit/nrf52_adafruit_feather/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,524 |
```cmake
board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000" "--reset-after-load")
board_runner_args(pyocd "--target=nrf52832")
set(OPENOCD_NRF5_SUBFAMILY "nrf52")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake)
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52832_qfaa.dtsi>
#include "decawave_dwm1001_dev-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Decawave DWM1001-DEV";
compatible = "decawave,dwm1001";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
led0_red: led_0 {
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
label = "Red LED 0";
};
led1_green: led_1 {
gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
label = "Green LED 1";
};
led2_red: led_2 {
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
label = "Red LED 2";
};
led3_blue: led_3 {
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
label = "Blue LED 3";
};
};
pwmleds {
compatible = "pwm-leds";
pwm_led0_red: pwm_led_0 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "Red PWM LED";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button switch 0";
zephyr,code = <INPUT_KEY_0>;
};
};
/* These aliases are provided for compatibility with samples */
aliases {
sw0 = &button0;
led0 = &led0_red;
led1 = &led1_green;
led2 = &led2_red;
led3 = &led3_blue;
led0-red = &led0_red;
led1-green = &led1_green;
led2-red = &led2_red;
led3-blue = &led3_blue;
pwm-led0 = &pwm_led0_red;
watchdog0 = &wdt0;
accel0 = &lis2dh12;
};
};
® {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&adc {
status = "okay";
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&uart0 {
status = "okay";
compatible = "nordic,nrf-uart";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c0 {
compatible = "nordic,nrf-twim";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
lis2dh12: lis2dh12@19 {
compatible = "st,lis2dh12", "st,lis2dh";
reg = <0x19>;
irq-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
};
};
&spi1 {
compatible = "nordic,nrf-spi";
status = "okay";
cs-gpios = <&gpio0 3 0>;
pinctrl-0 = <&spi1_default>;
pinctrl-1 = <&spi1_sleep>;
pinctrl-names = "default", "sleep";
};
&spi2 {
compatible = "nordic,nrf-spi";
status = "okay";
cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&spi2_default>;
pinctrl-1 = <&spi2_sleep>;
pinctrl-names = "default", "sleep";
ieee802154: dw1000@0 {
compatible = "decawave,dw1000";
spi-max-frequency = <8000000>;
int-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; /* P0.19 */
reset-gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; /* P0.24 */
status = "okay";
reg = <0>;
};
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0xc000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x32000>;
};
slot1_partition: partition@3e000 {
label = "image-1";
reg = <0x0003E000 0x32000>;
};
scratch_partition: partition@70000 {
label = "image-scratch";
reg = <0x00070000 0xa000>;
};
storage_partition: partition@7a000 {
label = "storage";
reg = <0x0007a000 0x00006000>;
};
};
};
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,417 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
board:
name: decawave_dwm1001_dev
vendor: qorvo
socs:
- name: nrf52832
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
# DecaWave DWM1001 board configuration
if BOARD_DECAWAVE_DWM1001_DEV
config BT_CTLR
default BT
config I2C
default SENSOR
config SPI
default y
depends on IEEE802154
endif # BOARD_DECAWAVE_DWM1001_DEV
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_RTT_CONSOLE=y
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```unknown
# DecaWave DWM1001 board configuration
config BOARD_DECAWAVE_DWM1001_DEV
select SOC_NRF52832_QFAA
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/Kconfig.decawave_dwm1001_dev | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 5)>,
<NRF_PSEL(UART_RX, 0, 11)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 5)>,
<NRF_PSEL(UART_RX, 0, 11)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 29)>,
<NRF_PSEL(TWIM_SCL, 0, 28)>;
bias-pull-up;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 29)>,
<NRF_PSEL(TWIM_SCL, 0, 28)>;
low-power-enable;
};
};
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 4)>,
<NRF_PSEL(SPIM_MOSI, 0, 6)>,
<NRF_PSEL(SPIM_MISO, 0, 7)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 4)>,
<NRF_PSEL(SPIM_MOSI, 0, 6)>,
<NRF_PSEL(SPIM_MISO, 0, 7)>;
low-power-enable;
};
};
spi2_default: spi2_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
<NRF_PSEL(SPIM_MOSI, 0, 20)>,
<NRF_PSEL(SPIM_MISO, 0, 18)>;
};
};
spi2_sleep: spi2_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
<NRF_PSEL(SPIM_MOSI, 0, 20)>,
<NRF_PSEL(SPIM_MISO, 0, 18)>;
low-power-enable;
};
};
pwm0_default: pwm0_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 22)>;
nordic,invert;
};
};
pwm0_sleep: pwm0_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 22)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 666 |
```yaml
identifier: decawave_dwm1001_dev
name: Decawave-DWM1001-DEV
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 512
supported:
- spi
- i2c
vendor: decawave
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```restructuredtext
.. _boards-ebyte:
Chengdu Ebyte Electronic Technology
###################################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/ebyte/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```cmake
board_runner_args(jlink "--device=nrf52" "--speed=4000")
board_runner_args(pyocd "--target=nrf52" "--frequency=4000000")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake)
``` | /content/code_sandbox/boards/ebyte/e73_tbb/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
# Enable GPIO
CONFIG_GPIO=y
# Enable uart driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```restructuredtext
.. _decawave_dwm1001_dev:
Decawave DWM1001
#################
Overview
********
The DWM1001 development board includes the DWM1001 module, battery
connector and charging circuit, LEDs, buttons, Raspberry-Pi and USB
connector. In addition, the board comes with J-Link OB adding
debugging and Virtual COM Port capabilities.
See `Qorvo (Decawave) DWM1001-DEV website`_ for more information about the development
board, `Qorvo (Decawave) DWM1001 website`_ about the board itself, and `nRF52832 website`_ for the
official reference on the IC itself.
Programming and Debugging
*************************
Applications for the ``decawave_dwm1001_dev`` board configuration can be built,
flashed, and debugged in the usual way. See :ref:`build_an_application` and
:ref:`application_run` for more details on building and running.
Flashing
========
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`. Then build and flash
applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Here is an example for the :ref:`hello_world` application.
First, run your favorite terminal program to listen for output.
.. code-block:: console
$ minicom -D <tty_device> -b 115200
Replace :code:`<tty_device>` with the port where the board nRF52 DK
can be found. For example, under Linux, :code:`/dev/ttyACM0`.
Then build and flash the application in the usual way.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: decawave_dwm1001_dev
:goals: build flash
References
**********
.. target-notes::
.. _nRF52832 website: path_to_url
.. _Qorvo (Decawave) DWM1001 website: path_to_url
.. _Qorvo (Decawave) DWM1001-DEV website: path_to_url
``` | /content/code_sandbox/boards/qorvo/decawave_dwm1001_dev/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 487 |
```yaml
identifier: ebyte_e73_tbb/nrf52832
name: EBYTE-E73-TBB-NRF52832
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 512
supported:
- adc
- gpio
- counter
- nvs
- i2c
- pwm
- spi
- watchdog
``` | /content/code_sandbox/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```yaml
board:
name: ebyte_e73_tbb
vendor: ebyte
socs:
- name: nrf52832
``` | /content/code_sandbox/boards/ebyte/e73_tbb/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
low-power-enable;
};
};
pwm0_default: pwm0_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
nordic,invert;
};
};
pwm0_sleep: pwm0_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 287 |
```unknown
# EBYTE E73-TBB NRF52832 board configuration
if BOARD_EBYTE_E73_TBB_NRF52832
config BT_CTLR
default BT
endif # BOARD_EBYTE_E73_TBB_NRF52832
``` | /content/code_sandbox/boards/ebyte/e73_tbb/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
# EBYTE-TBB board configuration
config BOARD_EBYTE_E73_TBB
select SOC_NRF52832_QFAA
``` | /content/code_sandbox/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52832_qfaa.dtsi>
#include "ebyte_e73_tbb_nrf52832-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "EBYTE E73-TBB NRF52832";
compatible = "ebyte,e73-tbb-nrf52832";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
label = "Red LED1";
};
led1: led_1 {
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
label = "Red LED2";
};
};
pwmleds {
compatible = "pwm-leds";
pwm_led0: pwm_led_0 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button SW1";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button SW2";
zephyr,code = <INPUT_KEY_1>;
};
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
led1 = &led1;
pwm-led0 = &pwm_led0;
sw0 = &button0;
sw1 = &button1;
bootloader-led0 = &led0;
watchdog0 = &wdt0;
};
};
&adc {
status = "okay";
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&uart0 {
status = "okay";
compatible = "nordic,nrf-uarte";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0xc000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x32000>;
};
slot1_partition: partition@3e000 {
label = "image-1";
reg = <0x0003E000 0x32000>;
};
scratch_partition: partition@70000 {
label = "image-scratch";
reg = <0x00070000 0xa000>;
};
storage_partition: partition@7a000 {
label = "storage";
reg = <0x0007a000 0x00006000>;
};
};
};
``` | /content/code_sandbox/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 913 |
```restructuredtext
.. _boards-openisa:
OpenISA
#######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/openisa/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```cmake
set(OPENOCD_USE_LOAD_IMAGE NO)
if(CONFIG_SOC_OPENISA_RV32M1_RI5CY)
board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_ri5cy.cfg")
elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY)
board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_zero_riscy.cfg")
endif()
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```unknown
/*
*/
/dts-v1/;
#include "openisa/rv32m1_zero_riscy.dtsi"
#include "rv32m1_vega_openisa_rv32m1.dtsi"
/ {
model = "OpenISA RV32M1 Vega Zero RISCY";
compatible = "openisa,rv32m1";
chosen {
zephyr,sram = &m0_tcm;
zephyr,flash = &m0_flash;
zephyr,console = &lpuart0;
zephyr,uart-pipe = &lpuart0;
zephyr,code-partition = &zero_riscy_code_partition;
};
};
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```unknown
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_MULTI_LEVEL_INTERRUPTS=y
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```restructuredtext
.. _ebyte_e73_tbb_nrf52832:
EBYTE E73-TBB
#############
Overview
********
The EBYTE E73-TBB hardware provides
support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and
the following devices:
* :abbr:`ADC (Analog to Digital Converter)`
* CLOCK
* FLASH
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`I2C (Inter-Integrated Circuit)`
* :abbr:`MPU (Memory Protection Unit)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`PWM (Pulse Width Modulation)`
* RADIO (Bluetooth Low Energy)
* :abbr:`RTC (nRF RTC System Clock)`
* Segger RTT (RTT Console)
* :abbr:`SPI (Serial Peripheral Interface)`
* :abbr:`UART (Universal asynchronous receiver-transmitter)`
* :abbr:`WDT (Watchdog Timer)`
.. figure:: img/ebyte_e73_tbb_nrf52832.jpg
:align: center
:alt: EBYTE E73-TBB
EBYTE E73-TBB (Credit: EBYTE)
More information about the board can be found at the
`E73-TBB website`_. The `Nordic Semiconductor Infocenter`_
contains the processor's information and the datasheet.
Hardware
********
E73-TBB has two external oscillators. The frequency of
the slow clock is 32.768 kHz. The frequency of the main clock
is 32 MHz. Additionally the board features CH340 USB-UART converter.
It is possible to connect external BT antenna using U.FL socket
and solder NFC antenna using NFC_ANT connector.
Supported Features
==================
The ebyte_e73_tbb/nrf52832 board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| ADC | on-chip | adc |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+----------------------+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
| RADIO | on-chip | Bluetooth |
+-----------+------------+----------------------+
| RTC | on-chip | system clock |
+-----------+------------+----------------------+
| RTT | Segger | console |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
Other hardware features are not supported by the Zephyr kernel.
See `E73-TBB website`_ and `Nordic Semiconductor Infocenter`_
for a complete list of nRF52832 hardware features.
Connections and IOs
===================
LED
---
* LED0 (red) = P0.17
* LED1 (red) = P0.18
Push buttons
------------
* BUTTON0 = SW1 = P0.14
* BUTTON1 = SW2 = P0.13
External Connectors
-------------------
P1 Header
+-------+--------------+
| PIN # | Signal Name |
+=======+==============+
| 1 | GND |
+-------+--------------+
| 2 | 3.3V |
+-------+--------------+
| 3 | P0.04 |
+-------+--------------+
| 4 | P0.03 |
+-------+--------------+
| 5 | P0.02 |
+-------+--------------+
| 6 | P0.31 |
+-------+--------------+
| 7 | P0.30 |
+-------+--------------+
| 8 | P0.29 |
+-------+--------------+
| 9 | P0.28 |
+-------+--------------+
| 10 | P0.27 |
+-------+--------------+
| 11 | P0.26 |
+-------+--------------+
| 12 | P0.25 |
+-------+--------------+
P2 Header
+-------+--------------+
| PIN # | Signal Name |
+=======+==============+
| 1 | P0.24 |
+-------+--------------+
| 2 | P0.23 |
+-------+--------------+
| 3 | P0.22 |
+-------+--------------+
| 4 | SWDIO |
+-------+--------------+
| 5 | SWDCLK |
+-------+--------------+
| 6 | P0.21/RST |
+-------+--------------+
| 7 | P0.20 |
+-------+--------------+
| 8 | P0.19 |
+-------+--------------+
| 9 | P0.16 |
+-------+--------------+
| 10 | P0.15 |
+-------+--------------+
| 11 | P0.12 |
+-------+--------------+
| 12 | P0.11 |
+-------+--------------+
NFC_ANT
+-------+--------------+
| PIN # | Signal Name |
+=======+==============+
| 1 | P0.10 |
+-------+--------------+
| 2 | P0.09 |
+-------+--------------+
Programming and Debugging
*************************
Flashing
========
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software.
To flash the board connect pins: SWDIO, SWDCLK, RST, GND from E73-TBB
to corresponding pins on your J-Link device, then build and flash the application in the usual way.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: ebyte_e73_tbb/nrf52832
:goals: build flash
Debugging
=========
Refer to the :ref:`nordic_segger` page to learn about debugging Nordic chips with a
Segger IC.
Testing the LEDs and buttons in the E73-TBB
*******************************************
There are 2 samples that allow you to test that the buttons (switches) and LEDs on
the board are working properly with Zephyr:
.. code-block:: console
:zephyr:code-sample:`blinky`
:zephyr:code-sample:`button`
You can build and flash the examples to make sure Zephyr is running correctly on
your board. The button and LED definitions can be found in
:zephyr_file:`boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts`.
References
**********
.. target-notes::
.. _E73-TBB website: path_to_url
.. _Nordic Semiconductor Infocenter: path_to_url
``` | /content/code_sandbox/boards/ebyte/e73_tbb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,623 |
```unknown
/*
*/
#include <zephyr/dt-bindings/pinctrl/rv32m1-pinctrl.h>
&pinctrl {
lpuart0_default: lpuart0_default {
group0 {
pinmux = <RV32M1_MUX('C', 7, 3)>,
<RV32M1_MUX('C', 8, 3)>;
slew-rate = "slow";
};
};
lpuart1_default: lpuart1_default {
group0 {
pinmux = <RV32M1_MUX('C', 29, 2)>,
<RV32M1_MUX('C', 30, 2)>;
slew-rate = "slow";
};
};
lpi2c0_default: lpi2c0_default {
group0 {
pinmux = <RV32M1_MUX('C', 9, 4)>,
<RV32M1_MUX('C', 10, 4)>;
slew-rate = "slow";
};
};
lpi2c3_default: lpi2c3_default {
group0 {
pinmux = <RV32M1_MUX('E', 29, 3)>,
<RV32M1_MUX('E', 30, 3)>;
slew-rate = "slow";
};
};
lpspi0_default: lpspi0_default {
group0 {
pinmux = <RV32M1_MUX('B', 4, 2)>,
<RV32M1_MUX('B', 5, 2)>,
<RV32M1_MUX('B', 6, 2)>,
<RV32M1_MUX('B', 7, 2)>;
slew-rate = "slow";
};
};
lpspi1_default: lpspi1_default {
group0 {
pinmux = <RV32M1_MUX('B', 20, 2)>,
<RV32M1_MUX('B', 21, 2)>,
<RV32M1_MUX('B', 22, 2)>,
<RV32M1_MUX('B', 24, 2)>;
slew-rate = "slow";
};
};
tpm2_default: tpm2_default {
group0 {
pinmux = <RV32M1_MUX('A', 22, 6)>,
<RV32M1_MUX('A', 23, 6)>,
<RV32M1_MUX('A', 24, 6)>;
slew-rate = "slow";
};
};
};
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 586 |
```yaml
identifier: rv32m1_vega/openisa_rv32m1/ri5cy
name: RV32M1-VEGA (RI5CY)
type: mcu
arch: riscv
toolchain:
- cross-compile
- zephyr
supported:
- arduino_gpio
- arduino_i2c
- arduino_spi
- i2c
- pwm
- spi
vendor: openisa
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```yaml
identifier: rv32m1_vega/openisa_rv32m1/zero_riscy
name: RV32M1-VEGA (ZERO-RISCY)
type: mcu
arch: riscv
toolchain:
- cross-compile
- zephyr
supported:
- arduino_gpio
- arduino_i2c
- i2c
- pwm
vendor: openisa
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```yaml
board:
name: rv32m1_vega
vendor: openisa
socs:
- name: openisa_rv32m1
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
config BOARD_RV32M1_VEGA
select SOC_OPENISA_RV32M1_RI5CY if BOARD_RV32M1_VEGA_OPENISA_RV32M1_RI5CY
select SOC_OPENISA_RV32M1_ZERO_RISCY if BOARD_RV32M1_VEGA_OPENISA_RV32M1_ZERO_RISCY
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/Kconfig.rv32m1_vega | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```unknown
/*
*/
/dts-v1/;
#include "openisa/rv32m1_ri5cy.dtsi"
#include "rv32m1_vega_openisa_rv32m1.dtsi"
/ {
model = "OpenISA RV32M1 Vega RI5CY";
compatible = "openisa,rv32m1";
chosen {
zephyr,sram = &m4_dtcm;
zephyr,flash = &m4_flash;
zephyr,console = &lpuart0;
zephyr,shell-uart = &lpuart0;
zephyr,uart-pipe = &lpuart0;
zephyr,code-partition = &slot0_partition;
zephyr,bt-hci = &bt_hci_controller;
};
};
&bt_hci_controller {
status = "okay";
};
&m4_flash {
/*
* For more information, see:
* path_to_url
*/
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
slot0_partition: partition@0 {
label = "image-0";
reg = <0x00000000 0x00069000>;
};
slot1_partition: partition@69000 {
label = "image-1";
reg = <0x00069000 0x00069000>;
};
scratch_partition: partition@d2000 {
label = "image-scratch";
reg = <0x000d2000 0x0001e000>;
};
storage_partition: partition@f0000 {
label = "storage";
reg = <0x000f0000 0x00004000>;
};
boot_partition: partition@f4000 {
label = "mcuboot";
reg = <0x000f4000 0x0000C000>;
};
};
};
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 434 |
```unknown
if BOARD_RV32M1_VEGA
if BT
config BT_CTLR
default y
#TODO: Resolve the complete non-BLE support for crypto CAU3 firmware/driver
#config HAS_RV32M1_CAU3
# bool
# default y if BT_CTLR_CRYPTO && !BT_CTLR_LE_ENC_SUPPORT
config HAS_RV32M1_CAU3_BLE
bool
default y if BT_CTLR_CRYPTO && \
(BT_CTLR_LE_ENC_SUPPORT || BT_CTLR_PRIVACY_SUPPORT)
config RV32M1_INTMUX_CHANNEL_2
default n
config RV32M1_INTMUX_CHANNEL_3
default n
endif # BT
endif # BOARD_RV32M1_VEGA
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```unknown
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_MULTI_LEVEL_INTERRUPTS=y
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
/*
*/
#include "rv32m1_vega_openisa_rv32m1-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
led3 = &sts_led;
pwm-led0 = &blue_pwm_led;
pwm-led1 = &green_pwm_led;
pwm-led2 = &red_pwm_led;
blue-pwm-led = &blue_pwm_led;
green-pwm-led = &green_pwm_led;
red-pwm-led = &red_pwm_led;
sw0 = &user_button_2;
sw1 = &user_button_3;
sw2 = &user_button_4;
sw3 = &user_button_5;
magn0 = &fxos8700;
accel0 = &fxos8700;
};
leds {
compatible = "gpio-leds";
blue_led: led_0 {
gpios = <&gpioa 22 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
green_led: led_1 {
gpios = <&gpioa 23 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
red_led: led_2 {
gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
sts_led: led_3 {
gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>;
label = "User LD4";
};
};
pwmleds {
compatible = "pwm-leds";
blue_pwm_led: pwm_led_0 {
pwms = <&tpm2 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "User PWM LD1";
};
green_pwm_led: pwm_led_1 {
pwms = <&tpm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "User PWM LD2";
};
red_pwm_led: pwm_led_2 {
pwms = <&tpm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "User PWM LD3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpioe 8 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
user_button_4: button_2 {
label = "User SW4";
gpios = <&gpioe 9 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_2>;
};
user_button_5: button_3 {
label = "User SW5";
gpios = <&gpioe 12 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_3>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioc 11 0>, /* A0 */
<1 0 &gpioc 12 0>, /* A1 */
<2 0 &gpiob 9 0>, /* A2 */
<3 0 &gpioe 4 0>, /* A3 */
<4 0 &gpioe 10 0>, /* A4 */
<5 0 &gpioe 11 0>, /* A5 */
<6 0 &gpioa 25 0>, /* D0 */
<7 0 &gpioa 26 0>, /* D1 */
<8 0 &gpioa 27 0>, /* D2 */
<9 0 &gpiob 13 0>, /* D3 */
<10 0 &gpiob 14 0>, /* D4 */
<11 0 &gpioa 30 0>, /* D5 */
<12 0 &gpioa 31 0>, /* D6 */
<13 0 &gpiob 1 0>, /* D7 */
<14 0 &gpiob 2 0>, /* D8 */
<15 0 &gpiob 3 0>, /* D9 */
<16 0 &gpiob 6 0>, /* D10 */
<17 0 &gpiob 5 0>, /* D11 */
<18 0 &gpiob 7 0>, /* D12 */
<19 0 &gpiob 4 0>, /* D13 */
<20 0 &gpioc 9 0>, /* D14 */
<21 0 &gpioc 10 0>; /* D15 */
};
};
arduino_serial: &lpuart1 {
pinctrl-0 = <&lpuart1_default>;
pinctrl-names = "default";
};
&lpuart0 {
current-speed = <115200>;
status = "okay";
pinctrl-0 = <&lpuart0_default>;
pinctrl-names = "default";
};
arduino_i2c: &lpi2c0 {
status = "okay";
pinctrl-0 = <&lpi2c0_default>;
pinctrl-names = "default";
};
&lpi2c3 {
status = "okay";
pinctrl-0 = <&lpi2c3_default>;
pinctrl-names = "default";
fxos8700: fxos8700@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
reset-gpios = <&gpioe 27 GPIO_ACTIVE_HIGH>;
int1-gpios = <&gpioe 1 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpioe 22 GPIO_ACTIVE_LOW>;
};
};
arduino_spi: &lpspi0 {
status = "okay";
pinctrl-0 = <&lpspi0_default>;
pinctrl-names = "default";
};
&lpspi1 {
status = "okay";
cs-gpios = <&gpiob 22 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&lpspi1_default>;
pinctrl-names = "default";
mx25r32: mx25r3235f@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
jedec-id = [c2 28 16];
size = <33554432>;
};
};
&tpm2 {
status = "okay";
pinctrl-0 = <&tpm2_default>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,618 |
```ini
set _WORKAREASIZE 0x2000
adapter speed 1000
interface jlink
transport select jtag
set _WORKAREASIZE 0x1000
set _CHIPNAME rv32m1
reset_config srst_only
# OpenCores Mohor JTAG TAP ID
set _CPUTAPID 0x249511C3
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAME
# Select the TAP core we are using
tap_select mohor
# Select the debug unit core we are using. This debug unit as an option.
set ADBG_USE_HISPEED 1
# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
# on burst reads and writes to improve download speeds.
# This option must match the RTL configured option.
du_select adv [expr $ADBG_USE_HISPEED]
# Select core 1
core_select 1
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
$_TARGETNAME configure -event gdb-detach {
resume
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
proc ri5cy_boot { } {
# Erase all block unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFF03FF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
proc cm4_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFFFFF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
proc zero_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFF03BF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
proc cm0_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFFFBF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 880 |
```ini
set _WORKAREASIZE 0x2000
adapter speed 1000
interface jlink
transport select jtag
set _WORKAREASIZE 0x1000
set _CHIPNAME rv32m1
reset_config srst_only
# OpenCores Mohor JTAG TAP ID
set _CPUTAPID 0x249511C3
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAME
# Select the TAP core we are using
tap_select mohor
# Select the debug unit core we are using. This debug unit as an option.
set ADBG_USE_HISPEED 1
# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
# on burst reads and writes to improve download speeds.
# This option must match the RTL configured option.
du_select adv [expr $ADBG_USE_HISPEED]
# Select core 0
core_select 0
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
$_TARGETNAME configure -event gdb-detach {
resume
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
proc ri5cy_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFF03FF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
proc cm4_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFFFFF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
proc zero_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFF03BF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
proc cm0_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFFFBF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
# All cores are available, CM4 & RI5CY boot first
proc core0_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFA3FF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
# All cores are available, CM0 & ZERO_RISCY boot first
proc core1_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFA3BF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,175 |
```restructuredtext
.. _boards-starfive:
StarFive
########
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/starfive/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
config BOARD_VISIONFIVE2
select SOC_JH7110
``` | /content/code_sandbox/boards/starfive/visionfive2/Kconfig.visionfive2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 17 |
```yaml
identifier: visionfive2
name: Visionfive JH7110 (NON-SMP)
type: mcu
arch: riscv
toolchain:
- zephyr
- cross-compile
supported:
- uart
``` | /content/code_sandbox/boards/starfive/visionfive2/visionfive2.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```yaml
board:
name: visionfive2
vendor: starfive
socs:
- name: jh7110
``` | /content/code_sandbox/boards/starfive/visionfive2/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
/*
*
*/
/dts-v1/;
#include "starfive/jh7110-visionfive-v2.dtsi"
/ {
model = "StarFive VisionFive V2";
compatible = "starfive,visionfive-v2";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &l2lim;
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
&uart1 {
status = "okay";
current-speed = <115200>;
};
``` | /content/code_sandbox/boards/starfive/visionfive2/visionfive2.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 127 |
```unknown
if BOARD_VISIONFIVE2_JH7110
config SYS_CLOCK_TICKS_PER_SEC
default 1000
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
endif # BOARD_VISIONFIVE2_JH7110
``` | /content/code_sandbox/boards/starfive/visionfive2/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
# Zephyr Kernel Configuration
CONFIG_PRINTK=y
CONFIG_XIP=n
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/starfive/visionfive2/visionfive2_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```restructuredtext
.. _visionfive2:
Starfive VisionFive 2 JH7110
############################
Overview
********
The StarFive VisionFive 2 is a development board with a StarFive JH7110
multi-core 64bit RISC-V SoC.
.. image:: img/visionfive2.webp
:align: center
:alt: StarFive VisionFive 2 Board
Programming and debugging
*************************
Building
========
Applications for the ``visionfive2`` board configuration can be built
as usual (see :ref:`build_an_application`) using the corresponding board name:
.. zephyr-app-commands::
:board: visionfive2
:goals: build
`spl_tool <path_to_url`_
is a jh7110 signature tool used to generate spl header information
and generate ``zephyr.bin.normal.out``.
.. code-block:: console
./spl_tool -c -f build/zephyr/zephyr.bin
This will create a new file ``build/zephyr/zephyr.bin.normal.out`` that can be flashed.
This step is necessary as zephyr binary must contain the SPL header info in order
to run it in M-Mode (Machine Mode) since S-Mode (Supervisor Mode) is
currently not supported.
Flashing
========
.. note::
The following steps use minicom for serial communication, feel free to use
any other serial terminal that supports xmodem based file transfers.
Thanks to @orangecms for his vf2-loader tool which makes the flashing process easier
git clone the vf2-loader tool from path_to_url and
xmodem tool from path_to_url side by side.
VisionFive2 uses uart for flashing. Refer to
`VisionFive2 Recovery Quick Start Guide
<path_to_url`_
to connect your serial-to-usb converter. Now power on the board and using
minicom access board's serial and press the reset switch on the board until you see CCCCCC... prompt
Copy the ``zephyr.bin.normal.out`` from ``build/zephyr/zephyr.bin.normal.out``
to previously git cloned vf2-loader/ directory and cd into it.
Flash the ``zephyr.bin.normal.out`` using this command:
.. code-block:: console
cargo run -- zephyr.bin.normal.out && minicom -D /dev/ttyUSB0
.. code-block:: text
cargo run -- zephyr.bin.normal.out && minicom -D /dev/ttyUSB0
Finished dev [unoptimized + debuginfo] target(s) in 0.03s
Running `target/debug/vf2-loader zephyr.bin.normal.out`
Welcome to minicom 2.7.1
OPTIONS: I18n
Compiled on Dec 23 2019, 02:06:26.
Port /dev/ttyUSB0, 14:59:24
Press CTRL-A Z for help on special keys
6*** Booting Zephyr OS build v3.6.0-rc3 ***
Hello World! visionfive2
``` | /content/code_sandbox/boards/starfive/visionfive2/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 652 |
```restructuredtext
.. _boards-others:
Other and unknown vendors
#########################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/others/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```cmake
board_runner_args(jlink "--device=STM32F407ZG" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/others/black_f407zg_pro/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f407Xg.dtsi>
#include <st/f4/stm32f407z(e-g)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "black_f407zg_pro board";
compatible = "st,stm32f407";
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,ccm = &ccm0;
zephyr,canbus = &can2;
};
leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpiof 9 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
green_led_2: led_2 {
gpios = <&gpiof 10 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_0: K0 {
label = "Key K0";
gpios = <&gpiob 9 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_1: K1 {
label = "Key K1";
gpios = <&gpiob 8 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
user_button_UP: K_UP {
label = "Key WK_UP";
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_UP>;
};
};
aliases {
led0 = &green_led_1;
led1 = &green_led_2;
sw0 = &user_button_UP;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <336>;
div-p = <2>;
div-q = <7>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(168)>;
ahb-prescaler = <1>;
apb1-prescaler = <4>;
apb2-prescaler = <2>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&timers2 {
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch1_pa0>;
pinctrl-names = "default";
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_rx_pd0 &can1_tx_pd1>;
pinctrl-names = "default";
status = "disabled";
};
&can2 {
pinctrl-0 = <&can2_rx_pb12 &can2_tx_pb13>;
pinctrl-names = "default";
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_sck_pb10 &spi2_miso_pc2 &spi2_mosi_pc3>;
pinctrl-names = "default";
status = "okay";
};
``` | /content/code_sandbox/boards/others/black_f407zg_pro/black_f407zg_pro.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 934 |
```unknown
config BOARD_BLACK_F407ZG_PRO
select SOC_STM32F407XG
``` | /content/code_sandbox/boards/others/black_f407zg_pro/Kconfig.black_f407zg_pro | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```yaml
board:
name: black_f407zg_pro
vendor: others
socs:
- name: stm32f407xx
``` | /content/code_sandbox/boards/others/black_f407zg_pro/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: black_f407zg_pro
name: Black STM32 F407ZG Pro Development Board
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 192
flash: 1024
supported:
- can
- pwm
- counter
- usb
- spi
- gpio
``` | /content/code_sandbox/boards/others/black_f407zg_pro/black_f407zg_pro.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART
CONFIG_SERIAL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# Enable GPIO
CONFIG_GPIO=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/others/black_f407zg_pro/black_f407zg_pro_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
# black_f407zg board configuration
if BOARD_BLACK_F407ZG_PRO
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_BLACK_F407ZG_PRO
``` | /content/code_sandbox/boards/others/black_f407zg_pro/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```ini
source [find board/stm32f4discovery.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/others/black_f407zg_pro/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```restructuredtext
.. _black_f407zg_pro_board:
Black STM32 F407ZG Pro Development Board
########################################
Overview
********
The BLACK_F407ZG_PRO board features an ARM Cortex-M4 based STM32F407zg MCU
with a wide range of connectivity support and configurations. There are
multiple version of this board like ``black_f407ve``.
Here are some highlights of the BLACK_F407ZG_PRO board:
- STM32 microcontroller in LQFP144 package
- Extension header for all LQFP144 I/Os for quick connection to prototyping
board and easy probing
- Flexible board power supply:
- USB VBUS or external source (3.3V, 5V)
- Power management access point
- Three LEDs:
- 3.3 V power on (LD0)
- Two user LEDs: green (LD1), green (LD2)
- Four push-buttons: RESET, K0, K1 and WK_UP
- Mini-AB connector
.. image:: img/black_f407zg_pro.jpg
:align: center
:alt: BLACK_F407ZG_PRO
.. warning:: The +5V pins on this board are directly connected to the +5V pin
of the USB connector. There is no protection in place. Do not
power this board through USB and an external power supply at
the same time.
Hardware
********
BLACK_F407ZG_PRO board provides the following hardware components:
- STM32F407ZGT6 in LQFP144 package
- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
- 168 MHz max CPU frequency
- VDD from 1.8 V to 3.6 V
- 8MHz system crystal
- 32.768KHz RTC crystal
- JTAG/SWD header
- 1024 kB Flash
- 192+4 KB SRAM including 64-Kbyte of core coupled memory
- GPIO with external interrupt capability
- 3x12-bit ADC with 24 channels
- 2x12-bit D/A converters
- RTC battery CR1220
- Advanced-control Timer (2)
- General Purpose Timers (12)
- Watchdog Timers (2)
- USART (3), UART (2)
- I2C (3)
- I2S (2)
- SPI (3)
- SDIO (1)
- CAN (2)
- USB 2.0 OTG FS with on-chip PHY
- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI
- 10/100 Ethernet MAC with dedicated DMA
- CRC calculation unit
- True random number generator
- DMA Controller
- Micro SD
- 1x 10/100 Ethernet MAC
- 1x 8 to 12-bit Parallel Camera interface
- Micro USB for power and comms
- 2x jumpers for bootloader selection
- 2x16 FMSC LCD Interface
- NRF24L01 socket
- Dimensions: 102.5mm x 74.56mm
More information about STM32F407ZG SOC can be found here:
- `STM32F407ZG on www.st.com`_
Supported Features
==================
The Zephyr black_f407zg_pro board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| USB | on-chip | usb |
+-----------+------------+-------------------------------------+
| CAN | on-chip | CAN controller |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
.. note:: CAN feature requires CAN transceiver.
Zephyr default configuration uses CAN_2 exclusively, as
simultaneous use of CAN_1 and CAN_2 is not yet supported.
Other hardware features are not yet supported on Zephyr porting.
The default configuration can be found in
:zephyr_file:`boards/others/black_f407zg_pro/black_f407zg_pro_defconfig`
Pin Mapping
===========
BLACK_F407ZG_PRO has 7 GPIO controllers. These controllers are responsible for pin
muxing, input/output, pull-up, etc.
Default Zephyr Peripheral Mapping:
----------------------------------
.. rst-class:: rst-columns
- UART_1_TX : PB6
- UART_1_RX : PB7
- UART_2_TX : PA2
- UART_2_RX : PA3
- USER_PB : PA0
- LD3 : PD13
- LD4 : PD12
- LD5 : PD14
- LD6 : PD15
- USB DM : PA11
- USB DP : PA12
- CAN1_RX : PD0
- CAN1_TX : PD1
- CAN2_RX : PB12
- CAN2_TX : PB13
- SPI2 MISO : PC2
- SPI2 MOSI : PC3
- SPI2 SCK : PB10
System Clock
============
BLACK_F407ZG_PRO System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock
at 168MHz, driven by 8MHz high speed external clock.
Serial Port
===========
BLACK_F407ZG_PRO has up to 6 UARTs. The Zephyr console output is assigned to UART2.
Default settings are 115200 8N1.
Please note that ST-Link Virtual Com Port is not wired to chip serial port.
In order to enable console output you should use a serial cable and connect
it to UART2 pins (PA2/PA3).
Programming and Debugging
*************************
Applications for the ``black_f407zg_pro`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
BLACK_F407ZG_PRO board includes an ST-LINK/V2 embedded debug tool interface.
This interface is supported by the openocd version included in Zephyr SDK.
Flashing an application to BLACK_F407ZG_PRO
-------------------------------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
Run a serial host program to connect with your board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Build and flash the application:
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: black_f407zg_pro
:goals: build flash
You should see user led "LD1" blinking.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: black_f407zg_pro
:maybe-skip-config:
:goals: debug
.. _STM32F407ZG on www.st.com:
path_to_url
``` | /content/code_sandbox/boards/others/black_f407zg_pro/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,656 |
```cmake
set(BOARD_REVISIONS "blue" "black")
if(NOT DEFINED BOARD_REVISION)
set(BOARD_REVISION "blue")
else()
if(NOT BOARD_REVISION IN_LIST BOARD_REVISIONS)
message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for stm32_min_dev. Accepted revisions: ${BOARD_REVISIONS}")
endif()
endif()
``` | /content/code_sandbox/boards/others/stm32_min_dev/revision.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```cmake
board_runner_args(jlink "--device=STM32F103C8" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/others/stm32_min_dev/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
# STM32 Minimum Development Board Configuration
config BOARD_STM32_MIN_DEV
select SOC_STM32F103X8
``` | /content/code_sandbox/boards/others/stm32_min_dev/Kconfig.stm32_min_dev | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
/*
*
*/
/ {
model = "STM32 Minimum Development Board (Black)";
compatible = "stm32_min_dev_black", "st,stm32f103c8";
leds {
led: led {
gpios = <&gpiob 12 GPIO_ACTIVE_LOW>;
};
};
};
``` | /content/code_sandbox/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_black.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```yaml
board:
name: stm32_min_dev
vendor: others
revision:
format: custom
socs:
- name: stm32f103xb
``` | /content/code_sandbox/boards/others/stm32_min_dev/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```yaml
identifier: stm32_min_dev@black
name: STM32 Minimum Development Board (black)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 20
supported:
- i2c
- pwm
- spi
- adc
- gpio
``` | /content/code_sandbox/boards/others/stm32_min_dev/stm32_min_dev_black.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
/*
*
*/
/ {
model = "STM32 Minimum Development Board (Blue)";
compatible = "stm32_min_dev_blue", "st,stm32f103c8";
leds {
led: led {
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
};
};
};
``` | /content/code_sandbox/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_blue.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f1/stm32f103X8.dtsi>
#include <st/f1/stm32f103r(8-b)tx-pinctrl.dtsi>
/ {
model = "STM32 Minimum Development Board";
compatible = "st,stm32f103c8";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,osdp-uart = &usart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
led: led {
gpios = <&gpiob 12 GPIO_ACTIVE_HIGH>;
label = "LD";
};
};
aliases {
led0 = &led;
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};
&pll {
mul = <9>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(72)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
/* usbpre not set: USB clock = 72 / 1.5: 48MHz */
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
current-speed = <115200>;
pinctrl-names = "default";
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
current-speed = <115200>;
pinctrl-names = "default";
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
current-speed = <115200>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
pinctrl-0 = < &i2c1_scl_pb6 &i2c1_sda_pb7 >;
status = "okay";
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = < &i2c2_scl_pb10 &i2c2_sda_pb11 >;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_nss_master_pa4 &spi1_sck_master_pa5
&spi1_miso_master_pa6 &spi1_mosi_master_pa7>;
pinctrl-names = "default";
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_nss_master_pb12 &spi2_sck_master_pb13
&spi2_miso_master_pb14 &spi2_mosi_master_pb15>;
pinctrl-names = "default";
status = "okay";
};
&timers1 {
status = "okay";
pwm1: pwm {
status = "okay";
pinctrl-0 = <&tim1_ch1_pwm_out_pa8>;
pinctrl-names = "default";
};
};
zephyr_udc0: &usb {
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in0_pa0>;
pinctrl-names = "default";
status = "okay";
};
``` | /content/code_sandbox/boards/others/stm32_min_dev/stm32_min_dev.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 824 |
```yaml
identifier: stm32_min_dev@blue
name: STM32 Minimum Development Board (blue)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 20
supported:
- i2c
- pwm
- spi
- adc
- gpio
``` | /content/code_sandbox/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
# STM32 Minimum Development Board Configuration
#
#
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# enable clock control
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/others/stm32_min_dev/stm32_min_dev_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```restructuredtext
.. highlight:: sh
.. _rv32m1_vega:
OpenISA VEGAboard
#################
Overview
********
The VEGAboard contains the RV32M1 SoC, featuring two RISC-V CPUs,
on-die XIP flash, and a full complement of peripherals, including a
2.4 GHz multi-protocol radio. It also has built-in sensors and
Arduino-style expansion connectors.
.. figure:: rv32m1_vega.jpg
:align: center
:alt: RV32M1-VEGA
OpenISA VEGAboard (image copyright: www.open-isa.org)
The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are
respectively based on the `PULP platform`_ designs by the same names:
`RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more
flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a
"secondary" core. The main ZERO-RISCY use-case is as a wireless
coprocessor for applications running on RI5CY. The two cores can
communicate via shared memory and messaging peripherals.
Currently, Zephyr supports RI5CY with the ``rv32m1_vega/openisa_rv32m1/ri5cy`` board
configuration name, and ZERO_RISCY with the ``rv32m1_vega/openisa_rv32m1/zero_riscy`` board
configuration name.
Hardware
********
The VEGAboard includes the following features.
RV32M1 multi-core SoC:
- 1 MiB flash and 192 KiB SRAM (RI5CY core)
- 256 KiB flash and 128 KiB SRAM (ZERO-RISCY core)
- Low power modes
- DMA support
- Watchdog, CRC, cryptographic acceleration, ADC, DAC, comparator,
timers, PWM, RTC, I2C, UART, SPI, external memory, I2S, smart
card, USB full-speed, uSDHC, and 2.4 GHz multiprotocol radio
peripherals
On-board sensors and peripherals:
- 32 Mbit SPI flash
- 6-axis accelerometer, magnetometer, and temperature sensor (FXOS8700)
- Ambient light sensor
- RGB LED
- microSD card slot
- Antenna interface
Additional features:
- Form-factor compatible with Arduino Uno Rev 3 expansion connector
layout (not all Arduino shields may be pin-compatible)
- UART via USB using separate OpenSDA chip
- RISC-V flash and debug using external JTAG dongle (not included) via
2x5 5 mil pitch connector (commonly called the "ARM 10-pin JTAG"
connector)
Supported Features
==================
Zephyr's RI5CY configuration, ``rv32m1_vega/openisa_rv32m1/ri5cy``, currently supports
the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| EVENT | on-chip | event unit interrupt controller |
+-----------+------------+-------------------------------------+
| INTMUX | on-chip | level 2 interrupt controller |
+-----------+------------+-------------------------------------+
| LPTMR | on-chip | lptmr-based system timer |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial |
+-----------+------------+-------------------------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| TPM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| SENSOR | off-chip | fxos8700 polling; |
| | | fxos8700 trigger; |
+-----------+------------+-------------------------------------+
Zephyr's ZERO-RISCY configuration, ``rv32m1_vega/openisa_rv32m1/zero_riscy``, currently
supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| EVENT | on-chip | event unit interrupt controller |
+-----------+------------+-------------------------------------+
| INTMUX | on-chip | level 2 interrupt controller |
+-----------+------------+-------------------------------------+
| LPTMR | on-chip | lptmr-based system timer |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial |
+-----------+------------+-------------------------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+-------------------------------------+
| TPM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| SENSOR | off-chip | fxos8700 polling; |
| | | fxos8700 trigger; |
+-----------+------------+-------------------------------------+
BLE Software Link Layer experimental support
==================================================
This is an experimental feature supported on the Zephyr's RI5CY
configuration, ``rv32m1_vega/openisa_rv32m1/ri5cy``. It uses the Software Link Layer
framework by Nordic Semi to enable the on-SoC radio and transceiver for
implementing a software defined BLE controller. By using both the controller
and the host stack available in Zephyr, the following BLE samples can be used
with this board:
- beacon
- central
- central_hr
- eddystone
- hci_uart
- ibeacon
- peripheral_csc (Cycling Speed Cadence)
- peripheral_dis (Device Information Service)
- peripheral_esp (Environmental Sensing Service)
- peripheral_hr (Heart Rate)
- peripheral_ht (Health Thermometer)
- peripheral
- scan_adv
.. note::
BLE Software Link Layer limitations:
- no 512/256 Kbps PHY
- no TX power adjustment
Connections and IOs
===================
RV32M1 SoC pins are brought out to Arduino-style expansion connectors.
These are 2 pins wide each, adding an additional row of expansion pins
per header compared to the standard Arduino layout.
They are described in the tables in the following subsections. Since
pins are usually grouped by logical function in rows on these headers,
the odd- and even-numbered pins are listed in separate tables. The
"Port/bit" columns refer to the SoC PORT and GPIO peripheral
naming scheme, e.g. "E/13" means PORTE/GPIOE pin 13.
See the schematic and chip reference manual for details.
(Documentation is available from the `OpenISA GitHub releases`_ page.)
.. note::
Pins with peripheral functionality may also be muxed as GPIOs.
**Top right expansion header (J1)**
Odd/bottom pins:
=== ======== =================
Pin Port/bit Function
=== ======== =================
1 E/13 I2S_TX_BCLK
3 E/14 I2S_TX_FS
5 E/15 I2S_TXD
7 E/19 I2S_MCLK
9 E/16 I2S_RX_BCLK
11 E/21 SOF_OUT
13 E/17 I2S_RX_FS
15 E/18 I2S_RXD
=== ======== =================
Even/top pins:
=== ======== =================
Pin Port/bit Function
=== ======== =================
2 A/25 UART1_RX
4 A/26 UART1_TX
6 A/27 GPIO
8 B/13 PWM
10 B/14 GPIO
12 A/30 PWM
14 A/31 PWM/CMP
16 B/1 GPIO
=== ======== =================
**Top left expansion header (J2)**
Odd/bottom pins:
=== ======== =================
Pin Port/bit Function
=== ======== =================
1 D/5 FLEXIO_D25
3 D/4 FLEXIO_D24
5 D/3 FLEXIO_D23
7 D/2 FLEXIO_D22
9 D/1 FLEXIO_D21
11 D/0 FLEXIO_D20
13 C/30 FLEXIO_D19
15 C/29 FLEXIO_D18
17 C/28 FLEXIO_D17
19 B/29 FLEXIO_D16
=== ======== =================
Even/top pins:
=== ======== =================
Pin Port/bit Function
=== ======== =================
2 B/2 GPIO
4 B/3 PWM
6 B/6 SPI0_PCS2
8 B/5 SPI0_SOUT
10 B/7 SPI0_SIN
12 B/4 SPI0_SCK
14 - GND
16 - AREF
18 C/9 I2C0_SDA
20 C/10 I2C0_SCL
=== ======== =================
**Bottom left expansion header (J3)**
Note that the headers at the bottom of the board have odd-numbered
pins on the top, unlike the headers at the top of the board.
Odd/top pins:
=== ======== ====================
Pin Port/bit Function
=== ======== ====================
1 A/21 ARDUINO_EMVSIM_PD
3 A/20 ARDUINO_EMVSIM_IO
5 A/19 ARDUINO_EMVSIM_VCCEN
7 A/18 ARDUINO_EMVSIM_RST
9 A/17 ARDUINO_EMVSIM_CLK
11 B/17 FLEXIO_D7
13 B/16 FLEXIO_D6
15 B/15 FLEXIO_D5
=== ======== ====================
Even/bottom pins: note that these are mostly power-related.
=== ======== =================
Pin Port/bit Function
=== ======== =================
2 - SDA_GPIO0
4 - BRD_IO_PER
6 - RST_SDA
8 - BRD_IO_PER
10 - P5V_INPUT
12 - GND
14 - GND
16 - P5-9V VIN
=== ======== =================
**Bottom right expansion header (J4)**
Note that the headers at the bottom of the board have odd-numbered
pins on the top, unlike the headers at the top of the board.
Odd/top pins:
=== ======== ========================================
Pin Port/bit Function
=== ======== ========================================
1 - TAMPER2
3 - TAMPER1/RTC_CLKOUT
5 - TAMPER0/RTC_WAKEUP_b
7 E/2 ADC0_SE19
9 E/5 LPCMP1_IN2/LPCMP1_OUT
11 - DAC0_OUT/ADC0_SE16/LPCMP0_IN3/LPCMP1_IN3
=== ======== ========================================
Even/bottom pins:
=== ======== ===========================================
Pin Port/bit Function
=== ======== ===========================================
2 C/11 ADC0_SE6
4 C/12 ADC0_SE7
6 B/9 ADC0_SE3
8 E/4 ADC0_SE21
10 E/10 ADC0_SE19 (and E/10, I2C3_SDA via 0 Ohm DNP)
12 E/11 ADC0_SE20 (and E/11, I2C3_SCL via 0 Ohm DNP)
=== ======== ===========================================
Additional Pins
---------------
For an up-to-date description of additional pins (such as buttons,
LEDs, etc.) supported by Zephyr, see the board DTS files in the Zephyr
source code, i.e.
:zephyr_file:`boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts` for RI5CY and
:zephyr_file:`boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts` for
ZERO-RISCY.
See the schematic in the documentation available from the `OpenISA
GitHub releases`_ page for additional details.
System Clocks
=============
The RI5CY and ZERO-RISCY cores are configured to use the slow internal
reference clock (SIRC) as the clock source for an LPTMR peripheral to manage
the system timer, and the fast internal reference clock (FIRC) to generate a
48MHz core clock.
Serial Port
===========
The USB connector at the top left of the board (near the RESET button) is
connected to an OpenSDA chip which provides a serial USB device. This is
connected to the LPUART0 peripheral which the RI5CY and ZERO-RISCY cores use by
default for console and logging.
.. warning::
The OpenSDA chip cannot be used to flash or debug the RISC-V cores.
See the next section for flash and debug instructions for the
RISC-V cores using an external JTAG dongle.
Programming and Debugging
*************************
.. _rv32m1-programming-hw:
.. important::
To use this board, you will need:
- a `SEGGER J-Link`_ debug probe to debug the RISC-V cores
- a J-Link `9-Pin Cortex-M Adapter`_ board and ribbon cable
- the SEGGER `J-Link Software and Documentation Pack`_ software
installed
A JTAG dongle is not included with the board itself.
Follow these steps to:
#. Get a toolchain and OpenOCD
#. Set up the board for booting RI5CY
#. Compile a Zephyr application for the RI5CY core
#. Flash the application to your board
#. Debug the board using GDB
.. _rv32m1-toolchain-openocd:
Get the Toolchain and OpenOCD
=============================
Before programming and debugging, you first need to get a GNU
toolchain and an OpenOCD build. There are vendor-specific versions of
each for the RV32M1 SoC\ [#toolchain_openocd]_.
Option 1 (Recommended): Prebuilt Toolchain and OpenOCD
------------------------------------------------------
The following prebuilt toolchains and OpenOCD archives are available
on the `OpenISA GitHub releases`_ page:
- :file:`Toolchain_Linux.tar.gz`
- :file:`Toolchain_Mac.tar.gz`
- :file:`Toolchain_Windows.zip`
Download and extract the archive for your system, then extract the
toolchain and OpenOCD archives inside.
Linux::
tar xvzf Toolchain_Linux.tar.gz
tar xvzf openocd.tar.gz
tar xvzf riscv32-unknown-elf-gcc.tar.gz
mv openocd ~/rv32m1-openocd
mv riscv32-unknown-elf-gcc ~
macOS (unfortunately, the OpenISA 1.0.0 release's Mac
:file:`riscv32-unknown-elf-gcc.tar.gz` file doesn't expand into a
:file:`riscv32-unknown-elf-gcc` directory, so it has to be created)::
tar xvzf Toolchain_Mac.tar.gz
tar xvzf openocd.tar.gz
mkdir riscv32-unknown-elf-gcc
mv riscv32-unknown-elf-gcc.tar.gz riscv32-unknown-elf-gcc
cd riscv32-unknown-elf-gcc/
tar xvzf riscv32-unknown-elf-gcc.tar.gz
cd ..
mv openocd ~/rv32m1-openocd
mv riscv32-unknown-elf-gcc ~
Windows:
#. Extract :file:`Toolchain_Windows.zip` in the file manager
#. Extract the :file:`openocd.zip` and :file:`riscv32-unknown-elf-gcc.zip` files
in the resulting :file:`Toolchain_Windows` folder
#. Move the extracted :file:`openocd` folder to :file:`C:\\rv32m1-openocd`
#. Move the extracted :file:`riscv32-unknown-elf-gcc` folder to
:file:`C:\\riscv32-unknown-elf-gcc`
For simplicity, this guide assumes:
- You put the extracted toolchain at :file:`~/riscv32-unknown-elf-gcc`
on macOS or Linux, and :file:`C:\\riscv32-unknown-elf-gcc` on
Windows.
- You put the extracted OpenOCD binary at :file:`~/rv32m1-openocd` on
macOS or Linux, and the OpenOCD folder into :file:`C:\\rv32m1-openocd`
on Windows.
You can put them elsewhere, but be aware:
- If you put the toolchain somewhere else, you will need to change
the ``CROSS_COMPILE`` value described below accordingly.
- If you put OpenOCD somewhere else, you will need to change the
OpenOCD path in the flashing and debugging instructions below.
- Don't use installation directories with spaces anywhere in the path;
this won't work with Zephyr's build system.
Option 2: Building Toolchain and OpenOCD From Source
----------------------------------------------------
See :ref:`rv32m1_vega_toolchain_build`.
.. _rv32m1-vega-jtag:
JTAG Setup
==========
This section describes how to connect to your board via the J-Link
debugger and adapter board. See the :ref:`above information
<rv32m1-programming-hw>` for details on required hardware.
#. Connect the J-Link debugger through the adapter board to the
VEGAboard as shown in the figure.
.. figure:: rv32m1_vega_jtag.jpg
:align: center
:alt: RV32M1-VEGA
VEGAboard connected properly to J-Link debugger.
VEGAboard connector J55 should be used. Pin 1 is on the bottom left.
#. Power the VEGAboard via USB. The OpenSDA connector at the top left
is recommended for UART access.
#. Make sure your J-Link is connected to your computer via USB.
One-Time Board Setup For Booting RI5CY or ZERO-RISCY
====================================================
Next, you'll need to make sure your board boots the RI5CY or ZERO-RISCY core.
**You only need to do this once.**
The RV32M1 SoC on the VEGAboard has multiple cores, any of which can
be selected as the boot core. Before flashing and debugging, you'll
first make sure you're booting the right core.
**Linux and macOS**:
.. note::
Linux users: to run these commands as a normal user, you will need
to install the `60-openocd.rules`_ udev rules file (usually by
placing it in :file:`/etc/udev/rules.d`, then unplugging and
plugging the J-Link in again via USB).
.. note::
These Zephyr-specific instructions differ slightly from the
equivalent SDK ones. The Zephyr OpenOCD configuration file does not
run ``init``, so you have to do it yourself as explained below.
1. In one terminal, use OpenOCD to connect to the board::
~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
The output should look like this:
.. code-block:: console
$ ~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
Open On-Chip Debugger 0.10.0+dev-00431-ge1ec3c7d (2018-10-31-07:29)
[...]
Info : Listening on port 3333 for gdb connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
2. In another terminal, connect to OpenOCD's telnet server and execute
the ``init`` and ``ri5cy_boot`` commands **with the reset button on
the board (at top left) pressed down**::
$ telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> init
> ri5cy_boot
To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with
``zero_boot``.
The reset button is at top left, as shown in the following figure.
.. figure:: ri5cy_boot.jpg
:align: center
:alt: Reset button is pressed
Now quit the telnet session in this terminal and exit OpenOCD in the
other terminal.
3. Unplug your J-Link and VEGAboard, and plug them back in.
**Windows**:
In one cmd.exe prompt in the Zephyr directory::
C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\openisa\rv32m1_vega\support\openocd_rv32m1_vega_ri5cy.cfg
In a telnet program of your choice:
#. Connect to localhost port 4444 using telnet.
#. Run ``init`` and ``ri5cy_boot`` as shown above, with RESET held down.
#. Quit the OpenOCD and telnet sessions.
#. Unplug your J-Link and VEGAboard, and plug them back in.
To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with
``zero_boot``.
Compiling a Program
===================
.. important::
These instructions assume you've set up a development system,
cloned the Zephyr repository, and installed Python dependencies as
described in the :ref:`getting_started`.
You should also have already downloaded and installed the toolchain
and OpenOCD as described above in :ref:`rv32m1-toolchain-openocd`.
The first step is to set up environment variables to point at your
toolchain and OpenOCD::
# Linux or macOS
export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile
export CROSS_COMPILE=~/riscv32-unknown-elf-gcc/bin/riscv32-unknown-elf-
# Windows
set ZEPHYR_TOOLCHAIN_VARIANT=cross-compile
set CROSS_COMPILE=C:\riscv32-unknown-elf-gcc\bin\riscv32-unknown-elf-
.. note::
The above only sets these variables for your current shell session.
You need to make sure this happens every time you use this board.
Now let's compile the :ref:`hello_world` application. (You can try
others as well; see :ref:`samples-and-demos` for more.)
.. We can't use zephyr-app-commands to provide build instructions
due to the below mentioned linker issue.
Due to a toolchain `linker issue`_, you need to add an option setting
``CMAKE_REQUIRED_FLAGS`` when running CMake to generate a build system
(see :ref:`application` for information about Zephyr's build system).
Linux and macOS (run this in a terminal from the Zephyr directory)::
# Set up environment and create build directory:
source zephyr-env.sh
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:tool: cmake
:cd-into:
:board: rv32m1_vega/openisa_rv32m1/ri5cy
:gen-args: -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=/dev/null
:goals: build
Windows (run this in a ``cmd`` prompt, from the Zephyr directory)::
# Set up environment and create build directory
zephyr-env.cmd
cd samples\hello_world
mkdir build & cd build
# Use CMake to generate a Ninja-based build system:
type NUL > empty.ld
cmake -GNinja -DBOARD=rv32m1_vega/openisa_rv32m1/ri5cy -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=%cd%\empty.ld ..
# Build the sample
ninja
Flashing
========
.. note::
Make sure you've done the :ref:`JTAG setup <rv32m1-vega-jtag>`, and
that the VEGAboard's top left USB connector is connected to your
computer too (for UART access).
.. note::
Linux users: to run these commands as a normal user, you will need
to install the `60-openocd.rules`_ udev rules file (usually by
placing it in :file:`/etc/udev/rules.d`, then unplugging and
plugging the J-Link in again via USB).
Make sure you've followed the above instructions to set up your board
and build a program first.
Since you need to use a special OpenOCD, the easiest way to flash is
by using :ref:`west flash <west-build-flash-debug>` instead of ``ninja
flash`` like you might see with other Zephyr documentation.
Run these commands from the build directory where you ran ``ninja`` in
the above section.
Linux and macOS::
# Don't use "~/rv32m1-openocd". It won't work.
west flash --openocd=$HOME/rv32m1-openocd
Windows::
west flash --openocd=C:\rv32m1-openocd\bin\openocd.exe
If you have problems:
- Make sure you don't have another ``openocd`` process running in the
background.
- Unplug the boards and plug them back in.
- On Linux, make sure udev rules are installed, as described above.
As an alternative, for manual steps to run OpenOCD and GDB to flash,
see the `SDK README`_.
Debugging
=========
.. note::
Make sure you've done the :ref:`JTAG setup <rv32m1-vega-jtag>`, and
that the VEGAboard's top left USB connector is connected to your
computer too (for UART access).
.. note::
Linux users: to run these commands as a normal user, you will need
to install the `60-openocd.rules`_ udev rules file (usually by
placing it in :file:`/etc/udev/rules.d`, then unplugging and
plugging the J-Link in again via USB).
Make sure you've followed the above instructions to set up your board
and build a program first.
To debug with gdb::
# Linux, macOS
west debug --openocd=$HOME/rv32m1-openocd
# Windows
west debug --openocd=C:\rv32m1-openocd\bin\openocd.exe
Then, from the ``(gdb)`` prompt, follow these steps to halt the core,
load the binary (:file:`zephyr.elf`), and re-sync with the OpenOCD
server::
(gdb) monitor init
(gdb) monitor reset halt
(gdb) load
(gdb) monitor gdb_sync
(gdb) stepi
You can then set breakpoints and debug using normal GDB commands.
.. note::
GDB can get out of sync with the target if you execute commands
that reset it. To reset RI5CY and get GDB back in sync with it
without reloading the binary::
(gdb) monitor reset halt
(gdb) monitor gdb_sync
(gdb) stepi
If you have problems:
- Make sure you don't have another ``openocd`` process running in the
background.
- Unplug the boards and plug them back in.
- On Linux, make sure udev rules are installed, as described above.
References
**********
- OpenISA developer portal: path_to_url
- `OpenISA GitHub releases`_: includes toolchain and OpenOCD
prebuilts, as well as documentation, such as the SoC datasheet and
reference manual, board schematic and user guides, etc.
- Base toolchain: `pulp-riscv-gnu-toolchain`_; extra toolchain patches:
`rv32m1_gnu_toolchain_patch`_ (only needed if building from source).
- OpenOCD repository: `rv32m1-openocd`_ (only needed if building from
source).
- Vendor SDK: `rv32m1_sdk_riscv`_. Contains HALs, non-Zephyr sample
applications, and information on using the board with Eclipse which
may be interesting when combined with the Eclipse Debugging
information in the :ref:`application`.
.. _rv32m1_vega_toolchain_build:
Appendix: Building Toolchain and OpenOCD from Source
****************************************************
.. note::
Toolchain and OpenOCD build instructions are provided for Linux and
macOS only.
Instructions for building OpenOCD have only been verified on Linux.
.. warning::
Don't use installation directories with spaces anywhere in
the path; this won't work with Zephyr's build system.
Ubuntu 18.04 users need to install these additional dependencies::
sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
libmpfr-dev libgmp-dev gawk build-essential bison \
flex texinfo gperf libtool patchutils bc zlib1g-dev \
libusb-1.0-0-dev libudev1 libudev-dev g++
Users of other Linux distributions need to install the above packages
with their system package manager.
macOS users need to install dependencies with Homebrew::
brew install gawk gnu-sed gmp mpfr libmpc isl zlib
The build toolchain is based on the `pulp-riscv-gnu-toolchain`_, with
some additional patches hosted in a separate repository,
`rv32m1_gnu_toolchain_patch`_. To build the toolchain, follow the
instructions in the ``rv32m1_gnu_toolchain_patch`` repository's
`readme.md`_ file to apply the patches, then run::
./configure --prefix=<toolchain-installation-dir> --with-arch=rv32imc --with-cmodel=medlow --enable-multilib
make
If you set ``<toolchain-installation-dir>`` to
:file:`~/riscv32-unknown-elf-gcc`, you can use the above instructions
for setting ``CROSS_COMPILE`` when building Zephyr
applications. If you set it to something else, you will need to update
your ``CROSS_COMPILE`` setting accordingly.
.. note::
Strangely, there is no separate ``make install`` step for the
toolchain. That is, the ``make`` invocation both builds and
installs the toolchain. This means ``make`` has to be run as root
if you want to set ``--prefix`` to a system directory such as
:file:`/usr/local` or :file:`/opt` on Linux.
To build OpenOCD, clone the `rv32m1-openocd`_ repository, then run
these from the repository top level::
./bootstrap
./configure --prefix=<openocd-installation-dir>
make
make install
If ``<openocd-installation-dir>`` is :file:`~/rv32m1-openocd`, you
should set your OpenOCD path to :file:`~/rv32m1-openocd/bin/openocd`
in the above flash and debug instructions.
.. _RI5CY:
path_to_url
.. _ZERO-RISCY:
path_to_url
.. _PULP platform:
path_to_url
.. _pulp-riscv-gnu-toolchain:
path_to_url
.. _rv32m1_gnu_toolchain_patch:
path_to_url
.. _rv32m1-openocd:
path_to_url
.. _readme.md:
path_to_url
.. _OpenISA GitHub releases:
path_to_url
.. _rv32m1_sdk_riscv:
path_to_url
.. _linker issue:
path_to_url
.. _60-openocd.rules:
path_to_url
.. _SEGGER J-Link:
path_to_url
.. _9-Pin Cortex-M Adapter:
path_to_url
.. _J-Link Software and Documentation Pack:
path_to_url#J-LinkSoftwareAndDocumentationPack
.. _SDK README:
path_to_url
.. rubric:: Footnotes
.. [#toolchain_openocd]
For Linux users, the RISC-V toolchain in the :ref:`Zephyr SDK
<toolchain_zephyr_sdk>` may work, but it hasn't been thoroughly tested with this
SoC, and will not allow use of any available RISC-V ISA extensions.
Support for the RV32M1 SoC is not currently available in the OpenOCD
upstream repository or the OpenOCD build in the Zephyr SDK.
``` | /content/code_sandbox/boards/openisa/rv32m1_vega/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,459 |
```ini
source [find interface/stlink.cfg]
# Work-area size (RAM size) = 20kB
set WORKAREASIZE 0x5000
source [find target/stm32f1x.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/others/stm32_min_dev/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```cmake
#
#
#
board_runner_args(stm32flash "--start-addr=0x08000000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/stm32flash.board.cmake)
``` | /content/code_sandbox/boards/others/stm32f030_demo/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```yaml
identifier: stm32f030_demo
name: STM32F030 DEMO BOARD
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 4
flash: 16
supported:
- uart
- gpio
- adc
``` | /content/code_sandbox/boards/others/stm32f030_demo/stm32f030_demo.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
config BOARD_STM32F030_DEMO
select SOC_STM32F030X4
``` | /content/code_sandbox/boards/others/stm32f030_demo/Kconfig.stm32f030_demo | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
board:
name: stm32f030_demo
vendor: others
socs:
- name: stm32f030x6
``` | /content/code_sandbox/boards/others/stm32f030_demo/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# Kernel Options due to Low Memory (4k)
CONFIG_MAIN_STACK_SIZE=640
CONFIG_IDLE_STACK_SIZE=200
CONFIG_ISR_STACK_SIZE=512
# Prevent Interrupt Vector Table in RAM
CONFIG_SRAM_VECTOR_TABLE=n
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# GPIO Controller
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/others/stm32f030_demo/stm32f030_demo_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f0/stm32f030X4.dtsi>
#include <st/f0/stm32f030f4px-pinctrl.dtsi>
/ {
model = "STM32F030 DEMO board";
compatible = "stm32f030-demo";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
led: led {
gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
label = "User LED";
};
};
aliases {
led0 = &led;
watchdog0 = &iwdg;
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};
&pll {
prediv = <1>;
mul = <6>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
/* Due to limited available memory, don't enable gpioc,d,e,f */
&gpioc {status = "disabled";};
&gpiod {status = "disabled";};
&gpiof {status = "disabled";};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&iwdg {
status = "okay";
};
``` | /content/code_sandbox/boards/others/stm32f030_demo/stm32f030_demo.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 392 |
```ini
source [find interface/stlink.cfg]
# Work-area size (RAM size) = 4kB
set WORKAREASIZE 0x1000
source [find target/stm32f0x.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/others/stm32f030_demo/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```restructuredtext
.. _stm32_min_dev:
STM32 Minimum Development Board
###############################
Overview
********
The STM32 Minimum Development Board, is a popular and inexpensive
breadboard-friendly breakout board for the `STM32F103x8`_ CPU. There
are two variants of the board:
- Blue Pill Board
- Black Pill Board
Zephyr applications can use the stm32_min_dev@blue or stm32_min_dev@black board
configuration to use these boards.
.. figure:: img/stm32_min_dev.jpg
:align: center
:alt: STM32 Minimum Development Board
STM32 Minimum Development Board
As the name suggests, these boards have the bare minimum components required to
power on the CPU. For practical use, you'll need to add additional components
and circuits using a breadboard, for example.
Pin Mapping
===========
This port is a starting point for your own customizations and not a complete
port for a specific board. Most of the GPIOs on the STM32 SoC has been exposed
in the external header with silk screen labels that match the SoC's pin names.
Each board vendor has their own variations in pin mapping on their boards'
external connectors and placement of components. Many vendors use port PC13/PB12
for connecting an LED, so only this device is supported by our Zephyr port.
Additional device support is left for the user to implement.
More information on hooking up peripherals and lengthy how to articles can be
found at `EmbedJournal`_.
The pinout diagram of STM32 Minimum Development Blue Pill board can be seen
below. The Black Pill's one is similar:
.. figure:: img/stm32_min_dev_pinout_blue.jpg
:align: center
:alt: Pinout for STM32 Minimum Development Blue Pill Board
Pinout for STM32 Minimum Development Blue Pill Board
STLinkV2 connection:
====================
The board can be flashed by using STLinkV2 with the following connections.
+--------+---------------+
| Pin | STLINKv2 |
+========+===============+
| G | GND |
+--------+---------------+
| CLK | Clock |
+--------+---------------+
| IO | SW IO |
+--------+---------------+
| V3 | VCC |
+--------+---------------+
Boot Configuration
==================
The boot configuration for this board is configured through jumpers on B0 (Boot 0)
and B1 (Boot 1). The pins B0 and B1 are present in between logic 0 and 1 lines. The
silk screen on the PCB reads BX- or BX+ to indicate 0 and 1 logic lines for B0 and B1
respectively.
+--------+--------+-------------------+---------------------------------------------+
| Boot 1 | Boot 0 | Boot Mode | Aliasing |
+========+========+===================+=============================================+
| X | 0 | Main Flash Memory | Main flash memory is selected as boot space |
+--------+--------+-------------------+---------------------------------------------+
| 0 | 1 | System Memory | System memory is selected as boot space |
+--------+--------+-------------------+---------------------------------------------+
| 1 | 1 | Embedded SRAM | Embedded SRAM is selected as boot space |
+--------+--------+-------------------+---------------------------------------------+
Supported Features
==================
The stm32_min_dev board configuration supports the following hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| NVIC | on-chip | nested vectored |
| | | interrupt controller |
+-----------+------------+----------------------+
| SYSTICK | on-chip | system clock |
+-----------+------------+----------------------+
| UART | on-chip | serial port |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| I2C | on-chip | i2c |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
| USB | on-chip | USB device |
+-----------+------------+----------------------+
| ADC | on-chip | adc |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
Connections and IOs
===================
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX: PA9/PA10
- UART_2 TX/RX: PA2/PA3
- UART_3 TX/RX: PB10/PB11
- I2C_1 SCL/SDA : PB6/PB7
- I2C_2 SCL/SDA : PB10/PB11
- PWM_1_CH1: PA8
- SPI_1 NSS_OE/SCK/MISO/MOSI: PA4/PA5/PA6/PA7
- SPI_2 NSS_OE/SCK/MISO/MOSI: PB12/PB13/PB14/PB15
- USB_DC DM/DP: PA11/PA12
- ADC_1: PA0
System Clock
------------
The on-board 8Mhz crystal is used to produce a 72Mhz system clock with PLL.
Serial Port
-----------
STM32 Minimum Development Board has 3 U(S)ARTs. The Zephyr console output is
assigned to UART_1. Default settings are 115200 8N1.
On-Board LEDs
-------------
The board has one on-board LED that is connected to PB12/PC13 on the black/blue
variants respectively.
Programming and Debugging
*************************
Applications for the ``stm32_min_dev@(blue|black)`` board configuration can be
built and flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32_min_dev
:goals: build flash
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32_min_dev
:maybe-skip-config:
:goals: debug
.. _STM32F103x8:
path_to_url
.. _EmbedJournal:
path_to_url
``` | /content/code_sandbox/boards/others/stm32_min_dev/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,459 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART
CONFIG_SERIAL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# Enable GPIO
CONFIG_GPIO=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/others/black_f407ve/black_f407ve_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```cmake
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
board_runner_args(jlink "--device=STM32F407VE" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
``` | /content/code_sandbox/boards/others/black_f407ve/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```unknown
config BOARD_BLACK_F407VE
select SOC_STM32F407XE
``` | /content/code_sandbox/boards/others/black_f407ve/Kconfig.black_f407ve | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 18 |
```yaml
identifier: black_f407ve
name: Black STM32 F407VE Development Board
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 192
flash: 512
supported:
- can
- pwm
- counter
- usb
- spi
- gpio
``` | /content/code_sandbox/boards/others/black_f407ve/black_f407ve.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```restructuredtext
.. _stm32f030_demo:
STM32F030 DEMO BOARD
####################
This board has the bare minimum components required to power on
the STM32F030F4P6 MCU. Most of the GPIOs on the STM32 SoC have
been exposed in the external headers with silk screen labels
that match the SoC's pin names.
For practical use, you'll need to add additional components
and circuits using a breadboard, for example.
.. image:: img/stm32f030_demo.jpg
:align: center
:alt: STM32F030 DEMO BOARD
More information about the board can be found at the `stm32-base.org website`_.
More information about STM32F030F4P6 can be found here:
- `STM32F030 reference manual`_
- `STM32F030 data sheet`_
Hardware
********
- STM32F030F4P6 ARM Cortex-M0 processor, frequency up to 48 MHz
- 16 KiB of flash memory and 4 KiB of RAM
- 8 MHz quartz crystal
- 1 user LED
- One reset button
- 2-way jumper (BOOT0)
- Serial (1x4 male dupont (2.54mm))
- SWD (1x4 male dupont (2.54mm))
- USB port (power only)
Supported Features
==================
The Zephyr stm32f030_demo board configuration supports the following
hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| die-temp | on-chip | die temperature sensor |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr porting.
The default configuration can be found in
:zephyr_file:`boards/others/stm32f030_demo/stm32f030_demo_defconfig`
Pin Mapping
===========
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX : PA9/PA10
- LED : PA4
Programming and Debugging
*************************
Applications for the ``stm32f030_demo`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
The board can be flashed by using ST-LINKV2 in-circuit debugger and programmer.
This interface is supported by the openocd version included in the Zephyr SDK.
Flashing an application to STM32F030 DEMO BOARD
-----------------------------------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32f030_demo
:goals: build flash
You will see the LED blinking every second.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32f030_demo
:maybe-skip-config:
:goals: debug
References
**********
.. target-notes::
.. _stm32-base.org website:
path_to_url
.. _STM32F030 reference manual:
path_to_url
.. _STM32F030 data sheet:
path_to_url
``` | /content/code_sandbox/boards/others/stm32f030_demo/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 853 |
```yaml
board:
name: black_f407ve
vendor: others
socs:
- name: stm32f407xx
``` | /content/code_sandbox/boards/others/black_f407ve/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
# black_f407ve board configuration
if BOARD_BLACK_F407VE
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_BLACK_F407VE
``` | /content/code_sandbox/boards/others/black_f407ve/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f407Xe.dtsi>
#include <st/f4/stm32f407v(e-g)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "black_f407ve board";
compatible = "black-stm32f407";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,ccm = &ccm0;
zephyr,canbus = &can2;
};
leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
green_led_2: led_2 {
gpios = <&gpioa 7 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_0: K0 {
label = "Key K0";
gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_1: K1 {
label = "Key K1";
gpios = <&gpioe 3 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
user_button_UP: K_UP {
label = "Key WK_UP";
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_UP>;
};
};
aliases {
led0 = &green_led_1;
led1 = &green_led_2;
sw0 = &user_button_UP;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <336>;
div-p = <2>;
div-q = <7>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(168)>;
ahb-prescaler = <1>;
apb1-prescaler = <4>;
apb2-prescaler = <2>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&timers2 {
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch1_pa0>;
pinctrl-names = "default";
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_rx_pd0 &can1_tx_pd1>;
pinctrl-names = "default";
status = "disabled";
};
&can2 {
pinctrl-0 = <&can2_rx_pb12 &can2_tx_pb13>;
pinctrl-names = "default";
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_sck_pb3 &spi1_miso_pb4 &spi1_mosi_pb5>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>;
w25q16cv: w25q16cv@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
size = <0x1000000>;
has-dpd;
t-enter-dpd = <4000>;
t-exit-dpd = <25000>;
jedec-id = [ef 40 15];
};
};
&spi2 {
pinctrl-0 = <&spi2_sck_pb10 &spi2_miso_pc2 &spi2_mosi_pc3>;
pinctrl-names = "default";
status = "okay";
};
``` | /content/code_sandbox/boards/others/black_f407ve/black_f407ve.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,086 |
```ini
source [find board/stm32f4discovery.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/others/black_f407ve/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```cmake
board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/others/neorv32/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```yaml
identifier: neorv32
name: NEORV32 Processor (SoC)
type: mcu
arch: riscv
toolchain:
- cross-compile
- zephyr
ram: 32
flash: 64
supported:
- gpio
``` | /content/code_sandbox/boards/others/neorv32/neorv32.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```yaml
board:
name: neorv32
vendor: others
revision:
format: major.minor.patch
default: "1.8.6"
revisions:
- name: "1.8.6"
socs:
- name: neorv32
``` | /content/code_sandbox/boards/others/neorv32/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
CONFIG_SOC_NEORV32_ISA_C=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/others/neorv32/neorv32_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
config BOARD_NEORV32
select SOC_NEORV32_V1_8_6 if "$(BOARD_REVISION)" = "1.8.6"
``` | /content/code_sandbox/boards/others/neorv32/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
/*
*
*/
/dts-v1/;
#include <neorv32.dtsi>
#include <freq.h>
#include <mem.h>
/ {
model = "NEORV32";
compatible = "neorv32";
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
};
chosen {
zephyr,flash = &imem;
zephyr,sram = &dmem;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-pipe = &uart0;
};
soc {
imem: memory@0 {
compatible = "soc-nv-flash", "mmio-sram";
reg = <0x0 DT_SIZE_K(64)>;
};
bootrom: memory@ffff0000 {
compatible = "soc-nv-flash", "mmio-sram";
reg = <0xffff0000 DT_SIZE_K(4)>;
};
dmem: memory@80000000 {
compatible = "mmio-sram";
reg = <0x80000000 DT_SIZE_K(32)>;
};
};
leds {
compatible = "gpio-leds";
led0: led0 {
gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
label = "LED_0";
};
led1: led1 {
gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
label = "LED_1";
};
led2: led2 {
gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
label = "LED_2";
};
led3: led3 {
gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
label = "LED_3";
};
};
};
&cpu0 {
clock-frequency = <DT_FREQ_M(100)>;
};
&uart0 {
status = "okay";
current-speed = <19200>;
};
&gpio_lo {
status = "okay";
};
&gpio_hi {
status = "okay";
};
``` | /content/code_sandbox/boards/others/neorv32/neorv32.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 481 |
```unknown
config BOARD_NEORV32
select SOC_NEORV32
``` | /content/code_sandbox/boards/others/neorv32/Kconfig.neorv32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.