text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```ini
adapter driver ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
if { [info exists _ZEPHYR_BOARD_SERIAL] } {
ftdi_serial $_ZEPHYR_BOARD_SERIAL
}
ftdi_layout_init 0x0038 0x003b
adapter speed 1000
ftdi_layout_signal nTRST -ndata 0x0010 -noe 0x0040
source [find neorv32.cfg]
``` | /content/code_sandbox/boards/others/neorv32/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```ini
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME neorv32
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 256
}
if { [info exists WORKAREAADDR] } {
set _WORKAREAADDR $WORKAREAADDR
} else {
set _WORKAREAADDR 0x80000000
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0cafe001
}
transport select jtag
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
$_TARGETNAME.0 configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1
``` | /content/code_sandbox/boards/others/neorv32/support/neorv32.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 242 |
```restructuredtext
.. _black_f407ve_board:
Black STM32 F407VE Development Board
####################################
Overview
********
The BLACK_F407VE board features an ARM Cortex-M4 based STM32F407xx MCU
with a wide range of connectivity support and configurations. There are
multiple version of this board like ``black_f407ve``.
Here are some highlights of the BLACK_F407VE board:
- STM32 microcontroller in LQFP100 package
- Extension header for all LQFP100 I/Os for quick connection to prototyping
board and easy probing
- Flexible board power supply:
- USB VBUS or external source (3.3V, 5V)
- Power management access point
- Three LEDs:
- 3.3 V power on (LD0)
- Two user LEDs: green (LD1), green (LD2)
- Four push-buttons: RESET, K0, K1 and WK_UP
- Mini-AB connector
.. image:: img/black_f407ve.jpg
:align: center
:alt: BLACK_F407VE
See also board descriptions at `STM32-base website`_,
`STM32F407VET6 black board`_ and `MCUDev Black STM32F407VET6`_
.. warning:: The +5V pins on this board are directly connected to the +5V pin
of the USB connector. There is no protection in place. Do not
power this board through USB and an external power supply at
the same time.
Hardware
********
BLACK_F407VE board provides the following hardware components:
- STM32F407VET6 in LQFP100 package
- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
- 168 MHz max CPU frequency
- VDD from 1.8 V to 3.6 V
- 8MHz system crystal
- 32.768KHz RTC crystal
- JTAG/SWD header
- 512 kB Flash
- 192+4 KB SRAM including 64-Kbyte of core coupled memory
- GPIO with external interrupt capability
- 3x12-bit ADC with 24 channels
- 2x12-bit D/A converters
- RTC battery CR1220
- Advanced-control Timer (2)
- General Purpose Timers (12)
- Watchdog Timers (2)
- USART (3), UART (2)
- I2C (3)
- I2S (2)
- SPI (3)
- SDIO (1)
- CAN (2)
- USB 2.0 OTG FS with on-chip PHY
- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI
- 10/100 Ethernet MAC with dedicated DMA
- CRC calculation unit
- True random number generator
- DMA Controller
- Micro SD
- 1x 10/100 Ethernet MAC
- 1x 8 to 12-bit Parallel Camera interface
- Micro USB for power and comms
- 2x jumpers for bootloader selection
- 2x16 FMSC LCD Interface
- NRF24L01 socket
- Dimensions: 85.1mm x 72.45mm
More information about STM32F407VE SOC can be found here:
- `STM32F407VE on www.st.com`_
Supported Features
==================
The Zephyr black_f407ve board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| USB | on-chip | usb |
+-----------+------------+-------------------------------------+
| CAN | on-chip | CAN controller |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
.. note:: CAN feature requires CAN transceiver.
Zephyr default configuration uses CAN_2 exclusively, as
simultaneous use of CAN_1 and CAN_2 is not yet supported.
Other hardware features are not yet supported on Zephyr porting.
The default configuration can be found in
:zephyr_file:`boards/others/black_f407ve/black_f407ve_defconfig`
Pin Mapping
===========
BLACK_F407VE has 5 GPIO controllers. These controllers are responsible for pin
muxing, input/output, pull-up, etc.
.. image:: img/stm32f407vet6_left02.jpg
:align: center
:alt: left pins
.. image:: img/stm32f407vet6_right01.jpg
:align: center
:alt: right pins
.. image:: img/stm32f407vet6_st-link02.jpg
:align: center
:alt: bottom and top pins
Default Zephyr Peripheral Mapping:
----------------------------------
.. rst-class:: rst-columns
- UART_1_TX : PA9
- UART_1_RX : PA10
- UART_2_TX : PA2
- UART_2_RX : PA3
- USER_PB : PA0
- LD3 : PD13
- LD4 : PD12
- LD5 : PD14
- LD6 : PD15
- USB DM : PA11
- USB DP : PA12
- CAN1_RX : PD0
- CAN1_TX : PD1
- CAN2_RX : PB12
- CAN2_TX : PB13
- SPI1 MISO : PB4
- SPI1 MOSI : PB5
- SPI1 SCK : PB3
- SPI1 Flash CS : PB0
- SPI2 MISO : PC2
- SPI2 MOSI : PC3
- SPI2 SCK : PB10
System Clock
============
BLACK_F407VE System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock
at 168MHz, driven by 8MHz high speed external clock.
Serial Port
===========
BLACK_F407VE has up to 6 UARTs. The Zephyr console output is assigned to UART1.
Default settings are 115200 8N1.
Please note that ST-Link Virtual Com Port is not wired to chip serial port.
In order to enable console output you should use a serial cable and connect
it to UART1 pins (PA9/PA10).
Programming and Debugging
*************************
Applications for the ``black_f407ve`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
BLACK_F407VE board includes an ST-LINK/V2 embedded debug tool interface.
This interface is supported by the openocd version included in Zephyr SDK.
Flashing an application to BLACK_F407VE
---------------------------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
Run a serial host program to connect with your board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Build and flash the application:
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: black_f407ve
:goals: build flash
You should see user led "LD1" blinking.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: black_f407ve
:maybe-skip-config:
:goals: debug
.. _STM32-base website:
path_to_url
.. _STM32F407VE on www.st.com:
path_to_url
.. _STM32F407VET6 black board:
path_to_url
.. _MCUDev Black STM32F407VET6:
path_to_url
``` | /content/code_sandbox/boards/others/black_f407ve/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,826 |
```cmake
include(${ZEPHYR_BASE}/boards/common/bossac.board.cmake)
``` | /content/code_sandbox/boards/others/serpente/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```unknown
/*
*
*/
/dts-v1/;
#include <atmel/samd21.dtsi>
#include <atmel/samx2xx18.dtsi>
#include "serpente-pinctrl.dtsi"
/ {
model = "Serpente";
compatible = "arturo182,serpente";
chosen {
zephyr,console = &sercom2;
zephyr,shell-uart = &sercom2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &code_partition;
};
aliases {
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
red-led = &red_led;
green-led = &green_led;
blue-led = &blue_led;
pwm-led0 = &red_pwm_led;
pwm-led1 = &green_pwm_led;
pwm-led2 = &blue_pwm_led;
red-pwm-led = &red_pwm_led;
green-pwm-led = &green_pwm_led;
blue-pwm-led = &blue_pwm_led;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&porta 22 GPIO_ACTIVE_LOW>;
label = "Red LED";
};
green_led: led_1 {
gpios = <&porta 19 GPIO_ACTIVE_LOW>;
label = "Green LED";
};
blue_led: led_2 {
gpios = <&porta 23 GPIO_ACTIVE_LOW>;
label = "Blue LED";
};
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: pwm_led_0 {
pwms = <&tcc0 0 PWM_MSEC(20)>;
label = "Red PWM LED";
};
green_pwm_led: pwm_led_1 {
pwms = <&tcc0 3 PWM_MSEC(20)>;
label = "Green PWM LED";
};
blue_pwm_led: pwm_led_2 {
pwms = <&tcc0 1 PWM_MSEC(20)>;
label = "Blue PWM LED";
};
};
};
&cpu0 {
clock-frequency = <48000000>;
};
&sercom0 {
status = "okay";
};
&sercom2 {
status = "okay";
compatible = "atmel,sam0-uart";
current-speed = <115200>;
rxpo = <1>;
txpo = <0>;
pinctrl-0 = <&sercom2_uart_default>;
pinctrl-names = "default";
};
&sercom3 {
status = "okay";
compatible = "atmel,sam0-spi";
dipo = <1>;
dopo = <1>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&sercom3_spi_default>;
pinctrl-names = "default";
};
zephyr_udc0: &usb0 {
status = "okay";
pinctrl-0 = <&usb_dc_default>;
pinctrl-names = "default";
};
&tcc0 {
status = "okay";
compatible = "atmel,sam0-tcc-pwm";
prescaler = <4>;
#pwm-cells = <2>;
pinctrl-0 = <&pwm_default>;
pinctrl-names = "default";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "uf2";
reg = <0x00000000 DT_SIZE_K(8)>;
read-only;
};
code_partition: partition@2000 {
label = "code";
reg = <0x2000 DT_SIZE_K(256-8)>;
read-only;
};
};
};
``` | /content/code_sandbox/boards/others/serpente/serpente.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 893 |
```yaml
identifier: serpente
name: SERPENTE
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
flash: 256
ram: 32
supported:
- adc
- counter
- gpio
- hwinfo
- i2c
- pwm
- spi
- uart
- usb
- usb_device
- watchdog
``` | /content/code_sandbox/boards/others/serpente/serpente.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```unknown
config BOARD_SERPENTE
select SOC_SAMD21E18A
``` | /content/code_sandbox/boards/others/serpente/Kconfig.serpente | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 17 |
```restructuredtext
.. _neorv32:
NEORV32
#######
Overview
********
The NEORV32 is an open-source RISC-V compatible processor system intended as a
ready-to-go auxiliary processor within larger SoC designs or as a stand-alone
customizable microcontroller.
For more information about the NEORV32, see the following websites:
- `The NEORV32 RISC-V Processor GitHub`_
- `The NEORV32 RISC-V Processor Datasheet`_
- `The NEORV32 RISC-V Processor User Guide`_
The currently supported version is 1.8.6.
Supported Features
==================
The ``neorv32`` board configuration can be used a generic definition for NEORV32
based boards. Customisation to fit custom NEORV32 implementations can be done
using :ref:`devicetree overlays <use-dt-overlays>`.
Zephyr currently supports the following hardware features of the NEORV32
Processor (SoC):
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| INTC | on-chip | interrupt controller |
+-----------+------------+-------------------------------------+
| MTIME | on-chip | system timer |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio, non-interrupt |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
The default board configuration for the NEORV32 Processor (SoC) can be found in
the defconfig file: :file:`boards/riscv/neorv32/neorv32_defconfig`.
System Clock
============
The default board configuration assumes a system clock of 100 MHz. The clock
frequency can be overridden by changing the ``clock-frequency`` property of the
``cpu0`` devicetree node.
CPU
===
The default board configuration assumes the NEORV32 CPU implementation has the
following RISC-V ISA extensions enabled:
- C (Compresses Instructions)
- M (Integer Multiplication and Division)
- Zicsr (Control and Status Register (CSR) Instructions)
Internal Instruction Memory
===========================
The default board configuration assumes the NEORV32 SoC implementation has a 64k
byte internal instruction memory (IMEM) for code execution. The size of the
instruction memory can be overridden by changing the ``reg`` property of the
``imem`` devicetree node.
Internal Data Memory
====================
The default board configuration assumes the NEORV32 SoC implementation has a 32k
byte internal data memory (DMEM). The size of the data memory can be overridden
by changing the ``reg`` property of the ``dmem`` devicetree node.
Serial Port
===========
The default configuration assumes the NEORV32 SoC implements UART0 for use as
system console.
.. note::
The default configuration uses a baud rate of 19200 to match that of the
standard NEORV32 bootloader. The baudrate can be changed by modifying the
``current-speed`` property of the ``uart0`` devicetree node.
True Random-Number Generator
============================
The True Random-Number Generator (TRNG) of the NEORV32 is supported, but
disabled by default. For NEORV32 SoC implementations supporting the TRNG,
support can be enabled by setting the ``status`` property of the ``trng``
devicetree node to ``okay``.
Programming and Debugging
*************************
First, configure the FPGA with the NEORV32 bitstream as described in the NEORV32
user guide.
Next, build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Console
=====================
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 19200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing via JTAG
=================
Here is an example for building and flashing the :ref:`hello_world` application
for the NEORV32 via JTAG. Flashing via JTAG requires a NEORV32 SoC
implementation with the On-Chip Debugger (OCD) and bootloader enabled.
.. note::
If the bootloader is not enabled, the internal instruction memory (IMEM) is
configured as ROM which cannot be modified via JTAG.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: neorv32
:goals: flash
The default board configuration uses an :ref:`openocd-debug-host-tools`
configuration similar to the example provided by the NEORV32 project. Other
JTAGs can be used by providing further arguments when building. Here is an
example for using the Flyswatter JTAG:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: neorv32
:goals: flash
:gen-args: -DBOARD_RUNNER_ARGS_openocd="--config;interface/ftdi/flyswatter.cfg;--config;neorv32.cfg;--cmd-pre-init;'adapter speed 2000'"
After flashing, you should see message similar to the following in the terminal:
.. code-block:: console
*** Booting Zephyr OS build zephyr-vn.n.nn ***
Hello World! neorv32
Note, however, that the application was not persisted in flash memory by the
above steps. It was merely written to internal block RAM in the FPGA. It will
revert to the application stored in the block RAM within the FPGA bitstream
the next time the FPGA is configured.
The steps to persist the application within the FPGA bitstream are covered by
the NEORV32 user guide. If the :kconfig:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and
the NEORV32 ``image_gen`` binary is available, the build system will
automatically generate a :file:`zephyr.vhd` file suitable for initialising the
internal instruction memory of the NEORV32.
In order for the build system to automatically detect the ``image_gen`` binary
it needs to be in the :envvar:`PATH` environment variable. If not, the path
can be passed at build time:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: neorv32
:goals: build
:gen-args: -DCMAKE_PROGRAM_PATH=<path/to/neorv32/sw/image_gen/>
Uploading via UART
==================
If the :kconfig:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and the NEORV32
``image_gen`` binary is available, the build system will automatically generate
a :file:`zephyr_exe.bin` file suitable for uploading to the NEORV32 via the
built-in bootloader as described in the NEORV32 user guide.
Debugging via JTAG
==================
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: neorv32
:goals: debug
Step through the application in your debugger, and you should see a message
similar to the following in the terminal:
.. code-block:: console
*** Booting Zephyr OS build zephyr-vn.n.nn ***
Hello World! neorv32
.. _The NEORV32 RISC-V Processor GitHub:
path_to_url
.. _The NEORV32 RISC-V Processor Datasheet:
path_to_url
.. _The NEORV32 RISC-V Processor User Guide:
path_to_url
``` | /content/code_sandbox/boards/others/neorv32/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,739 |
```yaml
board:
name: serpente
vendor: solderparty
socs:
- name: samd21e18a
``` | /content/code_sandbox/boards/others/serpente/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - /soc/pinmux@41004400 & /soc/gpio@41004400
# - /soc/pinmux@41004480 & /soc/gpio@41004480
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/others/serpente/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
CONFIG_SOC_ATMEL_SAMD_OSC8M=y
CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y
CONFIG_BOOTLOADER_BOSSA=y
CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
``` | /content/code_sandbox/boards/others/serpente/serpente_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
/*
*/
#include <dt-bindings/pinctrl/samd21-da1eXabcd-pinctrl.h>
&pinctrl {
pwm_default: pwm_default {
group1 {
pinmux = <PA22F_TCC0_WO4>,
<PA19F_TCC0_WO3>,
<PA23F_TCC0_WO5>;
};
};
sercom0_i2c_default: sercom0_i2c_default {
group1 {
pinmux = <PA4D_SERCOM0_PAD0>,
<PA5D_SERCOM0_PAD1>;
};
};
sercom0_spi_default: sercom0_spi_default {
group1 {
pinmux = <PA6D_SERCOM0_PAD2>,
<PA4D_SERCOM0_PAD0>,
<PA5D_SERCOM0_PAD1>;
};
};
sercom3_spi_default: sercom3_spi_default {
group1 {
pinmux = <PA18D_SERCOM3_PAD2>,
<PA16D_SERCOM3_PAD0>,
<PA17D_SERCOM3_PAD1>;
};
};
sercom0_uart_default: sercom0_uart_default {
group1 {
pinmux = <PA5D_SERCOM0_PAD1>,
<PA4D_SERCOM0_PAD0>;
};
};
sercom2_uart_default: sercom2_uart_default {
group1 {
pinmux = <PA9D_SERCOM2_PAD1>,
<PA8D_SERCOM2_PAD0>;
};
};
usb_dc_default: usb_dc_default {
group1 {
pinmux = <PA25G_USB_DP>,
<PA24G_USB_DM>;
};
};
};
``` | /content/code_sandbox/boards/others/serpente/serpente-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 389 |
```cmake
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
board_runner_args(jlink "--device=STM32F401CC" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake)
``` | /content/code_sandbox/boards/others/stm32f401_mini/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```restructuredtext
.. _serpente:
Arturo182 Serpente
##################
Overview
********
The Serpente is a very small low-cost development and prototyping
board equipped with 4MiB flash storage, a PWM enabled RGB led and 6 I/O pins.
The board comes with 3 different USB connector options: USB Type-C plug,
USB Type-C socket and USB Type-A plug.
.. image:: img/serpente.jpg
:align: center
:alt: Serpente Boards
Hardware
********
- ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz
- 256 KiB flash memory and 32 KiB of RAM
- Extra 4MiB SPI flash memory
- RGB User LED
- Reset button
- Native USB port
Supported Features
==================
The Serpente board configuration supports the
following hardware features:
+-----------+------------+------------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+==========================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+------------------------------------------+
| Flash | on-chip | Can be used with LittleFS to store files |
+-----------+------------+------------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+------------------------------------------+
| WDT | on-chip | Watchdog |
+-----------+------------+------------------------------------------+
| GPIO | on-chip | I/O ports |
+-----------+------------+------------------------------------------+
| PWM | on-chip | Pulse Width Modulation |
+-----------+------------+------------------------------------------+
| USART | on-chip | Serial ports |
+-----------+------------+------------------------------------------+
| SPI | on-chip | Serial Peripheral Interface ports |
+-----------+------------+------------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+------------------------------------------+
Other hardware features are not currently supported by Zephyr.
The default configuration can be found in the Kconfig file
:zephyr_file:`boards/others/serpente/serpente_defconfig`.
Connections and IOs
===================
The `Serpente documentation`_ has detailed information about the board
including `pinouts`_ and the `schematic`_.
System Clock
============
The SAMD21 MCU is configured to use the 8MHz internal oscillator
with the on-chip PLL generating the 48 MHz system clock.
USB Device Port
===============
The SAMD21 MCU has a USB device port that can be used to communicate
with a host PC. See the :ref:`usb-samples` sample applications for
more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which prints "Hello World!"
to the host PC.
Programming and Debugging
=========================
The Serpente ships the BOSSA compatible UF2 bootloader. The bootloader
can be entered by quickly tapping the reset button twice.
Flashing
========
#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application:
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: serpente
:goals: build
:compact:
#. Connect the Serpente to your host computer using USB
#. Tap the reset button twice quickly to enter bootloader mode
#. Flash the image:
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: serpente
:goals: flash
:compact:
You should see the User LED blink.
References
**********
.. target-notes::
.. _Serpente documentation:
path_to_url
.. _pinouts:
path_to_url
.. _schematic:
path_to_url
``` | /content/code_sandbox/boards/others/serpente/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 829 |
```yaml
identifier: stm32f401_mini
name: STM32 Mini F401
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- counter
- spi
- usb
- i2c
- uart
- pwm
- adc
``` | /content/code_sandbox/boards/others/stm32f401_mini/stm32f401_mini.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f401Xc.dtsi>
#include <st/f4/stm32f401c(b-c)ux-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STM32 Mini F401";
compatible = "stm32f401_mini";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
user_led: led {
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
label = "User LED";
};
};
gpio_keys {
compatible = "gpio-keys";
boot1: button {
label = "BOOT1";
gpios = <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &user_led;
sw0 = &boot1;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 DT_SIZE_K(128)>;
};
slot1_partition: partition@40000 {
label = "image-1";
reg = <0x00040000 DT_SIZE_K(128)>;
};
scratch_partition: partition@60000 {
label = "image-scratch";
reg = <0x00060000 DT_SIZE_K(128)>;
};
};
};
&timers4 {
status = "okay";
pwm4: pwm {
status = "okay";
pinctrl-0 = <&tim4_ch1_pb6 &tim4_ch2_pb7>;
pinctrl-names = "default";
};
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
status = "okay";
current-speed = <115200>;
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_nss_pa4
&spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in1_pa1>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <2>;
status = "okay";
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};
&pll {
div-m = <25>;
mul-n = <336>;
div-p = <4>;
div-q = <7>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/others/stm32f401_mini/stm32f401_mini.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 993 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Clock configuration
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/others/stm32f401_mini/stm32f401_mini_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
config BOARD_STM32F401_MINI
select SOC_STM32F401XC
``` | /content/code_sandbox/boards/others/stm32f401_mini/Kconfig.stm32f401_mini | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```yaml
board:
name: stm32f401_mini
vendor: others
socs:
- name: stm32f401xc
``` | /content/code_sandbox/boards/others/stm32f401_mini/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
# STM32 Mini F401 board definitions
if BOARD_STM32F401_MINI
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_STM32F401_MINI
``` | /content/code_sandbox/boards/others/stm32f401_mini/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32f4x.cfg]
reset_config srst_only
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/others/stm32f401_mini/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```cmake
if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
set(OPENOCD OPENOCD-NOTFOUND)
endif()
find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/others/icev_wireless/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32c3-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32c3-gpio-sigmap.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_GPIO21>;
output-high;
};
group2 {
pinmux = <UART0_RX_GPIO20>;
};
};
spim2_default: spim2_default {
group1 {
pinmux = <SPIM2_MISO_GPIO4>,
<SPIM2_SCLK_GPIO5>,
<SPIM2_CSEL_GPIO6>;
};
group2 {
pinmux = <SPIM2_MOSI_GPIO7>;
output-low;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_GPIO2>,
<I2C0_SCL_GPIO8>;
/* Note: external 10k pull-ups on GPIO2 and GPIO8 */
drive-open-drain;
output-high;
};
};
};
``` | /content/code_sandbox/boards/others/icev_wireless/icev_wireless-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 278 |
```unknown
choice BOOTLOADER
default BOOTLOADER_MCUBOOT
endchoice
choice BOOT_SIGNATURE_TYPE
default BOOT_SIGNATURE_TYPE_NONE
endchoice
``` | /content/code_sandbox/boards/others/icev_wireless/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: icev_wireless
name: ICE-V Wireless
type: mcu
arch: riscv
toolchain:
- zephyr
testing:
ignore_tags:
- net
- bluetooth
vendor: espressif
``` | /content/code_sandbox/boards/others/icev_wireless/icev_wireless.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
config BOARD_ICEV_WIRELESS
select SOC_ESP32C3_MINI_N4
``` | /content/code_sandbox/boards/others/icev_wireless/Kconfig.icev_wireless | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/others/icev_wireless/icev_wireless_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```yaml
board:
name: icev_wireless
vendor: others
socs:
- name: esp32c3
``` | /content/code_sandbox/boards/others/icev_wireless/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```restructuredtext
.. _stm32f401_mini:
STM32 Mini F401
###############
Overview
********
The STM32 Mini F401 is an extremely low cost and bare-bones
development board featuring the STM32F401CC, see `STM32F401CC website`_.
More info about the board with schematics available `here <stm32-base-board-page_>`_
.. image:: img/STM32_Mini_F401-1.jpg
:align: center
:alt: STM32 Mini F401
Hardware
********
The STM32F401CC based board provides the following
hardware components:
- STM32F401CCU6 in UFQFPN48 package
- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
- 84 MHz max CPU frequency
- VDD from 1.7 V to 3.6 V
- 256 KB Flash
- 64 KB SRAM
- GPIO with external interrupt capability
- 1x12-bit, 2.4 MSPS ADC with 16 channels
- DMA Controller
- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer)
- USART/UART (3)
- I2C (3)
- SPI/I2S (4)
- SDIO
- USB 2.0 full-speed device/host/OTG controller with on-chip PHY
- CRC calculation unit
- 96-bit unique ID
- RTC
Supported Features
==================
The Zephyr stm32f401_mini board configuration supports the following
hardware features:
+------------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+============+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+------------+------------+-------------------------------------+
| SYSTICK | on-chip | system clock |
+------------+------------+-------------------------------------+
| UART | on-chip | serial port |
+------------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+------------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+------------+------------+-------------------------------------+
| FLASH | on-chip | flash |
+------------+------------+-------------------------------------+
| SPI | on-chip | spi |
+------------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+------------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+------------+------------+-------------------------------------+
| USB OTG FS | on-chip | USB device |
+------------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/others/stm32f401_mini/stm32f401_mini_defconfig`
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX : PA9/PA10
- I2C1 SCL/SDA : PB8/PB9
- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7
- PWM_4_CH1 : PB6
- PWM_4_CH2 : PB7
- ADC_1 : PA1
- SW0 : PB2 (routed to BOOT1 dip switch)
- LED0 : PC13
Clock Sources
-------------
The board has two external oscillators. The frequency of the slow clock (LSE) is
32.768 kHz. The frequency of the main clock (HSE) is 25 MHz.
The default configuration sources the system clock from the PLL, which is
derived from HSE, and is set at 84MHz.
Programming and Debugging
*************************
There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
bootloader, and another by using the SWD debug port (which requires additional
hardware). Flashing using the ROM bootloader requires a special activation
pattern, which can be triggered by using the BOOT0 pin, which on this board
is a dip switch.
Flashing
========
Installing dfu-util
-------------------
It is recommended to use at least v0.8 of `dfu-util`_. The package available in
debian/ubuntu can be quite old, so you might have to build dfu-util from source.
There is also a Windows version which works, but you may have to install the
right USB drivers with a tool like `Zadig`_.
Flashing an Application
-----------------------
Connect a USB-C cable and the board should power ON. Force the board into DFU mode
by setting the BOOT0 dip switch position to ON. Reset the board with the NRST button.
The dfu-util runner is supported on this board and so a sample can be built and
tested easily.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32f401_mini
:goals: build flash
Debugging
=========
The board can be debugged by installing the included 100 mil (0.1 inch) header,
and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO
pins on that header.
References
**********
.. target-notes::
.. _Zadig:
path_to_url
.. _stm32-base-board-page:
path_to_url
.. _dfu-util:
path_to_url
.. _STM32F401CC website:
path_to_url
``` | /content/code_sandbox/boards/others/stm32f401_mini/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,194 |
```unknown
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
``` | /content/code_sandbox/boards/others/icev_wireless/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```ini
set ESP_RTOS none
source [find interface/esp_usb_jtag.cfg]
source [find target/esp32c3.cfg]
adapter speed 5000
``` | /content/code_sandbox/boards/others/icev_wireless/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32c3/esp32c3_fx4.dtsi>
#include "icev_wireless-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "ICEV Wireless";
compatible = "espressif,esp32c3";
chosen {
zephyr,sram = &sram0;
zephyr,console = &usb_serial;
zephyr,shell-uart = &usb_serial;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,bt-hci = &esp32_bt_hci;
};
aliases {
led0 = &led_green;
i2c-0 = &i2c0;
sw0 = &user_button1;
watchdog0 = &wdt0;
};
leds {
compatible = "gpio-leds";
led_green: led_0 {
gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
label = "LED Green";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button1: button_1 {
label = "User SW1";
gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
};
};
&uart0 {
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&usb_serial {
status = "okay";
};
&i2c0 {
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
status = "okay";
};
&trng0 {
status = "okay";
};
&spi2 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&spim2_default>;
pinctrl-names = "default";
};
&gpio0 {
status = "okay";
};
&wdt0 {
status = "okay";
};
&timer0 {
status = "okay";
};
&timer1 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000F000>;
read-only;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
&esp32_bt_hci {
status = "okay";
};
``` | /content/code_sandbox/boards/others/icev_wireless/icev_wireless.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 758 |
```restructuredtext
.. _boards-holyiot:
Shenzhen Holyiot Technology Co.
###############################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/holyiot/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52832_qfaa.dtsi>
#include "holyiot_yj16019-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Holyiot YJ-16019";
compatible = "holyiot,yj-16019";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
label = "LED";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
label = "Push button switch";
zephyr,code = <INPUT_KEY_0>;
};
};
/* These aliases are provided for compatibility with samples */
aliases {
sw0 = &button0;
led0 = &led0;
watchdog0 = &wdt0;
};
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000C000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x00067000>;
};
slot1_partition: partition@73000 {
label = "image-1";
reg = <0x00073000 0x00067000>;
};
scratch_partition: partition@da000 {
label = "image-scratch";
reg = <0x000da000 0x0001e000>;
};
/*
* The flash starting at 0x000f8000 and ending at
* 0x000fffff is reserved for use by the application.
*/
/*
* Storage partition will be used by FCB/LittleFS/NVS
* if enabled.
*/
storage_partition: partition@f8000 {
label = "storage";
reg = <0x000f8000 0x00008000>;
};
};
};
``` | /content/code_sandbox/boards/holyiot/yj16019/holyiot_yj16019.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 632 |
```cmake
board_runner_args(nrfjprog "--softreset")
board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/holyiot/yj16019/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/holyiot/yj16019/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
/*
*/
&pinctrl {
pwm0_default: pwm0_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 29)>;
};
};
pwm0_sleep: pwm0_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 29)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/holyiot/yj16019/holyiot_yj16019-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```yaml
identifier: holyiot_yj16019
name: Holyiot YJ-16019
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- ble
- pwm
- watchdog
ram: 64
flash: 512
``` | /content/code_sandbox/boards/holyiot/yj16019/holyiot_yj16019.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```yaml
board:
name: holyiot_yj16019
vendor: holyiot
socs:
- name: nrf52832
``` | /content/code_sandbox/boards/holyiot/yj16019/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# 32kHz clock source
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
# Enable GPIO
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/holyiot/yj16019/holyiot_yj16019_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
# Holyiot YJ-16019 board configuration
config BOARD_HOLYIOT_YJ16019
select SOC_NRF52832_QFAA
``` | /content/code_sandbox/boards/holyiot/yj16019/Kconfig.holyiot_yj16019 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
# Holyiot YJ-16019 board configuration
if BOARD_HOLYIOT_YJ16019
config BT_CTLR
default BT
endif # BOARD_HOLYIOT_YJ16019
``` | /content/code_sandbox/boards/holyiot/yj16019/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```restructuredtext
.. _icev_wireless:
ICE-V Wireless
##############
Overview
********
The ICE-V Wireless is a combined ESP32C3 and iCE40 FPGA board.
See the `ICE-V Wireless Github Project`_ for details.
.. figure:: img/icev_wireless.jpg
:align: center
:alt: ICE-V Wireless
ICE-V Wireless
Hardware
********
This board combines an Espressif ESP32-C3-MINI-1 (which includes 4MB of flash in the module) with a
Lattice iCE40UP5k-SG48 FPGA to allow WiFi and Bluetooth control of the FPGA. ESP32 and FPGA I/O is
mostly uncommitted except for the pins used for SPI communication between ESP32 and FPGA. Several
of the ESP32C3 GPIO pins are available for additonal interfaces such as serial, ADC, I2C, etc.
For details on ESP32-C3 hardware please refer to the following resources:
* `ESP32-C3-MINI-1 Datasheet`_
* `ESP32-C3 Datasheet`_
* `ESP32-C3 Technical Reference Manual`_
For details on iCE40 hardware please refer to the following resources:
* `iCE40 UltraPlus Family Datasheet`_
Supported Features
==================
The ICE-V Wireless board configuration supports the following hardware
features:
+-----------+------------+------------------+
| Interface | Controller | Driver/Component |
+===========+============+==================+
| PMP | on-chip | arch/riscv |
+-----------+------------+------------------+
| INTMTRX | on-chip | intc_esp32c3 |
+-----------+------------+------------------+
| PINMUX | on-chip | pinctrl_esp32 |
+-----------+------------+------------------+
| USB UART | on-chip | serial_esp32_usb |
+-----------+------------+------------------+
| GPIO | on-chip | gpio_esp32 |
+-----------+------------+------------------+
| UART | on-chip | uart_esp32 |
+-----------+------------+------------------+
| I2C | on-chip | i2c_esp32 |
+-----------+------------+------------------+
| SPI | on-chip | spi_esp32_spim |
+-----------+------------+------------------+
| ADC | on-chip | |
+-----------+------------+------------------+
Other hardware features have not been enabled yet for this board.
Connections and IOs
===================
The ICE-V Wireless provides 1 row of reference, ESP32-C3, and iCE40 signals
brought out to J3, as well as 3 PMOD connectors for interfacing directly to
the iCE40 FPGA. Note that several of the iCE40 pins brought out to the PMOD
connectors are capable of operating as differential pairs.
.. figure:: img/icev_wireless_back.jpg
:align: center
:alt: ICE-V Wireless (Back)
ICE-V Wireless (Back)
The J3 pins are 4V, 3.3V, NRST, GPIO2, GPIO3, GPIO8, GPIO9, GPIO10, GPIO20,
GPIO21, FPGA_P34, and GND. Note that GPIO2 and GPIO3 may be configured for
ADC operation.
For PMOD details, please refer to the `PMOD Specification`_ and the image
below.
.. figure:: img/icev_wireless_pinout.jpg
:align: center
:alt: ICE-V Wireless Pinout
Programming and Debugging
*************************
Programming and debugging for the ICE-V Wireless ESP32-C3 target is
incredibly easy following the steps below.
Building and Flashing
*********************
Simple boot
===========
The board could be loaded using the single binary image, without 2nd stage bootloader.
It is the default option when building the application without additional configuration.
.. note::
Simple boot does not provide any security features nor OTA updates.
MCUboot bootloader
==================
User may choose to use MCUboot bootloader instead. In that case the bootloader
must be build (and flash) at least once.
There are two options to be used when building an application:
1. Sysbuild
2. Manual build
.. note::
User can select the MCUboot bootloader by adding the following line
to the board default configuration file.
.. code:: cfg
CONFIG_BOOTLOADER_MCUBOOT=y
Sysbuild
========
The sysbuild makes possible to build and flash all necessary images needed to
bootstrap the board with the ESP32 SoC.
To build the sample application using sysbuild use the command:
.. zephyr-app-commands::
:tool: west
:app: samples/hello_world
:board: icev_wireless
:goals: build
:west-args: --sysbuild
:compact:
By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
images. But it can be configured to create other kind of images.
Build directory structure created by sysbuild is different from traditional
Zephyr build. Output is structured by the domain subdirectories:
.. code-block::
build/
hello_world
zephyr
zephyr.elf
zephyr.bin
mcuboot
zephyr
zephyr.elf
zephyr.bin
domains.yaml
.. note::
With ``--sysbuild`` option the bootloader will be re-build and re-flash
every time the pristine build is used.
For more information about the system build please read the :ref:`sysbuild` documentation.
Manual build
============
During the development cycle, it is intended to build & flash as quickly possible.
For that reason, images can be build one at a time using traditional build.
The instructions following are relevant for both manual build and sysbuild.
The only difference is the structure of the build directory.
.. note::
Remember that bootloader (MCUboot) needs to be flash at least once.
For the :code:`Hello, world!` application, follow the instructions below.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: icev_wireless
:goals: build flash
Open the serial monitor using the following command:
.. code-block:: console
$ west espressif monitor
After the board has automatically reset and booted, you should see the following
message in the monitor:
.. code-block:: console
***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! icev_wireless
Debugging
*********
As with much custom hardware, the ESP32C3 modules require patches to
OpenOCD that are not upstreamed. Espressif maintains their own fork of
the project. The custom OpenOCD can be obtained by running the following extension:
.. code-block:: console
west espressif install
.. note::
By default, the OpenOCD will be downloaded and installed under $HOME/.espressif/tools/zephyr directory
(%USERPROFILE%/.espressif/tools/zephyr on Windows).
The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
parameter when building.
Here is an example for building the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: icev_wireless
:goals: build flash
:gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: icev_wireless
:maybe-skip-config:
:goals: debug
References
**********
.. _ICE-V Wireless Github Project:
path_to_url
.. _ESP32-C3-MINI-1 Datasheet:
path_to_url
.. _ESP32-C3 Datasheet:
path_to_url
.. _ESP32-C3 Technical Reference Manual:
path_to_url
.. _iCE40 UltraPlus Family Datasheet:
path_to_url
.. _PMOD Specification:
path_to_url
``` | /content/code_sandbox/boards/others/icev_wireless/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,857 |
```restructuredtext
.. _boards-renesas:
Renesas Electronics Corporation
###############################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/renesas/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
/*
*/
/dts-v1/;
#include <renesas/ra/ra6/r7fa6m3ah3cfc.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include "ek_ra6m3-pinctrl.dtsi"
/ {
model = "Renesas EK-RA6M3";
compatible = "renesas,ra6m3", "renesas,ra";
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart8;
zephyr,shell-uart = &uart8;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
led1: led1 {
gpios = <&ioport4 3 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
led2: led2 {
gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>;
label = "LED2";
};
led3: led3 {
gpios = <&ioport1 0 GPIO_ACTIVE_HIGH>;
label = "LED3";
};
};
aliases {
led0 = &led1;
};
};
&ioport1 {
status = "okay";
};
&ioport4 {
status = "okay";
};
&sci8 {
pinctrl-0 = <&sci8_default>;
pinctrl-names = "default";
status = "okay";
uart8: uart {
current-speed = <115200>;
status = "okay";
};
};
&xtal {
clock-frequency = <DT_FREQ_M(24)>;
mosel = <0>;
#clock-cells = <0>;
status = "okay";
};
&subclk {
status = "okay";
};
&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "okay";
};
``` | /content/code_sandbox/boards/renesas/ek_ra6m3/ek_ra6m3.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 429 |
```cmake
board_runner_args(jlink "--device=R7FA6M3AH")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/renesas/ek_ra6m3/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*/
&pinctrl {
sci8_default: sci8_default {
group1 {
/* tx rx */
psels = <RA_PSEL(RA_PSEL_SCI_8, 1, 5)>,
<RA_PSEL(RA_PSEL_SCI_8, 1, 4)>;
};
};
};
``` | /content/code_sandbox/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```restructuredtext
.. _holyiot_yj16019:
Holyiot YJ-16019
################
Overview
********
The `Holyiot`_ YJ-16019 hardware provides support for the Nordic
Semiconductor nRF52832 ARM Cortex-M4 CPU and the following devices:
* CLOCK
* FLASH
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`MPU (Memory Protection Unit)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`PWM (Pulse Width Modulation)`
* RADIO (Bluetooth Low Energy)
* :abbr:`RTC (nRF RTC System Clock)`
* Segger RTT (RTT Console)
* :abbr:`WDT (Watchdog Timer)`
.. figure:: img/holyiot_yj16019_front.jpg
:align: center
:alt: Holyiot YJ-16019
Holyiot YJ-16019 (Credit: Holyiot)
The board is equipped with one LED, one push button, and is powered by
a CR2032 coin cell. The `Nordic Semiconductor Infocenter`_
contains the processor's information and the datasheet.
Hardware
********
The nRF52832 of the Holyiot YJ-16019 is clocked by an external crystal with a frequency of 32 MHz
(Y1). The 32.768 kHz crystal (Y2) shown on the board schematics is not mounted.
Supported Features
==================
The holyiot_yj16019 board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| CLOCK | on-chip | clock_control |
+-----------+------------+----------------------+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
| RADIO | on-chip | Bluetooth |
+-----------+------------+----------------------+
| RTC | on-chip | system clock |
+-----------+------------+----------------------+
| RTT | Segger | console |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
Connections and IOs
===================
LED and push button
-------------------
* Push button = P0.28
* LED = P0.29
Programming and Debugging
*************************
Applications for the ``holyiot_yj16019`` board configuration can be
built and flashed in the usual way (see :ref:`build_an_application`
and :ref:`application_run` for more details); however, an external
Segger J-Link is required since the board does not have any on-board
debug IC.
The following pins of the Segger J-Link must be connected to the following test
pads on the PCB (see image):
* VTref = VCC
* GND = GND
* SWDIO = SDO
* SWCLK = SCK
.. figure:: img/holyiot_yj16019_pcb.jpg
:align: center
:alt: Holyiot YJ-16019 PCB
Holyiot YJ-16019 PCB (Credit: Holyiot)
Flashing
========
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`. Then build and flash
applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: holyiot_yj16019
:goals: build flash
Debugging
=========
Refer to the :ref:`nordic_segger` page to learn about debugging Nordic
nRF52x-based boards with a Segger debugger.
Testing the LED and button on the Holyiot YJ-16019
**************************************************
There are 2 samples that allow you to test that the button and LED on
the board are working properly with Zephyr:
.. code-block:: console
samples/basic/blinky
samples/basic/button
You can build and flash the examples to make sure Zephyr is running
correctly on your board. The button and LED definitions can be found
in :zephyr_file:`boards/holyiot/yj16019/holyiot_yj16019.dts`.
References
**********
.. target-notes::
.. _Holyiot: path_to_url
.. _Nordic Semiconductor Infocenter: path_to_url
``` | /content/code_sandbox/boards/holyiot/yj16019/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,097 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_PINCTRL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```yaml
board:
name: ek_ra6m3
vendor: renesas
socs:
- name: r7fa6m3ah3cfc
``` | /content/code_sandbox/boards/renesas/ek_ra6m3/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
config BOARD_EK_RA6M3
select SOC_R7FA6M3AH3CFC
``` | /content/code_sandbox/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```yaml
identifier: ek_ra6m3
name: Renesas EK-RA6M3
type: mcu
arch: arm
ram: 640
flash: 2048
toolchain:
- zephyr
- gnuarmemb
supported:
- gpio
``` | /content/code_sandbox/boards/renesas/ek_ra6m3/ek_ra6m3.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```restructuredtext
.. _ek_ra6m3:
RA6M3 Evaluation Kit
####################
Overview
********
The Renesas RA6M3 group uses the high-performance Arm Cortex-M4 core and
offers a TFT controller with 2D accelerator and JPEG decoder. The RA6M3 is
suitable for IoT applications requiring TFT, Ethernet, security, large
embedded RAM, and USB High Speed (HS).
The key features of the EK-RA6M3 board are categorized in three groups as follow:
**MCU Native Pin Access**
- 120MHz Arm Cortex-M4 based RA6M3 MCU in 176 pins, LQFP package
- Native pin access through 4 x 40-pin male headers
- MCU and USB current measurement points for precision current consumption measurement
- Multiple clock sources - RA6M3 MCU oscillator and sub-clock oscillator crystals,
providing precision 24.000 MHz and 32,768 Hz reference clock.
Additional low precision clocks are avaialbe internal to the RA6M3 MCU
**System Control and Ecosystem Access**
- USB Full Speed Host and Device (micro AB connector)
- Four 5V input sources
- USB (Debug, Full Speed, High Speed)
- External power supply (using surface mount clamp test points and power input vias)
- Three Debug modes
- Debug on-board (SWD)
- Debug in (ETM, SWD and JTAG)
- Debug out (SWD)
- User LEDs and buttons
- Three User LEDs (red, blue, green)
- Power LED (white) indicating availability of regulated power
- Debug LED (yellow) indicating the debug connection
- Two User buttons
- One Reset button
- Four most popular ecosystems expansions
- Two Seeed Grove system (I2C) connectors
- Two Digilent Pmod (SPI and UART) connectors
- Arduino (Uno R3) connector
- MikroElektronika mikroBUS connector
- MCU boot configuration jumper
**Special Feature Access**
- Ethernet (RJ45 RMII interface)
- USB High Speed Host and Device (micro-AB connector)
- 32 Mb (256 Mb) External Quad-SPI Flash
.. figure:: ek-ra6m3-board.webp
:align: center
:alt: RA6M3 Evaluation Kit
EK-RA6M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
Hardware
********
Detailed hardware feature for the RA6M3 MCU group can be found at `RA6M3 Group User's Manual Hardware`_
.. figure:: ra6m3-block-diagram.webp
:width: 442px
:align: center
:alt: RA6M3 MCU group feature
RA6M3 Block diagram (Credit: Renesas Electronics Corporation)
Detail hardware feature for the EK-RA6M3 MCU can be found at `EK-RA6M3 - User's Manual`_
Supported Features
==================
The below features are currently supported on Zephyr OS for EK-RA6M3 board:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.
Programming and Debugging
*************************
Applications for the ``ek_ra6m3`` board target configuration can be
built, flashed, and debugged in the usual way. See
:ref:`build_an_application` and :ref:`application_run` for more details on
building and running.
Flashing
========
Program can be flashed to EK-RA6M3 via the on-board SEGGER J-Link debugger.
SEGGER J-link's drivers are avaialbe at path_to_url
To flash the program to board
1. Connect to J-Link OB via USB port to host PC
2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M3 - User's Manual`_
3. Execute west command
.. code-block:: console
west flash -r jlink
Debugging
=========
You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
Once downloaded and installed, open Segger Ozone and configure the debug project
like so:
* Target Device: R7FA6M3AH
* Target Interface: SWD
* Target Interface Speed: 4 MHz
* Host Interface: USB
* Program File: <path/to/your/build/zephyr.elf>
**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
version of Segger Ozone
References
**********
- `EK-RA6M3 Website`_
- `RA6M3 MCU group Website`_
.. _EK-RA6M3 Website:
path_to_url
.. _RA6M3 MCU group Website:
path_to_url
.. _EK-RA6M3 - User's Manual:
path_to_url
.. _RA6M3 Group User's Manual Hardware:
path_to_url
.. _Segger Ozone Download:
path_to_url#Ozone
``` | /content/code_sandbox/boards/renesas/ek_ra6m3/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,220 |
```cmake
#
#
#
board_runner_args(ezflashcli)
board_runner_args(jlink --device=DA14699)
include(${ZEPHYR_BASE}/boards/common/ezflashcli.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
/*
*/
/dts-v1/;
#include <renesas/smartbond/da14699.dtsi>
#include "da1469x_dk_pro-pinctrl.dtsi"
/ {
model = "DA1469x series Development Kit Pro";
compatible = "renesas,da1469x_dk_pro";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart;
zephyr,shell-uart = &uart;
zephyr,code-partition = &slot0_partition;
zephyr,bt-hci = &bt_hci_da1469x;
};
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map =
<0 0 &gpio1 9 0>, /* A0 */
<1 0 &gpio0 25 0>, /* A1 */
<2 0 &gpio0 8 0>, /* A2 */
<3 0 &gpio0 9 0>, /* A3 */
<4 0 &gpio1 13 0>, /* A4 */
<5 0 &gpio1 12 0>, /* A5 */
<6 0 &gpio1 2 0>, /* D0 */
<7 0 &gpio1 3 0>, /* D1 */
<8 0 &gpio1 4 0>, /* D2 */
<9 0 &gpio1 5 0>, /* D3 */
<10 0 &gpio1 7 0>, /* D4 */
<11 0 &gpio1 8 0>, /* D5 */
<12 0 &gpio0 17 0>, /* D6 */
<13 0 &gpio0 18 0>, /* D7 */
<14 0 &gpio0 19 0>, /* D8 */
<15 0 &gpio0 20 0>, /* D9 */
<16 0 &gpio0 21 0>, /* D10 */
<17 0 &gpio0 24 0>, /* D11 */
<18 0 &gpio0 26 0>, /* D12 */
<19 0 &gpio0 27 0>, /* D13 */
<20 0 &gpio0 28 0>, /* D14 */
<21 0 &gpio0 29 0>; /* D15 */
};
aliases {
led0 = &red_led;
watchdog0 = &wdog;
};
sysclk: system-clock {
compatible = "fixed-clock";
clock-frequency = <32000000>;
#clock-cells = <0>;
};
};
&flash0 {
reg = <0x16000000 DT_SIZE_M(1)>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* Flash area from 0x0000 to 0x2400 is reserved
* for product header added by flasher.
*/
boot_partition: partition@2400 {
label = "mcuboot";
reg = <0x000002400 0x00009c00>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000c000 0x00076000>;
};
slot1_partition: partition@80000 {
label = "image-1";
reg = <0x00082000 0x00076000>;
};
storage_partition: partition@f8000 {
label = "storage";
reg = <0x000f8000 0x00008000>;
};
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart {
current-speed = <115200>;
status = "okay";
pinctrl-0 = <&uart_default>;
pinctrl-names = "default";
rx-wake-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
};
zephyr_udc0: &usbd {
compatible = "renesas,smartbond-usbd";
status = "okay";
};
&rc32m {
status = "disabled";
};
&xtal32m {
status = "okay";
};
&xtal32k {
status = "okay";
};
/*
* On board level we switch to XTAL32K and
* so RCX can be disabled.
*/
&rcx {
status = "disabled";
};
&lp_clk {
clock-src = <&xtal32k>;
};
&sys_clk {
clock-src = <&xtal32m>;
};
&i2c {
pinctrl-0 = <&i2c_default>;
pinctrl-1 = <&i2c_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c2 {
pinctrl-0 = <&i2c2_default>;
pinctrl-1 = <&i2c2_sleep>;
pinctrl-names = "default", "sleep";
};
&spi {
pinctrl-0 = <&spi_controller>;
pinctrl-1 = <&spi_sleep>;
pinctrl-names = "default", "sleep";
};
&spi2 {
pinctrl-0 = <&spi2_controller>;
pinctrl-1 = <&spi2_sleep>;
pinctrl-names = "default", "sleep";
};
&bt_hci_da1469x {
status = "okay";
};
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,389 |
```yaml
identifier: da1469x_dk_pro
name: DA1469X_DK_PRO
type: mcu
arch: arm
ram: 512
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- counter
- gpio
- hwinfo
- watchdog
- i2c
- spi
- usb_device
- rtc
- crypto
- dma
- mipi_dbi
- display
- memc
vendor: renesas
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```unknown
# DA1469x series Development Kit Pro board configuration
config BOARD_DA1469X_DK_PRO
select SOC_DA14699
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/Kconfig.da1469x_dk_pro | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```unknown
CONFIG_HW_STACK_PROTECTION=y
CONFIG_GPIO=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_BUILD_OUTPUT_HEX=n
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
board:
name: da1469x_dk_pro
vendor: renesas
socs:
- name: da14699
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
# DA1469x series Development Kit Pro board configuration
if BOARD_DA1469X_DK_PRO
config I2C_CALLBACK
default y if I2C_SMARTBOND
if LVGL
config LV_Z_BITS_PER_PIXEL
default 16
# LCDC imposes display buffer's stride be word aligned
config LV_Z_AREA_X_ALIGNMENT_WIDTH
default 2 if MIPI_DBI_SMARTBOND
config LV_Z_FLUSH_THREAD
default y if DISPLAY_RENESAS_LCDC
# Use double buffering to avoid visual artifacts as long as
# the DMA is copying data into driver's frame buffer.
config LV_Z_DOUBLE_VDB
default y if DISPLAY_RENESAS_LCDC
endif # LVGL
if INPUT
config INPUT_FT5336_INTERRUPT
default y
config LV_Z_POINTER_INPUT_MSGQ_COUNT
default 70
endif # INPUT
if PM || PM_DEVICE || PM_DEVICE_RUNTIME
# Increase stack size to avoid raising usage-fault
# exceptions due to stack overflow.
config IDLE_STACK_SIZE
default 2048
# Make sure the serial device has higher
# initialization priority.
config SERIAL_INIT_PRIORITY
default KERNEL_INIT_PRIORITY_DEFAULT
endif # PM || PM_DEVICE
if BT
config BT_WAIT_NOP
default y
config TEST_RANDOM_GENERATOR
default y
endif # BT
endif # BOARD_DA1469X_DK_PRO
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 285 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/display/ili9xxx.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
/ {
chosen {
zephyr,display = &ili9340;
};
lvgl_pointer {
input = <&display_touch>;
status = "okay";
swap-xy;
invert-x;
invert-y;
};
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
display_touch: ft6206@38 {
compatible = "focaltech,ft5336";
status = "okay";
reg = <0x38>;
int-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
};
};
&lcdc {
compatible = "renesas,smartbond-mipi-dbi";
status = "okay";
reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&mipi_dbi_default>;
pinctrl-1 = <&mipi_dbi_read>;
pinctrl-2 = <&mipi_dbi_sleep>;
pinctrl-names = "default", "read", "sleep";
#address-cells = <1>;
#size-cells = <0>;
ili9340: ili9340@0 {
compatible = "ilitek,ili9340";
mipi-max-frequency = <48000000>;
status = "okay";
reg = <0>;
width = <240>;
height = <320>;
pixel-format = <ILI9XXX_PIXEL_FORMAT_RGB565>;
rotation = <0>;
};
};
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 358 |
```unknown
/*
*/
#include <zephyr/dt-bindings/pinctrl/smartbond-pinctrl.h>
&pinctrl {
uart_default: uart_default {
group1 {
pinmux = <SMARTBOND_PINMUX(UART_TX, 0, 9)>;
};
group2 {
pinmux = <SMARTBOND_PINMUX(UART_RX, 0, 8)>;
bias-pull-up;
};
};
i2c_default: i2c_default {
group1 {
pinmux = <SMARTBOND_PINMUX(I2C_SDA, 0, 31)>,
<SMARTBOND_PINMUX(I2C_SCL, 0, 30)>;
bias-pull-up;
};
};
/omit-if-no-ref/ i2c_sleep: i2c_sleep {
group1 {
pinmux = <SMARTBOND_PINMUX(GPIO, 0, 31)>,
<SMARTBOND_PINMUX(GPIO, 0, 30)>;
bias-pull-up;
};
};
i2c2_default: i2c2_default {
group1 {
pinmux = <SMARTBOND_PINMUX(I2C2_SDA, 0, 28)>,
<SMARTBOND_PINMUX(I2C2_SCL, 0, 29)>;
bias-pull-up;
};
};
/omit-if-no-ref/ i2c2_sleep: i2c2_sleep {
group1 {
pinmux = <SMARTBOND_PINMUX(GPIO, 0, 28)>,
<SMARTBOND_PINMUX(GPIO, 0, 29)>;
bias-pull-up;
};
};
display_controller_default: display_controller_default {
group1 {
pinmux = <SMARTBOND_PINMUX(LCD, 1, 2)>,
<SMARTBOND_PINMUX(LCD, 1, 3)>,
<SMARTBOND_PINMUX(LCD, 1, 4)>,
<SMARTBOND_PINMUX(LCD, 1, 5)>,
<SMARTBOND_PINMUX(LCD, 1, 7)>,
<SMARTBOND_PINMUX(LCD, 1, 8)>,
<SMARTBOND_PINMUX(LCD, 0, 27)>,
<SMARTBOND_PINMUX(LCD, 0, 28)>,
<SMARTBOND_PINMUX(LCD, 0, 29)>,
<SMARTBOND_PINMUX(LCD, 0, 30)>;
};
};
/omit-if-no-ref/ display_controller_sleep: display_controller_sleep {
group1 {
pinmux = <SMARTBOND_PINMUX(GPIO, 1, 2)>,
<SMARTBOND_PINMUX(GPIO, 1, 3)>,
<SMARTBOND_PINMUX(GPIO, 1, 4)>,
<SMARTBOND_PINMUX(GPIO, 1, 5)>,
<SMARTBOND_PINMUX(GPIO, 1, 7)>,
<SMARTBOND_PINMUX(GPIO, 1, 8)>,
<SMARTBOND_PINMUX(GPIO, 0, 27)>,
<SMARTBOND_PINMUX(GPIO, 0, 28)>,
<SMARTBOND_PINMUX(GPIO, 0, 29)>,
<SMARTBOND_PINMUX(GPIO, 0, 30)>;
};
};
/omit-if-no-ref/ spi_sleep: spi_sleep {
group1 {
pinmux = <SMARTBOND_PINMUX(GPIO, 0, 21)>,
<SMARTBOND_PINMUX(GPIO, 0, 24)>,
<SMARTBOND_PINMUX(GPIO, 0, 26)>;
};
};
spi_controller: spi_controller {
group1 {
pinmux = <SMARTBOND_PINMUX(SPI_CLK, 0, 21)>,
<SMARTBOND_PINMUX(SPI_DO, 0, 26)>;
output-enable;
};
group2 {
pinmux = <SMARTBOND_PINMUX(SPI_DI, 0, 24)>;
input-enable;
};
};
/omit-if-no-ref/ spi2_sleep: spi2_sleep {
group1 {
pinmux = <SMARTBOND_PINMUX(GPIO, 1, 3)>,
<SMARTBOND_PINMUX(GPIO, 1, 4)>,
<SMARTBOND_PINMUX(GPIO, 1, 5)>;
};
};
spi2_controller: spi2_controller {
group1 {
pinmux = < SMARTBOND_PINMUX(SPI2_CLK, 1, 3) >,
<SMARTBOND_PINMUX(SPI2_DO, 1, 5)>;
output-enable;
};
group2 {
pinmux = <SMARTBOND_PINMUX(SPI2_DI, 1, 4)>;
input-enable;
};
};
/omit-if-no-ref/ mipi_dbi_default: mipi_dbi_default {
group1 {
pinmux = <SMARTBOND_PINMUX(LCD_SPI_DC, 0, 20)>,
<SMARTBOND_PINMUX(LCD_SPI_EN, 0, 21)>,
<SMARTBOND_PINMUX(LCD_SPI_DO, 0, 24)>,
<SMARTBOND_PINMUX(LCD_SPI_CLK, 0, 27)>;
};
group2 {
/* TE signal - mapped on fixed positions */
pinmux = <SMARTBOND_PINMUX(LCD, 1, 22)>;
};
};
/omit-if-no-ref/ mipi_dbi_sleep: mipi_dbi_sleep {
group1 {
pinmux = <SMARTBOND_PINMUX(GPIO, 0, 20)>,
<SMARTBOND_PINMUX(GPIO, 0, 21)>,
<SMARTBOND_PINMUX(GPIO, 0, 24)>,
<SMARTBOND_PINMUX(GPIO, 0, 27)>;
output-enable;
};
group2 {
pinmux = <SMARTBOND_PINMUX(GPIO, 1, 22)>;
input-enable;
};
};
/* Same signal can be multiplexed to multiple I/O pins */
/omit-if-no-ref/ mipi_dbi_read: mipi_dbi_read {
group1 {
pinmux = <SMARTBOND_PINMUX(SPI2_CLK, 0, 27)>;
output-enable;
};
group2 {
pinmux = <SMARTBOND_PINMUX(SPI2_DI, 0, 26)>;
input-enable;
};
};
};
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,516 |
```unknown
/*
*
*/
/ {
aliases {
sram-ext = &memc;
};
};
&psram {
status = "okay";
};
/* QSPIC settings for the APS6404L-3SQR QSPI PSRAM memory in QPI mode. */
&memc {
status = "okay";
is-ram;
dev-size = <DT_SIZE_M(64)>;
dev-type = <0x5D>;
dev-id = <0x0D>;
dev-density = <0xE040>;
reset-delay-us = <50>;
read-cs-idle-min-ns = <18>;
tcem-max-us = <2>;
enter-qpi-mode;
enter-qpi-cmd = <0x35>;
extra-byte-enable;
extra-byte = <0x0>;
dummy-bytes-count = "dummy-bytes-count2";
read-cmd = <0xEB>;
write-cmd = <0x38>;
rx-inst-mode = "quad-spi";
rx-addr-mode = "quad-spi";
rx-data-mode = "quad-spi";
rx-dummy-mode = "quad-spi";
rx-extra-mode = "quad-spi";
tx-inst-mode = "quad-spi";
tx-addr-mode = "quad-spi";
tx-data-mode = "quad-spi";
};
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_psram.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 277 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/display/panel.h>
/ {
chosen {
zephyr,display = &lcdc;
};
lvgl_pointer {
input = <&display_touch>;
status = "okay";
swap-xy;
};
};
&pinctrl {
i2c2_default: i2c2_default {
group1 {
pinmux = <SMARTBOND_PINMUX(I2C2_SDA, 0, 19)>,
<SMARTBOND_PINMUX(I2C2_SCL, 0, 18)>;
bias-pull-up;
};
};
i2c2_sleep: i2c2_sleep {
group1 {
pinmux = <SMARTBOND_PINMUX(GPIO, 0, 19)>,
<SMARTBOND_PINMUX(GPIO, 0, 18)>;
bias-pull-up;
};
};
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
display_touch: ft6206@38 {
compatible = "focaltech,ft5336";
status = "okay";
reg = <0x38>;
int-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
};
};
&lcdc {
status = "okay";
pinctrl-0 = <&display_controller_default>;
pinctrl-1 = <&display_controller_sleep>;
pinctrl-names = "default", "sleep";
width = <480>;
height = <272>;
disp-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
/*
* Panel settings for the NHD-4.3-480272EF-ASXP-CTP
* display panel model which integrates the SC7283
* driver IC.
*/
display-timings {
compatible = "zephyr,panel-timing";
hsync-len = <2>;
hfront-porch = <2>;
hback-porch = <3>;
vsync-len = <2>;
vfront-porch = <2>;
vback-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
clock-frequency = <12000000>;
};
};
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 532 |
```cmake
board_runner_args(jlink "--device=R7FA6E10F")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/renesas/fpb_ra6e1/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```yaml
identifier: fpb_ra6e1
name: Renesas FPB-RA6E1
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
supported:
- gpio
``` | /content/code_sandbox/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
/*
*/
&pinctrl {
sci0_default: sci0_default {
group1 {
/* tx rx */
psels = <RA_PSEL(RA_PSEL_SCI_0, 1, 1)>,
<RA_PSEL(RA_PSEL_SCI_0, 1, 0)>;
};
};
};
``` | /content/code_sandbox/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
config BOARD_FPB_RA6E1
select SOC_R7FA6E10F2CFP
``` | /content/code_sandbox/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```yaml
board:
name: fpb_ra6e1
vendor: renesas
socs:
- name: r7fa6e10f2cfp
``` | /content/code_sandbox/boards/renesas/fpb_ra6e1/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```restructuredtext
.. _da1469x_dk_pro:
DA1469x Development Kit Pro
###########################
Overview
********
The DA1469x Development Kit Pro hardware provides support for the Renesas
DA1469x ARM Cortex-M33 MCU family. The development kit consist of a motherboard
with connectors and integrated debugger and an interchangeable daughterboard
with an actual MCU (e.g. DA14695 or DA14699).
.. figure:: da14695-00hqdevkt-board.jpg
:width: 442px
:align: center
:alt: DA14695 Development Kit Pro
DA14695 Development Kit Pro (Credit: Renesas Electronics Corporation)
Hardware
********
DA1469x Development Kit Pro has two external oscillators. The frequency of
the sleep clock is 32768 Hz. The frequency of the system clock is 32 MHz.
Supported Features
==================
The _da1469x_dk_pro board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| RTT | Segger | console |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features, including the Configurable MAC (CMAC) controller,
are currently not supported by the port.
For more information about the DA14695 Development Kit see:
- `DA14695 DK website`_
- `DA14699 daughterboard website`_
System Clock
============
The DA1469x Development Kit Pro is configured to use the 32 MHz external oscillator
on the board.
Connections and IOs
===================
The DA1469x Development Kit Pro has one LED and one push button which can be used
by applications. The UART is connected to on-board serial converter and accessible
via USB1 port on motherboard.
The pin connections are as follows:
* LED (red), located on daughterboard = P1.01
* BUTTON, located on motherboard = P0.06
* UART RX, via USB1 on motherboard = P0.08
* UART TX, via USB1 on motherboard = P0.09
Programming and Debugging
*************************
Applications for the ``da1469x_dk_pro`` board configuration can be
built, flashed, and debugged in the usual way. See
:ref:`build_an_application` and :ref:`application_run` for more details on
building and running.
Flashing
========
The DA1469x boots from an external flash connected to QSPI interface. The image
written to flash has to have proper header prepended. The process is simplified
by using dedicated `eZFlashCLI`_ tool that takes care of writing header and can
handle different types of flash chips connected to DA1469x MCU. Follow instructions
on `ezFlashCLI`_ to install the tool. Once installed, flashing can be done in the
usual way.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: da1469x_dk_pro
:goals: build flash
Debugging
=========
The DA1469x Development Kit Pro includes a `J-Link`_ adaptor built-in on
motherboard which provides both debugging interface and serial port.
Application can be debugged in the usual way once DA1469x Development Kit Pro
is connected to PC via USB port on motherboard.
References
**********
.. target-notes::
.. _DA14695 DK website: path_to_url
.. _DA14699 daughterboard website: path_to_url
.. _DA1469x Datasheet: path_to_url
.. _J-Link: path_to_url
.. _ezFlashCLI: path_to_url
``` | /content/code_sandbox/boards/renesas/da1469x_dk_pro/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 906 |
```unknown
/*
*/
/dts-v1/;
#include <renesas/ra/ra6/r7fa6e10f2cfp.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include "fpb_ra6e1-pinctrl.dtsi"
/ {
model = "Renesas FPB-RA6E1";
compatible = "renesas,ra6e1", "renesas,ra";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
leds {
compatible = "gpio-leds";
led1: led1 {
gpios = <&ioport4 7 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
led2: led2 {
gpios = <&ioport4 8 GPIO_ACTIVE_HIGH>;
label = "LED2";
};
};
aliases {
led0 = &led1;
};
};
&sci0 {
pinctrl-0 = <&sci0_default>;
pinctrl-names = "default";
status = "okay";
uart0: uart {
current-speed = <115200>;
status = "okay";
};
};
&ioport4 {
status = "okay";
};
&subclk {
status = "okay";
};
&pll {
source = <RA_PLL_SOURCE_HOCO>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "application";
reg = <0x00000000 DT_SIZE_K(512)>;
};
storage_partition: partition@80000 {
label = "storage";
reg = <0x80000 DT_SIZE_K(512)>;
};
};
};
``` | /content/code_sandbox/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 457 |
```cmake
board_runner_args(jlink "--device=R7FA6E2BB")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/renesas/fpb_ra6e2/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
config BOARD_FPB_RA6E2
select SOC_R7FA6E2BB3CFM
``` | /content/code_sandbox/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_PINCTRL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```yaml
identifier: fpb_ra6e2
name: Renesas FPB-RA6E2
type: mcu
arch: arm
ram: 40
flash: 256
toolchain:
- zephyr
- gnuarmemb
supported:
- gpio
``` | /content/code_sandbox/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
/*
*/
&pinctrl {
sci0_default: sci0_default {
group1 {
/* tx rx */
psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 11)>,
<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
};
};
};
``` | /content/code_sandbox/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```restructuredtext
.. _fpb_ra6e1:
RA6E1 Fast Prototyping Board
############################
Overview
********
The Renesas RA6E1 group uses the high-performance Arm Cortex-M33 core with
TrustZone. The RA6E1 is suitable for entry IoT applications requiring streamlined
feature and connectivity integration including Ethernet, and unprecedented performance
with 790.75 CoreMark, which are 3.95CoreMark / Mhz.
The key features of the FPB-RA6E1 board are categorized in three groups as follow:
**MCU Native Pin Access**
- 200MHz Arm Cortex-M33 based RA6E1 MCU in 100 pins, LQFP package
- Native pin access through 2 x 50-pin male headers (not fitted)
- MCU current measurement point for precision current consumption measurement
- Multiple clock sources - Low-precision (~1%) clocks are available internal to
the RA MCU. RA MCU oscillator and sub-clock oscillator crystals, providing
precision 24.000 MHz (not fitted) and 32,768 Hz reference clocks are also available
**System Control and Ecosystem Access**
- Two 5V input sources
- USB (Debug, Full Speed, High Speed)
- External power supply (using 2-pin header) (not fitted)
- Built-in SEGGER J-Link Emulator On-Board programmer/debugger (SWD)
- User LEDs and buttons
- Two User LEDs (green)
- Power LED (green) (not fitted) indicating availability of regulated power
- Debug/power LED (yellow) indicating power and the debug connection
- One User button
- One Reset button
- Two popular ecosystems expansions
- Two Digilent PmodTM (SPI, UART) connectors (not fitted)
- Arduino (Uno R3) connector
- MCU boot configuration jumper
.. figure:: fpb-ra6e1-board.webp
:align: center
:alt: RA6E1 Evaluation Kit
FPB-RA6E1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
Hardware
********
Detailed hardware feature for the RA6E1 MCU group can be found at `RA6E1 Group User's Manual Hardware`_
.. figure:: ra6e1-block-diagram.webp
:width: 442px
:align: center
:alt: RA6E1 MCU group feature
RA6E1 Block diagram (Credit: Renesas Electronics Corporation)
Detailed hardware feature for the FPB-RA6E1 MCU can be found at `FPB-RA6E1 - User's Manual`_
Supported Features
==================
The below features are currently supported on Zephyr OS for FPB-RA6E1 board:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.
Programming and Debugging
*************************
Applications for the ``fpb_ra6e1`` board target configuration can be
built, flashed, and debugged in the usual way. See
:ref:`build_an_application` and :ref:`application_run` for more details on
building and running.
Flashing
========
Program can be flashed to FPB-RA6E1 via the on-board SEGGER J-Link debugger.
SEGGER J-link's drivers are avaialbe at path_to_url
To flash the program to board
1. Connect to J-Link OB via USB port to host PC
2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E1 - User's Manual`_
3. Execute west command
.. code-block:: console
west flash -r jlink
Debugging
=========
You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
Once downloaded and installed, open Segger Ozone and configure the debug project
like so:
* Target Device: R7FA6E10F
* Target Interface: SWD
* Target Interface Speed: 4 MHz
* Host Interface: USB
* Program File: <path/to/your/build/zephyr.elf>
**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
version of Segger Ozone
References
**********
- `FPB-RA6E1 Website`_
- `RA6E1 MCU group Website`_
.. _FPB-RA6E1 Website:
path_to_url#overview
.. _RA6E1 MCU group Website:
path_to_url
.. _FPB-RA6E1 - User's Manual:
path_to_url
.. _RA6E1 Group User's Manual Hardware:
path_to_url
.. _Segger Ozone Download:
path_to_url#Ozone
``` | /content/code_sandbox/boards/renesas/fpb_ra6e1/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,151 |
```yaml
board:
name: fpb_ra6e2
vendor: renesas
socs:
- name: r7fa6e2bb3cfm
``` | /content/code_sandbox/boards/renesas/fpb_ra6e2/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
/*
*/
/dts-v1/;
#include <renesas/ra/ra6/r7fa6e2bb3cfm.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include "fpb_ra6e2-pinctrl.dtsi"
/ {
model = "Renesas FPB-RA6E2";
compatible = "renesas,ra6e2", "renesas,ra";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
leds {
compatible = "gpio-leds";
led1: led1 {
gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
led2: led2 {
gpios = <&ioport2 6 GPIO_ACTIVE_HIGH>;
label = "LED2";
};
};
aliases {
led0 = &led1;
led1 = &led2;
};
};
&sci0 {
pinctrl-0 = <&sci0_default>;
pinctrl-names = "default";
status = "okay";
uart0: uart {
current-speed = <115200>;
status = "okay";
};
};
&ioport2 {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "application";
reg = <0x00000000 DT_SIZE_K(128)>;
};
storage_partition: partition@20000 {
label = "storage";
reg = <0x20000 DT_SIZE_K(128)>;
};
};
};
&subclk {
status = "okay";
};
&pll {
source = <RA_PLL_SOURCE_HOCO>;
div = <RA_PLL_DIV_1>;
mul = <10 0>;
status = "okay";
};
``` | /content/code_sandbox/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 466 |
```unknown
config BOARD_RCAR_SALVATOR_XS
select SOC_R8A77961
``` | /content/code_sandbox/boards/renesas/rcar_salvator_xs/Kconfig.rcar_salvator_xs | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
# Cache management
CONFIG_CACHE_MANAGEMENT=y
# Enable UART driver
CONFIG_SERIAL=y
CONFIG_AARCH64_IMAGE_HEADER=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8300000
CONFIG_XIP=n
CONFIG_MAX_XLAT_TABLES=24
CONFIG_ARMV8_A_NS=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable clock control
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```yaml
identifier: rcar_salvator_xs
name: Renesas Salvator XS M3 based on r8a77961
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 512
supported:
- clock_control
- uart
testing:
ignore_tags:
- net
- bluetooth
- isotp
vendor: renesas
``` | /content/code_sandbox/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```yaml
board:
name: rcar_salvator_xs
vendor: renesas
socs:
- name: r8a77961
``` | /content/code_sandbox/boards/renesas/rcar_salvator_xs/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
&pfc {
scif2_data_a_tx_default: scif2_data_a_tx_default {
pin = <PIN_TX2_A FUNC_TX2_A>;
};
scif2_data_a_rx_default: scif2_data_a_rx_default {
pin = <PIN_RX2_A FUNC_RX2_A>;
};
emmc2_clk: emmc2_clk {
pin = <PIN_SD2_CLK FUNC_SD2_CLK>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_cmd: emmc2_cmd {
pin = <PIN_SD2_CMD FUNC_SD2_CMD>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_data0: emmc2_data0 {
pin = <PIN_SD2_DATA0 FUNC_SD2_DAT0>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_data1: emmc2_data1 {
pin = <PIN_SD2_DATA1 FUNC_SD2_DAT1>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_data2: emmc2_data2 {
pin = <PIN_SD2_DATA2 FUNC_SD2_DAT2>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_data3: emmc2_data3 {
pin = <PIN_SD2_DATA3 FUNC_SD2_DAT3>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_data4: emmc2_data4 {
pin = <PIN_SD1_DATA0 FUNC_SD2_DAT4>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_data5: emmc2_data5 {
pin = <PIN_SD1_DATA1 FUNC_SD2_DAT5>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_data6: emmc2_data6 {
pin = <PIN_SD1_DATA2 FUNC_SD2_DAT6>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_data7: emmc2_data7 {
pin = <PIN_SD1_DATA3 FUNC_SD2_DAT7>;
power-source = <PIN_VOLTAGE_1P8V>;
};
emmc2_ds: emmc2_ds {
pin = <PIN_SD2_DS FUNC_SD2_DS>;
};
};
``` | /content/code_sandbox/boards/renesas/rcar_salvator_xs/rcar_salvator_xs-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 566 |
```restructuredtext
.. _fpb_ra6e2:
RA6E2 Fast Prototyping Board
############################
Overview
********
The FPB-RA6E2, a Fast Prototyping Board for RA6E2 MCU Group, based on
the 200 MHz Arm Cortex-M33 core with TrustZone, enables users to
seamlessly evaluate the features of the RA6E2 MCU group and develop
embedded systems applications using Flexible Software Package (FSP)
and e2 studio IDE. The users can use rich on-board features along with
their choice of popular ecosystems add-ons to bring their big ideas to life.
The key features of the FPB-RA6E2 board are categorized in three groups as follow:
**MCU Native Pin Access**
- 200MHz Arm Cortex-M33 based RA6E2 MCU in 64 pins, LQFP package
- 256 kB Code Flash, 40 kB SRAM
- Native pin access through 2 x 32-pin male headers
- MCU current measurement point for precision current consumption measurement
- Multiple clock sources - RA6E2 MCU oscillator and sub-clock oscillator crystals,
providing precision 24.000 MHz and 32,768 Hz reference clock.
Additional low precision clocks are avaialbe internal to the RA6E2 MCU
**System Control and Ecosystem Access**
- USB Full Speed Host and Device (micro-AB connector)
- Two 5V input sources
- USB (Debug, Full Speed)
- External power supply (using 2-pin header)
- On-board debugger (SWD)
- User LEDs and buttons
- Two User LEDs (green)
- Power LED (green) indicating availability of regulated power
- Debug/power LED (yellow) indicating power and the debug connection
- One User button
- One Reset button
- Two popular ecosystem expansions
- Two Digilent PmodTM (SPI, UART and I3C) connectors
- Arduino (Uno R3) connectors
- MCU boot configuration jumper
.. figure:: fpb-ra6e2-board.webp
:align: center
:alt: RA6E2 Fast Prototyping Board
FPB-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
Hardware
********
Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_
.. figure:: ra6e2-block-diagram.webp
:width: 442px
:align: center
:alt: RA6E2 MCU group feature
RA6E2 Block diagram (Credit: Renesas Electronics Corporation)
Detailed hardware feature for the FPB-RA6E2 MCU can be found at `FPB-RA6E2 - User's Manual`_
Supported Features
==================
The below features are currently supported on Zephyr OS for FPB-RA6E2 board:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.
Programming and Debugging
*************************
Applications for the ``fpb_ra6e2`` board target configuration can be
built, flashed, and debugged in the usual way. See
:ref:`build_an_application` and :ref:`application_run` for more details on
building and running.
Flashing
========
Program can be flashed to fpb-RA6E2 via the on-board SEGGER J-Link debugger.
SEGGER J-link's drivers are avaialbe at path_to_url
To flash the program to board
1. Connect to J-Link OB via USB port to host PC
2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E2 - User's Manual`_
3. Execute west command
.. code-block:: console
west flash -r jlink
Debugging
=========
You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
Once downloaded and installed, open Segger Ozone and configure the debug project
like so:
* Target Device: R7FA6E2BB
* Target Interface: SWD
* Target Interface Speed: 4 MHz
* Host Interface: USB
* Program File: <path/to/your/build/zephyr.elf>
**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
version of Segger Ozone
References
**********
- `FPB-RA6E2 Website`_
- `RA6E2 MCU group Website`_
.. _FPB-RA6E2 Website:
path_to_url
.. _RA6E2 MCU group Website:
path_to_url
.. _FPB-RA6E2 - User's Manual:
path_to_url
.. _RA6E2 Group User's Manual Hardware:
path_to_url
.. _Segger Ozone Download:
path_to_url#Ozone
``` | /content/code_sandbox/boards/renesas/fpb_ra6e2/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,162 |
```unknown
if BOARD_RCAR_SALVATOR_XS
config BUILD_OUTPUT_BIN
default y
endif # BOARD_RCAR_SALVATOR_XS
``` | /content/code_sandbox/boards/renesas/rcar_salvator_xs/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*
*/
/dts-v1/;
#include <mem.h>
#include <arm64/renesas/r8a77961.dtsi>
#include "rcar_salvator_xs-pinctrl.dtsi"
/ {
model = "Salvator XS M3";
chosen {
zephyr,sram = &ram;
zephyr,console = &scif2;
zephyr,shell-uart = &scif2;
};
/* These aliases are provided for compatibility with samples */
aliases {
sdhc0 = &emmc2;
};
ram: memory@48000000 {
device_type = "mmio-sram";
reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>;
};
};
&scif2 {
pinctrl-0 = <&scif2_data_a_tx_default &scif2_data_a_rx_default>;
pinctrl-names = "default";
status = "okay";
};
&emmc2 {
pinctrl-0 = <&emmc2_clk &emmc2_cmd &emmc2_ds
&emmc2_data0 &emmc2_data1 &emmc2_data2 &emmc2_data3
&emmc2_data4 &emmc2_data5 &emmc2_data6 &emmc2_data7>;
pinctrl-1 = <&emmc2_clk &emmc2_cmd &emmc2_ds
&emmc2_data0 &emmc2_data1 &emmc2_data2 &emmc2_data3
&emmc2_data4 &emmc2_data5 &emmc2_data6 &emmc2_data7>;
pinctrl-names = "default", "uhs";
disk {
compatible = "zephyr,mmc-disk";
status = "disabled";
};
bus-width = <8>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
non-removable;
};
``` | /content/code_sandbox/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 442 |
```cmake
board_runner_args(jlink "--device=R7FA2A1AB")
board_runner_args(pyocd "--target=r7fa2a1ab")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/renesas/ek_ra2a1/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
/*
*/
/dts-v1/;
#include <renesas/ra/ra2/r7fa2a1ab3cfm.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include "ek_ra2a1-pinctrl.dtsi"
/ {
model = "Renesas EK-RA2A1";
compatible = "renesas,ra2a1", "renesas,ra2";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
leds {
compatible = "gpio-leds";
led1: led1 {
gpios = <&ioport2 5 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
};
aliases {
led0 = &led1;
};
};
&xtal {
clock-frequency = <DT_FREQ_M(12)>;
mosel = <0>;
#clock-cells = <0>;
status = "okay";
};
&subclk {
status = "okay";
};
&ioport2 {
status = "okay";
};
&sci0 {
pinctrl-0 = <&sci0_default>;
pinctrl-names = "default";
status = "okay";
uart0: uart {
current-speed = <115200>;
status = "okay";
};
};
``` | /content/code_sandbox/boards/renesas/ek_ra2a1/ek_ra2a1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 321 |
```unknown
config BOARD_EK_RA2A1
select SOC_R7FA2A1AB3CFM
``` | /content/code_sandbox/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```restructuredtext
.. _rcar_salvator_xs:
R-CAR Salvator XS M3 ARM CA57 (ARMv8)
#####################################
Overview
********
The R-Car M3-W is an SOC that features the basic functions for next-generation
car navigation systems.
Hardware
********
The R-Car M3-W includes:
* two 1.5-GHz ARM Cortex-A57 MPCore cores;
* four 1.3-GHz ARM Cortex-A53 MPCore cores,
* memory controller for LPDDR4-3200 with 32 bits x 2 channels;
* 1 channels for HDMI1.4b output and 1 channel for RGB888 output and 1channel for LVDS;
* 2 channels MIPI-CSI2 Video Input, 2 channels digital Video Input;
* USB3.0 x 1ch and USB2.0 x 2ch interfaces;
* 800-MHz ARM Cortex-R7 core;
* two- and three-dimensional graphics engines;
* video processing units;
* sound processing units;
* MediaLB interface;
* SD card host interface;
* USB3.0 and USB2.0 interfaces;
* PCI Express interface;
* CAN interface;
* EtherAVB.
Supported Features
==================
The Renesas rcar_salvator_xs board configuration supports the following
hardware features:
+-----------+------------------------------+--------------------------------+
| Interface | Driver/components | Support level |
+===========+==============================+================================+
| PINCTRL | pinctrl | |
+-----------+------------------------------+--------------------------------+
| CLOCK | clock_control | |
+-----------+------------------------------+--------------------------------+
| UART | uart | serial port-polling |
+-----------+------------------------------+--------------------------------+
| MMC | renesas_rcar_mmc | DMA and SCC |
+-----------+------------------------------+--------------------------------+
Other hardware features have not been enabled yet for this board.
The default configuration can be found in
:zephyr_file:`boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig`
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
References
**********
- `Renesas R-Car Development Support website`_
- `eLinux Salvator-XS page`_
.. _Renesas R-Car Development Support website:
path_to_url
.. _eLinux Salvator-XS page:
path_to_url
``` | /content/code_sandbox/boards/renesas/rcar_salvator_xs/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 525 |
```unknown
/*
*
*/
&pinctrl {
sci0_default: sci0_default {
group1 {
/* rx */
psels = <RA_PSEL(RA_PSEL_SCI_0, 3, 1)>;
};
group2 {
/* tx */
psels = <RA_PSEL(RA_PSEL_SCI_0, 3, 2)>;
drive-strength = "medium";
};
};
};
``` | /content/code_sandbox/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_PINCTRL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```yaml
board:
name: ek_ra2a1
vendor: renesas
socs:
- name: r7fa2a1ab3cfm
``` | /content/code_sandbox/boards/renesas/ek_ra2a1/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```yaml
identifier: ek_ra2a1
name: Renesas EK-RA2A1
type: mcu
arch: arm
ram: 32
flash: 256
toolchain:
- zephyr
- gnuarmemb
supported:
- gpio
- uart
``` | /content/code_sandbox/boards/renesas/ek_ra2a1/ek_ra2a1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
``` | /content/code_sandbox/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```cmake
board_runner_args(jlink "--device=R7FA6M5BH")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/renesas/ek_ra6m5/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```yaml
identifier: ek_ra6m5
name: Renesas EK-RA6M5
type: mcu
arch: arm
ram: 512
flash: 2048
toolchain:
- zephyr
- gnuarmemb
supported:
- gpio
``` | /content/code_sandbox/boards/renesas/ek_ra6m5/ek_ra6m5.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
config BOARD_EK_RA6M5
select SOC_R7FA6M5BH3CFC
``` | /content/code_sandbox/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.