text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_imx8mq_m4.dtsi>
#include "imx8mq_evk-pinctrl.dtsi"
/ {
model = "NXP i.MX8MQ EVK board";
compatible = "nxp,mimx8mq_evk";
aliases {
uart-2 = &uart2;
};
chosen {
zephyr,flash = &tcml_code;
zephyr,sram = &tcmu_sys;
zephyr,console = &uart2;
zephyr,shell-uart = &uart2;
};
};
&uart2 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart2_default>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 178 |
```yaml
board:
name: imx8mq_evk
vendor: nxp
socs:
- name: mimx8mq6
``` | /content/code_sandbox/boards/nxp/imx8mq_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```yaml
#
#
#
identifier: imx8mq_evk/mimx8mq6/m4
name: NXP i.MX8MQ EVK CM4
type: mcu
arch: arm
ram: 128
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
testing:
ignore_tags:
- net
- bluetooth
vendor: nxp
``` | /content/code_sandbox/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
#
#
#
CONFIG_CLOCK_CONTROL=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_XIP=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
# MIMX8MQ EVK board
config BOARD_IMX8MQ_EVK
select SOC_PART_NUMBER_MIMX8MQ6DVAJZ
select SOC_MIMX8MQ6_M4 if BOARD_IMX8MQ_EVK_MIMX8MQ6_M4
``` | /content/code_sandbox/boards/nxp/imx8mq_evk/Kconfig.imx8mq_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```restructuredtext
.. _imx8mp_evk:
NXP i.MX8MP EVK
###############
Overview
********
i.MX8M Plus LPDDR4 EVK board is based on NXP i.MX8M Plus applications
processor, composed of a quad Cortex-A53 cluster and a single Cortex-M7 core.
Zephyr OS is ported to run on the Cortex-A53 core.
- Board features:
- RAM: 2GB LPDDR4
- Storage:
- SanDisk 16GB eMMC5.1
- Micron 32MB QSPI NOR
- microSD Socket
- Wireless:
- WiFi: 2.4/5GHz IEEE 802.11b/g/n
- Bluetooth: v4.1
- USB:
- OTG - 2x type C
- Ethernet
- PCI-E M.2
- Connectors:
- 40-Pin Dual Row Header
- LEDs:
- 1x Power status LED
- 1x UART LED
- Debug
- JTAG 20-pin connector
- MicroUSB for UART debug, two COM ports for A53 and M4
More information about the board can be found at the
`NXP website`_.
Supported Features
==================
The Zephyr mimx8mp_evk_a53 board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| GIC-v3 | on-chip | interrupt controller |
+-----------+------------+-------------------------------------+
| ARM TIMER | on-chip | system clock |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| RDC | on-chip | Resource Domain Controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet port |
+-----------+------------+-------------------------------------+
The Zephyr mimx8mp_evk_m7 board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 8 MHz.
The M7 Core is configured to run at a 800 MHz clock speed.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART4.
Programming and Debugging (A53)
*******************************
Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
plug the SD card into the board. Power it up and stop the u-boot execution at
prompt.
Use U-Boot to load and kick non-smp zephyr.bin:
.. code-block:: console
fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xc0000000
Or kick SMP zephyr.bin:
.. code-block:: console
fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0xc0000000
Use this configuration to run basic Zephyr applications and kernel tests,
for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: imx8mp_evk/mimx8ml8/a53
:goals: run
This will build an image with the synchronization sample app, boot it and
display the following console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 ***
thread_a: Hello World from cpu 0 on mimx8mp_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mp_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mp_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mp_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mp_evk_a53!
Use Jailhouse hypervisor, after root cell linux is up:
.. code-block:: console
#jailhouse enable imx8mp.cell
#jailhouse cell create imx8mp-zephyr.cell
#jailhouse cell load 1 zephyr.bin -a 0xc0000000
#jailhouse cell start 1
Programming and Debugging (M7)
******************************
The MIMX8MP EVK board doesn't have QSPI flash for the M7, and it needs
to be started by the A53 core. The A53 core is responsible to load the M7 binary
application into the RAM, put the M7 in reset, set the M7 Program Counter and
Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at
bootloader level or after the Linux system has booted.
The M7 can use up to 3 different RAMs (currently, only two configurations are
supported: ITCM and DDR). These are the memory mapping for A53 and M7:
+------------+-------------------------+------------------------+-----------------------+----------------------+
| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size |
+============+=========================+========================+=======================+======================+
| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
For more information about memory mapping see the
`i.MX 8M Applications Processor Reference Manual`_ (section 2.1 to 2.3)
At compilation time you have to choose which RAM will be used. This
configuration is done based on board name (imx8mp_evk/mimx8ml8/m7 for ITCM and
imx8mp_evk/mimx8ml8/m7/ddr for DDR).
There are two methods to load M7 Core images: U-Boot command and Linux remoteproc.
Load and Run M7 Zephyr Image from U-Boot
========================================
Load and run Zephyr on M7 from A53 using u-boot by copying the compiled
``zephyr.bin`` to the first FAT partition of the SD card and plug the SD
card into the board. Power it up and stop the u-boot execution at prompt.
Load the M7 binary onto the desired memory and start its execution using:
ITCM
====
.. code-block:: console
fatload mmc 0:1 0x48000000 zephyr.bin
cp.b 0x48000000 0x7e0000 20000
bootaux 0x7e0000
DDR
===
.. code-block:: console
fatload mmc 0:1 0x80000000 zephyr.bin
dcache flush
bootaux 0x80000000
Load and Run M7 Zephyr Image by using Linux remoteproc
======================================================
Prepare device tree:
The device tree must inlcude CM7 dts node with compatible string "fsl,imx8mn-cm7",
and also need to reserve M4 DDR memory if using DDR code and sys address, and also
need to put "m4_reserved" in the list of memory-region property of the cm7 node.
.. code-block:: console
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
m7_reserved: m4@80000000 {
no-map;
reg = <0 0x80000000 0 0x1000000>;
};
...
}
imx8mp-cm7 {
compatible = "fsl,imx8mn-cm7";
rsc-da = <0x55000000>;
clocks = <&clk IMX8MP_CLK_M7_DIV>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT>;
clock-names = "core", "audio";
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu 0 1
&mu 1 1
&mu 3 1>;
memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>, <&m7_reserved>;
status = "okay";
fsl,startup-delay-ms = <500>;
};
Extra Zephyr Kernel configure item for DDR Image:
If use remotepoc to boot DDR board (imx8mp_evk/mimx8ml8/m7/ddr), also need to enable
"CONFIG_ROMSTART_RELOCATION_ROM" in order to put romstart memory section into ITCM because
M7 Core will get the first instruction from zero address of ITCM, but romstart relocation
will make the storage size of zephyr.bin too large, so we don't enable it by default in
board defconfig.
.. code-block:: console
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig
index 17542cb4eec..8c30c5b6fa3 100644
--- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig
+++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig
@@ -12,3 +12,4 @@ CONFIG_CONSOLE=y
CONFIG_XIP=y
CONFIG_CODE_DDR=y
CONFIG_PINCTRL=y
+CONFIG_ROMSTART_RELOCATION_ROM=y
Then use the following steps to boot Zephyr kernel:
1. In U-Boot command line execute prepare script:
.. code-block:: console
u-boot=> run prepare_mcore
2. Boot Linux kernel with specified dtb and then boot Zephyr by using remoteproc:
.. code-block:: console
root@imx8mp-lpddr4-evk:~# echo zephyr.elf > /sys/devices/platform/imx8mp-cm7/remoteproc/remoteproc0/firmware
root@imx8mp-lpddr4-evk:~# echo start > /sys/devices/platform/imx8mp-cm7/remoteproc/remoteproc0/state
[ 39.195651] remoteproc remoteproc0: powering up imx-rproc
[ 39.203345] remoteproc remoteproc0: Booting fw image zephyr.elf, size 503992
[ 39.203388] remoteproc remoteproc0: No resource table in elf
root@imx8mp-lpddr4-evk:~# [ 39.711380] remoteproc remoteproc0: remote processor imx-rproc is now up
root@imx8mp-lpddr4-evk:~#
Debugging
=========
MIMX8MP EVK board can be debugged by connecting an external JLink
JTAG debugger to the J24 debug connector and to the PC. Then
the application can be debugged using the usual way.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: imx8mp_evk/mimx8ml8/m7
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v2.7.99-1310-g2801bf644a91 ***
Hello World! imx8mp_evk
References
==========
.. _NXP website:
path_to_url
.. _i.MX 8M Applications Processor Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/nxp/imx8mp_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,205 |
```cmake
board_runner_args(trace32
"--startup-args"
"elfFile=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}"
)
if(${CONFIG_XIP})
board_runner_args(trace32 "loadTo=flash")
else()
board_runner_args(trace32 "loadTo=sram")
endif()
board_runner_args(jlink "--device=S32K344" "--reset-after-load")
board_runner_args(pyocd "--target=s32k344")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/trace32.board.cmake)
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 143 |
```restructuredtext
.. _mimx8mq_evk:
NXP MIMX8MQ EVK
###############
Overview
********
i.MX8MQ EVK board is based on NXP i.MX8MQ applications
processor, composed of a quad Cortex-A53 cluster and a single Cortex-M4 core.
Zephyr OS is ported to run on the Cortex-M4 core.
- Board features:
- RAM: 3GB LPDDR4
- Storage:
- 16GB eMMC5.0
- 32MB QSPI NOR
- microSD Socket
- Wireless:
- WiFi: 2.4/5GHz IEEE 802.11 a/b/g/n/ac
- Bluetooth: v4.1
- USB:
- OTG - 1x type C
- HOST - 1x type A
- Ethernet
- PCI-E M.2
- LEDs:
- 1x Power status LED
- 1x UART LED
- Debug
- JTAG 10-pin connector
- MicroUSB for UART debug, two COM ports for A53 and M4
.. image:: img/mimx8mq_evk.jpg
:align: center
:alt: MIMX8MQ EVK
More information about the board can be found at the
`NXP website`_.
Supported Features
==================
The Zephyr mimx8mq_evk board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig`.
Other hardware features are not currently supported by the port.
Connections and IOs
===================
MIMX8MQ EVK board was tested with the following pinmux controller
configuration.
+---------------+-----------------+---------------------------+
| Board Name | SoC Name | Usage |
+===============+=================+===========================+
| UART2 RXD | UART2_TXD | UART Console |
+---------------+-----------------+---------------------------+
| UART2 TXD | UART2_RXD | UART Console |
+---------------+-----------------+---------------------------+
System Clock
============
The M4 Core is configured to run at a 266 MHz clock speed.
Serial Port
===========
The i.MX8MQ SoC has four UARTs. UART_2 is configured for the console and
the remaining are not used/tested.
Programming and Debugging
*************************
The MIMX8MQ EVK board doesn't have QSPI flash for the M4 and it needs
to be started by the A53 core. The A53 core is responsible to load the M4 binary
application into the RAM, put the M4 in reset, set the M4 Program Counter and
Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at
bootloader level or after the Linux system has booted.
The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4:
+------------+-------------------------+------------------------+-----------------------+----------------------+
| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size |
+============+=========================+========================+=======================+======================+
| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
For more information about memory mapping see the
`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3)
At compilation time you have to choose which RAM will be used. This
configuration is done in the file :zephyr_file:`boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts`
with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties.
The available configurations are:
.. code-block:: none
"zephyr,flash"
- &tcml_code
- &ocram_code
- &ocram_s_code
"zephyr,sram"
- &tcmu_sys
- &ocram_sys
- &ocram_s_sys
Load and run Zephyr on M4 from A53 using u-boot.
.. tabs::
.. group-tab:: From an SD card
Copy the compiled ``zephyr.bin`` to the first FAT partition of the
SD card and plug the SD card into the board. Power it up and stop the u-boot
execution at prompt.
Load the M4 binary onto the desired memory and start its execution using:
.. code-block:: console
fatload mmc 0:1 0x40480000 zephyr.bin
cp.b 0x40480000 0x7e0000 0x8000
bootaux 0x7e0000
.. group-tab:: From serial
This procedure requires ``screen`` and ``lrzsz`` to be installed.
Start ``screen``, power up the board, and stop the u-boot execution at prompt:
.. code-block:: console
screen <tty-device> 115200
Start ``loadx`` with offset ``7e0000``:
.. code-block:: console
loadx 7e0000 115200
Send the compiled ``zephyr.bin`` with ``sx`` by pressing :kbd:`Ctrl-a` followed by :kbd:`:`
and write:
.. code-block:: console
exec !! sx </full/path/to/zephyr.bin>
Start execution:
.. code-block:: console
bootaux 0x7e0000
Debugging
=========
MIMX8MQ EVK board can be debugged by connecting an external JLink
JTAG debugger to the J401 debug connector and to the PC. Then
the application can be debugged using the usual way.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: imx8mq_evk/mimx8mq6/m4
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS build zephyr-v2.6.99-30942-g6ee70bd22058 *****
Hello World! imx8mq_evk
References
==========
.. _NXP website:
path_to_url
.. _i.MX 8M Applications Processor Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/nxp/imx8mq_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,855 |
```unknown
config BOARD_MR_CANHUBK3
select SOC_S32K344
select SOC_PART_NUMBER_PS32K344EHVPBS
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/Kconfig.mr_canhubk3 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
/*
*
*/
#include <nxp/s32/S32K344-172MQFP-pinctrl.h>
&pinctrl {
eirq0_default: eirq0_default {
group1 {
pinmux = <PTD15_EIRQ31>, <PTA18_EIRQ0>, <PTA25_EIRQ5>, <PTD5_EIRQ13>;
input-enable;
};
};
lpuart0_default: lpuart0_default {
group1 {
pinmux = <PTA3_LPUART0_TX_O>, <PTA1_LPUART0_RTS>;
output-enable;
};
group2 {
pinmux = <PTA2_LPUART0_RX>, <PTA0_LPUART0_CTS>;
input-enable;
};
};
lpuart1_default: lpuart1_default {
group1 {
pinmux = <PTC7_LPUART1_TX_O>, <PTE6_LPUART1_RTS>;
output-enable;
};
group2 {
pinmux = <PTC6_LPUART1_RX>, <PTE2_LPUART1_CTS>;
input-enable;
};
};
lpuart2_default: lpuart2_default {
group1 {
pinmux = <PTA9_LPUART2_TX_O>;
output-enable;
};
group2 {
pinmux = <PTA8_LPUART2_RX>;
input-enable;
};
};
lpuart9_default: lpuart9_default {
group1 {
pinmux = <PTB3_LPUART9_TX_O>;
output-enable;
};
group2 {
pinmux = <PTB2_LPUART9_RX>;
input-enable;
};
};
lpuart10_default: lpuart10_default {
group1 {
pinmux = <PTC13_LPUART10_TX_O>;
output-enable;
};
group2 {
pinmux = <PTC12_LPUART10_RX>;
input-enable;
};
};
lpuart13_default: lpuart13_default {
group1 {
pinmux = <PTB18_LPUART13_TX_O>;
output-enable;
};
group2 {
pinmux = <PTB19_LPUART13_RX>;
input-enable;
};
};
lpuart14_default: lpuart14_default {
group1 {
pinmux = <PTB20_LPUART14_TX_O>;
output-enable;
};
group2 {
pinmux = <PTB21_LPUART14_RX>;
input-enable;
};
};
qspi0_default: qspi0_default {
group1 {
pinmux = <(PTD11_QUADSPI_IOFA0_O | PTD11_QUADSPI_IOFA0_I)>,
<(PTD7_QUADSPI_IOFA1_O | PTD7_QUADSPI_IOFA1_I)>,
<(PTD12_QUADSPI_IOFA2_O | PTD12_QUADSPI_IOFA2_I)>,
<(PTC2_QUADSPI_IOFA3_O | PTC2_QUADSPI_IOFA3_I)>;
output-enable;
input-enable;
};
group2 {
pinmux = <PTD10_QUADSPI_SCKFA_O>;
output-enable;
};
group3 {
pinmux = <PTC3_QUADSPI_PCSFA>;
output-enable;
bias-pull-up;
};
};
flexcan0_default: flexcan0_default {
group1 {
pinmux = <PTA6_CAN0_RX>;
input-enable;
};
group2 {
pinmux = <PTA7_CAN0_TX>;
output-enable;
};
};
flexcan1_default: flexcan1_default {
group1 {
pinmux = <PTC9_CAN1_RX>;
input-enable;
};
group2 {
pinmux = <PTC8_CAN1_TX>;
output-enable;
};
};
flexcan2_default: flexcan2_default {
group1 {
pinmux = <PTE25_CAN2_RX>;
input-enable;
};
group2 {
pinmux = <PTE24_CAN2_TX>;
output-enable;
};
};
flexcan3_default: flexcan3_default {
group1 {
pinmux = <PTC29_CAN3_RX>;
input-enable;
};
group2 {
pinmux = <PTC28_CAN3_TX>;
output-enable;
};
};
flexcan4_default: flexcan4_default {
group1 {
pinmux = <PTC31_CAN4_RX>;
input-enable;
};
group2 {
pinmux = <PTC30_CAN4_TX>;
output-enable;
};
};
flexcan5_default: flexcan5_default {
group1 {
pinmux = <PTC11_CAN5_RX>;
input-enable;
};
group2 {
pinmux = <PTC10_CAN5_TX>;
output-enable;
};
};
lpi2c0_default: lpi2c0_default {
group1 {
pinmux = <(PTD13_LPI2C0_SDA_I | PTD13_LPI2C0_SDA_O)>,
<(PTD14_LPI2C0_SCL_I | PTD14_LPI2C0_SCL_O)>;
input-enable;
output-enable;
};
};
lpi2c1_default: lpi2c1_default {
group1 {
pinmux = <(PTD8_LPI2C1_SDA_I | PTD8_LPI2C1_SDA_O)>,
<(PTD9_LPI2C1_SCL_I | PTD9_LPI2C1_SCL_O)>;
input-enable;
output-enable;
};
};
lpspi1_default: lpspi1_default {
group1 {
pinmux = <PTA28_LPSPI1_SCK_O>, <PTA29_LPSPI1_SIN_O>,
<PTA21_LPSPI1_PCS0_O>, <PTE4_LPSPI1_PCS1_O>;
output-enable;
};
group2 {
pinmux = <PTA30_LPSPI1_SOUT_I>;
input-enable;
};
};
lpspi2_default: lpspi2_default {
group1 {
pinmux = <PTB29_LPSPI2_SCK_O>, <PTB28_LPSPI2_SIN_O>,
<PTB25_LPSPI2_PCS0_O>, <PTC19_LPSPI2_PCS1_O>;
output-enable;
};
group2 {
pinmux = <PTB27_LPSPI2_SOUT_I>;
input-enable;
};
};
lpspi3_default: lpspi3_default {
group1 {
pinmux = <PTD1_LPSPI3_SCK_O>, <PTE10_LPSPI3_SIN_O>,
<PTD17_LPSPI3_PCS0_O>;
output-enable;
};
group2 {
pinmux = <PTD0_LPSPI3_SOUT_I>;
input-enable;
};
};
lpspi4_default: lpspi4_default {
group1 {
pinmux = <PTB10_LPSPI4_SCK_O>, <PTB11_LPSPI4_SIN_O>,
<PTB8_LPSPI4_PCS0_O>;
output-enable;
};
group2 {
pinmux = <PTB9_LPSPI4_SOUT_I>;
input-enable;
};
};
lpspi5_default: lpspi5_default {
group1 {
pinmux = <PTD26_LPSPI5_SCK_O>, <PTD28_LPSPI5_SIN_O>;
output-enable;
};
group2 {
pinmux = <PTD27_LPSPI5_SOUT_I>;
input-enable;
};
};
emac0_default: emac0_default {
group1 {
pinmux = <PTC0_EMAC_MII_RMII_RXD0>,
<PTC1_EMAC_MII_RMII_RXD1>,
<PTC14_EMAC_MII_RMII_RX_ER>,
<PTC15_EMAC_MII_RMII_RX_DV>,
<PTD6_EMAC_MII_RMII_TX_CLK>;
input-enable;
};
group2 {
pinmux = <PTB5_EMAC_MII_RMII_TXD0>,
<PTB4_EMAC_MII_RMII_TXD1>,
<PTE9_EMAC_MII_RMII_TX_EN>;
};
};
mdio0_default: mdio0_default {
group1 {
pinmux = <(PTD16_EMAC_MII_RMII_MDIO_O | PTD16_EMAC_MII_RMII_MDIO_I)>;
input-enable;
output-enable;
};
group2 {
pinmux = <PTE8_EMAC_MII_RMII_MDC>;
output-enable;
};
};
emios0_default: emios0_default {
group1 {
pinmux = <PTB12_EMIOS_0_CH0_X_O>, <PTB13_EMIOS_0_CH1_G_O>,
<PTB14_EMIOS_0_CH2_G_O>, <PTB15_EMIOS_0_CH3_G_O>,
<PTB16_EMIOS_0_CH4_G_O>, <PTB17_EMIOS_0_CH5_G_O>,
<PTE14_EMIOS_0_CH19_Y_O>;
output-enable;
};
};
emios1_default: emios1_default {
group1 {
pinmux = <PTA27_EMIOS_1_CH10_H_O>,
<PTE12_EMIOS_1_CH5_H_O>;
output-enable;
};
};
flexio0_pwm_default: flexio0_pwm_default {
group1 {
pinmux = <PTA17_FXIO_D19_O>, <PTE7_FXIO_D11_O>;
output-enable;
};
};
qdec_s32: qdec_s32 {
group1 {
pinmux = <PTB2_TRGMUX_IN3>,
<PTB3_TRGMUX_IN2>,
<TRGMUX_INT_OUT37_EMIOS_0_CH6_G>,
<TRGMUX_INT_OUT38_EMIOS_0_CH7_G>;
input-enable;
};
};
};
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/mr_canhubk3-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,408 |
```yaml
board:
name: mr_canhubk3
vendor: nxp
socs:
- name: s32k344
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```yaml
identifier: mr_canhubk3
name: NXP MR-CANHUBK3
type: mcu
arch: arm
ram: 1024
flash: 1024
toolchain:
- zephyr
supported:
- gpio
- uart
- can
- i2c
- adc
- spi
- watchdog
- netif:eth
- pwm
- dma
- display
- counter
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/mr_canhubk3.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```unknown
if BOARD_MR_CANHUBK3
if SERIAL
config UART_CONSOLE
default y
endif # SERIAL
if SPI
config SPI_INIT_PRIORITY
default 50
if WDT_NXP_FS26
config WDT_NXP_FS26_INIT_PRIORITY
default 51
endif # WDT_NXP_FS26
endif # SPI
if NETWORKING
config NET_L2_ETHERNET
default y if !NET_LOOPBACK && !NET_TEST
config MDIO
default y if NET_L2_ETHERNET
endif # NETWORKING
endif # BOARD_MR_CANHUBK3
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 125 |
```unknown
CONFIG_BUILD_OUTPUT_HEX=y
# Use Systick as system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=160000000
# Run from internal Flash
CONFIG_XIP=y
# Enable MPU
CONFIG_ARM_MPU=y
# Use no-cached memory for HAL
CONFIG_NOCACHE_MEMORY=y
# Drivers
CONFIG_PINCTRL=y
CONFIG_SERIAL=y
CONFIG_WATCHDOG=y
# Serial console
CONFIG_CONSOLE=y
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/mr_canhubk3_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
;*******************************************************************************
; *
; Lauterbach TRACE32 start-up script for debugging mr_canhubk3 *
; *
;*******************************************************************************
ENTRY %LINE &args
DO ~~~~/startup.cmm command=debug &args
ENDDO
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/support/debug.cmm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
/*
*
*/
/dts-v1/;
#include <arm/nxp/nxp_s32k344_m7.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <freq.h>
#include <dt-bindings/pwm/pwm.h>
#include "mr_canhubk3-pinctrl.dtsi"
#include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h>
/ {
model = "NXP MR-CANHUBK3";
compatible = "nxp,mr_canhubk3";
chosen {
zephyr,sram = &sram0_1;
zephyr,flash = &flash0;
zephyr,itcm = &itcm;
zephyr,dtcm = &dtcm;
zephyr,code-partition = &code_partition;
zephyr,console = &lpuart2;
zephyr,shell-uart = &lpuart2;
zephyr,flash-controller = &mx25l6433f;
zephyr,canbus = &flexcan0;
zephyr,display = &ssd1306;
};
aliases {
dma0 = &edma0;
led0 = &user_led1_red;
led1 = &user_led1_green;
led2 = &user_led1_blue;
sw0 = &user_button_1;
sw1 = &user_button_2;
watchdog0 = &swt0;
/* For pwm test suites */
pwm-0 = &emios0_pwm;
pwm-1 = &flexio0_pwm;
red-pwm-led = &user_led1_red_pwm;
green-pwm-led = &user_led1_green_pwm;
blue-pwm-led = &user_led1_blue_pwm;
pwm-led0 = &user_led1_blue_pwm;
qdec0 = &qdec0;
};
leds {
compatible = "gpio-leds";
user_led1_green: user_led1_green {
gpios = <&gpioa_h 11 GPIO_ACTIVE_LOW>;
label = "User RGB LED1 GREEN";
};
user_led1_blue: user_led1_blue {
gpios = <&gpioe_l 12 GPIO_ACTIVE_LOW>;
label = "User RGB LED1 BLUE";
};
user_led1_red: user_led1_red {
gpios = <&gpioe_l 14 GPIO_ACTIVE_LOW>;
label = "User RGB LED1 RED";
};
can_led0: can_led0 {
gpios = <&gpioc_h 2 GPIO_ACTIVE_LOW>;
label = "CAN LED0";
};
can_led1: can_led1 {
gpios = <&gpioe_l 5 GPIO_ACTIVE_LOW>;
label = "CAN LED1";
};
can_led2: can_led2 {
gpios = <&gpiod_h 4 GPIO_ACTIVE_LOW>;
label = "CAN LED2";
};
can_led3: can_led3 {
gpios = <&gpiob_h 8 GPIO_ACTIVE_LOW>;
label = "CAN LED3";
};
can_led4: can_led4 {
gpios = <&gpiob_h 10 GPIO_ACTIVE_LOW>;
label = "CAN LED4";
};
can_led5: can_led5 {
gpios = <&gpiod_h 15 GPIO_ACTIVE_LOW>;
label = "CAN LED5";
};
};
/* gpio-leds and pwm-leds are the same RGB LED and cannot be used at the same time. */
pwmleds {
compatible = "pwm-leds";
user_led1_blue_pwm: user_led1_blue {
pwms = <&emios1_pwm 5 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
user_led1_green_pwm: user_led1_green {
pwms = <&emios1_pwm 10 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
user_led1_red_pwm: user_led1_red {
pwms = <&emios0_pwm 19 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
};
qdec0: qdec0 {
compatible = "nxp,qdec-s32";
pinctrl-0 = <&qdec_s32>;
pinctrl-names = "default";
micro-ticks-per-rev = <685440000>;
status = "okay";
trgmux = <&trgmux>;
trgmux-io-config =
<0 TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH6 TRGMUX_IP_INPUT_LCU1_LC0_OUT_I2>,
<1 TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH7 TRGMUX_IP_INPUT_LCU1_LC0_OUT_I3>,
<2 TRGMUX_IP_OUTPUT_LCU1_0_INP_I0 TRGMUX_IP_INPUT_SIUL2_IN2>,
<3 TRGMUX_IP_OUTPUT_LCU1_0_INP_I1 TRGMUX_IP_INPUT_SIUL2_IN3>;
lcu = <&lcu1>;
lcu-input-idx =
<LCU_IP_IN_0 LCU_IP_IN_1
LCU_IP_IN_2 LCU_IP_IN_3>;
lcu-mux-sel =
<LCU_IP_MUX_SEL_LU_IN_0 LCU_IP_MUX_SEL_LU_IN_1
LCU_IP_MUX_SEL_LU_OUT_0 LCU_IP_MUX_SEL_LU_OUT_1>;
lcu-output-filter-config =
/* LCU Out HW ID, Rise Filter, Fall Filter */
<0 5 5>, /* LCU O0 */
<1 5 5>, /* LCU O1 */
<2 2 2>, /* LCU O2 */
<3 2 2>; /* LCU O3 */
emios = <&emios0>;
/*
* eMios channel numbers for qdec should be beyond the channel numbers
* used by the emios pwm
*/
emios-channels = <6 7>;
};
gpio_keys {
compatible = "gpio-keys";
user_button_1: button_0 {
label = "User SW1";
gpios = <&gpiod_l 15 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_2: button_1 {
label = "User SW2";
gpios = <&gpioa_h 9 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_1>;
};
};
can_phy0: can-phy0 {
compatible = "nxp,tja1443", "can-transceiver-gpio";
enable-gpios = <&gpioc_h 8 GPIO_ACTIVE_HIGH>;
standby-gpios = <&gpioc_h 5 GPIO_ACTIVE_LOW>;
max-bitrate = <5000000>;
#phy-cells = <0>;
};
can_phy1: can-phy1 {
compatible = "nxp,tja1443", "can-transceiver-gpio";
enable-gpios = <&gpiod_l 2 GPIO_ACTIVE_HIGH>;
standby-gpios = <&gpiod_h 7 GPIO_ACTIVE_LOW>;
max-bitrate = <5000000>;
#phy-cells = <0>;
};
can_phy2: can-phy2 {
compatible = "nxp,tja1463", "can-transceiver-gpio";
enable-gpios = <&gpiod_l 4 GPIO_ACTIVE_HIGH>;
standby-gpios = <&gpiod_h 6 GPIO_ACTIVE_LOW>;
max-bitrate = <8000000>;
#phy-cells = <0>;
};
can_phy3: can-phy3 {
compatible = "nxp,tja1463", "can-transceiver-gpio";
enable-gpios = <&gpiob_l 0 GPIO_ACTIVE_HIGH>;
standby-gpios = <&gpiob_l 1 GPIO_ACTIVE_LOW>;
max-bitrate = <8000000>;
#phy-cells = <0>;
};
can_phy4: can-phy4 {
compatible = "nxp,tja1153", "can-transceiver-gpio";
enable-gpios = <&gpioc_h 10 GPIO_ACTIVE_HIGH>;
standby-gpios = <&gpioc_h 9 GPIO_ACTIVE_LOW>;
max-bitrate = <2000000>;
#phy-cells = <0>;
};
can_phy5: can-phy5 {
compatible = "nxp,tja1153", "can-transceiver-gpio";
enable-gpios = <&gpioe_h 1 GPIO_ACTIVE_HIGH>;
standby-gpios = <&gpiod_h 14 GPIO_ACTIVE_LOW>;
max-bitrate = <2000000>;
#phy-cells = <0>;
};
};
&pmc {
lm-reg;
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
ivt_header: partition@0 {
label = "ivt-header";
reg = <0x00000000 0x100>;
};
code_partition: partition@100 {
label = "code-partition";
reg = <0x00000100 (DT_SIZE_K(4048) - 0x100)>;
};
};
};
&gpioa_h {
status = "okay";
};
&gpioe_l {
status = "okay";
};
/* Enable gpio to control the CAN transceivers and LEDs */
&gpiob_h {
status = "okay";
};
&gpioc_h {
status = "okay";
};
&gpiod_l {
status = "okay";
};
&gpiod_h {
status = "okay";
};
&gpiob_l {
status = "okay";
};
&gpioe_h {
status = "okay";
};
&eirq0 {
pinctrl-0 = <&eirq0_default>;
pinctrl-names = "default";
status = "okay";
};
&lpuart0 {
pinctrl-0 = <&lpuart0_default>;
pinctrl-names = "default";
dmas = <&edma0 0 37>, <&edma0 1 38>;
dma-names = "tx", "rx";
};
&lpuart1 {
pinctrl-0 = <&lpuart1_default>;
pinctrl-names = "default";
dmas = <&edma0 2 39>, <&edma0 3 40>;
dma-names = "tx", "rx";
};
&lpuart2 {
pinctrl-0 = <&lpuart2_default>;
pinctrl-names = "default";
current-speed = <115200>;
dmas = <&edma0 16 38>, <&edma0 17 39>;
dma-names = "tx", "rx";
status = "okay";
};
&lpuart9 {
pinctrl-0 = <&lpuart9_default>;
pinctrl-names = "default";
/*
* LPUART 1 and 9 share the same DMA source for TX
* and RX, using UART async API for both instances
* should be careful.
*/
dmas = <&edma0 4 39>, <&edma0 5 40>;
dma-names = "tx", "rx";
};
&lpuart10 {
pinctrl-0 = <&lpuart10_default>;
pinctrl-names = "default";
/*
* LPUART 2 and 10 share the same DMA source for TX
* and RX, using UART async API for both instances
* should be careful.
*/
dmas = <&edma0 18 38>, <&edma0 19 39>;
dma-names = "tx", "rx";
};
&lpuart13 {
pinctrl-0 = <&lpuart13_default>;
pinctrl-names = "default";
dmas = <&edma0 20 44>, <&edma0 21 45>;
dma-names = "tx", "rx";
};
&lpuart14 {
pinctrl-0 = <&lpuart14_default>;
pinctrl-names = "default";
dmas = <&edma0 22 46>, <&edma0 23 47>;
dma-names = "tx", "rx";
};
&qspi0 {
pinctrl-0 = <&qspi0_default>;
pinctrl-names = "default";
data-rate = "SDR";
a-rx-clock-source = "LOOPBACK";
a-dll-mode = "BYPASSED";
ahb-buffers-masters = <0 1 2 3>;
ahb-buffers-sizes = <0 0 0 256>;
ahb-buffers-all-masters;
status = "okay";
mx25l6433f: mx25l6433f@0 {
compatible = "nxp,s32-qspi-nor";
reg = <0>;
size = <DT_SIZE_M(64)>;
jedec-id = [c2 20 17];
quad-enable-requirements = "S1B6";
readoc = "1-4-4";
writeoc = "1-4-4";
has-32k-erase;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x0 0x100000>;
};
};
};
};
&flexcan0 {
pinctrl-0 = <&flexcan0_default>;
pinctrl-names = "default";
phys = <&can_phy0>;
status = "okay";
};
&flexcan1 {
pinctrl-0 = <&flexcan1_default>;
pinctrl-names = "default";
phys = <&can_phy1>;
};
&flexcan2 {
pinctrl-0 = <&flexcan2_default>;
pinctrl-names = "default";
phys = <&can_phy2>;
};
&flexcan3 {
pinctrl-0 = <&flexcan3_default>;
pinctrl-names = "default";
phys = <&can_phy3>;
};
&flexcan4 {
pinctrl-0 = <&flexcan4_default>;
pinctrl-names = "default";
phys = <&can_phy4>;
};
&flexcan5 {
pinctrl-0 = <&flexcan5_default>;
pinctrl-names = "default";
phys = <&can_phy5>;
};
&lpi2c0 {
pinctrl-0 = <&lpi2c0_default>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
ssd1306: ssd1306@3c {
compatible = "solomon,ssd1306fb";
reg = <0x3c>;
width = <128>;
height = <32>;
segment-offset = <0>;
page-offset = <0>;
display-offset = <0>;
multiplex-ratio = <31>;
segment-remap;
com-invdir;
com-sequential;
prechargep = <0x22>;
};
};
&lpi2c1 {
pinctrl-0 = <&lpi2c1_default>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
};
&lpspi1 {
pinctrl-0 = <&lpspi1_default>;
pinctrl-names = "default";
data-pin-config = "sdo-in,sdi-out";
};
&lpspi2 {
pinctrl-0 = <&lpspi2_default>;
pinctrl-names = "default";
data-pin-config = "sdo-in,sdi-out";
};
&lpspi3 {
pinctrl-0 = <&lpspi3_default>;
pinctrl-names = "default";
data-pin-config = "sdo-in,sdi-out";
status = "okay";
fs26_wdt: watchdog@0 {
compatible = "nxp,fs26-wdog";
reg = <0>;
spi-max-frequency = <DT_FREQ_M(5)>;
type = "challenger";
int-gpios = <&gpioa_h 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
&lpspi4 {
pinctrl-0 = <&lpspi4_default>;
pinctrl-names = "default";
data-pin-config = "sdo-in,sdi-out";
};
&lpspi5 {
pinctrl-0 = <&lpspi5_default>;
pinctrl-names = "default";
data-pin-config = "sdo-in,sdi-out";
};
&emac0 {
pinctrl-0 = <&emac0_default>;
pinctrl-names = "default";
phy-connection-type = "rmii";
local-mac-address = [02 04 9f aa bb cc];
phy-handle = <&phy>;
status = "okay";
};
&mdio0 {
pinctrl-0 = <&mdio0_default>;
pinctrl-names = "default";
status = "okay";
phy: ethernet-phy@12 {
compatible = "nxp,tja1103";
status = "okay";
reg = <0x12>;
int-gpios = <&gpiod_l 5 GPIO_ACTIVE_LOW>;
master-slave = "slave";
};
};
&emios0 {
clock-divider = <200>;
status = "okay";
master_bus {
/*
* Timebase for PWM led, setting clock 50KHz for internal counter,
* default period is 1000 cycles <-> 20ms.
*/
emios0_bus_a {
mode = "MCB_UP_COUNTER";
prescaler = <16>;
period = <1000>;
status = "okay";
};
};
emios0_pwm: pwm {
pinctrl-0 = <&emios0_default>;
pinctrl-names = "default";
status = "okay";
/* Default clock for internal counter for PWM channel 0-7 is 100Khz */
pwm_0 {
channel = <0>;
pwm-mode = "OPWFMB";
period = <65535>;
duty-cycle = <0>;
prescaler = <8>;
polarity = "ACTIVE_HIGH";
};
pwm_1 {
channel = <1>;
pwm-mode = "OPWFMB";
period = <65535>;
duty-cycle = <0>;
prescaler = <8>;
polarity = "ACTIVE_HIGH";
};
pwm_2 {
channel = <2>;
pwm-mode = "OPWFMB";
period = <65535>;
duty-cycle = <0>;
prescaler = <8>;
polarity = "ACTIVE_HIGH";
};
pwm_3 {
channel = <3>;
pwm-mode = "OPWFMB";
period = <65535>;
duty-cycle = <0>;
prescaler = <8>;
polarity = "ACTIVE_HIGH";
};
pwm_4 {
channel = <4>;
pwm-mode = "OPWFMB";
period = <65535>;
duty-cycle = <0>;
prescaler = <8>;
polarity = "ACTIVE_HIGH";
};
pwm_5 {
channel = <5>;
pwm-mode = "OPWFMB";
period = <65535>;
duty-cycle = <0>;
prescaler = <8>;
polarity = "ACTIVE_HIGH";
};
rgb_red {
channel = <19>;
master-bus = <&emios0_bus_a>;
duty-cycle = <0>;
pwm-mode = "OPWMB";
polarity = "ACTIVE_LOW";
};
};
};
&emios1 {
clock-divider = <200>;
status = "okay";
master_bus {
/*
* Timebase for PWM led, setting clock 50KHz for internal counter,
* default period is 1000 cycles <-> 20ms.
*/
emios1_bus_a {
prescaler = <16>;
mode = "MCB_UP_COUNTER";
period = <1000>;
status = "okay";
};
emios1_bus_f {
prescaler = <16>;
mode = "MCB_UP_COUNTER";
period = <1000>;
status = "okay";
};
};
emios1_pwm: pwm {
pinctrl-0 = <&emios1_default>;
pinctrl-names = "default";
status = "okay";
rgb_green {
channel = <10>;
master-bus = <&emios1_bus_a>;
duty-cycle = <0>;
pwm-mode = "OPWMB";
polarity = "ACTIVE_LOW";
};
rgb_blue {
channel = <5>;
master-bus = <&emios1_bus_f>;
duty-cycle = <0>;
pwm-mode = "OPWMB";
polarity = "ACTIVE_LOW";
};
};
};
&flexio0 {
status = "okay";
flexio0_pwm: flexio0_pwm {
pinctrl-0 = <&flexio0_pwm_default>;
pinctrl-names = "default";
status = "okay";
pwm_0 {
pin-id = <19>;
prescaler = <1>;
};
pwm_1 {
pin-id = <11>;
prescaler = <1>;
};
};
};
&lcu1 {
status = "okay";
};
&trgmux {
status = "okay";
};
&edma0 {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/mr_canhubk3.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,954 |
```unknown
;*******************************************************************************
; *
; Lauterbach TRACE32 start-up script for flashing mr_canhubk3 *
; *
;*******************************************************************************
ENTRY %LINE &args
DO ~~~~/startup.cmm command=flash &args
ENDDO
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/support/flash.cmm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
;*******************************************************************************
; *
; Lauterbach Trace32 start-up script for S32K344 / Cortex-M7 *
; *
; Parameters: *
; - command operation to execute *
; valid values: flash, debug *
; - elfFile filepath of ELF to load *
; - loadTo if "flash", the application will be downloaded to SoC *
; program flash by a flash programming routine; if "sram" it *
; will be downloaded to SoC SRAM. *
; valid values: flash, sram *
; default: flash *
; - eraseFlash if set to "yes", the whole content in Flash device will be *
; erased before the application is downloaded to either Flash *
; or SRAM. This routine takes time to execute *
; default: "no" *
; - verifyFlash if set to "yes", verify after program application to Flash *
; default: "no" *
;*******************************************************************************
ENTRY %LINE &args
&command=STRing.SCANAndExtract("&args","command=","")
&elfFile=STRing.SCANAndExtract("&args","elfFile=","")
&loadTo=STRing.SCANAndExtract("&args","loadTo=","flash")
&eraseFlash=STRing.SCANAndExtract("&args","eraseFlash=","no")
&verifyFlash=STRing.SCANAndExtract("&args","verifyFlash=","no")
IF ("&elfFile"=="")
(
PRINT %ERROR "Missing ELF file path"
PLIST
STOP
ENDDO
)
; Initialize debugger
RESet
SYStem.RESet
SYStem.CPU S32K344-M7
SYStem.CONFIG.DEBUGPORTTYPE JTAG
SYStem.Option.DUALPORT ON
SYStem.Option.DisMode THUMB
SYStem.MemAccess DAP
SYStem.JtagClock 10MHz
Trace.DISable
TrOnchip.Set MMERR OFF
TrOnchip.Set BUSERR OFF
SYStem.Up
; Init SRAM
DO ~~/demo/arm/hardware/s32k3/scripts/init_sram.cmm
; Only declares flash, does not execute flash programming
DO ~~/demo/arm/flash/s32k3.cmm PREPAREONLY
; The prepare cmm is protecting flash area for HSE firmware, but
; since HSE firmware usage feature is not enabled, this region can
; be used by application core, marked as programmable.
FLASH.CHANGEtype 0x007D4000--0x7F3FFF TARGET
IF ("&eraseFlash"=="yes")
(
FLASH.Erase ALL
)
IF ("&loadTo"=="flash")
(
; Switch target flash to reprogramming state, erase virtual flash programming memory,
; all target non-empty flash sectors are marked as pending, to be reprogrammed.
FLASH.ReProgram ALL /Erase
; Write contents of the file to virtual Flash programming memory
Data.LOAD.Elf &elfFile
; Program only changed sectors to target flash and erase obsolete code
FLASH.ReProgram off
IF ("&verifyFlash"=="yes")
(
Data.LOAD.Elf &elfFile /DIFF
IF FOUND()
(
AREA.view
PRINT %ERROR "ERROR ! Failed to download the code to flash"
Data.LOAD.Elf &elfFile /ComPare
ENDDO
)
)
; Reset the processor
SYStem.Up
)
ELSE
(
; Init ITCM
DO ~~/demo/arm/hardware/s32k3/scripts/init_itcm.cmm
Data.LOAD.Elf &elfFile
)
IF ("&command"=="flash")
(
; Execute the application and quit
Go
QUIT
)
ELSE IF ("&command"=="debug")
(
; Setup minimal debug environment
WinCLEAR
SETUP.Var.%SpotLight
WinPOS 0. 0. 120. 30.
List.auto
WinPOS 125. 0. 80. 10.
Frame.view
WinPOS 125. 18.
Register.view /SpotLight
)
ELSE
(
PRINT %ERROR "Invalid command"
)
ENDDO
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/support/startup.cmm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 934 |
```unknown
CONFIG_CONSOLE=y
CONFIG_RTT_CONSOLE=y
CONFIG_USE_SEGGER_RTT=y
CONFIG_PINCTRL=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000
CONFIG_OSC_EXTERNAL=y
``` | /content/code_sandbox/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```cmake
if (CONFIG_BOARD_HEXIWEAR_MK64F12)
board_runner_args(pyocd "--target=k64f")
board_runner_args(jlink "--device=MK64FN1M0xxx12")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
else()
board_runner_args(jlink "--device=MKW40Z160xxx4")
board_runner_args(pyocd "--target=kw40z4")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
endif()
``` | /content/code_sandbox/boards/nxp/hexiwear/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```unknown
/dts-v1/;
#include <nxp/nxp_k6x.dtsi>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include "hexiwear_mk64f12-pinctrl.dtsi"
/ {
model = "Hexiwear K64 board";
compatible = "nxp,hexiwear", "nxp,k64f", "nxp,k6x";
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
pwm-led0 = &green_pwm_led;
red-pwm-led = &red_pwm_led;
green-pwm-led = &green_pwm_led;
blue-pwm-led = &blue_pwm_led;
magn0 = &fxos8700;
accel0 = &fxos8700;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,bt-hci = &bt_hci_uart;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpioc 8 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
green_led: led_1 {
gpios = <&gpiod 0 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
blue_led: led_2 {
gpios = <&gpioc 9 GPIO_ACTIVE_LOW>;
label = "User LD3";
};
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: red_pwm_led {
pwms = <&ftm3 4 15625000 PWM_POLARITY_INVERTED>;
};
green_pwm_led: green_pwm_led {
pwms = <&ftm3 0 15625000 PWM_POLARITY_INVERTED>;
};
blue_pwm_led: blue_pwm_led {
pwms = <&ftm3 5 15625000 PWM_POLARITY_INVERTED>;
};
};
en_bat_sens: enable-battery-sense {
compatible = "regulator-fixed";
regulator-name = "en_bat_sens";
enable-gpios = <&gpioc 14 GPIO_ACTIVE_LOW>;
regulator-boot-on;
};
en_ldo: enable-ldo {
compatible = "regulator-fixed";
regulator-name = "en_ldo";
enable-gpios = <&gpioa 29 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
};
en_3v3b: enable-3v3b {
compatible = "regulator-fixed";
regulator-name = "en_3v3b";
enable-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>;
regulator-boot-on;
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
&cpu0 {
clock-frequency = <120000000>;
};
&adc0 {
status = "okay";
};
&adc1 {
status = "okay";
};
&ftm3 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
pinctrl-0 = <&ftm3_default>;
pinctrl-names = "default";
clock-source = "fixed";
};
&i2c0 {
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
max30101@57 {
status = "disabled";
compatible = "maxim,max30101";
reg = <0x57>;
};
};
&i2c1 {
status = "okay";
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
fxos8700: fxos8700@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
int1-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
};
fxas21002@20 {
compatible = "nxp,fxas21002";
reg = <0x20>;
int1-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpioc 18 GPIO_ACTIVE_LOW>;
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&uart4 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
bt_hci_uart: bt_hci_uart {
compatible = "zephyr,bt-hci-uart";
status = "okay";
};
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(8))>;
};
slot1_partition: partition@7a000 {
label = "image-1";
reg = <0x0007a000 DT_SIZE_K(416)>;
};
storage_partition: partition@e2000 {
label = "storage";
reg = <0x000e2000 DT_SIZE_K(120)>;
};
};
};
``` | /content/code_sandbox/boards/nxp/hexiwear/hexiwear_mk64f12.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,453 |
```yaml
identifier: hexiwear/mkw40z4
name: Hexiwear KW40Z
type: mcu
arch: arm
ram: 16
flash: 512
toolchain:
- zephyr
- gnuarmemb
- xtools
testing:
ignore_tags:
- net
vendor: nxp
``` | /content/code_sandbox/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```yaml
identifier: hexiwear/mk64f12
name: Hexiwear
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- ble
- gpio
- i2c
- pwm
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/hexiwear/hexiwear_mk64f12.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```yaml
board:
name: hexiwear
vendor: nxp
socs:
- name: mk64f12
- name: mkw40z4
``` | /content/code_sandbox/boards/nxp/hexiwear/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
CONFIG_OSC_LOW_POWER=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
``` | /content/code_sandbox/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
/dts-v1/;
#include <nxp/nxp_kw40z.dtsi>
#include "hexiwear_mkw40z4-pinctrl.dtsi"
/ {
model = "Hexiwear KW40 board";
compatible = "nxp,kw40z", "nxp,mkw40z4";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_OSC32KCLK>;
};
&adc0 {
status = "okay";
pinctrl-0 = <&adc0_default>;
pinctrl-names = "default";
};
&lpuart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&lpuart0_default>;
pinctrl-names = "default";
};
&gpioa {
status = "okay";
};
&gpioc {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/hexiwear/hexiwear_mkw40z4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 235 |
```unknown
config BOARD_HEXIWEAR
select SOC_MK64F12 if BOARD_HEXIWEAR_MK64F12
select SOC_PART_NUMBER_MK64FN1M0VDC12 if BOARD_HEXIWEAR_MK64F12
select SOC_MKW40Z4 if BOARD_HEXIWEAR_MKW40Z4
select SOC_PART_NUMBER_MKW40Z160VHT4 if BOARD_HEXIWEAR_MKW40Z4
``` | /content/code_sandbox/boards/nxp/hexiwear/Kconfig.hexiwear | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```unknown
# Hexiwear K64 board
if BOARD_HEXIWEAR_MK64F12
config OSC_XTAL0_FREQ
default 12000000
config MCG_PRDIV0
default 0x02
config MCG_VDIV0
default 0x06
config MCG_FCRDIV
default 1
config REGULATOR
default y if ADC || SENSOR
endif # BOARD_HEXIWEAR_MK64F12
# Hexiwear KW40Z board
if BOARD_HEXIWEAR_MKW40Z4
config OSC_XTAL0_FREQ
default 32000000
config MCG_FRDIV
default 5
config MCG_FCRDIV
default 0
endif # BOARD_HEXIWEAR_MKW40Z4
``` | /content/code_sandbox/boards/nxp/hexiwear/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 165 |
```unknown
/*
* NOTE: Autogenerated file by gen_board_pinctrl.py
* for MK64FN1M0VDC12/signal_configuration.xml
*
*/
#include <nxp/kinetis/MK64FN1M0VDC12-pinctrl.h>
&pinctrl {
ftm3_default: ftm3_default {
group0 {
pinmux = <FTM3_CH4_PTC8>,
<FTM3_CH0_PTD0>;
drive-strength = "low";
slew-rate = "fast";
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PTB0>,
<I2C0_SDA_PTB1>;
drive-strength = "low";
drive-open-drain;
slew-rate = "fast";
};
};
i2c1_default: i2c1_default {
group0 {
pinmux = <I2C1_SCL_PTC10>,
<I2C1_SDA_PTC11>;
drive-strength = "low";
drive-open-drain;
slew-rate = "fast";
};
};
uart0_default: uart0_default {
group0 {
pinmux = <UART0_RX_PTB16>,
<UART0_TX_PTB17>;
drive-strength = "low";
slew-rate = "fast";
};
};
uart4_default: uart4_default {
group0 {
pinmux = <UART4_RX_PTE25>,
<UART4_TX_PTE24>;
drive-strength = "low";
slew-rate = "fast";
};
};
};
``` | /content/code_sandbox/boards/nxp/hexiwear/hexiwear_mk64f12-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 386 |
```restructuredtext
.. _mr_canhubk3:
NXP MR-CANHUBK3
###############
Overview
********
`NXP MR-CANHUBK3`_ is an evaluation board for mobile robotics applications such
as autonomous mobile robots (AMR) and automated guided vehicles (AGV). It
features an `NXP S32K344`_ general-purpose automotive microcontroller based on
an Arm Cortex-M7 core (Lock-Step).
.. image:: img/mr_canhubk3_top.jpg
:align: center
:alt: NXP MR-CANHUBK3 (TOP)
Hardware
********
- NXP S32K344
- Arm Cortex-M7 (Lock-Step), 160 MHz (Max.)
- 4 MB of program flash, with ECC
- 320 KB RAM, with ECC
- Ethernet 100 Mbps, CAN FD, FlexIO, QSPI
- 12-bit 1 Msps ADC, 16-bit eMIOS timer
- `NXP FS26 Safety System Basis Chip`_
- Interfaces:
- Console UART
- 6x CAN FD
- 100Base-T1 Ethernet
- JST-GH connectors and I/O headers for I2C, SPI, GPIO,
PWM, etc.
More information about the hardware and design resources can be found at
`NXP MR-CANHUBK3`_ website.
Supported Features
==================
The ``mr_canhubk3`` board configuration supports the following hardware features:
============ ========== ================================
Interface Controller Driver/Component
============ ========== ================================
SIUL2 on-chip | pinctrl
| gpio
| external interrupt controller
WKPU on-chip interrupt controller
LPUART on-chip serial
QSPI on-chip flash
FLEXCAN on-chip can
LPI2C on-chip i2c
ADC SAR on-chip adc
LPSPI on-chip spi
WDT FS26 SBC watchdog
SWT on-chip watchdog
EMAC on-chip ethernet
mdio
eMIOS on-chip pwm
EDMA on-chip dma
FLEXIO PWM on-chip pwm
STM on-chip counter
============ ========== ================================
The default configuration can be found in the Kconfig file
:zephyr_file:`boards/nxp/mr_canhubk3/mr_canhubk3_defconfig`.
Connections and IOs
===================
Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high
bank, from pin 16 to 31. For example, ``PTA2`` is the pin 2 of ``gpioa_l`` (low
bank), and ``PTA20`` is the pin 4 of ``gpioa_h`` (high bank).
The GPIO controller provides the option to route external input pad interrupts
to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC.
By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller,
unless they are explicity configured to be directed to the WKPU interrupt
controller, as outlined in :zephyr_file:`dts/bindings/gpio/nxp,s32-gpio.yaml`.
To find information about which GPIOs are compatible with each interrupt
controller, refer to the device reference manual.
.. note::
It is important to highlight that the current board configuration lacks
support for wake-up events and power-management features. WKPU functionality
is restricted solely to serving as an interrupt controller.
LEDs
----
The MR-CANHUBK3 board has one user RGB LED:
======================= ===== ===== ===================================
Devicetree node Color Pin Pin Functions
======================= ===== ===== ===================================
led0 / user_led1_red Red PTE14 FXIO D7 / EMIOS0 CH19
led1 / user_led1_green Green PTA27 FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10
led2 / user_led1_blue Blue PTE12 FXIO D8 / EMIOS1 CH5
======================= ===== ===== ===================================
In addition to the RGB LED, the MR-CANHUBK3 board has six red LEDs, each located
next to one of the CAN connectors:
======================= ===== ===== ===================================
Devicetree node Color Pin Pin Functions
======================= ===== ===== ===================================
can_led0 Red PTC18 FXIO D6 / FXIO D12 / EMIOS2 CH12
can_led1 Red PTE5 FXIO D7 / EMIOS1 CH5 / EMIOS0 CH 19
can_led2 Red PTD20 EMIOS1 CH17 / EMIOS2 CH0
can_led3 Red PTB24 FXIO D5 / EMIOS1 CH20 / EMIOS2 CH20
can_led4 Red PTB26 FXIO D7 / EMIOS1 CH22 / EMIOS2 CH22
can_led5 Red PTD31 FXIO D6 / EMIOS2 CH22
======================= ===== ===== ===================================
The user can control the LEDs in any way. An output of ``0`` illuminates the LED.
Buttons
-------
The MR-CANHUBK3 board has two user buttons:
======================= ===== ===== ==============
Devicetree node Label Pin Pin Functions
======================= ===== ===== ==============
sw0 / user_button_1 SW1 PTD15 EIRQ31
sw0 / user_button_2 SW2 PTA25 EIRQ5 / WKPU34
======================= ===== ===== ==============
System Clock
============
The Arm Cortex-M7 (Lock-Step) are configured to run at 160 MHz.
Serial Console
==============
By default, the serial console is provided through ``lpuart2`` on the 7-pin
DCD-LZ debug connector ``P6``.
========= ===== ============
Connector Pin Pin Function
========= ===== ============
P6.2 PTA9 LPUART2_TX
P6.3 PTA8 LPUART2_RX
========= ===== ============
CAN
===
CAN is provided through FLEXCAN interface with 6 instances.
=============== ======= =============== =============
Devicetree node Pin Pin Function Bus Connector
=============== ======= =============== =============
flexcan0 | PTA6 | PTA6_CAN0_RX P12/P13
| PTA7 | PTA7_CAN0_TX
flexcan1 | PTC9 | PTC9_CAN0_RX P14/P15
| PTC8 | PTC8_CAN0_TX
flexcan2 | PTE25 | PTE25_CAN0_RX P16/P17
| PTE24 | PTE24_CAN0_TX
flexcan3 | PTC29 | PTC29_CAN0_RX P18/019
| PTC28 | PTC28_CAN0_TX
flexcan4 | PTC31 | PTC31_CAN0_RX P20/P21
| PTC30 | PTC30_CAN0_TX
flexcan5 | PTC11 | PTC11_CAN0_RX P22/P23
| PTC10 | PTC10_CAN0_TX
=============== ======= =============== =============
.. note::
There is limitation by HAL SDK, so CAN only has support maximum 64 message buffers (MBs)
and support maximum 32 message buffers for concurrent active instances with 8 bytes
payload. We need to pay attention to configuration options:
1. :kconfig:option:`CONFIG_CAN_MAX_MB` must be less or equal than the
maximum number of message buffers that is according to the table below.
2. :kconfig:option:`CONFIG_CAN_MAX_FILTER` must be less or equal than
:kconfig:option:`CONFIG_CAN_MAX_MB`.
=============== ========== ================ ================
Devicetree node Payload Hardware support Software support
=============== ========== ================ ================
flexcan0 | 8 bytes | 96 MBs | 64 MBs
| 16 bytes | 63 MBs | 42 MBs
| 32 bytes | 36 MBs | 24 MBs
| 64 bytes | 21 MBs | 14 MBs
flexcan1 | 8 bytes | 64 MBs | 64 MBs
| 16 bytes | 42 MBs | 42 MBs
| 32 bytes | 24 MBs | 24 MBs
| 64 bytes | 14 MBs | 14 MBs
flexcan2 | 8 bytes | 64 MBs | 64 MBs
| 16 bytes | 42 MBs | 42 MBs
| 32 bytes | 24 MBs | 24 MBs
| 64 bytes | 14 MBs | 14 MBs
flexcan3 | 8 bytes | 32 MBs | 32 MBs
| 16 bytes | 21 MBs | 21 MBs
| 32 bytes | 12 MBs | 12 MBs
| 64 bytes | 7 MBs | 7 MBs
flexcan4 | 8 bytes | 32 MBs | 32 MBs
| 16 bytes | 21 MBs | 21 MBs
| 32 bytes | 12 MBs | 12 MBs
| 64 bytes | 7 MBs | 7 MBs
flexcan5 | 8 bytes | 32 MBs | 32 MBs
| 16 bytes | 21 MBs | 21 MBs
| 32 bytes | 12 MBs | 12 MBs
| 64 bytes | 7 MBs | 7 MBs
=============== ========== ================ ================
.. note::
A CAN bus usually requires 120 Ohm termination at both ends of the bus. This may be
accomplished using one of the included CAN termination boards. For more details, refer
to the section ``6.3 CAN Connectors`` in the Hardware User Manual of `NXP MR-CANHUBK3`_.
I2C
===
I2C is provided through LPI2C interface with 2 instances ``lpi2c0`` and ``lpi2c1``
on corresponding connectors ``P4``, ``P3``.
========= ===== ============
Connector Pin Pin Function
========= ===== ============
P3.2 PTD9 LPI2C1_SCL
P3.3 PTD8 LPI2C1_SDA
P4.3 PTD14 LPI2C0_SCL
P4.4 PTD13 LPI2C0_SDA
========= ===== ============
The accompanying display board can be connected to ``lpi2c0`` via connector ``P4``.
ADC
===
ADC is provided through ADC SAR controller with 3 instances. ADC channels are divided into
3 groups (precision, standard and external).
.. note::
All channels of an instance only run on 1 group channel at the same time.
FS26 SBC Watchdog
=================
On normal operation after the board is powered on, there is a window of 256 ms
on which the FS26 watchdog must be serviced with a good token refresh, otherwise
the watchdog will signal a reset to the MCU. This board configuration enables
the FS26 watchdog driver that handles this initialization.
.. note::
The FS26 can also be started in debug mode (watchdog disabled) following
these steps:
1. Power off the board.
2. Remove the jumper ``JP1`` (pins 1-2 open), which is connected by default.
3. Power on the board.
4. Reconnect the jumper ``JP1`` (pins 1-2 shorted).
External Flash
==============
The on-board MX25L6433F 64M-bit multi-I/O Serial NOR Flash memory is connected
to the QSPI controller port A1. This board configuration selects it as the
default flash controller.
Ethernet
========
This board has a single instance of Ethernet Media Access Controller (EMAC)
interfacing with a `NXP TJA1103`_ 100Base-T1 Ethernet PHY. Currently, there is
limited driver for this PHY that allows for overiding the default pin strapping configuration for
the PHY (RMII, master, autonomous mode enabled, polarity correction enabled)
to slave mode.
The 100Base-T1 signals are available in connector ``P9`` and can be converted to
100Base-T using a Ethernet media converter such as `RDDRONE-T1ADAPT`_.
Programming and Debugging
*************************
Applications for the ``mr_canhubk3`` board can be built in the usual way as
documented in :ref:`build_an_application`.
This board configuration supports `Lauterbach TRACE32`_, `SEGGER J-Link`_ and `pyOCD`_
West runners for flashing and debugging applications. Follow the steps described
in :ref:`lauterbach-trace32-debug-host-tools`, :ref:`jlink-debug-host-tools` and
:ref:`pyocd-debug-host-tools`,
to setup the flash and debug host tools for these runners, respectively. The
default runner is J-Link.
Flashing
========
Run the ``west flash`` command to flash the application using SEGGER J-Link.
Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32, or
``west flash -r pyocd``` to use pyOCD.
The Lauterbach TRACE32 runner supports additional options that can be passed
through command line:
.. code-block:: console
west flash -r trace32 --startup-args elfFile=<elf_path> loadTo=<flash/sram>
eraseFlash=<yes/no> verifyFlash=<yes/no>
Where:
- ``<elf_path>`` is the path to the Zephyr application ELF in the output
directory
- ``loadTo=flash`` loads the application to the SoC internal program flash
(:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the
application to SRAM. Default is ``flash``.
- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the
application is downloaded to either Flash or SRAM. This routine takes time to
execute. Default is ``no``.
- ``verifyFlash=yes`` verify the SoC internal flash content after programming
(use together with ``loadTo=flash``). Default is ``no``.
For example, to erase and verify flash content:
.. code-block:: console
west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes
Debugging
=========
Run the ``west debug`` command to start a GDB session using SEGGER J-Link.
Alternatively, run ``west debug -r trace32`` or ``west debug -r pyocd``
to launch the Lauterbach TRACE32 or pyOCD software debugging interface respectively.
References
**********
.. target-notes::
.. _NXP MR-CANHUBK3:
path_to_url
.. _NXP S32K344:
path_to_url
.. _NXP FS26 Safety System Basis Chip:
path_to_url
.. _NXP TJA1103:
path_to_url
.. _RDDRONE-T1ADAPT:
path_to_url
.. _Lauterbach TRACE32:
path_to_url
.. _SEGGER J-Link:
path_to_url
.. _pyOCD:
path_to_url
``` | /content/code_sandbox/boards/nxp/mr_canhubk3/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,579 |
```unknown
/*
*/
#include <nxp/kinetis/MKW40Z160VHT4-pinctrl.h>
&pinctrl {
adc0_default: adc0_default {
group0 {
pinmux = <ADC0_SE1_PTB1>;
drive-strength = "low";
slew-rate = "fast";
};
};
lpuart0_default: lpuart0_default {
group0 {
pinmux = <UART0_RX_PTC6>,
<UART0_TX_PTC7>;
drive-strength = "low";
slew-rate = "fast";
};
};
};
``` | /content/code_sandbox/boards/nxp/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 140 |
```unknown
/*
* NOTE: Autogenerated file by gen_board_pinctrl.py
* for MKL25Z128VLK4/signal_configuration.xml
*
*/
#include <nxp/kinetis/MKL25Z128VLK4-pinctrl.h>
&pinctrl {
adc0_default: adc0_default {
group0 {
pinmux = <ADC0_SE12_PTB2>;
drive-strength = "low";
slew-rate = "slow";
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PTE24>,
<I2C0_SDA_PTE25>;
drive-strength = "low";
slew-rate = "slow";
};
};
uart0_default: uart0_default {
group0 {
pinmux = <UART0_RX_PTA1>,
<UART0_TX_PTA2>;
drive-strength = "low";
slew-rate = "slow";
};
};
};
``` | /content/code_sandbox/boards/nxp/frdm_kl25z/frdm_kl25z-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 232 |
```cmake
board_runner_args(jlink "--device=MKL25Z128xxx4")
board_runner_args(linkserver "--device=MKL25Z128xxx4:FRDM-KL25Z")
board_runner_args(pyocd "--target=kl25z")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/nxp/frdm_kl25z/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
config BOARD_FRDM_KL25Z
select SOC_MKL25Z4
select SOC_PART_NUMBER_MKL25Z128VLK4
``` | /content/code_sandbox/boards/nxp/frdm_kl25z/Kconfig.frdm_kl25z | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: frdm_kl25z
name: NXP FRDM-KL25Z
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
testing:
ignore_tags:
- net
- bluetooth
supported:
- adc
- arduino_gpio
- gpio
- i2c
- usb_device
vendor: nxp
``` | /content/code_sandbox/boards/nxp/frdm_kl25z/frdm_kl25z.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```unknown
/dts-v1/;
#include <nxp/nxp_kl25z.dtsi>
#include "frdm_kl25z-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP Freedom KL25Z board";
compatible = "nxp,frdm-kl25z", "nxp,kl25z", "nxp,mkl25z4";
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
sw0 = &user_button_0;
sw1 = &user_button_1;
accel0 = &mma8451q;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpiob 18 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
green_led: led_1 {
gpios = <&gpiob 19 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
blue_led: led_2 {
gpios = <&gpiod 1 GPIO_ACTIVE_LOW>;
label = "User LD3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_0: button_0 {
label = "User SW0";
gpios = <&gpioa 16 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_1: button_1 {
label = "User SW1";
gpios = <&gpioa 17 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpiob 0 0>, /* A0 */
<1 0 &gpiob 1 0>, /* A1 */
<2 0 &gpiob 2 0>, /* A2 */
<3 0 &gpiob 3 0>, /* A3 */
<4 0 &gpioc 2 0>, /* A4 */
<5 0 &gpioc 1 0>, /* A5 */
<6 0 &gpioa 1 0>, /* D0 */
<7 0 &gpioa 2 0>, /* D1 */
<8 0 &gpiod 4 0>, /* D2 */
<9 0 &gpioa 12 0>, /* D3 */
<10 0 &gpioa 4 0>, /* D4 */
<11 0 &gpioa 5 0>, /* D5 */
<12 0 &gpioc 8 0>, /* D6 */
<13 0 &gpioc 9 0>, /* D7 */
<14 0 &gpioa 13 0>, /* D8 */
<15 0 &gpiod 5 0>, /* D9 */
<16 0 &gpiod 0 0>, /* D10 */
<17 0 &gpiod 2 0>, /* D11 */
<18 0 &gpiod 3 0>, /* D12 */
<19 0 &gpiod 1 0>, /* D13 */
<20 0 &gpioe 0 0>, /* D14 */
<21 0 &gpioe 1 0>; /* D15 */
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_LPO1KHZ>;
};
&cpu0 {
clock-frequency = <48000000>;
};
&adc0 {
status = "okay";
pinctrl-0 = <&adc0_default>;
pinctrl-names = "default";
};
&i2c0 {
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
mma8451q: mma8451q@1d {
compatible = "nxp,fxos8700","nxp,mma8451q";
reg = <0x1d>;
int1-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpiod {
status = "okay";
};
zephyr_udc0: &usbotg {
compatible = "nxp,kinetis-usbd";
status = "okay";
num-bidir-endpoints = <8>;
};
``` | /content/code_sandbox/boards/nxp/frdm_kl25z/frdm_kl25z.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,221 |
```yaml
board:
name: frdm_kl25z
vendor: nxp
socs:
- name: mkl25z4
``` | /content/code_sandbox/boards/nxp/frdm_kl25z/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
# FRDM-KL25Z board
if BOARD_FRDM_KL25Z
config OSC_XTAL0_FREQ
default 8000000
config MCG_PRDIV0
default 0x01
config MCG_VDIV0
default 0x00
config MCG_FRDIV
default 5
config MCG_FCRDIV
default 0
if FXOS8700
choice FXOS8700_MODE
default FXOS8700_MODE_ACCEL
endchoice
endif # FXOS8700
endif # BOARD_FRDM_KL25Z
``` | /content/code_sandbox/boards/nxp/frdm_kl25z/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```unknown
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
CONFIG_OSC_LOW_POWER=y
``` | /content/code_sandbox/boards/nxp/frdm_kl25z/frdm_kl25z_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```restructuredtext
.. _hexiwear:
Hexiwear
########
Overview
********
Hexiwear is powered by a Kinetis K64 microcontroller based on the ARM Cortex-M4
core. Another Kinetis wireless MCU, the KW40Z, provides Bluetooth Low Energy
connectivity. Hexiwear also integrates a wide variety of sensors, as well as a
user interface consisting of a 1.1" 96px x 96px full color OLED display and six
capacitive buttons with haptic feedback.
- Eye-catching Smart Watch form factor with powerful, low power Kinetis K6x MCU
and 6 on-board sensors.
- Designed for wearable applications with the onboard rechargeable battery,
OLED screen and onboard sensors such as optical heart rate, accelerometer,
magnetometer and gyroscope.
- Designed for IoT end node applications with the onboard sensor's such as
temperature, pressure, humidity and ambient light.
- Flexibility to let you add the sensors of your choice nearly 200 additional
sensors through click boards.
.. image:: hexiwear_k64.jpg
:align: center
:alt: Hexiwear
Hardware
********
- Main MCU: NXP Kinetis K64x (ARM Cortex-M4, 120 MHz, 1M Flash, 256K SRAM)
- Wireless MCU: NXP Kinetis KW4x (ARM Cortex-M0+, Bluetooth Low Energy &
802.15.4 radio)
- 6-axis combo Accelerometer and Magnetometer NXP FXOS8700
- 3-Axis Gyroscope: NXP FXAS21002
- Absolute Pressure sensor NXP MPL3115
- Li-Ion/Li-Po Battery Charger NXP MC34671
- Optical heart rate sensor Maxim MAX30101
- Ambient Light sensor, Humidity and Temperature sensor
- 1.1" full color OLED display
- Haptic feedback engine
- 190 mAh 2C Li-Po battery
- Capacitive touch interface
- RGB LED
For more information about the K64F SoC and Hexiwear board:
- `K64F Website`_
- `K64F Datasheet`_
- `K64F Reference Manual`_
- `Hexiwear Website`_
- `Hexiwear Fact Sheet`_
- `Hexiwear Schematics`_
Supported Features
==================
The hexiwear/mk64f12 board variant supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| SENSOR | off-chip | fxos8700 polling; |
| | | fxos8700 trigger; |
| | | fxas21002 polling; |
| | | fxas21002 trigger; |
| | | max30101 polling |
+-----------+------------+-------------------------------------+
| RNGA | on-chip | entropy; |
| | | random |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/hexiwear/hexiwear_mk64f12_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The K64F SoC has five pairs of pinmux/gpio controllers.
+-------+-----------------+---------------------------+
| Name | Function | Usage |
+=======+=================+===========================+
| PTA29 | GPIO | LDO_EN |
+-------+-----------------+---------------------------+
| PTB0 | I2C0_SCL | I2C / MAX30101 |
+-------+-----------------+---------------------------+
| PTB1 | I2C0_SDA | I2C / MAX30101 |
+-------+-----------------+---------------------------+
| PTB12 | GPIO | 3V3B EN |
+-------+-----------------+---------------------------+
| PTB16 | UART0_RX | UART Console |
+-------+-----------------+---------------------------+
| PTB17 | UART0_TX | UART Console |
+-------+-----------------+---------------------------+
| PTC8 | GPIO / PWM | Red LED |
+-------+-----------------+---------------------------+
| PTC9 | GPIO / PWM | Green LED |
+-------+-----------------+---------------------------+
| PTC10 | I2C1_SCL | I2C / FXOS8700 / FXAS21002|
+-------+-----------------+---------------------------+
| PTC11 | I2C1_SDA | I2C / FXOS8700 / FXAS21002|
+-------+-----------------+---------------------------+
| PTC14 | GPIO | Battery sense enable |
+-------+-----------------+---------------------------+
| PTC18 | GPIO | FXAS21002 INT2 |
+-------+-----------------+---------------------------+
| PTD0 | GPIO / PWM | Blue LED |
+-------+-----------------+---------------------------+
| PTD13 | GPIO | FXOS8700 INT2 |
+-------+-----------------+---------------------------+
| PTE24 | UART4_RX | UART BT HCI |
+-------+-----------------+---------------------------+
| PTE25 | UART4_TX | UART BT HCI |
+-------+-----------------+---------------------------+
.. note::
To enable battery sensing, you will need to enable the ``en_bat_sens``
regulator in Devicetree. Similarly, to enable devices connected to the 1V8
or 3V3 power rails (sensors), you will need to enable the ``en_ldo``
and ``en_3v3b`` regulators in Devicetree.
System Clock
============
The K64F SoC is configured to use the 12 MHz external oscillator on the board
with the on-chip PLL to generate a 120 MHz system clock.
Serial Port
===========
The K64F SoC has six UARTs. One is configured for the console, another for BT
HCI, and the remaining are not used.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`,
but because Segger RTT is required for a console on KW40Z, we recommend that
you reconfigure the board for the :ref:`opensda-jlink-onboard-debug-probe`.
.. note::
OpenSDA is shared between the K64 and the KW40Z via switches, therefore only
one SoC can be flashed, debugged, or have an open console at a time.
Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended)
your_sha256_hash
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program
the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches
SW1 and SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals
are connected to the OpenSDA microcontroller.
Option 2: :ref:`opensda-daplink-onboard-debug-probe`
----------------------------------------------------
Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to
program the `OpenSDA DAPLink Hexiwear Firmware`_. Check that switches SW1 and
SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals are
connected to the OpenSDA microcontroller.
Add the arguments ``-DBOARD_FLASH_RUNNER=pyocd`` and
``-DBOARD_DEBUG_RUNNER=pyocd`` when you invoke ``west build`` to override the
default runner from J-Link to pyOCD:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: hexiwear/mk64f12
:gen-args: -DBOARD_FLASH_RUNNER=pyocd -DBOARD_DEBUG_RUNNER=pyocd
:goals: build
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console.
Connect a USB cable from your PC to CN1.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: hexiwear/mk64f12
:goals: flash
Open a serial terminal, reset the board (press the T4 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! hexiwear
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: hexiwear/mk64f12
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! hexiwear
Using Bluetooth
***************
Configure the KW40Z as a Bluetooth controller
=============================================
The K64 can support Zephyr Bluetooth host applications when you configure the
KW40Z as a Bluetooth controller.
#. Download and install the `KW40Z Connectivity Software`_. This package
contains Bluetooth controller application for the KW40Z.
#. Flash the file ``tools/binaries/BLE_HCI_Modem.bin`` to the KW40Z.
Now you can build and run the sample Zephyr Bluetooth host applications on the
K64. You do not need to repeat this step each time you flash a new Bluetooth
host application to the K64.
Peripheral Heart Rate Sensor
============================
Navigate to the Zephyr ``samples/bluetooth/peripheral_hr`` sample
application, then build and flash it to the Hexiwear K64. Make sure
the OpenSDA switches on the docking station are configured for the
K64.
.. zephyr-app-commands::
:zephyr-app: samples/bluetooth/peripheral_hr
:board: hexiwear/mk64f12
:goals: build flash
Reset the KW40Z and the K64 using the push buttons on the docking station.
Install the Kinetis BLE Toolbox on your smartphone:
- `Kinetis BLE Toolbox for iOS`_
- `Kinetis BLE Toolbox for Android`_
Open the app, tap the **Heart Rate** feature, and you should see a **Zephyr
Heartrate Sensor** device. Tap the **Zephyr Heartrate Sensor** device and you
will then see a plot of the heart rate data that updates once per second.
.. _Hexiwear Website:
path_to_url
.. _Hexiwear Fact Sheet:
path_to_url
.. _Hexiwear Schematics:
path_to_url
.. _K64F Website:
path_to_url
.. _K64F Datasheet:
path_to_url
.. _K64F Reference Manual:
path_to_url
.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader:
path_to_url
.. _OpenSDA DAPLink Hexiwear Firmware:
path_to_url
.. _KW40Z Connectivity Software:
path_to_url
.. _Kinetis BLE Toolbox for iOS:
path_to_url
.. _Kinetis BLE Toolbox for Android:
path_to_url
Hexiwear KW40Z
##############
Overview
********
The KW40Z is a secondary SoC on the board that provides wireless connectivity
with a multimode BLE and 802.15.4 radio.
For more information about the KW40Z SoC:
- `KW40Z Website`_
- `KW40Z Datasheet`_
- `KW40Z Reference Manual`_
Supported Features
==================
The hexiwear/mkw40z4 board variant supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| RTT | on-chip | console |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The KW40Z SoC has three pairs of pinmux/gpio controllers, but only one is
currently enabled (PORTC/GPIOC) for the hexiwear/mkw40z4 board.
+-------+-----------------+---------------------------+
| Name | Function | Usage |
+=======+=================+===========================+
| PTB1 | ADC | ADC0 channel 1 |
+-------+-----------------+---------------------------+
| PTC6 | UART0_RX | UART BT HCI |
+-------+-----------------+---------------------------+
| PTC7 | UART0_TX | UART BT HCI |
+-------+-----------------+---------------------------+
System Clock
============
The KW40Z SoC is configured to use the 32 MHz external oscillator on the board
with the on-chip FLL to generate a 40 MHz system clock.
Serial Port
===========
The KW40Z SoC has one UART, which is used for BT HCI. There is no UART
available for a console.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`,
but because Segger RTT is required for a console, you must reconfigure the
board for one of the following debug probes instead.
:ref:`opensda-jlink-onboard-debug-probe`
----------------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program
the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches
SW1 and SW2 are **off**, and SW3 and SW4 are **on** to ensure KW40Z SWD signals
are connected to the OpenSDA microcontroller.
Configuring a Console
=====================
The console is available using `Segger RTT`_.
Connect a USB cable from your PC to CN1.
Once you have started a debug session, run telnet:
.. code-block:: console
$ telnet localhost 19021
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
SEGGER J-Link V6.44 - Real time terminal output
J-Link OpenSDA 2 compiled Feb 28 2017 19:27:57 V1.0, SN=621000000
Process: JLinkGDBServerCLExe
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: hexiwear/mkw40z4
:goals: flash
The Segger RTT console is only available during a debug session. Use ``attach``
to start one:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: hexiwear/mkw40z4
:goals: attach
Run telnet as shown earlier, and you should see the following message in the
terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! hexiwear
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: hexiwear/mkw40z4
:goals: debug
Run telnet as shown earlier, step through the application in your debugger, and
you should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! hexiwear
.. _KW40Z Website:
path_to_url
.. _KW40Z Datasheet:
path_to_url
.. _KW40Z Reference Manual:
path_to_url
.. _Segger RTT:
path_to_url
.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader:
path_to_url
``` | /content/code_sandbox/boards/nxp/hexiwear/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,280 |
```restructuredtext
.. _frdm_kl25z:
NXP FRDM-KL25Z
##############
Overview
********
The Freedom KL25Z is an ultra-low-cost development platform for
Kinetis |reg| L Series KL1x (KL14/15) and KL2x (KL24/25) MCUs built
on ARM |reg| Cortex |reg|-M0+ processor.
The FRDM-KL25Z features include easy access to MCU I/O, battery-ready,
low-power operation, a standard-based form factor with expansion board
options and a built-in debug interface for flash programming and run-control.
.. image:: frdm_kl25z.jpg
:align: center
:alt: FRDM-KL25Z
Hardware
********
- MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP
- On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED
- OpenSDA debug interface
For more information about the KL25Z SoC and FRDM-KL25Z board:
- `KL25Z Website`_
- `KL25Z Datasheet`_
- `KL25Z Reference Manual`_
- `FRDM-KL25Z Website`_
- `FRDM-KL25Z User Guide`_
- `FRDM-KL25Z Schematics`_
Supported Features
==================
The frdm_kl25z board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/frdm_kl25z/frdm_kl25z_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The KL25Z SoC has five pairs of pinmux/gpio controllers, and all are currently enabled
(PORTA/GPIOA, PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE) for the FRDM-KL25Z board.
+-------+-------------+---------------------------+
| Name | Function | Usage |
+=======+=============+===========================+
| PTB2 | ADC | ADC0 channel 12 |
+-------+-------------+---------------------------+
| PTB18 | GPIO | Red LED |
+-------+-------------+---------------------------+
| PTB19 | GPIO | Green LED |
+-------+-------------+---------------------------+
| PTD1 | GPIO | Blue LED |
+-------+-------------+---------------------------+
| PTA1 | UART0_RX | UART Console |
+-------+-------------+---------------------------+
| PTA2 | UART0_TX | UART Console |
+-------+-------------+---------------------------+
| PTE24 | I2C0_SCL | I2C |
+-------+-------------+---------------------------+
| PTE25 | I2C0_SDA | I2C |
+-------+-------------+---------------------------+
System Clock
============
The KL25Z SoC is configured to use the 8 MHz external oscillator on the board
with the on-chip FLL to generate a 48 MHz system clock.
Serial Port
===========
The KL25Z UART0 is used for the console.
USB
===
The KL25Z SoC has a USB OTG (USBOTG) controller that supports both
device and host functions through its mini USB connector (USB KL25Z).
Only USB device function is supported in Zephyr at the moment.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`.
Early versions of this board have an outdated version of the OpenSDA bootloader
and require an update. Please see the `DAPLink Bootloader Update`_ page for
instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader.
Option 1: Linkserver: :ref:`opensda-daplink-onboard-debug-probe` (Recommended)
your_sha256_hash--------------
Install the :ref:`linkserver-debug-host-tools` and make sure they are in your
search path. LinkServer works with the CMSIS-DAP debug firmware. Please follow the
instructions on :ref:`opensda-daplink-onboard-debug-probe` and select the latest revision
of the firmware image.
Linkserver is the default for this board, ``west flash`` and ``west debug`` will
call the linkserver runner.
.. code-block:: console
west flash
west debug
Option 2: :ref:`opensda-jlink-onboard-debug-probe`
--------------------------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program
the `OpenSDA J-Link FRDM-KL25Z Firmware`_.
Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and
``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the
default runner from pyOCD to J-Link:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_kl25z
:gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink
:goals: build
Note:
-----
The runners supported by NXP are LinkServer and JLink. pyOCD is another potential option,
but NXP does not test or support the pyOCD runner.
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console.
Connect a USB cable from your PC to J7.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_kl25z
:goals: flash
Open a serial terminal, reset the board (press the SW1 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! frdm_kl25z
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_kl25z
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! frdm_kl25z
.. _FRDM-KL25Z Website:
path_to_url
.. _FRDM-KL25Z User Guide:
path_to_url
.. _FRDM-KL25Z Schematics:
path_to_url
.. _KL25Z Website:
path_to_url
.. _KL25Z Datasheet:
path_to_url
.. _KL25Z Reference Manual:
path_to_url
.. _DAPLink Bootloader Update:
path_to_url
.. _OpenSDA DAPLink FRDM-KL25Z Firmware:
path_to_url
.. _OpenSDA J-Link FRDM-KL25Z Firmware:
path_to_url
``` | /content/code_sandbox/boards/nxp/frdm_kl25z/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,977 |
```cmake
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1 |
```restructuredtext
.. _boards-firefly:
Firefly
#######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/firefly/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# Platform Configuration
CONFIG_ARM_ARCH_TIMER=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# ARMv8 NS world with cache management
CONFIG_ARMV8_A_NS=y
CONFIG_CACHE_MANAGEMENT=y
# Clock support
CONFIG_CLOCK_CONTROL=y
CONFIG_TICKLESS_KERNEL=y
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```unknown
config BOARD_ROC_RK3568_PC
select SOC_RK3568
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/Kconfig.roc_rk3568_pc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```unknown
/*
*/
/dts-v1/;
#include <arm64/rockchip/rk3568.dtsi>
#include <common/mem.h>
/ {
model = "Firefly ROC-RK3568-PC";
compatible = "rockchip,rk3568";
chosen {
zephyr,console = &uart2;
zephyr,shell-uart = &uart2;
zephyr,sram = &sram0;
};
sram0: memory@40000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x40000000 DT_SIZE_M(1)>;
};
};
&uart2 {
status = "okay";
current-speed = <1500000>;
};
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/roc_rk3568_pc.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 162 |
```yaml
identifier: roc_rk3568_pc
name: Rockchip ROC RK3568 PC
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 1024
testing:
ignore_tags:
- net
- bluetooth
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/roc_rk3568_pc.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```yaml
identifier: roc_rk3568_pc/rk3568/smp
name: Rockchip ROC RK3568 PC SMP
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 1024
supported:
- smp
testing:
ignore_tags:
- net
- bluetooth
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```yaml
board:
name: roc_rk3568_pc
vendor: firefly
socs:
- name: rk3568
variants:
- name: smp
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```unknown
/*
*
*/
#include "roc_rk3568_pc.dts"
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```unknown
# Platform Configuration
CONFIG_ARM_ARCH_TIMER=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# ARMv8 NS world with cache management
CONFIG_ARMV8_A_NS=y
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE=y
# Clock support
CONFIG_CLOCK_CONTROL=y
CONFIG_TICKLESS_KERNEL=y
# SMP support
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=4
CONFIG_MAX_THREAD_BYTES=4
# PSCI support
CONFIG_PM_CPU_OPS=y
CONFIG_PM_CPU_OPS_PSCI=y
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```restructuredtext
.. _boards-toradex:
Toradex
#######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/toradex/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_imx8ml_m7.dtsi>
#include "verdin_imx8mp-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Toradex Verdin iMX8M Plus M7";
compatible = "nxp,mimx8mp_evk";
chosen {
/* TCM */
zephyr,flash = &itcm;
zephyr,sram = &dtcm;
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
};
};
&gpio3 {
status = "okay";
};
&mailbox0 {
status = "okay";
};
&uart1 {
current-speed = <115200>;
pinctrl-0 = <&uart1_default>;
pinctrl-names = "default";
};
&uart4 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 236 |
```cmake
#
#
#
board_set_debugger_ifnset(jlink)
board_set_flasher_ifnset(jlink)
board_runner_args(jlink "--device=MIMX8ML8_M7")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```yaml
#
#
#
identifier: verdin_imx8mp/mimx8ml8/m7/ddr
name: Toradex Verdin iMX8M Plus (DDR)
type: mcu
arch: arm
ram: 2048
flash: 2048
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- uart
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```unknown
#
#
#
CONFIG_CLOCK_CONTROL=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_XIP=y
CONFIG_CODE_DDR=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
# VERDIN_IMX8MP board
config BOARD_VERDIN_IMX8MP
select SOC_MIMX8ML8_M7 if BOARD_VERDIN_IMX8MP_MIMX8ML8_M7 || BOARD_VERDIN_IMX8MP_MIMX8ML8_M7_DDR
select SOC_PART_NUMBER_MIMX8ML8DVNLZ
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```yaml
board:
name: verdin_imx8mp
vendor: toradex
socs:
- name: mimx8ml8
variants:
- name: ddr
cpucluster: m7
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```restructuredtext
.. _roc_rk3568_pc:
Firefly ROC-RK3568-PC (Quad-core Cortex-A55)
############################################
Overview
********
The ROC-RK3568-PC is a Quad-Core 64-Bit Mini Computer, which supports 4G large RAM. M.2
and SATA3.0 interfaces enables expansion with large hard drives.
Providing dual Gigabit Ethernet ports, it supports WiFi 6 wireless transmission.
Control Port can be connected with RS485/RS232 devices.
RK3568 quad-core 64-bit Cortex-A55 processor, with brand new ARM v8.2-A architecture,
has frequency up to 2.0GHz. Zephyr OS is ported to run on it.
- Board features:
- RAM: 4GB LPDDR4
- Storage:
- 32GB eMMC
- M.2 PCIe 3.0 x 1 (Expand with 2242 / 2280 NVMe SSD)
- TF-Card Slot
- Wireless:
- Supports WiFi 6 (802.11 AX)
- Supports BT5.0
- USB:
- One USB 3.0
- Two USB 2.0
- One Type-C
- Ethernet
- M.2 PCIe3.0 (Expand with NVMe SSD)
- LEDs:
- 1x Power status LED
- Debug
- UART debug ports for board
Supported Features
==================
The Zephyr roc_rk3568_pc board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| GIC-v3 | on-chip | interrupt controller |
+-----------+------------+-------------------------------------+
| ARM TIMER | on-chip | system clock |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 24 MHz.
Cortex-A55 Core runs up to 2.0 GHz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART2.
Programming and Debugging
*************************
Use U-Boot to load the zephyr.bin to the memory and kick it:
.. code-block:: console
tftp 0x40000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x40000000
Use this configuration to run basic Zephyr applications and kernel tests,
for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: roc_rk3568_pc
:goals: run
This will build an image with the synchronization sample app, boot it and
display the following ram console output:
.. code-block:: console
*** Booting Zephyr OS build bc695c6df5eb ***
thread_a: Hello World from cpu 0 on roc_rk3568_pc!
thread_b: Hello World from cpu 0 on roc_rk3568_pc!
thread_a: Hello World from cpu 0 on roc_rk3568_pc!
thread_b: Hello World from cpu 0 on roc_rk3568_pc!
``roc_rk3568_pc//smp`` support, use this configuration to run Zephyr smp applications and subsys tests,
for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: roc_rk3568_pc//smp
:goals: run
This will build an image with the shell_module sample app, boot it and
display the following ram console output:
.. code-block:: console
*** Booting Zephyr OS build bc695c6df5eb ***
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
I/TC: Secondary CPU 2 initializing
I/TC: Secondary CPU 2 switching to normal world boot
I/TC: Secondary CPU 3 initializing
I/TC: Secondary CPU 3 switching to normal world boot
Secondary CPU core 1 (MPID:0x100) is up
Secondary CPU core 2 (MPID:0x200) is up
Secondary CPU core 3 (MPID:0x300) is up
thread_a: Hello World from cpu 0 on roc_rk3568_pc!
thread_b: Hello World from cpu 1 on roc_rk3568_pc!
thread_a: Hello World from cpu 0 on roc_rk3568_pc!
thread_b: Hello World from cpu 1 on roc_rk3568_pc!
References
==========
More information can refer to Firefly official website:
`Firefly website`_.
.. _Firefly website:
path_to_url
``` | /content/code_sandbox/boards/firefly/roc_rk3568_pc/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,120 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_imx8ml_m7.dtsi>
#include "verdin_imx8mp-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Toradex Verdin iMX8M Plus M7";
compatible = "nxp,mimx8mp_evk";
chosen {
/* DDR */
zephyr,flash = &ddr_code;
zephyr,sram = &ddr_sys;
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
};
};
&gpio3 {
status = "okay";
};
&mailbox0 {
status = "okay";
};
&uart1 {
current-speed = <115200>;
pinctrl-0 = <&uart1_default>;
pinctrl-names = "default";
};
&uart4 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 237 |
```unknown
#
#
#
CONFIG_CLOCK_CONTROL=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_XIP=y
CONFIG_CODE_ITCM=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
/*
*
*/
#include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
&pinctrl {
uart1_default: uart1_default {
group0 {
drive-strength = "x1";
pinmux = <&iomuxc_uart1_rxd_uart_rx_uart1_rx>,
<&iomuxc_uart1_txd_uart_tx_uart1_tx>;
slew-rate = "slow";
};
};
uart4_default: uart4_default {
group0 {
bias-pull-up;
drive-strength = "x1";
pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
slew-rate = "slow";
};
};
};
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/verdin_imx8mp-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 184 |
```yaml
#
#
#
identifier: verdin_imx8mp/mimx8ml8/m7
name: Toradex Verdin iMX8M Plus (ITCM)
type: mcu
arch: arm
ram: 128
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- uart
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_imx7d_m4.dtsi>
#include "colibri_imx7d-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "TORADEX Colibri IMX7D board";
compatible = "nxp,mcimx7d_m4";
aliases {
led0 = &green_led;
sw0 = &user_switch_1;
};
chosen {
zephyr,flash = &tcml_code;
zephyr,sram = &tcmu_sys;
zephyr,console = &uart2;
zephyr,shell-uart = &uart2;
};
leds {
compatible = "gpio-leds";
green_led: led_0 {
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
label = "User LED1";
};
};
gpio_keys {
compatible = "gpio-keys";
user_switch_1: user_sw_1 {
gpios = <&gpio2 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "User SW1";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&uart2 {
status = "okay";
current-speed = <115200>;
modem-mode = <64>;
pinctrl-0 = <&uart2_default>;
pinctrl-names = "default";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
};
&i2c2 {
pinctrl-0 = <&i2c2_default>;
pinctrl-names = "default";
};
&i2c3 {
pinctrl-0 = <&i2c3_default>;
pinctrl-names = "default";
};
&i2c4 {
pinctrl-0 = <&i2c4_default>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_default>;
pinctrl-names = "default";
status = "okay";
};
&pwm2 {
pinctrl-0 = <&pwm2_default>;
pinctrl-names = "default";
};
&pwm3 {
pinctrl-0 = <&pwm3_default>;
pinctrl-names = "default";
};
&pwm4 {
pinctrl-0 = <&pwm4_default>;
pinctrl-names = "default";
};
&mub {
status = "okay";
};
``` | /content/code_sandbox/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 589 |
```unknown
#
#
#
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_XIP=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```yaml
#
#
#
identifier: colibri_imx7d/mcimx7d/m4
name: TORADEX Colibri IMX7D
type: mcu
arch: arm
ram: 32
flash: 32
toolchain:
- zephyr
- gnuarmemb
- xtools
testing:
ignore_tags:
- net
- bluetooth
supported:
- pwm
vendor: nxp
``` | /content/code_sandbox/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```yaml
board:
name: colibri_imx7d
vendor: toradex
socs:
- name: mcimx7d
``` | /content/code_sandbox/boards/toradex/colibri_imx7d/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
#include <nxp/nxp_imx/mimx7d-pinctrl.dtsi>
&pinctrl {
uart2_default: uart2_default {
group0 {
pinmux = <&mx7d_pad_uart2_rx_data__uart2_dce_rx>,
<&mx7d_pad_uart2_tx_data__uart2_dce_tx>;
bias-pull-up;
bias-pull-up-value = "100k";
input-schmitt-enable;
slew-rate = "slow";
drive-strength = "x1";
};
};
i2c1_default: i2c1_default {
group0 {
pinmux = <&mx7d_pad_i2c1_scl__i2c1_scl>,
<&mx7d_pad_i2c1_sda__i2c1_sda>;
bias-pull-up;
bias-pull-up-value = "100k";
input-schmitt-enable;
slew-rate = "slow";
drive-strength = "x1";
};
};
i2c2_default: i2c2_default {
group0 {
pinmux = <&mx7d_pad_i2c2_scl__i2c2_scl>,
<&mx7d_pad_i2c2_sda__i2c2_sda>;
bias-pull-up;
bias-pull-up-value = "100k";
input-schmitt-enable;
slew-rate = "slow";
drive-strength = "x1";
};
};
i2c3_default: i2c3_default {
group0 {
pinmux = <&mx7d_pad_i2c3_scl__i2c3_scl>,
<&mx7d_pad_i2c3_sda__i2c3_sda>;
bias-pull-up;
bias-pull-up-value = "100k";
input-schmitt-enable;
slew-rate = "slow";
drive-strength = "x1";
};
};
i2c4_default: i2c4_default {
group0 {
pinmux = <&mx7d_pad_i2c4_scl__i2c4_scl>,
<&mx7d_pad_i2c4_sda__i2c4_sda>;
bias-pull-up;
bias-pull-up-value = "100k";
input-schmitt-enable;
slew-rate = "slow";
drive-strength = "x1";
};
};
pwm1_default: pwm1_default {
group0 {
pinmux = <&mx7d_pad_gpio1_io08__pwm1_out>;
bias-pull-up;
bias-pull-up-value = "100k";
input-schmitt-enable;
slew-rate = "slow";
drive-strength = "x1";
};
};
pwm2_default: pwm2_default {
group0 {
pinmux = <&mx7d_pad_gpio1_io09__pwm2_out>;
bias-pull-up;
bias-pull-up-value = "100k";
input-schmitt-enable;
slew-rate = "slow";
drive-strength = "x1";
};
};
pwm3_default: pwm3_default {
group0 {
pinmux = <&mx7d_pad_gpio1_io10__pwm3_out>;
bias-pull-up;
bias-pull-up-value = "100k";
input-schmitt-enable;
slew-rate = "slow";
drive-strength = "x1";
};
};
pwm4_default: pwm4_default {
group0 {
pinmux = <&mx7d_pad_gpio1_io11__pwm4_out>;
bias-pull-up;
bias-pull-up-value = "100k";
input-schmitt-enable;
slew-rate = "slow";
drive-strength = "x1";
};
};
};
``` | /content/code_sandbox/boards/toradex/colibri_imx7d/colibri_imx7d-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 907 |
```unknown
config BOARD_COLIBRI_IMX7D
select SOC_PART_NUMBER_MCIMX7D5EVM10SC
select SOC_MCIMX7D_M4 if BOARD_COLIBRI_IMX7D_MCIMX7D_M4
``` | /content/code_sandbox/boards/toradex/colibri_imx7d/Kconfig.colibri_imx7d | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```restructuredtext
.. _verdin_imx8mp:
Toradex Verdin iMX8M Plus SoM
#############################
Overview
********
The Verdin iMX8M Plus is a Computer on Module (CoM) developed by Toradex. It is based on the NXP
i.MX 8M Plus family of processors (or System on Chips - SoCs).
The Verdin iMX8M Plus family consists of:
+-------------------------------------------------+-----------------------+
| CoM | SoC |
+=================================================+=======================+
| Verdin iMX8M Plus Quad 8GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad |
+-------------------------------------------------+-----------------------+
| Verdin iMX8M Plus Quad 4GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad |
+-------------------------------------------------+-----------------------+
| Verdin iMX8M Plus Quad 4GB IT | i.MX 8M Plus Quad |
+-------------------------------------------------+-----------------------+
| Verdin iMX8M Plus Quad 2GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad |
+-------------------------------------------------+-----------------------+
| Verdin iMX8M Plus QuadLite 1GB IT | i.MX 8M Plus QuadLite |
+-------------------------------------------------+-----------------------+
Quoting NXP:
The i.MX 8M Plus family focuses on machine learning and vision, advanced multimedia, and
industrial automation with high reliability. It is built to meet the needs of Smart Home,
Building, City and Industry 4.0 applications.
The Verdin iMX8M Plus integrates a total of 4 Arm Cortex-A53 CPUs, operating at 1.6 GHz, alongside
a single Arm Cortex-M7F microcontroller operating at 800 MHz.
.. figure:: verdin_imx8mp_front.jpg
:align: center
:alt: Toradex Verdin iMX8M Plus
Toradex Verdin iMX8M Plus (Credit: Toradex)
Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and
energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1
memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary
functions. This cache is housed within a single APR region. Facilitating debugging processes, the
cores support both real-time trace through the ETM system and static debugging via JTAG.
Furthermore, the platform features support for real-time trace capabilities, achieved through ARM's
CoreSight ETM modules, and also enables cross-triggering by utilizing CTI and CTM modules.
The Arm Cortex-M7 microcontroller is indicated for Real-time control, combining high-performance
with a minimal interrupt latency. It stands out for its compatibility with existing Cortex-M profile
processors. The microcontroller employs an efficient in-order super-scalar pipeline, allowing
dual-issued instructions such as load/load and load/store pairs, thanks to its multiple memory
interfaces. These interfaces encompass Tightly-Coupled Memory (TCM), Harvard caches, and an AXI
master interface. The Arm Cortex-M7 Platform boasts features like a 32 KB L1 Instruction Cache, 32
KB L1 Data Cache, Floating Point Unit (FPU) with FPv5 architecture support, and an Internal Trace
(TRC) mechanism. Furthermore, the chip supports 160 IRQs, and integrates crucial Arm CoreSight
components including ETM and CTI, dedicated to facilitating debug and trace functions.
Hardware
********
- SoC name: NXP i.MX 8M Plus
- CPU Type: 4x Arm Cortex-A53 (1.6 GHz)
- Microcontroller: 1x Arm Cortex-M7F (800 MHz)
- Memory:
- RAM -> A53: 1GB, 2GB, 4GB or 8GB
- RAM -> M7: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
- Flash -> A53: Up to 32GB eMMC
- Connectivity:
- USB 3.1: 1x Host / 1x OTG (Gen 1)
- USB 2.0: 1x Host / 1x OTG
- Ethernet Gigabit with TSN (+2nd RGMII)
- Wi-Fi Dual-band 802.11ac 2x2 MU-MIMO
- Bluetooth 5
- 5x I2C
- 3x SPI
- 1 QSPI
- 4x UART
- Up to 92 GPIO
- 4x Analog Input
- 2x CAN (FlexCAN)
- Multimedia:
- Neural Processing Unit (NPU)
- Image Signal Processor (ISP)
- 2D and 3D acceleration
- HDMI, MIPI-DSI and MIPI-CSI interface
For more information about the Verdin iMX8M Plus and the i.MX 8M Plus SoC refer to these links:
- `i.MX 8M Plus Applications Processor page`_
- `Verdin iMX8M Plus homepage`_
- `Verdin iMX8M Plus developer page`_
- `Verdin Development Board developer page`_
- `Verdin iMX8M Plus Datasheet`_
- `Verdin Development Board Datasheet`_
Supported Features
==================
The Zephyr verdin_imx8mp_m7 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | GPIO output |
| | | GPIO input |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
- :zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig`, if you choose to use
the ITCM memory.
- :zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig`, if you choose to use
the DDR memory.
It is recommended to disable peripherals used by the M7 core on the Linux host.
Other hardware features are not currently supported by the port.
Connections and IOs
===================
UART
----
Zephyr is configured to use the UART4 by default, which is connected to the FTDI USB converter on
most Toradex carrier boards.
This is also the UART connected to WiFi/BT chip in modules that have the WiFi/BT chip. Therefore, if
UART4 is used, WiFI/BT will not work properly.
If the WiFi/BT is needed, then another UART should be used for Zephyr (UART1 for example). You can
change the UART by changing the ``zephyr,console`` and ``zephyr,shell-uart`` in the
:zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts` or
:zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts` file.
+---------------+-----------------+---------------------------+
| Board Name | SoC Name | Usage |
+===============+=================+===========================+
| UART_1 | UART1 | General purpose UART |
+---------------+-----------------+---------------------------+
| UART_4 | UART4 | Cortex-M4 debug UART |
+---------------+-----------------+---------------------------+
GPIO
----
All the GPIO banks available are enabled in the :zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`.
System Clock
============
The M7 Core is configured to run at a 800 MHz clock speed.
Serial Port
===========
The i.MX8M Plus SoC has four UARTs. UART_4 is configured for the console and the remaining are not
used/tested.
Programming and Debugging
*************************
The Verdin iMX8M Plus board doesn't have QSPI flash for the M7, and it needs to be started by the
A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in
reset, set the M7 Program Counter and Stack Pointer, and get the M7 out of reset. The A53 can
perform these steps at bootloader level or after the Linux system has booted.
The M7 can use up to 3 different RAMs (currently, only two configurations are supported: ITCM and
DDR). These are the memory mapping for A53 and M7:
+------------+-------------------------+------------------------+-----------------------+----------------------+
| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size |
+============+=========================+========================+=======================+======================+
| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
For more information about memory mapping see the `i.MX 8M Plus Applications Processor Reference
Manual`_ (section 2.1 to 2.3)
At compilation time you have to choose which RAM will be used. To facilitate this process, there are
two targets available:
- ``verdin_imx8mp/mimx8ml8/m7``, which uses the ITCM configuration.
- ``verdin_imx8mp/mimx8ml8/m7/ddr``, which uses the DDR configuration.
Starting the Cortex-M7 via U-Boot
=================================
Load and run Zephyr on M7 from A53 using u-boot by copying the compiled ``zephyr.bin`` to the first
FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot
execution at prompt.
Load the M7 binary onto the desired memory and start its execution using:
ITCM
====
Loading the binary from an EXT4 partition:
.. code-block:: shell
ext4load mmc 2:2 ${loadaddr} /<path-to-binary>/zephyr.bin
cp.b ${loadaddr} 0x7e0000 <size_of_binary_in_bytes>
bootaux 0x7e0000
DDR
===
Loading the binary from an EXT4 partition:
.. code-block:: shell
ext4load mmc 2:2 ${loadaddr} /<path-to-binary>/zephyr.bin
cp.b ${loadaddr} 0x80000000 <size_of_binary_in_bytes>
bootaux 0x80000000
Debugging
=========
Toradex Verdin iMX8M Plus SoM can be debugged by connecting an external JLink JTAG debugger to the
X56 debug connector and to the PC, or simply connecting a USB-C to X66 on the Verdin Development
Board. Then, the application can be debugged using the usual way.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: verdin_imx8mp/mimx8ml8/m7/ddr
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v3.4.0-2300-g03905f7e55d2 ***
Hello World! verdin_imx8mp
References
==========
- `How to Load Compiled Binaries into Cortex-M`_
- `Cortex-M JTAG Debugging`_
- `NXP website`_
.. _NXP website:
path_to_url
.. _i.MX 8M Plus Applications Processor Reference Manual:
path_to_url
.. _How to Load Compiled Binaries into Cortex-M:
path_to_url
.. _Cortex-M JTAG Debugging:
path_to_url
.. _i.MX 8M Plus Applications Processor page:
path_to_url
.. _Verdin iMX8M Plus homepage:
path_to_url
.. _Verdin iMX8M Plus developer page:
path_to_url
.. _Verdin Development Board developer page:
path_to_url
.. _Verdin iMX8M Plus Datasheet:
path_to_url
.. _Verdin Development Board Datasheet:
path_to_url
``` | /content/code_sandbox/boards/toradex/verdin_imx8mp/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,177 |
```unknown
/*
*
*/
#include "waveshare_epaper_common.dtsi"
/ {
chosen {
zephyr,display = &uc8176_waveshare_epaper_gdew042t2;
};
mipi_dbi_waveshare_epaper_gdew042t2 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
write-only;
#address-cells = <1>;
#size-cells = <0>;
uc8176_waveshare_epaper_gdew042t2: uc8176@0 {
compatible = "gooddisplay,gdew042t2", "ultrachip,uc8176";
mipi-max-frequency = <4000000>;
reg = <0>;
width = <400>;
height = <300>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
softstart = [17 17 17];
full {
pwr = [03 00 26 26 09];
cdi = <0xd7>;
tcon = <0x22>;
};
};
};
};
``` | /content/code_sandbox/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 307 |
```unknown
/*
*
*/
#include "waveshare_epaper_common.dtsi"
/ {
chosen {
zephyr,display = &ssd16xx_waveshare_epaper_gdeh0154a07;
};
mipi_dbi_waveshare_epaper_gdeh0154a07 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
#address-cells = <1>;
#size-cells = <0>;
ssd16xx_waveshare_epaper_gdeh0154a07: ssd16xxfb@0 {
compatible = "gooddisplay,gdeh0154a07", "solomon,ssd1681";
mipi-max-frequency = <4000000>;
reg = <0>;
width = <200>;
height = <200>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
tssv = <0x80>;
full {
border-waveform = <0x05>;
};
partial {
border-waveform = <0x3c>;
};
};
};
};
``` | /content/code_sandbox/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0154a07.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 303 |
```unknown
config SHIELD_WAVESHARE_EPAPER_GDEH029A1
def_bool $(shields_list_contains,waveshare_epaper_gdeh029a1)
config SHIELD_WAVESHARE_EPAPER_GDEH0213B1
def_bool $(shields_list_contains,waveshare_epaper_gdeh0213b1)
config SHIELD_WAVESHARE_EPAPER_GDEH0213B72
def_bool $(shields_list_contains,waveshare_epaper_gdeh0213b72)
config SHIELD_WAVESHARE_EPAPER_GDEW075T7
def_bool $(shields_list_contains,waveshare_epaper_gdew075t7)
config SHIELD_WAVESHARE_EPAPER_GDEH0154A07
def_bool $(shields_list_contains,waveshare_epaper_gdeh0154a07)
config SHIELD_WAVESHARE_EPAPER_GDEW042T2
def_bool $(shields_list_contains,waveshare_epaper_gdew042t2)
config SHIELD_WAVESHARE_EPAPER_GDEW042T2_P
def_bool $(shields_list_contains,waveshare_epaper_gdew042t2-p)
config SHIELD_WAVESHARE_EPAPER_GDEY0213B74
def_bool $(shields_list_contains,waveshare_epaper_gdey0213b74)
``` | /content/code_sandbox/boards/shields/waveshare_epaper/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 300 |
```unknown
/*
*
*/
#include "waveshare_epaper_common.dtsi"
/ {
chosen {
zephyr,display = &uc8176_waveshare_epaper_gdew042t2_p;
};
mipi_dbi_waveshare_epaper_gdew042t2-p {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
write-only;
#address-cells = <1>;
#size-cells = <0>;
/*
* GoodDisplay GDEW042T2 with fast partial refresh. Based on
* configuration from GoodDisplay's Arduino example.
*/
uc8176_waveshare_epaper_gdew042t2_p: uc8176@0 {
compatible = "gooddisplay,gdew042t2", "ultrachip,uc8176";
mipi-max-frequency = <4000000>;
reg = <0>;
width = <400>;
height = <300>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
softstart = [ 17 17 17 ];
full {
cdi = <0x07>;
};
partial {
pwr = [ 03 02 2b 2b ];
cdi = <0x07>;
pll = <0x3c>;
vdcs = <0x08>;
lutc = [
00 01 0E 00 00 01
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00
];
lutww = [
00 01 0E 00 00 01
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
];
lutkw = [
20 01 0E 00 00 01
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
];
lutwk = [
10 01 0E 00 00 01
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
];
lutkk = [
00 01 0E 00 00 01
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00 00 00 00 00
];
};
};
};
};
``` | /content/code_sandbox/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2-p.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 917 |
```unknown
/*
*
*/
#include "waveshare_epaper_common.dtsi"
/ {
chosen {
zephyr,display = &ssd16xx_waveshare_epaper_gdeh0213b72;
};
mipi_dbi_waveshare_epaper_gdeh0213b72 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
#address-cells = <1>;
#size-cells = <0>;
ssd16xx_waveshare_epaper_gdeh0213b72: ssd16xxfb@0 {
compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a";
mipi-max-frequency = <4000000>;
reg = <0>;
width = <250>;
height = <120>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
full {
gdv = [15];
sdv = [41 a8 32];
vcom = <0x55>;
border-waveform = <0x03>;
dummy-line = <0x30>;
gate-line-width = <0x0a>;
lut = [
80 60 40 00 00 00 00
10 60 20 00 00 00 00
80 60 40 00 00 00 00
10 60 20 00 00 00 00
00 00 00 00 00 00 00
03 03 00 00 02
09 09 00 00 02
03 03 00 00 02
00 00 00 00 00
00 00 00 00 00
00 00 00 00 00
00 00 00 00 00
];
};
partial {
gdv = [15];
sdv = [41 a8 32];
vcom = <0x26>;
border-waveform = <0x01>;
dummy-line = <0x30>;
gate-line-width = <0x0a>;
lut = [
00 00 00 00 00 00 00
80 00 00 00 00 00 00
40 00 00 00 00 00 00
80 00 00 00 00 00 00
00 00 00 00 00 00 00
0A 00 00 00 04
00 00 00 00 00
00 00 00 00 00
00 00 00 00 00
00 00 00 00 00
00 00 00 00 00
00 00 00 00 00
];
};
};
};
};
``` | /content/code_sandbox/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b72.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 736 |
```unknown
/*
*
*/
#include "waveshare_epaper_common.dtsi"
/ {
chosen {
zephyr,display = &ssd16xx_waveshare_epaper_gdey0213b74;
};
mipi_dbi_waveshare_epaper_gdey0213b74 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
#address-cells = <1>;
#size-cells = <0>;
ssd16xx_waveshare_epaper_gdey0213b74: ssd16xxfb@0 {
compatible = "gooddisplay,gdey0213b74", "solomon,ssd1680";
mipi-max-frequency = <4000000>;
reg = <0>;
width = <250>;
height = <122>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
tssv = <0x80>;
full {
border-waveform = <0x05>;
};
partial {
border-waveform = <0x3c>;
};
};
};
};
``` | /content/code_sandbox/boards/shields/waveshare_epaper/waveshare_epaper_gdey0213b74.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 303 |
```unknown
/*
*
*/
#include "waveshare_epaper_common.dtsi"
/ {
chosen {
zephyr,display = &ssd16xx_waveshare_epaper_gdeh0213b1;
};
mipi_dbi_waveshare_epaper_gdeh0213b1 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
#address-cells = <1>;
#size-cells = <0>;
ssd16xx_waveshare_epaper_gdeh0213b1: ssd16xxfb@0 {
compatible = "gooddisplay,gdeh0213b1", "solomon,ssd1673";
mipi-max-frequency = <4000000>;
reg = <0>;
width = <250>;
height = <120>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
full {
gdv = [10 0a];
sdv = [19];
vcom = <0xa8>;
border-waveform = <0x71>;
dummy-line = <0x1a>;
gate-line-width = <0x08>;
lut = [
22 55 AA 55 AA 55 AA 11
00 00 00 00 00 00 00 00
1E 1E 1E 1E 1E 1E 1E 1E
01 00 00 00 00
];
};
partial {
gdv = [10 0a];
sdv = [19];
vcom = <0xa8>;
border-waveform = <0x71>;
dummy-line = <0x1a>;
gate-line-width = <0x08>;
lut = [
18 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
0F 01 00 00 00 00 00 00
00 00 00 00 00
];
};
};
};
};
``` | /content/code_sandbox/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b1.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 542 |
```unknown
#
#
#
if SHIELD_WAVESHARE_EPAPER_GDEH029A1 || SHIELD_WAVESHARE_EPAPER_GDEH0213B1 || SHIELD_WAVESHARE_EPAPER_GDEH0213B72 || SHIELD_WAVESHARE_EPAPER_GDEW075T7 || SHIELD_WAVESHARE_EPAPER_GDEH0154A07 || SHIELD_WAVESHARE_EPAPER_GDEW042T2 || SHIELD_WAVESHARE_EPAPER_GDEW042T2_P || SHIELD_WAVESHARE_EPAPER_GDEY0213B74
if DISPLAY
if LVGL
config LV_Z_VDB_SIZE
default 16 if SHIELD_WAVESHARE_EPAPER_GDEW075T7
default 16
config LV_DPI_DEF
default 188 if SHIELD_WAVESHARE_EPAPER_GDEH0154A07
default 120 if SHIELD_WAVESHARE_EPAPER_GDEW042T2
default 130
choice LV_COLOR_DEPTH
default LV_COLOR_DEPTH_1
endchoice
config LV_Z_BITS_PER_PIXEL
default 1
endif # LVGL
endif # DISPLAY
endif # SHIELD_WAVESHARE_EPAPER_GDEH02
``` | /content/code_sandbox/boards/shields/waveshare_epaper/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 266 |
```restructuredtext
.. _colibri_imx7d:
NXP i.MX 7 Computer on Module - Colibri iMX7
############################################
Overview
********
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7
core and Single Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will also
communicate with the A7 core (running Linux) via RPmsg.
.. image:: colibri_imx7d.jpg
:align: center
:alt: Colibri-iMX7
Hardware
********
- i.MX7 Single/Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
- Memory
- RAM -> A7: 256MB, 512MB and 1GB
- RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
- Flash -> A7: 4Gb eMMC and 512Mb NAND
- Display
- RGB 1920x1080x24bpp
- 4-wire Resistive touch
- Multimedia
- 1x Camera Parallel Interface
- 1x Analog Audio Line in (Stereo)
- 1x Analog Audio Mic in (Mono)
- 1x Analog Audio Headphone out (Stereo)
- Connectivity
- USB 2.0 OTG (High Speed)
- USB 2.0 host (High Speed)
- 10/100 Mbit/s Ethernet PHY
- 4x I2C
- 4x SPI
- 7x UART
- 1x IrDA
- 20x PWM
- Up to 125 GPIO
- 4x Analog Input (12 Bit)
- 2x SDIO/SD/MMC (8 Bit)
- 2x CAN
For more information about the i.MX 7 SoC, Colibri iMX7 Computer on Module
and Colibri Evaluation Board, see these references:
- `i.MX 7 Series Website`_
- `i.MX 7 Dual Datasheet`_
- `i.MX 7 Dual Reference Manual`_
- `Colibri iMX7 Website`_
- `Colibri iMX7 User Guide`_
- `Colibri iMX7 Datasheet`_
- `Colibri Evaluation Board Website`_
- `Colibri Evaluation Board Datasheet`_
Supported Features
==================
The Colibri iMX7D Computer on Module with Colibri Evaluation Board configuration
supports the following hardware features on the Cortex M4 Core:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The Colibri iMX7D Computer on Module with Colibri Evaluation Board
was tested with the following pinmux controller configuration.
+---------------+-----------------+---------------------------+
| Board Name | SoC Name | Usage |
+===============+=================+===========================+
| UART_B RXD | UART2_TXD | UART Console |
+---------------+-----------------+---------------------------+
| UART_B TXD | UART2_RXD | UART Console |
+---------------+-----------------+---------------------------+
| SODIMM_135 | GPIO1_IO02 | LED0 |
+---------------+-----------------+---------------------------+
| SODIMM_133 | GPIO2_IO26 | SW0 |
+---------------+-----------------+---------------------------+
| SODIMM_194 | I2C4_SDA | I2C_SDA |
+---------------+-----------------+---------------------------+
| SODIMM_196 | I2C4_SCL | I2C_SCL |
+---------------+-----------------+---------------------------+
| SODIMM_59 | PWM1/GPIO1_IO08 | PWM |
+---------------+-----------------+---------------------------+
System Clock
============
The M4 Core is configured to run at a 200 MHz clock speed.
Serial Port
===========
The iMX7D SoC has seven UARTs. The number 2 is configured for the console and
the remaining are not used/tested.
Programming and Debugging
*************************
The Colibri iMX7D doesn't have QSPI flash for the M4 and it needs to be started by
the A7 core. The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get
the M4 out of reset.
The A7 can perform these steps at bootloader level or after the Linux system has
booted.
The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4:
+------------+-----------------------+------------------------+-----------------------+----------------------+
| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size |
+============+=======================+========================+=======================+======================+
| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
References
==========
- `i.MX 7 Dual Reference Manual`_ from page 190 (section 2.1.2 and 2.1.3)
- `Toradex Wiki`_
At compilation time you have to choose which RAM will be used. This configuration is
done in the file :zephyr_file:`boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts`
with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram"
properties. The available configurations are:
.. code-block:: none
"zephyr,flash"
- &ddr_code
- &tcml_code
- &ocram_code
- &ocram_s_code
- &ocram_pxp_code
- &ocram_epdc_code
"zephyr,sram"
- &ddr_sys
- &tcmu_sys
- &ocram_sys
- &ocram_s_sys
- &ocram_pxp_sys
- &ocram_epdc_sys
Below you will find the instructions to load and run Zephyr on M4 from A7 using u-boot.
Copy the compiled zephyr.bin to the first EXT partition of the SD card and plug into the
board. Power it up and stop the u-boot execution.
Set the u-boot environment variables and run the zephyr.bin from the appropriated memory
configured in the Zephyr compilation:
.. code-block:: console
setenv bootm4 'ext4load mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr'
# TCML
setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000'
setenv bootm4tcml 'run m4tcml && run bootm4'
run bootm4tcml
# TCMU
setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000'
setenv bootm4tcmu 'run m4tcmu && run bootm4'
run bootm4tcmu
# OCRAM
setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000'
setenv bootm4ocram 'run m4ocram && run bootm4'
run bootm4ocram
# OCRAM_S
setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000'
setenv bootm4ocrams 'run m4ocrams && run bootm4'
run bootm4ocrams
# DDR
setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000'
setenv bootm4ddr 'run m4ddr && run bootm4'
run bootm4ddr
M4<->Linux IPC using RPMSG
**************************
The IMX7D soc supports the subsys/ipc/openamp_rsc_table sample to demonstrate the
usage of rpmsg_tty as an inter processor communication.
The board configuration is provided for the colibri_imx7d board.
The boot process of the M4 core is handled solely by the Linux kernel using the RPROC
framework.
The sample was tested with Toradex's LTS BSP 6.6.0 Minimal Open Embedded image with
upstream Linux kernel 6.1.83.
Required kernel modules must be loaded for RPMSG to work:
- imx_rproc
- virtio_rpmsg_bus
- rpmsg_tty (requiring rpmsg_core)
You need to modify your Linux device tree to add the M4 definitions:
- Enable MU_A
- Reserve memory areas for the M4 so Linux won't touch them.
- Define the M4 remoteproc node for the drivers.
If you have not downloaded the BSP sources, you can modify the board's device tree
from its currently loaded dtb file.
.. code-block:: none
#Check the which fdtfile is loaded for your board in U-boot
printenv
#For a Colibri_imx7d on Viola Carrier on BSP 6.6.0
fdtfile = imx7d-colibri-emmc-eval-v3.dtb
#Copy this file to your Linux PC through SSH from /boot
#Convert the dtb into a dts
dtc -I dtb -O dts -f imx7d-colibri-emmc-eval-v3.dtb -o imx7d-colibri-emmc-eval-v3.dts
#You need to find the following phandle numbers:
# reset-controller
# mailbox@30aa0000
#Note down the phandle value (0xbd)
grep -A10 "mailbox@30aa0000 {" imx7d-colibri-emmc-eval-v3.dts
# outputs your DTS's mailbox definition
# mailbox@30aa0000 {
# compatible = "fsl,imx7s-mu\0fsl,imx6sx-mu";
# reg = <0x30aa0000 0x10000>;
# interrupts = <0x00 0x58 0x04>;
# clocks = <0x01 0x1b1>;
# #mbox-cells = <0x02>;
# status = "disabled";
# phandle = <0xbd>;
# };
#Note down the phandle value (0x32)
grep -A8 "reset-controller@30390000 {" imx7d-colibri-emmc-eval-v3.dts
# outputs your DTS's reset-controller definition
# reset-controller@30390000 {
# compatible = "fsl,imx7d-src\0syscon";
# reg = <0x30390000 0x10000>;
# interrupts = <0x00 0x59 0x04>;
# #reset-cells = <0x01>;
# phandle = <0x32>;
# };
#Node down the biggest phandle value
grep "phandle = <" imx7d-colibri-emmc-eval-v3.dts | sort -r | head -1
# outputs your DTS's largest phandle definition
# phandle = <0xca>;
#Now we can add our nodes to the .dts file:
cp imx7d-colibri-emmc-eval-v3.dts imx7d-m4.dts
nano imx7d-m4.dts
#Modify MU_A node to enable it
mailbox@30aa0000 {
compatible = "fsl,imx7s-mu\0fsl,imx6sx-mu";
reg = <0x30aa0000 0x10000>;
interrupts = <0x00 0x58 0x04>;
clocks = <0x01 0x1b1>;
#mbox-cells = <0x02>;
status = "okay";
phandle = <0xbd>;
};
#Add these definitions under / { } just before the __symbols__
#Disgard the comments with #-->
reserved-memory {
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
vdev0buffer0@90002000 {
compatible = "shared-dma-pool";
reg = <0x90002000 0x8000>;
no-map;
phandle = <0xcb>; #--> biggest phandle +1
};
vdev0vring0@90000000 {
compatible = "shared-dma-pool";
reg = <0x90000000 0x1000>;
no-map;
phandle = <0xcc>; #--> biggest phandle +2
};
vdev0vring1@90001000 {
compatible = "shared-dma-pool";
reg = <0x90001000 0x1000>;
no-map;
phandle = <0xcd>; #--> biggest phandle +3
};
cm4tcmcode@7f8000 {
compatible = "shared-dma-pool";
reg = <0x7f8000 0x8000>;
no-map;
phandle = <0xce>; #--> biggest phandle +4
};
cm4sramcode@900000 {
compatible = "shared-dma-pool";
reg = <0x900000 0x40000>;
no-map;
phandle = <0xcf>; #--> biggest phandle +5
};
cm4reserved@8ff00000 {
compatible = "shared-dma-pool";
reg = <0x8ff00000 0x100000>;
no-map;
phandle = <0xd0>; #--> biggest phandle +6
};
};
imx7d-cm4 {
compatible = "fsl,imx7d-cm4";
mbox-names = "tx\0rx\0rxdb";
mboxes = <0xbd 0x00 0x00 0xbd 0x01 0x00 0xbd 0x03 0x00>; #--> MU_A phandle (0xbd)
memory-region = <0xcb 0xcc 0xcd 0xce 0xcf 0xd0>; #--> All the previously defined phandles
syscon = <0x32>; #--> phandle for the reset-controller
clocks = <0x01 0x42>;
};
#Recompile the dts into a dtb
dtc -I dts -O dtb -f imx7d-m4.dts -o imx7d-m4.dtb
#Copy the new dtb to /boot on the Colibri IMX7 board
#Start in U-boot and update the device-tree
setenv fdtfile imx7d-m4.dtb
saveenv
boot
When the OS has finished booting with your new device tree you can enable
the drivers and start the M4 core.
.. code-block:: console
#Copy zephyr_openamp_rsc_table.elf to /lib/firmware on your board
$ modprobe imx_rproc
$ modprobe virtio_rpmsg_bus
$ modprobe rpmsg_tty
#Request RPROC to load the M4 image
$ echo stop > /sys/class/remoteproc/remoteproc0/state
$ echo zephyr_openamp_rsc_table.elf > /sys/class/remoteproc/remoteproc0/firmware
$ echo start > /sys/class/remoteproc/remoteproc0/state
#dmesg will detail the boot process:
$ dmesg
[ 497.120499] remoteproc remoteproc0: stopped remote processor imx-rproc
[ 497.138938] remoteproc remoteproc0: powering up imx-rproc
[ 497.168735] remoteproc remoteproc0: Booting fw image zephyr_openamp_rsc_table.elf, size 1267076
[ 497.184826] rproc-virtio rproc-virtio.1.auto: assigned reserved memory node vdev0buffer0@90002000
[ 497.221395] virtio_rpmsg_bus virtio0: rpmsg host is online
[ 497.233806] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty addr 0x400
[ 497.236666] rproc-virtio rproc-virtio.1.auto: registered virtio0 (type 7)
[ 497.259822] remoteproc remoteproc0: remote processor imx-rproc is now up
[ 497.293913] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x401
[ 497.308388] rpmsg_client_sample virtio0.rpmsg-client-sample.-1.1025: new channel: 0x401 -> 0x401!
[ 497.337969] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty addr 0x402
$ ls /dev | grep ttyRPMSG
ttyRPMSG0 -> used for zephyr shell interface
ttyRPMSG1 -> used for sample interface
Debugging
=========
Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_.
To run Zephyr Binary using J-Link create the following script in order to
get the Program Counter and Stack Pointer from zephyr.bin.
get-pc-sp.sh:
.. code-block:: console
#!/bin/sh
firmware=$1
pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}')
sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}')
echo pc=$pc
echo sp=$sp
Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin``
.. code-block:: console
pc=00900f01
sp=00905020
Plug in the J-Link into the board and PC and run the J-Link command line tool:
.. code-block:: console
/usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript
The following steps are necessary to run the zephyr.bin:
1. Put the M4 core in reset
2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR)
3. Set PC (Program Counter)
4. Set SP (Stack Pointer)
5. Get the M4 core out of reset
Issue the following commands inside J-Link commander:
.. code-block:: console
w4 0x3039000C 0xAC
loadfile zephyr.bin,0x00900000
w4 0x00180000 00900f01
w4 0x00180004 00905020
w4 0x3039000C 0xAA
With these mechanisms, applications for the ``colibri_imx7d/imx7d/m4`` board
configuration can be built and debugged in the usual way (see
:ref:`build_an_application` and :ref:`application_run` for more details).
References
==========
- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_
- `J-Link iMX7D Instructions`_
.. _Colibri Evaluation Board Website:
path_to_url
.. _Colibri Evaluation Board Datasheet:
path_to_url
.. _Colibri iMX7 Website:
path_to_url
.. _Colibri iMX7 User Guide:
path_to_url
.. _Colibri iMX7 Datasheet:
path_to_url
.. _i.MX 7 Series Website:
path_to_url
.. _i.MX 7 Dual Datasheet:
path_to_url
.. _i.MX 7 Dual Reference Manual:
path_to_url
.. _J-Link Tools:
path_to_url#J-LinkSoftwareAndDocumentationPack
.. _NXP iMX7D Connect CortexM4.JLinkScript:
path_to_url
.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors:
path_to_url
.. _J-Link iMX7D Instructions:
path_to_url
.. _Toradex Wiki:
path_to_url#Memory_areas
``` | /content/code_sandbox/boards/toradex/colibri_imx7d/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,317 |
```unknown
/*
*
*/
#include "waveshare_epaper_common.dtsi"
/ {
chosen {
zephyr,display = &ssd16xx_waveshare_epaper_gdeh029a1;
};
mipi_dbi_waveshare_epaper_gdeh029a1 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
#address-cells = <1>;
#size-cells = <0>;
ssd16xx_waveshare_epaper_gdeh029a1: ssd16xxfb@0 {
compatible = "gooddisplay,gdeh029a1", "solomon,ssd1608";
mipi-max-frequency = <4000000>;
reg = <0>;
width = <296>;
height = <128>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
softstart = [d7 d6 9d];
full {
vcom = <0x9a>;
border-waveform = <0x33>;
dummy-line = <0x1a>;
gate-line-width = <0x08>;
lut = [
50 AA 55 AA 11 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 FF FF 1F 00
00 00 00 00 00 00
];
};
partial {
vcom = <0xa8>;
border-waveform = <0x01>;
dummy-line = <0x1a>;
gate-line-width = <0x08>;
lut = [
10 18 18 08 18 18 08 00
00 00 00 00 00 00 00 00
00 00 00 00 13 14 44 12
00 00 00 00 00 00
];
};
};
};
};
``` | /content/code_sandbox/boards/shields/waveshare_epaper/waveshare_epaper_gdeh029a1.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 514 |
```unknown
/*
*
*/
#include "waveshare_epaper_common.dtsi"
/ {
chosen {
zephyr,display = &uc8179_waveshare_epaper_gdew075t7;
};
mipi_dbi_waveshare_epaper_gdew075t7 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
write-only;
#address-cells = <1>;
#size-cells = <0>;
uc8179_waveshare_epaper_gdew075t7: uc8179@0 {
compatible = "gooddisplay,gdew075t7", "ultrachip,uc8179";
mipi-max-frequency = <4000000>;
reg = <0>;
width = <800>;
height = <480>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
softstart = [17 17 17 17];
full {
pwr = [07 07 3f 3f];
cdi = <07>;
tcon = <0x22>;
};
};
};
};
``` | /content/code_sandbox/boards/shields/waveshare_epaper/waveshare_epaper_gdew075t7.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 307 |
```unknown
/*
*
*/
&arduino_spi {
status = "okay";
cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>, /* D10 */
<&arduino_header 12 GPIO_ACTIVE_LOW>; /* D04 */
waveshare_epaper_sdhc: sdhc@1 {
compatible = "zephyr,sdhc-spi-slot";
reg = <1>;
status = "okay";
spi-max-frequency = <24000000>;
mmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
};
``` | /content/code_sandbox/boards/shields/waveshare_epaper/dts/waveshare_epaper_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```unknown
config SHIELD_LMP90100_EVB
def_bool $(shields_list_contains,lmp90100_evb)
``` | /content/code_sandbox/boards/shields/lmp90100_evb/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
if SHIELD_LMP90100_EVB
if ADC
config ADC_LMP90XXX_GPIO
default y
config ADC_INIT_PRIORITY
default 80
endif # ADC
endif # SHIELD_LMP90100_EVB
``` | /content/code_sandbox/boards/shields/lmp90100_evb/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
&arduino_spi {
status = "okay";
lmp90100_lmp90100_evb: lmp90100@0 {
compatible = "ti,lmp90100";
reg = <0x0>;
spi-max-frequency = <1000000>;
/* Uncomment to use IRQ instead of polling: */
/* drdyb-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; */
#io-channel-cells = <1>;
lmp90100_gpio: gpio {
compatible = "ti,lmp90xxx-gpio";
gpio-controller;
/* Reduce to 6 if drdyb is used */
ngpios = <7>;
#gpio-cells = <2>;
};
};
};
&arduino_i2c {
status = "okay";
eeprom0_lmp90100_evb: eeprom@57 {
compatible = "atmel,at24c02", "atmel,at24";
reg = <0x57>;
size = <256>;
pagesize = <8>;
address-width = <8>;
timeout = <5>;
};
};
``` | /content/code_sandbox/boards/shields/lmp90100_evb/lmp90100_evb.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 280 |
```restructuredtext
.. _waveshare_epaper:
WAVESHARE e-Paper Raw Panel Shield
##################################
Overview
********
The WAVESHARE e-Paper Raw Panel Shield is a universal driver shield.
The shield can be used to drive various Electrophoretic (electronic ink)
Display (EPD) with a SPI interface.
This shield includes a 23LC1024 1Mb SPI Serial SRAM that is
not currently supported by the Zephyr RTOS.
More information about the shield can be found
at the `Universal e-Paper Raw Panel Driver Shield website`_.
Pins Assignment of the e-Paper Shield
=====================================
+-----------------------+------------+----------------------------+
| Shield Connector Pin | Function | |
+=======================+============+============================+
| D5 | RAM CSn | RAM Chip Select |
+-----------------------+------------+----------------------------+
| D6 | SD CSn | EPD SD Card Chip Select |
+-----------------------+------------+----------------------------+
| D7 | EPD BUSY | EPD Busy Output |
+-----------------------+------------+----------------------------+
| D8 | EPD RESETn | EPD Reset Input |
+-----------------------+------------+----------------------------+
| D9 | EPD DC | EPD Data/Command Input |
+-----------------------+------------+----------------------------+
| D10 | EPD CSn | EPD Chip Select Input |
+-----------------------+------------+----------------------------+
| D11 | SPI MOSI | Serial Data Input |
+-----------------------+------------+----------------------------+
| D12 | SPI MISO | Serial Data Out |
+-----------------------+------------+----------------------------+
| D13 | SPI SCK | Serial Clock Input |
+-----------------------+------------+----------------------------+
Current supported displays
==========================
+--------------+-----------------+--------------+------------------------------+
| Display | Ribbon Cable | Controller / | Shield Designation |
| | Label | Driver | |
+==============+=================+==============+==============================+
| Good Display | HINK-E0213 | SSD1673 / | waveshare_epaper_gdeh0213b1 |
| GDEH0213B1 | | ssd16xx | |
+--------------+-----------------+--------------+------------------------------+
| Good Display | HINK-E0213A22 | SSD1675A / | waveshare_epaper_gdeh0213b72 |
| GDEH0213B72 | | ssd16xx | |
+--------------+-----------------+--------------+------------------------------+
| Good Display | E029A01 | SSD1608 / | waveshare_epaper_gdeh029a1 |
| GDEH029A1 | | ssd16xx | |
+--------------+-----------------+--------------+------------------------------+
| Good Display | WFT0583CZ61 | UC8179 / | waveshare_epaper_gdew075t7 |
| GDEW075T7 | | gd7965 | |
+--------------+-----------------+--------------+------------------------------+
| Good Display | HINK-E0154A07 | SSD1681 / | waveshare_epaper_gdeh0154a07 |
| GDEH0154D67 | | ssd16xx | |
+--------------+-----------------+--------------+------------------------------+
| Good Display | WFT0420CZ15 | UC8176 / | waveshare_epaper_gdew042t2 |
| GDEW042T2 | | gd7965 | waveshare_epaper_gdew042t2-p |
+--------------+-----------------+--------------+------------------------------+
| Good Display | FPC-A002 | SSD1680 / | waveshare_epaper_gdey0213b74 |
| GDEY0213B74 | | ssd16xx | |
+--------------+-----------------+--------------+------------------------------+
Requirements
************
This shield can only be used with a board that provides a configuration
for Arduino connectors and defines node aliases for SPI and GPIO interfaces
(see :ref:`shields` for more details).
Programming
***********
Correct shield designation (see the table above) for your display must
be entered when you invoke ``west build``.
For example:
.. zephyr-app-commands::
:zephyr-app: samples/subsys/display/lvgl
:board: nrf52840dk/nrf52840
:shield: waveshare_epaper_gdeh0213b1
:goals: build
References
**********
.. target-notes::
.. _Universal e-Paper Raw Panel Driver Shield website:
path_to_url
``` | /content/code_sandbox/boards/shields/waveshare_epaper/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,041 |
```restructuredtext
.. _lmp90100_evb_shield:
LMP90100 Sensor AFE Evaluation Board
####################################
Overview
********
The Texas Instruments LMP90100 Sensor AFE Evaluation Board (EVB) is a
development kit for the TI LMP90xxx series of analog sensor frontends.
.. figure:: lmp90100eb_lmp90100eb.jpg
:align: center
:alt: LMP90100 EVB
LMP90100 EVB (Credit: Texas Instruments)
Requirements
************
This shield can only be used with a development board that provides a
configuration for Arduino connectors and defines a node alias for the
SPI interface (see :ref:`shields` for more details).
The SPIO connector pins on the LMP90100 EVB can be connected to the
Arduino headers of the development board using jumper wires.
For more information about interfacing the LMP90xxx series and the
LMP90100 EVB in particular, see these TI documents:
- `LMP90100 Sensor AFE Evaluation Board User's Guide`_
- `LMP90100 Multi-Channel, Low Power 24-Bit Sensor AFE`_
Samples
*******
Zephyr RTOS includes one sample targeting the LMP90100 EVB:
* :ref:`lmp90100_evb_rtd_sample`
Programming
***********
Set ``--shield lmp90100_evb`` when you invoke ``west build``. For example:
.. zephyr-app-commands::
:zephyr-app: samples/shields/lmp90100_evb/rtd
:board: frdm_k64f
:shield: lmp90100_evb
:goals: build
.. _LMP90100 Sensor AFE Evaluation Board User's Guide:
path_to_url
.. _LMP90100 Multi-Channel, Low Power 24-Bit Sensor AFE:
path_to_url
``` | /content/code_sandbox/boards/shields/lmp90100_evb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 408 |
```unknown
config SHIELD_X_NUCLEO_IKS02A1
def_bool $(shields_list_contains,x_nucleo_iks02a1)
``` | /content/code_sandbox/boards/shields/x_nucleo_iks02a1/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
&arduino_i2s {
status = "okay";
mp34dt05_x_nucleo_iks02a1_mic: mp34dt05@0 {
compatible = "st,mpxxdtyy";
reg = <0>;
};
};
``` | /content/code_sandbox/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1_mic.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```unknown
/*
*
*/
/*
* Mode 2: SensorHub Mode
*
* JP7 => 2-3 (I2C1 = I2Cx)
* JP8 => 2-3 (I2C1 = I2Cx)
*
* Only ISM330DHCX and IIS2DLPC sensors are accessible from the main board mcu.
* IIS2MDC is connected directly to ISM330DHCX SCx/SDX (I2Cx) pins, so it is not
* declared in DTS file.
*/
/ {
aliases {
accel0 = &iis2dlpc_19_x_nucleo_iks02a1_shub;
accel1 = &ism330dhcx_6b_x_nucleo_iks02a1_shub;
};
};
&arduino_i2c {
iis2dlpc_19_x_nucleo_iks02a1_shub: iis2dlpc@19 {
compatible = "st,iis2dlpc";
reg = <0x19>;
drdy-gpios = <&arduino_header 4 GPIO_ACTIVE_HIGH>; /* A4 - INT2 */
drdy-int = <2>;
};
ism330dhcx_6b_x_nucleo_iks02a1_shub: ism330dhcx@6b {
compatible = "st,ism330dhcx";
reg = <0x6b>;
drdy-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; /* D5 - INT2 */
int-pin = <2>;
};
};
``` | /content/code_sandbox/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1_shub.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 352 |
```unknown
/*
*
*/
&plli2s {
mul-n = <192>;
div-r = <3>;
status = "okay";
};
&dma2 {
status = "okay";
};
``` | /content/code_sandbox/boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
/*
*
*/
/*
* Mode 1: Standard Mode
*
* JP7 => 1-2, 3-4 (I2C1 = I2C2, I2Cx=GND)
* JP8 => 1-2, 3-4 (I2C1 = I2C2, I2Cx=GND)
*
* ISM330DHCX, IIS2MDC and IIS2DLPC sensors are accessible from the main board mcu.
*/
/ {
aliases {
accel0 = &iis2dlpc_19_x_nucleo_iks02a1;
accel1 = &ism330dhcx_6b_x_nucleo_iks02a1;
};
};
&arduino_i2c {
iis2dlpc_19_x_nucleo_iks02a1: iis2dlpc@19 {
compatible = "st,iis2dlpc";
reg = <0x19>;
drdy-gpios = <&arduino_header 4 GPIO_ACTIVE_HIGH>; /* A4 - INT2 */
drdy-int = <2>;
};
iis2mdc_x_nucleo_iks02a1: iis2mdc@1e {
compatible = "st,iis2mdc";
reg = <0x1e>;
drdy-gpios = <&arduino_header 2 GPIO_ACTIVE_HIGH>; /* A2 */
};
ism330dhcx_6b_x_nucleo_iks02a1: ism330dhcx@6b {
compatible = "st,ism330dhcx";
reg = <0x6b>;
drdy-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; /* D5 - INT2 */
int-pin = <2>;
};
};
``` | /content/code_sandbox/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 401 |
```unknown
config SHIELD_SEMTECH_SX1276MB1MAS
def_bool $(shields_list_contains,semtech_sx1276mb1mas)
``` | /content/code_sandbox/boards/shields/semtech_sx1276mb1mas/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
/*
*
*/
/ {
aliases {
lora0 = &lora_semtech_sx1276mb1mas;
};
};
&arduino_spi {
status = "okay";
cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
lora_semtech_sx1276mb1mas: lora@0 {
compatible = "semtech,sx1276";
reg = <0x0>;
spi-max-frequency = <DT_FREQ_M(1)>;
reset-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>; /* A0 */
dio-gpios = <&arduino_header 8 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO0 is D2 */
<&arduino_header 9 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO1 is D3 */
<&arduino_header 10 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO2 is D4 */
<&arduino_header 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO3 is D5 */
<&arduino_header 14 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO4 is D8 */
<&arduino_header 15 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* DIO5 is D9 */
rfo-enable-gpios = <&arduino_header 4 GPIO_ACTIVE_HIGH>; /* RXTX_EXT is A4 */
};
};
``` | /content/code_sandbox/boards/shields/semtech_sx1276mb1mas/semtech_sx1276mb1mas.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 319 |
```restructuredtext
.. _x-nucleo-iks02a1:
X-NUCLEO-IKS02A1: MEMS Inertial and Environmental Multi sensor shield
#####################################################################
Overview
********
The X-NUCLEO-IKS02A1 is a motion MEMS expansion board for the STM32 Nucleo,
fitting the requirements of industrial applications.
It is equipped with Arduino UNO R3 connector layout, and
is designed around the ISM330DHCX 3-axis accelerometer and 3-axis gyroscope,
the IIS2MDC 3-axis magnetometer, the IIS2DLPC 3-axis accelerometer and
the IMP34DT05 digital microphone.
The X-NUCLEO-IKS02A1 interfaces with the STM32 microcontroller via the I2C pin,
and it is possible to change the default I2C port.
.. image:: img/x-nucleo-iks02a1.jpg
:align: center
:alt: X-NUCLEO-IKS02A1
More information about the board can be found at the
`X-NUCLEO-IKS02A1 website`_.
Hardware Description
********************
X-NUCLEO-IKS02A1 provides the following key features:
- ISM330DHCX MEMS 3D accelerometer (2/4/8/16 g) and
3D gyroscope (125/250/500/1000/2000 dps)
- IIS2MDC MEMS 3D magnetometer (50 gauss)
- IIS2DLPC MEMS 3D accelerometer low power (2/4/8/16 g)
- IMP34DT05 MEMS digital omnidirectional microphone (-26 dBFS, 3 dB sensitivity)
- DIL24 socket for additional MEMS adapters and other sensors (configurable in I2C or SPI)
- I2C sensor hub features on ISM330DHCX available
- Compatible with STM32 Nucleo boards
- Equipped with Arduino UNO R3 connector
- RoHS compliant
- WEEE compliant
Hardware Configuration
**********************
X-NUCLEO-IKS02A1 board connects the various devices on two separate I2C bus:
- IIS2DLPC and ISM330DHCX are on I2C2
- IIS2MDC is on I2C1
X-NUCLEO-IKS02A1 board can be configured in two different hardware modes, Mode 1 and Mode 2,
using the JP7/JP8 jumpers to modify to what the I2C1 bus connects to.
Mode 1: Standard Mode
=====================
In standard I2C mode the two buses are connected together. As a consequence, all devices on the shield
reside on the same I2C bus and are accessible from the main board mcu.
The jumper configuration to activate this mode is:
- JP7 => 1-2, 3-4 (I2C1 = I2C2, I2Cx=GND)
- JP8 => 1-2, 3-4 (I2C1 = I2C2, I2Cx=GND)
Mode 2: SensorHub Mode
======================
In SensorHub mode ISM330DHCX and IIS2DLPC are connected to I2C2 and are accessible from the main board mcu.
Instead, the IIS2MDC device is connected only to ISM330DHCX sensor through its SCx/SDX (I2Cx) pins.
The jumper configuration to activate this mode is:
- JP7 => 2-3 (I2C1 = I2Cx)
- JP8 => 2-3 (I2C1 = I2Cx)
More information about X-NUCLEO-IKS02A1 configuration modes can be found in the
`X-NUCLEO-IKS02A1 user manual`_
Programming
***********
Three samples are provided as examples for ``x-nucleo-iks02a1`` shield:
- :zephyr:code-sample:`x-nucleo-iks02a1-std` application, to be used when the shield is configured
in Standard Mode
- :zephyr:code-sample:`x-nucleo-iks02a1-shub` application, to be used when the shield is configured
in SensorHub Mode
- :zephyr:code-sample:`x-nucleo-iks02a1-mic` application, to be used to acquire data through the
on-board PDM microphone
See also :ref:`shields` for more details.
References
**********
.. target-notes::
.. _X-NUCLEO-IKS02A1 website:
path_to_url
.. _X-NUCLEO-IKS02A1 user manual:
path_to_url
``` | /content/code_sandbox/boards/shields/x_nucleo_iks02a1/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,030 |
```unknown
/*
*
*/
/{
chosen {
zephyr,camera = &dvp_fpc24_interface;
};
};
&dvp_fpc24_i2c {
mt9m114: mt9m114@48 {
compatible = "aptina,mt9m114";
reg = <0x48>;
port {
mt9m114_ep_out: endpoint {
remote-endpoint = <&dfi_ep_in>;
};
};
};
};
&dvp_fpc24_interface {
status = "okay";
port {
dfi_ep_in: endpoint {
remote-endpoint = <&mt9m114_ep_out>;
};
};
};
``` | /content/code_sandbox/boards/shields/dvp_fpc24_mt9m114/dvp_fpc24_mt9m114.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 151 |
```restructuredtext
.. _semtech_sx1276mb1mas:
Semtech SX1276MB1MAS LoRa Shield
################################
Overview
********
The Semtech SX1276MB1MAS LoRa shield is an Arduino compatible shield based on
the SX1276 LoRa transceiver from Semtech.
More information about the shield can be found at the `mbed SX1276MB1xAS
website`_.
Pins Assignment of the Semtech SX1276MB1MAS LoRa Shield
=======================================================
+-----------------------+-----------------+
| Shield Connector Pin | Function |
+=======================+=================+
| A0 | SX1276 RESET |
+-----------------------+-----------------+
| A3 | SX1276 DIO4 (1) |
+-----------------------+-----------------+
| A4 | Antenna RX/TX |
+-----------------------+-----------------+
| D2 | SX1276 DIO0 |
+-----------------------+-----------------+
| D3 | SX1276 DIO1 |
+-----------------------+-----------------+
| D4 | SX1276 DIO2 |
+-----------------------+-----------------+
| D5 | SX1276 DIO3 |
+-----------------------+-----------------+
| D8 | SX1276 DIO4 (1) |
+-----------------------+-----------------+
| D9 | SX1276 DIO5 |
+-----------------------+-----------------+
| D10 | SX1276 SPI NSS |
+-----------------------+-----------------+
| D11 | SX1276 SPI MOSI |
+-----------------------+-----------------+
| D12 | SX1276 SPI MISO |
+-----------------------+-----------------+
| D13 | SX1276 SPI SCK |
+-----------------------+-----------------+
(1) SX1276 DIO4 is configured on D8 by default. It is possible to reconfigure it
in devicetree to A3 if needed.
Requirements
************
This shield can only be used with a board which provides a configuration for
Arduino connectors and defines node aliases for SPI and GPIO interfaces (see
:ref:`shields` for more details).
Programming
***********
Set ``--shield semtech_sx1271mb1mas`` when you invoke ``west build``. For
example:
.. zephyr-app-commands::
:zephyr-app: samples/subsys/lorawan/class_a
:board: nucleo_l073rz
:shield: semtech_sx1276mb1mas
:goals: build
References
**********
.. target-notes::
.. _mbed SX1276MB1xAS website:
path_to_url
``` | /content/code_sandbox/boards/shields/semtech_sx1276mb1mas/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 579 |
```unknown
config SHIELD_DVP_FPC24_MT9M114
def_bool $(shields_list_contains,DVP_FPC24_MT9M114)
``` | /content/code_sandbox/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*
*/
&dvp_fpc24_interface {
source = <&mt9m114>;
};
``` | /content/code_sandbox/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1060_evkb.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
/*
*
*/
&dvp_fpc24_interface {
source = <&mt9m114>;
};
``` | /content/code_sandbox/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1064_evk.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
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