text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```cmake
board_runner_args(linkserver "--device=MKE17Z256xxx7:FRDM-KE17Z")
board_runner_args(jlink "--device=MKE17Z256xxx7" "--reset-after-load")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/nxp/frdm_ke17z/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_ke17z.dtsi>
#include "frdm_ke17z-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
/ {
model = "NXP Freedom KE17Z board";
compatible = "nxp,frdm-ke17z", "nxp,ke17z", "nxp,mke17z7";
aliases {
watchdog0 = &wdog;
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
sw0 = &user_button_0;
sw1 = &user_button_1;
pwm-led0 = &red_pwm_led;
pwm-led1 = &green_pwm_led;
pwm-led2 = &blue_pwm_led;
};
chosen {
zephyr,sram = &sram_u;
zephyr,flash = &flash0;
zephyr,console = &lpuart0;
zephyr,shell-uart = &lpuart0;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpiod 10 GPIO_ACTIVE_LOW>;
label = "RGB RED";
};
green_led: led_1 {
gpios = <&gpiod 11 GPIO_ACTIVE_LOW>;
label = "RGB GREEN";
};
blue_led: led_2 {
gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
label = "RGB BLUE";
};
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: led_pwm_0 {
pwms = <&ftm2 0 PWM_HZ(20) PWM_POLARITY_INVERTED>;
label = "RED RGB PWM LED";
};
green_pwm_led: led_pwm_1 {
pwms = <&ftm2 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "GREEN RGB PWM LED";
};
blue_pwm_led: led_pwm_2 {
pwms = <&ftm2 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "BLUE RGB PWM LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_0: button_0 {
label = "User SW2";
gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_1: button_1 {
label = "User SW3";
gpios = <&gpioe 14 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
};
&idle {
min-residency-us = <1>;
};
&stop {
min-residency-us = <20000>;
exit-latency-us = <13>;
};
&lpuart0 {
dmas = <&edma 1 2>, <&edma 2 3>;
dma-names = "rx", "tx";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&lpuart0_default>;
pinctrl-names = "default";
};
&adc0 {
status = "okay";
sample-time = <12>;
pinctrl-0 = <&adc0_default>;
pinctrl-names = "default";
};
&lpi2c0 {
status = "okay";
pinctrl-0 = <&lpi2c0_default>;
pinctrl-names = "default";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&ftm2 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
clocks = <&scg KINETIS_SCG_SIRC_CLK>;
prescaler = <128>;
pinctrl-0 = <&ftm2_default>;
pinctrl-names = "default";
clock-source = "system";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 DT_SIZE_K(44)>;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@b000 {
label = "image-0";
reg = <0xb000 (DT_SIZE_K(98) + DT_SIZE_K(4))>;
};
slot1_partition: partition@24800 {
label = "image-1";
reg = <0x24800 DT_SIZE_K(98)>;
};
storage_partition: partition@3d000 {
label = "storage";
reg = <0x3d000 DT_SIZE_K(12)>;
};
};
};
&lpspi0 {
dmas = <&edma 0 14>, <&edma 1 15>;
dma-names = "rx", "tx";
status = "okay";
pinctrl-0 = <&lpspi0_default>;
pinctrl-names = "default";
};
&edma {
status = "okay";
};
&wdog {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/frdm_ke17z/frdm_ke17z.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,241 |
```restructuredtext
.. _lpcxpresso11u68:
NXP LPCXpresso11U68
###################
Overview
********
The LPCXpresso11u68 development board uses an NXP LPC11U68 MCU based
on an ARM Cortex-M0+ core.
.. figure:: lpcxpresso11u68.jpg
:align: center
:alt: LPCXpresso11U68
Hardware
********
The LPCxpresso 11U68 board provides the following hardware components:
- LPC11U68 microcontroller in LQFP100 package
- ARM Cortex-M0+
- Memory:
- 256KB of flash memory
- 32KB of SRAM
- 2x2KB of additional SRAM
- 4 KB EEPROM
- USB:
- USB 2.0 Full-Speed device controller
- DMA controller
- 5x USART
- 2x I2C
- 2x SSP with DMA support
- Board power supply: through USB bus or external power supply (3V and 5V)
- Arduino connectors compatible with the 'Arduino UNO' platform
- Tri-color user LED, Power On Led, Reset LED
- Three push buttons: target reset, ISP and user
More information can be found here:
- `LPC11UXX SoC Website`_
- `LPC11U6X Datasheet`_
- `LPC11U6X Reference Manual`_
- `LPCXPRESSO11U68 Website`_
- `LPCXPRESSO11U68 Schematics`_
Supported Features
==================
The lpcxpresso11U68 supports the following features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| IOCON | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock and reset control |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c master/slave controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port interrupt |
+-----------+------------+-------------------------------------+
| EEPROM | on-chip | eeprom |
+-----------+------------+-------------------------------------+
Other hardware is not yet supported on Zephyr.
Connections and IOs
===================
The IOCON controller can be used to configure the LPC11U68 pins.
+---------+-----------------+----------------------------+
| Name | Function | Usage |
+=========+=================+============================+
| PIO2_11 | UART | USART RX |
+---------+-----------------+----------------------------+
| PIO2_12 | UART | USART TX |
+---------+-----------------+----------------------------+
| PIO2_16 | GPIO | GREEN LED |
+---------+-----------------+----------------------------+
| PIO2_17 | GPIO | RED LED |
+---------+-----------------+----------------------------+
| PIO2_18 | GPIO | BLUE_LED |
+---------+-----------------+----------------------------+
| PIO0_4 | I2C | I2C SCL |
+---------+-----------------+----------------------------+
| PIO0_5 | I2C | I2C SDA |
+---------+-----------------+----------------------------+
Programming and Debugging
*************************
Flashing
========
The LPCXpresso11U68 board can be flashed by using the on-board LPC-Link2 debug
probe (based on a NXP LPC43xx MCU). This MCU provides either a CMSIS-DAP or
a J-Link interface. It depends on the embedded firmware image. The default
OpenOCD configuration supports the CMSIS-DAP interface. If you want to
switch to J-Link, then you need to edit the
:zephyr_file:`boards/nxp/lpcxpresso11u68/support/openocd.cfg` file and to replace::
source [find interface/cmsis-dap.cfg]
with::
source [find interface/jlink.cfg]
.. note::
The firmware image of the LPC-Link2 can be updated using the
`LPCScrypt tool <path_to_url`_.
.. note::
The `Mbed project <path_to_url`_ also provides some firmware images
`here <path_to_url`_.
In addition to a CMSIS-DAP interface, they also provide a convenient update
mechanism through a pseudo USB disk.
Here are the steps to flash a firmware you built into a LPCXpresso11U68 board:
#. Connect the "Link" micro-B USB port to your host computer.
#. Next, simply run the ``west flash`` command
Debugging
=========
Please refer to the `Flashing`_ section and run the ``west debug`` command
instead of ``west flash``.
References
**********
- `LPC11UXX SoC Website`_
- `LPC11U6X Datasheet`_
- `LPC11U6X Reference Manual`_
- `LPCXPRESSO11U68 Website`_
- `LPCXPRESSO11U68 Schematics`_
.. _LPC11UXX SoC Website:
path_to_url
.. _LPC11U6X Datasheet:
path_to_url
.. _LPC11U6x Reference Manual:
path_to_url
.. _LPCXPRESSO11U68 Website:
path_to_url
.. _LPCXPRESSO11U68 Schematics:
path_to_url
``` | /content/code_sandbox/boards/nxp/lpcxpresso11u68/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,272 |
```unknown
# FRDM-KE17Z board configuration
config BOARD_FRDM_KE17Z
select SOC_MKE17Z7
select SOC_PART_NUMBER_MKE17Z256VLL7
``` | /content/code_sandbox/boards/nxp/frdm_ke17z/Kconfig.frdm_ke17z | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```unknown
#
#
#
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
# GPIO Controller
CONFIG_GPIO=y
# Clock Control
CONFIG_CLOCK_CONTROL=y
# Enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
/*
*
*/
#include <nxp/kinetis/MKE17Z256VLL7-pinctrl.h>
&pinctrl {
adc0_default: adc0_default {
group0 {
pinmux = <ADC0_SE0_PTE9>;
drive-strength = "low";
slew-rate = "slow";
};
};
lpuart0_default: lpuart0_default {
group0 {
pinmux = <LPUART0_TX_PTB1>,
<LPUART0_RX_PTB0>;
drive-strength = "low";
slew-rate = "slow";
};
};
ftm2_default: ftm2_default {
group0 {
pinmux = <FTM2_CH0_PTD10>,
<FTM2_CH1_PTD11>,
<FTM2_CH2_PTD12>;
drive-strength = "low";
slew-rate = "slow";
};
};
lpi2c0_default: lpi2c0_default {
group0 {
pinmux = <LPI2C0_SDA_PTA16>,
<LPI2C0_SCL_PTB8>;
bias-pull-up;
drive-strength = "low";
slew-rate = "slow";
};
};
lpspi0_default: lpspi0_default {
group0 {
pinmux = <LPSPI0_SCK_PTB2>,
<LPSPI0_SIN_PTB3>,
<LPSPI0_SOUT_PTB4>,
<LPSPI0_PCS1_PTB5>;
bias-pull-up;
drive-strength = "low";
slew-rate = "slow";
};
};
};
``` | /content/code_sandbox/boards/nxp/frdm_ke17z/frdm_ke17z-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 392 |
```yaml
identifier: frdm_ke17z
name: NXP FRDM-KE17Z
type: mcu
arch: arm
ram: 32
flash: 256
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- counter
- gpio
- adc
- uart
- pwm
- i2c
- spi
- dma
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/frdm_ke17z/frdm_ke17z.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```yaml
board:
name: frdm_ke17z
vendor: nxp
socs:
- name: mke17z7
``` | /content/code_sandbox/boards/nxp/frdm_ke17z/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
#
#
#
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_RUNTIME_NMI=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_TRUSTED_EXECUTION_SECURE=y
CONFIG_ARM_TRUSTZONE_M=y
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```cmake
#
#
#
## DAP Link implementation in pyocd is underway,
## until then jlink can be used or copy image to storage
if(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR
CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS OR
CONFIG_SECOND_CORE_MCUX)
board_runner_args(jlink "--device=LPC55S69_M33_0")
board_runner_args(linkserver "--device=LPC55S69:LPCXpresso55S69")
board_runner_args(linkserver "--override=/device/memory/0/flash-driver=LPC55xx_S.cfx")
board_runner_args(linkserver "--override=/device/memory/0/location=0x10000000")
elseif(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1)
board_runner_args(jlink "--device=LPC55S69_M33_1")
endif()
board_runner_args(pyocd "--target=lpc55s69")
if(CONFIG_BUILD_WITH_TFM)
set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
endif()
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 294 |
```yaml
#
#
#
identifier: lpcxpresso55s69/lpc55s69/cpu0
name: NXP LPCXpresso55S69 (CPU0)
type: mcu
arch: arm
ram: 64
flash: 256
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- arduino_i2c
- arduino_serial
- arduino_spi
- counter
- gpio
- i2c
- i2s
- spi
- sdhc
- usb_device
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```yaml
#
#
#
identifier: lpcxpresso55s69/lpc55s69/cpu0/ns
name: NXP LPCXpresso55S69 (Non-Secure)
type: mcu
arch: arm
ram: 136
flash: 96
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- arduino_spi
- counter
- dma
- gpio
- spi
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```restructuredtext
.. _frdm_ke17z:
NXP FRDM-KE17Z
##############
Overview
********
The FRDM-KE17Z is a development board for NXP Kinetis KE1xZ 32-bit
MCU-based platforms. The FRDM-KE17Z contains a robust TSI module
with up to 50 channels which makes this board highly flexible
for touch keys. Offers options for serial
communication, flash programming, and run-control debugging.
.. figure:: frdmke17z.webp
:align: center
:alt: FRDM-KE17Z
FRDM-KE17Z (Credit: NXP)
Hardware
********
- MKE17Z256VLL7 MCU (up to 72 MHz, 256 KB flash memory, 48 KB SRAM,
and 100 Low profile Quad Flat Package (LQFP))
- 3.3 V or 5 V MCU operation
- 6-axis FXOS8700CQ digital accelerometer
- 3-axis digital angular rate gyroscope
- One RGB LED
- Two user push-buttons
- Thermistor
- Two capacitive touchpads
- Flex I/O pin header
For more information about the KE1xZ SoC and the FRDM-KE17Z board, see
these NXP reference documents:
- `FRDM-KE17Z Website`_
- `FRDM-KE17Z User Guide`_
- `FRDM-KE17Z Reference Manual`_
- `FRDM-KE17Z Datasheet`_
Supported Features
==================
The frdm_ke17z board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINCTRL | on-chip | pinctrl |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| LPTMR | on-chip | counter |
+-----------+------------+-------------------------------------+
| UART | on-chip | uart |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| FTM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| ACMP | on-chip | sensor |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/frdm_ke17z/frdm_ke17z_defconfig`.
Other hardware features are not currently supported by the port.
System Clock
============
The KE17Z SoC is configured to run at 48 MHz using the FIRC.
Serial Port
===========
The KE17Z SoC has three UARTs. UART0 is configured for the console.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use Linkserver.
Early versions of this board have an outdated version of the OpenSDA bootloader
and require an update. Please see the `DAPLink Bootloader Update`_ page for
instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader.
Option 1: Linkserver
--------------------
Install the :ref:`linkserver-debug-host-tools` and make sure they are in your
search path. LinkServer works with the default CMSIS-DAP firmware included in
the on-board debugger.
Linkserver is the default for this board, ``west flash`` and ``west debug`` will
call the linkserver runner.
.. code-block:: console
west flash
External JLink: :ref:`jlink-external-debug-probe`
-------------------------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Attach a J-Link 10-pin connector to J14. Check that jumpers J8 and J9 are
**off** (they are on by default when boards ship from the factory) to ensure
SWD signals are disconnected from the OpenSDA microcontroller.
Use the ``-r jlink`` option with west to use the jlink runner.
.. code-block:: console
west flash -r jlink
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console.
Connect a USB cable from your PC to J6.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_ke17z
:goals: flash
Open a serial terminal, reset the board (press the SW1 button), and you should
see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build xxxxxxxxxxxx ***
Hello World! frdm_ke17z/mke17z7
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_ke17z
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build xxxxxxxxxxxx ***
Hello World! frdm_ke17z/mke17z7
.. _FRDM-KE17Z Website:
path_to_url
.. _FRDM-KE17Z User Guide:
path_to_url
.. _FRDM-KE17Z Reference Manual:
path_to_url
.. _FRDM-KE17Z Datasheet:
path_to_url
.. _DAPLink Bootloader Update:
path_to_url
.. _OpenSDA DAPLink FRDM-KE17Z Firmware:
path_to_url
.. _linkserver-debug-host-tools:
path_to_url
.. _OpenSDA J-Link Firmware for FRDM-KE17Z:
path_to_url
``` | /content/code_sandbox/boards/nxp/frdm_ke17z/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,546 |
```unknown
choice MCUBOOT_MODE
default MCUBOOT_MODE_OVERWRITE_ONLY
endchoice
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
config BOARD_LPCXPRESSO55S69
select SOC_LPC55S69_CPU0 if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 || \
BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS
select SOC_LPC55S69_CPU1 if BOARD_LPCXPRESSO55S69_LPC55S69_CPU1
select SOC_PART_NUMBER_LPC55S69JBD100
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/Kconfig.lpcxpresso55s69 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
/*
* NOTE: File generated by gen_board_pinctrl.py
* from LPCXpresso55S69.mex
*
*/
#include <nxp/lpc/LPC55S69JBD100-pinctrl.h>
&pinctrl {
pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
group0 {
pinmux = <FC0_TXD_SCL_MISO_WS_PIO0_30>,
<FC0_RXD_SDA_MOSI_DATA_PIO0_29>;
slew-rate = "standard";
};
};
/* conflicts with hs_lspi pins */
pinmux_flexcomm2_usart: pinmux_flexcomm2_usart {
group0 {
pinmux = <FC2_RXD_SDA_MOSI_DATA_PIO1_24>,
<FC2_TXD_SCL_MISO_WS_PIO0_27>;
slew-rate = "standard";
};
};
pinmux_flexcomm4_i2c: pinmux_flexcomm4_i2c {
group0 {
pinmux = <FC4_TXD_SCL_MISO_WS_PIO1_20>,
<FC4_RXD_SDA_MOSI_DATA_PIO1_21>;
slew-rate = "standard";
};
};
pinmux_flexcomm6_i2s: pinmux_flexcomm6_i2s {
group0 {
pinmux = <FC6_RXD_SDA_MOSI_DATA_PIO1_13>;
bias-pull-up;
slew-rate = "standard";
};
};
pinmux_flexcomm7_i2s: pinmux_flexcomm7_i2s {
group0 {
pinmux = <FC7_TXD_SCL_MISO_WS_PIO0_19>,
<FC7_RXD_SDA_MOSI_DATA_PIO0_20>,
<FC7_SCK_PIO0_21>;
bias-pull-up;
slew-rate = "standard";
};
};
pinmux_hs_lspi_default: pinmux_hs_lspi_default {
group0 {
pinmux = <HS_SPI_SSEL1_PIO1_1>,
<HS_SPI_SCK_PIO1_2>,
<HS_SPI_MISO_PIO1_3>,
<HS_SPI_MOSI_PIO0_26>;
bias-pull-up;
slew-rate = "standard";
};
};
pinmux_lpadc0: pinmux_lpadc0 {
group0 {
pinmux = <ADC0_CH0_PIO0_23>,
<ADC0_CH8_PIO0_16>,
<ADC0_CH4_PIO1_8>,
<ADC0_CH12_PIO1_9>;
slew-rate = "standard";
nxp,analog-mode;
};
};
pinmux_sctimer_default: pinmux_sctimer_default {
group0 {
pinmux = <SCT0_OUT2_PIO0_15>,
<SCT0_OUT0_PIO1_4>;
slew-rate = "standard";
};
};
/* conflicts with sctimer pins */
pinmux_sdif_default: pinmux_sdif_default {
group0 {
pinmux = <SDIF_SD0_D0_PIO0_24>,
<SDIF_SD0_D1_PIO0_25>,
<SDIF_SD0_D2_PIO0_31>,
<SD0_CLK_PIO0_7>,
<SD0_CMD_PIO0_8>,
<SD0_POW_EN_PIO0_9>,
<SDIF_SD0_D3_PIO1_0>;
slew-rate = "fast";
};
group1 {
pinmux = <SD0_WR_PRT_PIO0_15>,
<SD0_CARD_DET_N_PIO0_17>;
slew-rate = "standard";
};
};
pinmux_usbfs: pinmux_usbfs {
group0 {
pinmux = <USB0_VBUS_PIO0_22>;
slew-rate = "standard";
};
};
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 935 |
```c
/*
*/
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <fsl_common.h>
#include <soc.h>
static int lpcxpresso_55s69_board_init(void)
{
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2s, okay)) && \
(DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_i2s, okay)) && \
CONFIG_I2S
/*
* Flexcomm 6 and 7 are connected to codec on board, and shared signal
* sets are used to enable one I2S device to handle RX and one to handle
* TX
*/
CLOCK_EnableClock(kCLOCK_Sysctl);
/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm 7 */
SYSCTL->SHAREDCTRLSET[0] = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(7) |
SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(7);
#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
/* Select Data in from Transmit I2S - Flexcomm 7 */
SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(7);
/* Enable Transmit I2S - Flexcomm 7 for Shared Data Out */
SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(1);
#endif
/* Set Receive I2S - Flexcomm 6 SCK, WS from shared signal set 0 */
SYSCTL->FCCTRLSEL[6] = SYSCTL_FCCTRLSEL_SCKINSEL(1) |
SYSCTL_FCCTRLSEL_WSINSEL(1);
/* Set Transmit I2S - Flexcomm 7 SCK, WS from shared signal set 0 */
SYSCTL->FCCTRLSEL[7] = SYSCTL_FCCTRLSEL_SCKINSEL(1) |
SYSCTL_FCCTRLSEL_WSINSEL(1);
#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
/* Select Receive I2S - Flexcomm 6 Data in from shared signal set 0 */
SYSCTL->FCCTRLSEL[6] |= SYSCTL_FCCTRLSEL_DATAINSEL(1);
/* Select Transmit I2S - Flexcomm 7 Data out to shared signal set 0 */
SYSCTL->FCCTRLSEL[7] |= SYSCTL_FCCTRLSEL_DATAOUTSEL(1);
#endif
#endif
return 0;
}
SYS_INIT(lpcxpresso_55s69_board_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/board.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 577 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_lpc55S6x_ns.dtsi>
#include "lpcxpresso55s69.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP LPCXpresso55S69 board";
compatible = "nxp,lpc55xxx", "nxp,lpc";
cpus {
/delete-node/ cpu@1;
};
aliases {
sw0 = &user_button_1;
sw1 = &user_button_2;
sw2 = &user_button_3;
watchdog0 = &wwdt0;
accel0 = &mma8652fc;
};
chosen {
zephyr,sram = &non_secure_ram;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_ns_partition;
zephyr,console = &flexcomm0;
zephyr,shell-uart = &flexcomm0;
zephyr,entropy = &rng;
};
gpio_keys {
compatible = "gpio-keys";
user_button_1: button_0 {
label = "User SW1";
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_2: button_1 {
label = "User SW2";
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
user_button_3: button_2 {
label = "User SW3";
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_2>;
};
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&green_led {
status = "okay";
};
&red_led {
status = "okay";
};
&blue_led {
status = "okay";
};
&flexcomm0 {
status = "okay";
};
&flexcomm4 {
status = "okay";
};
&hs_lspi {
status = "okay";
};
&wwdt0 {
status = "okay";
};
&adc0 {
status = "okay";
pinctrl-0 = <&pinmux_lpadc0>;
pinctrl-names = "default";
};
&dma0 {
/*
* The total number of dma channels available is defined by
* FSL_FEATURE_DMA_NUMBER_OF_CHANNELS in the SoC features file.
* Since memory from the heap pool is allocated based on the number
* of DMA channels, set this property to as many channels is needed
* for the platform. Adjust HEAP_MEM_POOL_SIZE in case you need more
* memory.
*/
dma-channels = <20>;
status = "okay";
};
zephyr_udc0: &usbhs {
status = "okay";
};
&ctimer0 {
status = "okay";
};
&ctimer1 {
status = "okay";
};
&ctimer2 {
status = "okay";
};
&ctimer3 {
status = "okay";
};
&ctimer4 {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 698 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_lpc55S6x_ns.dtsi>
#include "lpcxpresso55s69.dtsi"
/ {
model = "NXP LPCXpresso55S69 board";
compatible = "nxp,lpc55xxx", "nxp,lpc";
cpus {
/delete-node/ cpu@0;
};
chosen {
zephyr,sram = &sram3;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_ns_partition;
zephyr,entropy = &rng;
};
};
/*
* Default for this board is to allocate SRAM3-4 to cpu1 but the
* application can have an application specific device tree to
* allocate the SRAM0-4 differently.
*
* For example, SRAM0-3 could be allocated to cpu0 with only SRAM4
* for cpu1. This would require the zephyr,sram chosen value for cpu1
* to be changed to sram4 and the value of sram0 to have a DT_SIZE_K
* of 256.
*
*/
&sram3 {
compatible = "mmio-sram";
reg = <0x20030000 DT_SIZE_K(80)>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&blue_led {
status = "okay";
};
&mailbox0 {
status = "okay";
};
&mma8652fc {
status = "disabled";
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 333 |
```yaml
board:
name: lpcxpresso55s69
vendor: nxp
socs:
- name: lpc55s69
variants:
- name: "ns"
cpucluster: 'cpu0'
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
#
#
#
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_RUNTIME_NMI=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_ARM_MPU=n
# Enable TrustZone-M
CONFIG_TRUSTED_EXECUTION_SECURE=n
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
CONFIG_ARM_TRUSTZONE_M=y
CONFIG_BUILD_WITH_TFM=y
CONFIG_BUILD_OUTPUT_HEX=y
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
if BOARD_LPCXPRESSO55S69
if FXOS8700
choice FXOS8700_MODE
default FXOS8700_MODE_ACCEL
endchoice
config FXOS8700_DRDY_INT1
default y
depends on FXOS8700_TRIGGER
endif # FXOS8700
# For the secure version of the board the firmware is linked at the beginning
# of the flash, or into the code-partition defined in DT if it is intended to
# be loaded by MCUboot. If the secure firmware is to be combined with a non-
# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always
# be restricted to the size of its code partition.
# For the non-secure version of the board, the firmware
# must be linked into the code-partition (non-secure) defined in DT, regardless.
# Apply this configuration below by setting the Kconfig symbols used by
# the linker according to the information extracted from DT partitions.
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
config FLASH_LOAD_SIZE
default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
depends on BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 && TRUSTED_EXECUTION_SECURE
if TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_LPC55S69_CPU1
config FLASH_LOAD_OFFSET
default 0x50000 if (!TFM_BL2 && BUILD_WITH_TFM)
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
config FLASH_LOAD_SIZE
default 0x40000 if (!TFM_BL2 && BUILD_WITH_TFM)
default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
config PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY
default y if MBEDTLS_PSA_CRYPTO_CLIENT && MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
endif # TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_LPC55S69_CPU1
choice TFM_PROFILE_TYPE
depends on BUILD_WITH_TFM
default TFM_PROFILE_TYPE_MEDIUM
endchoice
if BOOTLOADER_MCUBOOT
choice MCUBOOT_BOOTLOADER_MODE
# Board only supports MCUBoot via "upgrade only" method:
default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY
endchoice
endif #BOOTLOADER_MCUBOOT
endif # BOARD_LPCXPRESSO55S69
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 546 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_lpc55S6x.dtsi>
#include "lpcxpresso55s69.dtsi"
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP LPCXpresso55S69 board";
compatible = "nxp,lpc55xxx", "nxp,lpc";
cpus {
/delete-node/ cpu@1;
};
aliases{
sw0 = &user_button_1;
sw1 = &user_button_2;
sw2 = &user_button_3;
watchdog0 = &wwdt0;
/* For pwm test suites */
pwm-0 = &sc_timer;
pwm-led0 = &red_pwm_led;
red-pwm-led = &red_pwm_led;
sdhc0 = &sdhc0;
accel0 = &mma8652fc;
sdhc0 = &sdif;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,code-cpu1-partition = &slot0_ns_partition;
zephyr,sram-cpu1-partition = &sram3;
zephyr,console = &flexcomm0;
zephyr,shell-uart = &flexcomm0;
zephyr,entropy = &rng;
};
gpio_keys {
compatible = "gpio-keys";
user_button_1: button_0 {
label = "User SW1";
gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_2: button_1 {
label = "User SW2";
gpios = <&gpio1 18 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_1>;
};
user_button_3: button_2 {
label = "User SW3";
gpios = <&gpio1 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_2>;
};
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: red_pwm_led {
pwms = <&sc_timer 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "Red PWM LED";
status = "okay";
};
};
};
/*
* Default for this board is to allocate SRAM0-2 to cpu0 but the
* application can have an application specific device tree to
* allocate the SRAM0-4 differently.
*
* For example, SRAM0-3 could be allocated to cpu0 with only SRAM4
* for cpu1. This would require the zephyr,sram chosen value for cpu1
* to be changed to sram4 and the value of sram0 to have a DT_SIZE_K
* of 256.
*
*/
&sram0 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(192)>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&green_led {
status = "okay";
};
&red_led {
status = "okay";
};
&flexcomm0 {
status = "okay";
};
&flexcomm4 {
status = "okay";
};
&sdif {
status = "okay";
pinctrl-0 = <&pinmux_sdif_default>;
pinctrl-names = "default";
mmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
&hs_lspi {
status = "okay";
cs-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
&wwdt0 {
status = "okay";
};
&adc0 {
status = "okay";
pinctrl-0 = <&pinmux_lpadc0>;
pinctrl-names = "default";
};
&mailbox0 {
status = "okay";
};
&usbfs {
pinctrl-0 = <&pinmux_usbfs>;
pinctrl-names = "default";
};
zephyr_udc0: &usbhs {
status = "okay";
phy_handle = <&usbphy1>;
};
&usbphy1 {
status = "okay";
tx-d-cal = <5>;
tx-cal-45-dp-ohms = <10>;
tx-cal-45-dm-ohms = <10>;
};
&ctimer0 {
status = "okay";
};
&ctimer1 {
status = "okay";
};
&ctimer2 {
status = "okay";
};
&ctimer3 {
status = "okay";
};
&ctimer4 {
status = "okay";
};
/* I2S receive channel */
i2s0: &flexcomm6 {
status = "okay";
compatible = "nxp,lpc-i2s";
#address-cells = <1>;
#size-cells = <0>;
};
/* I2S transmit channel */
i2s1: &flexcomm7 {
status = "okay";
compatible = "nxp,lpc-i2s";
#address-cells = <1>;
#size-cells = <0>;
};
&sc_timer {
status = "okay";
};
&dma0 {
status = "okay";
};
&dma1 {
status = "okay";
};
&mrt_channel0 {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,228 |
```yaml
#
#
#
identifier: lpcxpresso55s69/lpc55s69/cpu1
name: NXP LPCXpresso55S69 (CPU1)
type: mcu
arch: arm
ram: 64
flash: 256
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
vendor: nxp
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```unknown
/*
*
*/
#include "lpcxpresso55s69-pinctrl.dtsi"
/ {
aliases{
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
spi-8 = &hs_lspi;
usart-0 = &flexcomm0;
};
leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
label = "User LD2";
status = "disabled";
};
blue_led: led_2 {
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
label = "User LD3";
status = "disabled";
};
red_led: led_3 {
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
label = "User LD4";
status = "disabled";
};
};
mikrobus_header: mikrobus-connector {
compatible = "mikro-bus";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 16 0>, /* AN */
/* Not a GPIO*/ /* RST */
<2 0 &gpio1 1 0>, /* CS */
<3 0 &gpio1 2 0>, /* SCK */
<4 0 &gpio1 3 0>, /* MISO */
<5 0 &gpio0 26 0>, /* MOSI */
/* +3.3V */
/* GND */
<6 0 &gpio1 5 0>, /* PWM */
<7 0 &gpio1 18 0>, /* INT */
<8 0 &gpio1 24 0>, /* RX */
<9 0 &gpio0 27 0>, /* TX */
<10 0 &gpio1 20 0>, /* SCL */
<11 0 &gpio1 21 0>; /* SDA */
/* +5V */
/* GND */
};
arduino_header: arduino-connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 16 0>, /* A0 */
<1 0 &gpio0 23 0>, /* A1 */
<2 0 &gpio0 0 0>, /* A2 */
<3 0 &gpio1 31 0>, /* A3 */
<4 0 &gpio0 13 0>, /* A4 */
<5 0 &gpio0 14 0>, /* A5 */
<6 0 &gpio1 24 0>, /* D0 */
<7 0 &gpio0 27 0>, /* D1 */
<8 0 &gpio0 15 0>, /* D2 */
<9 0 &gpio1 6 0>, /* D3 */
<10 0 &gpio1 7 0>, /* D4 */
<11 0 &gpio1 4 0>, /* D5 */
<12 0 &gpio1 10 0>, /* D6 */
<13 0 &gpio1 9 0>, /* D7 */
<14 0 &gpio1 8 0>, /* D8 */
<15 0 &gpio1 5 0>, /* D9 */
<16 0 &gpio1 1 0>, /* D10 */
<17 0 &gpio0 26 0>, /* D11 */
<18 0 &gpio1 3 0>, /* D12 */
<19 0 &gpio1 2 0>, /* D13 */
<20 0 &gpio1 21 0>, /* D14 */
<21 0 &gpio1 20 0>; /* D15 */
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* RAM split used by TFM */
secure_ram: partition@20000000 {
label = "secure-memory";
reg = <0x20000000 DT_SIZE_K(136)>;
};
non_secure_ram: partition@20022000 {
label = "non-secure-memory";
reg = <0x20022000 DT_SIZE_K(136)>;
};
};
};
&flexcomm0 {
compatible = "nxp,lpc-usart";
current-speed = <115200>;
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(32)>;
read-only;
};
slot0_partition: partition@8000 {
label = "image-0";
reg = <0x00008000 DT_SIZE_K(160)>;
};
slot0_ns_partition: partition@30000 {
label = "image-0-nonsecure";
reg = <0x00030000 DT_SIZE_K(96)>;
};
slot1_partition: partition@48000 {
label = "image-1";
reg = <0x00048000 DT_SIZE_K(160)>;
};
slot1_ns_partition: partition@70000 {
label = "image-1-nonsecure";
reg = <0x00070000 DT_SIZE_K(96)>;
};
/*
* The flash starting at 0x88000 and ending at
* 0x949FF is reserved for the application.
*/
storage_partition: partition@88000 {
label = "storage";
reg = <0x00088000 DT_SIZE_K(50)>;
};
};
};
arduino_i2c: &flexcomm4 {
compatible = "nxp,lpc-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
mma8652fc: mma8652fc@1d {
compatible = "nxp,fxos8700","nxp,mma8652fc";
reg = <0x1d>;
int1-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
};
};
arduino_serial: &flexcomm2 {
compatible = "nxp,lpc-usart";
current-speed = <115200>;
};
arduino_spi: &hs_lspi {
};
arduino_gpio: &gpio1 {
};
mikrobus_serial: &flexcomm2 {
};
mikrobus_spi: &hs_lspi {
};
&flexcomm0 {
pinctrl-0 = <&pinmux_flexcomm0_usart>;
pinctrl-names = "default";
};
&flexcomm2 {
pinctrl-0 = <&pinmux_flexcomm2_usart>;
pinctrl-names = "default";
};
&flexcomm4 {
pinctrl-0 = <&pinmux_flexcomm4_i2c>;
pinctrl-names = "default";
};
&flexcomm6 {
pinctrl-0 = <&pinmux_flexcomm6_i2s>;
pinctrl-names = "default";
};
&flexcomm7 {
pinctrl-0 = <&pinmux_flexcomm7_i2s>;
pinctrl-names = "default";
};
&hs_lspi {
pinctrl-0 = <&pinmux_hs_lspi_default>;
pinctrl-names = "default";
};
&sc_timer {
pinctrl-0 = <&pinmux_sctimer_default>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,853 |
```cmake
#
#
#
board_runner_args(pyocd "--target=mimxrt1060")
board_runner_args(jlink "--device=MIMXRT1062xxx6A")
board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=HyperFlash")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/mimxrt1062_fmurt6/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```yaml
#
#
#
identifier: mimxrt1062_fmurt6
name: NXP MIMXRT1062-FMURT6
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 768
flash: 65536
supported:
- counter
- uart
- dma
- gpio
- i2c
- netif:eth
- sdhc
- spi
- usb_device
- can
- watchdog
- adc
- pwm
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```restructuredtext
.. _lpcxpresso55s69:
NXP LPCXPRESSO55S69
###################
Overview
********
The LPCXpresso55S69 development board provides the ideal platform for evaluation
of and development with the LPC55S6x MCU based on the Arm Cortex-M33
architecture. The board includes a high performance onboard debug probe, audio
subsystem, and accelerometer, with several options for adding off-the-shelf
add-on boards for networking, sensors, displays, and other interfaces.
.. image:: lpcxpresso55s69.jpg
:align: center
:alt: LPCXPRESSO55S69
Hardware
********
- LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz
- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link
protocol options
- UART and SPI port bridging from LPC55S69 target to USB via the onboard debug
probe
- Hardware support for external debug probe
- 3 x user LEDs, plus Reset, ISP (3) and user buttons
- Micro SD card slot (4-bit SDIO)
- NXP MMA8652FCR1 accelerometer
- Stereo audio codec with line in/out
- High and full speed USB ports with micro A/B connector for host or device
functionality
- MikroEletronika Click expansion option
- LPCXpresso-V3 expansion option compatible with Arduino UNO
- PMod compatible expansion / host connector
For more information about the LPC55S69 SoC and LPCXPRESSO55S69 board, see:
- `LPC55S69 SoC Website`_
- `LPC55S69 Datasheet`_
- `LPC55S69 Reference Manual`_
- `LPCXPRESSO55S69 Website`_
- `LPCXPRESSO55S69 User Guide`_
- `LPCXPRESSO55S69 Schematics`_
- `LPCXPRESSO55S69 Debug Firmware`_
Supported Features
==================
NXP considers the LPCXpresso55S69 as the superset board for the LPC55xx
series of MCUs. This board is a focus for NXP's Full Platform Support for
Zephyr, to better enable the entire LPC55xx series. NXP prioritizes enabling
this board with new support for Zephyr features. The lpcxpresso55s69 board
configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| IOCON | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| USART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| WWDT | on-chip | windowed watchdog timer |
+-----------+------------+-------------------------------------+
| TrustZone | on-chip | Trusted Firmware-M |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| MAILBOX | on-chip | ipm |
+-----------+------------+-------------------------------------+
| HWINFO | on-chip | Unique device serial number |
+-----------+------------+-------------------------------------+
| USB HS | on-chip | USB High Speed device |
+-----------+------------+-------------------------------------+
| USB FS | on-chip | USB Full Speed device |
+-----------+------------+-------------------------------------+
| COUNTER | on-chip | counter |
+-----------+------------+-------------------------------------+
| I2S | on-chip | i2s |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| RNG | on-chip | entropy; |
| | | random |
+-----------+------------+-------------------------------------+
| IAP | on-chip | flash programming |
+-----------+------------+-------------------------------------+
| SDIF | on-chip | sdhc |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma (on CPU0) |
+-----------+------------+-------------------------------------+
Targets available
==================
The default configuration file
:zephyr_file:`boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig`
only enables the first core.
CPU0 is the only target that can run standalone.
- *lpcxpresso55s69/lpc55s69/cpu0* secure (S) address space for CPU0
- *lpcxpresso55s69/lpc55s69/cpu0/ns* non-secure (NS) address space for CPU0
- *lpcxpresso55s69/lpc55s69/cpu1* CPU1 target, no security extensions
NS target for CPU0 does not work correctly without a secure image to configure
the system, then hand execution over to the NS environment. To enable a secure
image, run any of the ``tfm_integration`` samples. When using the NS target
``CONFIG_BUILD_WITH_TFM`` is always enabled to ensure that a valid S image is
included during the build process.
CPU1 does not work without CPU0 enabling it.
To enable it, run one of the following samples in ``subsys\ipc``:
- ``ipm_mcux``
- ``openamp``
Connections and IOs
===================
The LPC55S69 SoC has IOCON registers, which can be used to configure the
functionality of a pin.
+---------+-----------------+----------------------------+
| Name | Function | Usage |
+=========+=================+============================+
| PIO0_26 | SPI | SPI MOSI |
+---------+-----------------+----------------------------+
| PIO0_27 | USART | USART TX |
+---------+-----------------+----------------------------+
| PIO0_29 | USART | USART RX |
+---------+-----------------+----------------------------+
| PIO0_30 | USART | USART TX |
+---------+-----------------+----------------------------+
| PIO1_1 | SPI | SPI SSEL |
+---------+-----------------+----------------------------+
| PIO1_2 | SPI | SPI SCK |
+---------+-----------------+----------------------------+
| PIO1_3 | SPI | SPI MISO |
+---------+-----------------+----------------------------+
| PIO1_4 | GPIO | RED LED |
+---------+-----------------+----------------------------+
| PIO1_6 | GPIO | BLUE_LED |
+---------+-----------------+----------------------------+
| PIO1_7 | GPIO | GREEN LED |
+---------+-----------------+----------------------------+
| PIO1_20 | I2C | I2C SCL |
+---------+-----------------+----------------------------+
| PIO1_21 | I2C | I2C SDA |
+---------+-----------------+----------------------------+
| PIO1_24 | USART | USART RX |
+---------+-----------------+----------------------------+
| PIO0_20 | I2S | I2S DATAOUT |
+---------+-----------------+----------------------------+
| PIO0_19 | I2S | I2S TX WS |
+---------+-----------------+----------------------------+
| PIO0_21 | I2S | I2S TX SCK |
+---------+-----------------+----------------------------+
| PIO1_13 | I2S | I2S DATAIN |
+---------+-----------------+----------------------------+
| PIO0_15 | SCT0_OUT2 | PWM |
+---------+-----------------+----------------------------+
| PIO0_24 | SD0_D0 | SDHC |
+---------+-----------------+----------------------------+
| PIO0_25 | SD0_D1 | SDHC |
+---------+-----------------+----------------------------+
| PIO0_31 | SD0_D2 | SDHC |
+---------+-----------------+----------------------------+
| PIO0_7 | SD0_CLK | SDHC |
+---------+-----------------+----------------------------+
| PIO0_8 | SD0_CMD | SDHC |
+---------+-----------------+----------------------------+
| PIO0_9 | SD0_POW_EN | SDHC |
+---------+-----------------+----------------------------+
| PIO1_0 | SD0_D3 | SDHC |
+---------+-----------------+----------------------------+
Memory mappings
===============
There are multiple memory configurations, they all start from the
MCUboot partitioning which looks like the table below
+----------+------------------+---------------------------------+
| Name | Address[Size] | Comment |
+==========+==================+=================================+
| boot | 0x00000000[32K] | Bootloader |
+----------+------------------+---------------------------------+
| slot0 | 0x00008000[160k] | Image that runs after boot |
+----------+------------------+---------------------------------+
| slot0_ns | 0x00030000[96k] | Second image, core 1 or NS |
+----------+------------------+---------------------------------+
| slot1 | 0x00048000[160k] | Updates slot0 image |
+----------+------------------+---------------------------------+
| slot1_ns | 0x00070000[96k] | Updates slot0_ns image |
+----------+------------------+---------------------------------+
| storage | 0x00088000[50k] | File system, persistent storage |
+----------+------------------+---------------------------------+
See below examples of how this partitioning is used
Trusted Execution
*****************
+-----------+------------------+--------------------+
| Memory | Address[Size] | Comment |
+===========+==================+====================+
| MCUboot | 0x00000000[32K] | Secure bootloader |
+-----------+------------------+--------------------+
| TFM_S | 0x00008000[160k] | Secure image |
+-----------+------------------+--------------------+
| Zephyr_NS | 0x00030000[96k] | Non-Secure image |
+-----------+------------------+--------------------+
| storage | 0x00088000[50k] | Persistent storage |
+-----------+------------------+--------------------+
+----------------+------------------+-------------------+
| RAM | Address[Size] | Comment |
+================+==================+===================+
| secure_ram | 0x20000000[136k] | Secure memory |
+----------------+------------------+-------------------+
| non_secure_ram | 0x20022000[136k] | Non-Secure memory |
+----------------+------------------+-------------------+
Dual Core samples
*****************
+--------+------------------+----------------------------+
| Memory | Address[Size] | Comment |
+========+==================+============================+
| CPU0 | 0x00000000[630K] | CPU0, can access all flash |
+--------+------------------+----------------------------+
| CPU1 | 0x00030000[96k] | CPU1, has no MPU |
+--------+------------------+----------------------------+
+-------+------------------+-----------------------+
| RAM | Address[Size] | Comment |
+=======+==================+=======================+
| sram0 | 0x20000000[64k] | CPU0 memory |
+-------+------------------+-----------------------+
| sram3 | 0x20030000[64k] | CPU1 memory |
+-------+------------------+-----------------------+
| sram4 | 0x20040000[16k] | Mailbox/shared memory |
+-------+------------------+-----------------------+
System Clock
============
The LPC55S69 SoC is configured to use PLL1 clocked from the external 16MHz
crystal, running at 144MHz as a source for the system clock. When the flash
controller is enabled, the core clock will be reduced to 96MHz. The application
may reconfigure clocks after initialization, provided that the core clock is
always set to 96MHz when flash programming operations are performed.
Serial Port
===========
The LPC55S69 SoC has 8 FLEXCOMM interfaces for serial communication. One is
configured as USART for the console and the remaining are not used.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe,
however the :ref:`pyocd-debug-host-tools` does not yet support this probe so you
must reconfigure the board for one of the following debug probes instead.
:ref:`lpclink2-jlink-onboard-debug-probe`
-----------------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program
the J-Link firmware. Please make sure you have the latest firmware for this
board.
:ref:`lpclink2-cmsis-onboard-debug-probe`
-----------------------------------------
1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path.
2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware`
:ref:`opensda-daplink-onboard-debug-probe`
------------------------------------------
PyOCD support for this board is ongoing and not yet available.
To use DAPLink's flash memory programming on this board, follow the instructions
for `updating LPCXpresso firmware`_.
Configuring a Console
=====================
Connect a USB cable from your PC to P6, and use the serial terminal of your choice
(minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application. This example uses the
:ref:`jlink-debug-host-tools` as default.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: lpcxpresso55s69/lpc55s69/cpu0
:goals: flash
Open a serial terminal, reset the board (press the RESET button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0 *****
Hello World! lpcxpresso55s69
Building and flashing secure/non-secure with Arm |reg| TrustZone |reg|
your_sha256_hash------
The TF-M integration samples can be run using the
``lpcxpresso55s69/lpc55s69/cpu0/ns`` target. To run we need to manually flash
the resulting image (``tfm_merged.hex``) with a J-Link as follows
(reset and erase are for recovering a locked core):
.. code-block:: console
JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1
J-Link>r
J-Link>erase
J-Link>loadfile build/zephyr/tfm_merged.hex
We need to reset the board manually after flashing the image to run this code.
Building a dual-core image
--------------------------
The dual-core samples are run using ``lpcxpresso55s69/lpc55s69/cpu0`` target.
Images built for ``lpcxpresso55s69/lpc55s69/cpu1`` will be loaded from flash
and executed on the second core when ``SECOND_CORE_MCUX`` is selected. For
an example of building for both cores with sysbuild, see
``samples/subsys/ipc/openamp/``
Debugging
=========
Here is an example for the :ref:`hello_world` application. This example uses the
:ref:`jlink-debug-host-tools` as default.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: lpcxpresso55s69/lpc55s69/cpu0
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS zephyr-v1.14.0 *****
Hello World! lpcxpresso55s69
.. _LPC55S69 SoC Website:
path_to_url
.. _LPC55S69 Datasheet:
path_to_url
.. _LPC55S69 Reference Manual:
path_to_url
.. _LPCXPRESSO55S69 Website:
path_to_url
.. _LPCXPRESSO55S69 User Guide:
path_to_url
.. _LPCXPRESSO55S69 Debug Firmware:
path_to_url
.. _LPCXPRESSO55S69 Schematics:
path_to_url
.. _updating LPCXpresso firmware:
path_to_url
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s69/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,900 |
```unknown
/*
*
*/
#include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
/* Flash RESET pin is DNP here unlike RT1050 */
&pinctrl {
/* ADC1 inputs 0 and 15 */
pinmux_adc1: pinmux_adc1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_11_adc1_in0>;
bias-disable;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc_gpio_b0_15_enet2_ref_clk2>;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "50-mhz";
bias-pull-down-value = "100k";
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_b1_01_enet2_rx_data0>,
<&iomuxc_gpio_b1_02_enet2_rx_data1>,
<&iomuxc_gpio_b1_03_enet2_rx_en>,
<&iomuxc_gpio_b0_12_enet2_tx_data0>,
<&iomuxc_gpio_b0_13_enet2_tx_data1>,
<&iomuxc_gpio_b0_14_enet2_tx_en>,
<&iomuxc_gpio_b0_00_enet2_mdc>;
drive-strength = "r0-5";
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_b1_00_enet2_rx_er>;
bias-pull-down-value = "100k";
drive-strength = "r0-5";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group3 {
pinmux = <&iomuxc_gpio_b0_01_enet2_mdio>;
drive-strength = "r0-5";
drive-open-drain;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "50-mhz";
};
};
pinmux_flexcan1: pinmux_flexcan1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_08_flexcan1_tx>,
<&iomuxc_gpio_b0_03_flexcan1_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_flexcan2: pinmux_flexcan2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_02_flexcan2_tx>,
<&iomuxc_gpio_ad_b0_03_flexcan2_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_flexcan3: pinmux_flexcan3 {
group0 {
pinmux = <&iomuxc_gpio_emc_36_flexcan3_tx>,
<&iomuxc_gpio_ad_b0_11_flexcan3_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* pwm pins for fmu and io ports */
pinmux_flexpwm_fmu_ch1: pinmux_flexpwm_fmu_ch1 {
group0 {
pinmux = <&iomuxc_gpio_b0_06_flexpwm2_pwma0>;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_flexpwm_fmu_ch2: pinmux_flexpwm_fmu_ch2 {
group0 {
pinmux = <&iomuxc_gpio_emc_08_flexpwm2_pwma1>;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_flexpwm_fmu_ch3: pinmux_flexpwm_fmu_ch3 {
group0 {
pinmux = <&iomuxc_gpio_emc_10_flexpwm2_pwma2>;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_flexpwm_fmu_ch4: pinmux_flexpwm_fmu_ch4 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_09_flexpwm2_pwma3>;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_flexpwm_fmu_ch5: pinmux_flexpwm_fmu_ch5 {
group0 {
pinmux = <&iomuxc_gpio_emc_33_flexpwm3_pwma2>;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_flexpwm_fmu_ch6: pinmux_flexpwm_fmu_ch6 {
group0 {
pinmux = <&iomuxc_gpio_emc_30_flexpwm3_pwmb0>;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_flexpwm_fmu_ch7: pinmux_flexpwm_fmu_ch7 {
group0 {
pinmux = <&iomuxc_gpio_emc_04_flexpwm4_pwma2>;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_flexpwm_fmu_ch8: pinmux_flexpwm_fmu_ch8 {
group0 {
pinmux = <&iomuxc_gpio_emc_01_flexpwm4_pwmb0>;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_fmu_ppm_rc: pinmux_fmu_ppm_rc {
group0 {
pinmux = <&iomuxc_gpio_b1_06_gpt1_capture2>;
drive-strength = "disabled";
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
input-enable;
};
};
pinmux_flexspi1: pinmux_flexspi1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_05_flexspi_a_dqs>;
drive-strength = "r0-6";
input-schmitt-enable;
bias-pull-down;
bias-pull-down-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_sd_b1_03_flexspi_b_data0>,
<&iomuxc_gpio_sd_b1_00_flexspi_b_data3>,
<&iomuxc_gpio_sd_b1_01_flexspi_b_data2>,
<&iomuxc_gpio_sd_b1_02_flexspi_b_data1>,
<&iomuxc_gpio_sd_b1_04_flexspi_b_sclk>,
<&iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b>,
<&iomuxc_gpio_sd_b1_07_flexspi_a_sclk>,
<&iomuxc_gpio_sd_b1_08_flexspi_a_data0>,
<&iomuxc_gpio_sd_b1_09_flexspi_a_data1>,
<&iomuxc_gpio_sd_b1_10_flexspi_a_data2>,
<&iomuxc_gpio_sd_b1_11_flexspi_a_data3>;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "200-mhz";
input-enable;
};
};
/* Configures pin routing and optionally pin electrical features. */
pinmux_lpi2c1: pinmux_lpi2c1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_01_lpi2c1_sda>,
<&iomuxc_gpio_ad_b1_00_lpi2c1_scl>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
pinmux_lpi2c2: pinmux_lpi2c2 {
group0 {
pinmux = <&iomuxc_gpio_b0_05_lpi2c2_sda>,
<&iomuxc_gpio_b0_04_lpi2c2_scl>;
drive-strength = "r0-7";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
pinmux_lpi2c3: pinmux_lpi2c3 {
group0 {
pinmux = <&iomuxc_gpio_emc_21_lpi2c3_sda>,
<&iomuxc_gpio_emc_22_lpi2c3_scl>;
drive-strength = "r0-7";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
pinmux_lpi2c4: pinmux_lpi2c4 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_lpi2c4_sda>,
<&iomuxc_gpio_ad_b0_12_lpi2c4_scl>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* SPI1 SENSOR - ICM20602 */
pinmux_lpspi1: pinmux_lpspi1 {
group0 {
pinmux = <&iomuxc_gpio_emc_37_gpio3_io23>,
<&iomuxc_gpio_emc_27_lpspi1_sck>,
<&iomuxc_gpio_emc_29_lpspi1_sdi>,
<&iomuxc_gpio_emc_28_lpspi1_sdo>,
<&iomuxc_gpio_emc_12_gpio4_io12>;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "100-mhz";
bias-pull-up-value = "47k";
};
};
/* SPI2 SENSOR - ISM330 */
pinmux_lpspi2: pinmux_lpspi2 {
group0 {
pinmux = <&iomuxc_gpio_emc_34_gpio3_io20>,
<&iomuxc_gpio_emc_00_lpspi2_sck>,
<&iomuxc_gpio_emc_03_lpspi2_sdi>,
<&iomuxc_gpio_emc_02_lpspi2_sdo>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* SPI3 SENSOR - BMI088 */
pinmux_lpspi3: pinmux_lpspi3 {
group0 {
pinmux = <&iomuxc_gpio_b1_15_gpio2_io31>,
<&iomuxc_gpio_b1_10_gpio2_io26>,
<&iomuxc_gpio_ad_b1_15_lpspi3_sck>,
<&iomuxc_gpio_ad_b1_13_lpspi3_sdi>,
<&iomuxc_gpio_ad_b1_14_lpspi3_sdo>,
<&iomuxc_gpio_emc_16_gpio4_io16>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* FRAM */
pinmux_lpspi4: pinmux_lpspi4 {
group0 {
pinmux = <&iomuxc_gpio_b1_14_gpio2_io30>,
<&iomuxc_gpio_b1_07_lpspi4_sck>,
<&iomuxc_gpio_b1_05_lpspi4_sdi>,
<&iomuxc_gpio_b0_02_lpspi4_sdo>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "200-mhz";
};
};
/* FMU CONSOLE */
pinmux_lpuart7: pinmux_lpuart7 {
group0 {
pinmux = <&iomuxc_gpio_emc_32_lpuart7_rx>,
<&iomuxc_gpio_emc_31_lpuart7_tx>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart7_sleep: pinmux_lpuart7_sleep {
group0 {
pinmux = <&iomuxc_gpio_emc_32_lpuart7_rx>,
<&iomuxc_gpio_emc_31_lpuart7_tx>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "50-mhz";
};
};
pinmux_lpuart2: pinmux_lpuart2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_02_lpuart2_tx>,
<&iomuxc_gpio_ad_b1_03_lpuart2_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart2_sleep: pinmux_lpuart2_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_03_lpuart2_rx>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_02_lpuart2_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart3: pinmux_lpuart3 {
group0 {
pinmux = <&iomuxc_gpio_b0_08_lpuart3_tx>,
<&iomuxc_gpio_b0_09_lpuart3_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* Flow control for lpuart3 */
pinmux_lpuart3_flow_control: pinmux_lpuart3_flow_control {
group0 {
pinmux = <&iomuxc_gpio_b0_08_lpuart3_tx>,
<&iomuxc_gpio_b0_09_lpuart3_rx>,
<&iomuxc_gpio_sd_b1_04_gpio3_io04>,
<&iomuxc_gpio_emc_24_gpio4_io24>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
group0 {
pinmux = <&iomuxc_gpio_b0_09_lpuart3_rx>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_b0_08_lpuart3_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart5: pinmux_lpuart5 {
group0 {
pinmux = <&iomuxc_gpio_emc_23_lpuart5_tx>,
<&iomuxc_gpio_b1_13_lpuart5_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart5_sleep: pinmux_lpuart5_sleep {
group0 {
pinmux = <&iomuxc_gpio_b1_13_lpuart5_rx>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_emc_23_lpuart5_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_ptp: pinmux_ptp {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_02_enet_1588_event2_out>,
<&iomuxc_gpio_ad_b1_03_enet_1588_event2_in>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* Note SWO is configured with a cpu frequency of 132MHz and SWO frequency of 7500KHz */
pinmux_swo: pinmux_swo {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_10_arm_trace_swo>;
bias-disable;
drive-strength = "r0-7";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_usdhc1: pinmux_usdhc1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_b1_12_gpio2_io28>,
<&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_b1_14_usdhc1_vselect>;
drive-strength = "r0-4";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group3 {
pinmux = <&iomuxc_gpio_ad_b0_05_gpio1_io05>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* fast pinmux settings for USDHC (over 100 Mhz) */
pinmux_usdhc1_fast: pinmux_usdhc1_fast {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
/* medium pinmux settings for USDHC (under 100 Mhz) */
pinmux_usdhc1_med: pinmux_usdhc1_med {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
/* slow pinmux settings for USDHC (under 50 Mhz) */
pinmux_usdhc1_slow: pinmux_usdhc1_slow {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "50-mhz";
};
};
/* Wakeup Input Source */
pinmux_wakeup: pinmux_wakeup {
group0 {
pinmux = <&iomuxc_snvs_wakeup_gpio5_io00>;
drive-strength = "disabled";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "22k";
slew-rate = "slow";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,688 |
```yaml
board:
name: mimxrt1062_fmurt6
vendor: nxp
socs:
- name: mimxrt1062
``` | /content/code_sandbox/boards/nxp/mimxrt1062_fmurt6/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
# Enable Regulators
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_INIT_PRIORITY=75
``` | /content/code_sandbox/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
config BOARD_MIMXRT1062_FMURT6
select SOC_PART_NUMBER_MIMXRT1062DVL6A
``` | /content/code_sandbox/boards/nxp/mimxrt1062_fmurt6/Kconfig.mimxrt1062_fmurt6 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```unknown
# MIMXRT1062-FMURT6 board
if BOARD_MIMXRT1062_FMURT6
config DEVICE_CONFIGURATION_DATA
default y
config NXP_IMX_EXTERNAL_SDRAM
default y
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
endif # BOARD_MIMXRT1062_FMURT6
``` | /content/code_sandbox/boards/nxp/mimxrt1062_fmurt6/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt1060.dtsi>
#include "mimxrt1062_fmurt6-pinctrl.dtsi"
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <freq.h>
/ {
model = "NXP MIMXRT1062 FMURT6 board";
compatible = "nxp,mimxrt1062";
aliases {
led0 = &green_led;
led1 = &red_led;
watchdog0 = &wdog0;
sdhc0 = &usdhc1;
gps1 = &lpuart2;
telem1 = &lpuart3;
telem4-gps2 = &lpuart5;
};
chosen {
zephyr,flash-controller = &s26ks512s0;
zephyr,flash = &s26ks512s0;
zephyr,code-partition = &slot0_partition;
zephyr,sram = &ocram;
zephyr,itcm = &itcm;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart7;
zephyr,shell-uart = &lpuart7;
zephyr,canbus = &flexcan1;
};
leds {
compatible = "gpio-leds";
green_led: led-1 {
gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
label = "User LED1";
};
red_led: led-2 {
gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
label = "User LED2";
};
};
/* This regulator controls VDD_3V3_SD_CARD onboard supply */
reg-3v3-sdcard {
compatible = "regulator-fixed";
regulator-name = "reg-3v3-sdcard";
enable-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
regulator-always-on;
status = "okay";
};
/* This regulator controls VDD_5V_PERIPH onboard supply */
reg-5v-periph {
compatible = "regulator-fixed";
regulator-name = "reg-5v-periph";
enable-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
regulator-always-on;
status = "okay";
};
/* This regulator controls VDD_5V_HIPOWER onboard supply */
reg-5v-hipower {
compatible = "regulator-fixed";
regulator-name = "reg-5v-hipower";
enable-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
regulator-always-on;
status = "okay";
};
/* This regulator controls the 3V3_S line, which powers sensors on-board. */
reg-3v3-sensor {
compatible = "regulator-fixed";
regulator-name = "reg-3v3-sensor";
enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
regulator-always-on;
status = "okay";
};
/* This regulator controls VDD_3V3_SPEKTRUM onboard supply */
reg-3v3-spektrum {
compatible = "regulator-fixed";
regulator-name = "reg-3v3-spektrum";
enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
regulator-always-on;
status = "okay";
};
/* This regulator controls ETH_VDD_3V3 supply to power up the TJA1103 PHY */
reg-eth-power {
compatible = "regulator-fixed";
regulator-name = "reg-eth-power";
enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
regulator-always-on;
status = "okay";
};
};
&flexcan1 {
status = "okay";
pinctrl-0 = <&pinmux_flexcan1>;
pinctrl-names = "default";
can-transceiver {
max-bitrate = <5000000>;
};
};
&flexcan2 {
status = "disabled";
pinctrl-0 = <&pinmux_flexcan2>;
pinctrl-names = "default";
can-transceiver {
max-bitrate = <5000000>;
};
};
&flexcan3 {
status = "disabled";
pinctrl-0 = <&pinmux_flexcan3>;
pinctrl-names = "default";
can-transceiver {
max-bitrate = <5000000>;
};
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&gpio5 {
status = "okay";
};
&gpio6 {
status = "okay";
};
&gpio7 {
status = "okay";
};
&gpio8 {
status = "okay";
};
&gpio9 {
status = "okay";
};
&adc1 {
status = "okay";
pinctrl-0 = <&pinmux_adc1>;
pinctrl-names = "default";
};
&flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
ahb-bufferable;
ahb-cacheable;
sck-differential-clock;
combination-mode;
rx-clock-source = <3>;
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>;
s26ks512s0: s26ks512s@0 {
compatible = "nxp,imx-flexspi-hyperflash";
size = <DT_SIZE_M(64*8)>;
reg = <0>;
spi-max-frequency = <166000000>;
word-addressable;
cs-interval-unit = <1>;
cs-interval = <2>;
cs-hold-time = <0>;
cs-setup-time = <3>;
data-valid-time = <1>;
column-space = <3>;
ahb-write-wait-unit = <2>;
ahb-write-wait-interval = <20>;
status = "okay";
erase-block-size = <4096>;
write-block-size = <16>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
/* The MCUBoot swap-move algorithm uses the last 14 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>;
};
slot1_partition: partition@32E000 {
label = "image-1";
reg = <0x0032E000 DT_SIZE_M(3)>;
};
storage_partition: partition@62E000 {
label = "storage";
reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>;
};
};
};
};
&lpi2c1 {
status = "okay";
pinctrl-0 = <&pinmux_lpi2c1>;
pinctrl-names = "default";
};
&lpi2c2 {
status = "okay";
pinctrl-0 = <&pinmux_lpi2c2>;
pinctrl-names = "default";
bmp388: bmp388@76 {
compatible = "bosch,bmp388";
reg = <0x76>;
status = "okay";
};
};
&lpi2c4 {
status = "okay";
pinctrl-0 = <&pinmux_lpi2c2>;
pinctrl-names = "default";
bmm150: bmm150@10 {
compatible = "bosch,bmm150";
status = "disabled";
reg = <0x10>;
};
};
&lpuart7 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart7>;
pinctrl-1 = <&pinmux_lpuart7_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart2 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart2>;
pinctrl-1 = <&pinmux_lpuart2_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart3 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart3>;
pinctrl-1 = <&pinmux_lpuart3_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart5 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart5>;
pinctrl-1 = <&pinmux_lpuart5_sleep>;
pinctrl-names = "default", "sleep";
};
&lpspi1 {
status = "okay";
pinctrl-0 = <&pinmux_lpspi1>;
pinctrl-names = "default";
cs-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
clock-frequency = <DT_FREQ_M(10)>;
};
&lpspi2 {
status = "disabled";
pinctrl-0 = <&pinmux_lpspi2>;
pinctrl-names = "default";
clock-frequency = <DT_FREQ_M(1)>;
ism330dhcx: ism330dhcx@0 {
compatible = "st,ism330dhcx";
status = "disabled";
spi-max-frequency = <1000000>;
reg = <0>;
};
};
&lpspi3 {
status = "okay";
pinctrl-0 = <&pinmux_lpspi3>;
pinctrl-names = "default";
/* Accelerometer */
/* Gyroscope */
cs-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>,
<&gpio2 26 GPIO_ACTIVE_LOW>;
clock-frequency = <DT_FREQ_M(10)>;
};
&flexpwm2_pwm0 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm_fmu_ch1>;
pinctrl-names = "default";
nxp,prescaler = <64>;
};
&flexpwm2_pwm1 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm_fmu_ch2>;
pinctrl-names = "default";
nxp,prescaler = <64>;
};
&flexpwm2_pwm2 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm_fmu_ch3>;
pinctrl-names = "default";
nxp,prescaler = <64>;
};
&flexpwm2_pwm3 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm_fmu_ch4>;
pinctrl-names = "default";
nxp,prescaler = <64>;
};
&flexpwm3_pwm2 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm_fmu_ch5>;
pinctrl-names = "default";
nxp,prescaler = <64>;
};
&flexpwm3_pwm0 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm_fmu_ch6>;
pinctrl-names = "default";
nxp,prescaler = <64>;
};
&flexpwm4_pwm2 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm_fmu_ch7>;
pinctrl-names = "default";
nxp,prescaler = <64>;
};
&flexpwm4_pwm0 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm_fmu_ch8>;
pinctrl-names = "default";
nxp,prescaler = <64>;
};
&enet2_mac {
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
zephyr,random-mac-address;
phy-connection-type = "rmii";
phy-handle = <&phy>;
};
&enet2_mdio {
status = "okay";
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "ethernet-phy";
reg = <0>;
status = "okay";
};
};
zephyr_udc0: &usb1 {
status = "okay";
};
&usdhc1 {
status = "okay";
power-delay-ms = <1000>;
pwr-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinmux_usdhc1>;
pinctrl-1 = <&pinmux_usdhc1_slow>;
pinctrl-2 = <&pinmux_usdhc1_med>;
pinctrl-3 = <&pinmux_usdhc1_fast>;
pinctrl-names = "default", "slow", "med", "fast";
sdmmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
&wdog0 {
status = "okay";
};
&edma0 {
status = "okay";
};
/* GPT and Systick are enabled. If power management is enabled, the GPT
* timer will be used instead of systick, as allows the core clock to
* be gated.
*/
&gpt_hw_timer {
status = "okay";
};
&systick {
status = "okay";
};
&iomuxcgpr {
status = "okay";
};
&itm {
pinctrl-0 = <&pinmux_swo>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,107 |
```unknown
#
#
#
config BOARD_MIMXRT1160_EVK
select SOC_PART_NUMBER_MIMXRT1166DVM6A
select SOC_MIMXRT1166_CM7 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7
select SOC_MIMXRT1166_CM4 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/Kconfig.mimxrt1160_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```unknown
/*
*
* Note: File generated by gen_board_pinctrl.py
* from mimxrt1160_evk.mex
*/
#include <nxp/nxp_imx/rt/mimxrt1166dvm6a-pinctrl.dtsi>
&pinctrl {
/* conflicts with fxos8700 sensor */
pinmux_csi: pinmux_csi {
group0 {
pinmux = <&iomuxc_gpio_disp_b2_14_gpio11_io15>;
drive-strength = "high";
bias-pull-down;
slew-rate = "fast";
};
group1 {
pinmux = <&iomuxc_gpio_ad_26_gpio9_io25>;
drive-strength = "high";
bias-pull-up;
slew-rate = "fast";
};
group2 {
pinmux = <&iomuxc_lpsr_gpio_lpsr_07_lpi2c6_scl>,
<&iomuxc_lpsr_gpio_lpsr_06_lpi2c6_sda>;
drive-strength = "high";
slew-rate = "fast";
input-enable;
};
};
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc_gpio_ad_12_gpio9_io11>,
<&iomuxc_gpio_disp_b2_08_enet_rx_en>,
<&iomuxc_gpio_disp_b2_09_enet_rx_er>;
drive-strength = "high";
bias-pull-down;
slew-rate = "fast";
};
group1 {
pinmux = <&iomuxc_gpio_disp_b2_06_enet_rdata00>,
<&iomuxc_gpio_disp_b2_07_enet_rdata01>;
drive-strength = "high";
bias-pull-down;
slew-rate = "fast";
input-enable;
};
group2 {
pinmux = <&iomuxc_lpsr_gpio_lpsr_12_gpio12_io12>;
drive-strength = "high";
bias-pull-up;
slew-rate = "fast";
};
group3 {
pinmux = <&iomuxc_gpio_disp_b2_02_enet_tdata00>,
<&iomuxc_gpio_disp_b2_03_enet_tdata01>,
<&iomuxc_gpio_disp_b2_04_enet_tx_en>;
drive-strength = "high";
slew-rate = "fast";
};
group4 {
pinmux = <&iomuxc_gpio_disp_b2_05_enet_ref_clk>;
drive-strength = "high";
slew-rate = "slow";
input-enable;
};
};
pinmux_enet_mdio: pinmux_enet_mdio {
group0 {
pinmux = <&iomuxc_gpio_ad_32_enet_mdc>,
<&iomuxc_gpio_ad_33_enet_mdio>;
drive-strength = "high";
slew-rate = "fast";
};
};
pinmux_ptp: pinmux_ptp {
};
pinmux_flexcan3: pinmux_flexcan3 {
group0 {
pinmux = <&iomuxc_lpsr_gpio_lpsr_01_can3_rx>,
<&iomuxc_lpsr_gpio_lpsr_00_can3_tx>;
drive-strength = "high";
slew-rate = "fast";
};
};
pinmux_flexpwm1: pinmux_flexpwm1 {
group0 {
pinmux = <&iomuxc_gpio_ad_04_flexpwm1_pwm2_a>;
drive-strength = "high";
bias-pull-down;
slew-rate = "fast";
};
};
pinmux_flexspi1: pinmux_flexspi1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b2_05_flexspi1_a_dqs>,
<&iomuxc_gpio_sd_b2_06_flexspi1_a_ss0_b>,
<&iomuxc_gpio_sd_b2_07_flexspi1_a_sclk>,
<&iomuxc_gpio_sd_b2_08_flexspi1_a_data00>,
<&iomuxc_gpio_sd_b2_09_flexspi1_a_data01>,
<&iomuxc_gpio_sd_b2_10_flexspi1_a_data02>,
<&iomuxc_gpio_sd_b2_11_flexspi1_a_data03>;
bias-pull-down;
input-enable;
};
};
/* interrupt gpios for fxos8700 */
pinmux_fxos8700_int: pinmux_fxos8700_int {
group0 {
pinmux = <&iomuxc_gpio_disp_b2_14_gpio11_io15>,
<&iomuxc_gpio_disp_b2_13_gpio11_io14>;
drive-strength = "high";
slew-rate = "fast";
};
};
/* conflicts with lpspi1 */
pinmux_lcdif: pinmux_lcdif {
group0 {
pinmux = <&iomuxc_gpio_ad_30_gpio9_io29>,
<&iomuxc_gpio_ad_02_gpio9_io01>;
drive-strength = "high";
bias-pull-down;
slew-rate = "fast";
};
group1 {
pinmux = <&iomuxc_gpio_disp_b2_15_gpio11_io16>;
drive-strength = "high";
bias-pull-up;
slew-rate = "fast";
};
};
pinmux_lpadc0: pinmux_lpadc0 {
group0 {
pinmux = <&iomuxc_gpio_ad_06_adc1_ch0a>;
drive-strength = "high";
bias-pull-down;
slew-rate = "fast";
};
};
pinmux_lpi2c1: pinmux_lpi2c1 {
group0 {
pinmux = <&iomuxc_gpio_ad_08_lpi2c1_scl>,
<&iomuxc_gpio_ad_09_lpi2c1_sda>;
drive-strength = "normal";
drive-open-drain;
slew-rate = "fast";
input-enable;
};
};
/* Connected to FXOS8700 */
pinmux_lpi2c5: pinmux_lpi2c5 {
group0 {
pinmux = <&iomuxc_lpsr_gpio_lpsr_05_lpi2c5_scl>,
<&iomuxc_lpsr_gpio_lpsr_04_lpi2c5_sda>;
drive-strength = "normal";
drive-open-drain;
slew-rate = "fast";
input-enable;
};
};
pinmux_lpspi1: pinmux_lpspi1 {
group0 {
pinmux = <&iomuxc_gpio_ad_29_lpspi1_pcs0>,
<&iomuxc_gpio_ad_28_lpspi1_sck>,
<&iomuxc_gpio_ad_31_lpspi1_sdi>,
<&iomuxc_gpio_ad_30_lpspi1_sdo>;
drive-strength = "high";
slew-rate = "fast";
};
};
pinmux_lpuart1: pinmux_lpuart1 {
group0 {
pinmux = <&iomuxc_gpio_ad_25_lpuart1_rx>,
<&iomuxc_gpio_ad_24_lpuart1_tx>;
drive-strength = "high";
slew-rate = "fast";
};
};
pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_25_gpio_mux3_io24>;
drive-strength = "high";
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <&iomuxc_gpio_ad_24_lpuart1_tx>;
drive-strength = "high";
slew-rate = "fast";
};
};
pinmux_lpuart2: pinmux_lpuart2 {
group0 {
pinmux = <&iomuxc_gpio_disp_b2_11_lpuart2_rx>,
<&iomuxc_gpio_disp_b2_10_lpuart2_tx>;
drive-strength = "high";
slew-rate = "fast";
};
};
pinmux_lpuart2_sleep: pinmux_lpuart2_sleep {
group0 {
pinmux = <&iomuxc_gpio_disp_b2_11_gpio_mux5_io12>;
drive-strength = "high";
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <&iomuxc_gpio_disp_b2_10_lpuart2_tx>;
drive-strength = "high";
slew-rate = "fast";
};
};
pinmux_sai1: pinmux_sai1 {
group0 {
pinmux = <&iomuxc_gpio_ad_17_sai1_mclk>,
<&iomuxc_gpio_ad_20_sai1_rx_data00>,
<&iomuxc_gpio_ad_21_sai1_tx_data00>,
<&iomuxc_gpio_ad_22_sai1_tx_bclk>,
<&iomuxc_gpio_ad_23_sai1_tx_sync>;
drive-strength = "high";
slew-rate = "fast";
input-enable;
};
};
/* conflicts with enet pins */
pinmux_usdhc1: pinmux_usdhc1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b1_01_usdhc1_clk>,
<&iomuxc_gpio_sd_b1_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b1_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b1_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b1_05_usdhc1_data3>;
bias-pull-up;
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_ad_34_usdhc1_vselect>,
<&iomuxc_gpio_ad_32_gpio_mux3_io31_cm7>;
drive-strength = "high";
bias-pull-down;
slew-rate = "fast";
};
group2 {
pinmux = <&iomuxc_gpio_ad_35_gpio10_io02>;
drive-strength = "high";
bias-pull-up;
slew-rate = "fast";
};
};
/* removes pull on dat3 for card detect */
pinmux_usdhc1_dat3_nopull: pinmux_usdhc1_dat3_nopull {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_05_usdhc1_data3>;
bias-disable;
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b1_01_usdhc1_clk>,
<&iomuxc_gpio_sd_b1_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b1_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b1_04_usdhc1_data2>;
bias-pull-up;
input-enable;
};
group2 {
pinmux = <&iomuxc_gpio_ad_34_usdhc1_vselect>,
<&iomuxc_gpio_ad_32_gpio_mux3_io31_cm7>;
drive-strength = "high";
bias-pull-down;
slew-rate = "fast";
};
group3 {
pinmux = <&iomuxc_gpio_ad_35_gpio10_io02>;
drive-strength = "high";
bias-pull-up;
slew-rate = "fast";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,776 |
```cmake
#
#
#
if(CONFIG_SOC_MIMXRT1166_CM7 OR CONFIG_SECOND_CORE_MCUX)
board_runner_args(pyocd "--target=mimxrt1160_cm7")
board_runner_args(jlink "--device=MIMXRT1166xxx6_M7" "--reset-after-load")
board_runner_args(linkserver "--device=MIMXRT1166xxxxx:MIMXRT1160-EVK")
elseif(CONFIG_SOC_MIMXRT1166_CM4)
board_runner_args(pyocd "--target=mimxrt1160_cm4")
# Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
board_runner_args(jlink "--device=MIMXRT1166xxx6_M4")
endif()
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 218 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```yaml
#
#
#
identifier: mimxrt1160_evk/mimxrt1166/cm7
name: NXP MIMXRT1160-EVK CM7
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 256
flash: 16384
supported:
- counter
- can
- dma
- gpio
- hwinfo
- i2c
- netif:eth
- pwm
- spi
- usb_device
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 136 |
```restructuredtext
.. _fmurt6:
NXP FMURT6
##################
Overview
********
The MIMXRT1062_FMURT6 adds to the industry's crossover
processor series and expands the i.MX RT series to three scalable families.
The i.MX RT1062 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin
compatibility with i.MX RT1050. This series introduces additional features
ideal for real-time applications such as High-Speed GPIO, CAN FD, and
synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1062 runs on the
Arm Cortex-M7 core up to 600 MHz.
.. image:: mimxrt1062_fmurt6.jpg
:align: center
:alt: MIMXRT1062_FMURT6
Hardware
********
- MIMXRT1062DVL6B MCU (600 MHz, 1024 KB on-chip memory)
- Memory
- 256 Mbit SDRAM
- 512 Mbit Hyper Flash
- TF socket for SD card
- Ethernet
- 10/100 Mbit/s Ethernet PHY
- USB
- USB 2.0 OTG connector
- USB 2.0 host connector
- Audio
- 3.5 mm audio stereo headphone jack
- Board-mounted microphone
- Left and right speaker out connectors
- Power
- 5 V DC jack
- Debug
- JTAG 20-pin connector
- OpenSDA with DAPLink
- Sensor
- BMI088 6-axis e-compass
- Expansion port
- Arduino interface
- CAN bus connector
For more information about the MIMXRT1062 SoC and MIMXRT1062-FMURT6 board, see
these references:
- `i.MX RT1060 Website`_
- `i.MX RT1060 Reference Manual`_
- `MIMXRT1062-FMURT6 User Guide`_
- `MIMXRT1062-FMURT6 Schematics`_
Supported Features
==================
The mimxrt1062_fmurt6 board configuration supports the hardware features listed
below. For additional features not yet supported, please also refer to the
:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
NXP prioritizes enabling the superset board with NXP's Full Platform Support for
Zephyr. Therefore, the mimxrt1064_evk board may have additional features
already supported, which can also be re-used on this mimxrt1060_evk board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| DISPLAY | on-chip | display |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | QSPI hyper flash |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| CAN | on-chip | can |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
| FLEXSPI | on-chip | flash programming |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig`
Other hardware features are not currently supported by the port.
Connections and I/Os
====================
The MIMXRT1062 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| Name | Function | Usage |
+===============+=================+===========================+
| GPIO_AD_B1_08 | FLEXCAN1 TX | CAN |
+---------------+-----------------+---------------------------+
| GPIO_B0_03 | FLEXCAN1 RX | CAN |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_06 | PWM2A0 | PWM |
+---------------+-----------------+---------------------------+
| GPIO_EMC_08 | PWM2A1 | PWM |
+---------------+-----------------+---------------------------+
| GPIO_EMC_10 | PWM2A2 | PWM |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_09 | PWM2A3 | PWM |
+---------------+-----------------+---------------------------+
| GPIO_EMC_31 | LPUART7_TX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_EMC_32 | LPUART7_RX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_B0_04 | LPI2C2_SCL | I2C |
+---------------+-----------------+---------------------------+
| GPIO_B0_05 | LPI2C2_SDA | I2C |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_00 | LPI2C1_SCL | I2C |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_01 | LPI2C1_SDA | I2C |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_12 | LPI2C4_SCL | I2C |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | LPI2C4_SDA | I2C |
+---------------+-----------------+---------------------------+
| WAKEUP | GPIO | SW0 |
+---------------+-----------------+---------------------------+
| GPIO_B1_01 | ENET_RX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_02 | ENET_RX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_03 | ENET_RX_EN | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B0_12 | ENET_TX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B0_13 | ENET_TX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B0_14 | ENET_TX_EN | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B0_15 | ENET_REF_CLK | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_00 | ENET_RX_ER | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_12 | GPIO | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_B1_14 | USDHC1_VSELECT | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_EMC_40 | ENET_MDC | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B0_01 | ENET_MDIO | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_00 | USDHC1_CMD | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_01 | USDHC1_CLK | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_02 | USDHC1_DATA0 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_03 | USDHC1_DATA1 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_EMC_27 | LPSPI1_SCK | SPI |
+---------------+-----------------+---------------------------+
| GPIO_EMC_28 | LPSPI1_SDO | SPI |
+---------------+-----------------+---------------------------+
| GPIO_EMC_29 | LPSPI1_SDI | SPI |
+---------------+-----------------+---------------------------+
| GPIO_EMC_00 | LPSPI2_SCK | SPI |
+---------------+-----------------+---------------------------+
| GPIO_EMC_02 | LPSPI2_SDO | SPI |
+---------------+-----------------+---------------------------+
| GPIO_EMC_03 | LPSPI2_SDI | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_15 | LPSPI3_SCK | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_14 | LPSPI3_SDO | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_13 | LPSPI3_SDI | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_09 | ADC | ADC1 Channel 14 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_15 | ADC | ADC1 Channel 4 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_02 | UART2_TX_GPS1 | UART GPS |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_03 | UART2_RX_GPS1 | UART GPS |
+---------------+-----------------+---------------------------+
System Clock
============
The MIMXRT1062 SoC is configured to use SysTick as the system clock source,
running at 600MHz.
When power management is enabled, the 32 KHz low frequency
oscillator on the board will be used as a source for the GPT timer to
generate a system clock. This clock enables lower power states, at the
cost of reduced resolution
Serial Port
===========
The MIMXRT1062 SoC has eight UARTs. ``LPUART7`` is configured for the console,
``LPUART8 and 2`` for GPS/MAG, ``LPUART3 and 4`` for Telemetry and the remaining are not used.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`,
however the :ref:`pyocd-debug-host-tools` do not yet support programming the
external flashes on this board so you must reconfigure the board for one of the
following debug probes instead.
.. _Using J-Link RT1062:
Using J-Link
---------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
For Hyperflash support on i.MxRT106x use JLink_V780 or above.
There are two options: the onboard debug circuit can be updated with Segger
J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the
FMURT6 on J23 FMU Debug Port.
Run JLink.exe and choose device / core as MIMXRT106A-ALEXA.
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console.
Connect a USB cable from your PC to PixHawk debug adapter.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Using SWO
---------
SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``.
Your SWO viewer should be configured with a CPU frequency of 132MHz, and
SWO frequency of 7500KHz.
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1062_fmurt6
:goals: flash
Open a serial terminal, reset the board (press the SW9 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v3.20.0 *****
Hello World! mimxrt1062_fmurt6
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1062_fmurt6
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v3.20.0 *****
Hello World! mimxrt1062_fmurt6
Troubleshooting
===============
If the west flash or debug commands fail, and the command hangs while executing
runners.jlink, confirm the J-Link debug probe is configured, powered, and
connected to the FMURT6 properly.
.. _MIMXRT1062-FMURT6 Website:
path_to_url#
.. _MIMXRT1062-FMURT6 User Guide:
path_to_url
.. _MIMXRT1062-FMURT6 Schematics:
path_to_url
.. _i.MX RT1060 Website:
path_to_url
.. _i.MX RT1060 Datasheet:
path_to_url
.. _i.MX RT1060 Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/nxp/mimxrt1062_fmurt6/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,320 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```yaml
#
#
#
identifier: mimxrt1160_evk/mimxrt1166/cm4
name: NXP MIMXRT1160-EVK CM4
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 128
flash: 128
supported:
- dma
- i2c
- gpio
- pwm
- uart
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```yaml
board:
name: mimxrt1160_evk
vendor: nxp
socs:
- name: mimxrt1166
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
#include "mimxrt1160_evk-pinctrl.dtsi"
#include <nxp/nxp_rt1160.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases {
led0 = &green_led;
sw0 = &user_button;
magn0 = &fxos8700;
accel0 = &fxos8700;
sdhc0 = &usdhc1;
};
leds {
compatible = "gpio-leds";
green_led: led-1 {
gpios = <&gpio9 3 GPIO_ACTIVE_LOW>;
label = "User LED D6";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button-1 {
label = "User SW7";
gpios = <&gpio13 0 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
pwmleds {
compatible = "pwm-leds";
green_pwm_led: green_pwm_led {
pwms = <&flexpwm1_pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart1>;
pinctrl-1 = <&pinmux_lpuart1_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart2 {
pinctrl-0 = <&pinmux_lpuart2>;
pinctrl-1 = <&pinmux_lpuart2_sleep>;
pinctrl-names = "default", "sleep";
};
&user_button {
status = "okay";
};
&green_led {
status = "okay";
};
&lpi2c5 {
status = "okay";
pinctrl-0 = <&pinmux_lpi2c5>;
pinctrl-names = "default";
fxos8700: fxos8700@1f {
compatible = "nxp,fxos8700";
reg = <0x1f>;
/* Two zero ohm resistors (R256 and R270) isolate sensor
* interrupt gpios from the soc and are unpopulated by default.
* Note that if you populate them, they conflict with camera and
* ethernet PHY reset signals.
*/
int1-gpios = <&gpio11 14 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpio11 15 GPIO_ACTIVE_LOW>;
};
};
&flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
is25wp128: is25wp128@0 {
compatible = "nxp,imx-flexspi-nor";
size = <DT_SIZE_M(16*8)>;
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [9d 70 17];
erase-block-size = <4096>;
write-block-size = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
/* The MCUBoot swap-move algorithm uses the last 3 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>;
};
slot1_partition: partition@723000 {
label = "image-1";
reg = <0x00723000 DT_SIZE_M(7)>;
};
storage_partition: partition@E23000 {
label = "storage";
reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>;
};
};
};
};
&flexpwm1_pwm2 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm1>;
pinctrl-names = "default";
};
&enet_mac {
status = "okay";
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
phy-connection-type = "rmii";
zephyr,random-mac-address;
};
&enet_mdio {
status = "okay";
pinctrl-0 = <&pinmux_enet_mdio>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "microchip,ksz8081";
reg = <0>;
status = "okay";
reset-gpios = <&gpio12 12 GPIO_ACTIVE_HIGH>;
int-gpios = <&gpio9 11 GPIO_ACTIVE_HIGH>;
microchip,interface-type = "rmii";
};
};
&enet_ptp_clock {
status = "okay";
pinctrl-0 = <&pinmux_ptp>;
pinctrl-names = "default";
};
&csi {
pinctrl-0 = <&pinmux_csi>;
pinctrl-names = "default";
};
&flexcan3 {
pinctrl-0 = <&pinmux_flexcan3>;
pinctrl-names = "default";
};
&lcdif {
pinctrl-0 = <&pinmux_lcdif>;
pinctrl-names = "default";
};
&lpi2c1 {
pinctrl-0 =<&pinmux_lpi2c1>;
pinctrl-names = "default";
};
&lpspi1 {
pinctrl-0 = <&pinmux_lpspi1>;
pinctrl-names = "default";
};
&lpuart2 {
pinctrl-0 = <&pinmux_lpuart2>;
pinctrl-1 = <&pinmux_lpuart2_sleep>;
pinctrl-names = "default", "sleep";
};
&sai1 {
pinctrl-0 = <&pinmux_sai1>;
pinctrl-names = "default";
};
&lpadc0 {
pinctrl-0 = <&pinmux_lpadc0>;
pinctrl-names = "default";
};
&flexspi {
pinctrl-0 = <&pinmux_flexspi1>;
pinctrl-names = "default";
};
&usdhc1 {
pinctrl-0 = <&pinmux_usdhc1>;
pinctrl-1 = <&pinmux_usdhc1_dat3_nopull>;
pinctrl-names = "default", "nopull";
};
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,525 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt11xx_cm4.dtsi>
#include "mimxrt1160_evk.dtsi"
/ {
model = "NXP MIMXRT1160-EVK board";
compatible = "nxp,mimxrt1166";
chosen {
/*
* Note: when using DMA, the SRAM region must be set to
* a memory region that is not cached by the chip. If the chosen
* sram region is changed and DMA is in use, you will
* encounter issues!
*/
zephyr,sram = &sram1;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,flash-controller = &is25wp128;
zephyr,flash = &is25wp128;
nxp,m4-partition = &slot1_partition;
zephyr,ipc = &mailbox_b;
};
sdram0: memory@80000000 {
/* Winbond W9825G6KH-5I */
device_type = "memory";
reg = <0x80000000 DT_SIZE_M(64)>;
};
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
};
&lpi2c1 {
status = "okay";
};
/* GPT and Systick are enabled. If power management is enabled, the GPT
* timer will be used instead of systick, as allows the core clock to
* be gated.
*/
&gpt_hw_timer {
status = "okay";
};
&systick {
status = "okay";
};
&edma_lpsr0 {
status = "okay";
};
&mailbox_b {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 394 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt11xx_cm7.dtsi>
#include "mimxrt1160_evk.dtsi"
/ {
model = "NXP MIMXRT1160-EVK board";
compatible = "nxp,mimxrt1166";
chosen {
zephyr,sram = &sdram0;
zephyr,dtcm = &dtcm;
zephyr,itcm = &itcm;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,canbus = &flexcan3;
zephyr,flash-controller = &is25wp128;
zephyr,flash = &is25wp128;
zephyr,code-partition = &slot0_partition;
zephyr,cpu1-region = &ocram;
zephyr,ipc = &mailbox_a;
};
sdram0: memory@80000000 {
/* Winbond W9825G6KH-5I */
device_type = "memory";
reg = <0x80000000 DT_SIZE_M(64)>;
};
aliases {
watchdog0 = &wdog1;
};
/*
* This node describes the GPIO pins mapping of the 44-pin camera
* connector, J2 on the EVK. This camera interface is supported
* on several NXP RT11xx EVKs, such as RT1170 and RT1160 EVK and
* is used with an ov5640 camera module available as a Zephyr shield
*/
nxp_cam_connector: cam-connector {
compatible = "nxp,cam-44pins-connector";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <9 0 &gpio11 15 0>, /* Pin 9, RESETB */
<17 0 &gpio9 25 0>; /* Pin 17, PWDN */
};
/*
* This node describes the GPIO pins of the MIPI FPC interface,
* J48 on the EVK. This interface is standard to several
* NXP EVKs, and is used with several MIPI displays
* (available as zephyr shields)
*/
nxp_mipi_connector: mipi-connector {
compatible = "gpio-nexus";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio9 29 0>, /* Pin 1, LEDK */
<21 0 &gpio9 1 0>, /* Pin 21, RESET */
<22 0 &gpio9 4 0>, /* Pin 22, LPTE */
<26 0 &gpio6 4 0>, /* Pin 26, CTP_I2C SDA */
<27 0 &gpio6 5 0>, /* Pin 27, CTP_I2C SCL */
<28 0 &gpio9 0 0>, /* Pin 28, CTP_RST */
<29 0 &gpio2 31 0>, /* Pin 29, CTP_INT */
<32 0 &gpio11 16 0>, /* Pin 32, PWR_EN */
<34 0 &gpio9 29 0>; /* Pin 34, BL_PWM */
};
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
};
&flexcan3 {
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&lpi2c1 {
status = "okay";
};
&lpspi1 {
status = "okay";
};
/* GPT and Systick are enabled. If power management is enabled, the GPT
* timer will be used instead of systick, as allows the core clock to
* be gated.
*/
&gpt_hw_timer {
status = "okay";
};
&systick {
status = "okay";
};
&lpadc0 {
status = "okay";
};
&wdog1 {
status = "okay";
};
&edma0 {
status = "okay";
};
zephyr_udc0: &usb1 {
status = "okay";
};
&mailbox_a {
status = "okay";
};
&pit1 {
status = "okay";
};
&pit2 {
status = "okay";
};
nxp_cam_i2c: &lpi2c6 {};
nxp_mipi_csi: &mipi_csi2rx {};
nxp_csi: &csi {};
zephyr_lcdif: &lcdif {};
zephyr_mipi_dsi: &mipi_dsi {
dphy-ref-frequency = <24000000>;
};
nxp_mipi_i2c: &lpi2c5 {
pinctrl-0 = <&pinmux_lpi2c5>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
};
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,177 |
```unknown
# MIMXRT1160-EVK board
if BOARD_MIMXRT1160_EVK
# Only use DCD when booting primary core (M7)
config DEVICE_CONFIGURATION_DATA
default y if CPU_CORTEX_M7
config NXP_IMX_EXTERNAL_SDRAM
default y if CPU_CORTEX_M7
if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4
config BUILD_OUTPUT_INFO_HEADER
default y
DT_CHOSEN_IMAGE_M4 = nxp,m4-partition
# Adjust the offset of the output image if building for RT11xx SOC
config BUILD_OUTPUT_ADJUST_LMA
default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \
$(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \
$(dt_node_reg_addr_hex,/soc/ocram@20200000)"
endif
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 240000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 && CORTEX_M_SYSTICK
default 600000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 && CORTEX_M_SYSTICK
if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7
default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4
endchoice
endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
if NETWORKING
config NET_L2_ETHERNET
default y if CPU_CORTEX_M7 # No cache memory support is required for driver
config ETH_MCUX_PHY_RESET
default y
endif # NETWORKING
endif # BOARD_MIMXRT1160_EVK
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 418 |
```unknown
# ARM Options
CONFIG_AARCH64_IMAGE_HEADER=y
CONFIG_ARMV8_A_NS=y
CONFIG_ARM64_VA_BITS_36=y
CONFIG_ARM64_PA_BITS_36=y
# Cache Options
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE_LINE_SIZE_DETECT=y
CONFIG_ICACHE_LINE_SIZE_DETECT=y
# Zephyr Kernel Configuration
CONFIG_XIP=n
CONFIG_KERNEL_DIRECT_MAP=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```unknown
config BOARD_IMX8MM_EVK
select SOC_MIMX8MM6_A53 if BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP
select SOC_MIMX8MM6_M4 if BOARD_IMX8MM_EVK_MIMX8MM6_M4
select SOC_PART_NUMBER_MIMX8MM6DVTLZ
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/Kconfig.imx8mm_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```cmake
if(CONFIG_BOARD_IMX8MM_EVK_MIMX8MM6_M4)
board_set_debugger_ifnset(jlink)
board_set_flasher_ifnset(jlink)
board_runner_args(jlink "--device=MIMX8MD6_M4")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
endif()
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_mimx8mm_a53.dtsi>
#include "imx8mm_evk-pinctrl.dtsi"
/ {
model = "NXP i.MX8MM A53";
compatible = "fsl,mimx8mm";
chosen {
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
zephyr,sram = &sram0;
};
cpus {
cpu@0 {
status = "disabled";
};
cpu@1 {
status = "disabled";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
sram0: memory@93c00000 {
reg = <0x93c00000 DT_SIZE_M(1)>;
};
};
&enet {
status = "okay";
};
&enet_mac {
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rgmii";
status = "okay";
};
&enet_mdio {
pinctrl-0 = <&pinmux_mdio>;
pinctrl-names = "default";
status = "okay";
phy: phy@0 {
compatible = "qca,ar8031";
reg = <0>;
status = "okay";
};
};
&uart4 {
current-speed = <115200>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 370 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_imx8mm_m4.dtsi>
#include "imx8mm_evk-pinctrl.dtsi"
/ {
model = "NXP i.MX8M Mini EVK board";
compatible = "nxp,mimx8mm_evk";
aliases {
uart-4 = &uart4;
};
chosen {
zephyr,flash = &tcml_code;
zephyr,sram = &tcmu_sys;
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
};
};
&uart4 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
};
&mailbox0 {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 189 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_mimx8mm_a53.dtsi>
#include "imx8mm_evk-pinctrl.dtsi"
/ {
model = "NXP i.MX8MM A53";
compatible = "fsl,mimx8mm";
chosen {
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
zephyr,sram = &sram0;
};
cpus {
cpu@0 {
status = "disabled";
};
cpu@1 {
status = "disabled";
};
cpu@2 {
status = "disabled";
};
};
sram0: memory@93c00000 {
reg = <0x93c00000 DT_SIZE_M(1)>;
};
};
&enet {
status = "okay";
};
&enet_mac {
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rgmii";
status = "okay";
};
&enet_mdio {
pinctrl-0 = <&pinmux_mdio>;
pinctrl-names = "default";
status = "okay";
phy: phy@0 {
compatible = "qca,ar8031";
reg = <0>;
status = "okay";
};
};
&uart4 {
current-speed = <115200>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 358 |
```yaml
#
#
#
identifier: imx8mm_evk/mimx8mm6/a53
name: NXP i.MX8M Mini EVK A53
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 128
testing:
ignore_tags:
- net
- bluetooth
vendor: nxp
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
# ARM Options
CONFIG_AARCH64_IMAGE_HEADER=y
CONFIG_ARMV8_A_NS=y
CONFIG_ARM64_VA_BITS_36=y
CONFIG_ARM64_PA_BITS_36=y
# Cache Options
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE_LINE_SIZE_DETECT=y
CONFIG_ICACHE_LINE_SIZE_DETECT=y
# Zephyr Kernel Configuration
CONFIG_XIP=n
CONFIG_KERNEL_DIRECT_MAP=y
# SMP
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=2
CONFIG_PM_CPU_OPS=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 147 |
```yaml
board:
name: imx8mm_evk
vendor: nxp
socs:
- name: mimx8mm6
variants:
- name: smp
cpucluster: a53
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```yaml
#
#
#
identifier: imx8mm_evk/mimx8mm6/m4
name: NXP i.MX8M Mini EVK
type: mcu
arch: arm
ram: 128
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
testing:
ignore_tags:
- net
- bluetooth
vendor: nxp
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```yaml
#
#
#
identifier: imx8mm_evk/mimx8mm6/a53/smp
name: NXP i.MX8M Mini EVK A53 with SMP kernel
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 128
supported:
- smp
testing:
ignore_tags:
- net
- bluetooth
vendor: nxp
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```unknown
#
#
#
CONFIG_CLOCK_CONTROL=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_XIP=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
if BOARD_IMX8MM_EVK
if BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP
if NETWORKING
config NET_L2_ETHERNET
default y
config NET_TX_STACK_SIZE
default 8192
config NET_RX_STACK_SIZE
default 8192
if NET_TCP
config NET_TCP_WORKQ_STACK_SIZE
default 8192
endif # NET_TCP
if NET_MGMT_EVENT
config NET_MGMT_EVENT_STACK_SIZE
default 8192
endif # NET_MGMT_EVENT
if NET_SOCKETS_SERVICE
config NET_SOCKETS_SERVICE_STACK_SIZE
default 8192
endif # NET_SOCKETS_SERVICE
endif # NETWORKING
endif # BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP
endif # BOARD_IMX8MM_EVK
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 208 |
```restructuredtext
.. _mimxrt1160_evk:
NXP MIMXRT1160-EVK
##################
Overview
********
The dual core i.MX RT1160 runs on the Cortex-M7 core at 600 MHz and on the
Cortex-M4 at 240 MHz. The i.MX RT1160 MCU offers support over a wide
temperature range and is qualified for consumer, industrial and automotive
markets.
.. image:: mimxrt1160_evk.jpg
:align: center
:alt: MIMXRT1160-EVK
Hardware
********
- MIMXRT1166DVM6A MCU
- 600MHz Cortex-M7 & 240Mhz Cortex-M4
- 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4
- Memory
- 512 Mbit SDRAM
- 128 Mbit QSPI Flash
- 512 Mbit Octal Flash
- TF socket for SD card
- Display
- MIPI LCD connector
- Ethernet
- 10/100 Mbit/s Ethernet PHY
- 10/100/1000 Mbit/s Ethernet PHY
- USB
- USB 2.0 OTG connector
- USB 2.0 host connector
- Audio
- 3.5 mm audio stereo headphone jack
- Board-mounted microphone
- Left and right speaker out connectors
- Power
- 5 V DC jack
- Debug
- JTAG 20-pin connector
- OpenSDA with DAPLink
- Sensor
- MIPI camera sensor connector
- Expansion port
- Arduino interface
- CAN bus connector
For more information about the MIMXRT1160 SoC and MIMXRT1160-EVK board, see
these references:
- `i.MX RT1160 Website`_
- `i.MX RT1160 Datasheet`_
- `i.MX RT1160 Reference Manual`_
- `MIMXRT1160-EVK Website`_
- `MIMXRT1160-EVK Board Hardware User's Guide`_
External Memory
===============
This platform has the following external memories:
+--------------------+------------+-------------------------------------+
| Device | Controller | Status |
+====================+============+=====================================+
| W9825G6KH | SEMC | Enabled via device configuration |
| | | data block, which sets up SEMC at |
| | | boot time |
+--------------------+------------+-------------------------------------+
| IS25WP128 | FLEXSPI | Enabled via flash configurationn |
| | | block, which sets up FLEXSPI at |
| | | boot time. |
+--------------------+------------+-------------------------------------+
Supported Features
==================
The mimxrt1160_evk board configuration supports the hardware features listed
below. For additional features not yet supported, please also refer to the
:ref:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family.
NXP prioritizes enabling the superset board with NXP's Full Platform Support for
Zephyr. Therefore, the mimxrt1170_evk board may have additional features
already supported, which can also be re-used on this mimxrt1160_evk board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| COUNTER | on-chip | counter |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| CAN | on-chip | flexcan |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB Device |
+-----------+------------+-------------------------------------+
| HWINFO | on-chip | Unique device serial number |
+-----------+------------+-------------------------------------+
| CAAM RNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
| FLEXSPI | on-chip | flash programming |
+-----------+------------+-------------------------------------+
| PIT | on-chip | pit |
+-----------+------------+-------------------------------------+
| DISPLAY | on-chip | eLCDIF; MIPI-DSI. Tested with |
| | | :ref:`rk055hdmipi4m`, |
| | | :ref:`rk055hdmipi4ma0`, |
| | | and :ref:`g1120b0mipi` shields |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig`
Other hardware features are not currently supported by the port.
Connections and I/Os
====================
The MIMXRT1160 SoC has six pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| Name | Function | Usage |
+===============+=================+===========================+
| WAKEUP | GPIO | SW7 |
+---------------+-----------------+---------------------------+
| GPIO_AD_04 | GPIO | LED |
+---------------+-----------------+---------------------------+
| GPIO_AD_24 | LPUART1_TX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_25 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_LPSR_00 | CAN3_TX | flexcan |
+---------------+-----------------+---------------------------+
| GPIO_LPSR_01 | CAN3_RX | flexcan |
+---------------+-----------------+---------------------------+
| GPIO_AD_29 | SPI1_CS0 | spi |
+---------------+-----------------+---------------------------+
| GPIO_AD_28 | SPI1_CLK | spi |
+---------------+-----------------+---------------------------+
| GPIO_AD_30 | SPI1_SDO | spi |
+---------------+-----------------+---------------------------+
| GPIO_AD_31 | SPI1_SDI | spi |
+---------------+-----------------+---------------------------+
| GPIO_AD_08 | LPI2C1_SCL | i2c |
+---------------+-----------------+---------------------------+
| GPIO_AD_09 | LPI2C1_SDA | i2c |
+---------------+-----------------+---------------------------+
| GPIO_LPSR_05 | LPI2C5_SCL | i2c |
+---------------+-----------------+---------------------------+
| GPIO_LPSR_04 | LPI2C5_SDA | i2c |
+---------------+-----------------+---------------------------+
| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm |
+---------------+-----------------+---------------------------+
Dual Core samples
*****************
+-----------+------------------+----------------------------+
| Core | Boot Address | Comment |
+===========+==================+============================+
| Cortex M7 | 0x30000000[630K] | primary core |
+-----------+------------------+----------------------------+
| Cortex M4 | 0x20020000[96k] | boots from OCRAM |
+-----------+------------------+----------------------------+
+----------+------------------+-----------------------+
| Memory | Address[Size] | Comment |
+==========+==================+=======================+
| flexspi1 | 0x30000000[16M] | Cortex M7 flash |
+----------+------------------+-----------------------+
| sdram0 | 0x80030000[64M] | Cortex M7 ram |
+----------+------------------+-----------------------+
| ocram | 0x20020000[512K] | Cortex M4 "flash" |
+----------+------------------+-----------------------+
| sram1 | 0x20000000[128K] | Cortex M4 ram |
+----------+------------------+-----------------------+
| ocram2 | 0x200C0000[512K] | Mailbox/shared memory |
+----------+------------------+-----------------------+
Only the first 16K of ocram2 has the correct MPU region attributes set to be
used as shared memory
System Clock
============
The MIMXRT1160 SoC is configured to use SysTick as the system clock source,
running at 600MHz. When targeting the M4 core, SysTick will also be used,
running at 240MHz
When power management is enabled, the 32 KHz low frequency
oscillator on the board will be used as a source for the GPT timer to
generate a system clock. This clock enables lower power states, at the
cost of reduced resolution
Serial Port
===========
The MIMXRT1160 SoC has 12 UARTs. One is configured for the console and the
remaining are not used.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Building a Dual-Core Image
==========================
Dual core samples load the M4 core image from flash into the shared ``ocram``
region. The M7 core then sets the M4 boot address to this region. The only
sample currently enabled for dual core builds is the ``openamp`` sample.
To flash a dual core sample, the M4 image must be flashed first, so that it is
written to flash. Then, the M7 image must be flashed. The openamp sysbuild
sample will do this automatically by setting the image order.
The secondary core can be debugged normally in single core builds
(where the target is ``mimxrt1160_evk/mimxrt1166/cm4``). For dual core builds, the
secondary core should be placed into a loop, then a debugger can be attached
(see `AN13264`_, section 4.2.3 for more information)
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`,
however the :ref:`pyocd-debug-host-tools` do not yet support programming the
external flashes on this board so you must reconfigure the board for one of the
following debug probes instead.
Using J-Link
------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
There are two options: the onboard debug circuit can be updated with Segger
J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the
EVK. See `Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details.
Using LinkServer
----------------
Install the :ref:`linkserver-debug-host-tools` and make sure they are in your
search path. LinkServer works with the CMSIS-DAP firmware include in LinkServer
install. Please follow the ``LPCScrypt\docs\Debug_Probe_Firmware_Programming.pdf``
for more details.
Linkserver is the default runner. You may also se the ``-r linkserver`` option
with West to use the LinkServer runner.
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console. Check that
jumpers J5 and J8 are **on** (they are on by default when boards ship from
the factory) to connect UART signals to the OpenSDA microcontroller.
Connect a USB cable from your PC to J11.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
Before power on the board, make sure SW1 is set to 0001b
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1160_evk/mimxrt1166/cm7
:goals: flash
Power off the board, and change SW1 to 0010b. Then power on the board and
open a serial terminal, reset the board (press the SW4 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v2.6.0-xxxx-xxxxxxxxxxxxx *****
Hello World! mimxrt1160_evk
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1160_evk/mimxrt1166/cm7
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v2.4.0-xxxx-xxxxxxxxxxxxx *****
Hello World! mimxrt1160_evk
.. _MIMXRT1160-EVK Website:
path_to_url
.. _MIMXRT1160-EVK Board Hardware User's Guide:
path_to_url
.. _i.MX RT1160 Website:
path_to_url
.. _i.MX RT1160 Datasheet:
path_to_url
.. _i.MX RT1160 Reference Manual:
path_to_url
.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK:
path_to_url
.. _AN13264:
path_to_url
``` | /content/code_sandbox/boards/nxp/mimxrt1160_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,293 |
```unknown
/*
*
*/
#include <nxp/nxp_imx/mimx8mm6dvtlz-pinctrl.dtsi>
&pinctrl {
uart2_default: uart2_default {
group0 {
pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx>,
<&iomuxc_uart2_txd_uart_tx_uart2_tx>;
slew-rate = "fast";
drive-strength = "x6";
};
};
uart4_default: uart4_default {
group0 {
pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
slew-rate = "fast";
drive-strength = "x6";
};
};
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0>,
<&iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1>,
<&iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2>,
<&iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3>,
<&iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc>,
<&iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
slew-rate = "fast";
drive-strength = "x6";
};
group1 {
pinmux = <&iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
<&iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
<&iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
<&iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
<&iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
<&iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>;
slew-rate = "fast";
drive-strength = "x1";
};
group2 {
pinmux = <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>;
slew-rate = "fast";
drive-strength = "x1";
};
};
pinmux_mdio: pinmux_mdio {
group0 {
pinmux = <&iomuxc_enet_mdc_enet_mdc_enet1_mdc>,
<&iomuxc_enet_mdio_enet_mdio_enet1_mdio>;
slew-rate = "slow";
drive-strength = "x6";
};
};
};
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 681 |
```cmake
#
#
#
board_runner_args(pyocd "--target=mimxrt1064")
board_runner_args(jlink "--device=MIMXRT1064")
board_runner_args(linkserver "--device=MIMXRT1064xxxxA:EVK-MIMXRT1064")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
``` | /content/code_sandbox/boards/nxp/mimxrt1064_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 108 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
config BOARD_MIMXRT1064_EVK
select SOC_PART_NUMBER_MIMXRT1064DVL6A
``` | /content/code_sandbox/boards/nxp/mimxrt1064_evk/Kconfig.mimxrt1064_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```restructuredtext
.. _imx8mm_evk:
NXP i.MX8MM EVK
###############
Overview
********
i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications
processor, composed of a quad Cortex-A53 cluster and a single Cortex-M4 core.
Zephyr OS is ported to run on the Cortex-A53 core.
- Board features:
- RAM: 2GB LPDDR4
- Storage:
- SanDisk 16GB eMMC5.1
- Micron 32MB QSPI NOR
- microSD Socket
- Wireless:
- WiFi: 2.4/5GHz IEEE 802.11b/g/n
- Bluetooth: v4.1
- USB:
- OTG - 2x type C
- Ethernet
- PCI-E M.2
- Connectors:
- 40-Pin Dual Row Header
- LEDs:
- 1x Power status LED
- 1x UART LED
- Debug
- JTAG 20-pin connector
- MicroUSB for UART debug, two COM ports for A53 and M4
More information about the board can be found at the
`NXP website`_.
Supported Features
==================
The Zephyr imx8mm_evk board for Cortex-A53 configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| GIC-v3 | on-chip | interrupt controller |
+-----------+------------+-------------------------------------+
| ARM TIMER | on-chip | system clock |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| RDC | on-chip | Resource Domain Controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPT | on-chip | timer |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet port |
+-----------+------------+-------------------------------------+
The Zephyr imx8mm_evk board for Cortex-M4 supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | GPIO output |
| | | GPIO input |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig`
It is recommended to disable peripherals used by the M4 core on the Linux host.
Other hardware features are not currently supported by the port.
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 8 MHz.
The M4 Core is configured to run at a 400 MHz clock speed.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART4. This is used for the M4 and A53 core targets.
Programming and Debugging (A53)
*******************************
Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
plug the SD card into the board. Power it up and stop the u-boot execution at
prompt.
Use U-Boot to load and kick zephyr.bin:
.. code-block:: console
fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000
Or kick SMP zephyr.bin:
.. code-block:: console
fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000
Use this configuration to run basic Zephyr applications and kernel tests,
for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: imx8mm_evk/mimx8mm6/a53
:goals: run
This will build an image with the synchronization sample app, boot it and
display the following ram console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 ***
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
Use Jailhouse hypervisor, after root cell linux is up:
.. code-block:: console
#jailhouse enable imx8mm.cell
#jailhouse cell create imx8mm-zephyr.cell
#jailhouse cell load 1 zephyr.bin -a 0x93c00000
#jailhouse cell start 1
Programming and Debugging (M4)
******************************
The MIMX8MM EVK board doesn't have QSPI flash for the M4 and it needs
to be started by the A53 core. The A53 core is responsible to load the M4 binary
application into the RAM, put the M4 in reset, set the M4 Program Counter and
Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at
bootloader level or after the Linux system has booted.
The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4:
+------------+-------------------------+------------------------+-----------------------+----------------------+
| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size |
+============+=========================+========================+=======================+======================+
| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
For more information about memory mapping see the
`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3)
At compilation time you have to choose which RAM will be used. This
configuration is done in the file
:zephyr_file:`boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts`
with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties.
The available configurations are:
.. code-block:: none
"zephyr,flash"
- &tcml_code
- &ocram_code
- &ocram_s_code
"zephyr,sram"
- &tcmu_sys
- &ocram_sys
- &ocram_s_sys
Load and run Zephyr on M4 from A53 using u-boot by copying the compiled
``zephyr.bin`` to the first FAT partition of the SD card and plug the SD
card into the board. Power it up and stop the u-boot execution at prompt.
Load the M4 binary onto the desired memory and start its execution using:
.. code-block:: console
fatload mmc 0:1 0x7e0000 zephyr.bin;bootaux 0x7e0000
Debugging
=========
MIMX8MM EVK board can be debugged by connecting an external JLink
JTAG debugger to the J902 debug connector and to the PC. Then
the application can be debugged using the usual way.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: imx8mm_evk/mimx8mm6/m4
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 *****
Hello World! imx8mm_evk
References
==========
.. _NXP website:
path_to_url
.. _i.MX 8M Applications Processor Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/nxp/imx8mm_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,303 |
```unknown
/*
*
* Note: File generated by gen_board_pinctrl.py
* from mimxrt1064_evk.mex
*/
#include <nxp/nxp_imx/rt/mimxrt1064dvl6a-pinctrl.dtsi>
&pinctrl {
/* ADC1 inputs 0 and 15 */
pinmux_adc1: pinmux_adc1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_11_adc1_in0>,
<&iomuxc_gpio_ad_b1_10_adc1_in15>;
bias-disable;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with lpuart3 and flexcan1 */
pinmux_csi: pinmux_csi {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_02_gpio1_io18>;
drive-strength = "r0-6";
bias-pull-down;
bias-pull-down-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_04_csi_pixclk>,
<&iomuxc_gpio_ad_b1_05_csi_mclk>,
<&iomuxc_gpio_ad_b1_06_csi_vsync>,
<&iomuxc_gpio_ad_b1_07_csi_hsync>,
<&iomuxc_gpio_ad_b1_08_csi_data09>,
<&iomuxc_gpio_ad_b1_09_csi_data08>,
<&iomuxc_gpio_ad_b1_10_csi_data07>,
<&iomuxc_gpio_ad_b1_11_csi_data06>,
<&iomuxc_gpio_ad_b1_12_csi_data05>,
<&iomuxc_gpio_ad_b1_13_csi_data04>,
<&iomuxc_gpio_ad_b1_14_csi_data03>,
<&iomuxc_gpio_ad_b1_15_csi_data02>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc_gpio_b1_10_enet_ref_clk>;
bias-disable;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "50-mhz";
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_b1_04_enet_rx_data0>,
<&iomuxc_gpio_b1_05_enet_rx_data1>,
<&iomuxc_gpio_b1_06_enet_rx_en>,
<&iomuxc_gpio_b1_07_enet_tx_data0>,
<&iomuxc_gpio_b1_08_enet_tx_data1>,
<&iomuxc_gpio_b1_09_enet_tx_en>,
<&iomuxc_gpio_b1_11_enet_rx_er>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_enet_mdio: pinmux_enet_mdio {
group0 {
pinmux = <&iomuxc_gpio_emc_40_enet_mdc>,
<&iomuxc_gpio_emc_41_enet_mdio>,
<&iomuxc_gpio_ad_b0_10_gpio1_io10>,
<&iomuxc_gpio_ad_b0_09_gpio1_io09>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_ptp: pinmux_ptp {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_02_enet_1588_event2_out>,
<&iomuxc_gpio_ad_b1_03_enet_1588_event2_in>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with SAI1 */
pinmux_flexcan1: pinmux_flexcan1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_08_flexcan1_tx>,
<&iomuxc_gpio_ad_b1_09_flexcan1_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_flexcan2: pinmux_flexcan2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_14_flexcan2_tx>,
<&iomuxc_gpio_ad_b0_15_flexcan2_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_flexcan3: pinmux_flexcan3 {
group0 {
pinmux = <&iomuxc_gpio_emc_36_flexcan3_tx>,
<&iomuxc_gpio_emc_37_flexcan3_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* flexpwm output for board LED */
pinmux_flexpwm2: pinmux_flexpwm2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_09_flexpwm2_pwma3>;
drive-strength = "r0-4";
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* FLEXSPI1 is connected to external flash */
pinmux_flexspi1: pinmux_flexspi1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_05_flexspi_a_dqs>,
<&iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b>,
<&iomuxc_gpio_sd_b1_07_flexspi_a_sclk>,
<&iomuxc_gpio_sd_b1_08_flexspi_a_data0>,
<&iomuxc_gpio_sd_b1_09_flexspi_a_data1>,
<&iomuxc_gpio_sd_b1_10_flexspi_a_data2>,
<&iomuxc_gpio_sd_b1_11_flexspi_a_data3>;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "200-mhz";
input-enable;
};
};
/* Configures pin routing and optionally pin electrical features. */
pinmux_lcdif: pinmux_lcdif {
group0 {
pinmux = <&iomuxc_gpio_b0_00_lcdif_clk>,
<&iomuxc_gpio_b0_01_lcdif_enable>,
<&iomuxc_gpio_b0_02_lcdif_hsync>,
<&iomuxc_gpio_b0_03_lcdif_vsync>,
<&iomuxc_gpio_b0_04_lcdif_data00>,
<&iomuxc_gpio_b0_05_lcdif_data01>,
<&iomuxc_gpio_b0_06_lcdif_data02>,
<&iomuxc_gpio_b0_07_lcdif_data03>,
<&iomuxc_gpio_b0_08_lcdif_data04>,
<&iomuxc_gpio_b0_09_lcdif_data05>,
<&iomuxc_gpio_b0_10_lcdif_data06>,
<&iomuxc_gpio_b0_11_lcdif_data07>,
<&iomuxc_gpio_b0_12_lcdif_data08>,
<&iomuxc_gpio_b0_13_lcdif_data09>,
<&iomuxc_gpio_b0_14_lcdif_data10>,
<&iomuxc_gpio_b0_15_lcdif_data11>,
<&iomuxc_gpio_b1_00_lcdif_data12>,
<&iomuxc_gpio_b1_01_lcdif_data13>,
<&iomuxc_gpio_b1_02_lcdif_data14>,
<&iomuxc_gpio_b1_03_lcdif_data15>;
drive-strength = "r0-6";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_02_gpio1_io02>,
<&iomuxc_gpio_b1_15_gpio2_io31>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpi2c1: pinmux_lpi2c1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_01_lpi2c1_sda>,
<&iomuxc_gpio_ad_b1_00_lpi2c1_scl>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* Conflicts with USDHC pins. Connect R278, R279, R280, and R281 on evk board */
pinmux_lpspi1: pinmux_lpspi1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_lpspi1_pcs0>,
<&iomuxc_gpio_sd_b0_00_lpspi1_sck>,
<&iomuxc_gpio_sd_b0_03_lpspi1_sdi>,
<&iomuxc_gpio_sd_b0_02_lpspi1_sdo>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with lcdif pins */
pinmux_lpspi3: pinmux_lpspi3 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_03_lpspi3_pcs0>,
<&iomuxc_gpio_ad_b0_00_lpspi3_sck>,
<&iomuxc_gpio_ad_b0_02_lpspi3_sdi>,
<&iomuxc_gpio_ad_b0_01_lpspi3_sdo>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1: pinmux_lpuart1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_lpuart1_rx>,
<&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_gpio1_io13>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart3: pinmux_lpuart3 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_06_lpuart3_tx>,
<&iomuxc_gpio_ad_b1_07_lpuart3_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* Flow control for lpuart3 */
pinmux_lpuart3_flow_control: pinmux_lpuart3_flow_control {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_06_lpuart3_tx>,
<&iomuxc_gpio_ad_b1_07_lpuart3_rx>,
<&iomuxc_gpio_ad_b1_04_lpuart3_cts_b>,
<&iomuxc_gpio_ad_b1_05_lpuart3_rts_b>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_06_gpio1_io22>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_07_lpuart3_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_sai1: pinmux_sai1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_09_sai1_mclk>,
<&iomuxc_gpio_ad_b1_13_sai1_tx_data0>,
<&iomuxc_gpio_ad_b1_12_sai1_rx_data0>,
<&iomuxc_gpio_ad_b1_14_sai1_tx_bclk>,
<&iomuxc_gpio_ad_b1_15_sai1_tx_sync>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* note swo is configured with a cpu frequency of 132mhz and swo frequency of 7500khz */
pinmux_swo: pinmux_swo {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_10_arm_trace_swo>;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
pinmux_usdhc1: pinmux_usdhc1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_b1_12_gpio2_io28>,
<&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_b1_14_usdhc1_vselect>;
drive-strength = "r0-4";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group3 {
pinmux = <&iomuxc_gpio_ad_b0_05_gpio1_io05>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* fast pinmux settings for USDHC (over 100 Mhz) */
pinmux_usdhc1_fast: pinmux_usdhc1_fast {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
/* medium pinmux settings for USDHC (under 100 Mhz) */
pinmux_usdhc1_med: pinmux_usdhc1_med {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
/* slow pinmux settings for USDHC (under 50 Mhz) */
pinmux_usdhc1_slow: pinmux_usdhc1_slow {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "50-mhz";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,645 |
```yaml
board:
name: mimxrt1064_evk
vendor: nxp
socs:
- name: mimxrt1064
``` | /content/code_sandbox/boards/nxp/mimxrt1064_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
# MIMXRT1064-EVK board
if BOARD_MIMXRT1064_EVK
config DEVICE_CONFIGURATION_DATA
default y
config NXP_IMX_EXTERNAL_SDRAM
default y
if NETWORKING
config NET_L2_ETHERNET
default y
if ETH_MCUX
config ETH_MCUX_PHY_RESET
default y
endif # ETH_MCUX
endif # NETWORKING
endif # BOARD_MIMXRT1064_EVK
``` | /content/code_sandbox/boards/nxp/mimxrt1064_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```yaml
#
#
#
identifier: mimxrt1064_evk
name: NXP MIMXRT1064-EVK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32768
flash: 4096
supported:
- arduino_gpio
- arduino_serial
- counter
- display
- dma
- gpio
- hwinfo
- i2c
- netif:eth
- pwm
- sdhc
- spi
- usb_device
- video
- can
- watchdog
- adc
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 156 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt1064.dtsi>
#include "mimxrt1064_evk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP MIMXRT1064-EVK board";
compatible = "nxp,mimxrt1064";
aliases {
led0 = &green_led;
pwm-led0 = &green_pwm_led;
sw0 = &user_button;
watchdog0 = &wdog0;
sdhc0 = &usdhc1;
};
chosen {
zephyr,flash-controller = &is25wp064;
zephyr,flash = &w25q32jvwj0;
zephyr,code-partition = &slot0_partition;
zephyr,sram = &sdram0;
zephyr,itcm = &itcm;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,canbus = &flexcan2;
};
sdram0: memory@80000000 {
/* Micron MT48LC16M16A2B4-6AIT:G */
device_type = "memory";
reg = <0x80000000 DT_SIZE_M(32)>;
};
/*
* This node describes the GPIO pins of the parallel FPC interface,
* This interface is standard to several NXP EVKs, and is used with
* several parallel LCD displays (available as zephyr shields)
*/
nxp_parallel_lcd_connector: parallel-connector {
compatible = "nxp,parallel-lcd-connector";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */
};
/*
* This node describes the GPIO pins of the I2C display FPC interface,
* This interface is standard to several NXP EVKs, and is used with
* several parallel LCD displays (available as zephyr shields)
*/
nxp_i2c_touch_fpc: i2c-touch-connector {
compatible = "nxp,i2c-tsc-fpc";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <1 0 &gpio1 2 0>, /* Pin 2, LCD touch RST */
<2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */
};
leds {
compatible = "gpio-leds";
green_led: led-1 {
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
};
pwmleds {
compatible = "pwm-leds";
green_pwm_led: green_pwm_led {
pwms = <&flexpwm2_pwm3 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button-1 {
label = "User SW8";
gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
};
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <&ft5336>;
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio1 26 0>, /* A0 */
<1 0 &gpio1 27 0>, /* A1 */
<2 0 &gpio1 20 0>, /* A2 */
<3 0 &gpio1 21 0>, /* A3 */
<4 0 &gpio1 17 0>, /* A4 */
<5 0 &gpio1 16 0>, /* A5 */
<6 0 &gpio1 23 0>, /* D0 */
<7 0 &gpio1 22 0>, /* D1 */
<8 0 &gpio1 11 0>, /* D2 */
<9 0 &gpio1 24 0>, /* D3 */
<10 0 &gpio1 9 0>, /* D4 */
<11 0 &gpio1 10 0>, /* D5 */
<12 0 &gpio1 18 0>, /* D6 */
<13 0 &gpio1 19 0>, /* D7 */
<14 0 &gpio1 3 0>, /* D8 */
<15 0 &gpio1 2 0>, /* D9 */
<16 0 &gpio3 13 0>, /* D10 */
<17 0 &gpio3 14 0>, /* D11 */
<18 0 &gpio3 15 0>, /* D12 */
<19 0 &gpio3 12 0>, /* D13 */
<20 0 &gpio1 17 0>, /* D14 */
<21 0 &gpio1 16 0>; /* D15 */
};
};
nxp_touch_i2c: &lpi2c1 {};
zephyr_lcdif: &lcdif {
pinctrl-0 = <&pinmux_lcdif>;
pinctrl-names = "default";
};
nxp_parallel_i2c: &lpi2c1 {};
&lpi2c1 {
status = "okay";
pinctrl-0 = <&pinmux_lpi2c1>;
pinctrl-names = "default";
ft5336: ft5336@38 {
compatible = "focaltech,ft5336";
reg = <0x38>;
int-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
};
&flexspi {
status = "okay";
pinctrl-0 = <&pinmux_flexspi1>;
pinctrl-names = "default";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
is25wp064: is25wp064@0 {
compatible = "nxp,imx-flexspi-nor";
size = <67108864>;
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [9d 70 17];
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x00000000 DT_SIZE_M(8)>;
};
};
};
};
&w25q32jvwj0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 (DT_SIZE_K(1980) + DT_SIZE_K(8))>;
};
slot1_partition: partition@211000 {
label = "image-1";
reg = <0x00211000 DT_SIZE_K(1980)>;
};
/* The storage partition is located in is25wp064 */
};
};
&lpuart1 {
status = "okay";
pinctrl-0 = <&pinmux_lpuart1>;
pinctrl-1 = <&pinmux_lpuart1_sleep>;
pinctrl-names = "default", "sleep";
current-speed = <115200>;
};
arduino_serial: &lpuart3 {
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart3>;
pinctrl-1 = <&pinmux_lpuart3_sleep>;
pinctrl-names = "default", "sleep";
};
&enet_mac {
status = "okay";
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rmii";
};
&enet_mdio {
status = "okay";
pinctrl-0 = <&pinmux_enet_mdio>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "microchip,ksz8081";
reg = <0>;
status = "okay";
reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
microchip,interface-type = "rmii";
};
};
&enet_ptp_clock {
status = "okay";
pinctrl-0 = <&pinmux_ptp>;
pinctrl-names = "default";
};
zephyr_udc0: &usb1 {
status = "okay";
};
&csi {
pinctrl-0 = <&pinmux_csi>;
pinctrl-names = "default";
};
&flexpwm2_pwm3 {
status = "okay";
pinctrl-0 = <&pinmux_flexpwm2>;
pinctrl-names = "default";
};
&usdhc1 {
status = "okay";
pwr-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinmux_usdhc1>;
pinctrl-1 = <&pinmux_usdhc1_slow>;
pinctrl-2 = <&pinmux_usdhc1_med>;
pinctrl-3 = <&pinmux_usdhc1_fast>;
pinctrl-names = "default", "slow", "med", "fast";
sdmmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
&edma0 {
status = "okay";
};
&flexcan2 {
status = "okay";
pinctrl-0 = <&pinmux_flexcan2>;
pinctrl-names = "default";
can-transceiver {
max-bitrate = <5000000>;
};
};
&wdog0 {
status = "okay";
};
&lpspi1 {
status = "okay";
/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
dmas = <&edma0 0 13>, <&edma0 1 14>;
dma-names = "rx", "tx";
pinctrl-0 = <&pinmux_lpspi1>;
pinctrl-names = "default";
};
&lpspi3 {
status = "okay";
/* DMA channels 2 and 3, muxed to LPSPI3 RX and TX */
dmas = <&edma0 2 15>, <&edma0 3 16>;
dma-names = "rx", "tx";
pinctrl-0 = <&pinmux_lpspi3>;
pinctrl-names = "default";
};
&adc1 {
status = "okay";
pinctrl-0 = <&pinmux_adc1>;
pinctrl-names = "default";
};
/* GPT and Systick are enabled. If power management is enabled, the GPT
* timer will be used instead of systick, as allows the core clock to
* be gated.
*/
&gpt_hw_timer {
status = "okay";
};
&systick {
status = "okay";
};
&itm {
pinctrl-0 = <&pinmux_swo>;
pinctrl-names = "default";
};
&pxp {
status = "okay";
};
dvp_fpc24_i2c: &lpi2c1 {};
dvp_fpc24_interface: &csi {};
``` | /content/code_sandbox/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,839 |
```cmake
board_runner_args(jlink "--device=MK64FN1M0xxx12")
board_runner_args(linkserver "--device=MK64FN1M0xxx12:FRDM-K64F")
board_runner_args(pyocd "--target=k64f")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/canopen.board.cmake)
``` | /content/code_sandbox/boards/nxp/frdm_k64f/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 138 |
```unknown
config BOARD_FRDM_K64F
select SOC_MK64F12
select SOC_PART_NUMBER_MK64FN1M0VLL12
``` | /content/code_sandbox/boards/nxp/frdm_k64f/Kconfig.frdm_k64f | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/dts-v1/;
#include <nxp/nxp_k6x.dtsi>
#include "frdm_k64f-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP Freedom MK64F board";
compatible = "nxp,mk64f12", "nxp,k64f", "nxp,k6x";
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
sw0 = &user_button_3;
sw1 = &user_button_2;
magn0 = &fxos8700;
accel0 = &fxos8700;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-pipe = &uart0;
zephyr,canbus = &flexcan0;
zephyr,uart-mcumgr = &uart0;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpiob 22 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
green_led: led_1 {
gpios = <&gpioe 26 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
blue_led: led_2 {
gpios = <&gpiob 21 GPIO_ACTIVE_LOW>;
label = "User LD3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpioc 6 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpiob 2 0>, /* A0 */
<1 0 &gpiob 3 0>, /* A1 */
<2 0 &gpiob 10 0>, /* A2 */
<3 0 &gpiob 11 0>, /* A3 */
<4 0 &gpioc 11 0>, /* A4 */
<5 0 &gpioc 10 0>, /* A5 */
<6 0 &gpioc 16 0>, /* D0 */
<7 0 &gpioc 17 0>, /* D1 */
<8 0 &gpiob 9 0>, /* D2 */
<9 0 &gpioa 1 0>, /* D3 */
<10 0 &gpiob 23 0>, /* D4 */
<11 0 &gpioa 2 0>, /* D5 */
<12 0 &gpioc 2 0>, /* D6 */
<13 0 &gpioc 3 0>, /* D7 */
/* NOTE: HW Rev D and below use: */
/* <14 0 &gpioa 0 0>, */
/* NOTE: HW Rev E and on use: */
<14 0 &gpioc 12 0>, /* D8 */
<15 0 &gpioc 4 0>, /* D9 */
<16 0 &gpiod 0 0>, /* D10 */
<17 0 &gpiod 2 0>, /* D11 */
<18 0 &gpiod 3 0>, /* D12 */
<19 0 &gpiod 1 0>, /* D13 */
<20 0 &gpioe 25 0>, /* D14 */
<21 0 &gpioe 24 0>; /* D15 */
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
arduino_serial: &uart3 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart3_default>;
pinctrl-names = "default";
};
&cpu0 {
clock-frequency = <120000000>;
};
&adc0 {
status = "okay";
pinctrl-0 = <&adc0_default>;
pinctrl-names = "default";
};
&adc1 {
status = "okay";
pinctrl-0 = <&adc1_default>;
pinctrl-names = "default";
};
&temp1 {
status = "okay";
};
&dac0 {
status = "okay";
voltage-reference = <2>;
};
arduino_i2c: &i2c0 {
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
fxos8700: fxos8700@1d {
compatible = "nxp,fxos8700";
reg = <0x1d>;
int1-gpios = <&gpioc 6 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
};
};
arduino_spi: &spi0 {
status = "okay";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
};
&spi1 {
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
sdhc0: sdhc@0 {
compatible = "zephyr,sdhc-spi-slot";
reg = <0>;
status = "okay";
sdmmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
spi-max-frequency = <24000000>;
};
};
&ftm0 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
pinctrl-0 = <&ftm0_default>;
pinctrl-names = "default";
clock-source = "fixed";
};
&ftm3 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
pinctrl-0 = <&ftm3_default>;
pinctrl-names = "default";
clock-source = "fixed";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&uart2 {
pinctrl-0 = <&uart2_default>;
pinctrl-names = "default";
};
zephyr_udc0: &usbotg {
compatible = "nxp,kinetis-usbd";
status = "okay";
num-bidir-endpoints = <8>;
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(8))>;
};
slot1_partition: partition@7a000 {
label = "image-1";
reg = <0x0007a000 DT_SIZE_K(416)>;
};
storage_partition: partition@e2000 {
label = "storage";
reg = <0x000e2000 DT_SIZE_K(120)>;
};
};
};
&enet_mac {
status = "okay";
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rmii";
};
&enet_mdio {
status = "okay";
pinctrl-0 = <&pinmux_enet_mdio>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "microchip,ksz8081";
reg = <0>;
status = "okay";
microchip,interface-type = "rmii-25MHz";
};
};
&enet_ptp_clock {
status = "okay";
pinctrl-0 = <&pinmux_ptp>;
pinctrl-names = "default";
};
&flexcan0 {
status = "okay";
pinctrl-0 = <&flexcan0_default>;
pinctrl-names = "default";
};
&edma0 {
status = "okay";
};
&pit0 {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/frdm_k64f/frdm_k64f.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,197 |
```unknown
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
CONFIG_OSC_EXTERNAL=y
# Enable MPU
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
``` | /content/code_sandbox/boards/nxp/frdm_k64f/frdm_k64f_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```unknown
/*
* NOTE: Autogenerated file by gen_board_pinctrl.py
* for MK64FN1M0VLL12/signal_configuration.xml
*
*/
#include <nxp/kinetis/MK64FN1M0VLL12-pinctrl.h>
&pinctrl {
adc0_default: adc0_default {
group0 {
pinmux = <ADC0_SE14_PTC0>;
drive-strength = "low";
slew-rate = "fast";
};
};
adc1_default: adc1_default {
group0 {
pinmux = <ADC1_SE14_PTB10>;
drive-strength = "low";
slew-rate = "fast";
};
};
pinmux_enet: pinmux_enet {
group1 {
pinmux = <RMII0_RXER_PTA5>,
<RMII0_RXD1_PTA12>,
<RMII0_RXD0_PTA13>,
<RMII0_CRS_DV_PTA14>,
<RMII0_TXEN_PTA15>,
<RMII0_TXD0_PTA16>,
<RMII0_TXD1_PTA17>;
drive-strength = "low";
slew-rate = "fast";
};
};
pinmux_enet_mdio: pinmux_enet_mdio {
group0 {
pinmux = <RMII0_MDIO_PTB0>;
drive-strength = "low";
drive-open-drain;
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <RMII0_MDC_PTB1>;
drive-strength = "low";
slew-rate = "fast";
};
};
pinmux_ptp: pinmux_ptp {
group0 {
pinmux = <ENET0_1588_TMR0_PTC16>,
<ENET0_1588_TMR1_PTC17>,
<ENET0_1588_TMR2_PTC18>;
drive-strength = "low";
slew-rate = "fast";
};
};
flexcan0_default: flexcan0_default {
group0 {
pinmux = <CAN0_RX_PTB19>;
drive-strength = "low";
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <CAN0_TX_PTB18>;
drive-strength = "low";
slew-rate = "fast";
};
};
ftm0_default: ftm0_default {
group0 {
pinmux = <FTM0_CH0_PTC1>;
drive-strength = "low";
slew-rate = "fast";
};
};
ftm3_default: ftm3_default {
group0 {
pinmux = <FTM3_CH4_PTC8>,
<FTM3_CH5_PTC9>;
drive-strength = "low";
slew-rate = "fast";
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PTE24>,
<I2C0_SDA_PTE25>;
drive-strength = "low";
drive-open-drain;
slew-rate = "fast";
};
};
/* PTC16 and PTC17 conflict with uart3 pins */
ptp_default: ptp_default {
group0 {
pinmux = <ENET0_1588_TMR0_PTC16>,
<ENET0_1588_TMR1_PTC17>,
<ENET0_1588_TMR2_PTC18>;
drive-strength = "low";
slew-rate = "fast";
};
};
/* pins conflict with uart2 */
spi0_default: spi0_default {
group0 {
pinmux = <SPI0_PCS0_PTD0>,
<SPI0_SCK_PTD1>,
<SPI0_SOUT_PTD2>,
<SPI0_SIN_PTD3>;
drive-strength = "low";
slew-rate = "fast";
};
};
spi1_default: spi1_default {
group0 {
pinmux = <SPI1_PCS0_PTE4>,
<SPI1_SCK_PTE2>,
<SPI1_SOUT_PTE3>,
<SPI1_SIN_PTE1>;
drive-strength = "low";
slew-rate = "fast";
};
};
uart0_default: uart0_default {
group0 {
pinmux = <UART0_RX_PTB16>,
<UART0_TX_PTB17>;
drive-strength = "low";
slew-rate = "fast";
};
};
/* pins conflict with spi0 */
uart2_default: uart2_default {
group0 {
pinmux = <UART2_CTS_b_PTD1>,
<UART2_RTS_b_PTD0>,
<UART2_RX_PTD2>,
<UART2_TX_PTD3>;
drive-strength = "low";
slew-rate = "fast";
};
};
/* PTC16 and PTC17 conflict with PTP timer pins */
uart3_default: uart3_default {
group0 {
pinmux = <UART3_RX_PTC16>,
<UART3_TX_PTC17>;
drive-strength = "low";
slew-rate = "fast";
};
};
};
``` | /content/code_sandbox/boards/nxp/frdm_k64f/frdm_k64f-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,261 |
```restructuredtext
.. _mimxrt1064_evk:
NXP MIMXRT1064-EVK
##################
Overview
********
The i.MX RT1064 adds to the industry's first crossover
processor series and expands the i.MX RT series to three scalable families.
The i.MX RT1064 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin
compatibility with i.MX RT1050. This series introduces additional features
ideal for real-time applications such as High-Speed GPIO, CAN FD, and
synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1064 runs on the
Arm Cortex-M7 core up to 600 MHz.
.. image:: mimxrt1064_evk.jpg
:align: center
:alt: MIMXRT1064-EVK
Hardware
********
- MIMXRT1064DVL6A MCU (600 MHz, 1024 KB on-chip memory, 4096KB on-chip QSPI
flash)
- Memory
- 256 Mbit SDRAM
- 64 Mbit QSPI Flash
- 512 Mbit Hyper Flash
- TF socket for SD card
- Display
- LCD connector
- Ethernet
- 10/100 Mbit/s Ethernet PHY
- USB
- USB 2.0 OTG connector
- USB 2.0 host connector
- Audio
- 3.5 mm audio stereo headphone jack
- Board-mounted microphone
- Left and right speaker out connectors
- Power
- 5 V DC jack
- Debug
- JTAG 20-pin connector
- OpenSDA with DAPLink
- Sensor
- FXOS8700CQ 6-axis e-compass
- CMOS camera sensor interface
- Expansion port
- Arduino interface
- CAN bus connector
For more information about the MIMXRT1064 SoC and MIMXRT1064-EVK board, see
these references:
- `i.MX RT1064 Website`_
- `i.MX RT1064 Datasheet`_
- `i.MX RT1064 Reference Manual`_
- `MIMXRT1064-EVK Website`_
- `MIMXRT1064-EVK Quick Reference Guide`_
- `MIMXRT1064-EVK User Guide`_
- `MIMXRT1064-EVK Schematics`_
- `MIMXRT1064-EVK Debug Firmware`_
External Memory
===============
This platform has the following external memories:
+--------------------+------------+-------------------------------------+
| Device | Controller | Status |
+====================+============+=====================================+
| MT48LC16M16A2 | SEMC | Enabled via device configuration |
| | | data block, which sets up SEMC at |
| | | boot time |
+--------------------+------------+-------------------------------------+
Supported Features
==================
NXP considers the MIMXRT1064-EVK as the superset board for the i.MX RT10xx
family of MCUs. This board is a focus for NXP's Full Platform Support for
Zephyr, to better enable the entire RT10xx family. NXP prioritizes enabling
this board with new support for Zephyr features. The mimxrt1064_evk board
configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| DISPLAY | on-chip | eLCDIF. Tested with |
| | | :ref:`rk043fn02h_ct`, and |
| | | :ref:`rk043fn66hs_ctg` shields |
+-----------+------------+-------------------------------------+
| VIDEO | on-chip | video, using CSI |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | QSPI flash |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| SDHC | on-chip | disk access |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| CAN | on-chip | can |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| HWINFO | on-chip | Unique device serial number |
+-----------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
| FLEXSPI | on-chip | flash programming |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig`
Other hardware features are not currently supported by the port.
Connections and I/Os
====================
The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| Name | Function | Usage |
+===============+=================+===========================+
| GPIO_AD_B0_00 | LPSPI1_SCK | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_01 | LPSPI1_SDO | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_05 | GPIO | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_09 | GPIO/ENET_RST | LED/Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_11 | GPIO | Touch Interrupt |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_12 | LPUART1_TX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_06 | LPUART3_TX | UART Arduino |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_07 | LPUART3_RX | UART Arduino |
+---------------+-----------------+---------------------------+
| WAKEUP | GPIO | SW0 |
+---------------+-----------------+---------------------------+
| GPIO_B0_00 | LCD_CLK | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_01 | LCD_ENABLE | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_02 | LCD_HSYNC | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_03 | LCD_VSYNC | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_04 | LCD_DATA00 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_05 | LCD_DATA01 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_06 | LCD_DATA02 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_07 | LCD_DATA03 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_08 | LCD_DATA04 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_09 | LCD_DATA05 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_10 | LCD_DATA06 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_11 | LCD_DATA07 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_12 | LCD_DATA08 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_13 | LCD_DATA09 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_14 | LCD_DATA10 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_15 | LCD_DATA11 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_00 | LCD_DATA12 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_01 | LCD_DATA13 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_02 | LCD_DATA14 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_03 | LCD_DATA15 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_06 | ENET_RX_EN | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_09 | ENET_TX_EN | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_10 | ENET_REF_CLK | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_11 | ENET_RX_ER | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_12 | GPIO | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_B1_14 | USDHC1_VSELECT | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_EMC_40 | ENET_MDC | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_EMC_41 | ENET_MDIO | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_09 | ENET_RST | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_10 | ENET_INT | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_05 | FLEXSPIA_DQS | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_06 | FLEXSPIA_SS0_B | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_07 | FLEXSPIA_SCLK | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_08 | FLEXSPIA_DATA00 | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_09 | FLEXSPIA_DATA01 | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_10 | FLEXSPIA_DATA02 | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_11 | FLEXSPIA_DATA03 | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_10 | ADC | ADC1 Channel 1 |
+---------------+-----------------+---------------------------+
.. note::
In order to use the SPI peripheral on this board, resistors R278, R279,
R280 and R281 must be populated with zero ohm resistors
System Clock
============
The MIMXRT1064 SoC is configured to use SysTick as the system clock source,
running at 600MHz.
When power management is enabled, the 32 KHz low frequency
oscillator on the board will be used as a source for the GPT timer to
generate a system clock. This clock enables lower power states, at the
cost of reduced resolution
Serial Port
===========
The MIMXRT1064 SoC has eight UARTs. ``LPUART1`` is configured for the console
and the remaining are not used.
Programming and Debugging
*************************
This board supports 3 debug host tools. Please install your preferred host
tool, then follow the instructions in `Configuring a Debug Probe`_ to
configure the board appropriately.
* :ref:`jlink-debug-host-tools` (Default, Supported by NXP)
* :ref:`linkserver-debug-host-tools` (Supported by NXP)
* :ref:`pyocd-debug-host-tools` (Not supported by NXP)
Once the host tool and board are configured, build and flash applications
as usual (see :ref:`build_an_application` and :ref:`application_run` for more
details).
Configuring a Debug Probe
=========================
.. note::
When the device transitions into low power states, the debugger may be
unable to access the chip. Use caution when enabling ``CONFIG_PM``, and
if the debugger cannot flash the part, see :ref:`Troubleshooting RT1064`
For the RT1064, J47/J48 are the SWD isolation jumpers, J42 is the DFU
mode jumper, and J21 is the 20 pin JTAG/SWD header.
.. include:: ../../common/rt1xxx-lpclink2-debug.rst
:start-after: rt1xxx-lpclink2-probes
See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ for more
details.
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console. Check that
jumpers J45 and J46 are **on** (they are on by default when boards ship from
the factory) to connect UART signals to the OpenSDA microcontroller.
Connect a USB cable from your PC to J41.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Using SWO
---------
SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``.
Your SWO viewer should be configured with a CPU frequency of 132MHz, and
SWO frequency of 7500KHz.
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1064_evk
:goals: flash
Open a serial terminal, reset the board (press the SW9 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1064_evk
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1064_evk
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1064_evk
.. _Troubleshooting RT1064:
Troubleshooting
===============
If the debug probe fails to connect with the following error, it's possible
that the boot header in QSPI flash is invalid or corrupted. The boot header is
configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`.
.. code-block:: console
Remote debugging using :2331
Remote communication error. Target disconnected.: Connection reset by peer.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
(gdb) Could not connect to target.
Please check power, connection and settings.
You can fix it by erasing and reprogramming the QSPI flash with the following
steps:
#. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash.
#. Reset by pressing SW9
#. Run ``west debug`` or ``west flash`` again with a known working Zephyr
application.
#. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash.
#. Reset by pressing SW9
If the west flash or debug commands fail, and the command hangs while executing
runners.jlink, confirm the J-Link debug probe is configured, powered, and
connected to the EVK properly.
.. _MIMXRT1064-EVK Website:
path_to_url
.. _MIMXRT1064-EVK Quick Reference Guide:
path_to_url
.. _MIMXRT1064-EVK User Guide:
path_to_url
.. _MIMXRT1064-EVK Debug Firmware:
path_to_url
.. _MIMXRT1064-EVK Schematics:
path_to_url
.. _i.MX RT1064 Website:
path_to_url
.. _i.MX RT1064 Datasheet:
path_to_url
.. _i.MX RT1064 Reference Manual:
path_to_url
.. _Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK:
path_to_url
``` | /content/code_sandbox/boards/nxp/mimxrt1064_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,460 |
```yaml
identifier: frdm_k64f
name: NXP FRDM-K64F
type: mcu
arch: arm
ram: 192
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- arduino_gpio
- arduino_i2c
- arduino_serial
- arduino_spi
- can
- counter
- dac
- dma
- gpio
- i2c
- netif:eth
- nvs
- pwm
- spi
- usb_device
- usbd
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/frdm_k64f/frdm_k64f.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```yaml
board:
name: frdm_k64f
vendor: nxp
socs:
- name: mk64f12
``` | /content/code_sandbox/boards/nxp/frdm_k64f/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```ini
source [find interface/cmsis-dap.cfg]
source [find target/k60.cfg]
``` | /content/code_sandbox/boards/nxp/frdm_k64f/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
# FRDM-K64F board
if BOARD_FRDM_K64F
config OSC_XTAL0_FREQ
default 50000000
config MCG_PRDIV0
default 0x13
config MCG_VDIV0
default 0x18
config MCG_FCRDIV
default 1
config TEST_EXTRA_STACK_SIZE
default 128
if NETWORKING
config NET_L2_ETHERNET
default y if !MODEM
endif # NETWORKING
endif # BOARD_FRDM_K64F
``` | /content/code_sandbox/boards/nxp/frdm_k64f/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```cmake
#
#
#
board_runner_args(linkserver "--device=LPC55S06:LPCXpresso55S06")
board_runner_args(jlink "--device=LPC55S06" "--reset-after-load")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
#
config BOARD_LPCXPRESSO55S06
select SOC_LPC55S06
select SOC_PART_NUMBER_LPC55S06JBD64
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/Kconfig.lpcxpresso55s06 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
* NOTE: File generated by gen_board_pinctrl.py
* from LPCXpresso55S06.mex
*
*/
#include <nxp/lpc/LPC55S06JBD64-pinctrl.h>
&pinctrl {
pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
group0 {
pinmux = <FC0_RXD_SDA_MOSI_DATA_PIO0_29>,
<FC0_TXD_SCL_MISO_WS_PIO0_30>;
slew-rate = "standard";
};
};
pinmux_can0: pinmux_can0 {
group0 {
pinmux = <CAN0_RD_PIO1_3>,
<CAN0_TD_PIO1_2>;
slew-rate = "standard";
};
};
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/lpcxpresso55s06-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 182 |
```unknown
choice MCUBOOT_MODE
default MCUBOOT_MODE_OVERWRITE_ONLY
endchoice
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```yaml
# LPCXpresso55S06 board
identifier: lpcxpresso55s06
name: NXP LPCXpresso55S06
type: mcu
arch: arm
ram: 96
flash: 256
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- can
vendor: nxp
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```yaml
board:
name: lpcxpresso55s06
vendor: nxp
socs:
- name: lpc55s06
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_lpc55S06_ns.dtsi>
#include "lpcxpresso55s06_common.dtsi"
/ {
model = "NXP LPCXpresso55S06 board";
compatible = "nxp,lpc55xxx", "nxp,lpc";
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
/*
*
*/
#include "lpcxpresso55s06-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,console = &flexcomm0;
zephyr,shell-uart = &flexcomm0;
zephyr,entropy = &rng;
zephyr,flash-controller = &iap;
zephyr,canbus = &can0;
};
aliases {
led0 = &blue_led;
led1 = &red_led;
led2 = &green_led;
sw0 = &btn_wk;
sw1 = &btn_usr;
sw2 = &btn_isp;
usart-0 = &flexcomm0;
};
leds {
compatible = "gpio-leds";
blue_led: led_0 {
gpios = <&gpio0 22 0>;
label = "Blue LED";
};
red_led: led_1 {
gpios = <&gpio0 21 0>;
label = "Red LED";
};
green_led: led_2 {
gpios = <&gpio0 18 0>;
label = "Green LED";
};
};
gpio_keys {
compatible = "gpio-keys";
btn_wk: button_0 {
label = "Wakeup button";
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_WAKEUP>;
};
btn_usr: button_1 {
label = "User button";
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
btn_isp: button_2 {
label = "ISP button";
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
mikrobus_header: mikrobus-connector {
compatible = "mikro-bus";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 16 0>, /* AN */
/* Not a GPIO */ /* RST */
<2 0 &gpio1 1 0>, /* CS */
<3 0 &gpio1 2 0>, /* SCK */
<4 0 &gpio1 3 0>, /* MISO */
<5 0 &gpio0 26 0>, /* MOSI */
/* +3.3V */
/* GND */
<6 0 &gpio1 5 0>, /* PWM */
<7 0 &gpio0 28 0>, /* INT */
<8 0 &gpio1 10 0>, /* RX */
<9 0 &gpio1 11 0>, /* TX */
<10 0 &gpio0 24 0>, /* SCL */
<11 0 &gpio0 25 0>; /* SDA */
/* +5V */
/* GND */
};
arduino_header: arduino-connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 16 0>, /* A0 */
<1 0 &gpio0 23 0>, /* A1 */
<2 0 &gpio0 9 0>, /* A2 */
<3 0 &gpio0 0 0>, /* A3 */
<4 0 &gpio0 13 0>, /* A4 */
<5 0 &gpio0 14 0>, /* A5 */
<6 0 &gpio1 10 0>, /* D0 */
<7 0 &gpio1 11 0>, /* D1 */
<8 0 &gpio0 15 0>, /* D2 */
<9 0 &gpio0 23 0>, /* D3 */
<10 0 &gpio0 22 0>, /* D4 */
<11 0 &gpio0 19 0>, /* D5 */
<12 0 &gpio0 18 0>, /* D6 */
<13 0 &gpio0 2 0>, /* D7 */
<14 0 &gpio0 10 0>, /* D8 */
<15 0 &gpio0 25 0>, /* D9 */
<16 0 &gpio1 1 0>, /* D10 */
<17 0 &gpio0 26 0>, /* D11 */
<18 0 &gpio1 3 0>, /* D12 */
<19 0 &gpio1 2 0>; /* D13 */
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 DT_SIZE_K(32)>;
};
slot0_partition: partition@8000 {
label = "image-0";
reg = <0x00008000 DT_SIZE_K(96)>;
};
slot1_partition: partition@20000 {
label = "image-1";
reg = <0x00020000 DT_SIZE_K(96)>;
};
storage_partition: partition@38000 {
label = "storage";
reg = <0x00038000 DT_SIZE_K(20)>;
};
/* The last 12KB are reserved for PFR on the 256KB flash. */
};
};
&flexcomm0 {
status = "okay";
compatible = "nxp,lpc-usart";
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm0_usart>;
pinctrl-names = "default";
};
&can0 {
status = "okay";
pinctrl-0 = <&pinmux_can0>;
pinctrl-names = "default";
can-transceiver {
max-bitrate = <5000000>;
};
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,541 |
```unknown
# LPCXpresso55S06 board
if BOARD_LPCXPRESSO55S06
if BOOTLOADER_MCUBOOT
choice MCUBOOT_BOOTLOADER_MODE
# Board only supports MCUBoot via "upgrade only" method:
default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY
endchoice
endif #BOOTLOADER_MCUBOOT
endif # BOARD_LPCXPRESSO55S06
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_ARM_MPU=y
CONFIG_RUNTIME_NMI=y
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```restructuredtext
.. _frdm_k64f:
NXP FRDM-K64F
##############
Overview
********
The Freedom-K64F is an ultra-low-cost development platform for Kinetis K64,
K63, and K24 MCUs.
- Form-factor compatible with the Arduino R3 pin layout
- Peripherals enable rapid prototyping, including a 6-axis digital
accelerometer and magnetometer to create full eCompass capabilities, a
tri-colored LED and 2 user push-buttons for direct interaction, a microSD
card slot, and connectivity using onboard Ethernet port and headers for use
with Bluetooth* and 2.4 GHz radio add-on modules
- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter
running an open source bootloader, offers options for serial communication,
flash programming, and run-control debugging
.. image:: frdm_k64f.jpg
:align: center
:alt: FRDM-K64F
Hardware
********
- MK64FN1M0VLL12 MCU (120 MHz, 1 MB flash memory, 256 KB RAM, low-power,
crystal-less USB, and 100 Low profile Quad Flat Package (LQFP))
- Dual role USB interface with micro-B USB connector
- RGB LED
- FXOS8700CQ accelerometer and magnetometer
- Two user push buttons
- Flexible power supply option - OpenSDAv2 USB, Kinetis K64 USB, and external source
- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors
- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface
software that provides:
- Mass storage device (MSD) flash programming interface
- CMSIS-DAP debug interface over a driver-less USB HID connection providing
run-control debugging and compatibility with IDE tools
- Virtual serial port interface
- Open source CMSIS-DAP software project
- Ethernet
- SDHC
For more information about the K64F SoC and FRDM-K64F board:
- `K64F Website`_
- `K64F Datasheet`_
- `K64F Reference Manual`_
- `FRDM-K64F Website`_
- `FRDM-K64F User Guide`_
- `FRDM-K64F Schematics`_
Supported Features
==================
NXP considers the FRDM-K64F as the superset board for the Kinetis K
series of MCUs. This board is a focus for NXP's Full Platform Support for
Zephyr, to better enable the entire Kinetis K series. NXP prioritizes enabling
this board with new support for Zephyr features. The frdm_k64f board
configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| DAC | on-chip | dac |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| ETHERNET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| SENSOR | off-chip | fxos8700 polling; |
| | | fxos8700 trigger |
+-----------+------------+-------------------------------------+
| CAN | on-chip | can |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| RNGA | on-chip | entropy; |
| | | random |
+-----------+------------+-------------------------------------+
| FTFE | on-chip | flash programming |
+-----------+------------+-------------------------------------+
| PIT | on-chip | pit |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/frdm_k64f/frdm_k64f_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The K64F SoC has five pairs of pinmux/gpio controllers.
+-------+-----------------+---------------------------+
| Name | Function | Usage |
+=======+=================+===========================+
| PTB22 | GPIO | Red LED |
+-------+-----------------+---------------------------+
| PTE26 | GPIO | Green LED |
+-------+-----------------+---------------------------+
| PTB21 | GPIO | Blue LED |
+-------+-----------------+---------------------------+
| PTC6 | GPIO | SW2 / FXOS8700 INT1 |
+-------+-----------------+---------------------------+
| PTC13 | GPIO | FXOS8700 INT2 |
+-------+-----------------+---------------------------+
| PTA4 | GPIO | SW3 |
+-------+-----------------+---------------------------+
| PTB10 | ADC | ADC1 channel 14 |
+-------+-----------------+---------------------------+
| PTB16 | UART0_RX | UART Console |
+-------+-----------------+---------------------------+
| PTB17 | UART0_TX | UART Console |
+-------+-----------------+---------------------------+
| PTB18 | CAN0_TX | CAN TX |
+-------+-----------------+---------------------------+
| PTB19 | CAN0_RX | CAN RX |
+-------+-----------------+---------------------------+
| PTC8 | PWM | PWM_3 channel 4 |
+-------+-----------------+---------------------------+
| PTC9 | PWM | PWM_3 channel 5 |
+-------+-----------------+---------------------------+
| PTC16 | UART3_RX | UART BT HCI |
+-------+-----------------+---------------------------+
| PTC17 | UART3_TX | UART BT HCI |
+-------+-----------------+---------------------------+
| PTD0 | SPI0_PCS0 | SPI |
+-------+-----------------+---------------------------+
| PTD1 | SPI0_SCK | SPI |
+-------+-----------------+---------------------------+
| PTD2 | SPI0_SOUT | SPI |
+-------+-----------------+---------------------------+
| PTD3 | SPI0_SIN | SPI |
+-------+-----------------+---------------------------+
| PTE24 | I2C0_SCL | I2C / FXOS8700 |
+-------+-----------------+---------------------------+
| PTE25 | I2C0_SDA | I2C / FXOS8700 |
+-------+-----------------+---------------------------+
| PTA5 | MII0_RXER | Ethernet |
+-------+-----------------+---------------------------+
| PTA12 | MII0_RXD1 | Ethernet |
+-------+-----------------+---------------------------+
| PTA13 | MII0_RXD0 | Ethernet |
+-------+-----------------+---------------------------+
| PTA14 | MII0_RXDV | Ethernet |
+-------+-----------------+---------------------------+
| PTA15 | MII0_TXEN | Ethernet |
+-------+-----------------+---------------------------+
| PTA16 | MII0_TXD0 | Ethernet |
+-------+-----------------+---------------------------+
| PTA17 | MII0_TXD1 | Ethernet |
+-------+-----------------+---------------------------+
| PTA28 | MII0_TXER | Ethernet |
+-------+-----------------+---------------------------+
| PTB0 | MII0_MDIO | Ethernet |
+-------+-----------------+---------------------------+
| PTB1 | MII0_MDC | Ethernet |
+-------+-----------------+---------------------------+
| PTC16 | ENET0_1588_TMR0 | Ethernet |
+-------+-----------------+---------------------------+
| PTC17 | ENET0_1588_TMR1 | Ethernet |
+-------+-----------------+---------------------------+
| PTC18 | ENET0_1588_TMR2 | Ethernet |
+-------+-----------------+---------------------------+
| PTC19 | ENET0_1588_TMR3 | Ethernet |
+-------+-----------------+---------------------------+
.. note::
Do not enable Ethernet and UART BT HCI simultaneously because they conflict
on PTC16-17.
System Clock
============
The K64F SoC is configured to use the 50 MHz external oscillator on the board
with the on-chip PLL to generate a 120 MHz system clock.
Serial Port
===========
The K64F SoC has six UARTs. One is configured for the console, another for BT
HCI, and the remaining are not used.
USB
===
The K64F SoC has a USB OTG (USBOTG) controller that supports both
device and host functions through its micro USB connector (K64F USB).
Only USB device function is supported in Zephyr at the moment.
CAN
===
The FRDM-K64F board does not come with an onboard CAN transceiver. In order to
use the CAN bus, an external CAN bus transceiver must be connected to ``PTB18``
(``CAN0_TX``) and ``PTB19`` (``CAN0_RX``).
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`.
Early versions of this board have an outdated version of the OpenSDA bootloader
and require an update. Please see the `DAPLink Bootloader Update`_ page for
instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader.
.. tabs::
.. group-tab:: OpenSDA DAPLink Onboard (Recommended)
Install the :ref:`linkserver-debug-host-tools` and make sure they are in your
search path. LinkServer works with the default CMSIS-DAP firmware included in
the on-board debugger.
Linkserver is the default for this board, ``west flash`` and ``west debug`` will
call the linkserver runner.
.. code-block:: console
west flash
Alternatively, pyOCD can be used to flash and debug the board by using the
``-r pyocd`` option with West. pyOCD is installed when you complete the
:ref:`gs_python_deps` step in the Getting Started Guide. The runners supported
by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP
does not test or support the pyOCD runner.
.. group-tab:: OpenSDA JLink Onboard
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
The version of J-Link firmware to program to the board depends on the version
of the DAPLink bootloader. Refer to `OpenSDA Serial and Debug Adapter`_ for
more details. On this page, change the pull-down menu for "Choose your board to
start" to FRDM-K64F, and review the section "To update your board with OpenSDA
applications". Note that Segger does provide an OpenSDA J-Link Board-Specific
Firmware for this board, however it is not compatible with the DAPLink
bootloader. After downloading the appropriate J-Link firmware, follow the
instructions in :ref:`opensda-jlink-onboard-debug-probe` to program to the
board.
Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and
``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the
default runner to J-Link:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_k64f
:gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink
:goals: build
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console.
Connect a USB cable from your PC to J26.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_k64f
:goals: flash
Open a serial terminal, reset the board (press the SW1 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! frdm_k64f
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_k64f
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! frdm_k64f
Troubleshooting
===============
If pyocd raises an uncaught ``DAPAccessIntf.TransferFaultError()`` exception
when you try to flash or debug, it's possible that the K64F flash may have been
locked by a corrupt application. You can unlock it with the following sequence
of pyocd commands:
.. code-block:: console
$ pyocd cmd
0001915:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device
Connected to K64F [Halted]: 0240000026334e450028400d5e0e000e4eb1000097969900
>>> unlock
0016178:WARNING:target_kinetis:K64F secure state: unlocked successfully
>>> reinit
0034584:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device
>>> load build/zephyr/zephyr.bin
[====================] 100%
>>> reset
Resetting target
>>> quit
.. _FRDM-K64F Website:
path_to_url
.. _FRDM-K64F User Guide:
path_to_url
.. _FRDM-K64F Schematics:
path_to_url
.. _K64F Website:
path_to_url
.. _K64F Datasheet:
path_to_url
.. _K64F Reference Manual:
path_to_url
.. _DAPLink Bootloader Update:
path_to_url
.. _OpenSDA DAPLink FRDM-K64F Firmware:
path_to_url
.. _OpenSDA Serial and Debug Adapter:
path_to_url#FRDM-K64F
``` | /content/code_sandbox/boards/nxp/frdm_k64f/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,619 |
```yaml
#
#
#
identifier: mimxrt1040_evk
name: NXP MIMXRT1040-EVK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32768
flash: 8192
supported:
- arduino_gpio
- gpio
- pwm
- adc
- spi
- i2c
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```cmake
#
#
#
board_runner_args(jlink "--device=MIMXRT1042XXX6B")
board_runner_args(linkserver "--device=MIMXRT1042xxxxB:MIMXRT1040-EVK")
board_runner_args(pyocd "--target=MIMXRT1042XJM5B")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/mimxrt1040_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```restructuredtext
.. _lpcxpresso55s06:
NXP LPCXpresso55S06
###################
Overview
********
The LPCXpresso55S06 board provides the ideal platform for evaluation
of the LPC55S0x/LPC550x MCU family, based on the Arm Cortex-M33
architecture. Arduino UNO compatible shield connectors are included,
with additional expansion ports around the Arduino footprint, along
with a PMod/host interface port and MikroElektronika Click module
site.
.. image:: lpcxpress55s06.jpg
:align: center
:alt: LPCXpresso55S06
Hardware
********
- LPC55S06 Arm Cortex-M33 microcontroller running at up to 96 MHz
- 256 KB flash and 96 KB SRAM on-chip
- LPC-Link2 debug high speed USB probe with VCOM port
- MikroElektronika Click expansion option
- LPCXpresso expansion connectors compatible with Arduino UNO
- PMod compatible expansion / host connector
- Reset, ISP, wake, and user buttons for easy testing of software functionality
- Tri-color LED
- UART header for external serial to USB cable
- CAN Transceiver
- NXP FXOS8700CQ accelerometer
For more information about the LPC55S06 SoC and LPCXPresso55S06 board, see:
- `LPC55S06 SoC Website`_
- `LPC55S06 User Manual`_
- `LPCXpresso55S06 Website`_
- `LPCXpresso55S06 User Manual`_
- `LPCXpresso55S06 Development Board Design Files`_
Supported Features
==================
The lpcxpresso55s06 board configuration supports the hardware features listed
below. For additional features not yet supported, please also refer to the
:ref:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series.
NXP prioritizes enabling the superset board with NXP's Full Platform Support for
Zephyr. Therefore, the lpcxpresso55s69 board may have additional features
already supported, which can also be re-used on this lpcxpresso55s06 board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| IOCON | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| USART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| RNG | on-chip | entropy; |
| | | random |
+-----------+------------+-------------------------------------+
| IAP | on-chip | flash programming |
+-----------+------------+-------------------------------------+
Other hardware features are not currently enabled.
Currently available targets for this board are:
- *lpcxpresso55s06*
Connections and IOs
===================
The LPC55S06 SoC has IOCON registers, which can be used to configure
the functionality of a pin.
+---------+-----------------+----------------------------+
| Name | Function | Usage |
+=========+=================+============================+
| PIO0_5 | GPIO | ISP SW4 |
+---------+-----------------+----------------------------+
| PIO0_29 | USART | USART RX |
+---------+-----------------+----------------------------+
| PIO0_30 | USART | USART TX |
+---------+-----------------+----------------------------+
| PIO1_4 | GPIO | RED LED |
+---------+-----------------+----------------------------+
| PIO1_6 | GPIO | BLUE_LED |
+---------+-----------------+----------------------------+
| PIO1_7 | GPIO | GREEN LED |
+---------+-----------------+----------------------------+
| PIO1_9 | GPIO | USR SW3 |
+---------+-----------------+----------------------------+
| PIO1_18 | GPIO | Wakeup SW1 |
+---------+-----------------+----------------------------+
System Clock
============
The LPC55S06 SoC is configured to use the internal FRO at 96MHz as a
source for the system clock. Other sources for the system clock are
provided in the SOC, depending on your system requirements.
Serial Port
===========
The LPC55S06 SoC has 8 FLEXCOMM interfaces for serial
communication. One is configured as USART for the console
and the remaining are not used.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application`
and :ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This
board is configured by default to use the LPC-Link2 CMSIS-DAP Onboard
Debug Probe, however the :ref:`pyocd-debug-host-tools` does not yet
support the LPC55S06 so you must reconfigure the board for one of the
J-Link debug probe instead.
First install the :ref:`jlink-debug-host-tools` and make sure they are
in your search path.
Then follow the instructions in
:ref:`lpclink2-jlink-onboard-debug-probe` to program the J-Link
firmware. Please make sure you have the latest firmware for this
board.
Configuring a Console
=====================
Connect a USB cable from your PC to J1 (LINK2), and use the serial
terminal of your choice (minicom, putty, etc.) with the following
settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: lpcxpresso55s06
:goals: flash
Open a serial terminal, reset the board (press the RESET button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v3.0.0 *****
Hello World! lpcxpresso55s06
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: lpcxpresso55s06
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS zephyr-v3.0.0 *****
Hello World! lpcxpresso55s06
.. _LPC55S06 SoC Website:
path_to_url
.. _LPC55S06 User Manual:
path_to_url
.. _LPCxpresso55S06 Website:
path_to_url
.. _LPCXpresso55S06 User Manual:
path_to_url
.. _LPCXpresso55S06 Development Board Design Files:
path_to_url
``` | /content/code_sandbox/boards/nxp/lpcxpresso55s06/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,633 |
```unknown
/*
*
* Note: File generated by gen_board_pinctrl.py
* from mimxrt1040_evk.mex
*/
#include <nxp/nxp_imx/rt/mimxrt1042xjm5b-pinctrl.dtsi>
&pinctrl {
/* Route ADC1 IN3 and IN4 to J33 pins 1 and 2 */
pinmux_adc1: pinmux_adc1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_14_adc1_in3>,
<&iomuxc_gpio_ad_b0_15_adc1_in4>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* Route PWM1 A3 to J16, pin 6 on arduino header */
pinmux_flexpwm1_pwm3: pinmux_flexpwm1_pwm3 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_10_flexpwm1_pwma3>;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
/* LPI2C1 SDA: J17 pin 9, LPI2C1 SCL: J17 pin 10 */
pinmux_lpi2c1: pinmux_lpi2c1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_00_lpi2c1_scl>,
<&iomuxc_gpio_ad_b1_01_lpi2c1_sda>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* LPI2C3 SDA: J33 pin 6, LPI2C3 SCL: J33 pin 5 */
pinmux_lpi2c3: pinmux_lpi2c3 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_06_lpi2c3_sda>,
<&iomuxc_gpio_ad_b1_07_lpi2c3_scl>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* Note that R350, R346, and R360 must be populated to use SPI */
pinmux_lpspi1: pinmux_lpspi1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_02_lpspi1_sdo>,
<&iomuxc_gpio_sd_b0_03_lpspi1_sdi>,
<&iomuxc_gpio_sd_b0_00_lpspi1_sck>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1: pinmux_lpuart1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_lpuart1_rx>,
<&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_gpio1_io13>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart3_flowcontrol: pinmux_lpuart3_flowcontrol {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_04_lpuart3_cts_b>,
<&iomuxc_gpio_ad_b1_05_lpuart3_rts_b>,
<&iomuxc_gpio_ad_b1_06_lpuart3_tx>,
<&iomuxc_gpio_ad_b1_07_lpuart3_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_05_gpio1_io21>,
<&iomuxc_gpio_ad_b1_07_gpio1_io23>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_04_lpuart3_cts_b>,
<&iomuxc_gpio_ad_b1_06_lpuart3_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lcdif: pinmux_lcdif {
group0 {
pinmux = <&iomuxc_gpio_b0_00_lcdif_clk>,
<&iomuxc_gpio_b0_01_lcdif_enable>,
<&iomuxc_gpio_b0_02_lcdif_hsync>,
<&iomuxc_gpio_b0_03_lcdif_vsync>,
<&iomuxc_gpio_b0_04_lcdif_data00>,
<&iomuxc_gpio_b0_05_lcdif_data01>,
<&iomuxc_gpio_b0_06_lcdif_data02>,
<&iomuxc_gpio_b0_07_lcdif_data03>,
<&iomuxc_gpio_b0_08_lcdif_data04>,
<&iomuxc_gpio_b0_09_lcdif_data05>,
<&iomuxc_gpio_b0_10_lcdif_data06>,
<&iomuxc_gpio_b0_11_lcdif_data07>,
<&iomuxc_gpio_b0_12_lcdif_data08>,
<&iomuxc_gpio_b0_13_lcdif_data09>,
<&iomuxc_gpio_b0_14_lcdif_data10>,
<&iomuxc_gpio_b0_15_lcdif_data11>,
<&iomuxc_gpio_b1_00_lcdif_data12>,
<&iomuxc_gpio_b1_01_lcdif_data13>,
<&iomuxc_gpio_b1_02_lcdif_data14>,
<&iomuxc_gpio_b1_03_lcdif_data15>;
drive-strength = "r0-6";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,668 |
```yaml
board:
name: mimxrt1040_evk
vendor: nxp
socs:
- name: mimxrt1042
``` | /content/code_sandbox/boards/nxp/mimxrt1040_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
if BOARD_MIMXRT1040_EVK
config DEVICE_CONFIGURATION_DATA
default y
config NXP_IMX_EXTERNAL_SDRAM
default y
endif # BOARD_MIMXRT1040_EVK
``` | /content/code_sandbox/boards/nxp/mimxrt1040_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
config BOARD_MIMXRT1040_EVK
select SOC_PART_NUMBER_MIMXRT1042XJM5B
``` | /content/code_sandbox/boards/nxp/mimxrt1040_evk/Kconfig.mimxrt1040_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
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