text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
config BOARD_MERCURY_XU
select SOC_XILINX_ZYNQMP_RPU
``` | /content/code_sandbox/boards/enclustra/mercury_xu/Kconfig.mercury_xu | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```yaml
identifier: up_squared_pro_7000
name: UP SQUARED PRO 7000 board
type: mcu
arch: x86
toolchain:
- zephyr
ram: 2048
supported:
- acpi
- smp
- watchdog
testing:
timeout_multiplier: 4
ignore_tags:
- net
- bluetooth
vendor: UP
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared_pro_7000/up_squared_pro_7000.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```cmake
board_set_flasher_ifnset(misc-flasher)
board_finalize_runner_args(misc-flasher)
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared_pro_7000/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_X2APIC=y
CONFIG_SMP=y
CONFIG_BUILD_OUTPUT_EFI=y
CONFIG_BUILD_NO_GAP_FILL=y
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared_pro_7000/up_squared_pro_7000_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```unknown
config BOARD_UP_SQUARED_PRO_7000
select SOC_ALDER_LAKE
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared_pro_7000/Kconfig.up_squared_pro_7000 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
/*
*
*/
#include "../../intel/adl/intel_adl.dts"
/ {
model = "UP Squared Pro 7000 board";
compatible = "aaeon,up_squared_pro_7000";
chosen {
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
};
};
&uart1 {
status = "okay";
};
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared_pro_7000/up_squared_pro_7000.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```yaml
board:
name: up_squared_pro_7000
socs:
- name: alder_lake
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared_pro_7000/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
if BOARD_UP_SQUARED_PRO_7000
config BUILD_OUTPUT_STRIPPED
default y
config MP_MAX_NUM_CPUS
default 2
# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1900000000 if APIC_TSC_DEADLINE_TIMER
default 1900000000 if APIC_TIMER_TSC
default 19200000
if APIC_TIMER
config APIC_TIMER_IRQ
default 24
endif
if APIC_TIMER_TSC
config APIC_TIMER_TSC_M
default 3
config APIC_TIMER_TSC_N
default 249
endif
config ACPI
default y
if ACPI
config HEAP_MEM_POOL_ADD_SIZE_ACPI
default 64000000
config MAIN_STACK_SIZE
default 320000
if SHELL
config SHELL_STACK_SIZE
default 320000
endif # SHELL
endif # ACPI
if DMA
config DMA_64BIT
default y
config DMA_DW_HW_LLI
default n
config DMA_DW_CHANNEL_COUNT
default 2
endif
config UART_NS16550_INTEL_LPSS_DMA
default y
config HAS_COVERAGE_SUPPORT
default y
endif # BOARD_UP_SQUARED_PRO_7000
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared_pro_7000/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 282 |
```cmake
board_set_flasher_ifnset(misc-flasher)
board_finalize_runner_args(misc-flasher)
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
config BOARD_UP_SQUARED
select SOC_APOLLO_LAKE
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared/Kconfig.up_squared | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 17 |
```yaml
identifier: up_squared
name: UP Squared (x86_64)
type: mcu
arch: x86
toolchain:
- zephyr
ram: 256
supported:
- acpi
- smp
testing:
ignore_tags:
- net
- bluetooth
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared/up_squared.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```restructuredtext
:orphan:
.. _up_squared_pro_7000_board:
UP Squared Pro 7000
###################
Overview
********
UP Squared Pro 7000 is the 3rd generation of palm-sized developer board of
UP Boards series. UP Squared Pro 7000 is powered by Intel Alder Lake N
(Intel N-series Platform).
For more information about Intel N-series Platform please refer to
:ref:`intel_adl_n`.
This board configuration enables kernel support for the UP Squared Pro 7000 boards.
Hardware
********
General information about the board can be found at the `UP Squared Pro 7000`_ website.
Connections and IOs
===================
Refer to the `UP Squared Pro 7000`_ website for more information.
Programming and Debugging
*************************
Use the following procedures for booting an image for an UP Squared Pro 7000 board.
.. contents::
:depth: 1
:local:
:backlinks: top
Build Zephyr application
========================
#. Build a Zephyr application; for instance, to build the ``hello_world``
application for UP Squared Pro 7000 board:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: up_squared_pro_7000
:goals: build
.. note::
A Zephyr EFI image file named :file:`zephyr.efi` is automatically
created in the build directory after the application is built.
Connect Serial Console
======================
Current board configuration assumes that serial console is connected to
connector ``CN14 USB 2.0/UART 1x10P Wafer``. Refer to `User Manual`_ for
description of the connector and location on the board.
Refer to `UP Serial Console`_ for additional information about serial
connection setup.
Booting the UP Squared Pro 7000 Board using UEFI
================================================
.. include:: ../../../intel/common/efi_boot.rst
:start-after: start_include_here
Booting the UP Squared Pro 7000 Board over network
==================================================
.. include:: ../../../intel/common/net_boot.rst
:start-after: start_include_here
References
**********
.. target-notes::
.. _UP Squared Pro 7000: path_to_url
.. _User Manual: path_to_url
.. _UP Serial Console: path_to_url
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared_pro_7000/doc/up_squared_pro_7000.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 517 |
```unknown
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_X2APIC=y
CONFIG_SMP=y
CONFIG_BUILD_OUTPUT_EFI=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_APIC_TSC_DEADLINE_TIMER=n
CONFIG_HPET_TIMER=y
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared/up_squared_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```yaml
board:
name: up_squared
socs:
- name: apollo_lake
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
/*
*
*/
/dts-v1/;
#include <mem.h>
#define DT_DRAM_SIZE DT_SIZE_M(2048)
#include <intel/apollo_lake.dtsi>
/ {
model = "up_squared";
compatible = "aaeon,up_squared";
aliases {
i2c-0 = &i2c0;
i2c-1 = &i2c1;
};
chosen {
zephyr,sram = &dram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,bt-hci = &bt_hci_uart;
zephyr,uart-pipe = &uart1;
zephyr,bt-mon-uart = &uart1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,apollo-lake";
d-cache-line-size = <64>;
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "intel,apollo-lake";
d-cache-line-size = <64>;
reg = <1>;
};
};
};
&uart1 {
bt_hci_uart: bt_hci_uart {
compatible = "zephyr,bt-hci-uart";
status = "okay";
};
};
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared/up_squared.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 318 |
```unknown
if BOARD_UP_SQUARED
config MP_MAX_NUM_CPUS
default 2 if BOARD_UP_SQUARED
config BUILD_OUTPUT_STRIPPED
default y
# TSC on this board is 1.5936 GHz, HPET and APIC are 19.2 MHz
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1593600000 if APIC_TSC_DEADLINE_TIMER
default 1593600000 if APIC_TIMER_TSC
default 19200000
if APIC_TIMER
config APIC_TIMER_IRQ
default 24
endif
if APIC_TIMER_TSC
config APIC_TIMER_TSC_M
default 3
config APIC_TIMER_TSC_N
default 249
endif
endif # BOARD_UP_SQUARED
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 164 |
```objective-c
/*
*
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
/* Map APL GPIO pins to pins on UP Squared HAT */
#define UP2_HAT_PIN_3_DEV APL_GPIO_DEV_N_0
#define UP2_HAT_PIN_3 APL_GPIO_28
#define UP2_HAT_PIN_5_DEV APL_GPIO_DEV_N_0
#define UP2_HAT_PIN_5 APL_GPIO_29
#define UP2_HAT_PIN_7_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_7 APL_GPIO_123
#define UP2_HAT_PIN_8_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_8 APL_GPIO_43
#define UP2_HAT_PIN_10_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_10 APL_GPIO_42
#define UP2_HAT_PIN_11_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_11 APL_GPIO_44
#define UP2_HAT_PIN_12_DEV APL_GPIO_DEV_W_0
#define UP2_HAT_PIN_12 APL_GPIO_146
#define UP2_HAT_PIN_13_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_13 APL_GPIO_122
#define UP2_HAT_PIN_15_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_15 APL_GPIO_121
#define UP2_HAT_PIN_16_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_16 APL_GPIO_37
#define UP2_HAT_PIN_18_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_18 APL_GPIO_88
#define UP2_HAT_PIN_19_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_19 APL_GPIO_110
#define UP2_HAT_PIN_21_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_21 APL_GPIO_109
#define UP2_HAT_PIN_22_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_22 APL_GPIO_85
#define UP2_HAT_PIN_23_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_23 APL_GPIO_104
#define UP2_HAT_PIN_24_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_24 APL_GPIO_105
#define UP2_HAT_PIN_26_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_26 APL_GPIO_106
#define UP2_HAT_PIN_27_DEV APL_GPIO_DEV_N_0
#define UP2_HAT_PIN_27 APL_GPIO_30
#define UP2_HAT_PIN_28_DEV APL_GPIO_DEV_N_0
#define UP2_HAT_PIN_28 APL_GPIO_31
#define UP2_HAT_PIN_29_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_29 APL_GPIO_120
#define UP2_HAT_PIN_31_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_31 APL_GPIO_87
#define UP2_HAT_PIN_32_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_32 APL_GPIO_34
#define UP2_HAT_PIN_33_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_33 APL_GPIO_35
#define UP2_HAT_PIN_35_DEV APL_GPIO_DEV_W_0
#define UP2_HAT_PIN_35 APL_GPIO_147
#define UP2_HAT_PIN_36_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_36 APL_GPIO_45
#define UP2_HAT_PIN_37_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_37 APL_GPIO_86
#define UP2_HAT_PIN_38_DEV APL_GPIO_DEV_W_0
#define UP2_HAT_PIN_38 APL_GPIO_148
#define UP2_HAT_PIN_40_DEV APL_GPIO_DEV_W_0
#define UP2_HAT_PIN_40 APL_GPIO_149
#endif /* __INC_BOARD_H */
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared/board.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,003 |
```restructuredtext
.. _boards-fanke:
Fanke
#####
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/fanke/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```cmake
board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(jlink "--device=STM32H7B0VB" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/fanke/fk7b0m1_vbt6/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```yaml
identifier: fk7b0m1_vbt6
name: FANKE FK7B0M1-VBT6 board
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 1376
flash: 128
supported:
- uart
- gpio
vendor: fanke
``` | /content/code_sandbox/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```yaml
board:
name: fk7b0m1_vbt6
vendor: fanke
socs:
- name: stm32h7b0xx
``` | /content/code_sandbox/boards/fanke/fk7b0m1_vbt6/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```restructuredtext
.. _up_squared:
UP Squared
##########
Overview
********
UP |sup2| (UP Squared) is an ultra compact single board computer with high
performance and low power consumption. It features the latest Intel |reg| Apollo
Lake Celeron |trade| and Pentium |trade| Processors with only 4W of Scenario Design Power and
a powerful and flexible Intel |reg| FPGA Altera MAX 10 onboard.
.. figure:: img/up_squared.jpg
:align: center
:alt: UP Squared
Up Squared (Credit: path_to_url
This board configuration enables kernel support for the `UP Squared`_ board.
.. note::
This board configuration works on all three variants of `UP Squared`_
boards containing Intel |reg| Pentium |trade| SoC,
Intel |reg| Celeron |trade| SoC, or Intel |reg| Atom |trade| SoC.
Hardware
********
General information about the board can be found at the `UP Squared`_ website.
.. include:: ../../../../soc/intel/apollo_lake/doc/supported_features.txt
GPIO
----
GPIOs are exposed through the HAT header, and can be referred using
predefined macros such as ``UP2_HAT_PIN3``. The physical pins are
connected to the on-board FPGA acting as level shifter. Therefore,
to actually utilize these GPIO pins, the function of the pins and
directions (input/output) must be set in the BIOS. This can be
accomplished in BIOS, under menu ``Advanced``, and option
``HAT Configurations``. When a corresponding pin is set to act as
GPIO, there is an option to set the direction of the pin. This needs
to be set accordingly for the GPIO to function properly.
Connections and IOs
===================
Refer to the `UP Squared`_ website and `UP Squared Pinout`_ website
for connection diagrams.
Programming and Debugging
*************************
Use the following procedures for booting an image on a UP Squared board.
.. contents::
:depth: 1
:local:
:backlinks: top
Build Zephyr application
========================
#. Build a Zephyr application; for instance, to build the ``hello_world``
application on UP Squared:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: up_squared
:goals: build
.. note::
A Zephyr EFI image file named :file:`zephyr.efi` is automatically
created in the build directory after the application is built.
Booting the UP Squared Board using UEFI
=======================================
.. include:: ../../../intel/common/efi_boot.rst
:start-after: start_include_here
.. note::
Refer to the `UP Squared Serial Console Wiki page
<path_to_url`_ for instructions on how to
connect serial console.
.. note::
You can safely ignore this message if it appears:
.. code-block:: console
WARNING: no console will be available to OS
Booting the UP Squared Board over network
=========================================
.. include:: ../../../intel/common/net_boot.rst
:start-after: start_include_here
.. note::
Refer to the `UP Squared Serial Console Wiki page
<path_to_url`_ for instructions on how to
connect serial console.
.. note::
To enable PXE boot for Up Squared board do the following:
#. Enable network from BIOS settings.
.. code-block:: console
Advanced -> Network Stack Configuration -> Enable Network Stack -> Enable Ipv4 PXE Support
#. Make network boot as the first boot option.
.. code-block:: console
Boot -> Boot Option #1 : [Network]
.. _UP Squared: path_to_url
.. _UP Squared Pinout: path_to_url
``` | /content/code_sandbox/boards/up-bridge-the-gap/up_squared/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 841 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART
CONFIG_SERIAL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable Pinctrl
CONFIG_PINCTRL=y
# Enable GPIO
CONFIG_GPIO=y
# Enable clocks
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
config BOARD_FK7B0M1_VBT6
select SOC_STM32H7B0XX
``` | /content/code_sandbox/boards/fanke/fk7b0m1_vbt6/Kconfig.fk7b0m1_vbt6 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```ini
source [find interface/stlink-dap.cfg]
transport select "dapdirect_swd"
set WORKAREASIZE 0x8000
set CHIPNAME STM32H7B0VB
set BOARDNAME FK7B0M1-VBT6
source [find target/stm32h7x.cfg]
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0
``` | /content/code_sandbox/boards/fanke/fk7b0m1_vbt6/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 155 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h7b0Xb.dtsi>
#include <st/h7/stm32h7b0vbtx-pinctrl.dtsi>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "FANKE FK7B0M1-VBT6 board";
compatible = "fanke,fk7b0m1-vbt6";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
user_led: led_0 {
gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>;
label = "User LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button_0 {
label = "User PB";
gpios = <&gpioc 13 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &user_led;
sw0 = &user_button;
};
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};
/* PLL1P is used for system clock (280 MHz) */
&pll {
div-m = <5>;
mul-n = <112>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(280)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <2>;
d2ppre1 = <2>;
d2ppre2 = <2>;
d3ppre = <2>;
};
&octospi1 {
pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pb6
&octospim_p1_io0_pd11 &octospim_p1_io1_pd12
&octospim_p1_io2_pe2 &octospim_p1_io3_pd13>;
pinctrl-names = "default";
status = "okay";
/* Winbond external flash */
w25q64jvssiq_qspi: qspi-nor-flash@0 {
compatible = "st,stm32-ospi-nor";
reg = <0 DT_SIZE_M(8)>; /* 64 Mbits */
ospi-max-frequency = <DT_FREQ_M(133)>;
spi-bus-width = <OSPI_QUAD_MODE>;
data-rate = <OSPI_STR_TRANSFER>;
writeoc = "PP_1_1_4";
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
slot0_partition: partition@0 {
reg = <0x00000000 DT_SIZE_M(8)>; /* 64 Mbits */
};
};
};
};
&spi6 {
pinctrl-0 = <&spi6_sck_pb3 &spi6_miso_pb4 &spi6_mosi_pb5>;
cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
status = "okay";
w25q64jvssiq_spi: spi-nor-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <DT_FREQ_M(40)>;
size = <DT_SIZE_M(64)>; /* 64 Mbits */
status = "okay";
jedec-id = [ef 40 17];
has-dpd;
t-enter-dpd = <3500>;
t-exit-dpd = <3500>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x00000000 DT_SIZE_M(8)>; /* 64 Mbits */
};
};
};
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&backup_sram {
status = "okay";
};
zephyr_udc0: &usbotg_hs {
pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&rng {
status = "okay";
};
``` | /content/code_sandbox/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,122 |
```restructuredtext
.. _boards-contextual-electronics:
Contextual Electronics
######################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/contextualelectronics/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```cmake
set(OPENOCD_NRF5_SUBFAMILY "nrf52")
board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake)
``` | /content/code_sandbox/boards/contextualelectronics/abc/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 129 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "contextualelectronics_abc-pinctrl.dtsi"
/ {
model = "nRF52840 BLE Cell";
compatible = "nordic,nrf52840-ble-cell";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
aliases {
watchdog0 = &wdt0;
};
};
®1 {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uart";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_serial: &uart1 {
status = "okay";
current-speed = <115200>;
/* UART Pin info. */
/* Use hardware flow control. */
hw-flow-control;
/* BG9x description. */
pinctrl-0 = <&uart1_default>;
pinctrl-1 = <&uart1_sleep>;
pinctrl-names = "default", "sleep";
quectel_bg9x {
compatible = "quectel,bg9x";
status = "okay";
mdm-power-gpios = <&gpio1 5 0>;
mdm-reset-gpios = <&gpio1 6 0>;
mdm-dtr-gpios = <&gpio0 22 0>;
};
};
arduino_i2c: &i2c0 {
compatible = "nordic,nrf-twi";
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
&spi2 {
compatible = "nordic,nrf-spi";
status = "okay";
/* This SPI device is interfaced with the SD card. */
pinctrl-0 = <&spi2_default>;
pinctrl-1 = <&spi2_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000C000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x00067000>;
};
slot1_partition: partition@73000 {
label = "image-1";
reg = <0x00073000 0x00067000>;
};
scratch_partition: partition@da000 {
label = "image-scratch";
reg = <0x000da000 0x0001e000>;
};
/*
* The flash starting at 0x000f8000 and ending at
* 0x000fffff is reserved for use by the application.
*/
/*
* Storage partition will be used by FCB/LittleFS/NVS
* if enabled.
*/
storage_partition: partition@f8000 {
label = "storage";
reg = <0x000f8000 0x00008000>;
};
};
};
``` | /content/code_sandbox/boards/contextualelectronics/abc/contextualelectronics_abc.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 869 |
```restructuredtext
.. _fk7b0m1_vbt6:
FANKE FK7B0M1-VBT6
##################
Overview
********
The FK7B0M1-VBT6 core board by FANKE Technology Co., Ltd. is an advanced microcontroller
platform based on the STMicroelectronics Arm Cortex-M7 core STM32H7B0VBT6 microcontroller.
This board is an ideal solution for developers looking to create high-performance
applications, especially in the field of Human-Machine Interface (HMI), leveraging its
robust capabilities and support for sophisticated display and touch technologies.
The FK7B0M1-VBT6 is designed as a reference design for user application development before
transitioning to the final product, significantly simplifying the development process.
Its wide range of hardware features, including advanced display and touch capabilities,
make it exceptionally suitable for HMI applications, allowing for comprehensive evaluation
and testing of peripherals and functionalities.
.. figure:: img/fk7b0m1_vbt6.webp
:width: 600px
:align: center
:alt: FK7B0M1-VBT6
FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd)
Hardware
********
FK7B0M1-VBT6 provides the following hardware components:
- STM32H7B6VB in LQFP100 package
- ARM 32-bit Cortex-M7 CPU with FPU
- 280 MHz max CPU frequency
- VDD from 1.62 V to 3.6 V
- 128 KB Flash
- ~1.4 MB SRAM max (1.18 Mbytes user SRAM + 64 Kbytes ITCM RAM + 128 Kbytes DTCM RAM + 4 Kbytes SRAM in Backup domain)
- Main clock: External 25MHz crystal oscillator.
- RTC: 32.768kHz crystal oscillator.
- 32-bit timers(2)
- 16-bit timers(12)
- 1 reset button, 1 user button, and 1 BOOT button
- 1 user LED
- External 64-Mbit QSPI (W25Q64) NOR Flash memory.
- External 64-Mbit SPI (W25Q64) NOR Flash memory.
- USB OTG Full Speed and High Speed(1)
- 1 micro SD card
- 1 RGB LCD interface
- SWD and serial port accessibility through a pin header
- Bring out 39 IO ports
More information about STM32H7B0VB can be found here:
- `STM32H7B0VB on www.st.com`_
Supported Features
==================
The Zephyr fk7b0m1_vbt6 board configuration supports the following hardware
features:
+-------------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+=============+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-------------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-------------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-------------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-------------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-------------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-------------+------------+-------------------------------------+
| Backup SRAM | on-chip | Backup SRAM |
+-------------+------------+-------------------------------------+
| SPI | on-chip | spi bus |
+-------------+------------+-------------------------------------+
| OCTOSPI | on-chip | octospi |
+-------------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration per core can be found in
:zephyr_file:`boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig`
Pin Mapping
===========
FK7B0M1-VBT6 board has 5 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
.. figure:: img/fk7b0m1_vbt6_pins.webp
:width: 600px
:align: center
:alt: FK7B0M1-VBT6
FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd)
Default Zephyr Peripheral Mapping:
----------------------------------
The FK7B0M1-VBT6 board is configured as follows
- UART_1 TX/RX : PA9/PA10 (available on the header pins)
- User LED (blue) : PC1
- User PB : PC13
- SPI1 NCS/CLK/MISO/MOSI : PA15/PB3/PB4/PB5 (NOR Flash)
- QuadSPI NCS/CLK/IO0/IO1/IO2/IO3 : PB6/PB2/PD11/PD12/PE2/PD13 (NOR Flash)
- USB DM/DP : PA11/PA12
System Clock
============
The FK7B0M1-VBT6 System Clock could be driven by an internal or external oscillator,
as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 280MHz,
driven by an 25MHz external crystal oscillator.
Serial Port
===========
The Zephyr console output is assigned to UART1. The default communication settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``fk7b0m1_vbt6`` board configuration can be built and flashed in the usual
way (see :ref:`build_an_application` and :ref:`application_run` for more details).
Flashing
========
The FK7B0M1-VBT6 board does not include an on-board debugger. As a result, it requires
an external debugger, such as ST-Link, for programming and debugging purposes.
The board provides header pins for the Serial Wire Debug (SWD) interface.
Flashing an application to FK7B0M1-VBT6
---------------------------------------
To begin, connect the ST-Link Debug Programmer to the FK7B0M1-VBT6 board using the SWD
interface. Next, connect the ST-Link to your host computer via a USB port.
Once this setup is complete, you can proceed to build and flash your application to the board
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: fk7b0m1_vbt6
:goals: build flash
Run a serial host program to connect with your board:
.. code-block:: console
$ minicom -D /dev/ttyACM0 -b 115200
Then, press the RESET button, you should see the following message:
.. code-block:: console
Hello World! fk7b0m1_vbt6
Debugging
=========
This current Zephyr port does not support debugging.
References
**********
.. target-notes::
.. _STM32H7B0VB on www.st.com: path_to_url
``` | /content/code_sandbox/boards/fanke/fk7b0m1_vbt6/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,575 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Enable uart driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/contextualelectronics/abc/contextualelectronics_abc_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```yaml
board:
name: contextualelectronics_abc
vendor: contextualelectronics
socs:
- name: nrf52840
``` | /content/code_sandbox/boards/contextualelectronics/abc/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/contextualelectronics/abc/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
# nRF52840 BLE Cell board configuration
if BOARD_CONTEXTUALELECTRONICS_ABC
config BT_CTLR
default BT
endif # BOARD_CONTEXTUALELECTRONICS_ABC
``` | /content/code_sandbox/boards/contextualelectronics/abc/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```yaml
identifier: contextualelectronics_abc
name: contextualelectronics_abc
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_i2c
- arduino_spi
- gpio
- i2c
- spi
- netif:openthread
vendor: contextualelectronics
``` | /content/code_sandbox/boards/contextualelectronics/abc/contextualelectronics_abc.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```unknown
# ABC board configuration
config BOARD_CONTEXTUALELECTRONICS_ABC
select SOC_NRF52840_QIAA
``` | /content/code_sandbox/boards/contextualelectronics/abc/Kconfig.contextualelectronics_abc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 7)>,
<NRF_PSEL(UART_RX, 0, 6)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 7)>,
<NRF_PSEL(UART_RX, 0, 6)>;
low-power-enable;
};
};
uart1_default: uart1_default {
group1 {
psels = <NRF_PSEL(UART_RX, 0, 20)>,
<NRF_PSEL(UART_TX, 0, 24)>,
<NRF_PSEL(UART_RTS, 0, 17)>,
<NRF_PSEL(UART_CTS, 0, 16)>;
};
};
uart1_sleep: uart1_sleep {
group1 {
psels = <NRF_PSEL(UART_RX, 0, 20)>,
<NRF_PSEL(UART_TX, 0, 24)>,
<NRF_PSEL(UART_RTS, 0, 17)>,
<NRF_PSEL(UART_CTS, 0, 16)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 27)>,
<NRF_PSEL(TWIM_SCL, 0, 26)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 27)>,
<NRF_PSEL(TWIM_SCL, 0, 26)>;
low-power-enable;
};
};
spi2_default: spi2_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
<NRF_PSEL(SPIM_MOSI, 0, 23)>,
<NRF_PSEL(SPIM_MISO, 0, 21)>;
};
};
spi2_sleep: spi2_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
<NRF_PSEL(SPIM_MOSI, 0, 23)>,
<NRF_PSEL(SPIM_MISO, 0, 21)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/contextualelectronics/abc/contextualelectronics_abc-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 598 |
```restructuredtext
.. _boards-vng:
VNG Corporation
###############
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/vngiotlab/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```cmake
board_runner_args(pyocd "--target=nrf51822")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# nRF51-VBLUNO51 board configuration
config BOARD_NRF51_VBLUNO51
select SOC_NRF51822_QFAC
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/Kconfig.nrf51_vbluno51 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & nrf-mpu@40000000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```yaml
board:
name: nrf51_vbluno51
vendor: vngiotlab
socs:
- name: nrf51822
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 10)>,
<NRF_PSEL(UART_RX, 0, 11)>,
<NRF_PSEL(UART_RTS, 0, 12)>,
<NRF_PSEL(UART_CTS, 0, 13)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 10)>,
<NRF_PSEL(UART_RX, 0, 11)>,
<NRF_PSEL(UART_RTS, 0, 12)>,
<NRF_PSEL(UART_CTS, 0, 13)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 29)>,
<NRF_PSEL(TWIM_SCL, 0, 30)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 29)>,
<NRF_PSEL(TWIM_SCL, 0, 30)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/nrf51_vbluno51-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 324 |
```unknown
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/nrf51_vbluno51_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```restructuredtext
.. _contextualelectronics_abc:
Contextual Electronics Advanced BLE Cell
########################################
Overview
********
The Contextual Electronics ABC (PCA10056) hardware provides support for the
Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices:
* CLOCK
* FLASH
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`I2C (Inter-Integrated Circuit)`
* :abbr:`MPU (Memory Protection Unit)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`PWM (Pulse Width Modulation)`
* Segger RTT (RTT Console)
* :abbr:`SPI (Serial Peripheral Interface)`
* :abbr:`UART (Universal asynchronous receiver-transmitter)`
* Quectel BG95 Modem
.. figure:: img/contextualelectronics_abc.jpg
:align: center
:alt: Contextual Electronics Advanced BLE Cell
Contextual Electronics Advanced BLE Cell (Credit: Chris Gamell)
More information about the board can be found at the `ABC Board website`_.
The `Nordic Semiconductor Infocenter`_ contains the processor's information
and the datasheet.
Hardware
********
ABC board has two external oscillators. The frequency of the slow clock
is 32.768 kHz. The frequency of the main clock is 32 MHz.
- nRF52840 ARM Cortex-M4F processor at 64 MHz
- 1 MB flash memory and 256 KB of SRAM
- SWD connector
Supported Features
==================
The contextualelectronics_abc board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| CLOCK | on-chip | clock_control |
+-----------+------------+----------------------+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
| RTC | on-chip | system clock |
+-----------+------------+----------------------+
| RTT | Segger | console |
+-----------+------------+----------------------+
| SPI(M) | on-chip | spi |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| Modem | on-board | quectel_bg9x |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
See `ABC Board website`_ for more details on this board, and
`Nordic Semiconductor Infocenter`_ for a complete list of SoC
features.
Programming and Debugging
*************************
Applications for the ``contextualelectronics_abc`` board configuration can be
built and flashed in the usual way (see :ref:`build_an_application`
and :ref:`application_run` for more details).
Flashing
========
Flashing Zephyr onto the ``contextualelectronics_abc`` board requires
an external programmer. The programmer is attached to the SWD header.
Build the Zephyr kernel and the :ref:`hello_world` sample application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: contextualelectronics_abc
:goals: build
:compact:
Flash the image.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: contextualelectronics_abc
:goals: flash
:compact:
To see the output, run your favorite terminal program.
.. code-block:: console
$ minicom -D <tty_device> -b 115200
Replace :code:`<tty_device>` with the port where the ABC board
can be found. For example, under Linux, :code:`/dev/ttyACM0`.
Debugging
=========
Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a
Segger IC.
Selecting the pins
==================
Pins can be configured in the board pinctrl file. To see the available mappings,
open the `nRF52840 Product Specification`_, chapter 7 'Hardware and Layout'.
In the table 7.1.1 'aQFN73 ball assignments' select the pins marked
'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used
in under-10KHz applications. They are not suitable for 115200 speed of UART.
References
**********
.. target-notes::
.. _ABC Board website: path_to_url
.. _Nordic Semiconductor Infocenter: path_to_url
.. _J-Link Software and documentation pack: path_to_url
.. _nRF52840 Product Specification: path_to_url
``` | /content/code_sandbox/boards/contextualelectronics/abc/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,135 |
```yaml
identifier: nrf51_vbluno51
name: nRF51-VBLUno51
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/nrf51_vbluno51.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
# nRF51 VBLUno51 board configuration
if BOARD_NRF51_VBLUNO51
config BT_CTLR
default BT
endif # BOARD_NRF51_VBLUNO51
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf51822_qfac.dtsi>
#include "nrf51_vbluno51-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "VNG VBLUno51 BLE board";
compatible = "vng,vbluno51";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
sw0 = &button0;
watchdog0 = &wdt0;
};
leds {
compatible = "gpio-leds";
/* green led */
led0: led_0 {
gpios = <&gpio0 7 0>;
label = "LED";
};
};
buttons {
/* Push button switch 0 KEY1 */
compatible = "gpio-keys";
button0: button_0 {
/* gpio flags need validation */
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
label = "Button";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&uart0 {
current-speed = <115200>;
status = "okay";
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/nrf51_vbluno51.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 470 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
<NRF_PSEL(TWIM_SCL, 0, 27)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
<NRF_PSEL(TWIM_SCL, 0, 27)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/nrf52_vbluno52-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 324 |
```cmake
board_runner_args(pyocd "--target=nrf52832")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/nrf52_vbluno52_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```unknown
# nRF52 VBLUno52 board configuration
config BOARD_NRF52_VBLUNO52
select SOC_NRF52832_QFAA
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/Kconfig.nrf52_vbluno52 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```restructuredtext
.. _nrf51_vbluno51:
nRF51-VBLUno51
##############
Overview
********
Zephyr uses the nrf51_vbluno51 board configuration to run on the VBLUno51 board,
a VNG Bluetooth Low Energy UNO using an nRF51822 ARM processor.
.. figure:: img/nrf51_vbluno51.jpg
:align: center
:alt: nRF51_VBLUno51
nrf51_vbluno51 Top
.. figure:: img/nrf51_vbluno51_bot.jpg
:align: center
:alt: nRF51_VBLUno51 Bottom
nrf51_vbluno51 Bottom
More information about the board can be found at the
`VBLUno51 wiki page`_.
Hardware
********
VBLUno51 board has two external oscillators. The frequency of
the slow clock is 32.768 kHz. The frequency of the main clock
is 16 MHz.
Supported Features
==================
- CPU:
+ Nordic nRF51822: ARM |reg| Cortex |trade| M0 32bit.
+ *Bluetooth Low Energy interface.*
+ 256KB Flash, 32KB RAM.
+ UART(1), I2C(2), SPI(1), PWM(3), SWD, Timer 16bit(3).
+ 21 digital channels, 6 ADC 10bit channels.
+ 1 Led and 1 Button onboard.
+ GPIO Voltage: 0 - 3.3V.
- DAPLink (CMSIS-DAP) interface for program and debug:
+ USB MSD: Drag and Drop programming flash memory.
+ USB HID (DAP): CMSIS-DAP compliant debug channel.
+ USB CDC: Virtual COM port for log, trace and terminal emulation.
- Supports hardware flow control features (RTS/CTS).
- *Energy monitoring for BLE module by current measurement (Only VBLUno51_EM)*
- FOTA (Firmware over the air): Upgrade firmware over BLE interface.
- Build good applications with:
+ Compiler and IDE: GCC, Keil MDK, IAR, Eclipse, Qt Creator.
+ Frameworks: Arduino, ARM mbed-OS, Zephyr-OS, Nordic SDK, RIOT-OS, MyNewt-OS, ChibiOS, NuttX RTOS
+ A lot of tutorials for Arduino, mbed-os and more.
- Pinout: Arduino Uno Rev3 compliant.
- Power:
+ USB port.
+ Power adapter: +9 -> +12V.
+ 3V Battery: CR20xx holder
+ Rechargeable battery jump: +3.7 -> +12V
- Open source: Hardware design, firmware, packages, tutorial and example codes
See `VBLUno51 wiki page`_ for full documents and tutorials about the VBLUno51 board.
Connections and IOs
===================
LED
---
* LED = LED0 (green) = P0.7
Push buttons
------------
* BUTTON = BUT = SW0 = P0.15
More details
------------
.. figure:: img/vbluno51_nordic_pinout.jpg
:align: center
:alt: nRF51_VBLUno51 Pinout
nrf51_vbluno51 Pinout
.. figure:: img/vbluno51_frizting.jpg
:align: center
:alt: nRF51_VBLUno51 Fritzing part
nrf51_vbluno51 Fritzing part
Programming and Debugging
*************************
Applications for the ``nrf51_vbluno51`` board configuration can be
built and flashed in the usual way (see :ref:`build_an_application`
and :ref:`application_run` for more details).
Flashing
========
The VBLUno51 board has on-board DAPLink (CMSIS-DAP) interface for flashing and debugging.
You do not need any other programming device.
You only need to install pyOCD tool (path_to_url
This tutorial uses the blinky application :zephyr:code-sample:`blinky`.
See the :ref:`getting_started` for general information on setting up
your development environment. Then build and flash the application in
the usual way.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nrf51_vbluno51
:goals: build flash
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nrf51_vbluno51
:maybe-skip-config:
:goals: debug
Testing the VBLUno51 with Zephyr: buttons, LEDs, UART, BLE
**********************************************************
Here are some sample applications that you can use to test different
components on the VBLUno51 board:
* :ref:`hello_world`
* :zephyr:code-sample:`blinky`
* :zephyr:code-sample:`button`
* :ref:`bluetooth-beacon-sample`
* :ref:`peripheral_hr`
References
**********
.. target-notes::
.. _VBLUno51 website: path_to_url
.. _VBLUno51 wiki page: path_to_url
``` | /content/code_sandbox/boards/vngiotlab/nrf51_vbluno51/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,161 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52832_qfaa.dtsi>
#include "nrf52_vbluno52-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "VNG VBLUno52 BLE 5.0 board";
compatible = "vng,vbluno52";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
sw0 = &button0;
watchdog0 = &wdt0;
};
leds {
compatible = "gpio-leds";
/* Green LED */
led0: led_0 {
gpios = <&gpio0 12 0>;
label = "LED";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
/* gpio flags need validation */
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
label = "Button";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&uart0 {
status = "okay";
compatible = "nordic,nrf-uart";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c0 {
compatible = "nordic,nrf-twim";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/nrf52_vbluno52.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 499 |
```yaml
board:
name: nrf52_vbluno52
vendor: vngiotlab
socs:
- name: nrf52832
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
# nRF52 VBLUno52 board configuration
if BOARD_NRF52_VBLUNO52
config BT_CTLR
default BT
endif # BOARD_NRF52_VBLUNO52
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```yaml
identifier: nrf52_vbluno52
name: nRF52-VBLUno52
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 512
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/nrf52_vbluno52.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```restructuredtext
.. _boards-ambiq:
Ambiq
#####
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/ambiq/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```cmake
board_runner_args(jlink "--device=AMA3B1KK-KBR" "--iface=swd" "--speed=1000")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/ambiq/apollo3_evb/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```restructuredtext
.. _nrf52_vbluno52:
nRF52-VBLUno52
##############
Overview
********
Zephyr can use the nrf52_vbluno52 board configuration to run on the VBLUno52 board,
a VNG Bluetooth Low Energy UNO using an nRF52832 ARM Cortex-M4F processor.
It provides support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and
the following devices:
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`RTC (nRF RTC System Clock)`
* UART
* GPIO
* FLASH
* RADIO (Bluetooth Low Energy 5.0)
.. figure:: img/nrf52_vbluno52.jpg
:align: center
:alt: nRF52 VBLUno52
nRF52_VBLUno52 board
Hardware
********
The VBLUno52 board has two external oscillators. The frequency of
the slow clock is 32.768 kHz. The frequency of the main clock
is 64 MHz.
Supported Features
==================
The nrf52_vbluno52 board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| NVIC | on-chip | nested vectored |
| | | interrupt controller |
+-----------+------------+----------------------+
| RTC | on-chip | system clock |
+-----------+------------+----------------------+
| UART | on-chip | serial port |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
| RADIO | on-chip | Bluetooth |
+-----------+------------+----------------------+
| I2C | on-chip | i2c |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
Connections and IOs
===================
LED
---
* LED = LED0 (green) = P0.12
Push buttons
------------
* BUTTON = BUT = SW0 = P0.17
Programming and Debugging
*************************
Flashing
========
The VBLUno52 board has an on-board DAPLink (CMSIS-DAP) interface for flashing and debugging.
You do not need any other programming device.
You only need to install the pyOCD tool (path_to_url
See the :ref:`getting_started` for general information on setting up
your development environment.
You can build and flash applications in the usual way. Here is an
example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nrf52_vbluno52
:goals: build flash
Testing the VBLUno52 with Zephyr: buttons, LEDs, UART, BLE
**********************************************************
Here are some sample applications that you can use to test different
components on the VBLUno52 board:
* :ref:`hello_world`
* :zephyr:code-sample:`blinky`
* :zephyr:code-sample:`button`
* :ref:`bluetooth-beacon-sample`
* :ref:`peripheral_hr`
``` | /content/code_sandbox/boards/vngiotlab/nrf52_vbluno52/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 738 |
```unknown
/*
*
*/
#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0TX_P22>;
};
group2 {
pinmux = <UART0RX_P23>;
input-enable;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c2_default: i2c2_default {
group1 {
pinmux = <M2SCL_P27>, <M2SDAWIR3_P25>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c3_default: i2c3_default {
group1 {
pinmux = <M3SCL_P42>, <M3SDAWIR3_P43>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c4_default: i2c4_default {
group1 {
pinmux = <M4SCL_P39>, <M4SDAWIR3_P40>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c5_default: i2c5_default {
group1 {
pinmux = <M5SCL_P48>, <M5SDAWIR3_P49>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
spi0_default: spi0_default {
group1 {
pinmux = <M0SCK_P5>, <M0MISO_P6>, <M0MOSI_P7>;
};
};
spi1_default: spi1_default {
group1 {
pinmux = <M1SCK_P8>, <M1MISO_P9>, <M1MOSI_P10>;
};
};
spi2_default: spi2_default {
group1 {
pinmux = <M2SCK_P27>, <M2MISO_P25>, <M2MOSI_P28>;
};
};
spi3_default: spi3_default {
group1 {
pinmux = <M3SCK_P42>, <M3MISO_P43>, <M3MOSI_P38>;
};
};
spi4_default: spi4_default {
group1 {
pinmux = <M4SCK_P39>, <M4MISO_P40>, <M4MOSI_P44>;
};
};
spi5_default: spi5_default {
group1 {
pinmux = <M5SCK_P48>, <M5MISO_P49>, <M5MOSI_P47>;
};
};
adc0_default: adc0_default{
group1 {
pinmux = <ADCSE4_P32>, <ADCSE7_P35>;
drive-strength = "0.1";
};
};
mspi0_default: mspi0_default{
group1 {
pinmux = <MSPI0_0_P22>,
<MSPI0_1_P26>,
<MSPI0_2_P4>,
<MSPI0_3_P23>,
<MSPI0_8_P24>;
};
group2 {
pinmux = <NCE19_P19>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-nce-module = <0>;
ambiq,iom-num = <6>;
};
};
bleif_default: bleif_default{
group1 {
pinmux = <BLEIF_SCK_P30>,
<BLEIF_MISO_P31>,
<BLEIF_MOSI_P32>,
<BLEIF_CSN_P33>,
<BLEIF_STATUS_P35>,
<BLEIF_IRQ_P41>;
};
};
};
``` | /content/code_sandbox/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,040 |
```yaml
board:
name: apollo3_evb
vendor: ambiq
socs:
- name: apollo3_blue
``` | /content/code_sandbox/boards/ambiq/apollo3_evb/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: apollo3_evb
name: Apollo3 Blue EVB
type: mcu
arch: arm
ram: 384
flash: 976
toolchain:
- zephyr
- gnuarmemb
supported:
- uart
- adc
- watchdog
- counter
- gpio
- spi
- i2c
testing:
ignore_tags:
- net
vendor: ambiq
``` | /content/code_sandbox/boards/ambiq/apollo3_evb/apollo3_evb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```unknown
#
config BOARD_APOLLO3_EVB
select SOC_APOLLO3_BLUE
``` | /content/code_sandbox/boards/ambiq/apollo3_evb/Kconfig.apollo3_evb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```unknown
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
``` | /content/code_sandbox/boards/ambiq/apollo3_evb/apollo3_evb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
/dts-v1/;
#include <ambiq/ambiq_apollo3_blue.dtsi>
#include "apollo3_evb-pinctrl.dtsi"
/ {
model = "Ambiq Apollo3 Blue evaluation board";
compatible = "ambiq,apollo3_evb";
chosen {
zephyr,itcm = &tcm;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-pipe = &uart0;
zephyr,flash-controller = &flash;
zephyr,bt_hci = &bt_hci_apollo;
};
aliases {
watchdog0 = &wdt0;
led0 = &led0;
led1 = &led1;
led2 = &led2;
sw0 = &button0;
sw1 = &button1;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0_31 10 GPIO_ACTIVE_LOW>;
label = "LED 0";
};
led1: led_1 {
gpios = <&gpio0_31 30 GPIO_ACTIVE_LOW>;
label = "LED 1";
};
led2: led_2 {
gpios = <&gpio0_31 15 GPIO_ACTIVE_LOW>;
label = "LED 2";
};
led3: led_3 {
gpios = <&gpio0_31 14 GPIO_ACTIVE_LOW>;
label = "LED 3";
};
led4: led_4 {
gpios = <&gpio0_31 17 GPIO_ACTIVE_LOW>;
label = "LED 4";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0_31 16 GPIO_ACTIVE_LOW>;
label = "BTN0";
};
button1: button_1 {
gpios = <&gpio0_31 18 GPIO_ACTIVE_LOW>;
label = "BTN1";
};
button2: button_2 {
gpios = <&gpio0_31 19 GPIO_ACTIVE_LOW>;
label = "BTN2";
};
};
};
&flash0 {
erase-block-size = <8192>;
write-block-size = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set 16KB of storage at the end of the 976KB of flash */
storage_partition: partition@f0000 {
label = "storage";
reg = <0x000f0000 0x4000>;
};
};
};
&bleif {
pinctrl-0 = <&bleif_default>;
pinctrl-names = "default";
status = "okay";
};
&uart0 {
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
status = "okay";
};
&wdt0 {
status = "okay";
};
&spi0 {
compatible = "ambiq,spi";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
clock-frequency = <DT_FREQ_M(1)>;
status = "okay";
};
&i2c3 {
compatible = "ambiq,i2c";
pinctrl-0 = <&i2c3_default>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
};
&counter0 {
status = "okay";
};
&counter1 {
status = "okay";
};
&counter2 {
status = "okay";
};
&counter3 {
status = "okay";
};
&counter4 {
status = "okay";
};
&counter5 {
status = "okay";
};
&counter6 {
status = "okay";
};
&counter7 {
status = "okay";
};
&adc0 {
compatible = "ambiq,adc";
pinctrl-0 = <&adc0_default>;
pinctrl-names = "default";
status = "disabled";
};
&gpio0_31 {
status = "okay";
};
&gpio32_63 {
status = "okay";
};
``` | /content/code_sandbox/boards/ambiq/apollo3_evb/apollo3_evb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 984 |
```cmake
board_runner_args(jlink "--device=AMAP42KK-KBR" "--iface=swd" "--speed=1000")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/ambiq/apollo4p_blue_kxr_evb/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
#
config BOARD_APOLLO4P_BLUE_KXR_EVB
select SOC_APOLLO4P_BLUE
``` | /content/code_sandbox/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.apollo4p_blue_kxr_evb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```unknown
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
``` | /content/code_sandbox/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
identifier: apollo4p_blue_kxr_evb
name: Apollo4 Blue Plus KXR EVB
type: mcu
arch: arm
ram: 2816
flash: 1952
toolchain:
- zephyr
- gnuarmemb
supported:
- uart
- watchdog
- counter
- gpio
- spi
- i2c
- clock_control
- ble
testing:
ignore_tags:
- net
vendor: ambiq
``` | /content/code_sandbox/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```restructuredtext
.. _apollo3_evb:
Ambiq Apollo3 Blue EVB
######################
Apollo3 Blue EVB is a board by Ambiq featuring their ultra-low power Apollo3 Blue SoC.
.. image:: ./apollo3-blue-soc-eval-board.jpg
:align: center
:alt: Apollo3 Blue EVB
Hardware
********
- Apollo3 Blue SoC with up to 96 MHz operating frequency
- ARM Cortex M4F core
- 16 kB 2-way Associative/Direct-Mapped Cache per core
- Up to 1 MB of flash memory for code/data
- Up to 384 KB of low leakage / low power RAM for code/data
- Integrated Bluetooth 5 Low-energy controller
For more information about the Apollo3 Blue SoC and Apollo3 Blue EVB board:
- `Apollo3 Blue Website`_
- `Apollo3 Blue Datasheet`_
- `Apollo3 Blue EVB Website`_
Supported Features
==================
The Apollo3 Blue EVB board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| MPU | on-chip | memory protection unit |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| STIMER | on-chip | stimer |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial |
+-----------+------------+-------------------------------------+
| WDT | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| RADIO | on-chip | bluetooth |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/apollo3_evb/apollo3_evb_defconfig``.
Programming and Debugging
=========================
Flashing an application
-----------------------
Connect your device to your host computer using the JLINK USB port.
The sample application :ref:`hello_world` is used for this example.
Build the Zephyr kernel and application, then flash it to the device:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: apollo3_evb
:goals: flash
.. note::
`west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module
to be installed on you host computer.
Open a serial terminal (minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Reset the board and you should be able to see on the corresponding Serial Port
the following message:
.. code-block:: console
Hello World! apollo3_evb
.. _Apollo3 Blue Website:
path_to_url
.. _Apollo3 Blue Datasheet:
path_to_url
.. _Apollo3 Blue EVB Website:
path_to_url
.. _SEGGER J-Link software:
path_to_url
.. _pylink:
path_to_url
``` | /content/code_sandbox/boards/ambiq/apollo3_evb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 723 |
```yaml
board:
name: apollo4p_blue_kxr_evb
vendor: ambiq
socs:
- name: apollo4p_blue
``` | /content/code_sandbox/boards/ambiq/apollo4p_blue_kxr_evb/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
/*
*
*/
#include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0TX_P12>;
};
group2 {
pinmux = <UART0RX_P47>;
input-enable;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c2_default: i2c2_default {
group1 {
pinmux = <M2SCL_P25>, <M2SDAWIR3_P26>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c3_default: i2c3_default {
group1 {
pinmux = <M3SCL_P31>, <M3SDAWIR3_P32>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c5_default: i2c5_default {
group1 {
pinmux = <M5SCL_P47>, <M5SDAWIR3_P48>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c6_default: i2c6_default {
group1 {
pinmux = <M6SCL_P61>, <M6SDAWIR3_P62>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c7_default: i2c7_default {
group1 {
pinmux = <M7SCL_P22>, <M7SDAWIR3_P23>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
spi0_default: spi0_default {
group1 {
pinmux = <M0SCK_P5>, <M0MISO_P7>, <M0MOSI_P6>;
};
};
spi1_default: spi1_default {
group1 {
pinmux = <M1SCK_P8>, <M1MISO_P10>, <M1MOSI_P9>;
};
};
spi2_default: spi2_default {
group1 {
pinmux = <M2SCK_P25>, <M2MISO_P27>, <M2MOSI_P26>;
};
};
spi3_default: spi3_default {
group1 {
pinmux = <M3SCK_P31>, <M3MISO_P33>, <M3MOSI_P32>;
};
};
spi4_default: spi4_default {
group1 {
pinmux = <M4SCK_P34>, <M4MISO_P36>, <M4MOSI_P35>;
};
};
spi5_default: spi5_default {
group1 {
pinmux = <M5SCK_P47>, <M5MISO_P49>, <M5MOSI_P48>;
};
};
spi6_default: spi6_default {
group1 {
pinmux = <M6SCK_P61>, <M6MISO_P63>, <M6MOSI_P62>;
};
};
spi7_default: spi7_default {
group1 {
pinmux = <M7SCK_P22>, <M7MISO_P24>, <M7MOSI_P23>;
};
};
mspi0_default: mspi0_default{
group1 {
pinmux = <MSPI0_0_P64>,
<MSPI0_1_P65>,
<MSPI0_8_P72>;
};
group2 {
pinmux = <NCE57_P57>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-nce-module = <32>;
};
};
mspi1_default: mspi1_default{
group1 {
pinmux = <MSPI1_0_P37>,
<MSPI1_1_P38>,
<MSPI1_8_P45>;
};
group2 {
pinmux = <NCE56_P56>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-nce-module = <34>;
};
};
mspi2_default: mspi2_default{
group1 {
pinmux = <MSPI2_0_P74>,
<MSPI2_1_P75>,
<MSPI2_8_P82>;
};
group2 {
pinmux = <NCE52_P52>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-nce-module = <36>;
};
};
xo32m_default: xo32m_default {
group1 {
pinmux = <CLKOUT_32M_P46>;
drive-strength = "0.1";
};
};
xo32k_default: xo32k_default {
group1 {
pinmux = <XT32KHZ_P4>;
drive-strength = "0.1";
};
};
};
``` | /content/code_sandbox/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,346 |
```unknown
#
if BOARD_APOLLO4P_BLUE_KXR_EVB
if BT
config MAIN_STACK_SIZE
default 2048
config BT_BUF_ACL_TX_COUNT
default 14
config BT_BUF_CMD_TX_SIZE
default $(UINT8_MAX)
config BT_BUF_EVT_RX_SIZE
default $(UINT8_MAX)
config BT_BUF_ACL_TX_SIZE
default 251
config BT_BUF_ACL_RX_SIZE
default 251
# L2CAP SDU/PDU TX MTU
# BT_L2CAP_RX_MTU = CONFIG_BT_BUF_ACL_RX_SIZE - BT_L2CAP_HDR_SIZE
config BT_L2CAP_TX_MTU
default 247
endif # BT
endif # BOARD_APOLLO4P_BLUE_KXR_EVB
``` | /content/code_sandbox/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```unknown
/dts-v1/;
#include <ambiq/ambiq_apollo4p_blue.dtsi>
#include "apollo4p_blue_kxr_evb-pinctrl.dtsi"
/ {
model = "Ambiq Apollo4 Blue Plus KXR evaluation board";
compatible = "ambiq,apollo4p_blue_kxr_evb";
chosen {
zephyr,itcm = &tcm;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-pipe = &uart0;
zephyr,flash-controller = &flash;
zephyr,bt-hci = &bt_hci_apollo;
};
aliases {
watchdog0 = &wdt0;
led0 = &led0;
led1 = &led1;
led2 = &led2;
sw0 = &button0;
sw1 = &button1;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0_31 30 GPIO_ACTIVE_LOW>;
label = "LED 0";
};
led1: led_1 {
gpios = <&gpio0_31 16 GPIO_ACTIVE_LOW>;
label = "LED 1";
};
led2: led_2 {
gpios = <&gpio64_95 27 GPIO_ACTIVE_LOW>;
label = "LED 2";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0_31 17 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "BTN0";
};
button1: button_1 {
gpios = <&gpio0_31 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "BTN1";
};
};
};
&uart0 {
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
status = "okay";
};
&counter0 {
status = "okay";
};
&wdt0 {
status = "okay";
};
&i2c0 {
compatible = "ambiq,i2c";
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
};
&spi1 {
compatible = "ambiq,spi";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
clock-frequency = <DT_FREQ_M(1)>;
status = "okay";
};
&spi4 {
pinctrl-0 = <&spi4_default>;
pinctrl-names = "default";
status = "okay";
};
&mspi0 {
pinctrl-0 = <&mspi0_default>;
pinctrl-names = "default";
status = "okay";
};
&flash0 {
erase-block-size = <2048>;
write-block-size = <16>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set 16KB of storage at the end of the 1952KB of flash */
storage_partition: partition@1e4000 {
label = "storage";
reg = <0x001e4000 0x4000>;
};
};
};
&xo32m {
pinctrl-0 = <&xo32m_default>;
pinctrl-names = "default";
status = "okay";
};
&xo32k {
pinctrl-0 = <&xo32k_default>;
pinctrl-names = "default";
status = "okay";
};
&gpio0_31 {
status = "okay";
};
&gpio32_63 {
status = "okay";
};
&gpio64_95 {
status = "okay";
};
&gpio96_127 {
status = "okay";
};
``` | /content/code_sandbox/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 915 |
```restructuredtext
.. _apollo4p_blue_kxr_evb:
Ambiq Apollo4 Blue Plus KXR EVB
###############################
Apollo4 Blue Plus KXR EVB is a board by Ambiq featuring their ultra-low power Apollo4 Blue Plus SoC.
.. image:: ./apollo4-blue-plus-kxr-soc-eval-board.jpg
:align: center
:alt: Apollo4 Blue Plus KXR EVB
Hardware
********
- Apollo4 Blue Plus SoC with upto 192 MHz operating frequency
- ARM Cortex M4F core
- 64 kB 2-way Associative/Direct-Mapped Cache per core
- Up to 2 MB of non-volatile memory (NVM) for code/data
- Up to 2.75 MB of low leakage / low power RAM for code/data
- 384 kB Tightly Coupled RAM
- 384 kB Extended RAM
- Bluetooth 5.1 Low Energy
For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KXR EVB board:
- `Apollo4 Blue Plus Website`_
- `Apollo4 Blue Plus Datasheet`_
- `Apollo4 Blue Plus KXR EVB Website`_
Supported Features
==================
The Apollo4 Blue Plus KXR EVB board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| MPU | on-chip | memory protection unit |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| STIMER | on-chip | stimer |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial |
+-----------+------------+-------------------------------------+
| WDT | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| SPI(M) | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| RADIO | on-chip | bluetooth |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig`
Programming and Debugging
=========================
Flashing an application
-----------------------
Connect your device to your host computer using the JLINK USB port.
The sample application :ref:`hello_world` is used for this example.
Build the Zephyr kernel and application, then flash it to the device:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: apollo4p_blue_kxr_evb
:goals: flash
.. note::
`west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module
to be installed on you host computer.
Open a serial terminal (minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Reset the board and you should be able to see on the corresponding Serial Port
the following message:
.. code-block:: console
Hello World! apollo4p_blue_kxr_evb
.. _Apollo4 Blue Plus Website:
path_to_url
.. _Apollo4 Blue Plus Datasheet:
path_to_url
.. _Apollo4 Blue Plus KXR EVB Website:
path_to_url
.. _SEGGER J-Link software:
path_to_url
.. _pylink:
path_to_url
``` | /content/code_sandbox/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 868 |
```cmake
board_runner_args(jlink "--device=AMA3B2KK-KBR" "--iface=swd" "--speed=1000")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/ambiq/apollo3p_evb/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```unknown
/dts-v1/;
#include <ambiq/ambiq_apollo3p_blue.dtsi>
#include "apollo3p_evb-pinctrl.dtsi"
/ {
model = "Ambiq Apollo3 Blue Plus evaluation board";
compatible = "ambiq,apollo3p_evb";
chosen {
zephyr,itcm = &tcm;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-pipe = &uart0;
zephyr,flash-controller = &flash;
zephyr,bt_hci = &bt_hci_apollo;
};
aliases {
watchdog0 = &wdt0;
led0 = &led0;
led1 = &led1;
led2 = &led2;
sw0 = &button0;
sw1 = &button1;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0_31 10 GPIO_ACTIVE_LOW>;
label = "LED 0";
};
led1: led_1 {
gpios = <&gpio0_31 30 GPIO_ACTIVE_LOW>;
label = "LED 1";
};
led2: led_2 {
gpios = <&gpio0_31 15 GPIO_ACTIVE_LOW>;
label = "LED 2";
};
led3: led_3 {
gpios = <&gpio0_31 14 GPIO_ACTIVE_LOW>;
label = "LED 3";
};
led4: led_4 {
gpios = <&gpio0_31 17 GPIO_ACTIVE_LOW>;
label = "LED 4";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0_31 16 GPIO_ACTIVE_LOW>;
label = "BTN0";
};
button1: button_1 {
gpios = <&gpio0_31 18 GPIO_ACTIVE_LOW>;
label = "BTN1";
};
button2: button_2 {
gpios = <&gpio0_31 19 GPIO_ACTIVE_LOW>;
label = "BTN2";
};
};
};
&flash0 {
erase-block-size = <8192>;
write-block-size = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set 16KB of storage at the end of the 2000KB of flash */
storage_partition: partition@1f0000 {
label = "storage";
reg = <0x001f0000 0x4000>;
};
};
};
&bleif {
pinctrl-0 = <&bleif_default>;
pinctrl-names = "default";
status = "okay";
};
&uart0 {
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
status = "okay";
};
&wdt0 {
status = "okay";
};
&spi0 {
compatible = "ambiq,spi";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
clock-frequency = <DT_FREQ_M(1)>;
status = "okay";
};
&i2c3 {
compatible = "ambiq,i2c";
pinctrl-0 = <&i2c3_default>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
};
&counter0 {
status = "okay";
};
&counter1 {
status = "okay";
};
&counter2 {
status = "okay";
};
&counter3 {
status = "okay";
};
&counter4 {
status = "okay";
};
&counter5 {
status = "okay";
};
&counter6 {
status = "okay";
};
&counter7 {
status = "okay";
};
&adc0 {
compatible = "ambiq,adc";
pinctrl-0 = <&adc0_default>;
pinctrl-names = "default";
status = "disabled";
};
&gpio0_31 {
status = "okay";
};
&gpio32_63 {
status = "okay";
};
&gpio64_95 {
status = "okay";
};
``` | /content/code_sandbox/boards/ambiq/apollo3p_evb/apollo3p_evb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,002 |
```unknown
#
config BOARD_APOLLO3P_EVB
select SOC_APOLLO3P_BLUE
``` | /content/code_sandbox/boards/ambiq/apollo3p_evb/Kconfig.apollo3p_evb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```yaml
identifier: apollo3p_evb
name: Apollo3 Blue Plus EVB
type: mcu
arch: arm
ram: 768
flash: 2000
toolchain:
- zephyr
- gnuarmemb
supported:
- uart
- adc
- watchdog
- counter
- gpio
- spi
- i2c
- mspi
testing:
ignore_tags:
- net
vendor: ambiq
``` | /content/code_sandbox/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 108 |
```yaml
board:
name: apollo3p_evb
vendor: ambiq
socs:
- name: apollo3p_blue
``` | /content/code_sandbox/boards/ambiq/apollo3p_evb/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
``` | /content/code_sandbox/boards/ambiq/apollo3p_evb/apollo3p_evb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
/*
*
*/
#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0TX_P22>;
};
group2 {
pinmux = <UART0RX_P23>;
input-enable;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c2_default: i2c2_default {
group1 {
pinmux = <M2SCL_P27>, <M2SDAWIR3_P25>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c3_default: i2c3_default {
group1 {
pinmux = <M3SCL_P42>, <M3SDAWIR3_P43>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c4_default: i2c4_default {
group1 {
pinmux = <M4SCL_P39>, <M4SDAWIR3_P40>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c5_default: i2c5_default {
group1 {
pinmux = <M5SCL_P48>, <M5SDAWIR3_P49>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
spi0_default: spi0_default {
group1 {
pinmux = <M0SCK_P5>, <M0MISO_P6>, <M0MOSI_P7>;
};
};
spi1_default: spi1_default {
group1 {
pinmux = <M1SCK_P8>, <M1MISO_P9>, <M1MOSI_P10>;
};
};
spi2_default: spi2_default {
group1 {
pinmux = <M2SCK_P27>, <M2MISO_P25>, <M2MOSI_P28>;
};
};
spi3_default: spi3_default {
group1 {
pinmux = <M3SCK_P42>, <M3MISO_P43>, <M3MOSI_P38>;
};
};
spi4_default: spi4_default {
group1 {
pinmux = <M4SCK_P39>, <M4MISO_P40>, <M4MOSI_P44>;
};
};
spi5_default: spi5_default {
group1 {
pinmux = <M5SCK_P48>, <M5MISO_P49>, <M5MOSI_P47>;
};
};
adc0_default: adc0_default{
group1 {
pinmux = <ADCSE4_P32>, <ADCSE7_P35>;
drive-strength = "0.1";
};
};
mspi0_default: mspi0_default{
group1 {
pinmux = <MSPI0_0_P22>,
<MSPI0_1_P26>,
<MSPI0_2_P4>,
<MSPI0_3_P23>,
<MSPI0_8_P24>;
};
group2 {
pinmux = <NCE37_P37>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-mspi = <0>;
ambiq,iom-nce-module = <0>;
ambiq,iom-num = <0>;
};
};
mspi1_default: mspi1_default{
group1 {
pinmux = <MSPI1_0_P51>,
<MSPI1_1_P52>,
<MSPI1_2_P53>,
<MSPI1_3_P54>,
<MSPI1_4_P55>,
<MSPI1_5_P56>,
<MSPI1_6_P57>,
<MSPI1_7_P58>,
<MSPI1_8_P59>;
};
group2 {
pinmux = <NCE50_P50>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-mspi = <0>;
ambiq,iom-nce-module = <0>;
ambiq,iom-num = <1>;
};
};
mspi2_default: mspi2_default{
group1 {
pinmux = <MSPI2_0_P64>,
<MSPI2_1_P65>,
<MSPI2_2_P66>,
<MSPI2_3_P67>,
<MSPI2_4_P68>;
};
group2 {
pinmux = <NCE63_P63>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-mspi = <0>;
ambiq,iom-nce-module = <0>;
ambiq,iom-num = <2>;
};
};
bleif_default: bleif_default{
group1 {
pinmux = <BLEIF_SCK_P30>,
<BLEIF_MISO_P31>,
<BLEIF_MOSI_P32>,
<BLEIF_CSN_P33>,
<BLEIF_STATUS_P35>,
<BLEIF_IRQ_P41>;
};
};
};
``` | /content/code_sandbox/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,384 |
```restructuredtext
.. _apollo3p_evb:
Ambiq Apollo3 Blue Plus EVB
###########################
Apollo3 Blue Plus EVB is a board by Ambiq featuring their ultra-low power Apollo3 Blue Plus SoC.
.. image:: ./apollo3-blue-plus-soc-eval-board.jpg
:align: center
:alt: Apollo3 Blue Plus EVB
Hardware
********
- Apollo3 Blue Plus SoC with up to 96 MHz operating frequency
- ARM Cortex M4F core
- 16 kB 2-way Associative/Direct-Mapped Cache per core
- Up to 2 MB of flash memory for code/data
- Up to 768 KB of low leakage / low power RAM for code/data
- Integrated Bluetooth 5 Low-energy controller
For more information about the Apollo3 Blue Plus SoC and Apollo3 Blue Plus EVB board:
- `Apollo3 Blue Plus Website`_
- `Apollo3 Blue Plus Datasheet`_
- `Apollo3 Blue Plus EVB Website`_
Supported Features
==================
The Apollo3 Blue Plus EVB board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| MPU | on-chip | memory protection unit |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| STIMER | on-chip | stimer |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial |
+-----------+------------+-------------------------------------+
| WDT | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| RADIO | on-chip | bluetooth |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/apollo3p_evb/apollo3p_evb_defconfig``.
Programming and Debugging
=========================
Flashing an application
-----------------------
Connect your device to your host computer using the JLINK USB port.
The sample application :ref:`hello_world` is used for this example.
Build the Zephyr kernel and application, then flash it to the device:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: apollo3p_evb
:goals: flash
.. note::
`west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module
to be installed on you host computer.
Open a serial terminal (minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Reset the board and you should be able to see on the corresponding Serial Port
the following message:
.. code-block:: console
Hello World! apollo3p_evb
.. _Apollo3 Blue Plus Website:
path_to_url
.. _Apollo3 Blue Plus Datasheet:
path_to_url
.. _Apollo3 Blue Plus EVB Website:
path_to_url
.. _SEGGER J-Link software:
path_to_url
.. _pylink:
path_to_url
``` | /content/code_sandbox/boards/ambiq/apollo3p_evb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 742 |
```cmake
board_runner_args(jlink "--device=AMAP42KK-KBR" "--iface=swd" "--speed=1000")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/ambiq/apollo4p_evb/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```yaml
identifier: apollo4p_evb
name: Apollo4P EVB
type: mcu
arch: arm
ram: 2816
flash: 1952
toolchain:
- zephyr
- gnuarmemb
supported:
- uart
- watchdog
- counter
- gpio
- spi
- i2c
- rtc
- hwinfo
testing:
ignore_tags:
- net
- bluetooth
vendor: ambiq
``` | /content/code_sandbox/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```unknown
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
``` | /content/code_sandbox/boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
board:
name: apollo4p_evb
vendor: ambiq
socs:
- name: apollo4p
``` | /content/code_sandbox/boards/ambiq/apollo4p_evb/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/dts-v1/;
#include <ambiq/ambiq_apollo4p.dtsi>
#include "apollo4p_evb-pinctrl.dtsi"
/ {
model = "Ambiq Apollo4 Plus evaluation board";
compatible = "ambiq,apollo4p_evb";
chosen {
zephyr,itcm = &tcm;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-pipe = &uart0;
zephyr,flash-controller = &flash;
};
aliases {
watchdog0 = &wdt0;
led0 = &led0;
led1 = &led1;
led2 = &led2;
sw0 = &button0;
sw1 = &button1;
rtc = &rtc0;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0_31 30 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "LED 0";
};
led1: led_1 {
gpios = <&gpio64_95 26 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "LED 1";
};
led2: led_2 {
gpios = <&gpio96_127 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "LED 2";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0_31 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "BTN0";
};
button1: button_1 {
gpios = <&gpio0_31 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "BTN1";
};
};
};
&uart0 {
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
status = "okay";
};
&counter0 {
status = "okay";
};
&rtc0 {
status = "okay";
clock = "XTAL";
};
&wdt0 {
status = "okay";
};
&iom0_i2c {
compatible = "ambiq,i2c";
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
};
&iom1_spi {
compatible = "ambiq,spi";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
clock-frequency = <1000000>;
status = "okay";
};
&mspi0 {
pinctrl-0 = <&mspi0_default>;
pinctrl-names = "default";
status = "okay";
};
&mspi1 {
pinctrl-0 = <&mspi1_default>;
pinctrl-names = "default";
status = "okay";
};
&mspi2 {
pinctrl-0 = <&mspi2_default>;
pinctrl-names = "default";
status = "okay";
};
&flash0 {
erase-block-size = <2048>;
write-block-size = <16>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set 16KB of storage at the end of the 1952KB of flash */
storage_partition: partition@1e4000 {
label = "storage";
reg = <0x001e4000 0x4000>;
};
};
};
&gpio0_31 {
status = "okay";
};
&gpio32_63 {
status = "okay";
};
&gpio64_95 {
status = "okay";
};
&gpio96_127 {
status = "okay";
};
``` | /content/code_sandbox/boards/ambiq/apollo4p_evb/apollo4p_evb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 900 |
```unknown
#
config BOARD_APOLLO4P_EVB
select SOC_APOLLO4P
``` | /content/code_sandbox/boards/ambiq/apollo4p_evb/Kconfig.apollo4p_evb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
/*
*
*/
#include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
#include "apollo4p_evb_connector.dtsi"
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0TX_P60>;
};
group2 {
pinmux = <UART0RX_P47>;
input-enable;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c2_default: i2c2_default {
group1 {
pinmux = <M2SCL_P25>, <M2SDAWIR3_P26>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c3_default: i2c3_default {
group1 {
pinmux = <M3SCL_P31>, <M3SDAWIR3_P32>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c4_default: i2c4_default {
group1 {
pinmux = <M4SCL_P34>, <M4SDAWIR3_P35>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c5_default: i2c5_default {
group1 {
pinmux = <M5SCL_P47>, <M5SDAWIR3_P48>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c6_default: i2c6_default {
group1 {
pinmux = <M6SCL_P61>, <M6SDAWIR3_P62>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c7_default: i2c7_default {
group1 {
pinmux = <M7SCL_P22>, <M7SDAWIR3_P23>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
spi0_default: spi0_default {
group1 {
pinmux = <M0SCK_P5>, <M0MISO_P7>, <M0MOSI_P6>;
};
};
spi1_default: spi1_default {
group1 {
pinmux = <M1SCK_P8>, <M1MISO_P10>, <M1MOSI_P9>;
};
};
spi2_default: spi2_default {
group1 {
pinmux = <M2SCK_P25>, <M2MISO_P27>, <M2MOSI_P26>;
};
};
spi3_default: spi3_default {
group1 {
pinmux = <M3SCK_P31>, <M3MISO_P33>, <M3MOSI_P32>;
};
};
spi4_default: spi4_default {
group1 {
pinmux = <M4SCK_P34>, <M4MISO_P36>, <M4MOSI_P35>;
};
};
spi5_default: spi5_default {
group1 {
pinmux = <M5SCK_P47>, <M5MISO_P49>, <M5MOSI_P48>;
};
};
spi6_default: spi6_default {
group1 {
pinmux = <M6SCK_P61>, <M6MISO_P63>, <M6MOSI_P62>;
};
};
spi7_default: spi7_default {
group1 {
pinmux = <M7SCK_P22>, <M7MISO_P24>, <M7MOSI_P23>;
};
};
mspi0_default: mspi0_default{
group1 {
pinmux = <MSPI0_0_P64>,
<MSPI0_1_P65>,
<MSPI0_8_P72>;
};
group2 {
pinmux = <NCE57_P57>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-nce-module = <32>;
};
};
mspi1_default: mspi1_default{
group1 {
pinmux = <MSPI1_0_P37>,
<MSPI1_1_P38>,
<MSPI1_8_P45>;
};
group2 {
pinmux = <NCE56_P56>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-nce-module = <34>;
};
};
mspi2_default: mspi2_default{
group1 {
pinmux = <MSPI2_0_P74>,
<MSPI2_1_P75>,
<MSPI2_8_P82>;
};
group2 {
pinmux = <NCE0_P0>;
drive-push-pull;
drive-strength = "0.5";
ambiq,iom-nce-module = <36>;
};
};
};
``` | /content/code_sandbox/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,338 |
```restructuredtext
.. _apollo4p_evb:
Ambiq Apollo4P EVB
##################
Apollo4P EVB is a board by Ambiq featuring their ultra-low power Apollo4 Plus SoC.
.. image:: ./apollo4-plus-soc-eval-board.jpg
:align: center
:alt: Apollo4P EVB
Hardware
********
- Apollo4 Plus SoC with upto 192 MHz operating frequency
- ARM Cortex M4F core
- 64 kB 2-way Associative/Direct-Mapped Cache per core
- Up to 2 MB of non-volatile memory (NVM) for code/data
- Up to 2.75 MB of low leakage / low power RAM for code/data
- 384 kB Tightly Coupled RAM
- 384 kB Extended RAM
For more information about the Apollo4 Plus SoC and Apollo4P EVB board:
- `Apollo4 Plus Website`_
- `Apollo4 Plus Datasheet`_
- `Apollo4P EVB Website`_
Supported Features
==================
The Apollo4P EVB board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| MPU | on-chip | memory protection unit |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| STIMER | on-chip | stimer |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial |
+-----------+------------+-------------------------------------+
| WDT | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| SPI(M) | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig`
Programming and Debugging
=========================
Flashing an application
-----------------------
Connect your device to your host computer using the JLINK USB port.
The sample application :ref:`hello_world` is used for this example.
Build the Zephyr kernel and application, then flash it to the device:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: apollo4p_evb
:goals: flash
.. note::
`west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module
to be installed on you host computer.
Open a serial terminal (minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Reset the board and you should be able to see on the corresponding Serial Port
the following message:
.. code-block:: console
Hello World! apollo4p_evb
.. _Apollo4 Plus Website:
path_to_url
.. _Apollo4 Plus Datasheet:
path_to_url
.. _Apollo4P EVB Website:
path_to_url
.. _SEGGER J-Link software:
path_to_url
.. _pylink:
path_to_url
``` | /content/code_sandbox/boards/ambiq/apollo4p_evb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 772 |
```restructuredtext
.. _boards-rak:
RAKwireless
###########
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/rak/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```cmake
# Sercan Erat <sercanerat@gmail.com>
board_runner_args(jlink "--device=AMA3B1KK-KBR" "--iface=swd" "--speed=1000")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/rak/rak11720/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
/*
*
*/
/ {
ambiq_header: connector {
compatible = "ambiq-header";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffff80>;
gpio-map-pass-thru = <0 0x7f>;
gpio-map = <0 0 &gpio0_31 0 0>, /* IOS_SPI_SCK, IOS_I2C_SCL, MSPI2_CE0 */
<1 0 &gpio0_31 1 0>, /* IOS_SPI_MOSI, IOS_I2C_SDA, MSPI0_CE0 */
<2 0 &gpio0_31 2 0>, /* IOS_SPI_MISO */
<3 0 &gpio0_31 3 0>, /* IOS_CE */
<4 0 &gpio0_31 4 0>, /* IOS_INT */
<5 0 &gpio0_31 5 0>, /* IOM0_SPI_SCK, IOM0_I2C_SCL */
<6 0 &gpio0_31 6 0>, /* IOM0_SPI_MOSI, IOM0_I2C_SDA */
<7 0 &gpio0_31 7 0>, /* See am_hal_pins.h file for further info */
<8 0 &gpio0_31 8 0>, /* IOM1_SPI_SCK, IOM1_I2C_SCL */
<9 0 &gpio0_31 9 0>, /* IOM1_SPI_MOSI, IOM1_I2C_SDA */
<10 0 &gpio0_31 10 0>, /* IOM1_SPI_MISO */
<11 0 &gpio0_31 11 0>, /* UART2_RX, IOM1_CS, I2S0_CLK */
<12 0 &gpio0_31 12 0>, /* ADCSE7, UART1_TX, I2S0_DATA, I2S0_SDOUT */
<13 0 &gpio0_31 13 0>, /* ADCSE6, UART2_TX, I2S0_WS */
<14 0 &gpio0_31 14 0>, /* ADCSE5, UART1_RX, I2S0_SDIN */
<15 0 &gpio0_31 15 0>, /* ADCSE4 */
<16 0 &gpio0_31 16 0>, /* ADCSE3, I2S1_CLK */
<17 0 &gpio0_31 17 0>, /* ADCSE2, UART3_RTS, I2S1_DATA */
<18 0 &gpio0_31 18 0>, /* BUTTON0, ADCSE1, I2S1_WS */
<19 0 &gpio0_31 19 0>, /* BUTTON1, ADCSE0, UART3_CTS, I2S1_SDIN */
<20 0 &gpio0_31 19 0>, /* SWDCK */
<21 0 &gpio0_31 19 0>, /* SWDIO */
<22 0 &gpio0_31 22 0>, /* IOM7_SPI_SCK, IOM7_I2C_SCL */
<23 0 &gpio0_31 23 0>, /* IOM7_SPI_MOSI, IOM7_I2C_SDA */
<24 0 &gpio0_31 24 0>, /* IOM7_SPI_MISO */
<25 0 &gpio0_31 25 0>, /* IOM2_SPI_SCK, IOM2_I2C_SCL */
<26 0 &gpio0_31 26 0>, /* IOM2_SPI_MOSI, IOM2_I2C_SDA */
<27 0 &gpio0_31 27 0>, /* IOM2_SPI_MISO */
<28 0 &gpio0_31 28 0>, /* ITM_SWO */
<29 0 &gpio0_31 29 0>, /* See am_hal_pins.h file for further info */
<30 0 &gpio0_31 30 0>, /* LED1, IOM6_CS */
<31 0 &gpio0_31 31 0>, /* IOM3_SPI_SCK, IOM3_I2C_SCL */
<32 0 &gpio32_63 0 0>, /* IOM3_SPI_MOSI, IOM3_I2C_SDA */
<33 0 &gpio32_63 1 0>, /* IOM3_SPI_MISO */
<34 0 &gpio32_63 2 0>, /* IOM4_SPI_SCK, IOM4_I2C_SCL */
<35 0 &gpio32_63 3 0>, /* IOM4_SPI_MOSI, IOM4_I2C_SDA */
<36 0 &gpio32_63 4 0>, /* IOM4_SPI_MISO */
<37 0 &gpio32_63 5 0>, /* IOM2_CS, MSPI1_D0, X16SPI_D8 */
<38 0 &gpio32_63 6 0>, /* MSPI1_D1, X16SPI_D9 */
<39 0 &gpio32_63 7 0>, /* MSPI1_D2, X16SPI_D10 */
<40 0 &gpio32_63 8 0>, /* MSPI1_D3, X16SPI_D11 */
<41 0 &gpio32_63 9 0>, /* MSPI1_D4, X16SPI_D12 */
<42 0 &gpio32_63 10 0>, /* MSPI1_D5, X16SPI_D13 */
<43 0 &gpio32_63 11 0>, /* MSPI1_D6, X16SPI_D14 */
<44 0 &gpio32_63 12 0>, /* MSPI1_D7, X16SPI_D15 */
<45 0 &gpio32_63 13 0>, /* MSPI1_SCK, X16SPI_DQS1DM1 */
<46 0 &gpio32_63 14 0>, /* MSPI1_DQSDM */
<47 0 &gpio32_63 15 0>, /* COM_UART_RX, IOM5_SPI_SCK, IOM5_I2C_SCL */
<48 0 &gpio32_63 16 0>, /* IOM5_SPI_MOSI, IOM5_I2C_SDA */
<49 0 &gpio32_63 17 0>, /* UART1_RTS, IOM5_SPI_MISO */
<50 0 &gpio32_63 18 0>, /* UART2_RTS, ETM_TRACECLK, PDM0_CLK */
<51 0 &gpio32_63 19 0>, /* UART1_CTS, EMT_TRACE0, PDM0_DATA */
<52 0 &gpio32_63 20 0>, /* UART2_CTS, MSPI0_CE1, ETM_TRACE1, PDM1_CLK */
<53 0 &gpio32_63 21 0>, /* ETM_TRACE2, PDM1_DATA */
<54 0 &gpio32_63 22 0>, /* ETM_TRACE3, PDM2_CLK */
<55 0 &gpio32_63 23 0>, /* ETM_TRACECTL, PDM2_DATA */
<56 0 &gpio32_63 24 0>, /* PDM3_CLK */
<57 0 &gpio32_63 25 0>, /* PDM3_DATA */
<58 0 &gpio32_63 26 0>, /* COM_UART_RTS, UART0_RTS */
<59 0 &gpio32_63 27 0>, /* COM_UART_CTS, UART0_CTS */
<60 0 &gpio32_63 28 0>, /* COM_UART_TX, UART0_TX, IOM5_CS */
<61 0 &gpio32_63 29 0>, /* UART3_TX, IOM6_SPI_SCK, IOM6_I2C_SCL */
<62 0 &gpio32_63 30 0>, /* IOM6_SPI_MOSI, IOM6_I2C_SDA */
<63 0 &gpio32_63 31 0>, /* UART3_RX, IOM6_SPI_MISO */
<64 0 &gpio64_95 0 0>, /* MSPI0_D0, X16SPI_D0 */
<65 0 &gpio64_95 1 0>, /* MSPI0_D1, X16SPI_D1 */
<66 0 &gpio64_95 2 0>, /* MSPI0_D2, X16SPI_D2 */
<67 0 &gpio64_95 3 0>, /* MSPI0_D3, X16SPI_D3 */
<68 0 &gpio64_95 4 0>, /* MSPI0_D4, X16SPI_D4 */
<69 0 &gpio64_95 5 0>, /* MSPI0_D5, X16SPI_D5 */
<70 0 &gpio64_95 6 0>, /* MSPI0_D6, X16SPI_D6 */
<71 0 &gpio64_95 7 0>, /* MSPI0_D7, X16SPI_D7 */
<72 0 &gpio64_95 8 0>, /* IOM0_CS, MSPI0_SCK, X16SPI_SCK */
<73 0 &gpio64_95 9 0>, /* MSPI0_DQSDM, X16SPI_DQSDM */
<74 0 &gpio64_95 10 0>, /* MSPI2_D0 */
<75 0 &gpio64_95 11 0>, /* MSPI2_D1 */
<76 0 &gpio64_95 12 0>, /* MSPI2_D2 */
<77 0 &gpio64_95 13 0>, /* MSPI2_D3 */
<78 0 &gpio64_95 14 0>, /* MSPI2_D4 */
<79 0 &gpio64_95 15 0>, /* IOM4_CS, MSPI2_D5, SDIF_DAT4 */
<80 0 &gpio64_95 16 0>, /* MSPI2_D6, SDIF_DAT5 */
<81 0 &gpio64_95 17 0>, /* MSPI2_D7, SDIF_DAT6 */
<82 0 &gpio64_95 18 0>, /* MSPI2_D8, SDIF_DAT7 */
<83 0 &gpio64_95 19 0>, /* MSPI2_DQSDM, SDIF_CMD */
<84 0 &gpio64_95 20 0>, /* SDIF_DAT0 */
<85 0 &gpio64_95 21 0>, /* IOM3_CS, SDIF_DAT1 */
<86 0 &gpio64_95 22 0>, /* MSPI2_CE1, SDIF_DAT2 */
<87 0 &gpio64_95 23 0>, /* SDIF_DAT3 */
<88 0 &gpio64_95 24 0>, /* IOM7_CS, SDIF_CLKOUT */
<89 0 &gpio64_95 25 0>, /* MSPI1_CE0, X16SPI_CE0, X16SPI_CE1 */
<90 0 &gpio64_95 26 0>, /* LED0 */
<91 0 &gpio64_95 27 0>, /* MSPI1_CE1, */
<92 0 &gpio64_95 28 0>, /* See am_hal_pins.h file for further info */
<93 0 &gpio64_95 29 0>, /* See am_hal_pins.h file for further info */
<94 0 &gpio64_95 30 0>, /* See am_hal_pins.h file for further info */
<95 0 &gpio64_95 31 0>, /* See am_hal_pins.h file for further info */
<96 0 &gpio96_127 0 0>, /* See am_hal_pins.h file for further info */
<97 0 &gpio96_127 1 0>, /* See am_hal_pins.h file for further info */
<98 0 &gpio96_127 2 0>, /* See am_hal_pins.h file for further info */
<99 0 &gpio96_127 3 0>, /* See am_hal_pins.h file for further info */
<100 0 &gpio96_127 4 0>, /* See am_hal_pins.h file for further info */
<101 0 &gpio96_127 5 0>, /* VDDUSB0P9_SWITCH */
<102 0 &gpio96_127 6 0>, /* See am_hal_pins.h file for further info */
<103 0 &gpio96_127 7 0>, /* VDDUSB33_SWITCH */
<104 0 &gpio96_127 8 0>; /* VDD18_SWITCH */
};
};
spi1: &iom1_spi {};
``` | /content/code_sandbox/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,054 |
```yaml
board:
name: rak11720
vendor: rakwireless
socs:
- name: apollo3_blue
``` | /content/code_sandbox/boards/rak/rak11720/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
# Sercan Erat <sercanerat@gmail.com>
config BOARD_RAK11720
select SOC_APOLLO3_BLUE
``` | /content/code_sandbox/boards/rak/rak11720/Kconfig.rak11720 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```yaml
identifier: rak11720
name: RAK11720
type: mcu
arch: arm
ram: 384
flash: 976
toolchain:
- zephyr
- gnuarmemb
supported:
- uart
- watchdog
- counter
- gpio
- spi
- i2c
- lora
testing:
ignore_tags:
- net
vendor: rak
``` | /content/code_sandbox/boards/rak/rak11720/rak11720.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```unknown
/*
* Sercan Erat <sercanerat@gmail.com>
*/
/dts-v1/;
#include <ambiq/ambiq_apollo3_blue.dtsi>
#include <zephyr/dt-bindings/lora/sx126x.h>
#include "rak11720_apollo3-pinctrl.dtsi"
/ {
model = "RAKwireless RAK11720 WisBlock LPWAN Module";
compatible = "ambiq,rak11720";
chosen {
zephyr,itcm = &tcm;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-pipe = &uart0;
zephyr,flash-controller = &flash;
zephyr,bt_hci = &bt_hci_apollo;
};
aliases {
watchdog0 = &wdt0;
led0 = &blue_led;
led1 = &green_led;
lora0 = &lora;
};
leds {
compatible = "gpio-leds";
blue_led: led_2 {
gpios = <&gpio32_63 13 GPIO_ACTIVE_HIGH>;
label = "Blue LED";
};
green_led: led_1 {
gpios = <&gpio32_63 12 GPIO_ACTIVE_HIGH>;
label = "Green LED";
};
};
};
&flash0 {
erase-block-size = <8192>;
write-block-size = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set 16KB of storage at the end of the 976KB of flash */
storage_partition: partition@f0000 {
label = "storage";
reg = <0x000f0000 0x4000>;
};
};
};
&bleif {
pinctrl-0 = <&bleif_default>;
pinctrl-names = "default";
status = "okay";
};
&uart0 {
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
status = "okay";
};
&wdt0 {
status = "okay";
};
&i2c2 {
compatible = "ambiq,i2c";
pinctrl-0 = <&i2c2_default>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
};
&spi0 {
compatible = "ambiq,spi";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
clock-frequency = <DT_FREQ_M(1)>;
status = "okay";
};
&spi1 {
compatible = "ambiq,spi";
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
clock-frequency = <DT_FREQ_M(1)>;
cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,sx1262";
reg = <0>;
reset-gpios = <&gpio0_31 17 GPIO_ACTIVE_LOW>;
busy-gpios = <&gpio0_31 16 GPIO_ACTIVE_HIGH>;
dio1-gpios = <&gpio0_31 15 GPIO_ACTIVE_HIGH>;
antenna-enable-gpios = <&gpio0_31 18 GPIO_ACTIVE_LOW>;
dio2-tx-enable;
dio3-tcxo-voltage = <SX126X_DIO3_TCXO_3V3>;
tcxo-power-startup-delay-ms = <5>;
spi-max-frequency = <DT_FREQ_M(1)>;
};
};
&counter0 {
status = "okay";
};
&counter1 {
status = "okay";
};
&counter2 {
status = "okay";
};
&counter3 {
status = "okay";
};
&counter4 {
status = "okay";
};
&counter5 {
status = "okay";
};
&counter6 {
status = "okay";
};
&counter7 {
status = "okay";
};
&gpio0_31 {
status = "okay";
};
&gpio32_63 {
status = "okay";
};
``` | /content/code_sandbox/boards/rak/rak11720/rak11720.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 958 |
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