text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f429Xi.dtsi>
#include <st/f4/stm32f429zitx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32F429ZI-NUCLEO board";
compatible = "st,stm32f429zi-nucleo";
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,ccm = &ccm0;
zephyr,code-partition = &slot0_partition;
};
leds: leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
blue_led_1: led_2 {
gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
red_led_1: led_3 {
gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led_1;
led1 = &blue_led_1;
led2 = &red_led_1;
sw0 = &user_button;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <336>;
div-p = <2>;
div-q = <7>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(168)>; /* highest value to get a precise USB clock */
ahb-prescaler = <1>;
apb1-prescaler = <4>;
apb2-prescaler = <2>;
};
&adc1 {
pinctrl-0 = <&adc1_in0_pa0>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <2>;
status = "okay";
};
&die_temp {
status = "okay";
};
&dac1 {
status = "okay";
pinctrl-0 = <&dac_out1_pa4>;
pinctrl-names = "default";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart6 {
pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&timers1 {
st,prescaler = <10000>;
status = "okay";
pwm1: pwm {
status = "okay";
pinctrl-0 = <&tim1_ch3_pe13>;
pinctrl-names = "default";
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&iwdg {
status = "okay";
};
&rng {
status = "okay";
};
&dma2 {
status = "okay";
};
&mac {
status = "okay";
pinctrl-0 = <ð_mdc_pc1
ð_rxd0_pc4
ð_rxd1_pc5
ð_ref_clk_pa1
ð_mdio_pa2
ð_crs_dv_pa7
ð_tx_en_pg11
ð_txd0_pg13
ð_txd1_pb13>;
pinctrl-names = "default";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* 64KB for bootloader */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/* storage: 64KB for settings */
storage_partition: partition@10000 {
label = "storage";
reg = <0x00010000 DT_SIZE_K(64)>;
};
/* application image slot: 256KB */
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 DT_SIZE_K(256)>;
};
/* backup slot: 256KB */
slot1_partition: partition@60000 {
label = "image-1";
reg = <0x00060000 DT_SIZE_K(256)>;
};
/* swap slot: 128KB */
scratch_partition: partition@a0000 {
label = "image-scratch";
reg = <0x000a0000 DT_SIZE_K(128)>;
};
};
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_f429zi/nucleo_f429zi.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,561 |
```yaml
identifier: nucleo_f429zi
name: ST Nucleo F429ZI
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 192
flash: 2048
supported:
- arduino_gpio
- arduino_i2c
- arduino_spi
- netif:eth
- i2c
- spi
- gpio
- pwm
- counter
- usb_device
- watchdog
- adc
- dac
- dma
- nvs
- rtc
- usbd
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_f429zi/nucleo_f429zi.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 151 |
```yaml
board:
name: nucleo_f429zi
vendor: st
socs:
- name: stm32f429xx
``` | /content/code_sandbox/boards/st/nucleo_f429zi/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```restructuredtext
.. _nucleo_l496zg_board:
ST Nucleo L496ZG
################
Overview
********
The Nucleo L496ZG board features an ARM Cortex-M4 based STM32L496ZG MCU
with a wide range of connectivity support and configurations. Here are
some highlights of the Nucleo L476ZG board:
- STM32 microcontroller in QFP144 package
- USB OTG FS with Micro-AB connector
- Two types of extension resources:
- Arduino Uno V3 connectivity
- ST morpho extension pin headers for full access to all STM32 I/Os
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Flexible board power supply:
- USB VBUS or external source(3.3V, 5V, 7 - 12V)
- Power management access point
- 8 LEDs: user LEDs (LD1, LD2, LD3), communication LED (LD4), USB
power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8)
- 2 push buttons: USER and RESET
.. image:: img/nucleo_l496zg.jpg
:align: center
:alt: Nucleo L496ZG
More information about the board can be found at the `Nucleo L496ZG website`_.
Hardware
********
The STM32L496ZG SoC provides the following hardware capabilities:
- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode)
- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
- Clock Sources:
- 4 to 48 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
- Internal low-power 32 kHz RC ( |plusminus| 5%)
- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
LSE (better than |plusminus| 0.25 % accuracy)
- 3 PLLs for system clock, USB, audio, ADC
- RTC with HW calendar, alarms and calibration
- LCD 8 x 40 or 4 x 44 with step-up converter
- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
- 16x timers:
- 2x 16-bit advanced motor-control
- 2x 32-bit and 5x 16-bit general purpose
- 2x 16-bit basic
- 2x low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- SysTick timer
- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
- Memories
- Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection
- Up to 320 KB of SRAM including 64 KB with hardware parity check
- External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories
- Quad SPI memory interface
- 4x digital filters for sigma delta modulator
- Rich analog peripherals (independent supply)
- 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
- 2x 12-bit DAC, low-power sample and hold
- 2x operational amplifiers with built-in PGA
- 2x ultra-low-power comparators
- 20x communication interfaces
- USB OTG 2.0 full-speed, LPM and BCD
- 2x SAIs (serial audio interface)
- 4x I2C FM+(1 Mbit/s), SMBus/PMBus
- 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem)
- 1x LPUART
- 3x SPIs (4x SPIs with the Quad SPI)
- 2x CAN (2.0B Active) and SDMMC interface
- SWPMI single wire protocol master I/F
- IRTIM (Infrared interface)
- 14-channel DMA controller
- True random number generator
- CRC calculation unit, 96-bit unique ID
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
More information about STM32L496ZG can be found here:
- `STM32L496ZG on www.st.com`_
- `STM32L496 reference manual`_
Supported Features
==================
The Zephyr nucleo_l496zg board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | System Window Watchdog |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/nucleo_l496zg/nucleo_l496zg_defconfig`
Connections and IOs
===================
Nucleo L496ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
For more details please refer to `STM32 Nucleo-144 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_2 TX/RX : PD5/PD6
- UART_3 TX/RX : PD8/PD9
- LPUART_1 TX/RX : PG7/PG8
- PWM_1_CH1: PE9
- PWM_1_CH2: PE11
- PWM_1_CH3: PE13
- PWM_2_CH1: PA0
- I2C_1_SCL: PB8
- I2C_1_SDA: PB7
- SPI_1_NSS: PD14
- SPI_1_SCK: PA5
- SPI_1_MISO: PA6
- SPI_1_MOSI: PA7
- USER_PB : PC13
- LD1 : PC7
- LD2 : PB7
- LD3 : PB14
System Clock
------------
Nucleo L496ZG System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
driven by 16MHz high speed internal oscillator.
Serial Port
-----------
Nucleo L496ZG board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2.
Default settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``nucleo_l496zg`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Nucleo L496ZG board includes an ST-LINK/V2-1 embedded debug tool
interface. This interface is supported by the openocd version
included in the Zephyr SDK since v0.9.5.
Flashing an application to Nucleo L496ZG
----------------------------------------
Connect the Nucleo L496ZG to your host computer using the USB port.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your Nucleo board:
.. code-block:: console
$ minicom -D /dev/ttyUSB0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_l496zg
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! arm
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_l496zg
:maybe-skip-config:
:goals: debug
.. _Nucleo L496ZG website:
path_to_url
.. _STM32 Nucleo-144 board User Manual:
path_to_url
.. _STM32L496ZG on www.st.com:
path_to_url
.. _STM32L496 reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_l496zg/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,130 |
```unknown
# NUCLEO-144 F429ZI board configuration
if BOARD_NUCLEO_F429ZI
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
endif # BOARD_NUCLEO_F429ZI
``` | /content/code_sandbox/boards/st/nucleo_f429zi/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 3 0>, /* A0 */
<1 0 &gpioc 0 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpiof 3 0>, /* A3 */
<4 0 &gpiof 5 0>, /* A4 */
<5 0 &gpiof 10 0>, /* A5 */
<6 0 &gpiog 9 0>, /* D0 */
<7 0 &gpiog 14 0>, /* D1 */
<8 0 &gpiof 15 0>, /* D2 */
<9 0 &gpioe 13 0>, /* D3 */
<10 0 &gpiof 14 0>, /* D4 */
<11 0 &gpioe 11 0>, /* D5 */
<12 0 &gpioe 9 0>, /* D6 */
<13 0 &gpiof 13 0>, /* D7 */
<14 0 &gpiof 12 0>, /* D8 */
<15 0 &gpiod 15 0>, /* D9 */
<16 0 &gpiod 14 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
arduino_serial: &usart6 {};
``` | /content/code_sandbox/boards/st/nucleo_f429zi/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 497 |
```unknown
config BOARD_NUCLEO_F429ZI
select SOC_STM32F429XX
``` | /content/code_sandbox/boards/st/nucleo_f429zi/Kconfig.nucleo_f429zi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```ini
source [find board/st_nucleo_f4.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/nucleo_f429zi/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```cmake
board_runner_args(jlink "--device=STM32F072RB" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32f072b_disco/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config BOARD_STM32F072B_DISCO
select SOC_STM32F072XB
``` | /content/code_sandbox/boards/st/stm32f072b_disco/Kconfig.stm32f072b_disco | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
identifier: stm32f072b_disco
name: ST STM32F072B Discovery
type: mcu
arch: arm
ram: 16
flash: 128
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- i2c
- spi
- can
- watchdog
testing:
ignore_tags:
- net
- bluetooth
vendor: st
``` | /content/code_sandbox/boards/st/stm32f072b_disco/stm32f072b_disco.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```yaml
board:
name: stm32f072b_disco
vendor: st
socs:
- name: stm32f072xb
``` | /content/code_sandbox/boards/st/stm32f072b_disco/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# GPIO Controller
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
# STM32F072B-DISCO board configuration
if BOARD_STM32F072B_DISCO
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_STM32F072B_DISCO
``` | /content/code_sandbox/boards/st/stm32f072b_disco/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```restructuredtext
.. _nucleo_f429zi_board:
ST Nucleo F429ZI
################
Overview
********
The Nucleo F429ZI board features an ARM Cortex-M4 based STM32F429ZI MCU
with a wide range of connectivity support and configurations. Here are
some highlights of the Nucleo F429ZI board:
- STM32 microcontroller in LQFP144 package
- LSE crystal: 32.768 kHz crystal oscillator
- USB OTG
- Ethernet compliant with IEEE-802.3-2002
- Two types of extension resources:
- ST Zio connector including: support for Arduino* Uno V3 connectivity
(A0 to A5, D0 to D15) and additional signals exposing a wide range of
peripherals
- ST morpho extension pin headers for full access to all STM32 I/Os
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Flexible board power supply:
- 5 V from ST-LINK/V2-1 USB VBUS
- External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho
connectors, 5 V on ST morpho connector
- Three user LEDs
- Two push-buttons: USER and RESET
.. image:: img/nucleo_f429zi.jpg
:align: center
:alt: Nucleo F429ZI
More information about the board can be found at the `Nucleo F429ZI website`_.
Hardware
********
The Nucleo F429ZI provides the following hardware components:
- STM32F429ZIT6 in LQFP144 package
- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
- 180 MHz max CPU frequency
- VDD from 1.8 V to 3.6 V
- 2 MB Flash
- 256+4 KB SRAM including 64-Kbyte of core coupled memory
- GPIO with external interrupt capability
- 3x12-bit ADC with 24 channels
- 2x12-bit D/A converters
- RTC
- Advanced-control Timer
- General Purpose Timers (17)
- Watchdog Timers (2)
- USART/UART (4/4)
- I2C (3)
- SPI (6)
- SDIO
- 2xCAN
- USB 2.0 OTG FS with on-chip PHY
- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI
- 10/100 Ethernet MAC with dedicated DMA
- 8- to 14-bit parallel camera
- CRC calculation unit
- True random number generator
- DMA Controller
More information about STM32F429ZI can be found here:
- `STM32F429ZI on www.st.com`_
- `STM32F429 reference manual`_
- `STM32F429 datasheet`_
Supported Features
==================
The Zephyr nucleo_f429zi board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| ETHERNET | on-chip | Ethernet |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| USB | on-chip | usb |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| DAC | on-chip | DAC Controller |
+-----------+------------+-------------------------------------+
| DMA | on-chip | Direct Memory Access |
+-----------+------------+-------------------------------------+
| die-temp | on-chip | die temperature sensor |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in
:zephyr_file:`boards/st/nucleo_f429zi/nucleo_f429zi_defconfig`
Connections and IOs
===================
The Nucleo F429ZI Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
Available pins:
---------------
.. image:: img/nucleo_f429zi_cn8.jpg
:align: center
:alt: Nucleo F429ZI ZIO connectors (left)
.. image:: img/nucleo_f429zi_cn7.jpg
:align: center
:alt: Nucleo F429ZI ZIO connectors (right)
.. image:: img/nucleo_f429zi_cn11.jpg
:align: center
:alt: Nucleo F429ZI Morpho connectors (left)
.. image:: img/nucleo_f429zi_cn12.jpg
:align: center
:alt: Nucleo F429ZI Morpho connectors (right)
For more details please refer to `STM32 Nucleo-144 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
The Nucleo F429ZI board features a ST Zio connector (extended Arduino Uno V3)
and a ST morpho connector. Board is configured as follows
- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com)
- UART_6 TX/RX : PG14/PG9 (Arduino Serial)
- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C)
- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI)
- PWM_2_CH1 : PE13
- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13
- USER_PB : PC13
- LD1 : PB0
- LD2 : PB7
- LD3 : PB14
- USB DM : PA11
- USB DP : PA12
- ADC1 : PA0
System Clock
------------
The Nucleo F429ZI System Clock could be driven by an internal or external oscillator,
as well as by the main PLL clock. By default System clock is driven by PLL clock at 180MHz,
driven by an 8MHz high speed external clock.
Serial Port
-----------
The Nucleo F429ZI board has 8 UARTs. The Zephyr console output is assigned to UART3.
Default settings are 115200 8N1.
Programming and Debugging
*************************
The Nucleo F429ZI board includes an ST-LINK/V2-1 embedded debug tool interface.
This interface is supported by the openocd version included in Zephyr SDK.
Flash partitions for MCUBoot bootloader
***************************************
The on-board STM32F429ZI MCU has 2MBs of internal flash memory. To use `MCUboot`_,
define a :ref:`Zephyr partition table <flash_map_api>` for the flash memory in
its devicetree file ``nucleo_f429zi.dts``. As a reference, a partition table for
MCUBoot is already defined in the devicetree file, with these settings:
- `MCUBoot`_ bootloader partition takes 64K bytes.
- Zephyr settings partition takes 64K bytes.
- Application image takes 256K bytes in Slot 0 partition.
- Updating image takes another 256K bytes in Slot 1 partition.
- A scratch partition with 128K is required for image swap.
A specific application can adjust each partition size based on its needs.
.. _Nucleo F429ZI website:
path_to_url
.. _STM32 Nucleo-144 board User Manual:
path_to_url
.. _STM32F429ZI on www.st.com:
path_to_url
.. _STM32F429 reference manual:
path_to_url
.. _STM32F429 datasheet:
path_to_url
.. _MCUBoot:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_f429zi/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,933 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f0/stm32f072Xb.dtsi>
#include <st/f0/stm32f072r(8-b)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32F072B-DISCO board";
compatible = "st,stm32f072b-disco";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,canbus = &can1;
};
leds {
compatible = "gpio-leds";
red_up_led_3: led_3 {
gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
yellow_left_4: led_4 {
gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>;
label = "User LD4";
};
green_right_led_5: led_5 {
gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>;
label = "User LD5";
};
blue_low_led_6: led_6 {
gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>;
label = "User LD6";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
pwmleds: pwmleds {
compatible = "pwm-leds";
status = "disabled";
red_pwm_led: red_pwm_led {
pwms = <&pwm3 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
aliases {
led0 = &red_up_led_3;
led1 = &yellow_left_4;
led2 = &green_right_led_5;
led3 = &blue_low_led_6;
pwm-led0 = &red_pwm_led;
sw0 = &user_button;
watchdog0 = &iwdg;
};
};
&clk_hsi {
status = "okay";
};
&pll {
prediv = <1>;
mul = <6>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_sck_pb3 &spi1_miso_pb4 &spi1_mosi_pb5>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can_rx_pb8 &can_tx_pb9>;
pinctrl-names = "default";
status = "okay";
};
&iwdg {
status = "okay";
};
&timers3 {
st,prescaler = <10000>;
status = "okay";
pwm3: pwm {
status = "okay";
pinctrl-0 = <&tim3_ch1_pc6>;
pinctrl-names = "default";
};
};
``` | /content/code_sandbox/boards/st/stm32f072b_disco/stm32f072b_disco.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 924 |
```ini
source [find board/stm32f0discovery.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/stm32f072b_disco/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```restructuredtext
.. _stm32f072b_disco_board:
ST STM32F072B Discovery
#######################
Overview
********
The STM32F072B-DISCO Discovery kit features an ARM Cortex-M0 based STM32F072RB
MCU with everything required for beginners and experienced users to get
started quickly. Here are some highlights of the STM32F072B-DISCO board:
- STM32 microcontroller in LQFP64 package
- Extension header for LQFP64 I/Os for a quick connection to the prototyping
board and easy probing
- On-board ST-LINK/V2, debugger/programmer with SWD connector
- Board power supply: through USB bus or from an external 5 V supply voltage
- External application power supply: 3 V and 5 V
- Six LEDs:
- LD1 (red/green) for USB communication
- LD2 (red) for 3.3 V power on
- Four user LEDs: LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue)
- Two push-buttons: USER and RESET
- USB USER with Mini-B connector
- L3GD20, ST MEMS motion sensor, 3-axis digital output gyroscope
- One linear touch sensor or four touch keys
- RF EEprom daughter board connector
.. image:: img/stm32f072b_disco.jpg
:align: center
:alt: STM32F072B-DISCO
More information about the board can be found at the
`STM32F072B-DISCO website`_.
Hardware
********
STM32F072B-DISCO Discovery kit provides the following hardware components:
- STM32F072RBTT6 in LQFP64 package
- ARM |reg| 32-bit Cortex |reg| -M0 CPU
- 48 MHz max CPU frequency
- VDD from 2.0 V to 3.6 V
- 128 KB Flash
- 16 KB SRAM
- GPIO with external interrupt capability
- 12-bit ADC with 39 channels
- 12-bit D/A converters
- RTC
- General Purpose Timers (12)
- USART/UART (4)
- I2C (2)
- SPI (2)
- CAN
- USB 2.0 full speed interface
- DMA Controller
- 24 capacitive sensing channels for touchkey, linear and rotary touch sensors
More information about STM32F072RB can be found here:
- `STM32F072RB on www.st.com`_
- `STM32F072xB reference manual`_
Supported Features
==================
The Zephyr stm32f072b_disco board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c controller |
+-----------+------------+-------------------------------------+
| SPI | on-chip | SPI controller |
+-----------+------------+-------------------------------------+
| CAN | on-chip | CAN controller |
+-----------+------------+-------------------------------------+
.. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_.
Other hardware features are not yet supported in this Zephyr port.
The default configuration can be found in
:zephyr_file:`boards/st/stm32f072b_disco/stm32f072b_disco_defconfig`
Pin Mapping
===========
STM32F072B-DISCO Discovery kit has 6 GPIO controllers. These controllers are
responsible for pin muxing, input/output, pull-up, etc.
For more details please refer to `STM32F072B-DISCO board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1_TX : PB6
- UART_1_RX : PB7
- I2C1_SCL : PB8
- I2C1_SDA : PB9
- I2C2_SCL : PB10
- I2C2_SDA : PB11
- SPI1_SCK : PB3
- SPI1_MISO : PB4
- SPI1_MOSI : PB5
- USER_PB : PA0
- LD3 : PC6
- LD4 : PC8
- LD5 : PC9
- LD6 : PC7
- CAN_RX : PB8
- CAN_TX : PB9
System Clock
============
STM32F072B-DISCO System Clock could be driven by internal or external
oscillator, as well as main PLL clock. By default System clock is driven
by PLL clock at 72 MHz, driven by internal 8 MHz oscillator.
Serial Port
===========
STM32F072B-DISCO Discovery kit has up to 4 UARTs. The Zephyr console output
is assigned to UART 1. Default settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``stm32f072b_disco`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
STM32F072B-DISCO board includes an ST-LINK/V2 embedded debug tool interface.
This interface is supported by the openocd version included in the Zephyr SDK.
Flashing an application to STM32F072B-DISCO
-------------------------------------------
First, connect the STM32F072B-DISCO Discovery kit to your host computer using
the USB port to prepare it for flashing. Then build and flash your application.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32f072b_disco
:goals: build flash
Run a serial host program to connect with your board. A TTL(3.3V) serial
adapter is required.
.. code-block:: console
$ minicom -D /dev/<tty device>
Replace <tty_device> with the port where the serial adapter can be found.
For example, under Linux, /dev/ttyUSB0.
You should see the following message on the console:
.. code-block:: console
Hello World! arm
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32f072b_disco
:goals: debug
References
**********
.. target-notes::
.. _STM32F072B-DISCO website:
path_to_url
.. _STM32F072B-DISCO board User Manual:
path_to_url
.. _STM32F072RB on www.st.com:
path_to_url
.. _STM32F072xB reference manual:
path_to_url
.. _SK Pang CAN breakout board:
path_to_url
``` | /content/code_sandbox/boards/st/stm32f072b_disco/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,647 |
```cmake
if(CONFIG_STM32_MEMMAP)
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(stm32cubeprogrammer "--extload=MX25LM51245G_STM32H573I-DK-RevB-SFIx.stldr")
else()
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
endif()
board_runner_args(pyocd "--target=stm32h573iikx")
board_runner_args(openocd "--tcl-port=6666")
board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable")
board_runner_args(openocd "--no-halt")
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
# FIXME: official openocd runner not yet available.
``` | /content/code_sandbox/boards/st/stm32h573i_dk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 226 |
```unknown
config BOARD_STM32H573I_DK
select SOC_STM32H573XX
``` | /content/code_sandbox/boards/st/stm32h573i_dk/Kconfig.stm32h573i_dk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
identifier: stm32h573i_dk
name: ST STM32H573I Discovery Kit
type: mcu
arch: arm
toolchain:
- zephyr
ram: 640
flash: 2048
supported:
- arduino_gpio
- gpio
- uart
- watchdog
- entropy
- dma
- adc
- dac
- netif:eth
- pwm
- counter
- spi
- octospi
- can
- usb_device
- usb
- i2c
- rtc
- usbd
vendor: st
``` | /content/code_sandbox/boards/st/stm32h573i_dk/stm32h573i_dk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```yaml
board:
name: stm32h573i_dk
vendor: st
socs:
- name: stm32h573xx
``` | /content/code_sandbox/boards/st/stm32h573i_dk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32h573i_dk/stm32h573i_dk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
# STM32H573I DISCOVERY KIT board configuration
#
#
#
if BOARD_STM32H573I_DK
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
if DISK_DRIVER_SDMMC
config SDMMC_STM32_CLOCK_CHECK
default n
endif # DISK_DRIVER_SDMMC
endif # BOARD_STM32H573I_DK
``` | /content/code_sandbox/boards/st/stm32h573i_dk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpiob 0 0>, /* A0 */
<1 0 &gpioa 4 0>, /* A1 */
<2 0 &gpioa 0 0>, /* A2 */
<3 0 &gpioa 5 0>, /* A3 */
<4 0 &gpioa 6 0>, /* A4 */
<5 0 &gpiof 12 0>, /* A5 */
<6 0 &gpiob 11 0>, /* D0 */
<7 0 &gpiob 10 0>, /* D1 */
<8 0 &gpiog 15 0>, /* D2 */
<9 0 &gpiob 5 0>, /* D3 */
<10 0 &gpiog 4 0>, /* D4 */
<11 0 &gpioh 11 0>, /* D5 */
<12 0 &gpioh 10 0>, /* D6 */
<13 0 &gpiog 5 0>, /* D7 */
<14 0 &gpiog 8 0>, /* D8 */
<15 0 &gpioa 8 0>, /* D9 */
<16 0 &gpioa 3 0>, /* D10 */
<17 0 &gpiob 15 0>, /* D11 */
<18 0 &gpioi 2 0>, /* D12 */
<19 0 &gpioi 1 0>, /* D13 */
<20 0 &gpiob 7 0>, /* D14 */
<21 0 &gpiob 6 0>; /* D15 */
};
};
arduino_spi: &spi2 {};
arduino_i2c: &i2c1 {};
``` | /content/code_sandbox/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 492 |
```ini
source [find interface/stlink-dap.cfg]
source [find target/stm32h5x.cfg]
transport select "dapdirect_swd"
set CHIPNAME STM32H573IIKXQ
set BOARDNAME STM32H573I-DK
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0
# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
old_init
reset halt
}
``` | /content/code_sandbox/boards/st/stm32h573i_dk/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 155 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h5/stm32h573Xi.dtsi>
#include <st/h5/stm32h573iikxq-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
/ {
model = "STMicroelectronics STM32H573I DISCOVERY KIT board";
compatible = "st,stm32h573i-dk";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram1;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,canbus = &fdcan1;
};
leds {
compatible = "gpio-leds";
green_led_0: led_1 {
gpios = <&gpioi 9 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
orange_led_0: led_2 {
gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
red_led_0: led_3 {
gpios = <&gpiof 1 GPIO_ACTIVE_LOW>;
label = "User LD3";
};
blue_led_0: led_4 {
gpios = <&gpiof 4 GPIO_ACTIVE_LOW>;
label = "User LD4";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &blue_led_0;
sw0 = &user_button;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
ext_memory: memory@90000000 {
compatible = "zephyr,memory-region";
reg = <0x90000000 DT_SIZE_M(64)>;
zephyr,memory-region = "EXTMEM";
/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
};
};
&clk_hsi48 {
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
status = "okay";
};
&pll {
div-m = <5>;
mul-n = <96>;
div-p = <2>;
div-q = <6>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(240)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&timers2 {
st,prescaler = <10000>;
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch4_pa3>;
pinctrl-names = "default";
};
};
&timers3 {
st,prescaler = <10000>;
status = "okay";
pwm3: pwm {
status = "okay";
pinctrl-0 = <&tim3_ch2_pb5>;
pinctrl-names = "default";
};
};
&aes {
status = "okay";
};
&rng {
status = "okay";
};
&mac {
status = "okay";
pinctrl-0 = <ð_rxd0_pc4
ð_rxd1_pc5
ð_ref_clk_pa1
ð_crs_dv_pa7
ð_tx_en_pg11
ð_txd0_pg13
ð_txd1_pg12>;
pinctrl-names = "default";
};
&mdio {
status = "okay";
pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set the partitions with first MB to make use of the whole Bank1 */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(416)>;
};
slot1_partition: partition@78000 {
label = "image-1";
reg = <0x00078000 DT_SIZE_K(416)>;
};
scratch_partition: partition@e0000 {
label = "image-scratch";
reg = <0x000e0000 DT_SIZE_K(64)>;
};
/* Set 64KB of storage at the end of Bank1 */
storage_partition: partition@f0000 {
label = "storage";
reg = <0x000f0000 DT_SIZE_K(64)>;
};
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>,
<&rcc STM32_SRC_LSE RTC_SEL(1)>;
status = "okay";
};
&iwdg {
status = "okay";
};
&gpdma1 {
status = "okay";
};
&gpdma2 {
status = "okay";
};
&dac1 {
/* only 2 output channels : out1 on pa4 or out2 on pa5 */
pinctrl-0 = <&dac1_out1_pa4>; /* Arduino A1 */
pinctrl-names = "default";
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_inp6_pf12>; /* Arduino A5 */
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <6>;
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_nss_pa3 &spi2_sck_pi1
&spi2_miso_pi2 &spi2_mosi_pb15>;
pinctrl-names = "default";
status = "okay";
};
&fdcan1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
<&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
pinctrl-names = "default";
status = "okay";
};
&xspi1 {
pinctrl-0 = <&octospi1_io0_pb1 &octospi1_io1_pd12
&octospi1_io2_pc2 &octospi1_io3_pd13
&octospi1_io4_ph2 &octospi1_io5_ph3
&octospi1_io6_pg9 &octospi1_io7_pc0
&octospi1_clk_pf10 &octospi1_ncs_pg6
&octospi1_dqs_pb2>;
pinctrl-names = "default";
status = "okay";
mx25lm51245: ospi-nor-flash@90000000 {
compatible = "st,stm32-xspi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
spi-bus-width = <XSPI_OCTO_MODE>;
data-rate = <XSPI_DTR_TRANSFER>;
four-byte-opcodes;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "nor";
reg = <0x00000000 DT_SIZE_M(64)>;
};
};
};
};
&sdmmc1 {
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
pinctrl-names = "default";
cd-gpios = <&gpioh 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
zephyr_udc0: &usb {
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&die_temp {
status = "okay";
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/stm32h573i_dk/stm32h573i_dk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,284 |
```unknown
/*
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/gpio/st-morpho-header.h>
/ {
st_morpho_header: st-morpho-header {
compatible = "st-morpho-header";
#gpio-cells = <2>;
gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
<ST_MORPHO_L_2 0 &gpioc 11 0>,
<ST_MORPHO_L_3 0 &gpioc 12 0>,
<ST_MORPHO_L_4 0 &gpiod 2 0>,
<ST_MORPHO_L_13 0 &gpioa 13 0>,
<ST_MORPHO_L_15 0 &gpioa 14 0>,
<ST_MORPHO_L_17 0 &gpioa 15 0>,
<ST_MORPHO_L_21 0 &gpiob 7 0>,
<ST_MORPHO_L_23 0 &gpioc 13 0>,
<ST_MORPHO_L_25 0 &gpioc 14 0>,
<ST_MORPHO_L_27 0 &gpioc 15 0>,
<ST_MORPHO_L_28 0 &gpioa 0 0>,
<ST_MORPHO_L_29 0 &gpioh 0 0>,
<ST_MORPHO_L_30 0 &gpioa 1 0>,
<ST_MORPHO_L_31 0 &gpioh 1 0>,
<ST_MORPHO_L_32 0 &gpioa 4 0>,
<ST_MORPHO_L_34 0 &gpiob 0 0>,
<ST_MORPHO_L_35 0 &gpioc 2 0>,
<ST_MORPHO_L_36 0 &gpioc 1 0>, /* SB56=ON, SB46=OFF */
<ST_MORPHO_L_37 0 &gpioc 3 0>,
<ST_MORPHO_L_38 0 &gpioc 0 0>, /* SB51=ON, SB52=OFF */
<ST_MORPHO_R_1 0 &gpioc 9 0>,
<ST_MORPHO_R_2 0 &gpioc 8 0>,
<ST_MORPHO_R_3 0 &gpiob 8 0>,
<ST_MORPHO_R_4 0 &gpioc 6 0>,
<ST_MORPHO_R_5 0 &gpiob 9 0>,
<ST_MORPHO_R_6 0 &gpioc 5 0>,
<ST_MORPHO_R_11 0 &gpioa 5 0>,
<ST_MORPHO_R_12 0 &gpioa 12 0>,
<ST_MORPHO_R_13 0 &gpioa 6 0>,
<ST_MORPHO_R_14 0 &gpioa 11 0>,
<ST_MORPHO_R_15 0 &gpioa 7 0>,
<ST_MORPHO_R_16 0 &gpiob 12 0>,
<ST_MORPHO_R_17 0 &gpiob 6 0>,
<ST_MORPHO_R_18 0 &gpiob 11 0>,
<ST_MORPHO_R_19 0 &gpioc 7 0>,
<ST_MORPHO_R_21 0 &gpioa 9 0>,
<ST_MORPHO_R_22 0 &gpiob 2 0>,
<ST_MORPHO_R_23 0 &gpioa 8 0>,
<ST_MORPHO_R_24 0 &gpiob 1 0>,
<ST_MORPHO_R_25 0 &gpiob 10 0>,
<ST_MORPHO_R_26 0 &gpiob 15 0>,
<ST_MORPHO_R_27 0 &gpiob 4 0>,
<ST_MORPHO_R_28 0 &gpiob 14 0>,
<ST_MORPHO_R_29 0 &gpiob 5 0>,
<ST_MORPHO_R_30 0 &gpiob 13 0>,
<ST_MORPHO_R_31 0 &gpiob 3 0>,
<ST_MORPHO_R_33 0 &gpioa 10 0>,
<ST_MORPHO_R_34 0 &gpioc 4 0>,
<ST_MORPHO_R_35 0 &gpioa 2 0>,
<ST_MORPHO_R_37 0 &gpioa 3 0>;
};
};
``` | /content/code_sandbox/boards/st/nucleo_l452re/st_morpho_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,183 |
```cmake
board_runner_args(jlink "--device=STM32L452RE" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_l452re/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config BOARD_NUCLEO_L452RE
select SOC_STM32L452XX
``` | /content/code_sandbox/boards/st/nucleo_l452re/Kconfig.nucleo_l452re | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
/*
*
*/
/dts-v1/;
#include "nucleo_l452re_common.dtsi"
#include <st/l4/stm32l452retxp-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
/ {
model = "STMicroelectronics STM32L452RE-P-NUCLEO board";
compatible = "st,stm32l452re-nucleo";
leds: leds {
compatible = "gpio-leds";
green_led: led_0 {
gpios = <&gpiob 13 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
aliases {
led0 = &green_led;
};
};
``` | /content/code_sandbox/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```yaml
identifier: nucleo_l452re/stm32l452xx/p
name: ST Nucleo L452RE-P
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 160
flash: 512
supported:
- nvs
- pwm
- can
- counter
- spi
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_l452re/nucleo_l452re_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```yaml
board:
name: nucleo_l452re
vendor: st
socs:
- name: stm32l452xx
variants:
- name: p
``` | /content/code_sandbox/boards/st/nucleo_l452re/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```unknown
# STM32L452RE Nucleo board configuration
#
#
if BOARD_NUCLEO_L452RE
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_NUCLEO_L452RE
``` | /content/code_sandbox/boards/st/nucleo_l452re/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```restructuredtext
.. _stm32h573i_dk_board:
ST STM32H573I-DK Discovery
##########################
Overview
********
The STM32H573I-DK Discovery kit is designed as a complete demonstration and
development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based
STM32H573IIK3Q microcontroller with TrustZone |reg|. Here are some highlights of
the STM32H573I-DK Discovery board:
- STM32H573IIK3Q microcontroller featuring 2 Mbytes of Flash memory and 640 Kbytes of SRAM in 176-pin BGA package
- 1.54-inch 240x240 pixels TFT-LCD with LED backlight and touch panel
- USB Type-C |trade| Host and device with USB power-delivery controller
- SAI Audio DAC stereo with one audio jacks for input/output,
- ST MEMS digital microphone with PDM interface
- Octo-SPI interface connected to 512Mbit Octo-SPI NORFlash memory device (MX25LM51245GXDI00 from MACRONIX)
- 10/100-Mbit Ethernet,
- microSD |trade|
- A WiFi add-on board
- Board connectors
- STMod+ expansion connector with fan-out expansion board for WiFi |reg|, Grove and mikroBUS |trade| compatible connectors
- Pmod |trade| expansion connector
- Audio MEMS daughterboard expansion connector
- ARDUINO |reg| Uno V3 expansion connector
- Flexible power-supply options
- ST-LINK
- USB VBUS
- external sources
- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability:
- mass storage
- Virtual COM port
- debug port
- 4 user LEDs
- User and reset push-buttons
.. image:: img/stm32h573i_dk.jpg
:align: center
:alt: STM32H573I-DK Discovery
More information about the board can be found at the `STM32H573I-DK Discovery website`_.
Hardware
********
The STM32H573xx devices are an high-performance microcontrollers family (STM32H5
Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core.
They operate at a frequency of up to 250 MHz.
- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU.
- Performance benchmark:
- 375 DMPIS/MHz (Dhrystone 2.1)
- Security
- Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension
- Up to 8 configurable SAU regions
- TrustZone |reg| aware and securable peripherals
- Flexible lifecycle scheme with secure debug authentication
- Preconfigured immutable root of trust (ST-iROT)
- SFI (secure firmware installation)
- Secure data storage with hardware unique key (HUK)
- Secure firmware upgrade support with TF-M
- 2x AES coprocessors including one with DPA resistance
- Public key accelerator, DPA resistant
- On-the-fly decryption of Octo-SPI external memories
- HASH hardware accelerator
- True random number generator, NIST SP800-90B compliant
- 96-bit unique ID
- Active tampers
- True Random Number Generator (RNG) NIST SP800-90B compliant
- Clock management:
- 25 MHz crystal oscillator (HSE)
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 64 MHz (HSI) trimmable by software
- Internal low-power 32 kHz RC (LSI)( |plusminus| 5%)
- Internal 4 MHz oscillator (CSI), trimmable by software
- Internal 48 MHz (HSI48) with recovery system
- 3 PLLs for system clock, USB, audio, ADC
- Power management
- Embedded regulator (LDO) with three configurable range output to supply the digital circuitry
- Embedded SMPS step-down converter
- RTC with HW calendar, alarms and calibration
- Up to 139 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V
- Up to 16 timers and 2 watchdogs
- 12x 16-bit
- 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
- 6x 16-bit low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- 2x SysTick timer
- Memories
- Up to 2 MB Flash, 2 banks read-while-write
- 1 Kbyte OTP (one-time programmable)
- 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC
- 4 Kbytes of backup SRAM available in the lowest power modes
- Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
- 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats
- 2x SD/SDIO/MMC interfaces
- Rich analog peripherals (independent supply)
- 2x 12-bit ADC with up to 5 MSPS in 12-bit
- 2x 12-bit D/A converters
- 1x Digital temperature sensor
- 34x communication interfaces
- 1x USB Type-C / USB power-delivery controller
- 1x USB 2.0 full-speed host and device
- 4x I2C FM+ interfaces (SMBus/PMBus)
- 1x I3C interface
- 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control)
- 1x LP UART
- 6x SPIs including 3 muxed with full-duplex I2S
- 5x additional SPI from 5x USART when configured in Synchronous mode
- 2x SAI
- 2x FDCAN
- 1x SDMMC interface
- 2x 16 channel DMA controllers
- 1x 8- to 14- bit camera interface
- 1x HDMI-CEC
- 1x Ethernel MAC interface with DMA controller
- 1x 16-bit parallel slave synchronous-interface
- CORDIC for trigonometric functions acceleration
- FMAC (filter mathematical accelerator)
- CRC calculation unit
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
More information about STM32H573 can be found here:
- `STM32H573 on www.st.com`_
- `STM32H573 reference manual`_
Supported Features
==================
The Zephyr STM32H573I_DK board configuration supports the following
hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| DAC | on-chip | DAC Controller |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+
| PWM | on-chip | PWM |
+-----------+------------+-------------------------------------+
| RTC | on-chip | Real Time Clock |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c bus |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi bus |
+-----------+------------+-------------------------------------+
| OCTOSPI | on-chip | octospi |
+-----------+------------+-------------------------------------+
| CAN | on-chip | can bus |
+-----------+------------+-------------------------------------+
| AES | on-chip | crypto |
+-----------+------------+-------------------------------------+
| SDMMC | on-chip | disk access |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB full-speed host/device bus |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig and dts files:
- Secure target:
- :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk_defconfig`
- :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk.dts`
Connections and IOs
===================
STM32H573I-DK Discovery Board has 9 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
For more details please refer to `STM32H573I-DK Discovery board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- USART_1 TX/RX : PA9/PA10 (VCP)
- USART_3 TX/RX : PB11/PB10 (Arduino USART3)
- USER_PB : PC13
- LD1 (green) : PI9
- DAC1 channel 1 output : PA4
- ADC1 channel 6 input : PF12
System Clock
------------
STM32H573I-DK System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at
240MHz, driven by 25MHz external oscillator (HSE).
Serial Port
-----------
STM32H573I-DK Discovery board has 3 U(S)ARTs. The Zephyr console output is
assigned to USART1. Default settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``stm32h573i_dk`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
OpenOCD Support
===============
For now, openocd support for stm32h5 is not available on upstream OpenOCD.
You can check `OpenOCD official Github mirror`_.
In order to use it though, you should clone from the cutomized
`STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines.
Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in
:zephyr_file:`boards/st/stm32h573i_dk/board.cmake` to point the build
to the paths of the OpenOCD binary and its scripts, before
including the common openocd.board.cmake file:
.. code-block:: none
set(OPENOCD "<path_to_openocd_repo>/src/openocd" CACHE FILEPATH "" FORCE)
set(OPENOCD_DEFAULT_PATH <path_to_opneocd_repo>/tcl)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
Flashing
========
STM32H573I-DK Discovery board includes an ST-LINK/V3E embedded debug tool
interface. Support is available on STM32CubeProgrammer V2.13.0.
Alternatively, pyocd or jlink via an external probe can also be used to flash
and debug the board if west is told to use it as runner, which can be done by
passing either or ``-r pyocd``, or ``-r jlink``.
For pyocd additional target information needs to be installed.
This can be done by executing the following commands.
.. code-block:: console
$ pyocd pack --update
$ pyocd pack --install stm32h5
Alternatively, the openocd interface will be supported by a next openocd version.
When available, OpenOCD could be used in the same way as other tools.
Flashing an application to STM32H573I-DK Discovery
--------------------------------------------------
Connect the STM32H573I-DK Discovery to your host computer using the USB port.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your Nucleo board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h573i_dk
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! stm32h573i_dk
Debugging
=========
Waiting for openocd support, debugging could be performed with pyocd which
requires to enable "pack" support with the following pyocd command:
.. code-block:: console
$ pyocd pack --update
$ pyocd pack --install stm32h5
Once installed, you can debug an application in the usual way. Here is an
example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h573i_dk
:maybe-skip-config:
:goals: debug
.. _STM32H573I-DK Discovery website:
path_to_url
.. _STM32H573I-DK Discovery board User Manual:
path_to_url
.. _STM32H573 on www.st.com:
path_to_url
.. _STM32H573 reference manual:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
.. _OpenOCD official Github mirror:
path_to_url
.. _STMicroelectronics OpenOCD Github:
path_to_url
``` | /content/code_sandbox/boards/st/stm32h573i_dk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,248 |
```unknown
/*
*
*/
/dts-v1/;
#include "nucleo_l452re_common.dtsi"
#include <st/l4/stm32l452r(c-e)tx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include "st_morpho_connector.dtsi"
/ {
model = "STMicroelectronics STM32L452RE-NUCLEO board";
compatible = "st,stm32l452re-nucleo";
leds: leds {
compatible = "gpio-leds";
green_led: led_0 {
gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
aliases {
led0 = &green_led;
};
};
``` | /content/code_sandbox/boards/st/nucleo_l452re/nucleo_l452re.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 165 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 0 0>, /* A0 */
<1 0 &gpioa 1 0>, /* A1 */
<2 0 &gpioa 4 0>, /* A2 */
<3 0 &gpiob 0 0>, /* A3 */
<4 0 &gpioc 1 0>, /* A4 */
<5 0 &gpioc 0 0>, /* A5 */
<6 0 &gpioa 3 0>, /* D0 */
<7 0 &gpioa 2 0>, /* D1 */
<8 0 &gpioa 10 0>, /* D2 */
<9 0 &gpiob 3 0>, /* D3 */
<10 0 &gpiob 5 0>, /* D4 */
<11 0 &gpiob 4 0>, /* D5 */
<12 0 &gpiob 10 0>, /* D6 */
<13 0 &gpioa 8 0>, /* D7 */
<14 0 &gpioa 9 0>, /* D8 */
<15 0 &gpioc 7 0>, /* D9 */
<16 0 &gpiob 6 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
``` | /content/code_sandbox/boards/st/nucleo_l452re/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 492 |
```yaml
identifier: nucleo_l452re
name: ST Nucleo L452RE
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 160
flash: 512
supported:
- nvs
- pwm
- can
- counter
- spi
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_l452re/nucleo_l452re.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32l4x.cfg]
reset_config srst_only
``` | /content/code_sandbox/boards/st/nucleo_l452re/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/l4/stm32l452Xe.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32L452RE-NUCLEO board";
compatible = "st,stm32l452re-nucleo";
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,canbus = &can1;
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
sw0 = &user_button;
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <20>;
div-p = <7>;
div-q = <2>;
div-r = <4>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(80)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpiob 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb7>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";
};
&timers2 {
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch1_pa0>;
pinctrl-names = "default";
};
};
&can1 {
pinctrl-0 = <&can1_rx_pa11 &can1_tx_pa12>;
pinctrl-names = "default";
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* Reserve the final 16 KiB for file system partition
*/
storage_partition: partition@7c000 {
label = "storage";
reg = <0x0007c000 0x00008000>;
};
};
};
``` | /content/code_sandbox/boards/st/nucleo_l452re/nucleo_l452re_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 785 |
```cmake
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(openocd "--tcl-port=6666")
board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable")
board_runner_args(openocd "--no-halt")
board_runner_args(pyocd "--target=stm32u5a5zjtx")
board_runner_args(jlink "--device=STM32U5A5ZJ" "--reset-after-load")
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 180 |
```yaml
identifier: nucleo_u5a5zj_q
name: ST Nucleo U5A5ZJ Q
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
supported:
- arduino_gpio
- arduino_i2c
- arduino_serial
- arduino_spi
- can
- adc
- dac
- gpio
- i2c
- spi
- usart
- watchdog
- backup_sram
- dma
- rtc
ram: 2450
flash: 4096
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 141 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable clock
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```yaml
board:
name: nucleo_u5a5zj_q
vendor: st
socs:
- name: stm32u5a5xx
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
config BOARD_NUCLEO_U5A5ZJ_Q
select SOC_STM32U5A5XX
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/Kconfig.nucleo_u5a5zj_q | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
/*
*
*/
/dts-v1/;
#include "nucleo_u5a5zj_q-common.dtsi"
/ {
model = "STMicroelectronics STM32U5A5ZJ-NUCLEO-Q board";
compatible = "st,stm32u5a5zj-nucleo-q";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,canbus = &fdcan1;
zephyr,code-partition = &slot0_partition;
};
aliases {
led0 = &blue_led_1;
sw0 = &user_button;
pwm-led0 = &pwm_led_1;
pwm-led1 = &pwm_led_2;
watchdog0 = &iwdg;
volt-sensor0 = &vref1;
volt-sensor1 = &vbat4;
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* Following flash partition is dedicated to the use of nucleo_u5a5zj_q
* with TZEN=0 (so w/o TFM).
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(1952)>;
};
slot1_partition: partition@1f8000 {
label = "image-1";
reg = <0x001f8000 DT_SIZE_K(1960)>;
};
storage_partition: partition@3e2000 {
label = "storage";
reg = <0x003e2000 DT_SIZE_K(120)>;
};
};
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&gpdma1 {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 545 |
```restructuredtext
.. _nucleo_l452re_board:
ST Nucleo L452RE
################
Overview
********
The Nucleo L452RE(-P) boards feature an ARM Cortex-M4 based STM32L452RE MCU
with a wide range of connectivity support and configurations. There are two variants:
- ST Nucleo L452RE
- ST Nucleo L452RE-P
Here some highlights of these boards:
- STM32 microcontroller in LQFP64 package
- Arduino Uno V3 connectivity
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Flexible board power supply:
- USB VBUS or external source(3.3V, 5V, 7 - 12V)
- Power management access point
- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3)
- One push-button: RESET
.. image:: img/nucleo_l452re_p.jpg
:align: center
:alt: Nucleo L452RE-P
The main difference between the ST Nucleo L452RE and the L452RE-P (note the missing
"-P" at the end) lays in the External Switched Mode Power Supply (SMPS) included in
the P series.
More information about the boards can be found at the `Nucleo L452RE website`_ and
the `Nucleo L452RE-P website`_.
Hardware
********
The STM32L452RE SoC provides the following hardware IPs:
- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84
|micro| A/MHz run mode)
- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz,
100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
- Clock Sources:
- 4 to 48 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
- Internal low-power 32 kHz RC ( |plusminus| 5%)
- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
LSE (better than |plusminus| 0.25 % accuracy)
- 2 PLLs for system clock, USB, audio, ADC
- RTC with HW calendar, alarms and calibration
- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors
- 12x timers:
- 1x 16-bit advanced motor-control
- 1x 32-bit and 3x 16-bit general purpose
- 2x 16-bit basic
- 2x low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- SysTick timer
- Up to 26 fast I/Os, most 5 V-tolerant
- Memories
- Up to 512 KB single bank Flash, proprietary code readout protection
- 160 KB of SRAM including 32 KB with hardware parity check
- Quad SPI memory interface
- Rich analog peripherals (independent supply)
- 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200
|micro| A/MSPS
- 2x 12-bit DAC, low-power sample and hold
- 1x operational amplifiers with built-in PGA
- 2x ultra-low-power comparators
- 17x communication interfaces
- USB 2.0 full-speed crystal less solution with LPM and BCD
- 1x SAI (serial audio interface)
- 4x I2C FM+(1 Mbit/s), SMBus/PMBus
- 3x USARTs (ISO 7816, LIN, IrDA, modem)
- 1x UART (LIN, IrDA, modem)
- 1x LPUART (Stop 2 wake-up)
- 3x SPIs (and 1x Quad SPI)
- CAN (2.0B Active) and SDMMC interface
- IRTIM (Infrared interface)
- 14-channel DMA controller
- True random number generator
- CRC calculation unit, 96-bit unique ID
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell*
More information about STM32L452RE can be found here:
- `STM32L452RE on www.st.com`_
- `STM32L452 reference manual`_
Supported Features
==================
The Zephyr nucleo_l452re board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| CAN | on-chip | can |
+-----------+------------+-------------------------------------+
.. note:: CAN feature requires CAN transceiver
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/nucleo_l452re/nucleo_l452re_defconfig`
And for Nucleo L452RE-P in this defconfig file:
:zephyr_file:`boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig`
Connections and IOs
===================
Nucleo L452RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
Available pins:
---------------
.. image:: img/nucleo_l452re_pinout.jpg
:align: center
:alt: Nucleo L452RE Pinout
.. image:: img/nucleo_l452re_p_pinout.jpg
:align: center
:alt: Nucleo L452RE-P Pinout
For more details please refer to `ST Nucleo L452RE User Manual`_ or
`ST Nucleo L452RE-P User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1_TX : PA9
- UART_1_RX : PA10
- UART_2_TX : PA2
- UART_2_RX : PA3
- I2C_1_SCL : PB8
- I2C_1_SDA : PB7
- PWM_2_CH1 : PA0
- SPI_NSS : PB6
- SPI_SCK : PA5
- SPI_MISO : PA6
- SPI_MOSI : PA7
- CAN_TX : PA11
- CAN_RX : PA12
- LD2 : PA5
System Clock
------------
Nucleo L452RE System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
driven by 16MHz high speed internal oscillator.
Serial Port
-----------
Nucleo L452RE board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2.
Default settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``nucleo_l452re`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Nucleo L452RE board includes an ST-LINK/V2-1 embedded debug tool
interface. This interface is supported by the openocd version
included in the Zephyr SDK since v0.9.2.
Flashing an application to Nucleo L452RE
----------------------------------------
Connect the Nucleo L452RE to your host computer using the USB port,
then run a serial host program to connect with your Nucleo board.
.. code-block:: console
$ minicom -D /dev/ttyACM0
Now build and flash an application. Here is an example for
:ref:`hello_world`.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_l452re
:goals: build flash
For Nucleo L452RE-P, use this command instead:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_l452re/stm32l452xx/p
:goals: build flash
You should see the following message on the console:
.. code-block:: console
$ Hello World! arm
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_l452re
:maybe-skip-config:
:goals: debug
.. _Nucleo L452RE website:
path_to_url
.. _Nucleo L452RE-P website:
path_to_url
.. _ST Nucleo L452RE User Manual:
path_to_url
.. _ST Nucleo L452RE-P User Manual:
path_to_url
.. _STM32L452RE on www.st.com:
path_to_url
.. _STM32L452 reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_l452re/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,183 |
```unknown
/*
*
*/
#include <st/u5/stm32u5a5Xj.dtsi>
#include <st/u5/stm32u5a5zjtxq-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
leds: leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
blue_led_1: led_2 {
gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
red_led_1: led_3 {
gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
pwmleds: pwmleds {
compatible = "pwm-leds";
status = "disabled";
pwm_led_1: green_led_1 {
pwms = <&pwm3 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "green led";
};
pwm_led_2: blue_led_1 {
pwms = <&pwm4 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "blue led";
};
};
};
&clk_hsi48 {
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_msis {
status = "okay";
msi-range = <4>;
msi-pll-mode;
};
&pll1 {
div-m = <1>;
mul-n = <80>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_msis>;
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pg7 &lpuart1_rx_pg8>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_nss_pe12 &spi1_sck_pa5
&spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&dac1 {
pinctrl-0 = <&dac1_out1_pa4>;
pinctrl-names = "default";
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in1_pc0>;
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&adc4 {
pinctrl-0 = <&adc4_in18_pb0>;
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&timers3 {
st,prescaler = <10000>;
status = "okay";
pwm3: pwm {
pinctrl-0 = <&tim3_ch2_pc7>;
pinctrl-names = "default";
status = "okay";
};
};
&timers4 {
st,prescaler = <10000>;
status = "okay";
pwm4: pwm {
pinctrl-0 = <&tim4_ch2_pb7>;
pinctrl-names = "default";
status = "okay";
};
};
&iwdg {
status = "okay";
};
&rng {
status = "okay";
};
&fdcan1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
<&rcc STM32_SRC_PLL1_Q FDCAN1_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
pinctrl-names = "default";
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>,
<&rcc STM32_SRC_LSE RTC_SEL(1)>;
status = "okay";
};
&vref1 {
status = "okay";
};
&vbat4 {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,218 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 3 0>, /* A0 */
<1 0 &gpioa 2 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpiob 0 0>, /* A3 */
<4 0 &gpioc 1 0>, /* A4 */
<5 0 &gpioc 0 0>, /* A5 */
<6 0 &gpiog 8 0>, /* D0 */
<7 0 &gpiog 7 0>, /* D1 */
<8 0 &gpiof 15 0>, /* D2 */
<9 0 &gpioe 13 0>, /* D3 */
<10 0 &gpiof 14 0>, /* D4 */
<11 0 &gpioe 11 0>, /* D5 */
<12 0 &gpioe 9 0>, /* D6 */
<13 0 &gpiof 13 0>, /* D7 */
<14 0 &gpiof 12 0>, /* D8 */
<15 0 &gpiod 15 0>, /* D9 */
<16 0 &gpiod 14 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
arduino_serial: &lpuart1 {};
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 500 |
```ini
source [find interface/stlink-dap.cfg]
set WORKAREASIZE 0x8000
transport select "dapdirect_swd"
set CHIPNAME STM32U5A5ZJTxQ
set BOARDNAME NUCLEO-U5A5ZJ-Q
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# STlink Debug clock frequency
set CLOCK_FREQ 8000
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0
# ACCESS PORT NUMBER
set AP_NUM 0
# GDB PORT
set GDB_PORT 3333
# BCTM CPU variables
source [find target/stm32u5x.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 258 |
```cmake
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(jlink "--device=STM32L475VG" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
``` | /content/code_sandbox/boards/st/disco_l475_iot1/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```yaml
identifier: disco_l475_iot1
name: ST Disco L475 IOT01 (B-L475E-IOT01A)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- arduino_i2c
- i2c
- hts221
- lps22hb
- lsm6dsl
- pwm
- counter
- gpio
- ble
- spi
- nvs
- vl53l0x
- watchdog
- adc
- dac
- qspi
- dma
- rtc
- usbd
ram: 96
flash: 1024
vendor: st
``` | /content/code_sandbox/boards/st/disco_l475_iot1/disco_l475_iot1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 179 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/l4/stm32l475Xg.dtsi>
#include <st/l4/stm32l475v(c-e-g)tx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics B-L475E-IOT01Ax board";
compatible = "st,stm32l475-disco-iot";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,flash-controller = &mx25r6435f;
zephyr,bt-c2h-uart = &usart1;
zephyr,bt-hci = &hci_spi;
};
leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
green_led_2: led_2 {
gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button_0 {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
pwmleds: pwmleds {
compatible = "pwm-leds";
status = "disabled";
/*
* green_pwm_1 is connected to CN1 pin 2 not LD1, since LD1
* shares a pin with the Arduino SPI SCL line.
*/
green_pwm_1: green_led_1 {
pwms = <&pwm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "green LD1";
};
green_pwm_2: green_led_2 {
pwms = <&pwm15 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "green LD2";
};
};
aliases {
led0 = &green_led_2;
led1 = &green_led_1;
pwm-led0 = &green_pwm_2;
pwm-led1 = &green_pwm_1;
sw0 = &user_button;
eswifi0 = &wifi0;
watchdog0 = &iwdg;
accel0 = &lsm6dsl;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_lsi {
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&clk_msi {
status = "okay";
msi-pll-mode;
msi-range = <11>; /* 48MHz USB bus clk */
};
&pll {
div-m = <1>;
mul-n = <20>;
div-p = <7>;
div-q = <2>;
div-r = <4>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(80)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&usart1 {
current-speed = <115200>;
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
pinctrl-names = "default";
status = "okay";
};
&uart4 {
pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pa1>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
lis3mdl-magn@1e {
compatible = "st,lis3mdl-magn";
reg = <0x1e>;
};
hts221@5f {
compatible = "st,hts221";
reg = <0x5f>;
drdy-gpios = <&gpiod 15 GPIO_ACTIVE_HIGH>;
};
lps22hb-press@5d {
compatible = "st,lps22hb-press";
reg = <0x5d>;
};
lsm6dsl: lsm6dsl@6a {
compatible = "st,lsm6dsl";
reg = <0x6a>;
irq-gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
};
vl53l0x@29 {
compatible = "st,vl53l0x";
reg = <0x29>;
xshut-gpios = <&gpioc 6 GPIO_ACTIVE_LOW>;
};
};
&i2c3 {
pinctrl-0 = <&i2c3_scl_pc0 &i2c3_sda_pc1>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpioa 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
&spi3_miso_pc11 { slew-rate = "very-high-speed"; };
&spi3 {
status = "okay";
pinctrl-0 = <&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12>;
pinctrl-names = "default";
cs-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>,
<&gpioe 0 GPIO_ACTIVE_LOW>;
hci_spi: spbtle-rf@0 {
compatible = "st,hci-spi-v1";
reg = <0>;
reset-gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpioe 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
spi-max-frequency = <DT_FREQ_M(2)>;
spi-hold-cs;
};
wifi0: ism43362@1 {
compatible = "inventek,eswifi";
spi-max-frequency = <2000000>;
reg = <1>;
resetn-gpios = <&gpioe 8 GPIO_ACTIVE_HIGH>;
boot0-gpios = <&gpiob 12 GPIO_ACTIVE_HIGH>;
wakeup-gpios = <&gpiob 13 GPIO_ACTIVE_HIGH>;
data-gpios = <&gpioe 1 GPIO_ACTIVE_HIGH>;
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/*
* The flash starting at offset 0x10000 and ending at
* offset 0x1ffff is reserved for use by the application.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 DT_SIZE_K(864)>;
};
scratch_partition: partition@f8000 {
label = "image-scratch";
reg = <0x000F8000 DT_SIZE_K(16)>;
};
};
};
&timers2 {
st,prescaler = <10000>;
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch1_pa15>; /* CN1 pin 2 (ARD.D9-PWM) */
pinctrl-names = "default";
};
};
&timers15 {
st,prescaler = <10000>;
status = "okay";
pwm15: pwm {
status = "okay";
pinctrl-0 = <&tim15_ch1_pb14>; /* LED2 */
pinctrl-names = "default";
};
};
stm32_lp_tick_source: &lptim1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12
&usb_otg_fs_id_pa10>;
pinctrl-names = "default";
status = "okay";
};
&iwdg {
status = "okay";
};
&rng {
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in3_pc2 &adc1_in4_pc3
&adc1_in13_pc4 &adc1_in14_pc5>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&die_temp {
status = "okay";
};
&dac1 {
status = "okay";
pinctrl-0 = <&dac1_out1_pa4>;
pinctrl-names = "default";
};
&dma1 {
status = "okay";
};
&quadspi {
pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
&quadspi_bk1_io0_pe12 &quadspi_bk1_io1_pe13
&quadspi_bk1_io2_pe14 &quadspi_bk1_io3_pe15>;
pinctrl-names = "default";
dmas = <&dma1 5 5 0x0000>;
dma-names = "tx_rx";
status = "okay";
mx25r6435f: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Mbits */
qspi-max-frequency = <50000000>;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
slot1_partition: partition@0 {
label = "image-1";
reg = <0x00000000 DT_SIZE_K(864)>;
};
storage_partition: partition@d8000 {
label = "storage";
reg = <0x000d8000 DT_SIZE_M(7)>;
};
};
};
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/disco_l475_iot1/disco_l475_iot1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,588 |
```yaml
board:
name: disco_l475_iot1
vendor: st
socs:
- name: stm32l475xx
``` | /content/code_sandbox/boards/st/disco_l475_iot1/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```restructuredtext
.. _nucleo_u5a5zj_q_board:
ST Nucleo U5A5ZJ Q
##################
Overview
********
The Nucleo U5A5ZJ Q board, featuring an ARM Cortex-M33 based STM32U5A5ZJ MCU,
provides an affordable and flexible way for users to try out new concepts and
build prototypes by choosing from the various combinations of performance and
power consumption features. Here are some highlights of the Nucleo U5A5ZJ Q
board:
- STM32U5A5ZJ microcontroller in LQFP144 package
- Internal SMPS to generate V core logic supply
- Two types of extension resources:
- Arduino Uno V3 connectivity
- ST morpho extension pin headers for full access to all STM32 I/Os
- On-board ST-LINK/V3E debugger/programmer
- Flexible board power supply:
- USB VBUS or external source(3.3V, 5V, 7 - 12V)
- ST-Link V3E
- Three users LEDs
- Two push-buttons: USER and RESET
- USB Type-C Sink device FS
Hardware
********
The STM32U5A5xx devices are an ultra-low-power microcontrollers family (STM32U5
Series) based on the high-performance Arm Cortex-M33 32-bit RISC core.
They operate at a frequency of up to 160 MHz.
- Includes ST state-of-the-art patented technology
- Ultra-low-power with FlexPowerControl:
- 1.71 V to 3.6 V power supply
- -40 C to +85/125 C temperature range
- Low-power background autonomous mode (LPBAM): autonomous peripherals with
DMA, functional down to Stop 2 mode
- VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM
- 150 nA Shutdown mode (24 wake-up pins)
- 195 nA Standby mode (24 wake-up pins)
- 480 nA Standby mode with RTC
- 2 A Stop 3 mode with 40-Kbyte SRAM
- 8.2 A Stop 3 mode with 2.5-Mbyte SRAM
- 4.65 A Stop 2 mode with 40-Kbyte SRAM
- 17.5 A Stop 2 mode with 2.5-Mbyte SRAM
- 18.5 A/MHz Run mode at 3.3 V
- Core:
- Arm 32-bit Cortex-M33 CPU with TrustZone, MPU, DSP,
and FPU ART Accelerator
- 32-Kbyte ICACHE allowing 0-wait-state execution from flash and external
memories: frequency up to 160 MHz, 240 DMIPS
- 16-Kbyte DCACHE1 for external memories
- Power management:
- Embedded regulator (LDO) and SMPSstep-down converter supporting switch
on-the-fly and voltage scaling
- Benchmarks:
- 1.5 DMIPS/MHz (Drystone 2.1)
- 655 CoreMark (4.09 CoreMark/MHz)
- 369 ULPMark-CP
- 89 ULPMark-PP
- 47.2 ULPMark-CM
- 120000 SecureMark-TLS
- Memories:
- 4-Mbyte flash memory with ECC, 2 banks readwhile-write, including 512 Kbytes
with 100 kcycles
- With SRAM3 ECC off: 2514-Kbyte RAM including 66 Kbytes with ECC
- With SRAM3 ECC on: 2450-Kbyte RAMincluding 322 Kbytes with ECC
- External memory interface supporting SRAM,PSRAM, NOR, NAND, and FRAM memories
- 2 Octo-SPI memory interfaces
- 16-bit HSPI memory interface up to 160 MHz
- Rich graphic features:
- Neo-Chrom GPU (GPU2D) accelerating any angle rotation, scaling, and
perspective correct texture mapping
- 16-Kbyte DCACHE2
- Chrom-ART Accelerator (DMA2D) for smoothmotion and transparency effects
- Chrom-GRC (GFXMMU) allowing up to 20 % of graphic resources optimization
- MIPI DSI host controller with two DSI lanes running at up to 500 Mbit/s each
- LCD-TFT controller (LTDC)
- Digital camera interface
- General-purpose input/outputs:
- Up to 156 fast I/Os with interrupt capability most 5V-tolerant and
up to 14 I/Os with independent supply down to 1.08 V
- Clock management:
- 4 to 50 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC ( 1 %)
- Internal low-power 32 kHz RC ( 5 %)
- 2 internal multispeed 100 kHz to 48 MHz oscillators, including one
autotrimmed by LSE (better than 0.25 % accuracy)
- Internal 48 MHz
- 5 PLLs for system clock, USB, audio, ADC, DSI
- Security and cryptography:
- SESIP3 and PSA Level 3 Certified Assurance Target
- Arm TrustZone and securable I/Os, memories, and peripherals
- Flexible life cycle scheme with RDP andpassword-protected debug
- Root of trust thanks to unique boot entry and secure hide-protection area (HDP)
- Secure firmware installation (SFI) thanks to embedded root secure services (RSS)
- Secure data storage with hardware unique key (HUK)
- Secure firmware upgrade support with TF-M
- 2 AES coprocessors including one with DPA resistance
- Public key accelerator, DPA resistant
- On-the-fly decryption of Octo-SPI external memories
- HASH hardware accelerator
- True random number generator, NIST SP800-90B compliant
- 96-bit unique ID
- 512-byte OTP (one-time programmable)
- Active tampers
- Up to 17 timers, 2 watchdogs and RTC:
- 19 timers: 2 16-bit advanced motor-control, 4 32-bit, 3 16-bit general
purpose, 2 16-bit basic, 4 low-power 16-bit (available in Stop mode),
2 SysTick timers, and 2 watchdogs
- RTC with hardware calendar, alarms, and calibration
- Up to 25 communication peripherals:
- 1 USB Type-C/USB power delivery controller
- 1 USB OTG high-speed with embedded PHY
- 2 SAIs (serial audio interface)
- 6 I2C FM+(1 Mbit/s), SMBus/PMBus
- 7 USARTs (ISO 7816, LIN, IrDA, modem)
- 3 SPIs (6x SPIs with OCTOSPI/HSPI)
- 1 CAN FD controller
- 2 SDMMC interfaces
- 1 multifunction digital filter (6 filters) + 1 audio digital filter
with sound-activity detection
- Parallel synchronous slave interface
- Mathematical coprocessor:
- CORDIC for trigonometric functions acceleration
- FMAC (filter mathematical accelerator)
- Rich analog peripherals (independent supply):
- 2 14-bit ADC 2.5-Msps with hardware oversampling
- 1 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode
- 12-bit DAC (2 channels), low-power sample, and hold, autonomous in Stop 2 mode
- 2 operational amplifiers with built-in PGA
- 2 ultra-low-power comparators
- ECOPACK2 compliant packages
More information about STM32U5A5ZJ can be found here:
- `STM32U5A5ZJ on www.st.com`_
- `STM32U5A5 reference manual`_
Supported Features
==================
The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| CAN/CANFD | on-chip | canbus |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| DAC | on-chip | DAC Controller |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| BKP SRAM | on-chip | Backup SRAM |
+-----------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig`
Connections and IOs
===================
Nucleo U5A5ZJ Q Board has 10 GPIO controllers. These controllers are responsible
for pin muxing, input/output, pull-up, etc.
For more details please refer to `STM32 Nucleo-144 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- CAN/CANFD_TX: PD1
- CAN/CANFD_RX: PD0
- DAC1_OUT1 : PA4
- I2C_1_SCL : PB8
- I2C_1_SDA : PB9
- I2C_2_SCL : PF1
- I2C_2_SDA : PF0
- LD1 : PC7
- LD2 : PB7
- LD3 : PG2
- LPUART_1_TX : PG7
- LPUART_1_RX : PG8
- SPI_1_NSS : PA4
- SPI_1_SCK : PA5
- SPI_1_MISO : PA6
- SPI_1_MOSI : PA7
- UART_1_TX : PA9
- UART_1_RX : PA10
- UART_2_TX : PD5
- UART_2_RX : PD6
- USER_PB : PC13
System Clock
------------
Nucleo U5A5ZJ Q System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at
160MHz, driven by 4MHz medium speed internal oscillator.
Serial Port
-----------
Nucleo U5A5ZJ Q board has 6 U(S)ARTs. The Zephyr console output is assigned to
USART1. Default settings are 115200 8N1.
Backup SRAM
-----------
In order to test backup SRAM you may want to disconnect VBAT from VDD. You can
do it by removing ``SB50`` jumper on the back side of the board.
Programming and Debugging
*************************
Nucleo U5A5ZJ-Q board includes an ST-LINK/V3 embedded debug tool interface.
This probe allows to flash the board using various tools.
Flashing
========
Board is configured to be flashed using west STM32CubeProgrammer runner.
Installation of `STM32CubeProgrammer`_ is then required to flash the board.
Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be
used to flash and debug the board if west is told to use it as runner,
which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``.
For pyocd additional target information needs to be installed.
This can be done by executing the following commands.
.. code-block:: console
$ pyocd pack --update
$ pyocd pack --install stm32u5
Flashing an application to Nucleo U5A5ZJ Q
------------------------------------------
Connect the Nucleo U5A5ZJ Q to your host computer using the USB port.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your Nucleo board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_u5a5zj_q
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! arm
Debugging
=========
Default flasher for this board is openocd. It could be used in the usual way.
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nucleo_u5a5zj_q
:goals: debug
Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts
(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI``
(which is used for initialization) is available in the PATH.
.. _STM32 Nucleo-144 board User Manual:
path_to_url
.. _STM32U5A5ZJ on www.st.com:
path_to_url
.. _STM32U5A5 reference manual:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
.. _STMicroelectronics customized version of OpenOCD:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_u5a5zj_q/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,202 |
```unknown
config BOARD_DISCO_L475_IOT1
select SOC_STM32L475XX
``` | /content/code_sandbox/boards/st/disco_l475_iot1/Kconfig.disco_l475_iot1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# enable GPIO
CONFIG_GPIO=y
# enable clock
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/disco_l475_iot1/disco_l475_iot1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioc 5 0>, /* A0 */
<1 0 &gpioc 4 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpioc 2 0>, /* A3 */
<4 0 &gpioc 1 0>, /* A4 */
<5 0 &gpioc 0 0>, /* A5 */
<6 0 &gpioa 1 0>, /* D0 */
<7 0 &gpioa 0 0>, /* D1 */
<8 0 &gpiod 14 0>, /* D2 */
<9 0 &gpiob 0 0>, /* D3 */
<10 0 &gpioa 3 0>, /* D4 */
<11 0 &gpiob 4 0>, /* D5 */
<12 0 &gpiob 1 0>, /* D6 */
<13 0 &gpioa 4 0>, /* D7 */
<14 0 &gpiob 2 0>, /* D8 */
<15 0 &gpioa 15 0>, /* D9 */
<16 0 &gpioa 2 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c3 {};
arduino_spi: &spi1 {};
arduino_serial: &uart4 {};
``` | /content/code_sandbox/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 501 |
```unknown
# Discovery IoT L475 board configuration
if BOARD_DISCO_L475_IOT1
config SPI_STM32_INTERRUPT
default y
depends on SPI
choice LIS3MDL_TRIGGER_MODE
default LIS3MDL_TRIGGER_NONE
endchoice
choice HTS221_TRIGGER_MODE
default HTS221_TRIGGER_NONE
endchoice
choice LSM6DSL_TRIGGER_MODE
default LSM6DSL_TRIGGER_GLOBAL_THREAD
depends on LSM6DSL
endchoice
if BT
config SPI
default y
config BT_SPI
default y
config BT_BLUENRG_ACI
default y
# Disable Flow control
config BT_HCI_ACL_FLOW_CONTROL
default n
config BT_HCI_VS
default n
endif # BT
endif # BOARD_DISCO_L475_IOT1
``` | /content/code_sandbox/boards/st/disco_l475_iot1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 164 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32l4x.cfg]
reset_config srst_only
``` | /content/code_sandbox/boards/st/disco_l475_iot1/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```cmake
board_runner_args(jlink "--device=STM32H7B3LI" "--speed=4000")
board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
if(CONFIG_STM32_MEMMAP)
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(stm32cubeprogrammer "--extload=MX25LM51245G_STM32H7B3I-DISCO.stldr")
else()
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw" )
endif()
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 187 |
```restructuredtext
.. _disco_l475_iot1_board:
ST Disco L475 IOT01 (B-L475E-IOT01A)
####################################
Overview
********
The B-L475E-IOT01A Discovery kit for IoT node allows users to develop
applications with direct connection to cloud servers.
The Discovery kit enables a wide diversity of applications by exploiting
low-power communication, multiway sensing and ARM |reg| Cortex |reg|-M4 core-based
STM32L4 Series features.
This kit provides:
- 64-Mbit Quad-SPI (Macronix) Flash memory
- Bluetooth |reg| V4.1 module (SPBTLE-RF)
- Sub-GHz (868 or 915 MHz) low-power-programmable RF module (SPSGRF-868 or SPSGRF-915)
- Wi-Fi |reg| module Inventek ISM43362-M3G-L44 (802.11 b/g/n compliant)
- Dynamic NFC tag based on M24SR with its printed NFC antenna
- 2 digital omni-directional microphones (MP34DT01)
- Capacitive digital sensor for relative humidity and temperature (HTS221)
- High-performance 3-axis magnetometer (LIS3MDL)
- 3D accelerometer and 3D gyroscope (LSM6DSL)
- 260-1260 hPa absolute digital output barometer (LPS22HB)
- Time-of-Flight and gesture-detection sensor (VL53L0X)
- 2 push-buttons (user and reset)
- USB OTG FS with Micro-AB connector
- Expansion connectors:
- Arduino |trade| Uno V3
- PMOD
- Flexible power-supply options:
- ST LINK USB VBUS or external sources
- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability:
- mass storage, virtual COM port and debug port
.. image:: img/disco_l475_iot1.jpg
:align: center
:alt: Disco L475 IoT1
More information about the board can be found at the `Disco L475 IoT1 website`_.
Hardware
********
The STM32L475VG SoC provides the following hardware IPs:
- Ultra-low-power with FlexPowerControl (down to 120 nA Standby mode and 100 uA/MHz run mode)
- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
- Clock Sources:
- 4 to 48 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
- Internal low-power 32 kHz RC ( |plusminus| 5%)
- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
LSE (better than |plusminus| 0.25 % accuracy)
- 3 PLLs for system clock, USB, audio, ADC
- RTC with HW calendar, alarms and calibration
- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
- 16x timers:
- 2x 16-bit advanced motor-control
- 2x 32-bit and 5x 16-bit general purpose
- 2x 16-bit basic
- 2x low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- SysTick timer
- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
- Memories
- Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection
- Up to 128 KB of SRAM including 32 KB with hardware parity check
- External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories
- Quad SPI memory interface
- 4x digital filters for sigma delta modulator
- Rich analog peripherals (independent supply)
- 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
- 2x 12-bit DAC, low-power sample and hold
- 2x operational amplifiers with built-in PGA
- 2x ultra-low-power comparators
- 18x communication interfaces
- USB OTG 2.0 full-speed, LPM and BCD
- 2x SAIs (serial audio interface)
- 3x I2C FM+(1 Mbit/s), SMBus/PMBus
- 6x USARTs (ISO 7816, LIN, IrDA, modem)
- 3x SPIs (4x SPIs with the Quad SPI)
- CAN (2.0B Active) and SDMMC interface
- SWPMI single wire protocol master I/F
- 14-channel DMA controller
- True random number generator
- CRC calculation unit, 96-bit unique ID
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
More information about STM32L475VG can be found here:
- `STM32L475VG on www.st.com`_
- `STM32L475 reference manual`_
Supported Features
==================
The Zephyr Disco L475 IoT board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| DAC | on-chip | DAC Controller |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| QSPI NOR | on-chip | off-chip flash |
+-----------+------------+-------------------------------------+
| die-temp | on-chip | die temperature sensor |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/disco_l475_iot1/disco_l475_iot1_defconfig`
Connections and IOs
===================
Disco L475 IoT Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
Note that LED LD1 and SPI1 SCK use the same GPIO pin and cannot be used simultaneously.
Available pins:
---------------
For detailed information about available pins please refer to `STM32 Disco L475 IoT1 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX : PB6/PB7 (ST-Link Virtual Port Com)
- UART_4 TX/RX : PA0/PA1 (Arduino Serial)
- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C)
- I2C2 SCL/SDA : PB10/PB11 (Sensor I2C bus)
- I2C3 SCL/SDA : PC0/PC1
- SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI)
- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus)
- PWM_2_CH1 : PA15
- PWM_15_CH1 : PB14 (LD2)
- USER_PB : PC13
- LD1 : PA5 (same as SPI1 SCK)
- LD2 : PB14
- ADC12_IN5 : PA0
- ADC123_IN3 : PC2
- ADC123_IN4 : PC3
- ADC12_IN13 : PC4
- ADC12_IN14 : PC5
- DAC1_OUT1 : PA4
System Clock
------------
Disco L475 IoT System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
driven by 16MHz high speed internal oscillator.
Serial Port
-----------
Disco L475 IoT board has 6 U(S)ARTs. The Zephyr console output is assigned to UART1.
Default settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``disco_l475_iot1`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Disco L475 IoT board includes an ST-LINK/V2-1 embedded debug tool
interface. This interface is supported by the openocd version
included in the Zephyr SDK since v0.9.2.
Flashing an application to Disco L475 IoT
-----------------------------------------
Here is an example for the :ref:`hello_world` application.
Connect the Disco L475 IoT to your host computer using the USB port, then
run a serial host program to connect with your Nucleo board. For example:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then build and flash the application:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: disco_l475_iot1
:goals: build flash
You should see the following message on the console:
.. code-block:: console
$ Hello World! arm
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: disco_l475_iot1
:maybe-skip-config:
:goals: debug
.. _Disco L475 IoT1 website:
path_to_url
.. _STM32 Disco L475 IoT1 board User Manual:
path_to_url
.. _STM32L475VG on www.st.com:
path_to_url
.. _STM32L475 reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/disco_l475_iot1/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,436 |
```linker script
/*
*
*/
#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay)
GROUP_START(SDRAM2)
SECTION_PROLOGUE(_STM32_SDRAM2_SECTION_NAME, (NOLOAD),)
{
*(.lvgl_buf)
} GROUP_LINK_IN(SDRAM2)
GROUP_END(SDRAM2)
#endif
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/dc_ram.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```yaml
board:
name: stm32h7b3i_dk
vendor: st
socs:
- name: stm32h7b3xx
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```yaml
identifier: stm32h7b3i_dk
name: ST STM32H7B3I Discovery Kit
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 1376
flash: 2048
supported:
- arduino_gpio
- uart
- gpio
- i2c
- memc
- backup_sram
- display
- can
vendor: st
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```unknown
# STM32H7B3I DISCOVERY KIT board configuration
if BOARD_STM32H7B3I_DK
config INPUT
default y if LVGL
config INPUT_FT5336_INTERRUPT
default y if INPUT_FT5336
# MEMC needs to be enabled in order to store
# display buffer to external SDRAM connected to FMC
config MEMC
default y if DISPLAY
if LVGL
config CACHE_MANAGEMENT
default y
config LV_USE_GPU_STM32_DMA2D
default y
config LV_GPU_DMA2D_CMSIS_INCLUDE
default "stm32h7xx.h"
config STM32_LTDC_FB_NUM
default 2
config LV_Z_VDB_SIZE
default 100
config LV_Z_DOUBLE_VDB
default y
config LV_Z_FULL_REFRESH
default y
config LV_Z_VBD_CUSTOM_SECTION
default y
config LV_Z_FLUSH_THREAD
default y
config LV_Z_BITS_PER_PIXEL
default 16 if STM32_LTDC_RGB565
endif # LVGL
endif # BOARD_STM32H7B3I_DK
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 231 |
```unknown
# Set SoC present on the board
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable serial
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable clocks
CONFIG_CLOCK_CONTROL=y
# Enable pinctrl
CONFIG_PINCTRL=y
# Enable SMPS
CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```unknown
config BOARD_STM32H7B3I_DK
select SOC_STM32H7B3XXQ
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/Kconfig.stm32h7b3i_dk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 4 0>, /* A0 */
<1 0 &gpioc 4 0>, /* A1 */
<2 0 &gpioa 0 0>, /* A2 */
<3 0 &gpioa 1 0>, /* A3 */
<4 0 &gpioc 2 0>, /* A4 */
<5 0 &gpioc 3 0>, /* A5 */
<6 0 &gpioh 14 0>, /* D0 */
<7 0 &gpioh 13 0>, /* D1 */
<8 0 &gpioi 9 0>, /* D2 */
<9 0 &gpioh 9 0>, /* D3 */
<10 0 &gpioe 2 0>, /* D4 */
<11 0 &gpioh 11 0>, /* D5 */
<12 0 &gpioh 10 0>, /* D6 */
<13 0 &gpioi 10 0>, /* D7 */
<14 0 &gpiof 10 0>, /* D8 */
<15 0 &gpioi 7 0>, /* D9 */
<16 0 &gpioi 0 0>, /* D10 */
<17 0 &gpiob 15 0>, /* D11 */
<18 0 &gpiob 14 0>, /* D12 */
<19 0 &gpioa 12 0>, /* D13 */
<20 0 &gpiod 13 0>, /* D14 */
<21 0 &gpiod 12 0>; /* D15 */
};
};
arduino_i2c: &i2c4 {};
arduino_spi: &spi2 {};
arduino_serial: &uart4 {};
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 495 |
```ini
source [find interface/stlink-dap.cfg]
transport select "dapdirect_swd"
set WORKAREASIZE 0x8000
set CHIPNAME STM32H7B3LIHxQ
set BOARDNAME STM32H7B3I_DK
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0
source [find target/stm32h7x.cfg]
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h7b3Xi.dtsi>
#include <st/h7/stm32h7b3lihxq-pinctrl.dtsi>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32H7B3I DISCOVERY KIT board";
compatible = "st,stm32h7b3i-dk";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,display = <dc;
zephyr,canbus = &fdcan1;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpiog 11 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
blue_led: led_1 {
gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User PB";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <&ft5336>;
};
sdram2: sdram@d0000000 {
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xd0000000 DT_SIZE_M(16)>;
zephyr,memory-region = "SDRAM2";
/* Frame buffer memory cache will cause screen flickering. */
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
};
octo_nor: memory@90000000 {
compatible = "zephyr,memory-region";
reg = <0x90000000 DT_SIZE_M(64)>;
zephyr,memory-region = "EXTMEM";
/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
};
transceiver0: can-phy0 {
compatible = "microchip,mcp2562fd", "can-transceiver-gpio";
standby-gpios = <&gpioh 8 GPIO_ACTIVE_HIGH>;
max-bitrate = <5000000>;
#phy-cells = <0>;
};
aliases {
led0 = &blue_led;
led1 = &red_led;
sw0 = &user_button;
};
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
status = "okay";
};
/* PLL1P is used for system clock (280 MHz), PLL1Q is used for FDCAN bit quantum clock (80 MHz) */
&pll {
div-m = <12>;
mul-n = <280>;
div-p = <2>;
div-q = <7>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
/* PLL3R is used for outputting 9 MHz pixel clock for LTDC */
&pll3 {
div-m = <8>;
mul-n = <60>;
div-p = <2>;
div-q = <2>;
div-r = <20>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(280)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <2>;
d2ppre1 = <2>;
d2ppre2 = <2>;
d3ppre = <2>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&uart4 {
pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_ph14>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c4 {
pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";
ft5336: ft5336@38 {
compatible = "focaltech,ft5336";
reg = <0x38>;
int-gpios = <&gpioh 2 0>;
};
};
&spi2 {
pinctrl-0 = <&spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15 &spi2_nss_pi0>;
pinctrl-names = "default";
status = "okay";
};
/* Connect solder bridges SB3, SB4 and SB5 to use CAN connector (CN21) */
&fdcan1 {
pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
<&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
phys = <&transceiver0>;
status = "okay";
};
&fmc {
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
&fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
&fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
&fmc_d15_pd10>;
pinctrl-names = "default";
status = "okay";
sdram {
status = "okay";
power-up-delay = <100>;
num-auto-refresh = <8>;
mode-register = <0x220>;
refresh-rate = <0x603>;
bank@1 {
reg = <1>;
st,sdram-control = <STM32_FMC_SDRAM_NC_9
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_16
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_2
STM32_FMC_SDRAM_SDCLK_PERIOD_3
STM32_FMC_SDRAM_RBURST_ENABLE
STM32_FMC_SDRAM_RPIPE_2>;
st,sdram-timing = <2 7 4 7 2 2 2>;
};
};
};
&sdmmc1 {
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
pinctrl-names = "default";
cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
<dc {
pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_pj2
<dc_r4_pj3 <dc_r5_pj4 <dc_r6_pj5 <dc_r7_pj6
<dc_g0_pj7 <dc_g1_pj8 <dc_g2_pj9 <dc_g3_pj10
<dc_g4_pj11 <dc_g5_pk0 <dc_g6_pk1 <dc_g7_pk2
<dc_b0_pj12 <dc_b1_pj13 <dc_b2_pj14 <dc_b3_pj15
<dc_b4_pk3 <dc_b5_pk4 <dc_b6_pk5 <dc_b7_pk6
<dc_de_pk7 <dc_clk_pi14 <dc_hsync_pi12 <dc_vsync_pi13>;
pinctrl-names = "default";
disp-on-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>;
bl-ctrl-gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>;
ext-sdram = <&sdram2>;
status = "okay";
width = <480>;
height = <272>;
pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
display-timings {
compatible = "zephyr,panel-timing";
de-active = <0>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
hsync-len = <1>;
vsync-len = <10>;
hback-porch = <43>;
vback-porch = <12>;
hfront-porch = <8>;
vfront-porch = <4>;
};
def-back-color-red = <0xFF>;
def-back-color-green = <0xFF>;
def-back-color-blue = <0xFF>;
};
&octospi1 {
pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pg6
&octospim_p1_io0_pd11 &octospim_p1_io1_pf9
&octospim_p1_io2_pf7 &octospim_p1_io3_pf6
&octospim_p1_io4_pc1 &octospim_p1_io5_ph3
&octospim_p1_io6_pg9 &octospim_p1_io7_pd7
&octospim_p1_dqs_pc5>;
pinctrl-names = "default";
status = "okay";
mx25lm51245: ospi-nor-flash@90000000 {
compatible = "st,stm32-ospi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
spi-bus-width = <OSPI_OPI_MODE>;
data-rate = <OSPI_DTR_TRANSFER>;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "nor";
reg = <0x00000000 DT_SIZE_M(4)>;
};
};
};
};
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,686 |
```cmake
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
``` | /content/code_sandbox/boards/st/sensortile_box_pro/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/u5/stm32u585Xi.dtsi>
#include <st/u5/stm32u585aiixq-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics SENSORTILE-BOX-PRO board";
compatible = "st,sensortile-box-pro";
chosen {
zephyr,console = &cdc_acm_uart0;
zephyr,shell-uart = &cdc_acm_uart0;
zephyr,bt-c2h-uart = &cdc_acm_uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,bt-hci = &hci_spi;
};
leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpiof 6 GPIO_ACTIVE_HIGH>;
label = "User GREEN led";
};
red_led_1: led_2 {
gpios = <&gpioh 11 GPIO_ACTIVE_HIGH>;
label = "User RED led";
};
yellow_led_1: led_3 {
gpios = <&gpioh 12 GPIO_ACTIVE_HIGH>;
label = "User YELLOW led";
};
blue_led_1: led_4 {
gpios = <&gpiof 9 GPIO_ACTIVE_HIGH>;
label = "User YELLOW led";
};
};
gpio_keys {
compatible = "gpio-keys";
button1: button1 {
label = "User BT1";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
button2: button2 {
label = "User BT2";
gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_1>;
};
};
sd_card: sd-card {
compatible = "st,stile_sd_card";
en-sd-gpios = <&gpioh 10 (GPIO_ACTIVE_HIGH)>;
sel-sd-gpios = <&gpioh 8 (GPIO_ACTIVE_HIGH)>;
};
aliases {
led0 = &green_led_1;
led1 = &red_led_1;
led2 = &yellow_led_1;
led3 = &blue_led_1;
mcuboot-led0 = &blue_led_1;
mcuboot-button0 = &button1;
sw1 = &button1;
sw2 = &button2;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref1;
volt-sensor1 = &vbat4;
};
};
&clk_hsi48 {
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_msis {
status = "okay";
msi-range = <4>;
msi-pll-mode;
};
&gpioi {
status = "okay";
/* switch sensor IMU bus from I2C1 to SPI2 */
mcu-sel-gpios {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-low;
};
};
&pll1 {
div-m = <1>;
mul-n = <80>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_msis>;
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};
stm32_lp_tick_source: &lptim1 {
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>,
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
status = "okay";
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&uart4 {
pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pa1>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
status = "okay";
hci_spi: bluenrg-lp@0 {
compatible = "st,hci-spi-v2";
reg = <0>;
irq-gpios = <&gpiod 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
reset-gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
spi-cpol;
spi-cpha;
spi-hold-cs;
spi-max-frequency = <DT_FREQ_M(8)>;
controller-data-delay-us = <0>;
reset-assert-duration-ms = <6>;
};
};
&spi1_sck_pa5 {
/delete-property/ bias-pull-down;
bias-pull-up; /* Idle state for the clock pin is high-level due to SPI mode 3 */
};
&spi2 {
pinctrl-0 = <&spi2_sck_pi1 &spi2_miso_pi2 &spi2_mosi_pi3>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpioi 5 GPIO_ACTIVE_LOW>, <&gpioi 7 GPIO_ACTIVE_LOW>;
lsm6dsv16x: lsm6dsv16x@0 {
compatible = "st,lsm6dsv16x";
spi-max-frequency = <DT_FREQ_M(10)>;
reg = <0>;
int1-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
int2-gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
drdy-pin = <2>;
};
lis2du12: lis2du12@1 {
compatible = "st,lis2du12";
spi-max-frequency = <DT_FREQ_M(10)>;
reg = <1>;
int1-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
int2-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
drdy-pin = <1>;
};
};
&timers4 {
status = "okay";
st,prescaler = <1>;
pwm4: pwm {
status = "okay";
pinctrl-0 = <&tim4_ch1_pb6>;
pinctrl-names = "default";
};
};
&timers3 {
status = "okay";
st,prescaler = <255>;
pwm3: pwm {
status = "okay";
pinctrl-0 = <&tim3_ch2_pe4>;
pinctrl-names = "default";
};
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
lps22df@5d {
compatible = "st,lps22df";
reg = <0x5d>;
drdy-gpios = <&gpioe 8 GPIO_ACTIVE_HIGH>;
status = "okay";
};
lis2mdl@1e {
compatible = "st,lis2mdl";
reg = <0x1e>;
irq-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
stts22h@38 {
compatible = "st,stts22h";
reg = <0x38>;
int-gpios = <&gpiob 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_ph4 &i2c2_sda_ph5>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&aes {
status = "okay";
};
&rng {
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};
&adc1 {
pinctrl-0 = <&adc1_in15_pb0>;
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&adc4 {
pinctrl-0 = <&adc4_in19_pb1>;
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&die_temp {
status = "okay";
};
&dac1 {
pinctrl-0 = <&dac1_out1_pa4>;
pinctrl-names = "default";
status = "okay";
};
&iwdg {
status = "okay";
};
&vref1 {
status = "okay";
};
&vbat4 {
status = "okay";
};
&sdmmc1 {
status = "okay";
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2
&sdmmc1_d0dir_pc6 &sdmmc1_d123dir_pc7
&sdmmc1_cdir_pb9 &sdmmc1_ckin_pb8>;
pinctrl-names = "default";
cd-gpios = <&gpioc 5 GPIO_ACTIVE_LOW>;
pwr-gpios = <&gpioh 10 GPIO_ACTIVE_LOW>;
bus-width = <4>;
clk-div = <4>;
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* Following flash partition is dedicated to the use of sensortile_box_pro
* with TZEN=0 (so w/o TFM).
* Set the partitions with first MB to make use of the whole Bank1
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(416)>;
};
slot1_partition: partition@78000 {
label = "image-1";
reg = <0x00078000 DT_SIZE_K(416)>;
};
scratch_partition: partition@e0000 {
label = "image-scratch";
reg = <0x000e0000 DT_SIZE_K(64)>;
};
storage_partition: partition@f0000 {
label = "storage";
reg = <0x000f0000 DT_SIZE_K(64)>;
};
};
};
&gpdma1 {
status = "okay";
};
``` | /content/code_sandbox/boards/st/sensortile_box_pro/sensortile_box_pro.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,646 |
```yaml
identifier: sensortile_box_pro
name: ST SensorTile.box Pro
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- pwm
- spi
- ble
- i2c
- gpio
- usb device
- nvs
- counter
ram: 640
flash: 2048
vendor: st
``` | /content/code_sandbox/boards/st/sensortile_box_pro/sensortile_box_pro.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```yaml
board:
name: sensortile_box_pro
vendor: st
socs:
- name: stm32u585xx
``` | /content/code_sandbox/boards/st/sensortile_box_pro/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
# SENSORTILE_BOX_PRO board configuration
if BOARD_SENSORTILE_BOX_PRO
if BT
config SPI
default y
config BT_SPI
default y
config BT_BLUENRG_ACI
default y
# Disable Flow control
config BT_HCI_ACL_FLOW_CONTROL
default n
endif # BT
config SPI_STM32_INTERRUPT
default y
depends on SPI
if BOARD_SERIAL_BACKEND_CDC_ACM
config USB_DEVICE_STACK
default y
config USB_CDC_ACM
default SERIAL
config USB_DEVICE_INITIALIZE_AT_BOOT
default y if CONSOLE
config SHELL_BACKEND_SERIAL_CHECK_DTR
default SHELL
depends on UART_LINE_CTRL
config UART_LINE_CTRL
default SHELL
config USB_DEVICE_REMOTE_WAKEUP
default n
config USB_DEVICE_VID
default 0x0483
config USB_DEVICE_PID
default 0x5740
config USB_DEVICE_PRODUCT
default "Zephyr CDC SensorTile.box PRO"
if LOG
# Logger cannot use itself to log
choice USB_CDC_ACM_LOG_LEVEL_CHOICE
default USB_CDC_ACM_LOG_LEVEL_OFF
endchoice
endif # LOG
endif # BOARD_SERIAL_BACKEND_CDC_ACM
DT_CHOSEN_ZEPHYR_CONSOLE := zephyr,console
config UART_CONSOLE
default y if $(dt_chosen_enabled,$(DT_CHOSEN_ZEPHYR_CONSOLE)) && CONSOLE
endif # BOARD_SENSORTILE_BOX_PRO
``` | /content/code_sandbox/boards/st/sensortile_box_pro/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 303 |
```unknown
config BOARD_SENSORTILE_BOX_PRO
select SOC_STM32U585XX
``` | /content/code_sandbox/boards/st/sensortile_box_pro/Kconfig.sensortile_box_pro | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```unknown
# SENSORTILE_BOX_PRO board configuration
if BOARD_SENSORTILE_BOX_PRO
config BOARD_SERIAL_BACKEND_CDC_ACM
bool "Use USB CDC as serial console backend"
default y
endif # BOARD_SENSORTILE_BOX_PRO
``` | /content/code_sandbox/boards/st/sensortile_box_pro/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# Enable console
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/sensortile_box_pro/sensortile_box_pro_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```ini
source [find interface/stlink-dap.cfg]
set WORKAREASIZE 0x8000
transport select "dapdirect_swd"
set CHIPNAME STM32U575ZITxQ
set BOARDNAME STILE-BOX-PRO
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# STlink Debug clock frequency
set CLOCK_FREQ 8000
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0
# ACCESS PORT NUMBER
set AP_NUM 0
# GDB PORT
set GDB_PORT 3333
# BCTM CPU variables
source [find target/stm32u5x.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/sensortile_box_pro/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 251 |
```restructuredtext
.. _stm32h7b3i_dk_board:
ST STM32H7B3I Discovery kit
###########################
Overview
********
The STM32H7B3I-DK Discovery kit is a complete demonstration and development
platform for STMicroelectronics Arm Cortex-M7 core-based STM32H7B3LIH6QU
microcontroller.
The STM32H7B3I-DK Discovery kit is used as a reference design for user
application development before porting to the final product, thus simplifying
the application development.
The full range of hardware features available on the board helps users enhance
their application development by an evaluation of almost all peripherals (such as
USB OTG_HS, microSD, USART, FDCAN, audio DAC stereo with audio jack input and output,
camera, SDRAM, Octo-SPI Flash memory and RGB interface LCD with capacitive touch
panel). ARDUINO Uno V3 connectors provide easy connection to extension shields or
daughterboards for specific applications.
Important board features include:
- STM32H7B3LIH6Q microcontroller featuring 2 Mbytes of Flash memory and 1.4 Mbyte of RAM in BGA225 package
- 4.3" (480x272 pixels) TFT color LCD module including a capacitive touch panel with RGB interface
- Wi-Fi |reg| module compliant with 802.11 b/g/n
- USB OTG HS
- Audio codec
- 512-Mbit Octo-SPI NOR Flash memory
- 128-Mbit SDRAM
- 2 user LEDs
- User and Reset push-buttons
- Fanout daughterboard
- 1x FDCAN
- Board connectors:
- Camera (8 bit)
- USB with Micro-AB
- Stereo headset jack including analog microphone input
- Audio jack for external speakers
- microSD |trade| card
- TAG-Connect 10-pin footprint
- Arm |reg| Cortex |reg| 10-pin 1.27mm-pitch debug connector over STDC14 footprint
- ARDUINO |reg| Uno V3 expansion connector
- STMod+ expansion connector
- Audio daughterboard expansion connector
- External I2C expansion connector
- Flexible power-supply options:
- ST-LINK USB VBUS, USB OTG HS connector, or external sources
- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability
.. image:: img/stm32h7b3i_dk.jpg
:align: center
:alt: STM32H7B3I-DK
More information about the board can be found at the `STM32H7B3I-DK website`_.
Hardware
********
The STM32H7B3I Discovery kit provides the following hardware components:
- STM32H7B3LIH6Q in BGA225 package
- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU
- 280 MHz max CPU frequency
- VDD from 1.62 V to 3.6 V
- 2 MB Flash
- ~1.4 Mbytes SRAM
- 32-bit timers(2)
- 16-bit timers(15)
- SPI(6)
- I2C(4)
- I2S (4)
- USART(5)
- UART(5)
- USB OTG Full Speed and High Speed(1)
- CAN FD(2)
- 2xSAI (serial audio interface)
- SPDIFRX interface(1)
- HDMI-CEC(1)
- Octo-SPI memory interfaces with on-the-fly decryption(2)
- 8- to 14-bit camera interface (1)
- 8-/16-bit parallel synchronous data input/output slave interface (PSSI)
- GPIO (up to 168) with external interrupt capability
- 16-bit ADC(2) with 24 channels / 3.6 MSPS
- 1x12-bit single-channel DAC + 1x12-bit dual-channel DAC
- True Random Number Generator (RNG)
- 5 DMA controllers
- LCD-TFT Controller with XGA resolution
- Chrom-ART graphical hardware Accelerator (DMA2D)
- Hardware JPEG Codec
- Chrom-GRC (GFXMMU)
More information about STM32H7B3 can be found here:
- `STM32H7A3/7B3 on www.st.com`_
- `STM32H7A3/7B3/7B0 reference manual`_
- `STM32H7B3xI datasheet`_
Supported Features
==================
The current Zephyr stm32h7b3i_dk board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SDMMC | on-chip | disk access |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| OSPI NOR | on-chip | off-chip flash |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| FMC | on-chip | memc (SDRAM) |
+-----------+------------+-------------------------------------+
| LTDC | on-chip | display |
+-----------+------------+-------------------------------------+
| CANFD | on-chip | can |
+-----------+------------+-------------------------------------+
Other hardware features have not been enabled yet for this board.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig`
Pin Mapping
===========
STM32H7B3I Discovery kit has 11 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
For more details please refer to `STM32H7B3I-DK board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
The STM32H7B3I Discovery kit features an Arduino Uno V3 connector. Board is
configured as follows
- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com)
- UART_4 TX/RX : PH13/PH14 (Arduino Serial)
- I2C4 SCL/SDA : PD12/PD13 (Arduino I2C, Touchscreen FT5336 with PH2 Interrupt Pin)
- SPI2 SCK/MISO/MOSI/NSS : PA12/PB14/PB15/PI0 (Arduino SPI)
- LD1 : PG11
- LD2 : PG2
- USER_PB : PC13
- SDMMC D0/D1/D2/D3/CK/CMD/CD : PC8/PC9/PC10/PC11/PC12/PD2/PI8
- CANFD RX/TX/WAKE [#]_ : PA11/PA12/PH8
- FMC SDRAM :
- D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10
- A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1
- A14/A15 : PG4/PG5
- SDNRAS/SDNCAS : PF11/PG15
- NBL0/NBL1 : PE0/PE1
- SDCLK/SDNWE/SDCKE1/SDNE1 : PG8/PH5/PH7/PH6
- LTDC :
- R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6
- G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2
- B0-B7 : PJ12/PJ13/PJ14/PJ15/PK3/PK4/PK5/PK6
- DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13
System Clock
============
The STM32H7B3I System Clock can be driven by an internal or external oscillator,
as well as by the main PLL clock. By default, the System clock is driven
by the PLL clock at 280MHz. PLL clock is fed by a 24MHz high speed external clock.
Serial Port
===========
The STM32H7B3I Discovery kit has up to 10 UARTs. The Zephyr console output is assigned
to UART1 which is connected to the onboard STLINK-V3E. Virtual COM port interface
default communication settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``stm32h7b3i_dk`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
STM32H7B3I Discovery kit includes an STLINK-V3E embedded debug tool interface.
This interface is supported by the openocd version included in the Zephyr SDK.
Flashing may depend on the SoC option bytes configuration, which can be checked and
updated using `STM32CubeProgrammer`_.
Flashing an application to STM32H7B3I
-------------------------------------
First, connect the STM32H7B3I Discovery kit to your host computer using
the USB port to prepare it for flashing. Then build and flash your application.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h7b3i_dk
:goals: build flash
Run a serial host program to connect with your board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
You should see the following message on the console:
.. code-block:: console
Hello World! arm
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h7b3i_dk
:goals: debug
.. _STM32H7B3I-DK website:
path_to_url
.. _STM32H7B3I-DK board User Manual:
path_to_url
.. _STM32H7A3/7B3 on www.st.com:
path_to_url
.. _STM32H7A3/7B3/7B0 reference manual:
path_to_url
.. _STM32H7B3xI datasheet:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
.. _STM32H7B3I_DK board schematics:
path_to_url
.. [#] To use CAN, solder bridges SB3, SB4 and SB5 need to be connected.
Take note that CANFD pins are shared with STMOD+ connector (P1), so please check
`STM32H7B3I_DK board schematics`_ for possible collisions if using that connector.
``` | /content/code_sandbox/boards/st/stm32h7b3i_dk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,634 |
```cmake
board_runner_args(jlink "--device=STM32F100RB" "--speed=8000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32vl_disco/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# enable clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32vl_disco/stm32vl_disco_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```yaml
identifier: stm32vl_disco
name: ST STM32VL Discovery
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 8
flash: 128
supported:
- gpio
- i2c
- spi
vendor: st
``` | /content/code_sandbox/boards/st/stm32vl_disco/stm32vl_disco.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
config BOARD_STM32VL_DISCO
select SOC_STM32F100XB
``` | /content/code_sandbox/boards/st/stm32vl_disco/Kconfig.stm32vl_disco | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```yaml
board:
name: stm32vl_disco
vendor: st
socs:
- name: stm32f100xb
``` | /content/code_sandbox/boards/st/stm32vl_disco/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f1/stm32f100Xb.dtsi>
#include <st/f1/stm32f100r(8-b)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32VLDISCOVERY board";
compatible = "st,stm32vldiscovery";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
green_led: ld3 {
gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
blue_led: ld4 {
gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>;
label = "User LD4";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led;
led1 = &blue_led;
sw0 = &user_button;
};
};
&clk_hsi {
status = "okay";
};
&pll {
mul = <6>;
prediv = <1>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(24)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_nss_master_pa4 &spi1_sck_master_pa5
&spi1_miso_master_pa6 &spi1_mosi_master_pa7>;
pinctrl-names = "default";
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_nss_master_pb12 &spi2_sck_master_pb13
&spi2_miso_master_pb14 &spi2_mosi_master_pb15>;
pinctrl-names = "default";
status = "okay";
};
&timers1 {
st,prescaler = <10000>;
status = "okay";
pwm1: pwm {
status = "okay";
pinctrl-0 = <&tim1_ch1_pwm_out_pa8>;
pinctrl-names = "default";
};
};
``` | /content/code_sandbox/boards/st/stm32vl_disco/stm32vl_disco.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 846 |
```ini
source [find board/stm32vldiscovery.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/stm32vl_disco/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```restructuredtext
.. _sensortile_box_pro_board:
ST SensorTile.box PRO
#####################
Overview
********
The STEVAL-MKBOXPRO (SensorTile.box PRO) features an ARM Cortex-M33 based STM32U585AI MCU
and is a ready-to-use box kit for wireless IoT and wearable sensor platforms to help using
and developing apps based on remote motion and environmental sensor data.
The SensorTile.box PRO board fits into a small plastic box with a long-life rechargeable
battery, and communicates with a standard smartphone through its Bluetooth interface,
providing data coming from the sensors.
.. image:: img/sensortile_box_pro.jpg
:align: center
:alt: SensorTile.box PRO
More information about the board can be found at the `SensorTile.box PRO website`_.
Supported Features
******************
The SensorTile.box PRO provides motion, environmental, and audio
sensor data through either the BLE or USB protocols to a host application running
on a smartphone/PC to implement applications such as:
- Pedometer optimized for belt positioning
- Baby crying detection with Cloud AI learning
- Barometer / environmental monitoring
- Vehicle / goods tracking
- Vibration monitoring
- Compass and inclinometer
- Sensor data logger
(see `Motion and environmental sensors`_ section for the complete lists of available
sensors on board)
Hardware
********
The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5
Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core.
They operate at a frequency of up to 160 MHz.
- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode)
- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU.
- Performance benchmark:
- 1.5 DMPIS/MHz (Drystone 2.1)
- 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ)
- Security and cryptography
- Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals
- Flexible life cycle scheme with RDP (readout protection) and password protected debug
- Root of trust thanks to unique boot entry and secure hide protection area (HDP)
- Secure Firmware Installation thanks to embedded Root Secure Services
- Secure data storage with hardware unique key (HUK)
- Secure Firmware Update support with TF-M
- 2 AES coprocessors including one with DPA resistance
- Public key accelerator, DPA resistant
- On-the-fly decryption of Octo-SPI external memories
- HASH hardware accelerator
- Active tampers
- True Random Number Generator NIST SP800-90B compliant
- 96-bit unique ID
- 512-byte One-Time Programmable for user data
- Active tampers
- Clock management:
- 4 to 50 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
- Internal low-power 32 kHz RC ( |plusminus| 5%)
- 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by
LSE (better than |plusminus| 0.25 % accuracy)
- 3 PLLs for system clock, USB, audio, ADC
- Internal 48 MHz with clock recovery
- Power management
- Embedded regulator (LDO)
- Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling
- RTC with HW calendar and calibration
- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
- Up to 17 timers and 2 watchdogs
- 2x 16-bit advanced motor-control
- 2x 32-bit and 5 x 16-bit general purpose
- 4x low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- 2x SysTick timer
- ART accelerator
- 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and
external memories: up to 160 MHz, MPU, 240 DMIPS and DSP
- 4-Kbyte data cache for external memories
- Memories
- 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles
- 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON
- External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories
- 2 Octo-SPI memory interfaces
- Rich analog peripherals (independent supply)
- 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling
- 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode
- 12-bit DAC, low-power sample and hold
- 2 operational amplifiers with built-in PGA
- 2 ultra-low-power comparators
- Up to 22 communication interfaces
- USB Type-C / USB power delivery controller
- USB OTG 2.0 full-speed controller
- 2x SAIs (serial audio interface)
- 4x I2C FM+(1 Mbit/s), SMBus/PMBus
- 6x USARTs (ISO 7816, LIN, IrDA, modem)
- 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode)
- 1x FDCAN
- 2x SDMMC interface
- 16- and 4-channel DMA controllers, functional in Stop mode
- 1 multi-function digital filter (6 filters)+ 1 audio digital filter with
sound-activity detection
- CRC calculation unit
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
- True Random Number Generator (RNG)
- Graphic features
- Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
- 1 digital camera interface
- Mathematical co-processor
- CORDIC for trigonometric functions acceleration
- FMAC (filter mathematical accelerator)
More information about STM32U585AI can be found here:
- `STM32U585 on www.st.com`_
- `STM32U585 reference manual`_
Motion and environmental sensors
================================
- **LSM6DSV16X** 6-axis inertial measurement unit
(`lsm6dsv16x datasheet`_)
- **LIS2MDL** 3-axis magnetometer
(`lis2mdl datasheet`_)
- **LPS22DF** Altimeter / pressure sensor
(`lps22df datasheet`_)
- **LIS2DU12** 3-axis accelerometer
(`lis2du12 datasheet`_)
- **STTS22H** Digital temperature sensor
(`stts22hh datasheet`_)
- **MP23db01HP** Microphone / audio sensor
(`mp23db01hp datasheet`_)
Connections and IOs
===================
- 4x user LEDs
- **led0** (Green)
- **led1** (Red - shared with BLE)
- **led2** (Yellow)
- **led3** (Blue)
- 4x buttons/switch
- **User BT1** button, available to user application
- **User BT2** / **boot0** button, available to user application
but useful to let the SensorTile.box PRO enter DFU mode
if found pressed after h/w reset (see **rst** button and
`Programming and Debugging`_ section)
- **rst** button, used to reset the board (not available on case)
- **power** switch, used to Power on/off the board
System Clock
============
SensorTile.box PRO System Clock could be driven by internal or external
oscillator, as well as main PLL clock. By default, the System clock is
driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator.
The system clock can be boosted to 120MHz.
The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz.
Serial Port
===========
The SensorTile.box PRO has 4 U(S)ARTs. The UART4 is connected to JTAG/SWD connector
and may be used as console.
USB interface
=============
SensorTile.box PRO can be connected as a USB device to a PC host through its USB-C connector.
The final application may use it to declare SensorTile.box PRO device as belonging to a
certain standard or vendor class, e.g. a CDC, a mass storage or a composite device with both
functions.
Console
=======
There are two possible options for Zephyr console output:
- through USB as USB CDC/ACM class. This is the default case present in the board dts file
and is enabled by :kconfig:option:`CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM`.
.. code-block:: dts
:caption: boards/st/sensortile_box_pro/sensortile_box_pro.dts
/ {
chosen {
zephyr,console = &cdc_acm_uart0;
};
};
&zephyr_udc0 {
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};
- through UART4 which is available on SWD connector (JP2). In this case a JTAG adapter
can be used to connect SensorTile.box PRO and have both SWD and console lines available.
To enable console and shell over UART:
- in your prj.conf, override the board's default configuration by setting :code:`CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM=n`
- add an overlay file named ``<board>.overlay``:
.. code-block:: dts
/ {
chosen {
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
};
};
Console default settings are 115200 8N1.
Programming and Debugging
*************************
There are two alternative methods of flashing ST Sensortile.box Pro board:
1. Using DFU software tools
This method requires to enter STM32U585 ROM bootloader DFU mode
by powering up (or reset) the board while keeping the BOOT0 button pressed.
No additional hardware is required except a USB-C cable. This method is fully
supported by :ref:`flash-debug-host-tools`.
You can read more about how to enable and use the ROM bootloader by checking
the application note `AN2606`_ (STM32U585xx section).
2. Using SWD hardware tools
This method requires to connect additional hardware, like a ST-LINK/V3
embedded debug tool, to the board SWD connector.
DFU flashing
============
Install dfu-util
----------------
It is recommended to use at least v0.9 of dfu-util. The package available in
Debian and Ubuntu can be quite old, so you might have to build dfu-util from source.
Information about how to get the source code and how to build it can be found
at the `DFU-UTIL website`_
Flash an Application to SensorTile.box PRO
------------------------------------------
While pressing the BOOT0 button, connect the USB-C cable to the USB OTG SensorTile.box PRO
port and to your computer. The board should be forced to enter DFU mode.
Check that the board is indeed in DFU mode:
.. code-block:: console
$ sudo dfu-util -l
dfu-util 0.9
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to path_to_url
Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=2, name="@OTP Memory /0x1FFF7000/01*0001Ke", serial="204A325D574D"
Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=1, name="@Option Bytes /0x1FF00000/01*040 e/0x1FF01000/01*040 e", serial="204A325D574D"
Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=0, name="@Internal Flash /0x08000000/512*0004Kg", serial="204A325D574D"
You should see following confirmation on your Linux host:
.. code-block:: console
$ dmesg
usb 2-2: new full-speed USB device number 74 using xhci_hcd
usb 2-2: New USB device found, idVendor=0483, idProduct=df11
usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 2-2: Product: STM32 BOOTLOADER
usb 2-2: Manufacturer: STMicroelectronics
usb 2-2: SerialNumber: 204A325D574D
You can build and flash the provided sample application
(:ref:`sensortile_box_pro_sample_sensors`) that reads sensors data and outputs
values on the console.
References
**********
.. target-notes::
.. _SensorTile.box PRO website:
path_to_url
.. _STM32U585 on www.st.com:
path_to_url
.. _STM32U585 reference manual:
path_to_url
.. _lsm6dsv16x datasheet:
path_to_url
.. _lis2mdl datasheet:
path_to_url
.. _lps22df datasheet:
path_to_url
.. _lis2du12 datasheet:
path_to_url
.. _stts22hh datasheet:
path_to_url
.. _mp23db01hp datasheet:
path_to_url
.. _AN2606:
path_to_url
.. _DFU-UTIL website:
path_to_url
``` | /content/code_sandbox/boards/st/sensortile_box_pro/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,213 |
```restructuredtext
.. _stm32vl_disco_board:
ST STM32VL Discovery
####################
Overview
********
The STM32 Discovery series comes in many varieties, in this case the "Value
Line" STM32F100x SoC series is showcased. Like other Discovery board, an
integrated ST-LINK debugger and programmer is included (V1), but the only
included I/O devices are two user LEDs and one user button.
.. image:: img/stm32vl_disco.jpg
:align: center
:alt: STM32VLDISCOVERY
More information about the board can be found at the `STM32VLDISCOVERY website`_.
Hardware
********
The STM32 Discovery board features:
- On-board ST-LINK/V1 with selection mode switch to use the kit as a standalone
ST-LINK/V1 (with SWD connector for programming and debugging)
- Board power supply: through USB bus or from an external 5 V supply voltage
- External application power supply: 3 V and 5 V
- Four LEDs:
- LD1 (red) for 3.3 V power on
- LD2 (red/green) for USB communication
- LD3 (green) for PC9 output
- LD4 (blue) for PC8 output
- Two push buttons (user and reset)
- Extension header for all LQFP64 I/Os for quick connection to prototyping board
and easy probing
More information about the STM32F100x can be found in the
`STM32F100x reference manual`_ and the `STM32F100x data sheet`_.
Supported Features
==================
The Zephyr stm32vl_disco board configuration supports the following hardware features:
.. list-table:: Supported hardware
:header-rows: 1
* - Interface
- Controller
- Driver/component
* - NVIC
- on-chip
- nested vector interrupt controller
* - UART
- on-chip
- serial port-polling
serial port-interrupt
* - PINMUX
- on-chip
- pinmux
* - GPIO
- on-chip
- gpio
* - CLOCK
- on-chip
- reset and clock control
* - FLASH
- on-chip
- flash memory
* - WATCHDOG
- on-chip
- window watchdog
* - I2C
- on-chip
- i2c
* - SPI
- on-chip
- spi
* - ADC
- on-chip
- adc
Other hardware features are not yet supported in this Zephyr port.
The default configuration can be found in
:zephyr_file:`boards/st/stm32vl_disco/stm32vl_disco_defconfig`
Connections and IOs
===================
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
Default Zephyr Peripheral Mapping:
----------------------------------
.. rst-class:: rst-columns
- UART_1_TX : PA9
- UART_1_RX : PA10
- UART_2_TX : PA2
- UART_2_RX : PA3
- UART_3_TX : PB10
- UART_3_RX : PB11
- SPI1_NSS : PA4
- SPI1_SCK : PA5
- SPI1_MISO : PA6
- SPI1_MOSI : PA7
- SPI2_NSS : PB12
- SPI2_SCK : PB13
- SPI2_MISO : PB14
- SPI2_MOSI : PB15
- I2C1_SCL : PB6
- I2C1_SDA : PB7
- I2C2_SCL : PB10
- I2C2_SDA : PB11
For more details please refer to `STM32VLDISCOVERY board User Manual`_.
Programming and Debugging
*************************
Applications for the ``stm32vl_disco`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
STM32VLDISCOVERY board includes an ST-LINK/V1 embedded debug tool interface.
This interface is supported by the openocd version included in the Zephyr SDK.
Flashing an application
-----------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32vl_disco
:goals: build flash
You will see the LED blinking every second.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32vl_disco
:maybe-skip-config:
:goals: debug
USB mass storage issues
=======================
The ST-LINK/V1 includes a buggy USB mass storage gadget. To connect to the
ST-LINK from Linux, you might need to ignore the device using modprobe
configuration parameters:
.. code-block:: shell
$ echo "options usb-storage quirks=483:3744:i" | sudo tee /etc/modprobe.d/local.conf
$ sudo modprobe -r usb-storage
References
**********
.. target-notes::
.. _STM32VLDISCOVERY website:
path_to_url
.. _STM32F100x reference manual:
path_to_url
.. _STM32F100x data sheet:
path_to_url
.. _STM32VLDISCOVERY board User Manual:
path_to_url
``` | /content/code_sandbox/boards/st/stm32vl_disco/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,308 |
```cmake
board_runner_args(jlink "--device=STM32F722ZE" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_f722ze/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```yaml
board:
name: nucleo_f722ze
vendor: st
socs:
- name: stm32f722xx
``` | /content/code_sandbox/boards/st/nucleo_f722ze/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```yaml
identifier: nucleo_f722ze
name: ST Nucleo F722ZE
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- arduino_gpio
- arduino_i2c
- arduino_spi
- backup_sram
- can
- counter
- dac
- gpio
- i2c
- quadspi
- spi
- usb_device
- rtc
ram: 256
flash: 512
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_f722ze/nucleo_f722ze.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 135 |
```unknown
# STM32F722ZE Nucleo board configuration
#
if BOARD_NUCLEO_F722ZE
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_NUCLEO_F722ZE
``` | /content/code_sandbox/boards/st/nucleo_f722ze/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
config BOARD_NUCLEO_F722ZE
select SOC_STM32F722XX
``` | /content/code_sandbox/boards/st/nucleo_f722ze/Kconfig.nucleo_f722ze | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 3 0>, /* A0 */
<1 0 &gpioc 0 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpiof 3 0>, /* A3 */
<4 0 &gpiof 5 0>, /* A4 */
<5 0 &gpiof 10 0>, /* A5 */
<6 0 &gpiog 9 0>, /* D0 */
<7 0 &gpiog 14 0>, /* D1 */
<8 0 &gpiof 15 0>, /* D2 */
<9 0 &gpioe 13 0>, /* D3 */
<10 0 &gpiof 14 0>, /* D4 */
<11 0 &gpioe 11 0>, /* D5 */
<12 0 &gpioe 9 0>, /* D6 */
<13 0 &gpiof 13 0>, /* D7 */
<14 0 &gpiof 12 0>, /* D8 */
<15 0 &gpiod 15 0>, /* D9 */
<16 0 &gpiod 14 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
arduino_serial: &usart6 {};
``` | /content/code_sandbox/boards/st/nucleo_f722ze/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 497 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART
CONFIG_SERIAL=y
# Enable console (use UART by default)
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable clocks
CONFIG_CLOCK_CONTROL=y
# Enable pinctrl
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_f722ze/nucleo_f722ze_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```ini
source [find board/st_nucleo_f7.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/nucleo_f722ze/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
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