text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*
*/
/dts-v1/;
#include <st/f7/stm32f722Xe.dtsi>
#include <st/f7/stm32f722z(c-e)tx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32F722ZE-NUCLEO board";
compatible = "st,stm32f722ze-nucleo";
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,dtcm = &dtcm;
zephyr,canbus = &can1;
zephyr,code-partition = &slot0_partition;
};
leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
blue_led: led_2 {
gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
red_led: led_3 {
gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
sw0 = &user_button;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};
&clk_hsi {
status = "disabled";
};
&clk_lsi {
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <216>;
div-p = <2>;
div-q = <9>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(216)>;
ahb-prescaler = <1>;
apb1-prescaler = <4>;
apb2-prescaler = <2>;
};
&sdmmc1 {
status = "okay";
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 &sdmmc1_d2_pc10
&sdmmc1_d3_pc11 &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
pinctrl-names = "default";
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
};
&adc1 {
pinctrl-0 = <&adc1_in3_pa3 &adc1_in10_pc0>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <2>;
status = "okay";
};
&dac1 {
pinctrl-0 = <&dac_out1_pa4>;
pinctrl-names = "default";
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&can1 {
pinctrl-0 = <&can1_rx_pd0 &can1_tx_pd1>;
pinctrl-names = "default";
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6 &usart2_rts_pd4 &usart2_cts_pd3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
&timers1 {
status = "okay";
pwm1: pwm {
status = "okay";
pinctrl-0 = <&tim1_ch2_pe11 &tim1_ch3_pe13>;
pinctrl-names = "default";
};
};
&usart6 {
pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12 &usb_otg_fs_id_pa10>;
pinctrl-names = "default";
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&die_temp {
status = "okay";
};
&dma2 {
status = "okay";
};
&iwdg {
status = "okay";
};
&vref {
status = "okay";
};
&rng {
status = "okay";
};
&backup_sram {
status = "okay";
};
&quadspi {
pinctrl-names = "default";
pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb6
&quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12
&quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13>;
flash-id = <1>;
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* sectors 0-3 */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/* sector 4 */
storage_partition: partition@10000 {
label = "storage";
reg = <0x00010000 DT_SIZE_K(64)>;
};
/* sector 5 */
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 DT_SIZE_K(128)>;
};
/* sector 6 */
slot1_partition: partition@40000 {
label = "image-1";
reg = <0x00040000 DT_SIZE_K(128)>;
};
/* sector 7 */
scratch_partition: partition@60000 {
label = "image-scratch";
reg = <0x00060000 DT_SIZE_K(128)>;
};
};
};
``` | /content/code_sandbox/boards/st/nucleo_f722ze/nucleo_f722ze.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,710 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable clock
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```cmake
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
config BOARD_NUCLEO_WBA52CG
select SOC_STM32WBA52XX
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```yaml
board:
name: nucleo_wba52cg
vendor: st
socs:
- name: stm32wba52xx
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/wba/stm32wba52Xg.dtsi>
#include <st/wba/stm32wba52cgux-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32WBA52CG-NUCLEO board";
compatible = "st,stm32wba52cg-nucleo";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds: leds {
compatible = "gpio-leds";
blue_led_1: led_1 {
gpios = <&gpiob 4 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &blue_led_1;
sw0 = &user_button;
};
};
&clk_lsi {
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_hse {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&pll1 {
div-m = <8>;
mul-n = <48>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(96)>;
ahb-prescaler = <1>;
ahb5-prescaler = <4>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb7-prescaler = <1>;
};
&iwdg {
status = "okay";
};
&rtc {
status = "okay";
clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00200000>,
<&rcc STM32_SRC_LSE RTC_SEL(1)>;
prescaler = <32768>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb12 &usart1_rx_pa8>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pb5 &lpuart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_nss_pa12 &spi1_sck_pb4
&spi1_miso_pb3 &spi1_mosi_pa15>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb2 &i2c1_sda_pb1>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&adc4 {
pinctrl-0 = <&adc4_in8_pa1>;
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
stm32_lp_tick_source: &lptim1 {
clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000800>,
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
status = "okay";
};
&rng {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(448)>;
};
slot1_partition: partition@80000 {
label = "image-1";
reg = <0x00080000 DT_SIZE_K(448)>;
};
scratch_partition: partition@f0000 {
label = "image-scratch";
reg = <0x000f0000 DT_SIZE_K(16)>;
};
storage_partition: partition@f4000 {
label = "storage";
reg = <0x000f4000 DT_SIZE_K(48)>;
};
};
};
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,105 |
```unknown
# STM32WBA52CG Nucleo board configuration
if BOARD_NUCLEO_WBA52CG
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_NUCLEO_WBA52CG
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 7 0>, /* A0 */
<1 0 &gpioa 6 0>, /* A1 */
<2 0 &gpioa 2 0>, /* A2 */
<3 0 &gpioa 1 0>, /* A3 */
<4 0 &gpioa 5 0>, /* A4 */
<5 0 &gpioa 0 0>, /* A5 */
<6 0 &gpioa 10 0>, /* D0 */
<7 0 &gpiob 5 0>, /* D1 */
<8 0 &gpiob 7 0>, /* D2 */
<9 0 &gpiob 6 0>, /* D3 */
<10 0 &gpiob 13 0>, /* D4 */
<11 0 &gpiob 14 0>, /* D5 */
<12 0 &gpiob 0 0>, /* D6 */
<13 0 &gpiob 9 0>, /* D7 */
<14 0 &gpiob 15 0>, /* D8 */
<15 0 &gpioa 9 0>, /* D9 */
<16 0 &gpioa 12 0>, /* D10 */
<17 0 &gpioa 15 0>, /* D11 */
<18 0 &gpiob 3 0>, /* D12 */
<19 0 &gpiob 4 0>, /* D13 */
<20 0 &gpiob 1 0>, /* D14 */
<21 0 &gpiob 2 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 493 |
```restructuredtext
.. _nucleo_f722ze_board:
ST Nucleo F722ZE
################
Overview
********
The Nucleo F722ZE board features an ARM Cortex-M7 based STM32F722ZE MCU.
Key Features:
- STM32 microcontroller in LQFP144 package
- USB full-speed/high-speed device
- 3 user LEDs
- 1 user button and 1 reset button
- 32.768 kHz crystal oscillator
- Board connectors:
- USB Micro-AB
- SWD
- ST Zio connector (Arduino Uno R3 compatible)
- ST Morpho connector
- On-board ST-LINK debugger/programmer
- Flexible power supply options, including ST-LINK VBUS and external sources.
.. image:: img/nucleo_f722ze.jpg
:width: 800px
:align: center
:alt: Nucleo F722ZE
Hardware
********
Nucleo F722ZE provides the following hardware components:
- STM32F722ZET6 microcontroller in LQFP144 package
- ARM |reg| Cortex |reg|-M4 with FPU
- Adaptive Real-Time Accelerator (ART Accelerator)
- 216MHz max CPU frequency
- 512 KB flash
- 256 KB RAM
- I2C (3)
- USART/UART (4)
- SPI (5)
- I2S (3)
- SAI (2)
- USB OTG Full-speed (1)
- USB OTG Full-speed/high-speed (1)
- SDMMC (2)
- CAN (1)
- Dual mode Quad-SPI
- Random number generator (RNG)
- 3x 12-bit ADC, up to 2.4 MSPS with 24 channels or 7.2 MSPS in triple-interleaved mode
- 2x 12-bit DAC
- 16-channel DMA controller
- 16-bit timers (13) with PWM, pulse counter, and quadrature features
- 32-bit timers (2) with PWM, pulse counter, and quadrature features
- CRC
- 96-bit unique ID
- Die temperature
Supported Features
==================
+---------------+------------+-------------------------------+
| Interface | Controller | Driver/Component |
+===============+============+===============================+
| NVIC | on-chip | arch/arm |
+---------------+------------+-------------------------------+
| MPU | on-chip | arch/arm |
+---------------+------------+-------------------------------+
| ADC | on-chip | adc |
+---------------+------------+-------------------------------+
| CAN | on-chip | can |
+---------------+------------+-------------------------------+
| USART/UART | on-chip | console, serial |
+---------------+------------+-------------------------------+
| TIMER | on-chip | counter, pwm, timer |
+---------------+------------+-------------------------------+
| DAC | on-chip | dac |
+---------------+------------+-------------------------------+
| DMA | on-chip | dma |
+---------------+------------+-------------------------------+
| GPIO | on-chip | gpio |
+---------------+------------+-------------------------------+
| HWINFO | on-chip | hwinfo |
+---------------+------------+-------------------------------+
| I2C | on-chip | i2c |
+---------------+------------+-------------------------------+
| EXTI | on-chip | interrupt_controller |
+---------------+------------+-------------------------------+
| BACKUP_SRAM | on-chip | memory |
+---------------+------------+-------------------------------+
| QUADSPI | on-chip | memory |
+---------------+------------+-------------------------------+
| PINMUX | on-chip | pinctrl |
+---------------+------------+-------------------------------+
| RCC | on-chip | reset |
+---------------+------------+-------------------------------+
| RTC | on-chip | rtc |
+---------------+------------+-------------------------------+
| DIE_TEMP | on-chip | sensor |
+---------------+------------+-------------------------------+
| VREF | on-chip | sensor |
+---------------+------------+-------------------------------+
| VBAT | on-chip | sensor |
+---------------+------------+-------------------------------+
| SPI | on-chip | spi |
+---------------+------------+-------------------------------+
| USBOTG_HS | on-chip | usb |
+---------------+------------+-------------------------------+
| USBOTG_FS | on-chip | usb |
+---------------+------------+-------------------------------+
| IWDG | on-chip | watchdog |
+---------------+------------+-------------------------------+
| WWDG | on-chip | watchdog |
+---------------+------------+-------------------------------+
| RTC | on-chip | rtc |
+---------------+------------+-------------------------------+
Connections and IOs
===================
- SDMMC1: Pins marked as "SDMMC" on the ST Zio connector.
- D0: PC8 (CN8 pin 2)
- D1: PC9 (CN8 pin 4)
- D2: PC10 (CN8 pin 6)
- D3: PC11 (CN8 pin 8)
- CK: PC12 (CN8 pin 10)
- CMD: PD2 (CN8 pin 12)
- ADC1:
- IN3: PA3 (CN9 pin 1, Arduino A0)
- IN10: PC0 (CN9 pin 3, Arduino A1)
- DAC1:
- OUT1: PA4 (CN7 pin 17)
- I2C2: Pins marked as "I2C" on the ST Zio connector.
- SCL: PF1 (CN9 pin 19)
- SDA: PF0 (CN9 pin 21)
- CAN1: Pins marked as "CAN" on the ST Zio connector.
- RX: PD0 (CN9 pin 25)
- TX: PD1 (CN9 pin 27)
- USART2: Pins marked as "USART" on the ST Zio connector.
- RX: PD6 (CN9 pin 4)
- TX: PD5 (CN9 pin 6)
- RTS: PD4 (CN9 pin 8)
- CTS: PD3 (CN9 pin 10)
- PWM1: Uses TIMER1.
- PE13 (CN10 pin 10, Arduino D3)
- PE11 (CN10 pin 6, Arduino D5)
- USART3: Connected to ST-Link virtual COM port.
- TX: PD8
- RX: PD9
- USART6: Arduino UART port.
- RX: PG9 (CN10 pin 16, Arduino D0)
- TX: PG14 (CN10 pin 14, Arduino D1)
- USBOTG_FS: Connected to USB Micro-AB connector (CN13)
- DM: PA11
- DP: PA12
- ID: PA10
- QUADSPI: Pins marked as "QSPI" on the ST Zio connector.
- CS: PB6 (CN10 pin 13)
- CLK: PB2 (CN10 pin 15)
- IO3: PD13 (CN10 pin 19)
- IO1: PD12 (CN10 pin 21)
- IO0: PD11 (CN10 pin 23)
- IO2: PE2 (CN10 pin 25)
System Clock
------------
By default, the system clock is driven by the external clock supplied by
the ST-LINK interface. Nucleo F722ZE system clock can be driven by internal
or external sources.
Serial Port
-----------
Zephyr console is assigned to UART3 (ST-Link Virtual COM Port) by default,
using 115200 8N1.
Programming and Debugging
*************************
The ``nucleo_f722ze`` can be flashed and debugged in the typical manner.
The Nucleo F722ZE board includes an ST-LINK V2-1 debugger, which can be used
with the OpenOCD version provided with the Zephyr SDK. Refer to
:ref:`build_an_application` and :ref:`application_run` for detailed
instructions.
Flashing
========
Build the :ref:`hello_world` application and flash it using the on-board
ST-LINK interface:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_f722ze
:goals: build flash
Debugging
=========
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_f722ze
:maybe-skip-config:
:goals: debug
J-Link OB Firmware
------------------
Like many other STM32 evaluation boards, the Nucleo F722ZE's on-board ST-LINK
debug interface may be flashed with `SEGGER J-Link OB firmware`_. This
firmware turns the ST-LINK into a J-Link probe. If the on-board debugger has
been re-flashed with J-Link OB firmware, simply append ``--runner jlink`` to
all flashing/debugging commands.
References
**********
More information about the STM32F722ZE:
- `STM32F722ZE on www.st.com`_
- `STM32F722ZE Reference Manual (RM0431)`_ (PDF)
More information about Nucleo F722ZE:
- `Nucleo F722ZE on www.st.com`_
- `STM32 Nucleo-144 User Manual (UM1974)`_ (PDF)
.. _SEGGER J-Link OB firmware:
path_to_url
.. _STM32F722ZE on www.st.com:
path_to_url
.. _STM32F722ZE Reference Manual (RM0431):
path_to_url
.. _Nucleo F722ZE on www.st.com:
path_to_url
.. _STM32 Nucleo-144 User Manual (UM1974):
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_f722ze/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,173 |
```ini
# Note: Using OpenOCD using nucloe_wba52cg requires using STMicroelectronics
# openocd fork. See board documentation for more information
source [find interface/stlink-dap.cfg]
set WORKAREASIZE 0x8000
transport select "dapdirect_swd"
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# STlink Debug clock frequency
set CLOCK_FREQ 8000
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate
source [find target/stm32wbax.cfg]
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 160 |
```yaml
identifier: nucleo_wba52cg
name: ST Nucleo WBA52CG
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
supported:
- gpio
- i2c
- spi
- adc
- watchdog
- rng
- arduino_gpio
- arduino_i2c
- arduino_spi
- counter
ram: 128
flash: 1024
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/nucleo_wba52cg.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```unknown
config BOARD_STM32H750B_DK
select SOC_STM32H750XX
``` | /content/code_sandbox/boards/st/stm32h750b_dk/Kconfig.stm32h750b_dk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
# Enable the internal SMPS regulator
CONFIG_POWER_SUPPLY_LDO=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32h750b_dk/stm32h750b_dk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```cmake
board_runner_args(jlink "--device=STM32H735IG" "--speed=4000")
board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
if(CONFIG_STM32_MEMMAP)
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(stm32cubeprogrammer "--extload=MT25TL01G_STM32H750B-DISCO.stldr")
else()
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw" )
endif()
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32h750b_dk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 182 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h750Xb.dtsi>
#include <st/h7/stm32h750xbhx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32H750B DISCOVERY KIT";
compatible = "st,stm32h750b-dk";
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,flash-controller = &mt25ql512ab1;
zephyr,display = <dc;
};
sdram2: sdram@d0000000 {
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
zephyr,memory-region = "SDRAM2";
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
};
ext_memory: memory@90000000 {
compatible = "zephyr,memory-region";
reg = <0x90000000 DT_SIZE_M(256)>; /* max addressable area */
zephyr,memory-region = "EXTMEM";
/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
};
leds {
compatible = "gpio-leds";
red_led: led_1 {
gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
label = "USER1 LD6";
};
green_led: led_2 {
gpios = <&gpioj 2 GPIO_ACTIVE_LOW>;
label = "USER2 LD7";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led;
led1 = &red_led;
sw0 = &user_button;
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
hse-bypass;
status = "okay";
};
&clk_lse {
status = "okay";
};
<dc {
pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_ph9
<dc_r4_pj3 <dc_r5_pj4 <dc_r6_pj5 <dc_r7_pj6
<dc_g0_pj7 <dc_g1_pj8 <dc_g2_pj9 <dc_g3_pj10
<dc_g4_pj11 <dc_g5_pi0 <dc_g6_pi1 <dc_g7_pk2
<dc_b0_pj12 <dc_b1_pj13 <dc_b2_pj14 <dc_b3_pj15
<dc_b4_pk3 <dc_b5_pk4 <dc_b6_pk5 <dc_b7_pk6
<dc_de_pk7 <dc_clk_pi14 <dc_hsync_pi12 <dc_vsync_pi9>;
pinctrl-names = "default";
disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
ext-sdram = <&sdram2>;
status = "okay";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>,
<&rcc STM32_SRC_PLL3_R NO_SEL>;
width = <480>;
height = <272>;
pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
display-timings {
compatible = "zephyr,panel-timing";
de-active = <1>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
hsync-len = <1>;
vsync-len = <10>;
hback-porch = <43>;
vback-porch = <12>;
hfront-porch = <8>;
vfront-porch = <4>;
};
def-back-color-red = <0xFF>;
def-back-color-green = <0xFF>;
def-back-color-blue = <0xFF>;
};
&pll {
div-m = <5>;
mul-n = <192>;
div-p = <2>;
div-q = <4>;
div-r = <4>;
clocks = <&clk_hse>;
status = "okay";
};
&pll3 {
div-m = <5>;
mul-n = <192>;
div-p = <2>;
div-q = <20>;
div-r = <99>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(480)>;
d1cpre = <1>;
hpre = <2>;
d1ppre = <2>;
d2ppre1 = <2>;
d2ppre2 = <2>;
d3ppre = <2>;
};
&usart3 {
pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&quadspi {
pinctrl-names = "default";
pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk1_ncs_pg6
&quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pf9
&quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6
&quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3
&quadspi_bk2_io2_pg9 &quadspi_bk2_io3_pg14>;
dual-flash;
status = "okay";
mt25ql512ab1: qspi-nor-flash-1@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
spi-bus-width = <4>;
reset-cmd;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 DT_SIZE_M(64)>;
};
};
};
mt25ql512ab2: qspi-nor-flash-2@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
status = "okay";
};
};
&fmc {
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
&fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
&fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
&fmc_d15_pd10>;
pinctrl-names = "default";
status = "okay";
sdram {
status = "okay";
power-up-delay = <100>;
num-auto-refresh = <8>;
mode-register = <0x230>;
refresh-rate = <0x603>;
bank@1 {
reg = <1>;
st,sdram-control = <STM32_FMC_SDRAM_NC_8
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_16
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_3
STM32_FMC_SDRAM_SDCLK_PERIOD_2
STM32_FMC_SDRAM_RBURST_ENABLE
STM32_FMC_SDRAM_RPIPE_1>;
st,sdram-timing = <2 7 4 7 2 2 2>;
};
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
<&rcc STM32_SRC_LSE RTC_SEL(1)>;
status = "okay";
};
``` | /content/code_sandbox/boards/st/stm32h750b_dk/stm32h750b_dk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,217 |
```yaml
identifier: stm32h750b_dk
name: ST STM32H750B Discovery Kit
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 1024
flash: 128
supported:
- arduino_gpio
- gpio
- dma
- flash
- rtc
- memc
vendor: st
``` | /content/code_sandbox/boards/st/stm32h750b_dk/stm32h750b_dk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```restructuredtext
.. _nucleo_wba52cg_board:
ST Nucleo WBA52CG
#################
Overview
********
NUCLEO-WBA52CG is a Bluetooth Low Energy wireless and ultra-low-power board
embedding a powerful and ultra-low-power radio compliant with the Bluetooth
Low Energy SIG specification v5.3.
The ARDUINO Uno V3 connectivity support and the ST morpho headers allow the
easy expansion of the functionality of the STM32 Nucleo open development
platform with a wide choice of specialized shields.
- Ultra-low-power wireless STM32WBA52CG microcontroller based on the Arm
CortexM33 core, featuring 1 Mbyte of flash memory and 128 Kbytes of SRAM in
a UFQFPN48 package
- MCU RF board (MB1863):
- 2.4 GHz RF transceiver supporting Bluetooth specification v5.3
- Arm Cortex M33 CPU with TrustZone, MPU, DSP, and FPU
- Integrated PCB antenna
- Three user LEDs
- Three user and one reset push-buttons
- Board connectors:
- USB Micro-B
- ARDUINO Uno V3 expansion connector
- ST morpho headers for full access to all STM32 I/Os
- Flexible power-supply options: ST-LINK USB VBUS or external sources
- On-board STLINK-V3MODS debugger/programmer with USB re-enumeration capability:
mass storage, Virtual COM port, and debug port
.. image:: img/nucleowba52cg.jpg
:align: center
:alt: Nucleo WBA52CG
More information about the board can be found at the `Nucleo WBA52CG website`_.
Hardware
********
The STM32WBA52xx multiprotocol wireless and ultralow power devices embed a
powerful and ultralow power radio compliant with the Bluetooth SIG Low Energy
specification 5.3. They contain a high-performance Arm Cortex-M33 32-bit RISC
core. They operate at a frequency of up to 100 MHz.
- Includes ST state-of-the-art patented technology
- Ultra low power radio:
- 2.4 GHz radio
- RF transceiver supporting Bluetooth Low Energy 5.3 specification
- Proprietary protocols
- RX sensitivity: -96 dBm (Bluetooth Low Energy at 1 Mbps)
- Programmable output power, up to +10 dBm with 1 dB steps
- Integrated balun to reduce BOM
- Suitable for systems requiring compliance with radio frequency regulations
ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
- Ultra low power platform with FlexPowerControl:
- 1.71 to 3.6 V power supply
- - 40 C to 85 C temperature range
- Autonomous peripherals with DMA, functional down to Stop 1 mode
- 140 nA Standby mode (16 wake-up pins)
- 200 nA Standby mode with RTC
- 2.4 A Standby mode with 64 KB SRAM
- 16.3 A Stop mode with 64 KB SRAM
- 45 A/MHz Run mode at 3.3 V
- Radio: Rx 7.4 mA / Tx at 0 dBm 10.6 mA
- Core: Arm 32-bit Cortex-M33 CPU with TrustZone, MPU, DSP, and FPU
- ART Accelerator: 8-Kbyte instruction cache allowing 0-wait-state execution
from flash memory (frequency up to 100 MHz, 150 DMIPS)
- Power management: embedded regulator LDO supporting voltage scaling
- Benchmarks:
- 1.5 DMIPS/MHz (Drystone 2.1)
- 407 CoreMark (4.07 CoreMark/MHz)
- Clock sources:
- 32 MHz crystal oscillator
- 32 kHz crystal oscillator (LSE)
- Internal low-power 32 kHz (5%) RC
- Internal 16 MHz factory trimmed RC (1%)
- PLL for system clock and ADC
- Memories:
- 1 MB flash memory with ECC, including 256 Kbytes with 100 cycles
- 128 KB SRAM, including 64 KB with parity check
- 512-byte (32 rows) OTP
- Rich analog peripherals (independent supply):
- 12-bit ADC 2.5 Msps with hardware oversampling
- Communication peripherals:
- Three UARTs (ISO 7816, IrDA, modem)
- Two SPIs
- Two I2C Fm+ (1 Mbit/s), SMBus/PMBus
- System peripherals:
- Touch sensing controller, up to 20 sensors, supporting touch key, linear,
rotary touch sensors
- One 16-bit, advanced motor control timer
- Three 16-bit timers
- One 32-bit timer
- Two low-power 16-bit timers (available in Stop mode)
- Two Systick timers
- Two watchdogs
- 8-channel DMA controller, functional in Stop mode
- Security and cryptography:
- Arm TrustZone and securable I/Os, memories, and peripherals
- Flexible life cycle scheme with RDP and password protected debug
- Root of trust thanks to unique boot entry and secure hide protection area (HDP)
- SFI (secure firmware installation) thanks to embedded RSS (root secure services)
- Secure data storage with root hardware unique key (RHUK)
- Secure firmware upgrade support with TF-M
- Two AES co-processors, including one with DPA resistance
- Public key accelerator, DPA resistant
- HASH hardware accelerator
- True random number generator, NIST SP800-90B compliant
- 96-bit unique ID
- Active tampers
- CRC calculation unit
- Up to 35 I/Os (most of them 5 V-tolerant) with interrupt capability
- Development support:
- Serial wire debug (SWD), JTAG
- ECOPACK2 compliant package
More information about STM32WB55RG can be found here:
- `STM32WBA52CG on www.st.com`_
- `STM32WBA52CG datasheet`_
- `STM32WBA52CG reference manual`_
Supported Features
==================
The Zephyr nucleo_wba52cg board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig`
Connections and IOs
===================
Nucleo WBA52CG Board has 4 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
Default Zephyr Peripheral Mapping:
----------------------------------
.. rst-class:: rst-columns
- USART_1 TX/RX : PB12/PA8
- I2C_1_SCL : PB2
- I2C_1_SDA : PB1
- USER_PB : PC13
- LD1 : PB4
- SPI_1_NSS : PA12 (arduino_spi)
- SPI_1_SCK : PB4 (arduino_spi)
- SPI_1_MISO : PB3 (arduino_spi)
- SPI_1_MOSI : PA15 (arduino_spi)
System Clock
------------
Nucleo WBA52CG System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by HSE+PLL clock at 100MHz.
Serial Port
-----------
Nucleo WBA52CG board has 1 U(S)ARTs. The Zephyr console output is assigned to USART1.
Default settings are 115200 8N1.
Programming and Debugging
*************************
Nucleo WBA52CG board includes an ST-LINK/V3 embedded debug tool interface.
It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem tools.
Flashing
========
STM32CubeProgrammer is configured as flashing tool by default.
If available, OpenOCD could be used. Same process applies with both tools.
Flashing an application to Nucleo WBA52CG
-----------------------------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nucleo_wba52cg
:goals: build flash
You will see the LED blinking every second.
Debugging
=========
Debugging using OpenOCD
-----------------------
You can debug an application in the usual way using OpenOCD. Here is an example for the
:zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nucleo_wba52cg
:maybe-skip-config:
:goals: debug
Debugging using STM32CubeIDE
----------------------------
You can debug an application using a STM32WBA compatible version of STM32CubeIDE.
For that:
- Create an empty STM32WBA project by going to File > New > STM32 project
- Select your MCU, click Next, and select an Empty project.
- Right click on your project name, select Debug as > Debug configurations
- In the new window, create a new target in STM32 Cortex-M C/C++ Application
- Select the new target and enter the path to zephyr.elf file in the C/C++ Application field
- Check Disable auto build
- Run debug
.. _Nucleo WBA52CG website:
path_to_url
.. _STM32WBA52CG on www.st.com:
path_to_url
.. _STM32WBA52CG datasheet:
path_to_url
.. _STM32WBA52CG reference manual:
path_to_url
.. _OpenOCD official Github mirror:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,408 |
```unknown
# STM32H750B DISCOVERY board configuration
if BOARD_STM32H750B_DK
if DISPLAY
# MEMC needs to be enabled in order to store
# display buffer to external SDRAM connected to FMC
config MEMC
default y
endif # DISPLAY
endif # BOARD_STM32H750B_DK
``` | /content/code_sandbox/boards/st/stm32h750b_dk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```yaml
board:
name: stm32h750b_dk
vendor: st
socs:
- name: stm32h750xx
``` | /content/code_sandbox/boards/st/stm32h750b_dk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioc 0 0>, /* A0 */
<1 0 &gpiof 8 0>, /* A1 */
<2 0 &gpioa 0 0>, /* A2 */
<3 0 &gpioa 1 0>, /* A3 */
<4 0 &gpioc 2 0>, /* A4 */
<5 0 &gpioc 3 0>, /* A5 */
<6 0 &gpiob 7 0>, /* D0 */
<7 0 &gpiob 6 0>, /* D1 */
<8 0 &gpiog 3 0>, /* D2 */
<9 0 &gpioa 6 0>, /* D3 */
<10 0 &gpiok 1 0>, /* D4 */
<11 0 &gpioa 8 0>, /* D5 */
<12 0 &gpioe 6 0>, /* D6 */
<13 0 &gpioi 8 0>, /* D7 */
<14 0 &gpioe 3 0>, /* D8 */
<15 0 &gpioh 15 0>, /* D9 */
<16 0 &gpiob 4 0>, /* D10 */
<17 0 &gpiob 15 0>, /* D11 */
<18 0 &gpioi 2 0>, /* D12 */
<19 0 &gpiod 3 0>, /* D13 */
<20 0 &gpiod 13 0>, /* D14 */
<21 0 &gpiod 12 0>; /* D15 */
};
};
``` | /content/code_sandbox/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 475 |
```ini
source [find interface/stlink-dap.cfg]
transport select dapdirect_swd
set WORKAREASIZE 0x2000
set CHIPNAME STM32H750XB
set BOARDNAME STM23H750B_DK
source [find target/stm32h7x.cfg]
# Use connect_assert_srst here to be able to program
# even when core is in sleep mode
reset_config srst_only srst_nogate connect_assert_srst
$_CHIPNAME.cpu0 configure -event gdb-attach {
echo "Debugger attaching: halting execution"
gdb_breakpoint_override hard
}
$_CHIPNAME.cpu0 configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
old_init
reset halt
}
``` | /content/code_sandbox/boards/st/stm32h750b_dk/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f7/stm32f746Xg.dtsi>
#include <st/f7/stm32f746zgtx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/*
* WARNING: The pin PA7 will conflict on selection of SPI_1 and ETH_STM32_HAL.
* If you require both peripherals, and you do not need Arduino Uno v3
* compatibility, the pin PB5 (also on ST Zio connector) can be used
* for the SPI_1 MOSI signal.
*/
/ {
model = "STMicroelectronics STM32F746ZG-NUCLEO board";
compatible = "st,stm32f746zg-nucleo";
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,dtcm = &dtcm;
zephyr,canbus = &can1;
};
leds: leds {
compatible = "gpio-leds";
green_led: led_0 {
gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
blue_led: led_1 {
gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
red_led: led_2 {
gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button_0 {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
sw0 = &user_button;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <192>;
div-p = <2>;
div-q = <8>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(192)>;
ahb-prescaler = <1>;
apb1-prescaler = <4>;
apb2-prescaler = <2>;
};
&usart2 {
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6
&usart2_rts_pd4 &usart2_cts_pd3>;
pinctrl-names = "default";
current-speed = <115200>;
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart6 {
pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&timers1 {
st,prescaler = <10000>;
status = "okay";
pwm1: pwm {
status = "okay";
pinctrl-0 = <&tim1_ch3_pe13>;
pinctrl-names = "default";
};
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
&iwdg {
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_rx_pd0 &can1_tx_pd1>;
pinctrl-names = "default";
status = "okay";
};
&dma2 {
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in0_pa0>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <2>;
status = "okay";
};
&dac1 {
pinctrl-0 = <&dac_out1_pa4>;
pinctrl-names = "default";
status = "okay";
};
&rng {
status = "okay";
};
&die_temp {
status = "okay";
};
&mac {
status = "okay";
pinctrl-0 = <ð_mdc_pc1
ð_rxd0_pc4
ð_rxd1_pc5
ð_ref_clk_pa1
ð_mdio_pa2
ð_crs_dv_pa7
ð_tx_en_pg11
ð_txd0_pg13
ð_txd1_pb13>;
pinctrl-names = "default";
};
&backup_sram {
status = "okay";
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_f746zg/nucleo_f746zg.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,446 |
```cmake
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(jlink "--device=STM32F746ZG" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_f746zg/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```restructuredtext
.. _stm32h750b_dk_board:
ST STM32H750B Discovery Kit
###########################
Overview
********
The STM32H750B-DK Discovery kit is a complete demonstration and development
platform for Arm Cortex-M7 core-based STM32H750XBH6 microcontroller, with
128Kbytes of Flash memory and 1 Mbytes of SRAM.
The STM32H750B-DK Discovery kit is used as a reference design for user
application development before porting to the final product, thus simplifying
the application development.
The full range of hardware features available on the board helps users to enhance
their application development by an evaluation of all the peripherals (such as
USB OTG FS, Ethernet, microSD card, USART, CAN FD, SAI audio DAC stereo with
audio jack input and output, MEMS digital microphone, HyperRAM,
Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others).
ARDUINO Uno V3, Pmod and STMod+ connectors provide easy connection to extension
shields or daughterboards for specific applications.
STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and
programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H750B-DK board
comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive
software HAL library as well as various software examples.
.. image:: img/stm32h750b_dk.png
:align: center
:alt: STM32H750B-DK
More information about the board can be found at the `STM32H750B-DK website`_.
More information about STM32H750 can be found here:
- `STM32H750 on www.st.com`_
- `STM32H750xx reference manual`_
- `STM32H750xx datasheet`_
Supported Features
==================
The current Zephyr stm32h750b_dk board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| QSPI NOR | on-chip | off-chip flash |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on Zephyr porting.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/stm32h750b_dk/stm32h750b_dk_defconfig`
Pin Mapping
===========
For more details please refer to `STM32H750B-DK website`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com)
- LD1 : PJ2
- LD2 : PI13
System Clock
============
The STM32H750B System Clock can be driven by an internal or external oscillator,
as well as by the main PLL clock. By default, the System clock
is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock.
Serial Port
===========
The STM32H750B Discovery kit has up to 6 UARTs.
The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual
COM port interface. Default communication settings are 115200 8N1.
Programming and Debugging
*************************
See :ref:`build_an_application` for more information about application builds.
Flashing
========
Connect the STM32H750B-DK to your host computer using the ST-LINK
USB port, then run a serial host program to connect with the board. For example:
.. code-block:: console
$ minicom -b 115200 -D /dev/ttyACM0
You can then build and flash applications in the usual way.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h750b_dk
:goals: build flash
You should see the following message in the serial host program:
.. code-block:: console
$ Hello World! stm32h750b_dk
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h750b_dk
:goals: debug
.. _STM32H750B-DK website:
path_to_url
.. _STM32H750 on www.st.com:
path_to_url
.. _STM32H750xx reference manual:
path_to_url
.. _STM32H750xx datasheet:
path_to_url
``` | /content/code_sandbox/boards/st/stm32h750b_dk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,162 |
```yaml
board:
name: nucleo_f746zg
vendor: st
socs:
- name: stm32f746xx
``` | /content/code_sandbox/boards/st/nucleo_f746zg/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: nucleo_f746zg
name: ST Nucleo F746ZG
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 256
flash: 1024
supported:
- arduino_i2c
- arduino_gpio
- arduino_spi
- uart
- gpio
- netif:eth
- usb_device
- i2c
- pwm
- spi
- watchdog
- counter
- can
- adc
- dac
- dma
- backup_sram
- rtc
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_f746zg/nucleo_f746zg.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 156 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART
CONFIG_SERIAL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_f746zg/nucleo_f746zg_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
config BOARD_NUCLEO_F746ZG
select SOC_STM32F746XX
``` | /content/code_sandbox/boards/st/nucleo_f746zg/Kconfig.nucleo_f746zg | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
# STM32F746ZG Nucleo board configuration
if BOARD_NUCLEO_F746ZG
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
endif # BOARD_NUCLEO_F746ZG
``` | /content/code_sandbox/boards/st/nucleo_f746zg/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 3 0>, /* A0 */
<1 0 &gpioc 0 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpiof 3 0>, /* A3 */
<4 0 &gpiof 5 0>, /* A4 */
<5 0 &gpiof 10 0>, /* A5 */
<6 0 &gpiog 9 0>, /* D0 */
<7 0 &gpiog 14 0>, /* D1 */
<8 0 &gpiof 15 0>, /* D2 */
<9 0 &gpioe 13 0>, /* D3 */
<10 0 &gpiof 14 0>, /* D4 */
<11 0 &gpioe 11 0>, /* D5 */
<12 0 &gpioe 9 0>, /* D6 */
<13 0 &gpiof 13 0>, /* D7 */
<14 0 &gpiof 12 0>, /* D8 */
<15 0 &gpiod 15 0>, /* D9 */
<16 0 &gpiod 14 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_serial: &usart6 {};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
``` | /content/code_sandbox/boards/st/nucleo_f746zg/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 497 |
```ini
source [find board/st_nucleo_f7.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/nucleo_f746zg/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
/*
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/gpio/st-morpho-header.h>
/ {
st_morpho_header: st-morpho-header {
compatible = "st-morpho-header";
#gpio-cells = <2>;
gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
gpio-map = <ST_MORPHO_L_7 0 &gpioh 3 0>,
<ST_MORPHO_L_13 0 &gpioa 13 0>, /* shared with SWD connected to STLINK */
<ST_MORPHO_L_15 0 &gpioa 14 0>, /* shared with SWD connected to STLINK */
<ST_MORPHO_L_17 0 &gpioa 15 0>,
<ST_MORPHO_L_23 0 &gpioc 13 0>,
<ST_MORPHO_L_25 0 &gpioc 14 0>,
<ST_MORPHO_L_27 0 &gpioc 15 0>,
<ST_MORPHO_L_28 0 &gpiob 1 0>,
<ST_MORPHO_L_30 0 &gpiob 2 0>,
<ST_MORPHO_L_32 0 &gpioa 10 0>,
<ST_MORPHO_L_34 0 &gpiob 4 0>,
<ST_MORPHO_L_36 0 &gpiob 14 0>,
<ST_MORPHO_L_38 0 &gpiob 13 0>,
<ST_MORPHO_R_1 0 &gpioa 0 0>,
<ST_MORPHO_R_2 0 &gpioc 4 0>,
<ST_MORPHO_R_3 0 &gpioa 12 0>,
<ST_MORPHO_R_4 0 &gpioc 5 0>,
<ST_MORPHO_R_5 0 &gpioa 11 0>,
<ST_MORPHO_R_11 0 &gpioa 5 0>,
<ST_MORPHO_R_12 0 &gpioc 6 0>,
<ST_MORPHO_R_13 0 &gpioa 6 0>,
<ST_MORPHO_R_14 0 &gpioc 0 0>,
<ST_MORPHO_R_15 0 &gpioa 7 0>,
<ST_MORPHO_R_16 0 &gpioa 8 0>,
<ST_MORPHO_R_17 0 &gpioa 4 0>,
<ST_MORPHO_R_19 0 &gpioa 9 0>,
<ST_MORPHO_R_21 0 &gpioc 2 0>,
<ST_MORPHO_R_22 0 &gpiob 0 0>,
<ST_MORPHO_R_23 0 &gpioc 1 0>,
<ST_MORPHO_R_25 0 &gpiob 10 0>,
<ST_MORPHO_R_26 0 &gpiob 9 0>,
<ST_MORPHO_R_27 0 &gpiob 8 0>,
<ST_MORPHO_R_28 0 &gpiob 15 0>,
<ST_MORPHO_R_29 0 &gpiob 5 0>,
<ST_MORPHO_R_30 0 &gpiob 11 0>,
<ST_MORPHO_R_31 0 &gpiob 3 0>,
<ST_MORPHO_R_33 0 &gpiob 12 0>,
<ST_MORPHO_R_35 0 &gpiob 6 0>, /* SB7=ON, SB2=OFF, SB6=OFF */
<ST_MORPHO_R_36 0 &gpioa 1 0>,
<ST_MORPHO_R_37 0 &gpiob 7 0>, /* SB9=ON, SB4=OFF, SB10=OFF */
<ST_MORPHO_R_38 0 &gpioc 3 0>;
};
};
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/st_morpho_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,007 |
```cmake
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
config BOARD_NUCLEO_WL55JC
select SOC_STM32WL55XX
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/Kconfig.nucleo_wl55jc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/wl/stm32wl55Xc.dtsi>
#include <st/wl/stm32wl55jcix-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include "st_morpho_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32WL55JC-NUCLEO board";
compatible = "st,stm32wl55-nucleo";
chosen {
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds: leds {
compatible = "gpio-leds";
blue_led_1: led_0 {
gpios = <&gpiob 15 GPIO_ACTIVE_HIGH>;
label = "User LED1";
};
green_led_2: led_1 {
gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>;
label = "User LED2";
};
green_led_3: led_2 {
gpios = <&gpiob 11 GPIO_ACTIVE_HIGH>;
label = "User LED3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_1: button_0 {
label = "SW1";
gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_2: button_1 {
label = "SW2";
gpios = <&gpioa 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_1>;
};
user_button_3: button_2 {
label = "SW3";
gpios = <&gpioc 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_2>;
};
};
aliases {
led0 = &green_led_2;
sw0 = &user_button_1;
sw1 = &user_button_2;
sw2 = &user_button_3;
lora0 = &lora;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_lsi {
status = "okay";
};
stm32_lp_tick_source: &lptim1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
status = "okay";
};
&clk_hsi {
status = "okay";
};
&clk_lse {
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <6>;
div-r = <2>;
div-q = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
cpu1-prescaler = <1>;
cpu2-prescaler = <1>;
ahb3-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pa12 &i2c2_sda_pa11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
&spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&dac1 {
pinctrl-0 = <&dac_out1_pa10>;
pinctrl-names = "default";
status = "okay";
};
&timers2 {
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch4_pb11>;
pinctrl-names = "default";
};
};
&adc1 {
pinctrl-0 = <&adc_in5_pb1>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&die_temp {
status = "okay";
};
&aes {
status = "okay";
};
&rng {
status = "okay";
};
&iwdg {
status = "okay";
};
&subghzspi {
status = "okay";
lora: radio@0 {
status = "okay";
tx-enable-gpios = <&gpioc 4 GPIO_ACTIVE_LOW>; /* FE_CTRL1 */
rx-enable-gpios = <&gpioc 5 GPIO_ACTIVE_LOW>; /* FE_CTRL2 */
dio3-tcxo-voltage = <SX126X_DIO3_TCXO_1V7>;
tcxo-power-startup-delay-ms = <5>;
/* High-power output is selected as a consequence of using
* tx/rx-enable-gpio to control FE_CTRL1 and FE_CTRL2. Low-power
* output would require both FE_CTRL1 and FE_CTRL2 to be high,
* which is not currently supported by the driver.
*/
power-amplifier-output = "rfo-hp";
rfo-lp-max-power = <15>;
rfo-hp-max-power = <22>;
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(32)>;
read-only;
};
slot0_partition: partition@8000 {
label = "image-0";
reg = <0x00008000 DT_SIZE_K(104)>;
};
slot1_partition: partition@22000 {
label = "image-1";
reg = <0x00022000 DT_SIZE_K(104)>;
};
/*
* Set 16kB of storage (8x2kB pages) at the end of the 256kB of
* flash.
*/
storage_partition: partition@3c000 {
label = "storage";
reg = <0x0003c000 DT_SIZE_K(16)>;
};
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSE RTC_SEL(1)>;
status = "okay";
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,617 |
```yaml
identifier: nucleo_wl55jc
name: ST Nucleo WL55JC
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 256
supported:
- gpio
- i2c
- spi
- arduino_gpio
- arduino_i2c
- arduino_spi
- adc
- dac
- pwm
- counter
- dma
- watchdog
- nvs
- lora
- rtc
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/nucleo_wl55jc.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 138 |
```yaml
board:
name: nucleo_wl55jc
vendor: st
socs:
- name: stm32wl55xx
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpiob 1 0>, /* A0 */
<1 0 &gpiob 2 0>, /* A1 */
<2 0 &gpioa 10 0>, /* A2 */
<3 0 &gpiob 4 0>, /* A3 */
<4 0 &gpiob 14 0>, /* A4 */
<5 0 &gpiob 13 0>, /* A5 */
<6 0 &gpiob 7 0>, /* D0 */
<7 0 &gpiob 6 0>, /* D1 */
<8 0 &gpiob 12 0>, /* D2 */
<9 0 &gpiob 3 0>, /* D3 */
<10 0 &gpiob 5 0>, /* D4 */
<11 0 &gpiob 8 0>, /* D5 */
<12 0 &gpiob 10 0>, /* D6 */
<13 0 &gpioc 1 0>, /* D7 */
<14 0 &gpioc 2 0>, /* D8 */
<15 0 &gpioa 9 0>, /* D9 */
<16 0 &gpioa 4 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 11 0>, /* D14 */
<21 0 &gpiob 12 0>; /* D15 */
};
};
arduino_serial: &usart1 {};
arduino_i2c: &i2c2 {};
arduino_spi: &spi1 {};
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 505 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32wlx.cfg]
# Debug compatible reset configuration (default)
reset_config srst_only srst_nogate
# Sleep mode compatible reset configuration (stock firmware compatible)
# reset_config srst_only srst_nogate connect_assert_srst
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```restructuredtext
.. _nucleo_f746zg_board:
ST Nucleo F746ZG
################
Overview
********
The STM32 Nucleo-144 boards offer combinations of performance and power that
provide an affordable and flexible way for users to build prototypes and try
out new concepts. For compatible boards, the SMPS significantly reduces power
consumption in Run mode.
The Arduino-compatible ST Zio connector expands functionality of the Nucleo
open development platform, with a wide choice of specialized Arduino* Uno V3
shields.
The STM32 Nucleo-144 board does not require any separate probe as it integrates
the ST-LINK/V2-1 debugger/programmer.
The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
libraries and examples available with the STM32Cube MCU Package.
Key Features
- STM32 microcontroller in LQFP144 package
- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
- USB OTG or full-speed device (depending on STM32 support)
- 3 user LEDs
- 2 user and reset push-buttons
- 32.768 kHz crystal oscillator
- Board connectors:
- USB with Micro-AB
- SWD
- Ethernet RJ45 (depending on STM32 support)
- ST Zio connector including Arduino* Uno V3
- ST morpho
- Flexible power-supply options: ST-LINK USB VBUS or external sources.
- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
- capability: mass storage, virtual COM port and debug port.
- Comprehensive free software libraries and examples available with the
STM32Cube MCU package.
- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers)
.. image:: img/nucleo_f746zg.jpg
:align: center
:alt: Nucleo F746ZG
More information about the board can be found at the `Nucleo F746ZG website`_.
Hardware
********
Nucleo F746ZG provides the following hardware components:
- STM32F746ZG in LQFP144 package
- ARM 32-bit Cortex-M7 CPU with FPU
- Chrom-ART Accelerator
- ART Accelerator
- 216 MHz max CPU frequency
- VDD from 1.7 V to 3.6 V
- 1 MB Flash
- 320 KB SRAM
- 16-bit timers(10)
- 32-bit timers(2)
- SPI(6)
- I2C(4)
- I2S (3)
- USART(4)
- UART(4)
- USB OTG Full Speed and High Speed(1)
- USB OTG Full Speed(1)
- CAN(2)
- SAI(2)
- SPDIF_Rx(4)
- HDMI_CEC(1)
- Dual Mode Quad SPI(1)
- Camera Interface
- GPIO(up to 168) with external interrupt capability
- 12-bit ADC(3) with 24 channels / 2.4 MSPS
- 12-bit DAC with 2 channels(2)
- True Random Number Generator (RNG)
- 16-channel DMA
- LCD-TFT Controller with XGA resolution
Supported Features
==================
The Zephyr nucleo_f746zg board configuration supports the following hardware
features:
+-------------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+=============+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-------------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-------------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-------------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-------------+------------+-------------------------------------+
| ETHERNET | on-chip | ethernet |
+-------------+------------+-------------------------------------+
| USB | on-chip | usb_device |
+-------------+------------+-------------------------------------+
| COUNTER | on-chip | rtc |
+-------------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-------------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-------------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-------------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-------------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-------------+------------+-------------------------------------+
| DAC | on-chip | DAC Controller |
+-------------+------------+-------------------------------------+
| Backup SRAM | on-chip | Backup SRAM |
+-------------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-------------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in
:zephyr_file:`boards/st/nucleo_f746zg/nucleo_f746zg_defconfig`
For more details please refer to `STM32 Nucleo-144 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
The Nucleo F746ZG board features a ST Zio connector (extended Arduino Uno V3)
and a ST morpho connector. Board is configured as follows:
- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3
- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com)
- UART_6 TX/RX : PG14/PG9 (Arduino UART)
- USER_PB : PC13
- LD1 : PB0
- LD2 : PB7
- LD3 : PB14
- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13
- USB DM : PA11
- USB DP : PA12
- I2C : PB8, PB9
- PWM : PE13
- SPI : PD14, PA5, PA6, PA7
- ADC1_IN0 : PA0
- DAC1_OUT1 : PA4
Note. The Arduino Uno v3 specified SPI device conflicts with the on-board ETH
device on pin PA7.
System Clock
------------
Nucleo F746ZG System Clock could be driven by an internal or external
oscillator, as well as the main PLL clock. By default, the System clock is
driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock.
Serial Port
-----------
Nucleo F746ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is
assigned to UART3. Default settings are 115200 8N1.
Backup SRAM
-----------
In order to test backup SRAM you may want to disconnect VBAT from VDD. You can
do it by removing ``SB156`` jumper on the back side of the board.
Programming and Debugging
*************************
Applications for the ``nucleo_f746zg`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Nucleo F746ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
Flashing an application to Nucleo F746ZG
----------------------------------------
The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
so its installation is required to be able to flash the board.
Alternatively, openocd (provided in Zephyr SDK) or JLink can also be used to
flash the board using the ``--runner`` (or ``-r``) option:
.. code-block:: console
$ west flash --runner openocd
$ west flash --runner jlink
Here is an example for the :ref:`hello_world` application.
Run a serial host program to connect with your Nucleo board.
.. code-block:: console
$ minicom -b 115200 -D /dev/ttyACM0
Build and flash the application:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_f746zg
:goals: build flash
You should see the following message on the console:
.. code-block:: console
$ Hello World! nucleo_f746zg
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_f746zg
:maybe-skip-config:
:goals: debug
.. _Nucleo F746ZG website:
path_to_url
.. _STM32 Nucleo-144 board User Manual:
path_to_url
.. _STM32F746ZG on www.st.com:
path_to_url
.. _STM32F746 reference manual:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_f746zg/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,013 |
```unknown
config BOARD_STM32L4R9I_DISCO
select SOC_STM32L4R9XX
``` | /content/code_sandbox/boards/st/stm32l4r9i_disco/Kconfig.stm32l4r9i_disco | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```cmake
board_runner_args(jlink "--device=STM32L4R9AI" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32l4r9i_disco/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```yaml
identifier: stm32l4r9i_disco
name: ST STM32L4R9I Discovery
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 640
flash: 2048
vendor: st
supported:
- adc
- arduino_gpio
- arduino_i2c
- arduino_spi
- gpio
- i2c
- pwm
- rtc
- spi
- uart
- usb
- usb_device
``` | /content/code_sandbox/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable clocks
CONFIG_CLOCK_CONTROL=y
# Enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```yaml
board:
name: stm32l4r9i_disco
vendor: st
socs:
- name: stm32l4r9xx
``` | /content/code_sandbox/boards/st/stm32l4r9i_disco/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```restructuredtext
.. _nucleo_wl55jc_board:
ST Nucleo WL55JC
################
Overview
********
The NUCLEO-WL55JC STM32WL Nucleo-64 board provides an affordable and flexible
way for users to try out new concepts and build prototypes with the STM32WL
Series microcontroller, choosing from the various combinations of performance,
power consumption, and features.
- STM32WL55JC microcontroller multiprotocol LPWAN dual-core 32-bit
(Arm Cortex-M4/M0+ at 48 MHz) in UFBGA73 package featuring:
- Ultra-low-power MCU
- RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa,
(G)FSK, (G)MSK, and BPSK modulations
- 256-Kbyte Flash memory and 64-Kbyte SRAM
- 3 user LEDs
- 3 user buttons and 1 reset push-button
- 32.768 kHz LSE crystal oscillator
- 32 MHz HSE on-board oscillator
- Board connectors:
- USB with Micro-B
- MIPI debug connector
- ARDUINO Uno V3 expansion connector
- ST morpho extension pin headers for full access to all STM32WL I/Os
- Delivered with SMA antenna
- Flexible power-supply options: ST-LINK, USB VBUS, or external sources
- On-board STLINK-V3 debugger/programmer with USB re-enumeration capability:
mass storage, Virtual COM port, and debug port
- Comprehensive free software libraries and examples available with the
STM32CubeWL MCU Package
- Support of a wide choice of Integrated Development Environments (IDEs)
including IAR Embedded Workbench, MDK-ARM, and STM32CubeIDE
- Suitable for rapid prototyping of end nodes based on LoRaWAN, Sigfox, wM-Bus,
and many other proprietary protocols
- Fully open hardware platform
.. image:: img/nucleo_wl55jc.jpg
:align: center
:alt: Nucleo WL55JC
More information about the board can be found at the `Nucleo WL55JC website`_.
Hardware
********
The STM32WL55JC long-range wireless and ultra-low-power devices embed a powerful
and ultra-low-power LPWAN-compliant radio solution, enabling the following
modulations: LoRa, (G)FSK, (G)MSK, and BPSK
It provides the following hardware capabilities:
- Radio
- Frequency range: 150 MHz to 960 MHz
- Modulation: LoRa, (G)FSK, (G)MSK and BPSK
- RX sensitivity: 123 dBm for 2-FSK(at 1.2 Kbit/s), 148 dBm for LoRa
(at 10.4 kHz, spreading factor 12)
- Transmitter high output power, programmable up to +22 dBm
- Transmitter low output power, programmable up to +15 dBm
- Compliant with the following radio frequency regulations such as
ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, 101
and the Japanese ARIB STD-T30, T-67, T-108
- Compatible with standardized or proprietary protocols such as LoRaWAN,
Sigfox, W-MBus and more (fully open wireless system-on-chip)
- Core
- 32-bit Arm Cortex-M4 CPU
- Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state
execution from Flash memory, frequency up to 48 MHz, MPU
and DSP instructions
- 1.25 DMIPS/MHz (Dhrystone 2.1)
- 32-bit ArmCortex-M0+ CPU
- Frequency up to 48 MHz, MPU
- 0.95 DMIPS/MHz (Dhrystone 2.1)
- Security and identification
- Hardware encryption AES 256-bit
- True random number generator (RNG)
- Sector protection against read/write operations (PCROP, RDP, WRP)
- CRC calculation unit
- Unique device identifier (64-bit UID compliant with IEEE 802-2001 standard)
- 96-bit unique die identifier
- Hardware public key accelerator (PKA)
- Key management services
- Secure sub-GHz MAC layer
- Secure firmware update (SFU)
- Secure firmware install (SFI)
- Supply and reset management
- High-efficiency embedded SMPS step-down converter
- SMPS to LDO smart switch
- Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds
- Ultra-low-power POR/PDR
- Programmable voltage detector (PVD)
- VBAT mode with RTC and 20x32-byte backup registers
- Clock sources
- 32 MHz crystal oscillator
- TCXO support: programmable supply voltage
- 32 kHz oscillator for RTC with calibration
- High-speed internal 16 MHz factory trimmed RC ( 1 %)
- Internal low-power 32 kHz RC
- Internal multi-speed low-power 100 kHz to 48 MHz RC
- PLL for CPU, ADC and audio clocks
- Memories
- 256-Kbyte Flash memory
- 64-Kbyte RAM
- 20x32-bit backup register
- Bootloader supporting USART and SPI interfaces
- OTA (over-the-air) firmware update capable
- Sector protection against read/write operations
- Rich analog peripherals (down to 1.62 V)
- 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling,
conversion range up to 3.6 V
- 12-bit DAC, low-power sample-and-hold
- 2x ultra-low-power comparators
- System peripherals
- Mailbox and semaphores for communication between Cortex-M4 and Cortex-M0+
firmware
- Controllers
- 2x DMA controller (7 channels each) supporting ADC, DAC, SPI, I2C, LPUART,
USART, AES and timers
- 2x USART (ISO 7816, IrDA, SPI)
- 1x LPUART (low-power)
- 2x SPI 16 Mbit/s (1 over 2 supporting I2S)
- 3x I2C (SMBus/PMBus)
- 2x 16-bit 1-channel timer
- 1x 16-bit 4-channel timer (supporting motor control)
- 1x 32-bit 4-channel timer
- 3x 16-bit ultra-low-power timer
- 1x RTC with 32-bit sub-second wakeup counter
- 1x independent SysTick
- 1x independent watchdog
- 1x window watchdog
- Up to 43 I/Os, most 5 V-tolerant
- Development support
- Serial-wire debug (SWD), JTAG
- Dual CPU cross trigger capabilities
More information about STM32WL55JC can be found here:
- `STM32WL55JC on www.st.com`_
- `STM32WL55JC datasheet`_
- `STM32WL55JC reference manual`_
Supported Features
==================
The Zephyr nucleo_wl55jc board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| AES | on-chip | crypto |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock_control |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| RADIO | on-chip | LoRa |
+-----------+------------+-------------------------------------+
| RNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+
| DAC | on-chip | DAC Controller |
+-----------+------------+-------------------------------------+
| die-temp | on-chip | die temperature sensor |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in:
- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig`
- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc.dts`
Connections and IOs
===================
Nucleo WL55JC Board has 4 GPIO controllers. These controllers are responsible
for pin muxing, input/output, pull-up, etc.
Default Zephyr Peripheral Mapping:
----------------------------------
.. rst-class:: rst-columns
- LPUART_1 TX/RX : PA3/PA2 (ST-Link Virtual Port Com)
- I2C_2_SCL : PA12 (Arduino I2C)
- I2C_2_SDA : PA11 (Arduino I2C)
- SPI_1_NSS : PA4 (arduino_spi)
- SPI_1_SCK : PA5 (arduino_spi)
- SPI_1_MISO : PA6 (arduino_spi)
- SPI_1_MOSI : PA7 (arduino_spi)
- ADC1_IN5 : PB1 (Arduino pin A0)
- DAC1_OUT1 : PA10 (Arduino pin A2)
System Clock
------------
Nucleo WL55JC System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by HSE clock at
32MHz.
Serial Port
-----------
Nucleo WL55JC board has 2 (LP)U(S)ARTs. The Zephyr console output is assigned
to LPUART_1.
Default settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``nucleo_wl55jc`` board configuration can be built the
usual way (see :ref:`build_an_application`).
Flashing
========
Nucleo WL55JC board includes an STLINK-V3 embedded debug tool
interface. This interface is supported by the openocd version included in the
Zephyr SDK since v0.11.0.
You can also choose the ``stm32cubeprogrammer`` runner.
Flashing an application to Nucleo WL55JC
----------------------------------------
Connect the Nucleo WL55JC to your host computer using the USB port.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your Nucleo board:
.. code-block:: console
$ minicom -D /dev/ttyUSB0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_wl55jc
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! arm
.. Note:
Nucleo WL55JC board is provided with a stock firmware which demonstrates
sleep mode. Unfortunately, default openocd configuration, which is debug
compatible, doesn't allow flashing when SoC is in sleep mode.
As a consequence, when flashing Nucleo WL55JC board over a stock firmware,
please update board's openocd.cfg configuration file to select sleep mode
compatible configuration.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nucleo_wl55jc
:maybe-skip-config:
:goals: debug
.. _Nucleo WL55JC website:
path_to_url
.. _STM32WL55JC on www.st.com:
path_to_url
.. _STM32WL55JC datasheet:
path_to_url
.. _STM32WL55JC reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,872 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 7 0>, /* A0 */
<1 0 &gpioc 4 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpiob 0 0>, /* A3 */
<4 0 &gpioa 0 0>, /* A4 */
<5 0 &gpioa 5 0>, /* A5 */
<6 0 &gpioc 0 0>, /* D0 */
<7 0 &gpioc 1 0>, /* D1 */
<8 0 &gpiog 11 0>, /* D2 */
<9 0 &gpiof 10 0>, /* D3 */
<10 0 &gpiog 6 0>, /* D4 */
<11 0 &gpioa 1 0>, /* D5 */
<12 0 &gpiob 4 0>, /* D6 */
<13 0 &gpioa 4 0>, /* D7 */
<14 0 &gpioh 15 0>, /* D8 */
<15 0 &gpioh 13 0>, /* D9 */
<16 0 &gpioi 0 0>, /* D10 */
<17 0 &gpiob 15 0>, /* D11 */
<18 0 &gpiob 14 0>, /* D12 */
<19 0 &gpiob 13 0>, /* D13 */
<20 0 &gpiog 8 0>, /* D14 */
<21 0 &gpiog 7 0>; /* D15 */
};
};
arduino_i2c: &i2c3 {};
arduino_spi: &spi2 {};
``` | /content/code_sandbox/boards/st/stm32l4r9i_disco/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 516 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/l4/stm32l4r9Xi.dtsi>
#include <st/l4/stm32l4r9a(g-i)ix-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "arduino_r3_connector.dtsi"
/ {
model = "STMicroelectronics STM32L4R9I-DISCO board";
compatible = "st,stm32l4r9i-disco";
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
/* N.B. LD1 (orange) is not wired to MCU */
green_led: led_2 {
gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
joy_sel: joystick_selection {
label = "joystick selection";
gpios = <&gpioc 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
zephyr,code = <INPUT_KEY_ENTER>;
};
};
aliases {
led0 = &green_led;
sw0 = &joy_sel;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_lse {
status = "okay";
};
&clk_lsi {
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&clk_msi {
status = "okay";
msi-range = <6>;
msi-pll-mode;
};
&pll {
status = "okay";
div-m = <1>;
mul-n = <60>;
/*
* WORKAROUND: stm32l4-pll-clock does not allow arbitrary PLLP dividers.
* Disable PLLP completely since it only feeds SAI, which is not active either.
*/
/* div-p = <5>; */
div-q = <2>;
div-r = <2>;
clocks = <&clk_msi>;
};
&rcc {
clocks = <&pll>;
ahb-prescaler = <1>;
clock-frequency = <DT_FREQ_M(120)>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&usart2 {
status = "okay";
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
};
&lpuart1 {
status = "okay";
pinctrl-0 = <&lpuart1_tx_pc1 &lpuart1_rx_pc0>;
pinctrl-names = "default";
current-speed = <115200>;
};
&timers3 {
status = "okay";
pwm3: pwm {
status = "okay";
/*
* N.B.: Datasheet indicates that ARD_D11 (wired to PB15) is connected to TIM3_CH2.
* However, this is incorrect as PB15 cannot be muxed to TIM3 (see DS12023).
* Moved ARD_D11 to TIM15_CH2 instead.
*/
pinctrl-0 = <&tim3_ch1_pb4>;
pinctrl-names = "default";
};
};
&timers5 {
status = "okay";
pwm5: pwm {
status = "okay";
pinctrl-0 = <&tim5_ch2_pa1 &tim5_ch4_pi0>;
pinctrl-names = "default";
};
};
&timers8 {
status = "okay";
pwm8: pwm {
status = "okay";
pinctrl-0 = <&tim8_ch1n_ph13>;
pinctrl-names = "default";
};
};
&timers15 {
status = "okay";
pwm15: pwm {
status = "okay";
pinctrl-0 = <&tim15_ch2_pf10 &tim15_ch2_pb15>;
pinctrl-names = "default";
};
};
&i2c1 {
status = "okay";
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pg13>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
};
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3_scl_pg7 &i2c3_sda_pg8>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
};
&spi2 {
status = "okay";
pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
cs-gpios = <&gpioi 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSE RTC_SEL(1)>;
status = "okay";
};
&sdmmc1 {
status = "okay";
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
pinctrl-names = "default";
};
&adc1 {
status = "okay";
pinctrl-0 = <&adc1_in5_pa0 &adc1_in12_pa7 &adc1_in15_pb0
&adc1_in4_pc3 &adc1_in13_pc4>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <1>;
};
zephyr_udc0: &usbotg_fs {
status = "okay";
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12
&usb_otg_fs_id_pa10>;
pinctrl-names = "default";
};
&die_temp {
status = "okay";
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
&octospi2 {
status = "okay";
pinctrl-0 = <&octospim_p2_clk_pi6 &octospim_p2_ncs_pg12
&octospim_p2_io0_pi11 &octospim_p2_io1_pi10
&octospim_p2_io2_pi9 &octospim_p2_io3_ph8
&octospim_p2_io4_ph9 &octospim_p2_io5_ph10
&octospim_p2_io6_pg9 &octospim_p2_io7_pg10
&octospim_p2_dqs_pg15>;
pinctrl-names = "default";
mx25lm51245: ospi-nor-flash@90000000 {
status = "okay";
compatible = "st,stm32-ospi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
ospi-max-frequency = <DT_FREQ_M(25)>;
spi-bus-width = <OSPI_OPI_MODE>;
data-rate = <OSPI_STR_TRANSFER>;
four-byte-opcodes;
sfdp-bfp = [
53 46 44 50 06 01 02 ff
00 06 01 10 30 00 00 ff
c2 00 01 04 10 01 00 ff
84 00 01 02 c0 00 00 ff
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
e5 20 fb ff ff ff ff 1f
44 eb 08 6b 08 3b 04 bb
fe ff ff ff ff ff 00 ff
ff ff 44 eb 0c 20 0f 52
10 d8 00 ff d6 49 c5 00
81 df 04 e3 44 03 67 38
30 b0 30 b0 f7 bd d5 5c
4a 9e 29 ff f0 50 f9 85
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
7f ef ff ff 21 5c dc ff
];
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 DT_SIZE_M(64)>;
};
};
};
};
``` | /content/code_sandbox/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,190 |
```ini
source [find board/stm32l4discovery.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/stm32l4r9i_disco/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```restructuredtext
.. _stm32l4r9i_disco_board:
ST STM32L4R9I Discovery
#######################
Overview
********
The 32L4R9IDISCOVERY Discovery kit is a complete demonstration and development platform
for STMicroelectronics Arm Cortex-M4 core-based STM32L4R9AI microcontroller.
Leveraging the innovative ultra-low-power oriented features, 640 Kbytes of embedded RAM,
graphics performance (Chrom-ART Accelerator), and DSI controller offered by the STM32L4R9AI,
the 32L4R9IDISCOVERY Discovery kit enables users to easily prototype applications with
state-of-the-art energy efficiency, as well as stunning audio and graphics rendering with direct
support for AMOLED DSI round LCD display.
For even more user-friendliness, the on-board ST-LINK/V2-1 debugger provides out-of-the-box
programming and debugging capabilities.
.. image:: img/stm32l4r9i_disco.jpg
:align: center
:alt: STM32L4R9I-DISCO
More information about the board can be found at the `STM32L4R9I-DISCOVERY website`_.
More information about STM32L4R9 can be found here:
- `STM32L4R9/S9 on www.st.com`_
- `STM32L4+ Series reference manual`_
- `STM32L4R5xx/R7xx/R9xx datasheet`_
Supported Features
==================
The current Zephyr stm32l4r9i_disco board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | on-chip flash memory; |
| | | external OctoSPI memory |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+
| RTC | on-chip | Real Time Clock |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| SDMMC | on-chip | sd/mmc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on Zephyr porting.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig`
Pin Mapping
===========
For more details, please refer to `STM32L4R9I-DISCOVERY website`_.
System Clock
============
The STM32L4R9AI System Clock can be driven by an internal or external oscillator,
as well as by the main PLL clock. By default, the System clock is driven by
the PLL clock at 120MHz. PLL clock is driven by a 4MHz medium speed internal clock.
Serial Port
===========
The STM32L4R9I Discovery board has up to 6 U(S)ARTs.
The Zephyr console output is assigned to UART2, which is connected to the onboard
ST-LINK Virtual COM port interface. Default communication settings are 115200 8N1.
Programming and Debugging
*************************
Flashing
========
The STM32L4R9I Discovery board includes an ST-LINK/V2-1 debug tool.
Applications for the ``stm32l4r9i_disco`` board configuration can be
built and flashed in the usual way (see :ref:`build_an_application`
and :ref:`application_run` for more details).
Flashing an application to STM32L4R9I Discovery
-----------------------------------------------
Connect the STM32L4R9I Discovery to your host computer using the ST-LINK
USB port, then run a serial host program to connect with the board. For example:
.. code-block:: console
$ minicom -b 115200 -D /dev/ttyACM0
You can then build and flash applications in the usual way.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32l4r9i_disco
:goals: build flash
You should see the following message in the serial host program:
.. code-block:: console
$ Hello World! stm32l4r9i_disco
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32l4r9i_disco
:goals: debug
.. _STM32L4R9I-DISCOVERY website:
path_to_url
.. _STM32L4R9/S9 on www.st.com:
path_to_url
.. _STM32L4+ Series reference manual:
path_to_url
.. _STM32L4R5xx/R7xx/R9xx datasheet:
path_to_url
``` | /content/code_sandbox/boards/st/stm32l4r9i_disco/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,251 |
```cmake
if(CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M7)
board_runner_args(jlink "--device=STM32H747ZI_M7")
board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m7.cfg")
board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
elseif(CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M4)
board_runner_args(jlink "--device=STM32H747ZI_M4")
board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m4.cfg")
board_runner_args(openocd --target-handle=_CHIPNAME.cpu1)
endif()
if(CONFIG_STM32_MEMMAP)
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(stm32cubeprogrammer "--extload=MT25TL01G_STM32H747I-DISCO.stldr")
else()
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
endif()
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32h747i_disco/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 314 |
```yaml
identifier: stm32h747i_disco/stm32h747xx/m4
name: ST STM32H747I Discovery (M4)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 288
flash: 1024
supported:
- arduino_gpio
- gpio
testing:
ignore_tags:
- mpu
- nfc
- net
vendor: st
``` | /content/code_sandbox/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```yaml
identifier: stm32h747i_disco/stm32h747xx/m7
name: ST STM32H747I Discovery (M7)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 512
flash: 1024
supported:
- arduino_gpio
- gpio
- arduino_spi
- spi
- netif:eth
- qspi
- memc
- usb_device
vendor: st
``` | /content/code_sandbox/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h747Xi_m4.dtsi>
#include <st/h7/stm32h747xihx-pinctrl.dtsi>
#include "stm32h747i_disco.dtsi"
/ {
model = "STMicroelectronics STM32H747I DISCOVERY board";
compatible = "st,stm32h747i-disco";
/* HW resources are split between CM7 and CM4 */
chosen {
/* zephyr,console = &usart1; */
/* zephyr,shell-uart = &usart1; */
zephyr,sram = &sram1;
zephyr,flash = &flash1;
};
leds {
red_led_3:led_3 {
status = "okay";
};
blue_led_4:led_4 {
status = "okay";
};
};
gpio_keys {
joy_center: joystick_center {
status = "okay";
};
};
aliases {
led0 = &blue_led_4;
led1 = &red_led_3;
sw0 = &joy_center;
};
};
&rcc {
clock-frequency = <DT_FREQ_M(200)>;
};
&usart1 {
/* status = "okay"; */
};
&uart8 {
status = "okay";
};
arduino_serial: &uart8 {};
``` | /content/code_sandbox/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 313 |
```linker script
/*
*
*/
#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay)
GROUP_START(SDRAM2)
SECTION_PROLOGUE(_STM32_SDRAM2_SECTION_NAME, (NOLOAD),)
{
*(.lvgl_buf)
} GROUP_LINK_IN(SDRAM2)
GROUP_END(SDRAM2)
#endif
``` | /content/code_sandbox/boards/st/stm32h747i_disco/dc_ram.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
# Enable GPIO
CONFIG_GPIO=y
# Clock configuration
CONFIG_CLOCK_CONTROL=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART driver
CONFIG_SERIAL=y
# By default CONSOLE is assigned to m7
#CONFIG_CONSOLE=y
#CONFIG_UART_CONSOLE=y
# Enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
/*
*
*/
/ {
pmod0: pmod-connector {
compatible = "digilent,pmod";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 11 0>, /* IO1 */
<1 0 &gpioc 3 0>, /* IO2 */
<2 0 &gpioc 2 0>, /* IO3 */
<3 0 &gpioa 12 0>, /* IO4 */
<4 0 &gpioc 6 0>, /* IO5 */
<5 0 &gpioj 13 0>; /* IO6 */
/* IO7 - not connected */
/* IO8 - not connected */
};
};
``` | /content/code_sandbox/boards/st/stm32h747i_disco/pmod_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```yaml
board:
name: stm32h747i_disco
vendor: st
socs:
- name: stm32h747xx
``` | /content/code_sandbox/boards/st/stm32h747i_disco/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h747Xi_m7.dtsi>
#include <st/h7/stm32h747xihx-pinctrl.dtsi>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
#include "stm32h747i_disco.dtsi"
/ {
model = "STMicroelectronics STM32H747I DISCOVERY board";
compatible = "st,stm32h747i-disco";
/* HW resources are split between CM7 and CM4 */
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,flash-controller = &mt25ql512ab1;
};
sdram2: sdram@d0000000 {
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xd0000000 DT_SIZE_M(32)>;
zephyr,memory-region = "SDRAM2";
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
};
ext_memory: memory@90000000 {
compatible = "zephyr,memory-region";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
zephyr,memory-region = "EXTMEM";
/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
};
leds {
green_led_1:led_1 {
status = "okay";
};
orange_led_2:led_2 {
status = "okay";
};
};
gpio_keys {
wake_up: button {
status = "okay";
};
};
otghs_ulpi_phy: otghs_ulpis_phy {
compatible = "usb-ulpi-phy";
#phy-cells = <0>;
};
aliases {
led0 = &green_led_1;
led1 = &orange_led_2;
sw0 = &wake_up;
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&pll {
div-m = <5>;
mul-n = <160>;
div-p = <2>;
div-q = <4>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&pll2 {
div-m = <5>;
mul-n = <96>;
div-p = <2>;
div-q = <4>;
div-r = <10>;
clocks = <&clk_hse>; /* Assuming 25MHz HSE */
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(400)>;
};
&usart1 {
status = "okay";
};
&uart8 {
/* status = "okay"; */
};
&spi5 {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set 2KB of storage at the end of first 1MB flash */
storage_partition: partition@ff800 {
label = "storage";
reg = <0x000ff800 DT_SIZE_K(2)>;
};
};
};
&mac {
/*
* From UM2411 Rev 4:
* With the default setting, the Ethernet feature is not working due
* of a pin conflict between ETH_MDC and SAI4_D1 of the MEMs digital
* microphone.
* Cf Ethernet section in board documentation for more information on
* the hw modification to be done to enable it.
*/
status = "okay";
pinctrl-0 = <ð_ref_clk_pa1
ð_crs_dv_pa7
ð_rxd0_pc4
ð_rxd1_pc5
ð_tx_en_pg11
ð_txd0_pg13
ð_txd1_pg12>;
pinctrl-names = "default";
};
&mdio {
status = "okay";
pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};
&rng {
status = "okay";
};
&fmc {
status = "okay";
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4 &fmc_nbl3_pi5
&fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
&fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
&fmc_d15_pd10 &fmc_d16_ph8 &fmc_d17_ph9 &fmc_d18_ph10
&fmc_d19_ph11 &fmc_d20_ph12 &fmc_d21_ph13 &fmc_d22_ph14
&fmc_d23_ph15 &fmc_d24_pi0 &fmc_d25_pi1 &fmc_d26_pi2
&fmc_d27_pi3 &fmc_d28_pi6 &fmc_d29_pi7 &fmc_d30_pi9
&fmc_d31_pi10>;
pinctrl-names = "default";
sdram {
status = "okay";
power-up-delay = <100>;
num-auto-refresh = <8>;
mode-register = <0x220>;
refresh-rate = <603>;
bank@1 {
reg = <1>;
st,sdram-control = <STM32_FMC_SDRAM_NC_9
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_32
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_2
STM32_FMC_SDRAM_SDCLK_PERIOD_2
STM32_FMC_SDRAM_RBURST_ENABLE
STM32_FMC_SDRAM_RPIPE_0>;
st,sdram-timing = <2 6 4 6 2 2 2>;
};
};
};
zephyr_udc0: &usbotg_hs {
pinctrl-0 = <&usb_otg_hs_ulpi_ck_pa5
&usb_otg_hs_ulpi_d0_pa3
&usb_otg_hs_ulpi_d1_pb0
&usb_otg_hs_ulpi_d2_pb1
&usb_otg_hs_ulpi_d3_pb10
&usb_otg_hs_ulpi_d4_pb11
&usb_otg_hs_ulpi_d5_pb12
&usb_otg_hs_ulpi_d6_pb13
&usb_otg_hs_ulpi_d7_pb5
&usb_otg_hs_ulpi_stp_pc0
&usb_otg_hs_ulpi_dir_pi11
&usb_otg_hs_ulpi_nxt_ph4>;
pinctrl-names = "default";
maximum-speed = "high-speed";
/* Include the USB1ULPIEN clock enable bit */
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x06000000>,
<&rcc STM32_SRC_HSI48 USB_SEL(3)>;
phys = <&otghs_ulpi_phy>;
status = "okay";
};
&sdmmc1 {
status = "okay";
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>,
<&rcc STM32_SRC_PLL2_R SDMMC_SEL(1)>;
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
&sdmmc1_d4_pb8 &sdmmc1_d5_pb9
&sdmmc1_d6_pc6 &sdmmc1_d7_pc7
&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
pinctrl-names = "default";
cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
};
&quadspi {
pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pg6
&quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pf9
&quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6
&quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3
&quadspi_bk2_io2_pg9 &quadspi_bk2_io3_pg14>;
pinctrl-names = "default";
dual-flash;
status = "okay";
mt25ql512ab1: qspi-nor-flash-1@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
spi-bus-width = <4>;
reset-cmd;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 DT_SIZE_M(64)>;
};
};
};
mt25ql512ab2: qspi-nor-flash-2@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
status = "okay";
};
};
arduino_spi: &spi5 {};
``` | /content/code_sandbox/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,499 |
```unknown
# STM32H747I DISCOVERY board configuration
if BOARD_STM32H747I_DISCO
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
config DISK_DRIVER_SDMMC
default y if DISK_DRIVERS
endif # BOARD_STM32H747I_DISCO
``` | /content/code_sandbox/boards/st/stm32h747i_disco/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
# Enable the internal SMPS regulator
CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
# Enable GPIO
CONFIG_GPIO=y
# Enable clocks
CONFIG_CLOCK_CONTROL=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Disable following to assign serial ports to m4 core
# Enable uart driver
CONFIG_SERIAL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 4 0>, /* A0 */
<1 0 &gpiof 10 0>, /* A1 */
<2 0 &gpioa 0 0>, /* A2 */
<3 0 &gpioa 1 0>, /* A3 */
<4 0 &gpioc 2 0>, /* A4 */
<5 0 &gpioc 3 0>, /* A5 */
<6 0 &gpioj 9 0>, /* D0 */
<7 0 &gpioj 8 0>, /* D1 */
<8 0 &gpioj 3 0>, /* D2 */
<9 0 &gpiof 8 0>, /* D3 */
<10 0 &gpioj 4 0>, /* D4 */
<11 0 &gpioa 6 0>, /* D5 */
<12 0 &gpioj 7 0>, /* D6 */
<13 0 &gpioj 0 0>, /* D7 */
<14 0 &gpioj 5 0>, /* D8 */
<15 0 &gpioj 6 0>, /* D9 */
<16 0 &gpiok 1 0>, /* D10 */
<17 0 &gpioj 10 0>, /* D11 */
<18 0 &gpioj 11 0>, /* D12 */
<19 0 &gpiok 0 0>, /* D13 */
<20 0 &gpiod 13 0>, /* D14 */
<21 0 &gpiod 12 0>; /* D15 */
};
};
``` | /content/code_sandbox/boards/st/stm32h747i_disco/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 469 |
```unknown
# STM32H747I DISCOVERY board configuration
config BOARD_STM32H747I_DISCO
select SOC_STM32H747XX_M7 if BOARD_STM32H747I_DISCO_STM32H747XX_M7
select SOC_STM32H747XX_M4 if BOARD_STM32H747I_DISCO_STM32H747XX_M4
``` | /content/code_sandbox/boards/st/stm32h747i_disco/Kconfig.stm32h747i_disco | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
set DUAL_BANK 1
set DUAL_CORE 1
source [find target/stm32h7x.cfg]
reset_config srst_only srst_nogate connect_assert_srst
``` | /content/code_sandbox/boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m4.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32h7x.cfg]
# Use connect_assert_srst here to be able to program
# even when core is in sleep mode
reset_config srst_only srst_nogate connect_assert_srst
$_CHIPNAME.cpu0 configure -event gdb-attach {
echo "Debugger attaching: halting execution"
gdb_breakpoint_override hard
}
$_CHIPNAME.cpu0 configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
old_init
reset halt
}
``` | /content/code_sandbox/boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m7.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 167 |
```unknown
/*
*
*/
#include "arduino_r3_connector.dtsi"
#include "pmod_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
leds {
compatible = "gpio-leds";
green_led_1:led_1 {
gpios = <&gpioi 12 GPIO_ACTIVE_LOW>;
label = "User LD1";
status = "disabled";
};
orange_led_2:led_2 {
gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
label = "User LD2";
status = "disabled";
};
red_led_3:led_3 {
gpios = <&gpioi 14 GPIO_ACTIVE_LOW>;
label = "User LD3";
status = "disabled";
};
blue_led_4:led_4 {
gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
label = "User LD4";
status = "disabled";
};
};
gpio_keys {
compatible = "gpio-keys";
wake_up: button {
label = "Wakeup";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
status = "disabled";
zephyr,code = <INPUT_KEY_WAKEUP>;
};
joy_center: joystick_center {
label = "joystick center";
gpios = <&gpiok 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "disabled";
zephyr,code = <INPUT_KEY_ENTER>;
};
joy_down: joystick_down {
label = "joystick down";
gpios = <&gpiok 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "disabled";
zephyr,code = <INPUT_KEY_DOWN>;
};
joy_up: joystick_up {
label = "joystick up";
gpios = <&gpiok 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "disabled";
zephyr,code = <INPUT_KEY_UP>;
};
joy_left: joystick_left {
label = "joystick left";
gpios = <&gpiok 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "disabled";
zephyr,code = <INPUT_KEY_LEFT>;
};
joy_right: joystick_right {
label = "joystick right";
gpios = <&gpiok 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "disabled";
zephyr,code = <INPUT_KEY_RIGHT>;
};
};
dsi_lcd_qsh_030: connector_dsi_lcd {
compatible = "st,dsi-lcd-qsh-030";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <4 0 &gpiok 7 0>, /* TOUCH_INT */
<35 0 &gpioe 5 0>, /* SCLK/MCLK */
<37 0 &gpioe 4 0>, /* LRCLK */
<39 0 &gpioe 6 0>, /* I2S */
<40 0 &gpiod 13 0>, /* I2C4_SDA */
<44 0 &gpiod 12 0>, /* I2C4_SCL */
<45 0 &gpioa 8 0>, /* CEC_CLK */
<47 0 &gpiob 6 0>, /* CEC */
<49 0 &gpioj 2 0>, /* DSI_TE */
<53 0 &gpioj 12 0>, /* LCD_BL_CTRL */
<57 0 &gpiog 3 0>; /* DSI_RESET */
};
};
&rcc {
d1cpre = <1>;
hpre = <2>;
d1ppre = <2>;
d2ppre1 = <2>;
d2ppre2 = <2>;
d3ppre = <2>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
};
&uart8 {
pinctrl-0 = <&uart8_tx_pj8 &uart8_rx_pj9>;
pinctrl-names = "default";
current-speed = <115200>;
};
&spi5 {
pinctrl-0 = <&spi5_nss_pk1 &spi5_sck_pk0
&spi5_miso_pj11 &spi5_mosi_pj10>;
pinctrl-names = "default";
};
&mailbox {
status = "okay";
};
``` | /content/code_sandbox/boards/st/stm32h747i_disco/stm32h747i_disco.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,068 |
```unknown
/*
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/gpio/st-morpho-header.h>
/ {
st_morpho_header: st-morpho-header {
compatible = "st-morpho-header";
#gpio-cells = <2>;
gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
<ST_MORPHO_L_2 0 &gpioc 11 0>,
<ST_MORPHO_L_3 0 &gpioc 12 0>,
<ST_MORPHO_L_4 0 &gpiod 2 0>,
<ST_MORPHO_L_13 0 &gpioa 13 0>,
<ST_MORPHO_L_15 0 &gpioa 14 0>,
<ST_MORPHO_L_17 0 &gpioa 15 0>,
<ST_MORPHO_L_21 0 &gpiob 7 0>,
<ST_MORPHO_L_23 0 &gpioc 13 0>,
<ST_MORPHO_L_25 0 &gpioc 14 0>,
<ST_MORPHO_L_27 0 &gpioc 15 0>,
<ST_MORPHO_L_28 0 &gpioa 0 0>,
<ST_MORPHO_L_29 0 &gpioh 0 0>,
<ST_MORPHO_L_30 0 &gpioa 1 0>,
<ST_MORPHO_L_31 0 &gpioh 1 0>,
<ST_MORPHO_L_32 0 &gpioa 4 0>,
<ST_MORPHO_L_34 0 &gpiob 0 0>,
<ST_MORPHO_L_35 0 &gpioc 2 0>,
<ST_MORPHO_L_36 0 &gpioc 1 0>, /* SB56=ON, SB46=OFF */
<ST_MORPHO_L_37 0 &gpioc 3 0>,
<ST_MORPHO_L_38 0 &gpioc 0 0>, /* SB51=ON, SB52=OFF */
<ST_MORPHO_R_1 0 &gpioc 9 0>,
<ST_MORPHO_R_2 0 &gpioc 8 0>,
<ST_MORPHO_R_3 0 &gpiob 8 0>,
<ST_MORPHO_R_4 0 &gpioc 6 0>,
<ST_MORPHO_R_5 0 &gpiob 9 0>,
<ST_MORPHO_R_6 0 &gpioc 5 0>,
<ST_MORPHO_R_11 0 &gpioa 5 0>,
<ST_MORPHO_R_12 0 &gpioa 12 0>,
<ST_MORPHO_R_13 0 &gpioa 6 0>,
<ST_MORPHO_R_14 0 &gpioa 11 0>,
<ST_MORPHO_R_15 0 &gpioa 7 0>,
<ST_MORPHO_R_16 0 &gpiob 12 0>,
<ST_MORPHO_R_17 0 &gpiob 6 0>,
<ST_MORPHO_R_19 0 &gpioc 7 0>,
<ST_MORPHO_R_21 0 &gpioa 9 0>,
<ST_MORPHO_R_22 0 &gpiob 2 0>,
<ST_MORPHO_R_23 0 &gpioa 8 0>,
<ST_MORPHO_R_24 0 &gpiob 1 0>,
<ST_MORPHO_R_25 0 &gpiob 10 0>,
<ST_MORPHO_R_26 0 &gpiob 15 0>,
<ST_MORPHO_R_27 0 &gpiob 4 0>,
<ST_MORPHO_R_28 0 &gpiob 14 0>,
<ST_MORPHO_R_29 0 &gpiob 5 0>,
<ST_MORPHO_R_30 0 &gpiob 13 0>,
<ST_MORPHO_R_31 0 &gpiob 3 0>,
<ST_MORPHO_R_33 0 &gpioa 10 0>,
<ST_MORPHO_R_34 0 &gpioc 4 0>,
<ST_MORPHO_R_35 0 &gpioa 2 0>,
<ST_MORPHO_R_37 0 &gpioa 3 0>;
};
};
``` | /content/code_sandbox/boards/st/nucleo_f401re/st_morpho_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,162 |
```cmake
board_runner_args(jlink "--device=STM32F401RE" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_f401re/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f401Xe.dtsi>
#include <st/f4/stm32f401r(d-e)tx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include "st_morpho_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32F401RE-NUCLEO board";
compatible = "st,stm32f401re-nucleo";
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds: leds {
compatible = "gpio-leds";
green_led_2: led_2 {
gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
pwmleds {
compatible = "pwm-leds";
green_pwm_led: green_pwm_led {
pwms = <&pwm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led_2;
sw0 = &user_button;
pwm-led0 = &green_pwm_led;
watchdog0 = &wwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <336>;
div-p = <4>;
div-q = <7>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c3 {
pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_pc9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpiob 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
&spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/*
* The flash starting at offset 0x10000 and ending at
* offset 0x1ffff is reserved for use by the application.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 DT_SIZE_K(128)>;
};
slot1_partition: partition@40000 {
label = "image-1";
reg = <0x00040000 DT_SIZE_K(128)>;
};
scratch_partition: partition@60000 {
label = "image-scratch";
reg = <0x00060000 DT_SIZE_K(128)>;
};
};
};
&timers2 {
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch1_pa5>;
pinctrl-names = "default";
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in0_pa0>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <2>;
status = "okay";
};
&die_temp {
status = "okay";
};
&wwdg {
status = "okay";
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_f401re/nucleo_f401re.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,310 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_f401re/nucleo_f401re_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```yaml
board:
name: nucleo_f401re
vendor: st
socs:
- name: stm32f401xe
``` | /content/code_sandbox/boards/st/nucleo_f401re/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```yaml
identifier: nucleo_f401re
name: ST Nucleo F401RE
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- arduino_i2c
- arduino_spi
- pwm
- counter
- gpio
- i2c
- spi
- adc
- watchdog
- rtc
ram: 96
flash: 512
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_f401re/nucleo_f401re.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```unknown
# NUCLEO-64 F401RE board configuration
if BOARD_NUCLEO_F401RE
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_NUCLEO_F401RE
``` | /content/code_sandbox/boards/st/nucleo_f401re/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
config BOARD_NUCLEO_F401RE
select SOC_STM32F401XE
``` | /content/code_sandbox/boards/st/nucleo_f401re/Kconfig.nucleo_f401re | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 0 0>, /* A0 */
<1 0 &gpioa 1 0>, /* A1 */
<2 0 &gpioa 4 0>, /* A2 */
<3 0 &gpiob 0 0>, /* A3 */
<4 0 &gpioc 1 0>, /* A4 */
<5 0 &gpioc 0 0>, /* A5 */
<6 0 &gpioa 3 0>, /* D0 */
<7 0 &gpioa 2 0>, /* D1 */
<8 0 &gpioa 10 0>, /* D2 */
<9 0 &gpiob 3 0>, /* D3 */
<10 0 &gpiob 5 0>, /* D4 */
<11 0 &gpiob 4 0>, /* D5 */
<12 0 &gpiob 10 0>, /* D6 */
<13 0 &gpioa 8 0>, /* D7 */
<14 0 &gpioa 9 0>, /* D8 */
<15 0 &gpioc 7 0>, /* D9 */
<16 0 &gpiob 6 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
``` | /content/code_sandbox/boards/st/nucleo_f401re/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 492 |
```ini
source [find board/st_nucleo_f4.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/nucleo_f401re/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```restructuredtext
.. _stm32h747i_disco_board:
ST STM32H747I Discovery
#######################
Overview
********
The discovery kit enables a wide diversity of applications taking benefit
from audio, multi-sensor support, graphics, security, video,
and high-speed connectivity features.
The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU,
with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface,
large set of peripherals, SMPS, and MIPI-DSI.
Additionally, the board features:
- On-board ST-LINK/V3E supporting USB reenumeration capability
- USB ST-LINK functions: virtual COM port, mass storage, debug port
- Flexible power-supply options:
- ST-LINK USB VBUS, USB OTG HS connector, or external sources
- 4 capacitive touch LCD display module with MIPI DSI interface
- Ethernet compliant with IEEE802.3-2002
- USB OTG HS
- Stereo speaker outputs
- ST-MEMS digital microphones
- 2 x 512-Mbit QUAD-SPI NOR Flash memory
- 256-Mbit SDRAM
- 4 color user LEDs
- 1 user and reset push-button
- 4-direction joystick with selection button
- Arduino Uno V3 connectors
.. image:: img/stm32h747i_disco.jpg
:align: center
:alt: STM32H747I-DISCO
More information about the board can be found at the `STM32H747I-DISCO website`_.
More information about STM32H747XIH6 can be found here:
- `STM32H747XI on www.st.com`_
- `STM32H747xx reference manual`_
- `STM32H747xx datasheet`_
Supported Features
==================
The current Zephyr stm32h747i_disco board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| ETHERNET | on-chip | ethernet (*) |
+-----------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-----------+------------+-------------------------------------+
| FMC | on-chip | memc (SDRAM) |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| QSPI NOR | on-chip | off-chip flash |
+-----------+------------+-------------------------------------+
| SDMMC | on-chip | disk access |
+-----------+------------+-------------------------------------+
| IPM | on-chip | virtual mailbox based on HSEM |
+-----------+------------+-------------------------------------+
| DISPLAY | on-chip | MIPI DSI Host with shield (MP1166) |
| | | st_b_lcd40_dsi1_mb1166 |
+-----------+------------+-------------------------------------+
(*) From UM2411 Rev 4:
With the default setting, the Ethernet feature is not working because of
a conflict between ETH_MDC and SAI4_D1 of the MEMs digital microphone.
Make sure you have SB8 closed and SB21 open to get Ethernet working.
Other hardware features are not yet supported on Zephyr porting.
The default configuration per core can be found in the defconfig files:
:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig` and
:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig`
Pin Mapping
===========
STM32H747I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
For more details please refer to `STM32H747I-DISCO website`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com)
- UART_8 TX/RX : PJ8/PJ9 (Arduino Serial)
- SPI_5 NSS/SCK/MISO/MOSI : PK1/PK0/PJ11/PJ10 (Arduino SPI)
- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2
- LD1 : PI12
- LD2 : PI13
- LD3 : PI14
- LD4 : PI15
- W-UP : PC13
- J-CENTER : PK2
- J-DOWN : PK3
- J-LEFT : PK4
- J-RIGHT : PK5
- J-UP : PK6
System Clock
============
The STM32H747I System Clock can be driven by an internal or external oscillator,
as well as by the main PLL clock. By default, the CPU1 (Cortex-M7) System clock
is driven by the PLL clock at 400MHz, and the CPU2 (Cortex-M4) System clock
is driven at 200MHz. PLL clock is feed by a 25MHz high speed external clock.
Serial Port
===========
The STM32H747I Discovery kit has up to 8 UARTs.
Default configuration assigns USART1 and UART8 to the CPU1. The Zephyr console
output is assigned to UART1 which connected to the onboard ST-LINK/V3.0. Virtual
COM port interface. Default communication settings are 115200 8N1.
Ethernet
========
**Disclaimer:** This section is mostly copy-paste of corresponding
`DISCO_H747I modifications for Ethernet`_ mbed blog post. The author of this
article sincerely allowed to use the images and his knowledge about necessary
HW modifications to get Ethernet working with this board.
To get Ethernet working following HW modifications are required:
- **SB21**, **SB45** and **R87** should be opened
- **SB22**, **SB44**, **SB17** and **SB8** should be closed
Following two images shows necessary changes on the board marked:
.. image:: img/disco_h747i_ethernet_modification_1.jpg
:align: center
:alt: STM32H747I-DISCO - Ethernet modification 1 (**SB44**, **SB45**)
.. image:: img/disco_h747i_ethernet_modification_2.jpg
:align: center
:alt: STM32H747I-DISCO - Ethernet modification 2 (**SB21**, **R87**, **SB22**, **SB17** and **SB8**)
Display
=======
The STM32H747I Discovery kit has a dedicated DSI LCD connector **CN15**, where
the MB1166 (B-LCD40-DSI1) display extension board can be mounted. Enable display
support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` or
``st_b_lcd40_dsi1_mb1166_a09`` to your build command, for example:
.. zephyr-app-commands::
:zephyr-app: samples/drivers/display
:board: stm32h747i_disco/stm32h747xx/m7
:shield: st_b_lcd40_dsi1_mb1166
:goals: build flash
.. note::
The shield comes in different hardware revisions, the MB1166-A09
is utilizing a NT35510 panel controller and shall specifically
use ``st_b_lcd40_dsi1_mb1166_a09`` as SHIELD when building.
Prior versions are utilizing an OTM8009a controller and shall
use shield name without postfix, that is: ``st_b_lcd40_dsi1_mb1166``.
Shield version is printed on a sticker placed below the two bottom
mounting holes and has the format: MB1166-Axx.
Resources sharing
=================
The dual core nature of STM32H747 SoC requires sharing HW resources between the
two cores. This is done in 3 ways:
- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
has access to bus clock activation and deactivation.
- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in
devicetree before compilation. The user must ensure peripherals are not assigned
to both cores at the same time.
- **Run time protection**: Interrupt-controller and GPIO configurations could be
accessed by both cores at run time. Accesses are protected by a hardware semaphore
to avoid potential concurrent access issues.
Programming and Debugging
*************************
Applications for the ``stm32h747i_disco`` board should be built per core target,
using either ``stm32h747i_disco/stm32h747xx/m7`` or ```stm32h747i_disco/stm32h747xx/m4`` as the target.
See :ref:`build_an_application` for more information about application builds.
.. note::
If using OpenOCD you will need a recent development version as the last
official release does not support H7 dualcore yet.
Also, with OpenOCD, sometimes, flashing is not working. It is necessary to
erase the flash (with STM32CubeProgrammer for example) to make it work again.
Debugging with OpenOCD is currently working for this board only with Cortex M7,
not Cortex M4.
Flashing
========
Flashing operation will depend on the target to be flashed and the SoC
option bytes configuration.
It is advised to use `STM32CubeProgrammer`_ to check and update option bytes
configuration and flash ``stm32h747i_disco/stm32h747xx/m7`` and
``stm32h747i_disco/stm32h747xx/m7`` targets.
By default:
- CPU1 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0)
- CPU2 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0)
Also, default out of the box board configuration enables CM7 and CM4 boot when
board is powered (Option bytes BCM7 and BCM4 are checked).
It is possible to change Option Bytes so that CM7 boots first in stand alone,
and CM7 will wakeup CM4 after clock initialization.
Drivers are able to take into account both Option Bytes configurations
automatically.
Zephyr flash configuration has been set to meet these default settings.
Alternatively, west `STM32CubeProgrammer`_ runner can be used, after installing
it, to flash applications for both cores. The target core is detected automatically.
.. code-block:: console
$ west flash --runner stm32cubeprogrammer
Flashing an application to STM32H747I M7 Core
---------------------------------------------
First, connect the STM32H747I Discovery kit to your host computer using
the USB port to prepare it for flashing. Then build and flash your application.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h747i_disco/stm32h747xx/m7
:goals: build flash
Run a serial host program to connect with your board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
You should see the following message on the console:
.. code-block:: console
Hello World! stm32h747i_disco
.. note::
Sometimes, flashing is not working. It is necessary to erase the flash
(with STM32CubeProgrammer for example) to make it work again.
Similarly, you can build and flash samples on the M4 target. For this, please
take care of the resource sharing (UART port used for console for instance).
Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32h747i_disco/stm32h747xx/m7
:goals: build flash
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h747i_disco/stm32h747xx/m7
:goals: debug
Debugging with west is currently not available on Cortex M4 side.
In order to debug a Zephyr application on Cortex M4 side, you can use
`STM32CubeIDE`_.
.. _STM32H747I-DISCO website:
path_to_url
.. _STM32H747XI on www.st.com:
path_to_url
.. _STM32H747xx reference manual:
path_to_url
.. _STM32H747xx datasheet:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
.. _DISCO_H747I modifications for Ethernet:
path_to_url
.. _STM32CubeIDE:
path_to_url
``` | /content/code_sandbox/boards/st/stm32h747i_disco/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,020 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# enable clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32f103_mini/stm32f103_mini_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```cmake
board_runner_args(jlink "--device=STM32F103RC" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32f103_mini/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config BOARD_STM32F103_MINI
select SOC_STM32F103XE
``` | /content/code_sandbox/boards/st/stm32f103_mini/Kconfig.stm32f103_mini | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f1/stm32f103Xc.dtsi>
#include <st/f1/stm32f103r(c-d-e)tx-pinctrl.dtsi>
/ {
model = "stm32f103_mini board";
compatible = "stm32f103";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
};
aliases {
led0 = &green_led_1;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};
&pll {
mul = <9>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(72)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
/* usbpre not set: USB clock = 72 / 1.5: 48MHz */
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
};
&usart3 {
pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
pinctrl-names = "default";
current-speed = <115200>;
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_remap1_pb8 &i2c1_sda_remap1_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_nss_master_pa4 &spi1_sck_master_pa5
&spi1_miso_master_pa6 &spi1_mosi_master_pa7>;
pinctrl-names = "default";
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_nss_master_pb12 &spi2_sck_master_pb13
&spi2_miso_master_pb14 &spi2_mosi_master_pb15>;
pinctrl-names = "default";
status = "okay";
};
&iwdg {
status = "okay";
};
&timers1 {
st,prescaler = <10000>;
status = "okay";
pwm1: pwm {
status = "okay";
pinctrl-0 = <&tim1_ch1_pwm_out_pa8>;
pinctrl-names = "default";
};
};
zephyr_udc0: &usb {
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in0_pa0>;
pinctrl-names = "default";
status = "okay";
};
&die_temp {
status = "okay";
};
``` | /content/code_sandbox/boards/st/stm32f103_mini/stm32f103_mini.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 859 |
```restructuredtext
.. _nucleo_f401re_board:
ST Nucleo F401RE
################
Overview
********
The Nucleo F401RE board features an ARM Cortex-M4 based STM32F401RE MCU
with a wide range of connectivity support and configurations Here are
some highlights of the Nucleo F401RE board:
- STM32 microcontroller in QFP64 package
- Two types of extension resources:
- Arduino Uno V3 connectivity
- ST morpho extension pin headers for full access to all STM32 I/Os
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Flexible board power supply:
- USB VBUS or external source(3.3V, 5V, 7 - 12V)
- Power management access point
- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3)
- Two push-buttons: USER and RESET
.. image:: img/nucleo_f401re.jpg
:align: center
:alt: Nucleo F401RE
More information about the board can be found at the `Nucleo F401RE website`_.
Hardware
********
Nucleo F401RE provides the following hardware components:
- STM32F401RET6 in LQFP64 package
- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
- 84 MHz max CPU frequency
- VDD from 1.7 V to 3.6 V
- 512 KB Flash
- 96 KB SRAM
- GPIO with external interrupt capability
- 12-bit ADC with 16 channels
- RTC
- Advanced-control Timer
- General Purpose Timers (7)
- Watchdog Timers (2)
- USART/UART (3)
- I2C (3)
- SPI (4)
- SDIO
- USB 2.0 OTG FS
- DMA Controller
More information about STM32F401RE can be found here:
- `STM32F401RE on www.st.com`_
- `STM32F401 reference manual`_
Supported Features
==================
The Zephyr nucleo_401re board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | System Window Watchdog |
+-----------+------------+-------------------------------------+
| die-temp | on-chip | die temperature sensor |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on Zephyr porting.
The default configuration can be found in
:zephyr_file:`boards/st/nucleo_f401re/nucleo_f401re_defconfig`
Pin Mapping
===========
Nucleo F401RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
Available pins:
---------------
.. image:: img/nucleo_f401re_arduino.jpg
:align: center
:alt: Nucleo F401RE Arduino connectors
.. image:: img/nucleo_f401re_morpho.jpg
:align: center
:alt: Nucleo F401RE Morpho connectors
For more details please refer to `STM32 Nucleo-64 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX : PB6/PB7
- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com)
- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C)
- SPI1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI)
- PWM_2_CH1 : PA0
- USER_PB : PC13
- LD2 : PA5
System Clock
============
Nucleo F401RE System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz,
driven by 8MHz high speed external clock.
Serial Port
===========
Nucleo F401RE board has 3 UARTs. The Zephyr console output is assigned to UART2.
Default settings are 115200 8N1.
I2C
===
Nucleo F401RE board has up to 3 I2Cs. The default I2C mapping for Zephyr is:
- I2C1_SCL : PB8
- I2C1_SDA : PB9
Programming and Debugging
*************************
Applications for the ``nucleo_f401re`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Nucleo F401RE board includes an ST-LINK/V2-1 embedded debug tool interface.
This interface is supported by the openocd version included in Zephyr SDK.
Flashing an application to Nucleo F401RE
----------------------------------------
Connect the Nucleo F401RE to your host computer using the USB port,
then run a serial host program to connect with your Nucleo board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Now build and flash an application. Here is an example for
:ref:`hello_world`.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_f401re
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! arm
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_f401re
:maybe-skip-config:
:goals: debug
.. _Nucleo F401RE website:
path_to_url
.. _STM32 Nucleo-64 board User Manual:
path_to_url
.. _STM32F401RE on www.st.com:
path_to_url
.. _STM32F401 reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_f401re/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,554 |
```yaml
board:
name: stm32f103_mini
vendor: st
socs:
- name: stm32f103xe
``` | /content/code_sandbox/boards/st/stm32f103_mini/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32f1x.cfg]
reset_config srst_only
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/stm32f103_mini/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```yaml
identifier: stm32f103_mini
name: STM32F103RCT6 Mini Board
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 48
flash: 256
supported:
- gpio
- i2c
- spi
- pwm
- watchdog
- adc
- counter
- usbd
vendor: st
``` | /content/code_sandbox/boards/st/stm32f103_mini/stm32f103_mini.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```cmake
# By default stm32cubeprogrammer configured to use DFU upload method.
# Comment below line and uncomment the second line to use SWD upoad method.
board_runner_args(stm32cubeprogrammer "--port=usb1")
# board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
# Even if flash and start work, dfu-util return error 74. It can be ignored.
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
board_runner_args(openocd "--tcl-port=6666")
board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable")
board_runner_args(openocd "--no-halt")
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/st/steval_stwinbx1/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 223 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable GPIO
CONFIG_GPIO=y
CONFIG_GPIO_HOGS=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# Enable console
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/steval_stwinbx1/steval_stwinbx1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
config BOARD_STEVAL_STWINBX1
select SOC_STM32U585XX
``` | /content/code_sandbox/boards/st/steval_stwinbx1/Kconfig.steval_stwinbx1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```restructuredtext
.. _stm32f103_mini_board:
STM32F103 Mini
################
Overview
********
The STM32F103_MINI board features an ARM Cortex-M3 based STM32F103RC MCU
with a wide range of connectivity support and configurations. There are
multiple version of this board like ``stm32f103_mini``.
.. image:: img/stm32f103_mini_yellow.jpg
:align: center
:alt: STM32F103 Mini Yellow
.. image:: img/stm32f103_mini_blue.jpg
:align: center
:alt: STM32F103 Mini Blue
Hardware
********
STM32F103 Mini provides the following hardware components:
- STM32 microcontroller in QFP64 package
- Flexible board power supply:
- USB VBUS or external source (3.3V, 5V, 7 - 12V)
- Power management access point
- Two LEDs:
- User LED (LD1), power LED (LD2)
- USB re-enumeration capability:
- Mass storage
More information about STM32F103RC can be found here:
- `STM32F103 reference manual`_
- `STM32F103 data sheet`_
Supported Features
==================
The Zephyr stm32f103_mini board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| COUNTER | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported in this Zephyr port.
The default configuration can be found in
:zephyr_file:`boards/st/stm32f103_mini/stm32f103_mini_defconfig`
Connections and IOs
===================
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
Board connectors:
-----------------
.. image:: img/stm32f103_mini_pin.jpg
:align: center
:alt: Nucleo F103RB connectors
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX: PA9/PA10
- UART_2 TX/RX: PA2/PA3 (ST-Link Virtual COM Port)
- SPI1 NSS/SCK/MISO/MOSI: PA4/PA5/PA6/PA7
- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15
- I2C1 SDA/SCL: PB9/PB8
- PWM1_CH1: PA8
- USER_PB: PC13
- LD1: PA5
- USB_DC DM/DP: PA11/PA12
System Clock
------------
The on-board 8MHz crystal is used to produce a 72MHz system clock with PLL.
Programming and Debugging
*************************
Applications for the ``stm32f103_mini`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
There are 2 main entry points for flashing STM32F1X SoCs, one using the ROM
bootloader, and another by using the SWD debug port (which requires additional
hardware such as ST-Link). Flashing using the ROM bootloader requires a special activation
pattern, which can be triggered by using the BOOT0 pin.
Flashing an application to stm32f103 mini
-----------------------------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32f103_mini
:goals: build flash
You will see the LED blinking every second.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32f103_mini
:maybe-skip-config:
:goals: debug
References
**********
.. target-notes::
.. _STM32F103 reference manual:
path_to_url
.. _STM32F103 data sheet:
path_to_url
``` | /content/code_sandbox/boards/st/stm32f103_mini/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,224 |
```yaml
board:
name: steval_stwinbx1
vendor: st
socs:
- name: stm32u585xx
``` | /content/code_sandbox/boards/st/steval_stwinbx1/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: steval_stwinbx1
name: STEVAL STWINBX1 Development kit
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 786
flash: 2048
supported:
- counter
- gpio
- pwm
- watchdog
- ble
vendor: st
``` | /content/code_sandbox/boards/st/steval_stwinbx1/steval_stwinbx1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
# STEVAL_STWINBX1 Development kit board configuration
if BOARD_STEVAL_STWINBX1
if BT
config SPI
default y
config BT_SPI
default y
config BT_BLUENRG_ACI
default y
# Disable Flow control
config BT_HCI_ACL_FLOW_CONTROL
default n
endif # BT
config SPI_STM32_INTERRUPT
default y
depends on SPI
if BOARD_SERIAL_BACKEND_CDC_ACM
config USB_DEVICE_STACK
default y
config USB_CDC_ACM
default SERIAL
config USB_DEVICE_INITIALIZE_AT_BOOT
default y if CONSOLE
config SHELL_BACKEND_SERIAL_CHECK_DTR
default SHELL
depends on UART_LINE_CTRL
config UART_LINE_CTRL
default SHELL
config USB_DEVICE_REMOTE_WAKEUP
default n
config USB_DEVICE_VID
default 0x0483
config USB_DEVICE_PID
default 0x5740
config USB_DEVICE_PRODUCT
default "Zephyr CDC STEval-STWinbx1"
if LOG
# Logger cannot use itself to log
choice USB_CDC_ACM_LOG_LEVEL_CHOICE
default USB_CDC_ACM_LOG_LEVEL_OFF
endchoice
endif # LOG
endif # BOARD_SERIAL_BACKEND_CDC_ACM
DT_CHOSEN_ZEPHYR_CONSOLE := zephyr,console
config UART_CONSOLE
default y if $(dt_chosen_enabled,$(DT_CHOSEN_ZEPHYR_CONSOLE)) && CONSOLE
endif # BOARD_STEVAL_STWINBX1
``` | /content/code_sandbox/boards/st/steval_stwinbx1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 311 |
```unknown
# STEVAL_STWINBX1 Development kit board configuration
if BOARD_STEVAL_STWINBX1
config BOARD_SERIAL_BACKEND_CDC_ACM
bool "Use USB CDC as serial console backend"
default y
endif # BOARD_STEVAL_STWINBX1
``` | /content/code_sandbox/boards/st/steval_stwinbx1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```ini
source [find interface/stlink-dap.cfg]
set WORKAREASIZE 0x8000
transport select "dapdirect_swd"
set CHIPNAME STM32U585AIIxQ
set BOARDNAME STEVAL-STWINBX1
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# STlink Debug clock frequency
set CLOCK_FREQ 8000
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0
# ACCESS PORT NUMBER
set AP_NUM 0
# GDB PORT
set GDB_PORT 3333
# BCTM CPU variables
source [find target/stm32u5x.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/steval_stwinbx1/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 251 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/u5/stm32u585Xi.dtsi>
#include <st/u5/stm32u585aiixq-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STEVAL-STWINBX1 Development kit";
compatible = "st,steval_stwinbx1";
chosen {
zephyr,console = &cdc_acm_uart0;
zephyr,shell-uart = &cdc_acm_uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,bt-hci = &hci_spi;
};
leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpioh 12 GPIO_ACTIVE_HIGH>;
label = "LED_1";
};
orange_led: led_2 {
gpios = <&gpioh 10 GPIO_ACTIVE_HIGH>;
label = "LED_2";
};
};
pwmleds {
compatible = "pwm-leds";
green_pwm_led: green_pwm_led {
pwms = <&pwm5 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "LED_1 - PWM5";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led;
led1 = &orange_led;
pwm-led0 = &green_pwm_led;
sw0 = &user_button;
mcuboot-led0 = &green_led;
mcuboot-button0 = &user_button;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref1;
volt-sensor1 = &vbat4;
};
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_msis {
status = "okay";
msi-range = <4>;
msi-pll-mode;
};
&pll1 {
div-m = <1>;
mul-n = <10>;
div-q = <2>;
div-r = <1>;
clocks = <&clk_hse>;
status = "okay";
};
&pll2 {
div-m = <2>;
mul-n = <48>;
div-p = <2>;
div-q = <7>;
div-r = <25>;
clocks = <&clk_hse>;
status = "okay";
};
&pll3 {
div-m = <2>;
mul-n = <48>;
div-p = <2>;
div-q = <25>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};
&gpioe {
status = "okay";
/* Enable 2.7V Analog LDO */
ldo-enable-gpios {
gpio-hog;
gpios = <15 GPIO_ACTIVE_HIGH>;
output-high;
};
};
stm32_lp_tick_source: &lptim1 {
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>,
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_sck_pi1 &spi2_miso_pd3 &spi2_mosi_pi3>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpioh 6 GPIO_ACTIVE_LOW>,
<&gpioh 15 GPIO_ACTIVE_LOW>,
<&gpioi 7 GPIO_ACTIVE_LOW>;
iis2dlpc: iis2dlpc@0 {
compatible = "st,iis2dlpc";
spi-max-frequency = <DT_FREQ_M(10)>;
reg = <0>;
drdy-gpios = <&gpiof 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
drdy-int = <1>;
};
ism330dhcx: ism330dhcx@1 {
compatible = "st,ism330dhcx";
spi-max-frequency = <DT_FREQ_M(10)>;
reg = <1>;
drdy-gpios = <&gpiob 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
int-pin = <1>;
};
iis2iclx: iis2iclx@2 {
compatible = "st,iis2iclx";
spi-max-frequency = <DT_FREQ_M(10)>;
reg = <2>;
drdy-gpios = <&gpiof 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
int-pin = <2>;
};
};
&spi3 {
pinctrl-0 = <&spi3_sck_pg9 &spi3_miso_pb4 &spi3_mosi_pb5>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpioe 1 GPIO_ACTIVE_LOW>;
hci_spi: bluenrg-2@0 {
compatible = "st,hci-spi-v2";
reg = <0>;
reset-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpiof 14 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
spi-cpha; /* CPHA=1 */
spi-hold-cs;
spi-max-frequency = <DT_FREQ_M(1)>;
reset-assert-duration-ms = <6>;
};
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_ph4 &i2c2_sda_pf0>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
stts22h@3f {
compatible = "st,stts22h";
reg = <0x3f>;
int-gpios = <&gpiof 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
iis2mdc@1e {
compatible = "st,iis2mdc";
reg = <0x1e>;
drdy-gpios = <&gpiof 9 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&timers5 {
st,prescaler = <10000>;
status = "okay";
pwm5: pwm {
status = "okay";
pinctrl-0 = <&tim5_ch3_ph12>;
pinctrl-names = "default";
};
};
&aes {
status = "okay";
};
&rng {
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};
&adc1 {
pinctrl-0 = <&adc1_in1_pc0>;
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <4>;
vref-mv = <2750>;
status = "okay";
};
&adc4 {
pinctrl-0 = <&adc4_in3_pc2>;
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <4>;
vref-mv = <2750>;
status = "okay";
};
&die_temp {
status = "okay";
};
&iwdg {
status = "okay";
};
&vref1 {
status = "okay";
};
&vbat4 {
status = "okay";
};
&sdmmc1 {
status = "okay";
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
pinctrl-names = "default";
cd-gpios = <&gpiog 1 GPIO_ACTIVE_LOW>;
bus-width = <4>;
clk-div = <4>;
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* Following flash partition is dedicated to the use of steval_stwinbx1
* with TZEN=0 (so w/o TFM).
* Set the partitions with first MB to make use of the whole Bank1
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(416)>;
};
slot1_partition: partition@78000 {
label = "image-1";
reg = <0x00078000 DT_SIZE_K(416)>;
};
scratch_partition: partition@e0000 {
label = "image-scratch";
reg = <0x000e0000 DT_SIZE_K(64)>;
};
storage_partition: partition@f0000 {
label = "storage";
reg = <0x000f0000 DT_SIZE_K(64)>;
};
};
};
&gpdma1 {
status = "okay";
};
``` | /content/code_sandbox/boards/st/steval_stwinbx1/steval_stwinbx1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,300 |
```cmake
board_runner_args(jlink "--device=STM32F767ZI" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_f767zi/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
config BOARD_NUCLEO_F767ZI
select SOC_STM32F767XX
``` | /content/code_sandbox/boards/st/nucleo_f767zi/Kconfig.nucleo_f767zi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
identifier: nucleo_f767zi
name: ST Nucleo F767ZI
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 512
flash: 2048
supported:
- adc
- arduino_i2c
- arduino_gpio
- arduino_spi
- uart
- gpio
- netif:eth
- usb_device
- i2c
- pwm
- spi
- nvs
- watchdog
- counter
- can
- dac
- rtc
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_f767zi/nucleo_f767zi.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART
CONFIG_SERIAL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_f767zi/nucleo_f767zi_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
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