text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```cmake
set(SUPPORTED_EMU_PLATFORMS renode)
set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/m2gl025_miv.resc)
set(RENODE_UART sysbus.uart)
set_ifndef(BOARD_SIM_RUNNER renode)
set_ifndef(BOARD_ROBOT_RUNNER renode-robot)
include(${ZEPHYR_BASE}/boards/common/renode.board.cmake)
include(${ZEPHYR_BASE}/boards/common/renode_robot.board.cmake)
``` | /content/code_sandbox/boards/microchip/m2gl025_miv/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=n
CONFIG_XIP=y
# Workaround for incorrect SYS_CLOCK_HW_CYCLES_PER_SEC
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
``` | /content/code_sandbox/boards/microchip/m2gl025_miv/m2gl025_miv_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
config BOARD_M2GL025_MIV
select SOC_MIV
``` | /content/code_sandbox/boards/microchip/m2gl025_miv/Kconfig.m2gl025_miv | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```unknown
/*
*
*/
/dts-v1/;
#include <microchip/microchip-miv.dtsi>
/ {
model = "Microchip M2GL025 with MiV target";
compatible = "microchip,m2gl025-miv";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash = &flash0;
zephyr,sram = &sram0;
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
clock-frequency = <66000000>;
};
``` | /content/code_sandbox/boards/microchip/m2gl025_miv/m2gl025_miv.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```yaml
board:
name: m2gl025_miv
vendor: microchip
socs:
- name: miv
``` | /content/code_sandbox/boards/microchip/m2gl025_miv/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```yaml
identifier: m2gl025_miv
name: Microchip M2GL025 with MiV target
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 64
simulation: renode
simulation_exec: renode
testing:
default: true
ignore_tags:
- net
- bluetooth
renode:
uart: sysbus.uart
resc: boards/microchip/m2gl025_miv/support/m2gl025_miv.resc
vendor: microchip
``` | /content/code_sandbox/boards/microchip/m2gl025_miv/m2gl025_miv.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 118 |
```unknown
:name: Mi-V
:description: This script is prepared to run Zephyr on a Mi-V RISC-V board.
$name?="Mi-V"
using sysbus
mach create $name
machine LoadPlatformDescription $ORIGIN/m2gl025_miv.repl
showAnalyzer uart
cpu PerformanceInMips 4
macro reset
"""
sysbus LoadELF $elf
"""
runMacro $reset
``` | /content/code_sandbox/boards/microchip/m2gl025_miv/support/m2gl025_miv.resc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```unknown
using "platforms/cpus/miv.repl"
uart:
clockFrequency: 4000000
clint:
frequency: 4000000
timer0:
clockFrequency: 4000000
timer1:
clockFrequency: 4000000
``` | /content/code_sandbox/boards/microchip/m2gl025_miv/support/m2gl025_miv.repl | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```restructuredtext
.. _mec172xmodular_6930:
Microchip MEC172x Modular Card ASSY6930 (Rev. B)
################################################
Overview
********
The MEC172x Modular Card ASSY6930 (Rev. B) is a development board to evaluate the
Microchip MEC172X series microcontrollers. This board can work standalone
or be mated with any platform that complies with MECC specification.
.. image:: ./mec172xmodular_assy6930.jpg
:width: 576px
:align: center
:alt: MEC172x Modular ASSY 6930
Hardware
********
- MEC172x (MEC1723, MEC1727 and MEC1728) ARM Cortex-M4 Processor
- 416 KB RAM and 128 KB boot ROM
- UART1 using microUSB
- PECI interface 3.0
- FAN, PWM and TACHO pins
- 5 SMBus instances
- eSPI header
- VCI interface
- 1 hardware driven PS/2 ports
- Keyboard interface headers
For more information about the SOC please see `MEC172x Reference Manual`_
At difference from MEC172x evaluation board, modular MEC172x exposes the pins in 2 different ways:
1) Standalone mode via headers
- GPIOs
- JTAG port
- eSPI bus
- I2C0, I2C1 and I2C6
- PWM1, PWM2, PWM3
- Shared SPI
- Keyboard Interface
2) Mated mode with another platform that has a high density MECC connector
- FAN, PWM8
- I2C3 and I2C7
- eSPI bus
The board is powered through the +5V USB micro-A connector or from the MECC connector.
Supported Features
==================
The mec172xmodular_assy6930 (Rev. B) board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| PS/2 | on-chip | ps2 |
+-----------+------------+-------------------------------------+
| KSCAN | on-chip | kscan |
+-----------+------------+-------------------------------------+
| TACH | on-chip | tachometer |
+-----------+------------+-------------------------------------+
| RPMFAN | on-chip | Fan speed controller |
+-----------+------------+-------------------------------------+
Other hardware features are not currently supported by Zephyr (at the moment)
The default configuration can be found in the
:zephyr_file:`boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig` Kconfig file.
Connections and IOs
===================
This evaluation board kit is comprised of the following HW blocks:
- MEC172x Modular ASSY 6930 Rev B1 `MEC172x Modular EC Card - Assy_6930 Rev B1p1`_
System Clock
============
The MEC172x MCU is configured to use the 96Mhz internal oscillator with the
on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock
control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in
the references at the end of this document.
Serial Port
===========
UART1 is configured for serial logs.
Jumper settings
***************
Please follow the jumper settings below to properly demo this
board. Advanced users may deviate from this recommendation.
Jumper setting for MEC172x Modular Assy 6930 Rev B1p1
=====================================================
Power-Related Jumpers
---------------------
If you wish to power from type A/B connector ``P1`` set the jumper ``JP22 1-2``.
This is required for standalone mode.
If you wish to power through MECC connector ``P2`` and mate to external platform,
set the jumper to ``JP22 2-3``.
NOTE: A single jumper is required in JP22.
If you wish to set VTR2 to 3.3V, set the jumper ``JP26 2-3``.
This is required for Windows application.
If you wish to set VTR2 to 1.8V, set the jumper ``JP26 1-2``.
This is required for Chrome application.
Boot-ROM Straps
---------------
This jumper configures MEC172x Boot-ROM strap.
+---------------------+
| JP23 (UART_BSTRAP) |
+=====================+
| 1-2 |
+---------------------+
``JP23 1-2`` pulls UART_BSTRAP to GND. MEC172x Boot-ROM samples UART_BSTRAP and if low,
UART interface is used for Crisis Recovery.
Boot Source Select
------------------
The jumpers below configure MEC172x to boot from Shared SPI, Slave Attached Flash (SAF)
or Master Attached Flash (MAF).
+-------------------+----------+
| Boot Source | JP25 |
+===================+==========+
| Shared SPI or SAF | 5-6 |
+-------------------+----------+
| MAF | 1-2, 4-6 |
+-------------------+----------+
Programming and Debugging
*************************
Setup
=====
#. If you use Dediprog SF100 programmer, then setup it.
Windows version can be found at the `SF100 Product page`_.
Linux version source code can be found at `SF100 Linux GitHub`_.
Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer.
For Linux please make sure that you copied ``60-dediprog.rules``
from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d)
then restart service using:
.. code-block:: console
$ udevadm control --reload
Add directory with program ``dpcmd`` (on Linux)
or ``dpcmd.exe`` (on Windows) to your ``PATH``.
#. Clone the `MEC172x SPI Image Gen`_ repository or download the files within
that directory.
#. Make the image generation available for Zephyr, by making the tool
searchable by path, for example:
.. code-block:: console
-DMEC172X_SPI_GEN=<path to spi_gen tool>/mec172x_spi_gen_lin_x86_64
Note that the tools for Linux and Windows have different file names.
#. The default MEC172X_SPI_CFG file is spi_cfg.txt located in ${BOARD_DIR}/support.
Example of SPI_CFG for 4MBit (spi_cfg_4MBit.txt) and 128MBit (spi_cfg_128MBit.txt)
SPI flash can be found in the same folder. If needed, a custom SPI image
configuration file can be specified to override the default one.
.. code-block:: console
-DMEC172X_SPI_CFG=<path to spi_cfg file>/spi_cfg.txt
#. Example command to generate 128MBit spi image for hello_world:
.. code-block:: console
west build -p auto -b mec172xmodular_assy6930 samples/hello_world -- -DMEC172X_SPI_GEN=$HOME/CPGZephyrDocs/MEC172x/SPI_image_gen/mec172x_spi_gen_lin_x86_64 -DMEC172X_SPI_CFG=$HOME/zephyrproject/zephyr/boards/microchip/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt
Wiring
========
#. Connect programmer to the header J2 on the ASSY6930 board, it will flash the SPI NOR chip
``U2``. Make sure that your programmer's offset is 0x0.
For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips.
+------------+---------------+
| Dediprog | |
| Connector | J2 |
+============+===============+
| VCC | 1 |
+------------+---------------+
| GND | 2 |
+------------+---------------+
| CS | 3 |
+------------+---------------+
| CLK | 4 |
+------------+---------------+
| MISO | 6 |
+------------+---------------+
| MOSI | 5 |
+------------+---------------+
#. Connect UART1 port of the mec172xmodular_assy6930 (Rev. B) board
to your host computer using the RS232 cable.
#. Apply power to the board via a micro-USB cable.
Configure this option by using a jumper between ``JP22 1-2``.
Building
========
#. Build :ref:`hello_world` application as you would normally do.
#. The file :file:`spi_image.bin` will be created if the build system
can find the image generation tool. This binary image can be used
to flash the SPI chip.
Flashing
========
#. Run your favorite terminal program to listen for output.
Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it.
For example:
.. code-block:: console
$ minicom -D /dev/ttyUSB0 -o
The -o option tells minicom not to send the modem initialization
string. Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
#. Flash your board using ``west`` from the second terminal window.
Split first and second terminal windows to view both of them.
.. code-block:: console
$ west flash
.. note:: When west process started press Reset button ``S1`` and do not release it
till the whole west process will not be finished successfully.
#. You should see ``"Hello World! mec172xmodular_assy6930"`` in the first terminal window.
If you don't see this message, press the Reset button and the message should appear.
Debugging
=========
``J1`` header on the board allows for JTAG connections for debug.
Troubleshooting
===============
#. In case you don't see your application running, please make sure ``LED1`` is lit.
If ``LED1`` is off, check the power-related jumpers again.
#. If you can't program the board using Dediprog, disconnect and reconnect cable connected to
``P1`` and try again.
#. If Dediprog can't detect the onboard flash, press the board's ``S1`` Reset button and try again.
References
**********
.. target-notes::
.. _MEC172x Reference Manual:
path_to_url
.. _MEC172x Modular EC Card - Assy_6930 Rev B1p1:
path_to_url
.. _MEC172x SPI Image Gen:
path_to_url
.. _SF100 Linux GitHub:
path_to_url
.. _SF100 Product page:
path_to_url
.. _SF100 Linux manual:
path_to_url
``` | /content/code_sandbox/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,574 |
```cmake
set(SPI_IMAGE_NAME spi_image.bin)
board_set_flasher_ifnset(dediprog)
# --vcc=0 - use 3.5V to flash
board_finalize_runner_args(dediprog
"--spi-image=${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}"
"--vcc=0"
)
``` | /content/code_sandbox/boards/microchip/mec1501modular_assy6885/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
config BOARD_MEC1501MODULAR_ASSY6885
select SOC_MEC1501_HSZ
``` | /content/code_sandbox/boards/microchip/mec1501modular_assy6885/Kconfig.mec1501modular_assy6885 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```restructuredtext
.. _m2gl025-miv:
Microchip M2GL025 Mi-V
######################
Overview
********
The Microchip M2GL025 board is an IGLOO2 FPGA based development board.
The Mi-V RISC-V soft CPU can be deployed on the MGL025 board.
More information can be found on
`Microchip's website <path_to_url`_.
Programming and debugging
*************************
Building
========
Applications for the ``m2gl025_miv`` board configuration can be built as usual
(see :ref:`build_an_application`):
.. zephyr-app-commands::
:board: m2gl025_miv
:goals: build
Flashing
========
In order to upload the application to the device, you'll need OpenOCD and GDB
with RISC-V support.
You can get them as a part of SoftConsole SDK.
Download and installation instructions can be found on
`Microchip's SoftConsole website
<path_to_url`_.
With the necessary tools installed, you can connect to the board using OpenOCD.
To establish an OpenOCD connection run:
.. code-block:: bash
sudo LD_LIBRARY_PATH=<softconsole_path>/openocd/bin \
<softconsole_path>/openocd/bin/openocd --file \
<softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
Leave it running, and in a different terminal, use GDB to upload the binary to
the board. You can use the RISC-V GDB from a toolchain delivered with
SoftConsole SDK.
Here is the GDB terminal command to connect to the device
and load the binary:
.. code-block:: console
<softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
-ex "target extended-remote localhost:3333" \
-ex "set mem inaccessible-by-default off" \
-ex "set arch riscv:rv32" \
-ex "set riscv use_compressed_breakpoints no" \
-ex "load" <path_to_executable>
Debugging
=========
Refer to the detailed overview of :ref:`application_debugging`.
``` | /content/code_sandbox/boards/microchip/m2gl025_miv/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 478 |
```yaml
#
#
#
identifier: mec1501modular_assy6885
name: MEC1501 MODULAR ASSY 6885
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 32
flash: 224
supported:
- adc
- counter
- espi
- gpio
- i2c
- pwm
- watchdog
- kscan
- tach
vendor: microchip
``` | /content/code_sandbox/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```unknown
#
#
#
# Make sure external power management setup is as indicated in documentation
CONFIG_SOC_MEC1501_VTR3_1_8V=y
CONFIG_SOC_MEC1501_VCI_PINS_AS_GPIOS=n
CONFIG_RTOS_TIMER=y
CONFIG_CLOCK_CONTROL=y
CONFIG_PINCTRL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_PM=y
``` | /content/code_sandbox/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```unknown
/*
*
*/
/dts-v1/;
#include "mec1501modular_assy6885-pinctrl.dtsi"
/ {
model = "Microchip MEC1501MODULAR_ASSY6885 evaluation board";
compatible = "microchip,mec1501modular_assy6885",
"microchip,mec1501hsz";
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart1;
zephyr,flash = &flash0;
zephyr,keyboard-scan = &kscan_input;
};
aliases {
pwm-0 = &pwm0;
peci-0 = &peci0;
i2c0 = &i2c_smb_0;
i2c1 = &i2c_smb_1;
kscan0 = &kscan_input;
watchdog0 = &wdog;
};
};
&pcr {
status = "okay";
};
&uart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
pinctrl-names = "default";
};
&adc0 {
status = "okay";
pinctrl-0 = <&adc04_gpio204 &adc05_gpio205
&adc06_gpio206 &adc07_gpio207
&vref2_adc_gpio067 >;
pinctrl-names = "default";
};
&i2c_smb_0 {
status = "okay";
port_sel = <0>;
sda-gpios = <MCHP_GPIO_DECODE_003 0>;
scl-gpios = <MCHP_GPIO_DECODE_004 0>;
pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
pinctrl-names = "default";
};
&i2c_smb_1 {
status = "okay";
port_sel = <1>;
sda-gpios = <MCHP_GPIO_DECODE_130 0>;
scl-gpios = <MCHP_GPIO_DECODE_131 0>;
pinctrl-0 = < &i2c01_scl_gpio131 &i2c01_sda_gpio130 >;
pinctrl-names = "default";
};
&espi0 {
status = "okay";
io_girq = <19>;
vw_girqs = <24 25>;
pc_girq = <15>;
pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066
&espi_alert_n_gpio063 &espi_clk_gpio065
&espi_io0_gpio070 &espi_io1_gpio071
&espi_io2_gpio072 &espi_io3_gpio073 >;
pinctrl-names = "default";
};
&ps2_0 {
status = "okay";
pinctrl-0 = <&ps2_clk0b_gpio007 &ps2_dat0b_gpio010>;
pinctrl-1 = <&ps2_clk0b_gpio007_sleep &ps2_dat0b_gpio010_sleep>;
pinctrl-names = "default", "sleep";
};
&ps2_1 {
status = "okay";
pinctrl-0 = <&ps2_clk1b_gpio154 &ps2_dat1b_gpio155>;
pinctrl-1 = <&ps2_clk1b_gpio154_sleep &ps2_dat1b_gpio155_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_gpio053>;
pinctrl-names = "default";
};
&kbd0 {
status = "okay";
pinctrl-0 = < &kso00_gpio040 &kso01_gpio045 &kso02_gpio046 &kso12_gpio125
&kso13_gpio126 &kso03_gpio047 &kso04_gpio107 &kso05_gpio112
&kso06_gpio113 &kso14_gpio152 &kso15_gpio151 &kso07_gpio120
&kso08_gpio121 &kso09_gpio122 &kso10_gpio123 &kso11_gpio124
&ksi0_gpio017 &ksi1_gpio020 &ksi2_gpio021 &ksi3_gpio026
&ksi4_gpio027 &ksi5_gpio030 &ksi6_gpio031 &ksi7_gpio032 >;
pinctrl-1 = < &kso00_gpio040_sleep &kso01_gpio045_sleep &kso02_gpio046_sleep
&kso12_gpio125_sleep &kso13_gpio126_sleep &kso03_gpio047_sleep
&kso04_gpio107_sleep &kso05_gpio112_sleep &kso06_gpio113_sleep
&kso14_gpio152_sleep &kso15_gpio151_sleep &kso07_gpio120_sleep
&kso08_gpio121_sleep &kso09_gpio122_sleep &kso10_gpio123_sleep
&kso11_gpio124_sleep &ksi0_gpio017_sleep &ksi1_gpio020_sleep
&ksi2_gpio021_sleep &ksi3_gpio026_sleep &ksi4_gpio027_sleep
&ksi5_gpio030_sleep &ksi6_gpio031_sleep &ksi7_gpio032_sleep >;
pinctrl-names = "default", "sleep";
row-size = <8>;
col-size = <16>;
kscan_input: kscan-input {
compatible = "zephyr,kscan-input";
};
};
&peci0 {
status = "okay";
pinctrl-0 = <&peci_dat_gpio042 &vref_vtt_gpio044>;
pinctrl-1 = <&peci_dat_gpio042_sleep &vref_vtt_gpio044_sleep>;
pinctrl-names = "default", "sleep";
};
&tach0 {
status = "okay";
pinctrl-0 = <&ict0_tach0_gpio050>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,298 |
```unknown
/*
*
*/
/dts-v1/;
#include <microchip/mec1501hsz.dtsi>
#include <microchip/mec152x/mec152xhsz-pinctrl.dtsi>
&ps2_clk0b_gpio007 {
drive-open-drain;
};
&ps2_dat0b_gpio010 {
drive-open-drain;
};
&ps2_clk1b_gpio154 {
drive-open-drain;
};
&ps2_dat1b_gpio155 {
drive-open-drain;
};
&kso00_gpio040 {
bias-pull-up;
};
&kso01_gpio045 {
bias-pull-up;
};
&kso02_gpio046 {
bias-pull-up;
};
&kso12_gpio125 {
bias-pull-up;
};
&kso13_gpio126 {
bias-pull-up;
};
&kso03_gpio047 {
bias-pull-up;
};
&kso04_gpio107 {
bias-pull-up;
};
&kso05_gpio112 {
bias-pull-up;
};
&kso06_gpio113 {
bias-pull-up;
};
&kso14_gpio152 {
bias-pull-up;
};
&kso15_gpio151 {
bias-pull-up;
};
&kso07_gpio120 {
bias-pull-up;
};
&kso08_gpio121 {
bias-pull-up;
};
&kso09_gpio122 {
bias-pull-up;
};
&kso10_gpio123 {
bias-pull-up;
};
&kso11_gpio124 {
bias-pull-up;
};
&ksi0_gpio017 {
bias-pull-up;
};
&ksi1_gpio020 {
bias-pull-up;
};
&ksi2_gpio021 {
bias-pull-up;
};
&ksi3_gpio026 {
bias-pull-up;
};
&ksi4_gpio027 {
bias-pull-up;
};
&ksi5_gpio030 {
bias-pull-up;
};
&ksi6_gpio031 {
bias-pull-up;
};
&ksi7_gpio032 {
bias-pull-up;
};
``` | /content/code_sandbox/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 437 |
```yaml
board:
name: mec1501modular_assy6885
vendor: microchip
socs:
- name: mec1501_hsz
``` | /content/code_sandbox/boards/microchip/mec1501modular_assy6885/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
if BOARD_MEC1501MODULAR_ASSY6885
config INPUT
default y if KSCAN
#PS/2 driver is compiled in terms of this flag.
config ESPI_PERIPHERAL_8042_KBC
default y
depends on ESPI_XEC
if RTOS_TIMER
# XEC RTOS timer HW frequency is fixed at 32768
# The driver requires tickless mode and ticks per
# second to be 32768 for accurate operation.
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
config SYS_CLOCK_TICKS_PER_SEC
default 32768
endif # RTOS_TIMER
if !RTOS_TIMER
# If RTOS timer is not enabled we use ARM Cortex-M
# SYSTICK. SYSTICK frequency is 48MHz divided by
# SOC_MEC1501_PROC_CLK_DIV.
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 48000000
config SYS_CLOCK_TICKS_PER_SEC
default 1000
if ESPI
config ESPI_PERIPHERAL_UART_SOC_MAPPING
default 1
endif # ESPI
endif # RTOS_TIMER
endif # BOARD_MEC1501MODULAR_ASSY6885
``` | /content/code_sandbox/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 253 |
```cmake
set(SPI_IMAGE_NAME spi_image.bin)
board_set_flasher_ifnset(dediprog)
# --vcc=0 - use 3.5V to flash
board_finalize_runner_args(dediprog
"--spi-image=${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}"
"--vcc=0"
)
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```yaml
#
#
#
identifier: mec15xxevb_assy6853
name: MEC15XX EVB ASSY 6853
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 32
flash: 224
supported:
- adc
- counter
- espi
- gpio
- i2c
- pwm
- watchdog
- kscan
vendor: microchip
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 108 |
```unknown
config BOARD_MEC15XXEVB_ASSY6853
select SOC_MEC1501_HSZ
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/Kconfig.mec15xxevb_assy6853 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```unknown
#
#
#
CONFIG_SOC_MEC1501_VTR3_1_8V=y
CONFIG_RTOS_TIMER=y
CONFIG_CLOCK_CONTROL=y
CONFIG_CONSOLE=y
CONFIG_PINCTRL=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
# power management stuff
CONFIG_PM=y
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```yaml
board:
name: mec15xxevb_assy6853
vendor: microchip
socs:
- name: mec1501_hsz
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```restructuredtext
.. _mec1501modular_assy6885:
Microchip MEC1501 Modular card ASSY6885
#######################################
Overview
********
The MEC1501 Modular card ASSY6885 is a development board to evaluate the Microchip
MEC152X series microcontrollers. This board can work standalone or be mated with
any platform that complies with MECC specification.
.. image:: mec1501modular_assy6885.jpg
:align: center
:alt: MEC1501 Modular ASSY 6885
Hardware
********
- MEC1521HA0SZ ARM Cortex-M4 Processor
- 256 KB RAM and 64 KB boot ROM
- GPIO headers
- UART1 using microUSB
- PECI interface 3.0
- 10 SMBUS instances
- FAN, PMW and TACHO pins
- VCI interface
- Independent Hardware Driven PS/2 Ports
At difference from MEC15xx evaluation board, modular MEC1521 exposes the pins
in 2 different ways:
1) Standalone mode via headers
- GPIOs
- PWM5
- JTAG/SWD, ETM and MCHP Trace ports
- eSPI bus
- SMB0
2) Mated mode with another platform that has a high density MECC connector.
- FAN0, PWM0, SMB0, SMB1, SMB4 and SMB5
- eSPI bus
- Breathing/Blinking LEDs
The board is powered through the +5V USB Micro A connector or from the MECC connector.
For more information about the SOC please see the `MEC152x Reference Manual`_
Supported Features
==================
The mec1501modular_assy6885 board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| ESPI | on-chip | espi |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| RTOS | on-chip | timer |
+-----------+------------+-------------------------------------+
| TIMER | on-chip | counter |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| PS2 | on-chip | ps2 |
+-----------+------------+-------------------------------------+
Other hardware features are not currently supported by Zephyr (at the moment)
The default configuration can be found in the
:zephyr_file:`boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig`
Kconfig file.
Connections and IOs
===================
This evaluation board kit is comprised of the following HW blocks:
- MEC1501 Modular Card ASSY 6885 Rev A0 `MEC1501 Modular EC Card - Assy_6885 Rev A0p1`_
System Clock
============
The MEC1501 MCU is configured to use the 48Mhz internal oscillator with the
on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock
control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in
the references at the end of this document.
Serial Port
===========
UART1 is configured for serial logs.
Jumper settings
***************
Please follow the jumper settings below to properly demo this
board. Advanced users may deviate from this recommendation.
Jumper setting for MEC1501 Modular Assy 6885 Rev A1p0
=====================================================
Power-related jumpers
---------------------
If you wish to power from type A/B connector ``P10`` set the jumper ``JP35 1-2``.
If you wish to power through MECC connector ``P1`` and mate to external platform,
set the jumper to ``JP35 3-4``.
.. note:: A single jumper is required in JP35.
+------+---------+---------+------+------+------+----------+
| JP30 | JP31 | JP32 | JP33 | JP34 | JP40 | JP21 |
| VTR3 | VTR_PLL | VTR_REG | VTR1 | VTR2 | 3.3V | VREF_ADC |
+======+=========+=========+======+======+======+==========+
| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 |
+------+---------+---------+------+------+------+----------+
+------+------------+------+----------+
| JP6 | JP36 | JP27 | JP4 |
| VBAT | VTR_ANALOG | PECI | VREF_VTT |
+======+============+======+==========+
| 2-3 | 1-2 | 2-3 | open |
+------+------------+------+----------+
These jumpers configure nRESETI and JTAG_STRAP respectively.
+-----------+---------------+
| JP22 | JP29 |
| (nRESETI) | (JTAG_STRAP) |
+===========+===============+
| 11-12 | 1-2 |
+-----------+---------------+
Boot-ROM Straps
---------------
These jumpers configure MEC1501 Boot-ROM straps.
+-------------+------------+--------------+-------------+
| JP37 | J6 | JP41 | JP23 |
| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) |
+=============+============+==============+=============+
| 1-2 | 1-2 | 1-2 | 3-4 |
+-------------+------------+--------------+-------------+
``JP23 3-4`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples
SHD SPI CS0# and if high, it loads code from SHD SPI.
This is the recommended setup.
+-------------+------------+----------------------------+
| CR_STRAP | BSS_STRAP | SOURCE |
+-------------+------------+----------------------------+
| 0 | X | Use 3.3V Private SPI |
+-------------+------------+----------------------------+
| 1 | 0 | Use eSPI Flash channel |
+-------------+------------+----------------------------+
| | 1 | Use 3.3V Shared channel(R)|
+-------------+------------+----------------------------+
Power management
----------------
``JP20 2-3`` is required so all GPIOs powered by VTR3 rail worked at 1.8V.
.. note:: External 1.8V needs to be connected to JP13.1
+-------------------+-----------------+
| JP20 | JP13 |
| (VTR3 selection) | (1.8V source) |
+===================+=================+
| 2-3 | 1.8V to pin 1 |
+-------------------+-----------------+
Jumper location map
-------------------
.. code-block:: none
+your_sha256_hash----------------------+
| |------------| +----------+ J10 || |
| [BT1] + +------------+ J50 ++ ++ || |
| | JP38 JP43 ++ || || |
| + + + +-+ JP4 + + JP26 || || |
| JP6 + + + + + + + + || || |
| JP31 ++ JP32 JP36 +-+ JP27 + + + + J6 || |
| JP18 JP37 JP41 JP42 ++ |
| ++ + + +--------+ J48 |
| || JP21 + + +--------+ JP22 +----------+ |
| J2 || + JP34 JP30 J11 ++ |
| ++ + J44 || |
| ++ +----------------+ || |
| +---------------+ || + JP24 |----------------| ++ |
| |---------------| ++ + +----------+ +----------------+ J47 |
| JP20 +---------------+ JP23 JP40 +----------+ ++ |
| + ++ JP29 || |
| + + +----------+ + || |
| J52+---------------+ + + +----------+ J5 +-------------+ ++ |
| J45+---------------+ JP33 TP57 JP25 +-------------+ J4 J49 |
| |
| ++ TP4 +----------+ ++ |
| ++ + + + + + + TP61 +----------+ ++ |
| JP28 + + + + + TP65 + TP60 J51 JP35 |
| TP58 JP16 JP11 JP13 JP15 JP10 |
| TP5 |
| TP6 TP1 |
+your_sha256_hash----------------------+
Programming and Debugging
*************************
Setup
=====
#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within
that directory. For the pre-production MEC150x use the `MEC150x SPI Image Gen`_
repository.
#. Make the image generation available for Zephyr, by making the tool
searchable by path, or by setting an environment variable
``EVERGLADES_SPI_GEN``, for example:
.. code-block:: console
export EVERGLADES_SPI_GEN=<path to tool>/everglades_spi_gen_RomE
Note that the tools for Linux and Windows have different file names.
For the pre-production MEC1501 SOC use everglades_spi_gen_lin64.
#. If needed, a custom SPI image configuration file can be specified
to override the default one.
.. code-block:: console
export EVERGLADES_SPI_CFG=custom_spi_cfg.txt
Building
==========
#. Build :ref:`hello_world` application as you would normally do.
#. Once you have ``zephyr.bin``, use the `MEC152x SPI Image Gen`_ microchip tool
to create the final binary. You need the output from this tool to flash
in the SHD SPI memory.
Flashing
========
#. Connect Dediprog into header ``J2``.
#. Flash the SPI NOR ``U3`` at offset 0x0 using Dediprog SF100
or a similar tool for flashing SPI chips.
#. Run your favorite terminal program to listen for output. Under Linux the
terminal should be :code:`/dev/ttyACM0`. For example:
.. code-block:: console
$ minicom -D /dev/ttyACM0 -o
The -o option tells minicom not to send the modem initialization
string. Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
#. Connect the MEC1501MODULAR_ASSY6885 board to your host computer using the
UART1 port and apply power.
You should see ``"Hello World! mec1501modular_assy6885"`` in your terminal.
Debugging
=========
This board comes with a Cortex ETM port which facilitates tracing and debugging
using a single physical connection. In addition, it comes with sockets for
JTAG only sessions.
HW Issues
=========
In case you don't see your application running, please make sure ``LED1`` is lit.
If is off, then check the power related jumpers again.
References
**********
.. target-notes::
.. _MEC152x Preliminary Data Sheet:
path_to_url
.. _MEC152x Reference Manual:
path_to_url
.. _MEC1501 Modular EC Card - Assy_6885 Rev A0p1:
path_to_url
.. _MEC152x SPI Image Gen:
path_to_url
.. _MEC150x SPI Image Gen:
path_to_url
``` | /content/code_sandbox/boards/microchip/mec1501modular_assy6885/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,883 |
```unknown
/*
*
*/
/dts-v1/;
#include "mec15xxevb_assy6853-pinctrl.dtsi"
/ {
model = "Microchip MEC15XXEVB_ASSY6853 evaluation board";
compatible = "microchip,mec15xxevb_assy6853", "microchip,mec1501hsz";
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart2;
zephyr,flash = &flash0;
zephyr,keyboard-scan = &kscan_input;
};
aliases {
led0 = &led2;
led1 = &led3;
led2 = &led4;
pwm-0 = &pwm0;
peci-0 = &peci0;
i2c0 = &i2c_smb_0;
i2c-0 = &i2c_smb_0;
i2c1 = &i2c_smb_1;
i2c7 = &i2c_smb_2;
kscan0 = &kscan_input;
watchdog0 = &wdog;
};
leds {
compatible = "gpio-leds";
led2: led_0 {
/* GPIO156/LED0 on schematic,
* LED2 on silkscreen.
*/
gpios = <MCHP_GPIO_DECODE_156 GPIO_ACTIVE_LOW>;
label = "LED 2";
};
led3: led_1 {
/* GPIO157/LED1 on schematic,
* LED3 on silkscreen.
*/
gpios = <MCHP_GPIO_DECODE_157 GPIO_ACTIVE_LOW>;
label = "LED 3";
};
led4: led_2 {
/* GPIO153/LED2 on schematic,
* LED4 on silkscreen.
*/
gpios = <MCHP_GPIO_DECODE_153 GPIO_ACTIVE_LOW>;
label = "LED 4";
};
};
};
&pcr {
status = "okay";
};
&uart2 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart2_tx_gpio146 &uart2_rx_gpio145>;
pinctrl-names = "default";
};
&adc0 {
status = "okay";
pinctrl-0 = <&adc04_gpio204 &adc05_gpio205
&adc06_gpio206 &adc07_gpio207
&vref2_adc_gpio067 >;
pinctrl-names = "default";
};
&i2c_smb_0 {
status = "okay";
port_sel = <0>;
sda-gpios = <MCHP_GPIO_DECODE_003 0>;
scl-gpios = <MCHP_GPIO_DECODE_004 0>;
pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
pinctrl-names = "default";
};
&i2c_smb_1 {
status = "okay";
port_sel = <1>;
sda-gpios = <MCHP_GPIO_DECODE_130 0>;
scl-gpios = <MCHP_GPIO_DECODE_131 0>;
pinctrl-0 = < &i2c01_scl_gpio131 &i2c01_sda_gpio130 >;
pinctrl-names = "default";
pca9555@26 {
compatible = "nxp,pca95xx";
/* Depends on JP53 for device address.
* Pin 1-2 = A0, pin 3-4 = A1, pin 5-6 = A2.
* Address is: 0100<A2><A1><A0>b.
*
* Default has pin 1-2 on JP53 connected,
* resulting in device address 0x26.
*/
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c_smb_2 {
status = "okay";
port_sel = <7>;
sda-gpios = <MCHP_GPIO_DECODE_012 0>;
scl-gpios = <MCHP_GPIO_DECODE_013 0>;
pinctrl-0 = < &i2c07_scl_gpio013 &i2c07_sda_gpio012 >;
pinctrl-names = "default";
};
&espi0 {
status = "okay";
io_girq = <19>;
vw_girqs = <24 25>;
pc_girq = <15>;
pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066
&espi_alert_n_gpio063 &espi_clk_gpio065
&espi_io0_gpio070 &espi_io1_gpio071
&espi_io2_gpio072 &espi_io3_gpio073 >;
pinctrl-names = "default";
};
&timer5 {
status = "okay";
};
&ps2_0 {
status = "okay";
pinctrl-0 = <&ps2_clk0b_gpio007 &ps2_dat0b_gpio010>;
pinctrl-1 = <&ps2_clk0b_gpio007_sleep &ps2_dat0b_gpio010_sleep>;
pinctrl-names = "default", "sleep";
};
&ps2_1 {
status = "okay";
pinctrl-0 = <&ps2_clk1b_gpio154 &ps2_dat1b_gpio155>;
pinctrl-1 = <&ps2_clk1b_gpio154_sleep &ps2_dat1b_gpio155_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_gpio053>;
pinctrl-names = "default";
};
&kbd0 {
status = "okay";
pinctrl-0 = < &kso00_gpio040 &kso01_gpio045 &kso02_gpio046 &kso12_gpio125
&kso13_gpio126 &kso03_gpio047 &kso04_gpio107 &kso05_gpio112
&kso06_gpio113 &kso14_gpio152 &kso15_gpio151 &kso07_gpio120
&kso08_gpio121 &kso09_gpio122 &kso10_gpio123 &kso11_gpio124
&ksi0_gpio017 &ksi1_gpio020 &ksi2_gpio021 &ksi3_gpio026
&ksi4_gpio027 &ksi5_gpio030 &ksi6_gpio031 &ksi7_gpio032 >;
pinctrl-1 = < &kso00_gpio040_sleep &kso01_gpio045_sleep &kso02_gpio046_sleep
&kso12_gpio125_sleep &kso13_gpio126_sleep &kso03_gpio047_sleep
&kso04_gpio107_sleep &kso05_gpio112_sleep &kso06_gpio113_sleep
&kso14_gpio152_sleep &kso15_gpio151_sleep &kso07_gpio120_sleep
&kso08_gpio121_sleep &kso09_gpio122_sleep &kso10_gpio123_sleep
&kso11_gpio124_sleep &ksi0_gpio017_sleep &ksi1_gpio020_sleep
&ksi2_gpio021_sleep &ksi3_gpio026_sleep &ksi4_gpio027_sleep
&ksi5_gpio030_sleep &ksi6_gpio031_sleep &ksi7_gpio032_sleep >;
pinctrl-names = "default", "sleep";
row-size = <8>;
col-size = <16>;
kscan_input: kscan-input {
compatible = "zephyr,kscan-input";
};
};
&peci0 {
status = "okay";
pinctrl-0 = <&peci_dat_gpio042 &vref_vtt_gpio044>;
pinctrl-1 = <&peci_dat_gpio042_sleep &vref_vtt_gpio044_sleep>;
pinctrl-names = "default", "sleep";
};
&spi0 {
status = "okay";
port_sel = <0>;
chip_select = <0>;
lines = <1>;
pinctrl-0 = < &shd_cs0_n_gpio055
&shd_clk_gpio056
&shd_io0_gpio223
&shd_io1_gpio224 >;
pinctrl-names = "default";
};
&tach0 {
status = "okay";
pinctrl-0 = <&ict0_tach0_gpio050>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,856 |
```unknown
if BOARD_MEC15XXEVB_ASSY6853
config INPUT
default y if KSCAN
config ESPI_XEC
default y
depends on ESPI
if RTOS_TIMER
# XEC RTOS timer HW frequency is fixed at 32768
# The driver requires tickless mode and ticks per
# second to be 32768 for accurate operation.
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
config SYS_CLOCK_TICKS_PER_SEC
default 32768
endif # RTOS_TIMER
if !RTOS_TIMER
# If RTOS timer is not enabled we use ARM Cortex-M
# SYSTICK. SYSTICK frequency is 48MHz divided by
# SOC_MEC1501_PROC_CLK_DIV.
#
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 48000000
config SYS_CLOCK_TICKS_PER_SEC
default 1000
endif # RTOS_TIMER
endif # BOARD_MEC15XXEVB_ASSY6853
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 210 |
```objective-c
/*
*
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
#include <soc.h>
#endif /* __INC_BOARD_H */
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/board.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
/*
*
*/
/dts-v1/;
#include <microchip/mec1501hsz.dtsi>
#include <microchip/mec152x/mec152xhsz-pinctrl.dtsi>
&ps2_clk0b_gpio007 {
drive-open-drain;
};
&ps2_dat0b_gpio010 {
drive-open-drain;
};
&ps2_clk1b_gpio154 {
drive-open-drain;
};
&ps2_dat1b_gpio155 {
drive-open-drain;
};
&kso00_gpio040 {
bias-pull-up;
};
&kso01_gpio045 {
bias-pull-up;
};
&kso02_gpio046 {
bias-pull-up;
};
&kso12_gpio125 {
bias-pull-up;
};
&kso13_gpio126 {
bias-pull-up;
};
&kso03_gpio047 {
bias-pull-up;
};
&kso04_gpio107 {
bias-pull-up;
};
&kso05_gpio112 {
bias-pull-up;
};
&kso06_gpio113 {
bias-pull-up;
};
&kso14_gpio152 {
bias-pull-up;
};
&kso15_gpio151 {
bias-pull-up;
};
&kso07_gpio120 {
bias-pull-up;
};
&kso08_gpio121 {
bias-pull-up;
};
&kso09_gpio122 {
bias-pull-up;
};
&kso10_gpio123 {
bias-pull-up;
};
&kso11_gpio124 {
bias-pull-up;
};
&ksi0_gpio017 {
bias-pull-up;
};
&ksi1_gpio020 {
bias-pull-up;
};
&ksi2_gpio021 {
bias-pull-up;
};
&ksi3_gpio026 {
bias-pull-up;
};
&ksi4_gpio027 {
bias-pull-up;
};
&ksi5_gpio030 {
bias-pull-up;
};
&ksi6_gpio031 {
bias-pull-up;
};
&ksi7_gpio032 {
bias-pull-up;
};
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 437 |
```restructuredtext
.. _boards-kincony:
Kincony
#######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/kincony/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```cmake
if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
set(OPENOCD OPENOCD-NOTFOUND)
endif()
find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
config BOARD_KINCONY_KC868_A32
select SOC_ESP32_WROOM_32UE_N4
select SOC_ESP32_PROCPU if BOARD_KINCONY_KC868_A32_ESP32_PROCPU
select SOC_ESP32_APPCPU if BOARD_KINCONY_KC868_A32_ESP32_APPCPU
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/Kconfig.kincony_kc868_a32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```unknown
choice BOOTLOADER
default BOOTLOADER_MCUBOOT
endchoice
choice BOOT_SIGNATURE_TYPE
default BOOT_SIGNATURE_TYPE_NONE
endchoice
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32/esp32_wroom_32ue_n4.dtsi>
#include "kincony_kc868_a32-pinctrl.dtsi"
/ {
model = "Kincony KC868_A32 PROCPU";
compatible = "espressif,esp32";
aliases {
uart-0 = &uart0;
watchdog0 = &wdt0;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,bt-hci = &esp32_bt_hci;
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_STANDARD>;
sda-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>;
scl-gpios = <&gpio0 13 GPIO_OPEN_DRAIN>;
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
i2c0_pcf8574@21 {
compatible = "nxp,pcf857x";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
};
i2c0_pcf8574@22 {
compatible = "nxp,pcf857x";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
};
i2c0_pcf8574@24 {
compatible = "nxp,pcf857x";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
};
i2c0_pcf8574@25 {
compatible = "nxp,pcf857x";
reg = <0x25>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <I2C_BITRATE_STANDARD>;
sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>;
scl-gpios = <&gpio0 5 GPIO_OPEN_DRAIN>;
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
i2c1_pcf8574@21 {
compatible = "nxp,pcf857x";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
};
i2c1_pcf8574@22 {
compatible = "nxp,pcf857x";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
};
i2c1_pcf8574@24 {
compatible = "nxp,pcf857x";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
};
i2c1_pcf8574@25 {
compatible = "nxp,pcf857x";
reg = <0x25>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
};
};
&mdio {
pinctrl-0 = <&mdio_default>;
pinctrl-names = "default";
status = "okay";
phy: ethernet-phy@0 {
compatible = "ethernet-phy";
status = "okay";
reg = <0>;
};
};
ð {
status = "okay";
phy-handle = <&phy>;
ref-clk-output-gpios = <&gpio0 17 0>;
};
&psram0 {
status = "disabled";
};
&timer0 {
status = "okay";
};
&timer1 {
status = "okay";
};
&timer2 {
status = "okay";
};
&timer3 {
status = "okay";
};
&trng0 {
status = "okay";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 60kB for the bootloader */
boot_partition: partition@1000 {
label = "mcuboot";
reg = <0x00001000 0x0000F000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
&esp32_bt_hci {
status = "okay";
};
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,281 |
```yaml
identifier: kincony_kc868_a32/esp32/procpu
name: KINCONY-KC868-A32 PROCPU
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- gpio
- i2c
- watchdog
- uart
- nvs
- counter
- entropy
testing:
ignore_tags:
- net
- bluetooth
vendor: kincony
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```yaml
board:
name: kincony_kc868_a32
vendor: kincony
socs:
- name: esp32
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32/esp32_appcpu.dtsi>
/ {
model = "Kincony KC868_A32 APPCPU";
compatible = "espressif,esp32";
chosen {
zephyr,sram = &sram0;
zephyr,ipc_shm = &shm0;
zephyr,ipc = &ipm0;
};
};
&ipm0 {
status = "okay";
};
&trng0 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 60kB for the bootloader */
boot_partition: partition@1000 {
label = "mcuboot";
reg = <0x00001000 0x0000F000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 405 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32-gpio-sigmap.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_GPIO1>;
output-high;
};
group2 {
pinmux = <UART0_RX_GPIO3>;
bias-pull-up;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_GPIO15>,
<I2C0_SCL_GPIO13>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <I2C1_SDA_GPIO4>,
<I2C1_SCL_GPIO5>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
mdio_default: mdio_default {
group1 {
pinmux = <SMI_MDC_GPIO23>,
<SMI_MDIO_GPIO18>;
};
};
};
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 294 |
```yaml
identifier: kincony_kc868_a32/esp32/appcpu
name: KINCONY-KC868-A32 APPCPU
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- uart
testing:
ignore_tags:
- net
- bluetooth
- flash
- cpp
- posix
- watchdog
- logging
- kernel
- pm
- gpio
- crypto
- eeprom
- heap
- cmsis_rtos
- jwt
- zdsp
vendor: espressif
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```unknown
if BOARD_KINCONY_KC868_A32_ESP32_PROCPU
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
endif # BOARD_KINCONY_KC868_A32_ESP32_PROCPU
if BOARD_KINCONY_KC868_A32_ESP32_APPCPU
config HEAP_MEM_POOL_ADD_SIZE_BOARD
default 256
endif # BOARD_KINCONY_KC868_A32_ESP32_APPCPU
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
CONFIG_I2C=y
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```ini
set ESP_RTOS none
set ESP32_ONLYCPU 1
source [find interface/ftdi/esp32_devkitj_v1.cfg]
source [find target/esp32.cfg]
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```restructuredtext
.. _kincony_kc868_a32:
KINCONY KC868-A32
#################
Overview
********
Kincony KC868-A32 is a home automation relay module based on the
Espressif ESP-WROOM-32 module with all its inherent capabilities
(Wi-Fi, Bluetooth, etc.)
The features include the following:
- 32 digital optoisolated inputs dry contact
- 4 analog inputs 0-5 V
- 32 relays 220 V, 10 A (COM, NO, NC)
- RS485 interface
- I2C connector
- Connector GSM/HMI
- Ethernet LAN8270A
- USB Type-B connector for programming and filling firmware
- RESET and DOWNLOAD buttons
- Powered by 12V DC
.. figure:: img/kincony_kc868_a32.jpg
:align: center
:alt: KINCONCY-KC868-A32
KINCONCY-KC868-A32
System requirements
===================
Prerequisites
-------------
Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
below to retrieve those files.
.. code-block:: console
west blobs fetch hal_espressif
.. note::
It is recommended running the command above after :file:`west update`.
Building & Flashing
-------------------
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: kincony_kc868_a32/esp32/procpu
:goals: build
The usual ``flash`` target will work with the ``kincony_kc868_a32`` board
configuration. Here is an example for the :ref:`hello_world`
application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: kincony_kc868_a32/esp32/procpu
:goals: flash
Open the serial monitor using the following command:
.. code-block:: shell
west espressif monitor
After the board has automatically reset and booted, you should see the following
message in the monitor:
.. code-block:: console
***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! kincony_kc868_a32
Enabling Ethernet
*****************
Enable Ethernet in KConfig:
.. code-block:: cfg
CONFIG_NETWORKING=y
CONFIG_NET_L2_ETHERNET=y
CONFIG_MDIO=y
References
**********
.. _KINCONY KC868-A32 User Guide: path_to_url
``` | /content/code_sandbox/boards/kincony/kincony_kc868_a32/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 578 |
```restructuredtext
.. _mec15xxevb_assy6853:
Microchip MEC15xxEVB ASSY6853
#############################
Overview
********
The MEC15xxEVB_ASSY6853 kit is a future development platform to evaluate the
Microchip MEC15XX series microcontrollers. This board needs to be mated with
part number MEC1501 144WFBA SOLDER DC ASSY 6860(cpu board) in order to operate.
The MEC152x has superseded the MEC1501 in production. MEC152x is identical to
MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has
been updated requiring a new SPI image tool. MEC1501 and MEC152x SPI image
formats are not compatible with each other. Evaluation and cpu boards are
compatible.
.. image:: mec15xxevb_assy6853.jpg
:align: center
:alt: MEC15XX EVB ASSY 6853
Hardware
********
- MEC1521HA0SZ ARM Cortex-M4 Processor
- 256 KB RAM and 64 KB boot ROM
- Keyboard interface
- ADC & GPIO headers
- UART0, UART1, and UART2
- FAN0, FAN1, FAN2 headers
- FAN PWM interface
- JTAG/SWD, ETM and MCHP Trace ports
- PECI interface 3.0
- I2C voltage translator
- 10 SMBUS headers
- 4 SGPIO headers
- VCI interface
- 5 independent Hardware Driven PS/2 Ports
- eSPI header
- 3 Breathing/Blinking LEDs
- 2 Sockets for SPI NOR chips
- One reset and VCC_PWRDGD pushbuttons
- One external PCA9555 I/O port with jumper selectable I2C address.
- One external LTC2489 delta-sigma ADC with jumper selectable I2C address.
- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector.
For more information about the SOC's please see `MEC152x Reference Manual`_
Supported Features
==================
The mec15xxevb_assy6853 board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| PS/2 | on-chip | ps2 |
+-----------+------------+-------------------------------------+
| KSCAN | on-chip | kscan |
+-----------+------------+-------------------------------------+
| TACH | on-chip | tachometer |
+-----------+------------+-------------------------------------+
Other hardware features are not currently supported by Zephyr (at the moment)
The default configuration can be found in the
:zephyr_file:`boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig` Kconfig file.
Connections and IOs
===================
This evaluation board kit is comprised of the following HW blocks:
- MEC15xx EVB ASSY 6853 Rev A `MEC15xx EVB Schematic`_
- MEC1501 144WFBA SOLDER DC ASSY 6883 with MEC152x silicon `MEC1501 Daughter Card Schematic`_
- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_
System Clock
============
The MEC1521 MCU is configured to use the 48Mhz internal oscillator with the
on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock
control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in
the references at the end of this document.
Serial Port
===========
UART2 is configured for serial logs.
Jumper settings
***************
Please follow the jumper settings below to properly demo this
board. Advanced users may deviate from this recommendation.
Jumper setting for MEC15xx EVB Assy 6853 Rev A1p0
=================================================
Power-related jumpers
---------------------
If you wish to power from +5V power brick, then connect to barrel connector ``P11``
(5.5mm OD, 2.1mm ID) and move the jumper to ``JP88 5-6``.
If you wish to power from micro-USB type A/B connector ``P12``, move the
jumper to ``JP88 7-8``.
.. note:: A single jumper is required in JP88.
+-------+------+------+------+------+------+------+------+------+------+------+
| JP22 | JP32 | JP33 | JP37 | JP43 | JP47 | JP54 | JP56 | JP58 | JP64 | JP65 |
+=======+======+======+======+======+======+======+======+======+======+======+
| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 |
+-------+------+------+------+------+------+------+------+------+------+------+
+------+------+------+------+------+------+------+------+------+------+
| JP72 | JP73 | JP76 | JP79 | JP80 | JP81 | JP82 | JP84 | JP87 | JP89 |
+======+======+======+======+======+======+======+======+======+======+
| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 |
+------+------+------+------+------+------+------+------+------+------+
+------+------+-------+-------+-------+
| JP90 | JP91 | JP100 | JP101 | JP118 |
+======+======+=======+=======+=======+
| 1-2 | 1-2 | 1-2 | 1-2 | 2-3 |
+------+------+-------+-------+-------+
These jumpers configure VCC Power good, nRESETI and JTAG_STRAP respectively.
+------------------+-----------+--------------+
| JP5 | JP4 | JP45 |
| (VCC Power good) | (nRESETI) | (JTAG_STRAP) |
+==================+===========+==============+
| 1-2 | 1-2 | 2-3 |
+------------------+-----------+--------------+
Boot-ROM Straps.
----------------
These jumpers configure MEC1501 Boot-ROM straps.
+-------------+------------+--------------+-------------+
| JP93 | JP11 | JP46 | JP96 |
| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) |
+=============+============+==============+=============+
| 2-3 | 1-2 | 2-3 | 1-2 |
+-------------+------------+--------------+-------------+
``JP96 1-2`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples
SHD SPI CS0# and if high, it loads code from SHD SPI.
Peripheral Routing Jumpers
--------------------------
Each column of the following table illustrates how to enable UART2, SWD,
PVT SPI, SHD SPI and LED0-2 respectively.
+----------+----------+--------+-----------+----------+---------+
| JP48 | JP9 | JP9 | JP38 | JP98 | JP41 |
| (UART2) | (UART2) | (SWD) | (PVT SPI) | (SHD SPI)| (LED0-2)|
+==========+==========+========+===========+==========+=========+
| 1-2 | | 2-3 | 2-3 | 2-3 | 1-2 |
+----------+----------+--------+-----------+----------+---------+
| 4-5 | 4-5 | | 5-6 | 5-6 | 3-4 |
+----------+----------+--------+-----------+----------+---------+
| 7-8 | | 8-9 | 8-9 | 8-9 | 5-6 |
+----------+----------+--------+-----------+----------+---------+
| 10-11 | 10-11 | | 11-12 | 11-12 | |
+----------+----------+--------+-----------+----------+---------+
| | | | 14-15 | 14-15 | |
+----------+----------+--------+-----------+----------+---------+
| | | | 17-18 | 20-21 | |
+----------+----------+--------+-----------+----------+---------+
.. note:: For UART2 make sure JP39 have jumpers connected 1-2, 3-4.
To receive UART2 serial output, please refer to the picture below
to make sure that JP9 configured for UART2 output.
.. image:: mec15xxevb_assy6853_jp9_1.jpg
:align: center
:alt: JP9 header Assy6853
Jumper settings for MEC1501 144WFBGA Socket DC Assy 6883 Rev B1p0
=================================================================
The jumper configuration explained above covers the base board. The ASSY
6883 MEC1501 CPU board provides capability for an optional, external 32KHz
clock source. The card includes a 32KHz crystal oscillator. The card can
also be configured to use an external 50% duty cycle 32KHz source on the
XTAL2/32KHZ_IN pin. Note, firmware must set the MEC15xx clock enable
register to select the external source matching the jumper settings. If
using the MEC15xx internal silicon oscillator then the 32K jumper settings
are don't cares. ``JP1`` is for scoping test clock outputs. Please refer to
the schematic in reference section below.
Parallel 32KHz crystal configuration
------------------------------------
+-------+-------+
| JP2 | JP3 |
+=======+=======+
| 1-2 | 2-3 |
+-------+-------+
External 32KHz 50% duty cycle configuration
-------------------------------------------
+-------+-------+
| JP2 | JP3 |
+=======+=======+
| NC | 1-2 |
+-------+-------+
Jumper settings for MEC1503 144WFBGA Socket DC Assy 6856 Rev B1p0
=================================================================
The MEC1503 ASSY 6856 CPU card does not include an onboard external
32K crystal or oscillator. The one jumper block ``JP1`` is for scoping
test clock outputs not for configuration. Please refer to schematic
in reference section below.
Programming and Debugging
*************************
Setup
=====
#. If you use Dediprog SF100 programmer, then setup it.
Windows version can be found at the `SF100 Product page`_.
Linux version source code can be found at `SF100 Linux GitHub`_.
Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer.
For Linux please make sure that you copied ``60-dediprog.rules``
from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d)
then restart service using:
.. code-block:: console
$ udevadm control --reload
Add directory with program ``dpcmd`` (on Linux)
or ``dpcmd.exe`` (on Windows) to your ``PATH``.
#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within
that directory. For the pre-production MEC150x use `MEC150x SPI Image Gen`_
repository.
#. Make the image generation available for Zephyr, by making the tool
searchable by path, or by setting an environment variable
``EVERGLADES_SPI_GEN``, for example:
.. code-block:: console
export EVERGLADES_SPI_GEN=<path to tool>/everglades_spi_gen_RomE
Note that the tools for Linux and Windows have different file names.
For the pre-production MEC1501 SOC use everglades_spi_gen_lin64.
#. If needed, a custom SPI image configuration file can be specified
to override the default one.
.. code-block:: console
export EVERGLADES_SPI_CFG=custom_spi_cfg.txt
Wiring
========
#. Connect the SPI Dongle ASSY 6791 to ``J44`` in the EVB.
.. image:: spidongle_assy6791_view1.jpg
:align: center
:alt: SPI DONGLE ASSY 6791 Connected
#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip ``U3``
Make sure that your programmer's offset is 0x0.
For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips.
.. list-table:: Microchip board wiring
:align: center
* -
.. image:: spidongle_assy6791.jpg
:align: center
:alt: SPI DONGLE ASSY 6791
-
.. image:: spidongle_assy6791_view2.jpg
:align: center
:alt: SPI DONGLE ASSY 6791 view 2
|
.. image:: dediprog_connector_2.jpg
:align: center
:alt: SPI DONGLE ASSY 6791 Connected
.. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers!
Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board.
Wiring connection is described in the table below.
+------------+---------------+
| Dediprog | Assy6791 |
| Connector | J6 Connector |
+============+===============+
| VCC | 1 |
+------------+---------------+
| GND | 2 |
+------------+---------------+
| CS | 3 |
+------------+---------------+
| CLK | 4 |
+------------+---------------+
| MISO | 6 |
+------------+---------------+
| MOSI | 5 |
+------------+---------------+
#. Connect UART2 port of the MEC15xxEVB_ASSY_6853 board
to your host computer using the RS232 cable.
#. Apply power to the board via a micro-USB cable.
Configure this option by using a jumper between ``JP88 7-8``.
.. image:: jp88_power_options.jpg
:align: center
:alt: SPI DONGLE ASSY 6791 Connected
#. Final wiring for the board should look like this:
.. image:: mec_board_setup.jpg
:align: center
:alt: SPI DONGLE ASSY 6791 Connected
Building
========
#. Build :ref:`hello_world` application as you would normally do.
#. The file :file:`spi_image.bin` will be created if the build system
can find the image generation tool. This binary image can be used
to flash the SPI chip.
Flashing
========
#. Run your favorite terminal program to listen for output.
Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it.
For example:
.. code-block:: console
$ minicom -D /dev/ttyUSB0 -o
The -o option tells minicom not to send the modem initialization
string. Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
#. Flash your board using ``west`` from the second terminal window.
Split first and second terminal windows to view both of them.
.. code-block:: console
$ west flash
.. note:: When west process started press Reset button and do not release it
till the whole west process will not be finished successfully.
.. image:: reset_button_1.jpg
:align: center
:alt: SPI DONGLE ASSY 6791 Connected
.. note:: If you don't want to press Reset button every time, you can disconnect
SPI Dongle ASSY 6791 from the EVB during the west flash programming.
Then connect it back to the ``J44`` header and apply power to the EVB.
Result will be the same.
#. You should see ``"Hello World! mec15xxevb_assy6853"`` in the first terminal window.
If you don't see this message, press the Reset button and the message should appear.
Debugging
=========
This board comes with a Cortex ETM port which facilitates tracing and debugging
using a single physical connection. In addition, it comes with sockets for
JTAG only sessions.
Troubleshooting
===============
#. In case you don't see your application running, please make sure ``LED7``, ``LED8``, and ``LED1``
are lit. If one of these is off, then check the power-related jumpers again.
#. If you can't program the board using Dediprog, disconnect the Assy6791
from the main board Assy6853 and try again.
#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again.
Notes
=====
#. To enable PCA9555PW and test the I2C on mec15xxevb_assy6853, additional works are needed:
As the I2C slave device NXP pca95xx on mec15xxevb_assy6853 is connected to I2C00 port,
however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log,
so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use
I2C01 port by making some jumpers setting as below:
* JP99 1-2 Connected Connect I2C01_SDA from CPU to header J5
* JP99 13-14 Connected Connect I2C01_SCL from CPU to header J5
* JP25 21-22 Connected External pull-up for I2C01_SDA
* JP25 23-24 Connected External pull-up for I2C01_SCL
*
* JP44.1 J5.1 Connected Connect NXP PCA95xx to I2C01
* JP44.3 J5.3 Connected Connect NXP PCA95xx to I2C01
References
**********
.. target-notes::
.. _MEC1501 Preliminary Data Sheet:
path_to_url
.. _MEC1501 Reference Manual:
path_to_url
.. _MEC152x Preliminary Data Sheet:
path_to_url
.. _MEC152x Reference Manual:
path_to_url
.. _MEC15xx EVB Schematic:
path_to_url
.. _MEC1501 Daughter Card Schematic:
path_to_url
.. _MEC1503 Daughter Card Schematic:
path_to_url
.. _SPI Dongle Schematic:
path_to_url
.. _MEC152x SPI Image Gen:
path_to_url
.. _MEC150x SPI Image Gen:
path_to_url
.. _SF100 Linux GitHub:
path_to_url
.. _SF100 Product page:
path_to_url
.. _SF100 Linux manual:
path_to_url
``` | /content/code_sandbox/boards/microchip/mec15xxevb_assy6853/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,487 |
```restructuredtext
.. _boards-pjrc:
PJRC
####
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/pjrc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```yaml
#
#
#
identifier: teensy40
name: PJRC TEENSY40
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 768
flash: 2048
supported:
- counter
- gpio
- usb_device
testing:
ignore_tags:
- net
- posix
vendor: nxp
``` | /content/code_sandbox/boards/pjrc/teensy4/teensy40.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
#
#
#
config BOARD_TEENSY40
select SOC_PART_NUMBER_MIMXRT1062DVJ6A
``` | /content/code_sandbox/boards/pjrc/teensy4/Kconfig.teensy40 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```c
/*
*
* refer to hal_nxp board file
*
*/
#include <flexspi_nor_config.h>
#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const struct flexspi_nor_config_t Qspiflash_config = {
.memConfig = {
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc =
kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 8u * 1024u * 1024u,
.lookupTable = {
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0xEB, RADDR_SDR,
FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD,
0x06, READ_SDR,
FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = false,
};
#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */
``` | /content/code_sandbox/boards/pjrc/teensy4/flexspi_nor_config.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 364 |
```cmake
board_set_flasher_ifnset(teensy)
if(CONFIG_BOARD_TEENSY40)
board_runner_args(teensy "--mcu=TEENSY40")
else()
board_runner_args(teensy "--mcu=TEENSY41")
endif()
include(${ZEPHYR_BASE}/boards/common/teensy.board.cmake)
``` | /content/code_sandbox/boards/pjrc/teensy4/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
#
#
#
CONFIG_DEVICE_CONFIGURATION_DATA=n
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/pjrc/teensy4/teensy41_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
#
#
#
CONFIG_DEVICE_CONFIGURATION_DATA=n
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/pjrc/teensy4/teensy40_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
#
#
#
config BOARD_TEENSY41
select SOC_PART_NUMBER_MIMXRT1062DVL6A
``` | /content/code_sandbox/boards/pjrc/teensy4/Kconfig.teensy41 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```yaml
#
#
#
identifier: teensy41
name: PJRC TEENSY41
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 768
flash: 8192
supported:
- counter
- gpio
- sdhc
- usb_device
testing:
ignore_tags:
- net
- posix
vendor: nxp
``` | /content/code_sandbox/boards/pjrc/teensy4/teensy41.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 99 |
```yaml
boards:
- name: teensy40
vendor: pjrc
socs:
- name: mimxrt1062
- name: teensy41
vendor: pjrc
socs:
- name: mimxrt1062
``` | /content/code_sandbox/boards/pjrc/teensy4/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
#
#
#
if BOARD_TEENSY40 || BOARD_TEENSY41
config BUILD_OUTPUT_HEX
bool
default y
config DISK_DRIVER_SDMMC
default y if DISK_DRIVERS
endif # BOARD_TEENSY40 || BOARD_TEENSY41
``` | /content/code_sandbox/boards/pjrc/teensy4/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt1060.dtsi>
#include "teensy4-pinctrl.dtsi"
#include <freq.h>
#include <mem.h>
/ {
model = "PJRC TEENSY 4.0 board";
compatible = "nxp,mimxrt1062";
aliases {
led0 = &board_led;
};
chosen {
zephyr,flash-controller = &w25q16jvuxim;
zephyr,flash = &w25q16jvuxim;
zephyr,sram = &ocram;
zephyr,itcm = &itcm;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart6; /* Teensy Pins 0(RX1) 1(TX1) */
zephyr,shell-uart = &lpuart6;
zephyr,canbus = &flexcan1; /* Teensy Pins 23(CRX1) 22(CTX1) */
};
leds {
compatible = "gpio-leds";
board_led: led-1 {
gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
label = "User LED Pin 13";
};
};
};
&flexspi {
status = "okay";
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(2)>;
/* WINBOND flash memory*/
w25q16jvuxim: w25q16jvuxim@0 {
compatible = "nxp,imx-flexspi-nor";
size = <DT_SIZE_M(2 * 8)>;
reg = <0>;
spi-max-frequency = <DT_FREQ_M(133)>;
status = "okay";
jedec-id = [ef 40 15];
erase-block-size = <4096>;
write-block-size = <1>;
};
};
zephyr_udc0: &usb1 {
status = "okay";
};
&lpuart6 {
status = "okay";
current-speed = < 115200 >;
};
&edma0 {
status = "okay";
};
/* Pinmux settings */
&enet_mac {
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
zephyr,random-mac-address;
phy-connection-type = "rmii";
phy-handle = <&phy>;
};
&enet_mdio {
status = "okay";
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "ethernet-phy";
reg = <0>;
status = "okay";
};
};
&flexcan1 {
pinctrl-0 = <&pinmux_flexcan1>;
pinctrl-names = "default";
status = "okay";
};
&flexcan2 {
pinctrl-0 = <&pinmux_flexcan2>;
pinctrl-names = "default";
};
&flexcan3 {
pinctrl-0 = <&pinmux_flexcan3>;
pinctrl-names = "default";
};
&lpi2c1 {
pinctrl-0 = <&pinmux_lpi2c1>;
pinctrl-names = "default";
};
&lpi2c3 {
pinctrl-0 = <&pinmux_lpi2c3>;
pinctrl-names = "default";
};
&lpi2c4 {
pinctrl-0 = <&pinmux_lpi2c4>;
pinctrl-names = "default";
};
&lpspi3 {
pinctrl-0 = <&pinmux_lpspi3>;
pinctrl-names = "default";
};
&lpspi4 {
pinctrl-0 = <&pinmux_lpspi4>;
pinctrl-names = "default";
};
&lpuart1 {
pinctrl-0 = <&pinmux_lpuart1>;
pinctrl-1 = <&pinmux_lpuart1_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart2 {
pinctrl-0 = <&pinmux_lpuart2>;
pinctrl-1 = <&pinmux_lpuart2_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart3 {
pinctrl-0 = <&pinmux_lpuart3>;
pinctrl-1 = <&pinmux_lpuart3_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart4 {
pinctrl-0 = <&pinmux_lpuart4>;
pinctrl-1 = <&pinmux_lpuart4_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart5 {
pinctrl-0 = <&pinmux_lpuart5>;
pinctrl-1 = <&pinmux_lpuart5_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart6 {
pinctrl-0 = <&pinmux_lpuart6>;
pinctrl-1 = <&pinmux_lpuart6_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart7 {
pinctrl-0 = <&pinmux_lpuart7>;
pinctrl-1 = <&pinmux_lpuart7_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart8 {
pinctrl-0 = <&pinmux_lpuart8>;
pinctrl-1 = <&pinmux_lpuart8_sleep>;
pinctrl-names = "default", "sleep";
};
&usdhc1 {
pinctrl-0 = <&pinmux_usdhc1>;
pinctrl-1 = <&pinmux_usdhc1_slow>;
pinctrl-2 = <&pinmux_usdhc1_med>;
pinctrl-3 = <&pinmux_usdhc1_fast>;
pinctrl-names = "default", "slow", "med", "fast";
};
&systick {
status = "okay";
};
``` | /content/code_sandbox/boards/pjrc/teensy4/teensy40.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,349 |
```unknown
/*
*
*/
#include "teensy40.dts"
/ {
model = "PJRC TEENSY 4.1 board";
chosen {
zephyr,flash-controller = &w25q64jvxgim;
zephyr,flash = &w25q64jvxgim;
};
};
/delete-node/ &w25q16jvuxim;
&flexspi {
status = "okay";
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
/* WINBOND flash memory*/
w25q64jvxgim: w25q64jvxgim@0 {
compatible = "nxp,imx-flexspi-nor";
size = <DT_SIZE_M(8 * 8)>;
reg = <0>;
spi-max-frequency = <DT_FREQ_M(133)>;
status = "okay";
jedec-id = [ef 70 17];
erase-block-size = <4096>;
write-block-size = <1>;
};
};
&lpspi3 {
status = "okay";
};
&usdhc1 {
status = "okay";
no-1-8-v;
pinctrl-0 = <&pinmux_usdhc1>;
pinctrl-1 = <&pinmux_usdhc1_slow>;
pinctrl-2 = <&pinmux_usdhc1_med>;
pinctrl-3 = <&pinmux_usdhc1_fast>;
pinctrl-names = "default", "slow", "med", "fast";
mmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
``` | /content/code_sandbox/boards/pjrc/teensy4/teensy41.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 373 |
```unknown
/*
*
* Note: File generated by gen_board_pinctrl.py
* from teensy4.mex
*/
#include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
&pinctrl {
/* Mode Straps configuration DP83825 */
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc_gpio_b1_04_enet_rx_data0>,
<&iomuxc_gpio_b1_06_enet_rx_en>,
<&iomuxc_gpio_b1_11_enet_rx_er>;
drive-strength = "r0-5";
bias-pull-down;
bias-pull-down-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_b1_05_enet_rx_data1>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "22k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_b1_07_enet_tx_data0>,
<&iomuxc_gpio_b1_08_enet_tx_data1>,
<&iomuxc_gpio_b1_09_enet_tx_en>,
<&iomuxc_gpio_b1_14_enet_mdc>,
<&iomuxc_gpio_b1_15_enet_mdio>,
<&iomuxc_gpio_b0_15_gpio2_io15>,
<&iomuxc_gpio_b0_14_gpio2_io14>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group3 {
pinmux = <&iomuxc_gpio_b1_10_enet_ref_clk>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* FLEXCAN1 TX, RX on Teensy-Pins 22/23 */
pinmux_flexcan1: pinmux_flexcan1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_08_flexcan1_tx>,
<&iomuxc_gpio_ad_b1_09_flexcan1_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* FLEXCAN2 TX, RX on Teensy-Pins 1/0 */
pinmux_flexcan2: pinmux_flexcan2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_02_flexcan2_tx>,
<&iomuxc_gpio_ad_b0_03_flexcan2_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* FLEXCAN3 TX, RX on Teensy-Pins 31/30 */
pinmux_flexcan3: pinmux_flexcan3 {
group0 {
pinmux = <&iomuxc_gpio_emc_36_flexcan3_tx>,
<&iomuxc_gpio_emc_37_flexcan3_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* LPI2C1 SCL, SDA on Teensy-Pins 19/18 */
pinmux_lpi2c1: pinmux_lpi2c1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_01_lpi2c1_sda>,
<&iomuxc_gpio_ad_b1_00_lpi2c1_scl>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* LPI2C3 SCL, SDA on Teensy-Pins 16/17 */
pinmux_lpi2c3: pinmux_lpi2c3 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_07_lpi2c3_scl>,
<&iomuxc_gpio_ad_b1_06_lpi2c3_sda>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* LPI2C4 SCL, SDA on Teensy-Pins 24/25 */
pinmux_lpi2c4: pinmux_lpi2c4 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_12_lpi2c4_scl>,
<&iomuxc_gpio_ad_b0_13_lpi2c4_sda>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* LPSPI3 MISO, MOSI, SCK, CS on Teensy-Pins 39/26/27/38 */
pinmux_lpspi3: pinmux_lpspi3 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_12_lpspi3_pcs0>,
<&iomuxc_gpio_ad_b0_00_lpspi3_sck>,
<&iomuxc_gpio_ad_b0_02_lpspi3_sdi>,
<&iomuxc_gpio_ad_b0_01_lpspi3_sdo>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* LPSPI4 MISO, MOSI, SCK, CS on Teensy-Pins 12/11/13/10 */
pinmux_lpspi4: pinmux_lpspi4 {
group0 {
pinmux = <&iomuxc_gpio_b0_00_lpspi4_pcs0>,
<&iomuxc_gpio_b0_03_lpspi4_sck>,
<&iomuxc_gpio_b0_01_lpspi4_sdi>,
<&iomuxc_gpio_b0_02_lpspi4_sdo>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* LPUART1 TX/RX on Teensy-Pins 24/25 */
pinmux_lpuart1: pinmux_lpuart1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_lpuart1_rx>,
<&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_gpio1_io13>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* LPUART2 TX/RX on Teensy-Pins 14/15 */
pinmux_lpuart2: pinmux_lpuart2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_03_lpuart2_rx>,
<&iomuxc_gpio_ad_b1_02_lpuart2_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart2_sleep: pinmux_lpuart2_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_03_gpio1_io19>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_02_lpuart2_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* LPUART3 TX/RX on Teensy-Pins 17/16 */
pinmux_lpuart3: pinmux_lpuart3 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_07_lpuart3_rx>,
<&iomuxc_gpio_ad_b1_06_lpuart3_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_07_gpio1_io23>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_06_lpuart3_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* LPUART4 TX/RX on Teensy-Pins 8/7 */
pinmux_lpuart4: pinmux_lpuart4 {
group0 {
pinmux = <&iomuxc_gpio_b1_01_lpuart4_rx>,
<&iomuxc_gpio_b1_00_lpuart4_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart4_sleep: pinmux_lpuart4_sleep {
group0 {
pinmux = <&iomuxc_gpio_b1_01_gpio2_io17>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_b1_00_lpuart4_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* LPUART5 TX/RX on Teensy-Pins 35/34 */
pinmux_lpuart5: pinmux_lpuart5 {
group0 {
pinmux = <&iomuxc_gpio_b1_13_lpuart5_rx>,
<&iomuxc_gpio_b1_12_lpuart5_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart5_sleep: pinmux_lpuart5_sleep {
group0 {
pinmux = <&iomuxc_gpio_b1_13_gpio2_io29>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_b1_12_lpuart5_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* LPUART6 TX/RX on Teensy-Pins 1/0 */
pinmux_lpuart6: pinmux_lpuart6 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_03_lpuart6_rx>,
<&iomuxc_gpio_ad_b0_02_lpuart6_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart6_sleep: pinmux_lpuart6_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_03_gpio1_io03>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_02_lpuart6_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* LPUART7 TX/RX on Teensy-Pins 29/28 */
pinmux_lpuart7: pinmux_lpuart7 {
group0 {
pinmux = <&iomuxc_gpio_emc_31_lpuart7_tx>,
<&iomuxc_gpio_emc_32_lpuart7_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart7_sleep: pinmux_lpuart7_sleep {
group0 {
pinmux = <&iomuxc_gpio_emc_31_gpio4_io31>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_emc_32_lpuart7_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* LPUART8 TX/RX on Teensy-Pins 20/21 */
pinmux_lpuart8: pinmux_lpuart8 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_11_lpuart8_rx>,
<&iomuxc_gpio_ad_b1_10_lpuart8_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart8_sleep: pinmux_lpuart8_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_11_gpio1_io27>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_10_lpuart8_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_usdhc1: pinmux_usdhc1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_emc_41_usdhc1_vselect>;
drive-strength = "r0-4";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
/* fast pinmux settings for USDHC (over 100 Mhz) */
pinmux_usdhc1_fast: pinmux_usdhc1_fast {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
/* medium pinmux settings for USDHC (under 100 Mhz) */
pinmux_usdhc1_med: pinmux_usdhc1_med {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
/* slow pinmux settings for USDHC (under 50 Mhz) */
pinmux_usdhc1_slow: pinmux_usdhc1_slow {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "50-mhz";
};
};
};
``` | /content/code_sandbox/boards/pjrc/teensy4/teensy4-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,867 |
```unknown
# drivers configuration options
menu "Device Drivers"
# zephyr-keep-sorted-start
source "drivers/adc/Kconfig"
source "drivers/audio/Kconfig"
source "drivers/auxdisplay/Kconfig"
source "drivers/bbram/Kconfig"
source "drivers/bluetooth/Kconfig"
source "drivers/cache/Kconfig"
source "drivers/can/Kconfig"
source "drivers/charger/Kconfig"
source "drivers/clock_control/Kconfig"
source "drivers/console/Kconfig"
source "drivers/coredump/Kconfig"
source "drivers/counter/Kconfig"
source "drivers/crypto/Kconfig"
source "drivers/dac/Kconfig"
source "drivers/dai/Kconfig"
source "drivers/disk/Kconfig"
source "drivers/display/Kconfig"
source "drivers/dma/Kconfig"
source "drivers/dp/Kconfig"
source "drivers/edac/Kconfig"
source "drivers/eeprom/Kconfig"
source "drivers/entropy/Kconfig"
source "drivers/espi/Kconfig"
source "drivers/ethernet/Kconfig"
source "drivers/firmware/Kconfig"
source "drivers/flash/Kconfig"
source "drivers/fpga/Kconfig"
source "drivers/fuel_gauge/Kconfig"
source "drivers/gnss/Kconfig"
source "drivers/gpio/Kconfig"
source "drivers/haptics/Kconfig"
source "drivers/hwinfo/Kconfig"
source "drivers/hwspinlock/Kconfig"
source "drivers/i2c/Kconfig"
source "drivers/i2s/Kconfig"
source "drivers/i3c/Kconfig"
source "drivers/ieee802154/Kconfig"
source "drivers/input/Kconfig"
source "drivers/interrupt_controller/Kconfig"
source "drivers/interrupt_controller/Kconfig.shared_irq"
source "drivers/ipm/Kconfig"
source "drivers/kscan/Kconfig"
source "drivers/led/Kconfig"
source "drivers/led_strip/Kconfig"
source "drivers/lora/Kconfig"
source "drivers/mbox/Kconfig"
source "drivers/mdio/Kconfig"
source "drivers/memc/Kconfig"
source "drivers/mfd/Kconfig"
source "drivers/mipi_dbi/Kconfig"
source "drivers/mipi_dsi/Kconfig"
source "drivers/misc/Kconfig"
source "drivers/mm/Kconfig"
source "drivers/modem/Kconfig"
source "drivers/mspi/Kconfig"
source "drivers/net/Kconfig"
source "drivers/pcie/Kconfig"
source "drivers/peci/Kconfig"
source "drivers/pinctrl/Kconfig"
source "drivers/pm_cpu_ops/Kconfig"
source "drivers/power_domain/Kconfig"
source "drivers/ps2/Kconfig"
source "drivers/ptp_clock/Kconfig"
source "drivers/pwm/Kconfig"
source "drivers/regulator/Kconfig"
source "drivers/reset/Kconfig"
source "drivers/retained_mem/Kconfig"
source "drivers/rtc/Kconfig"
source "drivers/sdhc/Kconfig"
source "drivers/sensor/Kconfig"
source "drivers/serial/Kconfig"
source "drivers/sip_svc/Kconfig"
source "drivers/smbus/Kconfig"
source "drivers/spi/Kconfig"
source "drivers/syscon/Kconfig"
source "drivers/timer/Kconfig"
source "drivers/usb/Kconfig"
source "drivers/usb_c/Kconfig"
source "drivers/video/Kconfig"
source "drivers/virtualization/Kconfig"
source "drivers/w1/Kconfig"
source "drivers/watchdog/Kconfig"
source "drivers/wifi/Kconfig"
source "drivers/xen/Kconfig"
# zephyr-keep-sorted-stop
source "drivers/tee/Kconfig"
endmenu
``` | /content/code_sandbox/drivers/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 743 |
```unknown
config MDIO_ATMEL_SAM
bool "Atmel SAM MDIO driver"
depends on ETH_SAM_GMAC
default y
help
Enable Atmel SAM MCU Family MDIO driver.
``` | /content/code_sandbox/drivers/mdio/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```restructuredtext
.. _teensy40:
PJRC TEENSY 4
#############
Overview
********
The Teensy is a complete USB-based microcontroller development system, in a
very small footprint, capable of implementing many types of projects. All
programming is done via the USB port.
.. figure:: teensy40.jpg
:align: center
:alt: TEENSY40
TEENSY40 (Credit: path_to_url
.. figure:: teensy41.jpg
:align: center
:alt: TEENSY41
TEENSY41 (Credit: path_to_url
Hardware
********
Teensy 4.0:
- MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory)
- 16 Mbit QSPI Flash
- LED
- USB 2.0 host connector
Teensy 4.1:
- MIMXRT1062DVJ6A MCU (600 MHz, 1024 KB on-chip memory)
- 64 Mbit QSPI Flash
- LED
- USB 2.0 host connector
- USB 2.0 OTG connector
- 10/100 Mbit/s Ethernet PHY
- TF socket for SD card
See the `Teensy 4.0 Website`_ for a complete hardware description.
Supported Features
==================
The teensy40 board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/pjrc/teensy4/teensy40_defconfig`
The teensy41 board configuration supports additional hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| SDHC | on-chip | disk access |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/pjrc/teensy4/teensy41_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
Pin mappings from Teensy to MIMXRT1062 SoC.
+-----+------------+-------------------------------------+
| Pin | Pad ID | Usage |
+=====+============+=====================================+
| 0 | AD_B0_03 | GPIO1_3 / UART6_RX / CAN2_RX |
+-----+------------+-------------------------------------+
| 1 | AD_B0_02 | GPIO1_2 / UART6_TX / CAN2_TX |
+-----+------------+-------------------------------------+
| 2 | EMC_04 | GPIO4_4 |
+-----+------------+-------------------------------------+
| 3 | EMC_05 | GPIO4_5 |
+-----+------------+-------------------------------------+
| 4 | EMC_06 | GPIO4_6 |
+-----+------------+-------------------------------------+
| 5 | EMC_08 | GPIO4_8 |
+-----+------------+-------------------------------------+
| 6 | B0_10 | GPIO2_10 |
+-----+------------+-------------------------------------+
| 7 | B1_01 | GPIO2_17 / UART4_RX |
+-----+------------+-------------------------------------+
| 8 | B1_00 | GPIO2_16 / UART4_TX |
+-----+------------+-------------------------------------+
| 9 | B0_11 | GPIO2_11 |
+-----+------------+-------------------------------------+
| 10 | B0_00 | GPIO2_0 |
+-----+------------+-------------------------------------+
| 11 | B0_02 | GPIO2_2 |
+-----+------------+-------------------------------------+
| 12 | B0_01 | GPIO2_1 |
+-----+------------+-------------------------------------+
| 13 | B0_03 | GPIO2_3 / LED |
+-----+------------+-------------------------------------+
| 14 | AD_B1_02 | GPIO1_18 / UART2_TX |
+-----+------------+-------------------------------------+
| 15 | AD_B1_03 | GPIO1_19 / UART2_RX |
+-----+------------+-------------------------------------+
| 16 | AD_B1_07 | GPIO1_23 / UART3_RX / I2C3_SCL |
+-----+------------+-------------------------------------+
| 17 | AD_B1_06 | GPIO1_22 / UART3_TX / I2C3_SDA |
+-----+------------+-------------------------------------+
| 18 | AD_B1_01 | GPIO1_17 / I2C1_SDA |
+-----+------------+-------------------------------------+
| 19 | AD_B1_00 | GPIO1_16 / I2C1_SCL |
+-----+------------+-------------------------------------+
| 20 | AD_B1_10 | GPIO1_26 / UART8_TX |
+-----+------------+-------------------------------------+
| 21 | AD_B1_11 | GPIO1_27 / UART8_RX |
+-----+------------+-------------------------------------+
| 22 | AD_B1_08 | GPIO1_24 / CAN1_TX |
+-----+------------+-------------------------------------+
| 23 | AD_B1_09 | GPIO1_25 / CAN1_RX |
+-----+------------+-------------------------------------+
| 24 | AD_B0_12 | GPIO1_12 / UART1_TX / I2C4_SCL |
+-----+------------+-------------------------------------+
| 25 | AD_B0_13 | GPIO1_13 / UART1_RX / I2C4_SDA |
+-----+------------+-------------------------------------+
| 26 | AD_B1_14 | GPIO1_30 |
+-----+------------+-------------------------------------+
| 27 | AD_B1_15 | GPIO1_31 |
+-----+------------+-------------------------------------+
| 28 | EMC_32 | GPIO3_18 / UART7_RX |
+-----+------------+-------------------------------------+
| 29 | EMC_31 | GPIO4_31 / UART7_TX |
+-----+------------+-------------------------------------+
| 30 | EMC_37 | GPIO3_23 / CAN3_RX |
+-----+------------+-------------------------------------+
| 31 | EMC_36 | GPIO3_22 / CAN3_TX |
+-----+------------+-------------------------------------+
| 32 | B0_12 | GPIO2_12 |
+-----+------------+-------------------------------------+
| 33 | EMC_07 | GPIO4_7 |
+-----+------------+-------------------------------------+
Only Teensy 4.0:
+-----+------------+-------------------------------------+
| 34 | SD_B0_03 | GPIO3_15 |
+-----+------------+-------------------------------------+
| 35 | SD_B0_02 | GPIO3_14 |
+-----+------------+-------------------------------------+
| 36 | SD_B0_01 | GPIO3_13 |
+-----+------------+-------------------------------------+
| 37 | SD_B0_00 | GPIO3_12 |
+-----+------------+-------------------------------------+
| 38 | SD_B0_05 | GPIO3_17 |
+-----+------------+-------------------------------------+
| 39 | SD_B0_04 | GPIO3_16 |
+-----+------------+-------------------------------------+
Only Teensy 4.1:
+-----+------------+-------------------------------------+
| 34 | B1_13 | GPIO2_29 / UART5_RX |
+-----+------------+-------------------------------------+
| 35 | B1_12 | GPIO2_28 / UART5_TX |
+-----+------------+-------------------------------------+
| 36 | B1_02 | GPIO2_18 |
+-----+------------+-------------------------------------+
| 37 | B1_03 | GPIO2_19 |
+-----+------------+-------------------------------------+
| 38 | AD_B1_12 | GPIO1_28 |
+-----+------------+-------------------------------------+
| 39 | AD_B1_13 | GPIO1_29 |
+-----+------------+-------------------------------------+
| 40 | AD_B1_04 | GPIO1_20 |
+-----+------------+-------------------------------------+
| 41 | AD_B1_05 | GPIO1_21 |
+-----+------------+-------------------------------------+
Programming and Debugging
*************************
Flashing
========
Build applications as usual (see :ref:`build_an_application` for more details).
Flash hex-file with the documented tools:
.. _Teensy flash tools:
path_to_url
Debugging
=========
Console output is mapped to teensy pins 0 (RX1) and 1 (TX1). Connect a usb-to-serial adapter
to use this serial console. Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
References
**********
.. _Teensy 4.0 Website:
path_to_url
.. _Teensy Schematics:
path_to_url
.. _i.MX RT1060 Website:
path_to_url
.. _i.MX RT1060 Datasheet:
path_to_url
.. _i.MX RT1060 Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/pjrc/teensy4/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,289 |
```unknown
config MDIO_ADIN2111
bool "ADIN2111 MDIO driver"
default y
depends on DT_HAS_ADI_ADIN2111_MDIO_ENABLED
depends on ETH_ADIN2111
help
Enable ADIN2111 MDIO driver.
``` | /content/code_sandbox/drivers/mdio/Kconfig.adin2111 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```c
/*
*
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_adin2111, CONFIG_MDIO_LOG_LEVEL);
#define DT_DRV_COMPAT adi_adin2111_mdio
#include <stdint.h>
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/ethernet/eth_adin2111.h>
/* MDIO ready check retry delay */
#define ADIN2111_MDIO_READY_AWAIT_DELAY_POLL_US 5U
/* Number of retries for MDIO ready check */
#define ADIN2111_MDIO_READY_AWAIT_RETRY_COUNT 10U
/* MDIO Access Register 1 */
#define ADIN2111_MDIOACC0 0x20U
/* MDIO Access Register 2 */
#define ADIN2111_MDIOACC1 0x21U
/* MDIO MDIOACC Transaction Done */
#define ADIN211_MDIOACC_MDIO_TRDONE BIT(31)
struct mdio_adin2111_config {
const struct device *adin;
};
static int mdio_adin2111_wait_ready(const struct device *dev, uint16_t reg,
uint32_t *out)
{
const struct mdio_adin2111_config *const cfg = dev->config;
uint32_t count;
int ret;
for (count = 0U; count < ADIN2111_MDIO_READY_AWAIT_RETRY_COUNT; ++count) {
ret = eth_adin2111_reg_read(cfg->adin, reg, out);
if (ret >= 0) {
if ((*out) & ADIN211_MDIOACC_MDIO_TRDONE) {
break;
}
ret = -ETIMEDOUT;
}
k_sleep(K_USEC(ADIN2111_MDIO_READY_AWAIT_DELAY_POLL_US));
}
return ret;
}
static int mdio_adin2111_read_c45(const struct device *dev, uint8_t prtad,
uint8_t devad, uint16_t regad,
uint16_t *data)
{
const struct mdio_adin2111_config *const cfg = dev->config;
uint32_t rdy;
uint32_t cmd;
int ret;
/* address op */
cmd = (prtad & 0x1FU) << 21;
cmd |= (devad & 0x1FU) << 16;
cmd |= regad;
ret = eth_adin2111_reg_write(cfg->adin, ADIN2111_MDIOACC0, cmd);
if (ret < 0) {
return ret;
}
/* read op */
cmd = (cmd & ~UINT16_MAX) | (0x3U << 26);
ret = eth_adin2111_reg_write(cfg->adin, ADIN2111_MDIOACC1, cmd);
if (ret < 0) {
return ret;
}
ret = mdio_adin2111_wait_ready(dev, ADIN2111_MDIOACC1, &rdy);
if (ret < 0) {
return ret;
}
/* read out */
ret = eth_adin2111_reg_read(cfg->adin, ADIN2111_MDIOACC1, &cmd);
*data = cmd & UINT16_MAX;
return ret;
}
static int mdio_adin2111_write_c45(const struct device *dev, uint8_t prtad,
uint8_t devad, uint16_t regad,
uint16_t data)
{
const struct mdio_adin2111_config *const cfg = dev->config;
uint32_t rdy;
uint32_t cmd;
int ret;
/* address op */
cmd = (prtad & 0x1FU) << 21;
cmd |= (devad & 0x1FU) << 16;
cmd |= regad;
ret = eth_adin2111_reg_write(cfg->adin, ADIN2111_MDIOACC0, cmd);
if (ret < 0) {
return ret;
}
/* write op */
cmd |= BIT(26);
cmd = (cmd & ~UINT16_MAX) | data;
ret = eth_adin2111_reg_write(cfg->adin, ADIN2111_MDIOACC1, cmd);
if (ret < 0) {
return ret;
}
ret = mdio_adin2111_wait_ready(dev, ADIN2111_MDIOACC1, &rdy);
return ret;
}
static int mdio_adin2111_read(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t *data)
{
const struct mdio_adin2111_config *const cfg = dev->config;
uint32_t read;
uint32_t cmd;
int ret;
cmd = BIT(28);
cmd |= 0x3U << 26;
cmd |= (prtad & 0x1FU) << 21;
cmd |= (regad & 0x1FU) << 16;
ret = eth_adin2111_reg_write(cfg->adin, ADIN2111_MDIOACC0, cmd);
if (ret >= 0) {
ret = mdio_adin2111_wait_ready(dev, ADIN2111_MDIOACC0, &read);
*data = read & UINT16_MAX;
}
return ret;
}
static int mdio_adin2111_write(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t data)
{
const struct mdio_adin2111_config *const cfg = dev->config;
uint32_t cmd;
uint32_t rdy;
int ret;
cmd = BIT(28);
cmd |= BIT(26);
cmd |= (prtad & 0x1FU) << 21;
cmd |= (regad & 0x1FU) << 16;
cmd |= data;
ret = eth_adin2111_reg_write(cfg->adin, ADIN2111_MDIOACC0, cmd);
if (ret >= 0) {
ret = mdio_adin2111_wait_ready(dev, ADIN2111_MDIOACC0, &rdy);
}
return ret;
}
static void mdio_adin2111_bus_enable(const struct device *dev)
{
const struct mdio_adin2111_config *const cfg = dev->config;
eth_adin2111_lock(cfg->adin, K_FOREVER);
}
static void mdio_adin2111_bus_disable(const struct device *dev)
{
const struct mdio_adin2111_config *const cfg = dev->config;
eth_adin2111_unlock(cfg->adin);
}
static const struct mdio_driver_api mdio_adin2111_api = {
.read = mdio_adin2111_read,
.write = mdio_adin2111_write,
.read_c45 = mdio_adin2111_read_c45,
.write_c45 = mdio_adin2111_write_c45,
.bus_enable = mdio_adin2111_bus_enable,
.bus_disable = mdio_adin2111_bus_disable
};
#define ADIN2111_MDIO_INIT(n) \
static const struct mdio_adin2111_config mdio_adin2111_config_##n = { \
.adin = DEVICE_DT_GET(DT_INST_BUS(n)), \
}; \
DEVICE_DT_INST_DEFINE(n, NULL, NULL, \
NULL, &mdio_adin2111_config_##n, \
POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \
&mdio_adin2111_api);
DT_INST_FOREACH_STATUS_OKAY(ADIN2111_MDIO_INIT)
``` | /content/code_sandbox/drivers/mdio/mdio_adin2111.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,635 |
```unknown
config MDIO_LITEX_LITEETH
bool "Litex LiteEth MDIO controller driver"
default y
depends on DT_HAS_LITEX_LITEETH_MDIO_ENABLED
help
Enable MDIO support from Litex LiteEth controller.
``` | /content/code_sandbox/drivers/mdio/Kconfig.litex | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_mdio
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <esp_mac.h>
#include <hal/emac_hal.h>
#include <hal/emac_ll.h>
LOG_MODULE_REGISTER(mdio_esp32, CONFIG_MDIO_LOG_LEVEL);
#define PHY_OPERATION_TIMEOUT_US 1000
struct mdio_esp32_dev_data {
struct k_sem sem;
emac_hal_context_t hal;
};
struct mdio_esp32_dev_config {
const struct pinctrl_dev_config *pcfg;
};
static int mdio_transfer(const struct device *dev, uint8_t prtad, uint8_t regad,
bool write, uint16_t data_in, uint16_t *data_out)
{
struct mdio_esp32_dev_data *const dev_data = dev->data;
k_sem_take(&dev_data->sem, K_FOREVER);
if (emac_ll_is_mii_busy(dev_data->hal.mac_regs)) {
LOG_ERR("phy busy");
k_sem_give(&dev_data->sem);
return -EBUSY;
}
if (write) {
emac_ll_set_phy_data(dev_data->hal.mac_regs, data_in);
}
emac_hal_set_phy_cmd(&dev_data->hal, prtad, regad, write);
/* Poll until operation complete */
bool success = false;
for (uint32_t t_us = 0; t_us < PHY_OPERATION_TIMEOUT_US; t_us += 100) {
k_sleep(K_USEC(100));
if (!emac_ll_is_mii_busy(dev_data->hal.mac_regs)) {
success = true;
break;
}
}
if (!success) {
LOG_ERR("phy timeout");
k_sem_give(&dev_data->sem);
return -ETIMEDOUT;
}
if (!write && data_out != NULL) {
*data_out = emac_ll_get_phy_data(dev_data->hal.mac_regs);
}
k_sem_give(&dev_data->sem);
return 0;
}
static int mdio_esp32_read(const struct device *dev, uint8_t prtad, uint8_t regad,
uint16_t *data)
{
return mdio_transfer(dev, prtad, regad, false, 0, data);
}
static int mdio_esp32_write(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t data)
{
return mdio_transfer(dev, prtad, regad, true, data, NULL);
}
static int mdio_esp32_initialize(const struct device *dev)
{
const struct mdio_esp32_dev_config *const cfg = dev->config;
struct mdio_esp32_dev_data *const dev_data = dev->data;
int res;
k_sem_init(&dev_data->sem, 1, 1);
res = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (res != 0) {
goto err;
}
const struct device *clock_dev =
DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(mdio)));
clock_control_subsys_t clock_subsys =
(clock_control_subsys_t)DT_CLOCKS_CELL(DT_NODELABEL(mdio), offset);
/* clock is shared, so do not bail out if already enabled */
res = clock_control_on(clock_dev, clock_subsys);
if (res < 0 && res != -EALREADY) {
goto err;
}
/* Only the mac registers are required for MDIO */
dev_data->hal.mac_regs = &EMAC_MAC;
/* Init MDIO clock */
emac_hal_set_csr_clock_range(&dev_data->hal, esp_clk_apb_freq());
return 0;
err:
return res;
}
static const struct mdio_driver_api mdio_esp32_driver_api = {
.read = mdio_esp32_read,
.write = mdio_esp32_write,
};
#define MDIO_ESP32_CONFIG(n) \
static const struct mdio_esp32_dev_config mdio_esp32_dev_config_##n = { \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
};
#define MDIO_ESP32_DEVICE(n) \
PINCTRL_DT_INST_DEFINE(n); \
MDIO_ESP32_CONFIG(n); \
static struct mdio_esp32_dev_data mdio_esp32_dev_data##n; \
DEVICE_DT_INST_DEFINE(n, \
&mdio_esp32_initialize, \
NULL, \
&mdio_esp32_dev_data##n, \
&mdio_esp32_dev_config_##n, POST_KERNEL, \
CONFIG_MDIO_INIT_PRIORITY, \
&mdio_esp32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MDIO_ESP32_DEVICE)
``` | /content/code_sandbox/drivers/mdio/mdio_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,082 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_enet_mdio
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/net/mdio.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/ethernet/eth_nxp_enet.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys_clock.h>
struct nxp_enet_mdio_config {
const struct pinctrl_dev_config *pincfg;
const struct device *module_dev;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
uint32_t mdc_freq;
bool disable_preamble;
};
struct nxp_enet_mdio_data {
ENET_Type *base;
struct k_mutex mdio_mutex;
struct k_sem mdio_sem;
bool interrupt_up;
};
/*
* This function is used for both read and write operations
* in order to wait for the completion of an MDIO transaction.
* It returns -ETIMEDOUT if timeout occurs as specified in DT,
* otherwise returns 0 if EIR MII bit is set indicting completed
* operation, otherwise -EIO.
*/
static int nxp_enet_mdio_wait_xfer(const struct device *dev)
{
struct nxp_enet_mdio_data *data = dev->data;
ENET_Type *base = data->base;
/* This function will not make sense from IRQ context */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if (data->interrupt_up) {
/* Enable the interrupt */
base->EIMR |= ENET_EIMR_MII_MASK;
} else {
/* If the interrupt is not available to use yet, just busy wait */
k_busy_wait(CONFIG_MDIO_NXP_ENET_TIMEOUT);
k_sem_give(&data->mdio_sem);
}
/* Wait for the MDIO transaction to finish or time out */
k_sem_take(&data->mdio_sem, K_USEC(CONFIG_MDIO_NXP_ENET_TIMEOUT));
return 0;
}
/* MDIO Read API implementation */
static int nxp_enet_mdio_read(const struct device *dev,
uint8_t prtad, uint8_t regad, uint16_t *read_data)
{
struct nxp_enet_mdio_data *data = dev->data;
int ret;
/* Only one MDIO bus operation attempt at a time */
(void)k_mutex_lock(&data->mdio_mutex, K_FOREVER);
/*
* Clear the bit (W1C) that indicates MDIO transfer is ready to
* prepare to wait for it to be set once this read is done
*/
data->base->EIR |= ENET_EIR_MII_MASK;
/*
* Write MDIO frame to MII management register which will
* send the read command and data out to the MDIO bus as this frame:
* ST = start, 1 means start
* OP = operation, 2 means read
* PA = PHY/Port address
* RA = Register/Device Address
* TA = Turnaround, must be 2 to be valid
* data = data to be written to the PHY register
*/
data->base->MMFR = ENET_MMFR_ST(0x1U) |
ENET_MMFR_OP(MDIO_OP_C22_READ) |
ENET_MMFR_PA(prtad) |
ENET_MMFR_RA(regad) |
ENET_MMFR_TA(0x2U);
ret = nxp_enet_mdio_wait_xfer(dev);
if (ret) {
(void)k_mutex_unlock(&data->mdio_mutex);
return ret;
}
/* The data is received in the same register that we wrote the command to */
*read_data = (data->base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT;
/* Clear the same bit as before because the event has been handled */
data->base->EIR |= ENET_EIR_MII_MASK;
/* This MDIO interaction is finished */
(void)k_mutex_unlock(&data->mdio_mutex);
return ret;
}
/* MDIO Write API implementation */
static int nxp_enet_mdio_write(const struct device *dev,
uint8_t prtad, uint8_t regad, uint16_t write_data)
{
struct nxp_enet_mdio_data *data = dev->data;
int ret;
/* Only one MDIO bus operation attempt at a time */
(void)k_mutex_lock(&data->mdio_mutex, K_FOREVER);
/*
* Clear the bit (W1C) that indicates MDIO transfer is ready to
* prepare to wait for it to be set once this write is done
*/
data->base->EIR |= ENET_EIR_MII_MASK;
/*
* Write MDIO frame to MII management register which will
* send the write command and data out to the MDIO bus as this frame:
* ST = start, 1 means start
* OP = operation, 1 means write
* PA = PHY/Port address
* RA = Register/Device Address
* TA = Turnaround, must be 2 to be valid
* data = data to be written to the PHY register
*/
data->base->MMFR = ENET_MMFR_ST(0x1U) |
ENET_MMFR_OP(MDIO_OP_C22_WRITE) |
ENET_MMFR_PA(prtad) |
ENET_MMFR_RA(regad) |
ENET_MMFR_TA(0x2U) |
write_data;
ret = nxp_enet_mdio_wait_xfer(dev);
if (ret) {
(void)k_mutex_unlock(&data->mdio_mutex);
return ret;
}
/* Clear the same bit as before because the event has been handled */
data->base->EIR |= ENET_EIR_MII_MASK;
/* This MDIO interaction is finished */
(void)k_mutex_unlock(&data->mdio_mutex);
return ret;
}
static const struct mdio_driver_api nxp_enet_mdio_api = {
.read = nxp_enet_mdio_read,
.write = nxp_enet_mdio_write,
};
static void nxp_enet_mdio_isr_cb(const struct device *dev)
{
struct nxp_enet_mdio_data *data = dev->data;
data->base->EIR |= ENET_EIR_MII_MASK;
/* Signal that operation finished */
k_sem_give(&data->mdio_sem);
/* Disable the interrupt */
data->base->EIMR &= ~ENET_EIMR_MII_MASK;
}
static void nxp_enet_mdio_post_module_reset_init(const struct device *dev)
{
const struct nxp_enet_mdio_config *config = dev->config;
struct nxp_enet_mdio_data *data = dev->data;
uint32_t enet_module_clock_rate;
/* Set up MSCR register */
(void) clock_control_get_rate(config->clock_dev, config->clock_subsys,
&enet_module_clock_rate);
uint32_t mii_speed = (enet_module_clock_rate + 2 * config->mdc_freq - 1) /
(2 * config->mdc_freq) - 1;
uint32_t holdtime = (10 + NSEC_PER_SEC / enet_module_clock_rate - 1) /
(NSEC_PER_SEC / enet_module_clock_rate) - 1;
uint32_t mscr = ENET_MSCR_MII_SPEED(mii_speed) | ENET_MSCR_HOLDTIME(holdtime) |
(config->disable_preamble ? ENET_MSCR_DIS_PRE_MASK : 0);
data->base->MSCR = mscr;
}
void nxp_enet_mdio_callback(const struct device *dev,
enum nxp_enet_callback_reason event, void *cb_data)
{
struct nxp_enet_mdio_data *data = dev->data;
ARG_UNUSED(cb_data);
switch (event) {
case NXP_ENET_MODULE_RESET:
nxp_enet_mdio_post_module_reset_init(dev);
break;
case NXP_ENET_INTERRUPT:
nxp_enet_mdio_isr_cb(dev);
break;
case NXP_ENET_INTERRUPT_ENABLED:
data->interrupt_up = true;
break;
default:
break;
}
}
static int nxp_enet_mdio_init(const struct device *dev)
{
const struct nxp_enet_mdio_config *config = dev->config;
struct nxp_enet_mdio_data *data = dev->data;
int ret = 0;
data->base = (ENET_Type *)DEVICE_MMIO_GET(config->module_dev);
ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (ret) {
return ret;
}
ret = k_mutex_init(&data->mdio_mutex);
if (ret) {
return ret;
}
ret = k_sem_init(&data->mdio_sem, 0, 1);
if (ret) {
return ret;
}
/* All operations done after module reset should be done during device init too */
nxp_enet_mdio_post_module_reset_init(dev);
return ret;
}
#define NXP_ENET_MDIO_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
\
static const struct nxp_enet_mdio_config nxp_enet_mdio_cfg_##inst = { \
.module_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(inst))), \
.clock_subsys = (void *) DT_CLOCKS_CELL_BY_IDX( \
DT_INST_PARENT(inst), 0, name), \
.disable_preamble = DT_INST_PROP(inst, suppress_preamble), \
.mdc_freq = DT_INST_PROP(inst, clock_frequency), \
}; \
\
static struct nxp_enet_mdio_data nxp_enet_mdio_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, &nxp_enet_mdio_init, NULL, \
&nxp_enet_mdio_data_##inst, &nxp_enet_mdio_cfg_##inst, \
POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \
&nxp_enet_mdio_api);
DT_INST_FOREACH_STATUS_OKAY(NXP_ENET_MDIO_INIT)
``` | /content/code_sandbox/drivers/mdio/mdio_nxp_enet.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,299 |
```unknown
config MDIO_ESP32
bool "ESP32 MDIO driver"
default y
depends on SOC_SERIES_ESP32
depends on DT_HAS_ESPRESSIF_ESP32_MDIO_ENABLED
help
Enable ESP32 MCU Family MDIO driver.
``` | /content/code_sandbox/drivers/mdio/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
config MDIO_GPIO
bool "GPIO bitbang MDIO controller driver"
default y
depends on DT_HAS_ZEPHYR_MDIO_GPIO_ENABLED
help
Enable software driven (bit banging) MDIO support using GPIO pins
``` | /content/code_sandbox/drivers/mdio/Kconfig.gpio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config MDIO_NXP_S32_NETC
bool "NXP S32 NETC External MDIO driver"
default y
depends on DT_HAS_NXP_S32_NETC_EMDIO_ENABLED
depends on ETH_NXP_S32_NETC && DT_HAS_NXP_S32_NETC_PSI_ENABLED
select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
help
Enable NETC External MDIO Controller driver for NXP S32 SoCs.
``` | /content/code_sandbox/drivers/mdio/Kconfig.nxp_s32_netc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 99 |
```unknown
config MDIO_ST_STM32_HAL
bool "STM32 MDIO controller driver"
default y
depends on ETH_STM32_HAL_API_V2
depends on DT_HAS_ST_STM32_MDIO_ENABLED
help
Enable STM32 MDIO support.
``` | /content/code_sandbox/drivers/mdio/Kconfig.stm32_hal | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_mdio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/net/mdio.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_sam, CONFIG_MDIO_LOG_LEVEL);
/* GMAC */
#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM0
#define GMAC_MAN MAN.reg
#define GMAC_NSR NSR.reg
#define GMAC_NCR NCR.reg
#endif
struct mdio_sam_dev_data {
struct k_sem sem;
};
struct mdio_sam_dev_config {
Gmac * const regs;
const struct pinctrl_dev_config *pcfg;
#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM
const struct atmel_sam_pmc_config clock_cfg;
#endif
};
static int mdio_transfer(const struct device *dev, uint8_t prtad, uint8_t regad,
enum mdio_opcode op, bool c45, uint16_t data_in,
uint16_t *data_out)
{
const struct mdio_sam_dev_config *const cfg = dev->config;
struct mdio_sam_dev_data *const data = dev->data;
int timeout = 50;
k_sem_take(&data->sem, K_FOREVER);
/* Write mdio transaction */
cfg->regs->GMAC_MAN = (c45 ? 0U : GMAC_MAN_CLTTO)
| GMAC_MAN_OP(op)
| GMAC_MAN_WTN(0x02)
| GMAC_MAN_PHYA(prtad)
| GMAC_MAN_REGA(regad)
| GMAC_MAN_DATA(data_in);
/* Wait until done */
while (!(cfg->regs->GMAC_NSR & GMAC_NSR_IDLE)) {
if (timeout-- == 0U) {
LOG_ERR("transfer timedout %s", dev->name);
k_sem_give(&data->sem);
return -ETIMEDOUT;
}
k_sleep(K_MSEC(5));
}
if (data_out) {
*data_out = cfg->regs->GMAC_MAN & GMAC_MAN_DATA_Msk;
}
k_sem_give(&data->sem);
return 0;
}
static int mdio_sam_read(const struct device *dev, uint8_t prtad, uint8_t regad,
uint16_t *data)
{
return mdio_transfer(dev, prtad, regad, MDIO_OP_C22_READ, false,
0, data);
}
static int mdio_sam_write(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t data)
{
return mdio_transfer(dev, prtad, regad, MDIO_OP_C22_WRITE, false,
data, NULL);
}
static int mdio_sam_read_c45(const struct device *dev, uint8_t prtad,
uint8_t devad, uint16_t regad, uint16_t *data)
{
int err;
err = mdio_transfer(dev, prtad, devad, MDIO_OP_C45_ADDRESS, true,
regad, NULL);
if (!err) {
err = mdio_transfer(dev, prtad, devad, MDIO_OP_C45_READ, true,
0, data);
}
return err;
}
static int mdio_sam_write_c45(const struct device *dev, uint8_t prtad,
uint8_t devad, uint16_t regad, uint16_t data)
{
int err;
err = mdio_transfer(dev, prtad, devad, MDIO_OP_C45_ADDRESS, true,
regad, NULL);
if (!err) {
err = mdio_transfer(dev, prtad, devad, MDIO_OP_C45_WRITE, true,
data, NULL);
}
return err;
}
static void mdio_sam_bus_enable(const struct device *dev)
{
const struct mdio_sam_dev_config *const cfg = dev->config;
cfg->regs->GMAC_NCR |= GMAC_NCR_MPE;
}
static void mdio_sam_bus_disable(const struct device *dev)
{
const struct mdio_sam_dev_config *const cfg = dev->config;
cfg->regs->GMAC_NCR &= ~GMAC_NCR_MPE;
}
static int mdio_sam_initialize(const struct device *dev)
{
const struct mdio_sam_dev_config *const cfg = dev->config;
struct mdio_sam_dev_data *const data = dev->data;
int retval;
k_sem_init(&data->sem, 1, 1);
#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM
/* Enable GMAC module's clock */
(void) clock_control_on(SAM_DT_PMC_CONTROLLER, (clock_control_subsys_t) &cfg->clock_cfg);
#else
/* Enable MCLK clock on GMAC */
MCLK->AHBMASK.reg |= MCLK_AHBMASK_GMAC;
*MCLK_GMAC |= MCLK_GMAC_MASK;
#endif
retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
return retval;
}
static const struct mdio_driver_api mdio_sam_driver_api = {
.read = mdio_sam_read,
.write = mdio_sam_write,
.read_c45 = mdio_sam_read_c45,
.write_c45 = mdio_sam_write_c45,
.bus_enable = mdio_sam_bus_enable,
.bus_disable = mdio_sam_bus_disable,
};
#define MDIO_SAM_CLOCK(n) \
COND_CODE_1(CONFIG_SOC_FAMILY_ATMEL_SAM, \
(.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n),), () \
)
#define MDIO_SAM_CONFIG(n) \
static const struct mdio_sam_dev_config mdio_sam_dev_config_##n = { \
.regs = (Gmac *)DT_INST_REG_ADDR(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
MDIO_SAM_CLOCK(n) \
};
#define MDIO_SAM_DEVICE(n) \
PINCTRL_DT_INST_DEFINE(n); \
MDIO_SAM_CONFIG(n); \
static struct mdio_sam_dev_data mdio_sam_dev_data##n; \
DEVICE_DT_INST_DEFINE(n, \
&mdio_sam_initialize, \
NULL, \
&mdio_sam_dev_data##n, \
&mdio_sam_dev_config_##n, POST_KERNEL, \
CONFIG_MDIO_INIT_PRIORITY, \
&mdio_sam_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MDIO_SAM_DEVICE)
``` | /content/code_sandbox/drivers/mdio/mdio_sam.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,493 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32_gmac_mdio
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(nxp_s32_mdio, CONFIG_MDIO_LOG_LEVEL);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <Gmac_Ip.h>
#define GMAC_MDIO_REG_OFFSET (0x200)
#define GMAC_STATUS_TO_ERRNO(x) \
((x) == GMAC_STATUS_SUCCESS ? 0 : ((x) == GMAC_STATUS_TIMEOUT ? -ETIMEDOUT : -EIO))
struct mdio_nxp_s32_config {
uint8_t instance;
bool suppress_preamble;
const struct pinctrl_dev_config *pincfg;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
};
struct mdio_nxp_s32_data {
struct k_mutex bus_mutex;
uint32_t clock_freq;
};
static int mdio_nxp_s32_read_c45(const struct device *dev, uint8_t prtad, uint8_t devad,
uint16_t regad, uint16_t *regval)
{
const struct mdio_nxp_s32_config *const cfg = dev->config;
struct mdio_nxp_s32_data *data = dev->data;
Gmac_Ip_StatusType status;
k_mutex_lock(&data->bus_mutex, K_FOREVER);
/* Configure MDIO controller before initiating a transmission */
Gmac_Ip_EnableMDIO(cfg->instance, cfg->suppress_preamble, data->clock_freq);
status = Gmac_Ip_MDIOReadMMD(cfg->instance, prtad, devad, regad, regval,
CONFIG_MDIO_NXP_S32_TIMEOUT);
k_mutex_unlock(&data->bus_mutex);
return GMAC_STATUS_TO_ERRNO(status);
}
static int mdio_nxp_s32_write_c45(const struct device *dev, uint8_t prtad, uint8_t devad,
uint16_t regad, uint16_t regval)
{
const struct mdio_nxp_s32_config *const cfg = dev->config;
struct mdio_nxp_s32_data *data = dev->data;
Gmac_Ip_StatusType status;
k_mutex_lock(&data->bus_mutex, K_FOREVER);
/* Configure MDIO controller before initiating a transmission */
Gmac_Ip_EnableMDIO(cfg->instance, cfg->suppress_preamble, data->clock_freq);
status = Gmac_Ip_MDIOWriteMMD(cfg->instance, prtad, devad, regad, regval,
CONFIG_MDIO_NXP_S32_TIMEOUT);
k_mutex_unlock(&data->bus_mutex);
return GMAC_STATUS_TO_ERRNO(status);
}
static int mdio_nxp_s32_read_c22(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t *regval)
{
const struct mdio_nxp_s32_config *const cfg = dev->config;
struct mdio_nxp_s32_data *data = dev->data;
Gmac_Ip_StatusType status;
k_mutex_lock(&data->bus_mutex, K_FOREVER);
/* Configure MDIO controller before initiating a transmission */
Gmac_Ip_EnableMDIO(cfg->instance, cfg->suppress_preamble, data->clock_freq);
status = Gmac_Ip_MDIORead(cfg->instance, prtad, regad, regval,
CONFIG_MDIO_NXP_S32_TIMEOUT);
k_mutex_unlock(&data->bus_mutex);
return GMAC_STATUS_TO_ERRNO(status);
}
static int mdio_nxp_s32_write_c22(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t regval)
{
const struct mdio_nxp_s32_config *const cfg = dev->config;
struct mdio_nxp_s32_data *data = dev->data;
Gmac_Ip_StatusType status;
k_mutex_lock(&data->bus_mutex, K_FOREVER);
/* Configure MDIO controller before initiating a transmission */
Gmac_Ip_EnableMDIO(cfg->instance, cfg->suppress_preamble, data->clock_freq);
status = Gmac_Ip_MDIOWrite(cfg->instance, prtad, regad, regval,
CONFIG_MDIO_NXP_S32_TIMEOUT);
k_mutex_unlock(&data->bus_mutex);
return GMAC_STATUS_TO_ERRNO(status);
}
static int mdio_nxp_s32_init(const struct device *dev)
{
const struct mdio_nxp_s32_config *const cfg = dev->config;
struct mdio_nxp_s32_data *data = dev->data;
int err;
if (!device_is_ready(cfg->clock_dev)) {
LOG_ERR("Clock control device not ready");
return -ENODEV;
}
if (clock_control_get_rate(cfg->clock_dev, cfg->clock_subsys, &data->clock_freq)) {
LOG_ERR("Failed to get clock frequency");
return -EIO;
}
err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
if (err != 0) {
return err;
}
k_mutex_init(&data->bus_mutex);
return 0;
}
static const struct mdio_driver_api mdio_nxp_s32_driver_api = {
.read = mdio_nxp_s32_read_c22,
.write = mdio_nxp_s32_write_c22,
.read_c45 = mdio_nxp_s32_read_c45,
.write_c45 = mdio_nxp_s32_write_c45,
};
#define MDIO_NXP_S32_HW_INSTANCE_CHECK(i, n) \
(((DT_INST_REG_ADDR(n) - GMAC_MDIO_REG_OFFSET) == IP_GMAC_##i##_BASE) ? i : 0)
#define MDIO_NXP_S32_HW_INSTANCE(n) \
LISTIFY(__DEBRACKET FEATURE_GMAC_NUM_INSTANCES, \
MDIO_NXP_S32_HW_INSTANCE_CHECK, (|), n)
#define MDIO_NXP_S32_DEVICE(n) \
PINCTRL_DT_INST_DEFINE(n); \
static struct mdio_nxp_s32_data mdio_nxp_s32_data_##n; \
static const struct mdio_nxp_s32_config mdio_nxp_s32_config_##n = { \
.instance = MDIO_NXP_S32_HW_INSTANCE(n), \
.suppress_preamble = (bool)DT_INST_PROP(n, suppress_preamble), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
}; \
DEVICE_DT_INST_DEFINE(n, \
&mdio_nxp_s32_init, \
NULL, \
&mdio_nxp_s32_data_##n, \
&mdio_nxp_s32_config_##n, \
POST_KERNEL, \
CONFIG_MDIO_INIT_PRIORITY, \
&mdio_nxp_s32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MDIO_NXP_S32_DEVICE)
``` | /content/code_sandbox/drivers/mdio/mdio_nxp_s32_gmac.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,565 |
```unknown
config MDIO_NXP_ENET_QOS
bool "NXP ENET QoS MDIO driver"
default y
depends on DT_HAS_NXP_ENET_QOS_MDIO_ENABLED
help
Enable NXP ENET QOS (Quality of Service) MDIO driver.
if MDIO_NXP_ENET_QOS
config MDIO_NXP_ENET_QOS_RECHECK_COUNT
int "Number of times to recheck MDIO transaction status"
default 3
help
Number of times that the driver should recheck the status
of an MDIO bus transaction before timing out
Timeout time is:
CONFIG_MDIO_NXP_ENET_QOS_RECHECK_TIME * CONFIG_MDIO_NXP_ENET_QOS_RECHECK_COUNT
config MDIO_NXP_ENET_QOS_RECHECK_TIME
int "Time between rechecks of transaction status (us)"
default 100
help
The amount of time in microseconds that the driver should
busy wait between checks of the MDIO transaction status.
Timeout time is:
CONFIG_MDIO_NXP_ENET_QOS_RECHECK_TIME * CONFIG_MDIO_NXP_ENET_QOS_RECHECK_COUNT
endif
``` | /content/code_sandbox/drivers/mdio/Kconfig.nxp_enet_qos | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 248 |
```unknown
menuconfig MDIO_NXP_S32_GMAC
bool "NXP S32 GMAC MDIO driver"
default y
depends on DT_HAS_NXP_S32_GMAC_MDIO_ENABLED
select CLOCK_CONTROL
select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
help
Enable GMAC MDIO driver for NXP S32 SoCs.
if MDIO_NXP_S32_GMAC
config MDIO_NXP_S32_TIMEOUT
int "Timeout for read/write operations in milliseconds"
default 2
help
Timeout (in milliseconds) for read/write operations over MDIO.
endif # MDIO_NXP_S32_GMAC
``` | /content/code_sandbox/drivers/mdio/Kconfig.nxp_s32_gmac | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```unknown
config MDIO_NXP_ENET
bool "NXP ENET MDIO Driver"
default y
depends on DT_HAS_NXP_ENET_MDIO_ENABLED
help
Enable NXP ENET MDIO Driver. This Kconfig can be disabled manually
if all ethernet PHYs being used with ENET are not managed by MDIO bus.
if MDIO_NXP_ENET
config MDIO_NXP_ENET_TIMEOUT
int "NXP ENET MDIO Timeout time"
default 250
help
Time in microseconds before an MDIO transaction that has not
finished is considered to have timed out.
endif # MDIO_NXP_ENET
``` | /content/code_sandbox/drivers/mdio/Kconfig.nxp_enet | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 140 |
```c
/*
*
*/
#define DT_DRV_COMPAT litex_liteeth_mdio
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/mdio.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(litex_liteeth_mdio, CONFIG_MDIO_LOG_LEVEL);
#define LITEX_MDIO_CLK BIT(0)
#define LITEX_MDIO_OE BIT(1)
#define LITEX_MDIO_DO BIT(2)
#define LITEX_MDIO_DI BIT(0)
#define LITEX_MDIO_READ_OP 0
#define LITEX_MDIO_WRITE_OP 1
#define LITEX_MDIO_MSB 0x80000000
struct mdio_litex_data {
struct k_sem sem;
};
struct mdio_litex_config {
uint32_t w_addr;
uint32_t r_addr;
};
static void mdio_litex_read(const struct mdio_litex_config *dev_cfg, uint16_t *pdata)
{
uint16_t data = 0;
for (int i = 0; i < 16; i++) {
data <<= 1;
if (litex_read8(dev_cfg->r_addr) & LITEX_MDIO_DI) {
data |= 1;
}
litex_write8(LITEX_MDIO_CLK, dev_cfg->w_addr);
k_busy_wait(1);
litex_write8(0, dev_cfg->w_addr);
k_busy_wait(1);
}
LOG_DBG("Read data: 0x%04x", data);
*pdata = data;
}
static void mdio_litex_write(const struct mdio_litex_config *dev_cfg, uint32_t data, uint8_t len)
{
uint32_t v_data = data;
uint32_t v_len = len;
LOG_DBG("Write data: 0x%08x", data);
v_data <<= 32 - v_len;
while (v_len > 0) {
if (v_data & LITEX_MDIO_MSB) {
litex_write8(LITEX_MDIO_DO | LITEX_MDIO_OE, dev_cfg->w_addr);
k_busy_wait(1);
litex_write8(LITEX_MDIO_CLK | LITEX_MDIO_DO | LITEX_MDIO_OE,
dev_cfg->w_addr);
k_busy_wait(1);
litex_write8(LITEX_MDIO_DO | LITEX_MDIO_OE, dev_cfg->w_addr);
} else {
litex_write8(LITEX_MDIO_OE, dev_cfg->w_addr);
k_busy_wait(1);
litex_write8(LITEX_MDIO_CLK | LITEX_MDIO_OE, dev_cfg->w_addr);
k_busy_wait(1);
litex_write8(LITEX_MDIO_OE, dev_cfg->w_addr);
}
v_data <<= 1;
v_len--;
}
}
static void mdio_litex_turnaround(const struct mdio_litex_config *dev_cfg)
{
k_busy_wait(1);
litex_write8(LITEX_MDIO_CLK, dev_cfg->w_addr);
k_busy_wait(1);
litex_write8(0, dev_cfg->w_addr);
k_busy_wait(1);
litex_write8(LITEX_MDIO_CLK, dev_cfg->w_addr);
k_busy_wait(1);
litex_write8(0, dev_cfg->w_addr);
}
static int mdio_litex_transfer(const struct device *dev, uint8_t prtad, uint8_t devad, uint8_t rw,
uint16_t data_in, uint16_t *data_out)
{
const struct mdio_litex_config *const dev_cfg = dev->config;
struct mdio_litex_data *const dev_data = dev->data;
k_sem_take(&dev_data->sem, K_FOREVER);
litex_write8(LITEX_MDIO_OE, dev_cfg->w_addr);
/* PRE32: 32 bits '1' for sync*/
mdio_litex_write(dev_cfg, 0xFFFFFFFF, 32);
/* ST: 2 bits start of frame */
mdio_litex_write(dev_cfg, 0x1, 2);
/* OP: 2 bits opcode, read '10' or write '01' */
mdio_litex_write(dev_cfg, rw ? 0x1 : 0x2, 2);
/* PA5: 5 bits PHY address */
mdio_litex_write(dev_cfg, prtad, 5);
/* RA5: 5 bits register address */
mdio_litex_write(dev_cfg, devad, 5);
if (rw) { /* Write data */
/* TA: 2 bits turn-around */
mdio_litex_write(dev_cfg, 0x2, 2);
mdio_litex_write(dev_cfg, data_in, 16);
} else { /* Read data */
mdio_litex_turnaround(dev_cfg);
mdio_litex_read(dev_cfg, data_out);
}
mdio_litex_turnaround(dev_cfg);
k_sem_give(&dev_data->sem);
return 0;
}
static int mdio_litex_read_mmi(const struct device *dev, uint8_t prtad, uint8_t devad,
uint16_t *data)
{
return mdio_litex_transfer(dev, prtad, devad, LITEX_MDIO_READ_OP, 0, data);
}
static int mdio_litex_write_mmi(const struct device *dev, uint8_t prtad, uint8_t devad,
uint16_t data)
{
return mdio_litex_transfer(dev, prtad, devad, LITEX_MDIO_WRITE_OP, data, NULL);
}
static int mdio_litex_initialize(const struct device *dev)
{
struct mdio_litex_data *const dev_data = dev->data;
k_sem_init(&dev_data->sem, 1, 1);
return 0;
}
static const struct mdio_driver_api mdio_litex_driver_api = {
.read = mdio_litex_read_mmi,
.write = mdio_litex_write_mmi,
};
#define MDIO_LITEX_DEVICE(inst) \
static struct mdio_litex_config mdio_litex_dev_config_##inst = { \
.w_addr = DT_INST_REG_ADDR_BY_NAME(inst, mdio_w), \
.r_addr = DT_INST_REG_ADDR_BY_NAME(inst, mdio_r), \
}; \
static struct mdio_litex_data mdio_litex_dev_data_##inst; \
DEVICE_DT_INST_DEFINE(inst, &mdio_litex_initialize, NULL, &mdio_litex_dev_data_##inst, \
&mdio_litex_dev_config_##inst, POST_KERNEL, \
CONFIG_MDIO_INIT_PRIORITY, &mdio_litex_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MDIO_LITEX_DEVICE)
``` | /content/code_sandbox/drivers/mdio/mdio_litex_liteeth.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,502 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_mdio_gpio
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_gpio, CONFIG_MDIO_LOG_LEVEL);
#define MDIO_GPIO_READ_OP 0
#define MDIO_GPIO_WRITE_OP 1
#define MDIO_GPIO_MSB 0x80000000
struct mdio_gpio_data {
struct k_sem sem;
};
struct mdio_gpio_config {
struct gpio_dt_spec mdc_gpio;
struct gpio_dt_spec mdio_gpio;
};
static ALWAYS_INLINE void mdio_gpio_clock_the_bit(const struct mdio_gpio_config *dev_cfg)
{
k_busy_wait(1);
gpio_pin_set_dt(&dev_cfg->mdc_gpio, 1);
k_busy_wait(1);
gpio_pin_set_dt(&dev_cfg->mdc_gpio, 0);
}
static ALWAYS_INLINE void mdio_gpio_dir(const struct mdio_gpio_config *dev_cfg, uint8_t dir)
{
gpio_pin_configure_dt(&dev_cfg->mdio_gpio, dir ? GPIO_OUTPUT_ACTIVE : GPIO_INPUT);
if (dir == 0) {
mdio_gpio_clock_the_bit(dev_cfg);
}
}
static ALWAYS_INLINE void mdio_gpio_read(const struct mdio_gpio_config *dev_cfg, uint16_t *pdata)
{
uint16_t data = 0;
for (uint16_t i = 0; i < 16; i++) {
data <<= 1;
mdio_gpio_clock_the_bit(dev_cfg);
if (gpio_pin_get_dt(&dev_cfg->mdio_gpio) == 1) {
data |= 1;
}
}
*pdata = data;
}
static ALWAYS_INLINE void mdio_gpio_write(const struct mdio_gpio_config *dev_cfg,
uint32_t data, uint8_t len)
{
uint32_t v_data = data;
uint32_t v_len = len;
v_data <<= 32 - v_len;
for (; v_len > 0; v_len--) {
gpio_pin_set_dt(&dev_cfg->mdio_gpio, (v_data & MDIO_GPIO_MSB) ? 1 : 0);
mdio_gpio_clock_the_bit(dev_cfg);
v_data <<= 1;
}
}
static int mdio_gpio_transfer(const struct device *dev, uint8_t prtad, uint8_t devad, uint8_t rw,
uint16_t data_in, uint16_t *data_out)
{
const struct mdio_gpio_config *const dev_cfg = dev->config;
struct mdio_gpio_data *const dev_data = dev->data;
k_sem_take(&dev_data->sem, K_FOREVER);
/* DIR: output */
mdio_gpio_dir(dev_cfg, MDIO_GPIO_WRITE_OP);
/* PRE32: 32 bits '1' for sync*/
mdio_gpio_write(dev_cfg, 0xFFFFFFFF, 32);
/* ST: 2 bits start of frame */
mdio_gpio_write(dev_cfg, 0x1, 2);
/* OP: 2 bits opcode, read '10' or write '01' */
mdio_gpio_write(dev_cfg, rw ? 0x1 : 0x2, 2);
/* PA5: 5 bits PHY address */
mdio_gpio_write(dev_cfg, prtad, 5);
/* RA5: 5 bits register address */
mdio_gpio_write(dev_cfg, devad, 5);
if (rw) { /* Write data */
/* TA: 2 bits turn-around */
mdio_gpio_write(dev_cfg, 0x2, 2);
mdio_gpio_write(dev_cfg, data_in, 16);
} else { /* Read data */
/* Release the MDIO line */
mdio_gpio_dir(dev_cfg, MDIO_GPIO_READ_OP);
mdio_gpio_read(dev_cfg, data_out);
}
/* DIR: input. Tristate MDIO line */
mdio_gpio_dir(dev_cfg, MDIO_GPIO_READ_OP);
k_sem_give(&dev_data->sem);
return 0;
}
static int mdio_gpio_read_mmi(const struct device *dev, uint8_t prtad, uint8_t devad,
uint16_t *data)
{
return mdio_gpio_transfer(dev, prtad, devad, MDIO_GPIO_READ_OP, 0, data);
}
static int mdio_gpio_write_mmi(const struct device *dev, uint8_t prtad, uint8_t devad,
uint16_t data)
{
return mdio_gpio_transfer(dev, prtad, devad, MDIO_GPIO_WRITE_OP, data, NULL);
}
static int mdio_gpio_initialize(const struct device *dev)
{
const struct mdio_gpio_config *const dev_cfg = dev->config;
struct mdio_gpio_data *const dev_data = dev->data;
int rc;
k_sem_init(&dev_data->sem, 1, 1);
if (!device_is_ready(dev_cfg->mdc_gpio.port)) {
LOG_ERR("GPIO port for MDC pin is not ready");
return -ENODEV;
}
if (!device_is_ready(dev_cfg->mdio_gpio.port)) {
LOG_ERR("GPIO port for MDIO pin is not ready");
return -ENODEV;
}
rc = gpio_pin_configure_dt(&dev_cfg->mdc_gpio, GPIO_OUTPUT_INACTIVE);
if (rc < 0) {
LOG_ERR("Couldn't configure MDC pin; (%d)", rc);
return rc;
}
rc = gpio_pin_configure_dt(&dev_cfg->mdio_gpio, GPIO_INPUT);
if (rc < 0) {
LOG_ERR("Couldn't configure MDIO pin; (%d)", rc);
return rc;
}
return 0;
}
static const struct mdio_driver_api mdio_gpio_driver_api = {
.read = mdio_gpio_read_mmi,
.write = mdio_gpio_write_mmi,
};
#define MDIO_GPIO_CONFIG(inst) \
static struct mdio_gpio_config mdio_gpio_dev_config_##inst = { \
.mdc_gpio = GPIO_DT_SPEC_INST_GET(inst, mdc_gpios), \
.mdio_gpio = GPIO_DT_SPEC_INST_GET(inst, mdio_gpios), \
};
#define MDIO_GPIO_DEVICE(inst) \
MDIO_GPIO_CONFIG(inst); \
static struct mdio_gpio_data mdio_gpio_dev_data_##inst; \
DEVICE_DT_INST_DEFINE(inst, &mdio_gpio_initialize, NULL, &mdio_gpio_dev_data_##inst, \
&mdio_gpio_dev_config_##inst, POST_KERNEL, \
CONFIG_MDIO_INIT_PRIORITY, &mdio_gpio_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MDIO_GPIO_DEVICE)
``` | /content/code_sandbox/drivers/mdio/mdio_gpio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,433 |
```unknown
# MDIO configuration options
#
# MDIO options
#
menuconfig MDIO
bool "Management Data Input/Output (MDIO) drivers"
help
Enable MDIO Driver Configuration
if MDIO
config MDIO_SHELL
bool "MDIO Shell"
depends on SHELL
help
Enable MDIO Shell.
The MDIO shell currently supports scanning and device
read/write.
# Include these first so that any properties (e.g. defaults) below can be
# overridden (by defining symbols in multiple locations)
source "drivers/mdio/Kconfig.esp32"
source "drivers/mdio/Kconfig.sam"
source "drivers/mdio/Kconfig.nxp_s32_netc"
source "drivers/mdio/Kconfig.nxp_s32_gmac"
source "drivers/mdio/Kconfig.adin2111"
source "drivers/mdio/Kconfig.gpio"
source "drivers/mdio/Kconfig.litex"
source "drivers/mdio/Kconfig.nxp_enet"
source "drivers/mdio/Kconfig.stm32_hal"
source "drivers/mdio/Kconfig.xmc4xxx"
source "drivers/mdio/Kconfig.nxp_enet_qos"
config MDIO_INIT_PRIORITY
int "Init priority"
default 60
help
MDIO device driver initialization priority.
module = MDIO
module-str = mdio
source "subsys/logging/Kconfig.template.log_config"
endif # MDIO
``` | /content/code_sandbox/drivers/mdio/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 295 |
```c
/*
*
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_mdio
#include <errno.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <xmc_scu.h>
#include <xmc_eth_mac.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_xmc4xxx, CONFIG_MDIO_LOG_LEVEL);
#define MDIO_TRANSFER_TIMEOUT_US 250000
#define MAX_MDC_FREQUENCY 2500000u /* 400ns period */
#define MIN_MDC_FREQUENCY 1000000u /* 1us period */
struct mdio_xmc4xxx_clock_divider {
uint8_t divider;
uint8_t reg_val;
};
static const struct mdio_xmc4xxx_clock_divider mdio_clock_divider[] = {
{.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
{.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
{.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
};
struct mdio_xmc4xxx_dev_data {
struct k_mutex mutex;
uint32_t reg_value_gmii_address;
};
struct mdio_xmc4xxx_dev_config {
ETH_GLOBAL_TypeDef *const regs;
const struct pinctrl_dev_config *pcfg;
uint8_t mdi_port_ctrl;
};
static int mdio_xmc4xxx_transfer(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr,
uint8_t is_write, uint16_t data_write, uint16_t *data_read)
{
const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config;
ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs;
struct mdio_xmc4xxx_dev_data *const dev_data = dev->data;
uint32_t reg;
int ret = 0;
k_mutex_lock(&dev_data->mutex, K_FOREVER);
if ((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0) {
ret = -EBUSY;
goto finish;
}
reg = dev_data->reg_value_gmii_address;
if (is_write) {
reg |= ETH_GMII_ADDRESS_MW_Msk;
regs->GMII_DATA = data_write;
}
regs->GMII_ADDRESS = reg | ETH_GMII_ADDRESS_MB_Msk |
FIELD_PREP(ETH_GMII_ADDRESS_PA_Msk, phy_addr) |
FIELD_PREP(ETH_GMII_ADDRESS_MR_Msk, reg_addr);
if (!WAIT_FOR((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0,
MDIO_TRANSFER_TIMEOUT_US, k_msleep(5))) {
LOG_WRN("mdio transfer timedout");
ret = -ETIMEDOUT;
goto finish;
}
if (!is_write && data_read != NULL) {
*data_read = regs->GMII_DATA;
}
finish:
k_mutex_unlock(&dev_data->mutex);
return ret;
}
static int mdio_xmc4xxx_read(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr,
uint16_t *data)
{
return mdio_xmc4xxx_transfer(dev, phy_addr, reg_addr, 0, 0, data);
}
static int mdio_xmc4xxx_write(const struct device *dev, uint8_t phy_addr,
uint8_t reg_addr, uint16_t data)
{
return mdio_xmc4xxx_transfer(dev, phy_addr, reg_addr, 1, data, NULL);
}
static void mdio_xmc4xxx_bus_enable(const struct device *dev)
{
ARG_UNUSED(dev);
/* this will enable the clock for ETH, which generates to MDIO clk */
XMC_ETH_MAC_Enable(NULL);
}
static void mdio_xmc4xxx_bus_disable(const struct device *dev)
{
ARG_UNUSED(dev);
XMC_ETH_MAC_Disable(NULL);
}
static int mdio_xmc4xxx_set_clock_divider(const struct device *dev)
{
struct mdio_xmc4xxx_dev_data *dev_data = dev->data;
uint32_t eth_mac_clk = XMC_SCU_CLOCK_GetEthernetClockFrequency();
for (int i = 0; i < ARRAY_SIZE(mdio_clock_divider); i++) {
uint8_t divider = mdio_clock_divider[i].divider;
uint8_t reg_val = mdio_clock_divider[i].reg_val;
uint32_t mdc_clk = eth_mac_clk / divider;
if (mdc_clk > MIN_MDC_FREQUENCY && mdc_clk < MAX_MDC_FREQUENCY) {
LOG_DBG("Using MDC clock divider %d", divider);
LOG_DBG("MDC clock %dHz", mdc_clk);
dev_data->reg_value_gmii_address =
FIELD_PREP(ETH_GMII_ADDRESS_CR_Msk, reg_val);
return 0;
}
}
return -EINVAL;
}
static int mdio_xmc4xxx_initialize(const struct device *dev)
{
const struct mdio_xmc4xxx_dev_config *dev_cfg = dev->config;
struct mdio_xmc4xxx_dev_data *dev_data = dev->data;
XMC_ETH_MAC_PORT_CTRL_t port_ctrl = {0};
int ret;
k_mutex_init(&dev_data->mutex);
ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
return ret;
}
ret = mdio_xmc4xxx_set_clock_divider(dev);
if (ret != 0) {
LOG_ERR("Error setting MDIO clock divider");
return -EINVAL;
}
port_ctrl.mdio = dev_cfg->mdi_port_ctrl;
ETH0_CON->CON = port_ctrl.raw;
return ret;
}
static const struct mdio_driver_api mdio_xmc4xxx_driver_api = {
.read = mdio_xmc4xxx_read,
.write = mdio_xmc4xxx_write,
.bus_enable = mdio_xmc4xxx_bus_enable,
.bus_disable = mdio_xmc4xxx_bus_disable,
};
PINCTRL_DT_INST_DEFINE(0);
static const struct mdio_xmc4xxx_dev_config mdio_xmc4xxx_dev_config_0 = {
.regs = (ETH_GLOBAL_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(0)),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
.mdi_port_ctrl = DT_INST_ENUM_IDX(0, mdi_port_ctrl),
};
static struct mdio_xmc4xxx_dev_data mdio_xmc4xxx_dev_data_0;
DEVICE_DT_INST_DEFINE(0, &mdio_xmc4xxx_initialize, NULL, &mdio_xmc4xxx_dev_data_0,
&mdio_xmc4xxx_dev_config_0, POST_KERNEL,
CONFIG_MDIO_INIT_PRIORITY, &mdio_xmc4xxx_driver_api);
``` | /content/code_sandbox/drivers/mdio/mdio_xmc4xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,519 |
```c
/*
*
*/
#include <zephyr/shell/shell.h>
#include <stdlib.h>
#include <zephyr/drivers/mdio.h>
#include <string.h>
#include <zephyr/sys/util.h>
#include <zephyr/devicetree.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_shell, CONFIG_LOG_DEFAULT_LEVEL);
#if DT_HAS_COMPAT_STATUS_OKAY(atmel_sam_mdio)
#define DT_DRV_COMPAT atmel_sam_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(espressif_esp32_mdio)
#define DT_DRV_COMPAT espressif_esp32_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_netc_emdio)
#define DT_DRV_COMPAT nxp_s32_netc_emdio
#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_gmac_mdio)
#define DT_DRV_COMPAT nxp_s32_gmac_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(adi_adin2111_mdio)
#define DT_DRV_COMPAT adi_adin2111_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(smsc_lan91c111_mdio)
#define DT_DRV_COMPAT smsc_lan91c111_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(zephyr_mdio_gpio)
#define DT_DRV_COMPAT zephyr_mdio_gpio
#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_enet_mdio)
#define DT_DRV_COMPAT nxp_enet_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(infineon_xmc4xxx_mdio)
#define DT_DRV_COMPAT infineon_xmc4xxx_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_enet_qos_mdio)
#define DT_DRV_COMPAT nxp_enet_qos_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(litex_liteeth_mdio)
#define DT_DRV_COMPAT litex_liteeth_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_mdio)
#define DT_DRV_COMPAT st_stm32_mdio
#else
#error "No known devicetree compatible match for MDIO shell"
#endif
#define MDIO_NODE_ID DT_COMPAT_GET_ANY_STATUS_OKAY(DT_DRV_COMPAT)
/*
* Scan the entire 5-bit address space of the MDIO bus
*
* scan [<reg_addr>]
*/
static int cmd_mdio_scan(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
int cnt;
uint16_t data;
uint16_t reg_addr;
dev = DEVICE_DT_GET(MDIO_NODE_ID);
if (!device_is_ready(dev)) {
shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
return -ENODEV;
}
if (argc >= 2) {
reg_addr = strtol(argv[1], NULL, 16);
} else {
reg_addr = 0;
}
shell_print(sh,
"Scanning bus for devices. Reading register 0x%x",
reg_addr);
cnt = 0;
mdio_bus_enable(dev);
for (int i = 0; i < 32; i++) {
data = 0;
if (mdio_read(dev, i, reg_addr, &data) >= 0 &&
data != UINT16_MAX) {
cnt++;
shell_print(sh, "Found MDIO device @ 0x%x", i);
}
}
mdio_bus_disable(dev);
shell_print(sh, "%u devices found on %s", cnt, dev->name);
return 0;
}
/* mdio write <port_addr> <reg_addr> <data> */
static int cmd_mdio_write(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint16_t data;
uint16_t reg_addr;
uint16_t port_addr;
dev = DEVICE_DT_GET(MDIO_NODE_ID);
if (!device_is_ready(dev)) {
shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
return -ENODEV;
}
port_addr = strtol(argv[1], NULL, 16);
reg_addr = strtol(argv[2], NULL, 16);
data = strtol(argv[3], NULL, 16);
mdio_bus_enable(dev);
if (mdio_write(dev, port_addr, reg_addr, data) < 0) {
shell_error(sh, "Failed to write to device: %s", dev->name);
mdio_bus_disable(dev);
return -EIO;
}
mdio_bus_disable(dev);
return 0;
}
/* mdio read <port_addr> <reg_addr> */
static int cmd_mdio_read(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint16_t data;
uint16_t reg_addr;
uint16_t port_addr;
dev = DEVICE_DT_GET(MDIO_NODE_ID);
if (!device_is_ready(dev)) {
shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
return -ENODEV;
}
port_addr = strtol(argv[1], NULL, 16);
reg_addr = strtol(argv[2], NULL, 16);
mdio_bus_enable(dev);
if (mdio_read(dev, port_addr, reg_addr, &data) < 0) {
shell_error(sh, "Failed to read from device: %s", dev->name);
mdio_bus_disable(dev);
return -EIO;
}
mdio_bus_disable(dev);
shell_print(sh, "%x[%x]: 0x%x", port_addr, reg_addr, data);
return 0;
}
/* mdio write_c45 <port_addr> <dev_addr> <reg_addr> <value> */
static int cmd_mdio_write_45(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint16_t data;
uint16_t reg_addr;
uint8_t dev_addr;
uint8_t port_addr;
dev = DEVICE_DT_GET(MDIO_NODE_ID);
if (!device_is_ready(dev)) {
shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
return -ENODEV;
}
port_addr = strtol(argv[1], NULL, 16);
dev_addr = strtol(argv[2], NULL, 16);
reg_addr = strtol(argv[3], NULL, 16);
data = strtol(argv[4], NULL, 16);
mdio_bus_enable(dev);
if (mdio_write_c45(dev, port_addr, dev_addr, reg_addr, data) < 0) {
shell_error(sh, "Failed to write to device: %s", dev->name);
mdio_bus_disable(dev);
return -EIO;
}
mdio_bus_disable(dev);
return 0;
}
/* mdio read_c45 <port_addr> <dev_addr> <reg_addr> */
static int cmd_mdio_read_c45(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint16_t data;
uint16_t reg_addr;
uint8_t dev_addr;
uint8_t port_addr;
dev = DEVICE_DT_GET(MDIO_NODE_ID);
if (!device_is_ready(dev)) {
shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
return -ENODEV;
}
port_addr = strtol(argv[1], NULL, 16);
dev_addr = strtol(argv[2], NULL, 16);
reg_addr = strtol(argv[3], NULL, 16);
mdio_bus_enable(dev);
if (mdio_read_c45(dev, port_addr, dev_addr, reg_addr, &data) < 0) {
shell_error(sh, "Failed to read from device: %s", dev->name);
mdio_bus_disable(dev);
return -EIO;
}
mdio_bus_disable(dev);
shell_print(sh, "%x[%x:%x]: 0x%x", port_addr, dev_addr, reg_addr, data);
return 0;
}
SHELL_STATIC_SUBCMD_SET_CREATE(sub_mdio_cmds,
SHELL_CMD_ARG(scan, NULL,
"Scan MDIO bus for devices: scan [<reg_addr>]",
cmd_mdio_scan, 0, 1),
SHELL_CMD_ARG(read, NULL,
"Read from MDIO device: read <phy_addr> <reg_addr>",
cmd_mdio_read, 3, 0),
SHELL_CMD_ARG(write, NULL,
"Write to MDIO device: write <phy_addr> <reg_addr> <value>",
cmd_mdio_write, 4, 0),
SHELL_CMD_ARG(read_c45, NULL,
"Read from MDIO Clause 45 device: "
"read_c45 <port_addr> <dev_addr> <reg_addr>",
cmd_mdio_read_c45, 4, 0),
SHELL_CMD_ARG(write_c45, NULL,
"Write to MDIO Clause 45 device: "
"write_c45 <port_addr> <dev_addr> <reg_addr> <value>",
cmd_mdio_write_45, 5, 0),
SHELL_SUBCMD_SET_END /* Array terminated. */
);
SHELL_CMD_REGISTER(mdio, &sub_mdio_cmds, "MDIO commands", NULL);
``` | /content/code_sandbox/drivers/mdio/mdio_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,972 |
```unknown
config MDIO_INFINEON_XMC4XXX
bool "Infineon XMC4XXX MDIO driver"
default y
depends on DT_HAS_INFINEON_XMC4XXX_MDIO_ENABLED
help
Enable Infineon XMC4XXX MDIO driver.
``` | /content/code_sandbox/drivers/mdio/Kconfig.xmc4xxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32_netc_emdio
#include <zephyr/kernel.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(nxp_s32_emdio, CONFIG_MDIO_LOG_LEVEL);
#include <Netc_EthSwt_Ip.h>
struct nxp_s32_mdio_config {
const struct pinctrl_dev_config *pincfg;
uint8_t instance;
};
struct nxp_s32_mdio_data {
struct k_mutex rw_mutex;
};
static int nxp_s32_mdio_read(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t *regval)
{
const struct nxp_s32_mdio_config *cfg = dev->config;
struct nxp_s32_mdio_data *data = dev->data;
Std_ReturnType status;
k_mutex_lock(&data->rw_mutex, K_FOREVER);
status = Netc_EthSwt_Ip_ReadTrcvRegister(cfg->instance, prtad, regad, regval);
k_mutex_unlock(&data->rw_mutex);
return status == E_OK ? 0 : -EIO;
}
static int nxp_s32_mdio_write(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t regval)
{
const struct nxp_s32_mdio_config *cfg = dev->config;
struct nxp_s32_mdio_data *data = dev->data;
Std_ReturnType status;
k_mutex_lock(&data->rw_mutex, K_FOREVER);
status = Netc_EthSwt_Ip_WriteTrcvRegister(cfg->instance, prtad, regad, regval);
k_mutex_unlock(&data->rw_mutex);
return status == E_OK ? 0 : -EIO;
}
static int nxp_s32_mdio_initialize(const struct device *dev)
{
struct nxp_s32_mdio_data *data = dev->data;
const struct nxp_s32_mdio_config *cfg = dev->config;
int err;
err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
if (err != 0) {
return err;
}
k_mutex_init(&data->rw_mutex);
return 0;
}
static const struct mdio_driver_api nxp_s32_mdio_api = {
.read = nxp_s32_mdio_read,
.write = nxp_s32_mdio_write,
};
#define NXP_S32_MDIO_HW_INSTANCE_CHECK(i, n) \
((DT_INST_REG_ADDR(n) == IP_NETC_EMDIO_##n##_BASE) ? i : 0)
#define NXP_S32_MDIO_HW_INSTANCE(n) \
LISTIFY(__DEBRACKET NETC_F1_INSTANCE_COUNT, NXP_S32_MDIO_HW_INSTANCE_CHECK, (|), n)
#define NXP_S32_MDIO_INSTANCE_DEFINE(n) \
PINCTRL_DT_INST_DEFINE(n); \
static struct nxp_s32_mdio_data nxp_s32_mdio##n##_data; \
static const struct nxp_s32_mdio_config nxp_s32_mdio##n##_cfg = { \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.instance = NXP_S32_MDIO_HW_INSTANCE(n), \
}; \
DEVICE_DT_INST_DEFINE(n, \
&nxp_s32_mdio_initialize, \
NULL, \
&nxp_s32_mdio##n##_data, \
&nxp_s32_mdio##n##_cfg, \
POST_KERNEL, \
CONFIG_MDIO_INIT_PRIORITY, \
&nxp_s32_mdio_api);
DT_INST_FOREACH_STATUS_OKAY(NXP_S32_MDIO_INSTANCE_DEFINE)
``` | /content/code_sandbox/drivers/mdio/mdio_nxp_s32_netc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 829 |
```c
/*
*
*/
#include <stdint.h>
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/net/ethernet.h>
#include <zephyr/net/mdio.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_stm32_hal, CONFIG_MDIO_LOG_LEVEL);
#define DT_DRV_COMPAT st_stm32_mdio
#define ADIN1100_REG_VALUE_MASK GENMASK(15, 0)
struct mdio_stm32_data {
struct k_sem sem;
ETH_HandleTypeDef heth;
};
struct mdio_stm32_config {
const struct pinctrl_dev_config *pincfg;
};
static int mdio_stm32_read(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t *data)
{
struct mdio_stm32_data *const dev_data = dev->data;
ETH_HandleTypeDef *heth = &dev_data->heth;
uint32_t read;
int ret;
k_sem_take(&dev_data->sem, K_FOREVER);
ret = HAL_ETH_ReadPHYRegister(heth, prtad, regad, &read);
k_sem_give(&dev_data->sem);
if (ret != HAL_OK) {
return -EIO;
}
*data = read & ADIN1100_REG_VALUE_MASK;
return ret;
}
static int mdio_stm32_write(const struct device *dev, uint8_t prtad,
uint8_t regad, uint16_t data)
{
struct mdio_stm32_data *const dev_data = dev->data;
ETH_HandleTypeDef *heth = &dev_data->heth;
int ret;
k_sem_take(&dev_data->sem, K_FOREVER);
ret = HAL_ETH_WritePHYRegister(heth, prtad, regad, data);
k_sem_give(&dev_data->sem);
if (ret != HAL_OK) {
return -EIO;
}
return ret;
}
static void mdio_stm32_bus_enable(const struct device *dev)
{
ARG_UNUSED(dev);
}
static void mdio_stm32_bus_disable(const struct device *dev)
{
ARG_UNUSED(dev);
}
static int mdio_stm32_init(const struct device *dev)
{
struct mdio_stm32_data *const dev_data = dev->data;
const struct mdio_stm32_config *const config = dev->config;
int ret;
ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
k_sem_init(&dev_data->sem, 1, 1);
return 0;
}
static const struct mdio_driver_api mdio_stm32_api = {
.read = mdio_stm32_read,
.write = mdio_stm32_write,
.bus_enable = mdio_stm32_bus_enable,
.bus_disable = mdio_stm32_bus_disable,
};
#define MDIO_STM32_HAL_DEVICE(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
\
static struct mdio_stm32_data mdio_stm32_data_##inst = { \
.heth = {.Instance = (ETH_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(inst))}, \
}; \
static struct mdio_stm32_config mdio_stm32_config_##inst = { \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
DEVICE_DT_INST_DEFINE(inst, &mdio_stm32_init, NULL, \
&mdio_stm32_data_##inst, &mdio_stm32_config_##inst, \
POST_KERNEL, CONFIG_ETH_INIT_PRIORITY, \
&mdio_stm32_api);
DT_INST_FOREACH_STATUS_OKAY(MDIO_STM32_HAL_DEVICE)
``` | /content/code_sandbox/drivers/mdio/mdio_stm32_hal.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 853 |
```unknown
# Atmel SAM SPI
config SPI_SAM
bool "Atmel SAM series SPI driver"
default y
depends on DT_HAS_ATMEL_SAM_SPI_ENABLED
select GPIO
help
Enable support for the SAM SPI driver.
if SPI_SAM
config SPI_SAM_DMA
bool "SPI SAM DMA Support"
select DMA
help
Enable using DMA with SPI for SPI instances that enable dma channels in
their device tree node.
if SPI_RTIO
config SPI_SAM_RTIO_SQ_SIZE
int "Number of available submission queue entries"
default 8 # Sensible default that covers most common spi transactions
help
When RTIO is use with SPI each driver holds a context with which blocking
API calls use to perform SPI transactions. This queue needs to be as deep
as the longest set of spi_buf_sets used, where normal SPI operations are
used (equal length buffers). It may need to be slightly deeper where the
spi buffer sets for transmit/receive are not always matched equally in
length as these are transformed into normal transceives.
endif # SPI_RTIO
endif # SPI_SAM
``` | /content/code_sandbox/drivers/spi/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 242 |
```unknown
# Hidden option for turning on the dummy driver for vnd,spi devices
# used in testing.
config SPI_TEST
def_bool DT_HAS_VND_SPI_ENABLED
depends on DT_HAS_VND_SPI_ENABLED
``` | /content/code_sandbox/drivers/spi/Kconfig.test | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_enet_qos_mdio
#include <zephyr/net/mdio.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/ethernet/eth_nxp_enet_qos.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_nxp_enet_qos, CONFIG_MDIO_LOG_LEVEL);
struct nxp_enet_qos_mdio_config {
const struct device *enet_dev;
};
struct nxp_enet_qos_mdio_data {
struct k_mutex mdio_mutex;
};
struct mdio_transaction {
enum mdio_opcode op;
union {
uint16_t write_data;
uint16_t *read_data;
};
uint8_t portaddr;
uint8_t regaddr;
enet_qos_t *base;
struct k_mutex *mdio_bus_mutex;
};
static bool check_busy(enet_qos_t *base)
{
uint32_t val = base->MAC_MDIO_ADDRESS;
/* Return the busy bit */
return ENET_QOS_REG_GET(MAC_MDIO_ADDRESS, GB, val);
}
static int do_transaction(struct mdio_transaction *mdio)
{
enet_qos_t *base = mdio->base;
uint8_t goc_1_code;
int ret;
k_mutex_lock(mdio->mdio_bus_mutex, K_FOREVER);
if (mdio->op == MDIO_OP_C22_WRITE) {
base->MAC_MDIO_DATA =
/* Prepare the data to be written */
ENET_QOS_REG_PREP(MAC_MDIO_DATA, GD, mdio->write_data);
goc_1_code = 0b0;
} else if (mdio->op == MDIO_OP_C22_READ) {
goc_1_code = 0b1;
} else {
ret = -EINVAL;
goto done;
}
base->MAC_MDIO_ADDRESS =
/* OP command */
ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, GOC_1, goc_1_code) |
ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, GOC_0, 0b1) |
/* PHY address */
ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, PA, mdio->portaddr) |
/* Register address */
ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, RDA, mdio->regaddr);
base->MAC_MDIO_ADDRESS =
/* Start the transaction */
ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, GB, 0b1);
ret = -ETIMEDOUT;
for (int i = CONFIG_MDIO_NXP_ENET_QOS_RECHECK_COUNT; i > 0; i--) {
if (!check_busy(base)) {
ret = 0;
break;
}
k_busy_wait(CONFIG_MDIO_NXP_ENET_QOS_RECHECK_TIME);
}
if (ret) {
LOG_ERR("MDIO transaction timed out");
goto done;
}
if (mdio->op == MDIO_OP_C22_READ) {
uint32_t val = mdio->base->MAC_MDIO_DATA;
*mdio->read_data =
/* Decipher the read data */
ENET_QOS_REG_GET(MAC_MDIO_DATA, GD, val);
}
done:
k_mutex_unlock(mdio->mdio_bus_mutex);
return ret;
}
static int nxp_enet_qos_mdio_read(const struct device *dev,
uint8_t portaddr, uint8_t regaddr,
uint16_t *read_data)
{
const struct nxp_enet_qos_mdio_config *config = dev->config;
struct nxp_enet_qos_mdio_data *data = dev->data;
enet_qos_t *base = ENET_QOS_MODULE_CFG(config->enet_dev)->base;
struct mdio_transaction mdio_read = {
.op = MDIO_OP_C22_READ,
.read_data = read_data,
.portaddr = portaddr,
.regaddr = regaddr,
.base = base,
.mdio_bus_mutex = &data->mdio_mutex,
};
return do_transaction(&mdio_read);
}
static int nxp_enet_qos_mdio_write(const struct device *dev,
uint8_t portaddr, uint8_t regaddr,
uint16_t write_data)
{
const struct nxp_enet_qos_mdio_config *config = dev->config;
struct nxp_enet_qos_mdio_data *data = dev->data;
enet_qos_t *base = ENET_QOS_MODULE_CFG(config->enet_dev)->base;
struct mdio_transaction mdio_write = {
.op = MDIO_OP_C22_WRITE,
.write_data = write_data,
.portaddr = portaddr,
.regaddr = regaddr,
.base = base,
.mdio_bus_mutex = &data->mdio_mutex,
};
return do_transaction(&mdio_write);
}
static const struct mdio_driver_api nxp_enet_qos_mdio_api = {
.read = nxp_enet_qos_mdio_read,
.write = nxp_enet_qos_mdio_write,
};
static int nxp_enet_qos_mdio_init(const struct device *dev)
{
const struct nxp_enet_qos_mdio_config *mdio_config = dev->config;
struct nxp_enet_qos_mdio_data *data = dev->data;
const struct nxp_enet_qos_config *config = ENET_QOS_MODULE_CFG(mdio_config->enet_dev);
uint32_t enet_module_clk_rate;
int ret, divider;
ret = k_mutex_init(&data->mdio_mutex);
if (ret) {
return ret;
}
ret = clock_control_get_rate(config->clock_dev, config->clock_subsys,
&enet_module_clk_rate);
if (ret) {
return ret;
}
enet_module_clk_rate /= 1000000;
if (enet_module_clk_rate >= 20 && enet_module_clk_rate < 35) {
divider = 2;
} else if (enet_module_clk_rate < 60) {
divider = 3;
} else if (enet_module_clk_rate < 100) {
divider = 0;
} else if (enet_module_clk_rate < 150) {
divider = 1;
} else if (enet_module_clk_rate < 250) {
divider = 4;
} else {
LOG_ERR("ENET QOS clk rate does not allow MDIO");
return -ENOTSUP;
}
config->base->MAC_MDIO_ADDRESS =
/* Configure the MDIO clock range / divider */
ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, CR, divider);
return 0;
}
#define NXP_ENET_QOS_MDIO_INIT(inst) \
\
static const struct nxp_enet_qos_mdio_config \
nxp_enet_qos_mdio_cfg_##inst = { \
.enet_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
}; \
\
static struct nxp_enet_qos_mdio_data nxp_enet_qos_mdio_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, &nxp_enet_qos_mdio_init, NULL, \
&nxp_enet_qos_mdio_data_##inst, \
&nxp_enet_qos_mdio_cfg_##inst, \
POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \
&nxp_enet_qos_mdio_api); \
DT_INST_FOREACH_STATUS_OKAY(NXP_ENET_QOS_MDIO_INIT)
``` | /content/code_sandbox/drivers/mdio/mdio_nxp_enet_qos.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,674 |
```objective-c
/*
*
*/
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_atcspi200);
#include "spi_context.h"
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#ifdef CONFIG_ANDES_SPI_DMA_MODE
#include <zephyr/drivers/dma.h>
#endif
#define REG_TFMAT 0x10
#define REG_TCTRL 0x20
#define REG_CMD 0x24
#define REG_DATA 0x2c
#define REG_CTRL 0x30
#define REG_STAT 0x34
#define REG_INTEN 0x38
#define REG_INTST 0x3c
#define REG_TIMIN 0x40
#define REG_CONFIG 0x7c
#define SPI_TFMAT(base) (base + REG_TFMAT)
#define SPI_TCTRL(base) (base + REG_TCTRL)
#define SPI_CMD(base) (base + REG_CMD)
#define SPI_DATA(base) (base + REG_DATA)
#define SPI_CTRL(base) (base + REG_CTRL)
#define SPI_STAT(base) (base + REG_STAT)
#define SPI_INTEN(base) (base + REG_INTEN)
#define SPI_INTST(base) (base + REG_INTST)
#define SPI_TIMIN(base) (base + REG_TIMIN)
#define SPI_CONFIG(base) (base + REG_CONFIG)
/* Field mask of SPI transfer format register */
#define TFMAT_DATA_LEN_OFFSET (8)
#define TFMAT_CPHA_MSK BIT(0)
#define TFMAT_CPOL_MSK BIT(1)
#define TFMAT_SLVMODE_MSK BIT(2)
#define TFMAT_LSB_MSK BIT(3)
#define TFMAT_DATA_MERGE_MSK BIT(7)
#define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
#define TFMAT_ADDR_LEN_MSK GENMASK(18, 16)
/* Field mask of SPI transfer control register */
#define TCTRL_RD_TCNT_OFFSET (0)
#define TCTRL_WR_TCNT_OFFSET (12)
#define TCTRL_TRNS_MODE_OFFSET (24)
#define TCTRL_WR_TCNT_MSK GENMASK(20, 12)
#define TCTRL_TRNS_MODE_MSK GENMASK(27, 24)
/* Transfer mode */
#define TRNS_MODE_WRITE_READ (0)
#define TRNS_MODE_WRITE_ONLY (1)
#define TRNS_MODE_READ_ONLY (2)
/* Field mask of SPI interrupt enable register */
#define IEN_RX_FIFO_MSK BIT(2)
#define IEN_TX_FIFO_MSK BIT(3)
#define IEN_END_MSK BIT(4)
/* Field mask of SPI interrupt status register */
#define INTST_RX_FIFO_INT_MSK BIT(2)
#define INTST_TX_FIFO_INT_MSK BIT(3)
#define INTST_END_INT_MSK BIT(4)
/* Field mask of SPI config register */
#define CFG_RX_FIFO_SIZE_MSK GENMASK(3, 0)
#define CFG_TX_FIFO_SIZE_MSK GENMASK(7, 4)
/* Field mask of SPI status register */
#define STAT_RX_NUM_MSK GENMASK(12, 8)
#define STAT_TX_NUM_MSK GENMASK(20, 16)
/* Field mask of SPI control register */
#define CTRL_RX_FIFO_RST_OFFSET (1)
#define CTRL_TX_FIFO_RST_OFFSET (2)
#define CTRL_RX_THRES_OFFSET (8)
#define CTRL_TX_THRES_OFFSET (16)
#define CTRL_RX_FIFO_RST_MSK BIT(1)
#define CTRL_TX_FIFO_RST_MSK BIT(2)
#define CTRL_RX_DMA_EN_MSK BIT(3)
#define CTRL_TX_DMA_EN_MSK BIT(4)
#define CTRL_RX_THRES_MSK GENMASK(12, 8)
#define CTRL_TX_THRES_MSK GENMASK(20, 16)
/* Field mask of SPI status register */
#define TIMIN_SCLK_DIV_MSK GENMASK(7, 0)
#define TX_FIFO_THRESHOLD (1)
#define RX_FIFO_THRESHOLD (1)
#define MAX_TRANSFER_CNT (512)
#define MAX_CHAIN_SIZE (8)
#define TX_FIFO_SIZE_SETTING(base) \
(sys_read32(SPI_CONFIG(base)) & CFG_TX_FIFO_SIZE_MSK)
#define TX_FIFO_SIZE(base) \
(2 << (TX_FIFO_SIZE_SETTING(base) >> 4))
#define RX_FIFO_SIZE_SETTING(base) \
(sys_read32(SPI_CONFIG(base)) & CFG_RX_FIFO_SIZE_MSK)
#define RX_FIFO_SIZE(base) \
(2 << (RX_FIFO_SIZE_SETTING(base) >> 0))
#define TX_NUM_STAT(base) (sys_read32(SPI_STAT(base)) & STAT_TX_NUM_MSK)
#define RX_NUM_STAT(base) (sys_read32(SPI_STAT(base)) & STAT_RX_NUM_MSK)
#define GET_TX_NUM(base) (TX_NUM_STAT(base) >> 16)
#define GET_RX_NUM(base) (RX_NUM_STAT(base) >> 8)
``` | /content/code_sandbox/drivers/spi/spi_andes_atcspi200.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,062 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_qmspi
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_xec, CONFIG_SPI_LOG_LEVEL);
#include "spi_context.h"
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
/* Device constant configuration parameters */
struct spi_qmspi_config {
QMSPI_Type *regs;
uint32_t cs_timing;
uint8_t girq;
uint8_t girq_pos;
uint8_t girq_nvic_aggr;
uint8_t girq_nvic_direct;
uint8_t irq_pri;
uint8_t chip_sel;
uint8_t width; /* 1(single), 2(dual), 4(quad) */
uint8_t unused;
const struct pinctrl_dev_config *pcfg;
};
/* Device run time data */
struct spi_qmspi_data {
struct spi_context ctx;
};
static inline uint32_t descr_rd(QMSPI_Type *regs, uint32_t did)
{
uintptr_t raddr = (uintptr_t)regs + MCHP_QMSPI_DESC0_OFS +
((did & MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 2);
return REG32(raddr);
}
static inline void descr_wr(QMSPI_Type *regs, uint32_t did, uint32_t val)
{
uintptr_t raddr = (uintptr_t)regs + MCHP_QMSPI_DESC0_OFS +
((did & MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 2);
REG32(raddr) = val;
}
static inline void txb_wr8(QMSPI_Type *regs, uint8_t data8)
{
REG8(®s->TX_FIFO) = data8;
}
static inline uint8_t rxb_rd8(QMSPI_Type *regs)
{
return REG8(®s->RX_FIFO);
}
/*
* Program QMSPI frequency.
* MEC1501 base frequency is 48MHz. QMSPI frequency divider field in the
* mode register is defined as: 0=maximum divider of 256. Values 1 through
* 255 divide 48MHz by that value.
*/
static void qmspi_set_frequency(QMSPI_Type *regs, uint32_t freq_hz)
{
uint32_t div, qmode;
if (freq_hz == 0) {
div = 0; /* max divider = 256 */
} else {
div = MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ / freq_hz;
if (div == 0) {
div = 1; /* max freq. divider = 1 */
} else if (div > 0xffu) {
div = 0u; /* max divider = 256 */
}
}
qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK);
qmode |= (div << MCHP_QMSPI_M_FDIV_POS) & MCHP_QMSPI_M_FDIV_MASK;
regs->MODE = qmode;
}
/*
* SPI signalling mode: CPOL and CPHA
* CPOL = 0 is clock idles low, 1 is clock idle high
* CPHA = 0 Transmitter changes data on trailing of preceding clock cycle.
* Receiver samples data on leading edge of clock cycle.
* 1 Transmitter changes data on leading edge of current clock cycle.
* Receiver samples data on the trailing edge of clock cycle.
* SPI Mode nomenclature:
* Mode CPOL CPHA
* 0 0 0
* 1 0 1
* 2 1 0
* 3 1 1
* MEC1501 has three controls, CPOL, CPHA for output and CPHA for input.
* SPI frequency < 48MHz
* Mode 0: CPOL=0 CHPA=0 (CHPA_MISO=0 and CHPA_MOSI=0)
* Mode 3: CPOL=1 CHPA=1 (CHPA_MISO=1 and CHPA_MOSI=1)
* Data sheet recommends when QMSPI set at max. SPI frequency (48MHz).
* SPI frequency == 48MHz sample and change data on same edge.
* Mode 0: CPOL=0 CHPA=0 (CHPA_MISO=1 and CHPA_MOSI=0)
* Mode 3: CPOL=1 CHPA=1 (CHPA_MISO=0 and CHPA_MOSI=1)
*/
const uint8_t smode_tbl[4] = {
0x00u, 0x06u, 0x01u, 0x07u
};
const uint8_t smode48_tbl[4] = {
0x04u, 0x02u, 0x05u, 0x03u
};
static void qmspi_set_signalling_mode(QMSPI_Type *regs, uint32_t smode)
{
const uint8_t *ptbl;
uint32_t m;
ptbl = smode_tbl;
if (((regs->MODE >> MCHP_QMSPI_M_FDIV_POS) &
MCHP_QMSPI_M_FDIV_MASK0) == 1) {
ptbl = smode48_tbl;
}
m = (uint32_t)ptbl[smode & 0x03];
regs->MODE = (regs->MODE & ~(MCHP_QMSPI_M_SIG_MASK))
| (m << MCHP_QMSPI_M_SIG_POS);
}
/*
* QMSPI HW support single, dual, and quad.
* Return QMSPI Control/Descriptor register encoded value.
*/
static uint32_t qmspi_config_get_lines(const struct spi_config *config)
{
#ifdef CONFIG_SPI_EXTENDED_MODES
uint32_t qlines;
switch (config->operation & SPI_LINES_MASK) {
case SPI_LINES_SINGLE:
qlines = MCHP_QMSPI_C_IFM_1X;
break;
#if DT_INST_PROP(0, lines) > 1
case SPI_LINES_DUAL:
qlines = MCHP_QMSPI_C_IFM_2X;
break;
#endif
#if DT_INST_PROP(0, lines) > 2
case SPI_LINES_QUAD:
qlines = MCHP_QMSPI_C_IFM_4X;
break;
#endif
default:
qlines = 0xffu;
}
return qlines;
#else
return MCHP_QMSPI_C_IFM_1X;
#endif
}
/*
* Configure QMSPI.
* NOTE: QMSPI can control two chip selects. At this time we use CS0# only.
*/
static int qmspi_configure(const struct device *dev,
const struct spi_config *config)
{
const struct spi_qmspi_config *cfg = dev->config;
struct spi_qmspi_data *data = dev->data;
QMSPI_Type *regs = cfg->regs;
uint32_t smode;
if (spi_context_configured(&data->ctx, config)) {
return 0;
}
if (config->operation & SPI_HALF_DUPLEX) {
return -ENOTSUP;
}
if (config->operation & (SPI_TRANSFER_LSB | SPI_OP_MODE_SLAVE
| SPI_MODE_LOOP)) {
return -ENOTSUP;
}
smode = qmspi_config_get_lines(config);
if (smode == 0xff) {
return -ENOTSUP;
}
regs->CTRL = smode;
/* Use the requested or next highest possible frequency */
qmspi_set_frequency(regs, config->frequency);
smode = 0;
if ((config->operation & SPI_MODE_CPHA) != 0U) {
smode |= (1ul << 0);
}
if ((config->operation & SPI_MODE_CPOL) != 0U) {
smode |= (1ul << 1);
}
qmspi_set_signalling_mode(regs, smode);
if (SPI_WORD_SIZE_GET(config->operation) != 8) {
return -ENOTSUP;
}
/* chip select */
smode = regs->MODE & ~(MCHP_QMSPI_M_CS_MASK);
#if DT_INST_PROP(0, chip_select) == 0
smode |= MCHP_QMSPI_M_CS0;
#else
smode |= MCHP_QMSPI_M_CS1;
#endif
regs->MODE = smode;
/* chip select timing */
regs->CSTM = cfg->cs_timing;
data->ctx.config = config;
regs->MODE |= MCHP_QMSPI_M_ACTIVATE;
return 0;
}
/*
* Transmit dummy clocks - QMSPI will generate requested number of
* SPI clocks with I/O pins tri-stated.
* Single mode: 1 bit per clock -> IFM field = 00b. Max 0x7fff clocks
* Dual mode: 2 bits per clock -> IFM field = 01b. Max 0x3fff clocks
* Quad mode: 4 bits per clock -> IFM field = 1xb. Max 0x1fff clocks
* QMSPI unit size set to bits.
*/
static int qmspi_tx_dummy_clocks(QMSPI_Type *regs, uint32_t nclocks)
{
uint32_t descr, ifm, qstatus;
ifm = regs->CTRL & MCHP_QMSPI_C_IFM_MASK;
descr = ifm | MCHP_QMSPI_C_TX_DIS | MCHP_QMSPI_C_XFR_UNITS_BITS
| MCHP_QMSPI_C_DESCR_LAST | MCHP_QMSPI_C_DESCR0;
if (ifm & 0x01) {
nclocks <<= 1;
} else if (ifm & 0x02) {
nclocks <<= 2;
}
descr |= (nclocks << MCHP_QMSPI_C_XFR_NUNITS_POS);
descr_wr(regs, 0, descr);
regs->CTRL |= MCHP_QMSPI_C_DESCR_EN;
regs->IEN = 0;
regs->STS = 0xfffffffful;
regs->EXE = MCHP_QMSPI_EXE_START;
do {
qstatus = regs->STS;
if (qstatus & MCHP_QMSPI_STS_PROG_ERR) {
return -EIO;
}
} while ((qstatus & MCHP_QMSPI_STS_DONE) == 0);
return 0;
}
/*
* Return unit size power of 2 given number of bytes to transfer.
*/
static uint32_t qlen_shift(uint32_t len)
{
uint32_t ushift;
/* is len a multiple of 4 or 16? */
if ((len & 0x0F) == 0) {
ushift = 4;
} else if ((len & 0x03) == 0) {
ushift = 2;
} else {
ushift = 0;
}
return ushift;
}
/*
* Return QMSPI unit size of the number of units field in QMSPI
* control/descriptor register.
* Input: power of 2 unit size 4, 2, or 0(default) corresponding
* to 16, 4, or 1 byte units.
*/
static uint32_t get_qunits(uint32_t qshift)
{
if (qshift == 4) {
return MCHP_QMSPI_C_XFR_UNITS_16;
} else if (qshift == 2) {
return MCHP_QMSPI_C_XFR_UNITS_4;
} else {
return MCHP_QMSPI_C_XFR_UNITS_1;
}
}
/*
* Allocate(build) one or more descriptors.
* QMSPI contains 16 32-bit descriptor registers used as a linked
* list of operations. Using only 32-bits there are limitations.
* Each descriptor is limited to 0x7FFF units where unit size can
* be 1, 4, or 16 bytes. A descriptor can perform transmit or receive
* but not both simultaneously. Order of descriptor processing is specified
* by the first descriptor field of the control register, the next descriptor
* fields in each descriptor, and the descriptors last flag.
*/
static int qmspi_descr_alloc(QMSPI_Type *regs, const struct spi_buf *txb,
int didx, bool is_tx)
{
uint32_t descr, qshift, n, nu;
int dn;
if (didx >= MCHP_QMSPI_MAX_DESCR) {
return -EAGAIN;
}
if (txb->len == 0) {
return didx; /* nothing to do */
}
/* b[1:0] IFM and b[3:2] transmit mode */
descr = (regs->CTRL & MCHP_QMSPI_C_IFM_MASK);
if (is_tx) {
descr |= MCHP_QMSPI_C_TX_DATA;
} else {
descr |= MCHP_QMSPI_C_RX_EN;
}
/* b[11:10] unit size 1, 4, or 16 bytes */
qshift = qlen_shift(txb->len);
nu = txb->len >> qshift;
descr |= get_qunits(qshift);
do {
descr &= 0x0FFFul;
dn = didx + 1;
/* b[15:12] next descriptor pointer */
descr |= ((dn & MCHP_QMSPI_C_NEXT_DESCR_MASK0) <<
MCHP_QMSPI_C_NEXT_DESCR_POS);
n = nu;
if (n > MCHP_QMSPI_C_MAX_UNITS) {
n = MCHP_QMSPI_C_MAX_UNITS;
}
descr |= (n << MCHP_QMSPI_C_XFR_NUNITS_POS);
descr_wr(regs, didx, descr);
if (dn < MCHP_QMSPI_MAX_DESCR) {
didx++;
} else {
return -EAGAIN;
}
nu -= n;
} while (nu);
return dn;
}
static int qmspi_tx(QMSPI_Type *regs, const struct spi_buf *tx_buf,
bool close)
{
const uint8_t *p = tx_buf->buf;
size_t tlen = tx_buf->len;
uint32_t descr;
int didx;
if (tlen == 0) {
return 0;
}
/* Buffer pointer is NULL and number of bytes != 0 ? */
if (p == NULL) {
return qmspi_tx_dummy_clocks(regs, tlen);
}
didx = qmspi_descr_alloc(regs, tx_buf, 0, true);
if (didx < 0) {
return didx;
}
/* didx points to last allocated descriptor + 1 */
__ASSERT(didx > 0, "QMSPI descriptor index=%d expected > 0\n", didx);
didx--;
descr = descr_rd(regs, didx) | MCHP_QMSPI_C_DESCR_LAST;
if (close) {
descr |= MCHP_QMSPI_C_CLOSE;
}
descr_wr(regs, didx, descr);
regs->CTRL = (regs->CTRL & MCHP_QMSPI_C_IFM_MASK) |
MCHP_QMSPI_C_DESCR_EN | MCHP_QMSPI_C_DESCR0;
regs->IEN = 0;
regs->STS = 0xfffffffful;
/* preload TX_FIFO */
while (tlen) {
tlen--;
txb_wr8(regs, *p);
p++;
if (regs->STS & MCHP_QMSPI_STS_TXBF_RO) {
break;
}
}
regs->EXE = MCHP_QMSPI_EXE_START;
if (regs->STS & MCHP_QMSPI_STS_PROG_ERR) {
return -EIO;
}
while (tlen) {
while (regs->STS & MCHP_QMSPI_STS_TXBF_RO) {
}
txb_wr8(regs, *p);
p++;
tlen--;
}
/* Wait for TX FIFO to drain and last byte to be clocked out */
for (;;) {
if (regs->STS & MCHP_QMSPI_STS_DONE) {
break;
}
}
return 0;
}
static int qmspi_rx(QMSPI_Type *regs, const struct spi_buf *rx_buf,
bool close)
{
uint8_t *p = rx_buf->buf;
size_t rlen = rx_buf->len;
uint32_t descr;
int didx;
uint8_t data_byte;
if (rlen == 0) {
return 0;
}
didx = qmspi_descr_alloc(regs, rx_buf, 0, false);
if (didx < 0) {
return didx;
}
/* didx points to last allocated descriptor + 1 */
__ASSERT_NO_MSG(didx > 0);
didx--;
descr = descr_rd(regs, didx) | MCHP_QMSPI_C_DESCR_LAST;
if (close) {
descr |= MCHP_QMSPI_C_CLOSE;
}
descr_wr(regs, didx, descr);
regs->CTRL = (regs->CTRL & MCHP_QMSPI_C_IFM_MASK)
| MCHP_QMSPI_C_DESCR_EN | MCHP_QMSPI_C_DESCR0;
regs->IEN = 0;
regs->STS = 0xfffffffful;
/*
* Trigger read based on the descriptor(s) programmed above.
* QMSPI will generate clocks until the RX FIFO is filled.
* More clocks will be generated as we pull bytes from the RX FIFO.
* QMSPI Programming error will be triggered after start if
* descriptors were programmed options that cannot be enabled
* simultaneously.
*/
regs->EXE = MCHP_QMSPI_EXE_START;
if (regs->STS & MCHP_QMSPI_STS_PROG_ERR) {
return -EIO;
}
while (rlen) {
if (!(regs->STS & MCHP_QMSPI_STS_RXBE_RO)) {
data_byte = rxb_rd8(regs);
if (p != NULL) {
*p++ = data_byte;
}
rlen--;
}
}
return 0;
}
static int qmspi_transceive(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
const struct spi_qmspi_config *cfg = dev->config;
struct spi_qmspi_data *data = dev->data;
QMSPI_Type *regs = cfg->regs;
const struct spi_buf *ptx;
const struct spi_buf *prx;
size_t nb;
uint32_t descr, last_didx;
int err;
spi_context_lock(&data->ctx, false, NULL, NULL, config);
err = qmspi_configure(dev, config);
if (err != 0) {
goto done;
}
spi_context_cs_control(&data->ctx, true);
if (tx_bufs != NULL) {
ptx = tx_bufs->buffers;
nb = tx_bufs->count;
while (nb--) {
err = qmspi_tx(regs, ptx, false);
if (err != 0) {
goto done;
}
ptx++;
}
}
if (rx_bufs != NULL) {
prx = rx_bufs->buffers;
nb = rx_bufs->count;
while (nb--) {
err = qmspi_rx(regs, prx, false);
if (err != 0) {
goto done;
}
prx++;
}
}
/*
* If caller doesn't need CS# held asserted then find the last
* descriptor, set its close flag, and set stop.
*/
if (!(config->operation & SPI_HOLD_ON_CS)) {
/* Get last descriptor from status register */
last_didx = (regs->STS >> MCHP_QMSPI_C_NEXT_DESCR_POS)
& MCHP_QMSPI_C_NEXT_DESCR_MASK0;
descr = descr_rd(regs, last_didx) | MCHP_QMSPI_C_CLOSE;
descr_wr(regs, last_didx, descr);
regs->EXE = MCHP_QMSPI_EXE_STOP;
}
spi_context_cs_control(&data->ctx, false);
done:
spi_context_release(&data->ctx, err);
return err;
}
static int qmspi_transceive_sync(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
return qmspi_transceive(dev, config, tx_bufs, rx_bufs);
}
#ifdef CONFIG_SPI_ASYNC
static int qmspi_transceive_async(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs,
struct k_poll_signal *async)
{
return -ENOTSUP;
}
#endif
static int qmspi_release(const struct device *dev,
const struct spi_config *config)
{
struct spi_qmspi_data *data = dev->data;
const struct spi_qmspi_config *cfg = dev->config;
QMSPI_Type *regs = cfg->regs;
/* Force CS# to de-assert on next unit boundary */
regs->EXE = MCHP_QMSPI_EXE_STOP;
while (regs->STS & MCHP_QMSPI_STS_ACTIVE_RO) {
}
spi_context_unlock_unconditionally(&data->ctx);
return 0;
}
/*
* Initialize QMSPI controller.
* Disable sleep control.
* Disable and clear interrupt status.
* Initialize SPI context.
* QMSPI will be configured and enabled when the transceive API is called.
*/
static int qmspi_init(const struct device *dev)
{
int err;
const struct spi_qmspi_config *cfg = dev->config;
struct spi_qmspi_data *data = dev->data;
QMSPI_Type *regs = cfg->regs;
int ret;
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("QSPI pinctrl setup failed (%d)", ret);
return ret;
}
mchp_pcr_periph_slp_ctrl(PCR_QMSPI, MCHP_PCR_SLEEP_DIS);
regs->MODE = MCHP_QMSPI_M_SRST;
MCHP_GIRQ_CLR_EN(cfg->girq, cfg->girq_pos);
MCHP_GIRQ_SRC_CLR(cfg->girq, cfg->girq_pos);
MCHP_GIRQ_BLK_CLREN(cfg->girq);
NVIC_ClearPendingIRQ(cfg->girq_nvic_direct);
err = spi_context_cs_configure_all(&data->ctx);
if (err < 0) {
return err;
}
spi_context_unlock_unconditionally(&data->ctx);
return 0;
}
static const struct spi_driver_api spi_qmspi_driver_api = {
.transceive = qmspi_transceive_sync,
#ifdef CONFIG_SPI_ASYNC
.transceive_async = qmspi_transceive_async,
#endif
.release = qmspi_release,
};
#define XEC_QMSPI_CS_TIMING_VAL(a, b, c, d) (((a) & 0xFu) \
| (((b) & 0xFu) << 8) \
| (((c) & 0xFu) << 16) \
| (((d) & 0xFu) << 24))
#define XEC_QMSPI_0_CS_TIMING XEC_QMSPI_CS_TIMING_VAL( \
DT_INST_PROP(0, dcsckon), \
DT_INST_PROP(0, dckcsoff), \
DT_INST_PROP(0, dldh), \
DT_INST_PROP(0, dcsda))
#if DT_NODE_HAS_STATUS(DT_INST(0, microchip_xec_qmspi), okay)
PINCTRL_DT_INST_DEFINE(0);
static const struct spi_qmspi_config spi_qmspi_0_config = {
.regs = (QMSPI_Type *)DT_INST_REG_ADDR(0),
.cs_timing = XEC_QMSPI_0_CS_TIMING,
.girq = MCHP_QMSPI_GIRQ_NUM,
.girq_pos = MCHP_QMSPI_GIRQ_POS,
.girq_nvic_direct = MCHP_QMSPI_GIRQ_NVIC_DIRECT,
.irq_pri = DT_INST_IRQ(0, priority),
.chip_sel = DT_INST_PROP(0, chip_select),
.width = DT_INST_PROP(0, lines),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
};
static struct spi_qmspi_data spi_qmspi_0_dev_data = {
SPI_CONTEXT_INIT_LOCK(spi_qmspi_0_dev_data, ctx),
SPI_CONTEXT_INIT_SYNC(spi_qmspi_0_dev_data, ctx),
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(0), ctx)
};
DEVICE_DT_INST_DEFINE(0,
qmspi_init, NULL, &spi_qmspi_0_dev_data,
&spi_qmspi_0_config, POST_KERNEL,
CONFIG_SPI_INIT_PRIORITY, &spi_qmspi_driver_api);
#endif /* DT_NODE_HAS_STATUS(DT_INST(0, microchip_xec_qmspi), okay) */
``` | /content/code_sandbox/drivers/spi/spi_xec_qmspi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,624 |
```c
/*
*
*/
#define DT_DRV_COMPAT gd_gd32_spi
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/spi.h>
#ifdef CONFIG_SPI_GD32_DMA
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/dma/dma_gd32.h>
#endif
#include <gd32_spi.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(spi_gd32);
#include "spi_context.h"
/* SPI error status mask. */
#define SPI_GD32_ERR_MASK (SPI_STAT_RXORERR | SPI_STAT_CONFERR | SPI_STAT_CRCERR)
#define GD32_SPI_PSC_MAX 0x7U
#ifdef CONFIG_SPI_GD32_DMA
enum spi_gd32_dma_direction {
RX = 0,
TX,
NUM_OF_DIRECTION
};
struct spi_gd32_dma_config {
const struct device *dev;
uint32_t channel;
uint32_t config;
uint32_t slot;
uint32_t fifo_threshold;
};
struct spi_gd32_dma_data {
struct dma_config config;
struct dma_block_config block;
uint32_t count;
};
#endif
struct spi_gd32_config {
uint32_t reg;
uint16_t clkid;
struct reset_dt_spec reset;
const struct pinctrl_dev_config *pcfg;
#ifdef CONFIG_SPI_GD32_DMA
const struct spi_gd32_dma_config dma[NUM_OF_DIRECTION];
#endif
#ifdef CONFIG_SPI_GD32_INTERRUPT
void (*irq_configure)();
#endif
};
struct spi_gd32_data {
struct spi_context ctx;
#ifdef CONFIG_SPI_GD32_DMA
struct spi_gd32_dma_data dma[NUM_OF_DIRECTION];
#endif
};
#ifdef CONFIG_SPI_GD32_DMA
static uint32_t dummy_tx;
static uint32_t dummy_rx;
static bool spi_gd32_dma_enabled(const struct device *dev)
{
const struct spi_gd32_config *cfg = dev->config;
if (cfg->dma[TX].dev && cfg->dma[RX].dev) {
return true;
}
return false;
}
static size_t spi_gd32_dma_enabled_num(const struct device *dev)
{
return spi_gd32_dma_enabled(dev) ? 2 : 0;
}
#endif
static int spi_gd32_get_err(const struct spi_gd32_config *cfg)
{
uint32_t stat = SPI_STAT(cfg->reg);
if (stat & SPI_GD32_ERR_MASK) {
LOG_ERR("spi%u error status detected, err = %u",
cfg->reg, stat & (uint32_t)SPI_GD32_ERR_MASK);
return -EIO;
}
return 0;
}
static bool spi_gd32_transfer_ongoing(struct spi_gd32_data *data)
{
return spi_context_tx_on(&data->ctx) ||
spi_context_rx_on(&data->ctx);
}
static int spi_gd32_configure(const struct device *dev,
const struct spi_config *config)
{
struct spi_gd32_data *data = dev->data;
const struct spi_gd32_config *cfg = dev->config;
uint32_t bus_freq;
if (spi_context_configured(&data->ctx, config)) {
return 0;
}
if (SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_SLAVE) {
LOG_ERR("Slave mode not supported");
return -ENOTSUP;
}
SPI_CTL0(cfg->reg) &= ~SPI_CTL0_SPIEN;
SPI_CTL0(cfg->reg) |= SPI_MASTER;
SPI_CTL0(cfg->reg) &= ~SPI_TRANSMODE_BDTRANSMIT;
if (SPI_WORD_SIZE_GET(config->operation) == 8) {
SPI_CTL0(cfg->reg) |= SPI_FRAMESIZE_8BIT;
} else {
SPI_CTL0(cfg->reg) |= SPI_FRAMESIZE_16BIT;
}
/* Reset to hardware NSS mode. */
SPI_CTL0(cfg->reg) &= ~SPI_CTL0_SWNSSEN;
if (spi_cs_is_gpio(config)) {
SPI_CTL0(cfg->reg) |= SPI_CTL0_SWNSSEN;
} else {
/*
* For single master env,
* hardware NSS mode also need to set the NSSDRV bit.
*/
SPI_CTL1(cfg->reg) |= SPI_CTL1_NSSDRV;
}
SPI_CTL0(cfg->reg) &= ~SPI_CTL0_LF;
if (config->operation & SPI_TRANSFER_LSB) {
SPI_CTL0(cfg->reg) |= SPI_CTL0_LF;
}
SPI_CTL0(cfg->reg) &= ~SPI_CTL0_CKPL;
if (config->operation & SPI_MODE_CPOL) {
SPI_CTL0(cfg->reg) |= SPI_CTL0_CKPL;
}
SPI_CTL0(cfg->reg) &= ~SPI_CTL0_CKPH;
if (config->operation & SPI_MODE_CPHA) {
SPI_CTL0(cfg->reg) |= SPI_CTL0_CKPH;
}
(void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&cfg->clkid,
&bus_freq);
for (uint8_t i = 0U; i <= GD32_SPI_PSC_MAX; i++) {
bus_freq = bus_freq >> 1U;
if (bus_freq <= config->frequency) {
SPI_CTL0(cfg->reg) &= ~SPI_CTL0_PSC;
SPI_CTL0(cfg->reg) |= CTL0_PSC(i);
break;
}
}
data->ctx.config = config;
return 0;
}
static int spi_gd32_frame_exchange(const struct device *dev)
{
struct spi_gd32_data *data = dev->data;
const struct spi_gd32_config *cfg = dev->config;
struct spi_context *ctx = &data->ctx;
uint16_t tx_frame = 0U, rx_frame = 0U;
while ((SPI_STAT(cfg->reg) & SPI_STAT_TBE) == 0) {
/* NOP */
}
if (SPI_WORD_SIZE_GET(ctx->config->operation) == 8) {
if (spi_context_tx_buf_on(ctx)) {
tx_frame = UNALIGNED_GET((uint8_t *)(data->ctx.tx_buf));
}
/* For 8 bits mode, spi will forced SPI_DATA[15:8] to 0. */
SPI_DATA(cfg->reg) = tx_frame;
spi_context_update_tx(ctx, 1, 1);
} else {
if (spi_context_tx_buf_on(ctx)) {
tx_frame = UNALIGNED_GET((uint8_t *)(data->ctx.tx_buf));
}
SPI_DATA(cfg->reg) = tx_frame;
spi_context_update_tx(ctx, 2, 1);
}
while ((SPI_STAT(cfg->reg) & SPI_STAT_RBNE) == 0) {
/* NOP */
}
if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
/* For 8 bits mode, spi will forced SPI_DATA[15:8] to 0. */
rx_frame = SPI_DATA(cfg->reg);
if (spi_context_rx_buf_on(ctx)) {
UNALIGNED_PUT(rx_frame, (uint8_t *)data->ctx.rx_buf);
}
spi_context_update_rx(ctx, 1, 1);
} else {
rx_frame = SPI_DATA(cfg->reg);
if (spi_context_rx_buf_on(ctx)) {
UNALIGNED_PUT(rx_frame, (uint16_t *)data->ctx.rx_buf);
}
spi_context_update_rx(ctx, 2, 1);
}
return spi_gd32_get_err(cfg);
}
#ifdef CONFIG_SPI_GD32_DMA
static void spi_gd32_dma_callback(const struct device *dma_dev, void *arg,
uint32_t channel, int status);
static uint32_t spi_gd32_dma_setup(const struct device *dev, const uint32_t dir)
{
const struct spi_gd32_config *cfg = dev->config;
struct spi_gd32_data *data = dev->data;
struct dma_config *dma_cfg = &data->dma[dir].config;
struct dma_block_config *block_cfg = &data->dma[dir].block;
const struct spi_gd32_dma_config *dma = &cfg->dma[dir];
int ret;
memset(dma_cfg, 0, sizeof(struct dma_config));
memset(block_cfg, 0, sizeof(struct dma_block_config));
dma_cfg->source_burst_length = 1;
dma_cfg->dest_burst_length = 1;
dma_cfg->user_data = (void *)dev;
dma_cfg->dma_callback = spi_gd32_dma_callback;
dma_cfg->block_count = 1U;
dma_cfg->head_block = block_cfg;
dma_cfg->dma_slot = cfg->dma[dir].slot;
dma_cfg->channel_priority =
GD32_DMA_CONFIG_PRIORITY(cfg->dma[dir].config);
dma_cfg->channel_direction =
dir == TX ? MEMORY_TO_PERIPHERAL : PERIPHERAL_TO_MEMORY;
if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
dma_cfg->source_data_size = 1;
dma_cfg->dest_data_size = 1;
} else {
dma_cfg->source_data_size = 2;
dma_cfg->dest_data_size = 2;
}
block_cfg->block_size = spi_context_max_continuous_chunk(&data->ctx);
if (dir == TX) {
block_cfg->dest_address = (uint32_t)&SPI_DATA(cfg->reg);
block_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
if (spi_context_tx_buf_on(&data->ctx)) {
block_cfg->source_address = (uint32_t)data->ctx.tx_buf;
block_cfg->source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
} else {
block_cfg->source_address = (uint32_t)&dummy_tx;
block_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
}
}
if (dir == RX) {
block_cfg->source_address = (uint32_t)&SPI_DATA(cfg->reg);
block_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
if (spi_context_rx_buf_on(&data->ctx)) {
block_cfg->dest_address = (uint32_t)data->ctx.rx_buf;
block_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
} else {
block_cfg->dest_address = (uint32_t)&dummy_rx;
block_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
}
}
ret = dma_config(dma->dev, dma->channel, dma_cfg);
if (ret < 0) {
LOG_ERR("dma_config %p failed %d\n", dma->dev, ret);
return ret;
}
ret = dma_start(dma->dev, dma->channel);
if (ret < 0) {
LOG_ERR("dma_start %p failed %d\n", dma->dev, ret);
return ret;
}
return 0;
}
static int spi_gd32_start_dma_transceive(const struct device *dev)
{
const struct spi_gd32_config *cfg = dev->config;
struct spi_gd32_data *data = dev->data;
const size_t chunk_len = spi_context_max_continuous_chunk(&data->ctx);
struct dma_status stat;
int ret = 0;
for (size_t i = 0; i < spi_gd32_dma_enabled_num(dev); i++) {
dma_get_status(cfg->dma[i].dev, cfg->dma[i].channel, &stat);
if ((chunk_len != data->dma[i].count) && !stat.busy) {
ret = spi_gd32_dma_setup(dev, i);
if (ret < 0) {
goto on_error;
}
}
}
SPI_CTL1(cfg->reg) |= (SPI_CTL1_DMATEN | SPI_CTL1_DMAREN);
on_error:
if (ret < 0) {
for (size_t i = 0; i < spi_gd32_dma_enabled_num(dev); i++) {
dma_stop(cfg->dma[i].dev, cfg->dma[i].channel);
}
}
return ret;
}
#endif
static int spi_gd32_transceive_impl(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs,
spi_callback_t cb,
void *userdata)
{
struct spi_gd32_data *data = dev->data;
const struct spi_gd32_config *cfg = dev->config;
int ret;
spi_context_lock(&data->ctx, (cb != NULL), cb, userdata, config);
ret = spi_gd32_configure(dev, config);
if (ret < 0) {
goto error;
}
SPI_CTL0(cfg->reg) |= SPI_CTL0_SPIEN;
spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
spi_context_cs_control(&data->ctx, true);
#ifdef CONFIG_SPI_GD32_INTERRUPT
#ifdef CONFIG_SPI_GD32_DMA
if (spi_gd32_dma_enabled(dev)) {
for (size_t i = 0; i < ARRAY_SIZE(data->dma); i++) {
data->dma[i].count = 0;
}
ret = spi_gd32_start_dma_transceive(dev);
if (ret < 0) {
goto dma_error;
}
} else
#endif
{
SPI_STAT(cfg->reg) &=
~(SPI_STAT_RBNE | SPI_STAT_TBE | SPI_GD32_ERR_MASK);
SPI_CTL1(cfg->reg) |=
(SPI_CTL1_RBNEIE | SPI_CTL1_TBEIE | SPI_CTL1_ERRIE);
}
ret = spi_context_wait_for_completion(&data->ctx);
#else
do {
ret = spi_gd32_frame_exchange(dev);
if (ret < 0) {
break;
}
} while (spi_gd32_transfer_ongoing(data));
#ifdef CONFIG_SPI_ASYNC
spi_context_complete(&data->ctx, dev, ret);
#endif
#endif
while (!(SPI_STAT(cfg->reg) & SPI_STAT_TBE) ||
(SPI_STAT(cfg->reg) & SPI_STAT_TRANS)) {
/* Wait until last frame transfer complete. */
}
#ifdef CONFIG_SPI_GD32_DMA
dma_error:
SPI_CTL1(cfg->reg) &=
~(SPI_CTL1_DMATEN | SPI_CTL1_DMAREN);
#endif
spi_context_cs_control(&data->ctx, false);
SPI_CTL0(cfg->reg) &=
~(SPI_CTL0_SPIEN);
error:
spi_context_release(&data->ctx, ret);
return ret;
}
static int spi_gd32_transceive(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
return spi_gd32_transceive_impl(dev, config, tx_bufs, rx_bufs, NULL, NULL);
}
#ifdef CONFIG_SPI_ASYNC
static int spi_gd32_transceive_async(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs,
spi_callback_t cb,
void *userdata)
{
return spi_gd32_transceive_impl(dev, config, tx_bufs, rx_bufs, cb, userdata);
}
#endif
#ifdef CONFIG_SPI_GD32_INTERRUPT
static void spi_gd32_complete(const struct device *dev, int status)
{
struct spi_gd32_data *data = dev->data;
const struct spi_gd32_config *cfg = dev->config;
SPI_CTL1(cfg->reg) &=
~(SPI_CTL1_RBNEIE | SPI_CTL1_TBEIE | SPI_CTL1_ERRIE);
#ifdef CONFIG_SPI_GD32_DMA
for (size_t i = 0; i < spi_gd32_dma_enabled_num(dev); i++) {
dma_stop(cfg->dma[i].dev, cfg->dma[i].channel);
}
#endif
spi_context_complete(&data->ctx, dev, status);
}
static void spi_gd32_isr(struct device *dev)
{
const struct spi_gd32_config *cfg = dev->config;
struct spi_gd32_data *data = dev->data;
int err = 0;
err = spi_gd32_get_err(cfg);
if (err) {
spi_gd32_complete(dev, err);
return;
}
if (spi_gd32_transfer_ongoing(data)) {
err = spi_gd32_frame_exchange(dev);
}
if (err || !spi_gd32_transfer_ongoing(data)) {
spi_gd32_complete(dev, err);
}
}
#endif /* SPI_GD32_INTERRUPT */
#ifdef CONFIG_SPI_GD32_DMA
static bool spi_gd32_chunk_transfer_finished(const struct device *dev)
{
struct spi_gd32_data *data = dev->data;
struct spi_gd32_dma_data *dma = data->dma;
const size_t chunk_len = spi_context_max_continuous_chunk(&data->ctx);
return (MIN(dma[TX].count, dma[RX].count) >= chunk_len);
}
static void spi_gd32_dma_callback(const struct device *dma_dev, void *arg,
uint32_t channel, int status)
{
const struct device *dev = (const struct device *)arg;
const struct spi_gd32_config *cfg = dev->config;
struct spi_gd32_data *data = dev->data;
const size_t chunk_len = spi_context_max_continuous_chunk(&data->ctx);
int err = 0;
if (status < 0) {
LOG_ERR("dma:%p ch:%d callback gets error: %d", dma_dev, channel,
status);
spi_gd32_complete(dev, status);
return;
}
for (size_t i = 0; i < ARRAY_SIZE(cfg->dma); i++) {
if (dma_dev == cfg->dma[i].dev &&
channel == cfg->dma[i].channel) {
data->dma[i].count += chunk_len;
}
}
/* Check transfer finished.
* The transmission of this chunk is complete if both the dma[TX].count
* and the dma[RX].count reach greater than or equal to the chunk_len.
* chunk_len is zero here means the transfer is already complete.
*/
if (spi_gd32_chunk_transfer_finished(dev)) {
if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
spi_context_update_tx(&data->ctx, 1, chunk_len);
spi_context_update_rx(&data->ctx, 1, chunk_len);
} else {
spi_context_update_tx(&data->ctx, 2, chunk_len);
spi_context_update_rx(&data->ctx, 2, chunk_len);
}
if (spi_gd32_transfer_ongoing(data)) {
/* Next chunk is available, reset the count and
* continue processing
*/
data->dma[TX].count = 0;
data->dma[RX].count = 0;
} else {
/* All data is processed, complete the process */
spi_context_complete(&data->ctx, dev, 0);
return;
}
}
err = spi_gd32_start_dma_transceive(dev);
if (err) {
spi_gd32_complete(dev, err);
}
}
#endif /* DMA */
static int spi_gd32_release(const struct device *dev,
const struct spi_config *config)
{
struct spi_gd32_data *data = dev->data;
spi_context_unlock_unconditionally(&data->ctx);
return 0;
}
static const struct spi_driver_api spi_gd32_driver_api = {
.transceive = spi_gd32_transceive,
#ifdef CONFIG_SPI_ASYNC
.transceive_async = spi_gd32_transceive_async,
#endif
.release = spi_gd32_release
};
int spi_gd32_init(const struct device *dev)
{
struct spi_gd32_data *data = dev->data;
const struct spi_gd32_config *cfg = dev->config;
int ret;
#ifdef CONFIG_SPI_GD32_DMA
uint32_t ch_filter;
#endif
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret) {
LOG_ERR("Failed to apply pinctrl state");
return ret;
}
#ifdef CONFIG_SPI_GD32_DMA
if ((cfg->dma[RX].dev && !cfg->dma[TX].dev) ||
(cfg->dma[TX].dev && !cfg->dma[RX].dev)) {
LOG_ERR("DMA must be enabled for both TX and RX channels");
return -ENODEV;
}
for (size_t i = 0; i < spi_gd32_dma_enabled_num(dev); i++) {
if (!device_is_ready(cfg->dma[i].dev)) {
LOG_ERR("DMA %s not ready", cfg->dma[i].dev->name);
return -ENODEV;
}
ch_filter = BIT(cfg->dma[i].channel);
ret = dma_request_channel(cfg->dma[i].dev, &ch_filter);
if (ret < 0) {
LOG_ERR("dma_request_channel failed %d", ret);
return ret;
}
}
#endif
ret = spi_context_cs_configure_all(&data->ctx);
if (ret < 0) {
return ret;
}
#ifdef CONFIG_SPI_GD32_INTERRUPT
cfg->irq_configure(dev);
#endif
spi_context_unlock_unconditionally(&data->ctx);
return 0;
}
#define DMA_INITIALIZER(idx, dir) \
{ \
.dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(idx, dir)), \
.channel = DT_INST_DMAS_CELL_BY_NAME(idx, dir, channel), \
.slot = COND_CODE_1( \
DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1), \
(DT_INST_DMAS_CELL_BY_NAME(idx, dir, slot)), (0)), \
.config = DT_INST_DMAS_CELL_BY_NAME(idx, dir, config), \
.fifo_threshold = COND_CODE_1( \
DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1), \
(DT_INST_DMAS_CELL_BY_NAME(idx, dir, fifo_threshold)), \
(0)), \
}
#define DMAS_DECL(idx) \
{ \
COND_CODE_1(DT_INST_DMAS_HAS_NAME(idx, rx), \
(DMA_INITIALIZER(idx, rx)), ({0})), \
COND_CODE_1(DT_INST_DMAS_HAS_NAME(idx, tx), \
(DMA_INITIALIZER(idx, tx)), ({0})), \
}
#define GD32_IRQ_CONFIGURE(idx) \
static void spi_gd32_irq_configure_##idx(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), \
spi_gd32_isr, \
DEVICE_DT_INST_GET(idx), 0); \
irq_enable(DT_INST_IRQN(idx)); \
}
#define GD32_SPI_INIT(idx) \
PINCTRL_DT_INST_DEFINE(idx); \
IF_ENABLED(CONFIG_SPI_GD32_INTERRUPT, (GD32_IRQ_CONFIGURE(idx))); \
static struct spi_gd32_data spi_gd32_data_##idx = { \
SPI_CONTEXT_INIT_LOCK(spi_gd32_data_##idx, ctx), \
SPI_CONTEXT_INIT_SYNC(spi_gd32_data_##idx, ctx), \
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(idx), ctx) }; \
static struct spi_gd32_config spi_gd32_config_##idx = { \
.reg = DT_INST_REG_ADDR(idx), \
.clkid = DT_INST_CLOCKS_CELL(idx, id), \
.reset = RESET_DT_SPEC_INST_GET(idx), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
IF_ENABLED(CONFIG_SPI_GD32_DMA, (.dma = DMAS_DECL(idx),)) \
IF_ENABLED(CONFIG_SPI_GD32_INTERRUPT, \
(.irq_configure = spi_gd32_irq_configure_##idx)) }; \
DEVICE_DT_INST_DEFINE(idx, spi_gd32_init, NULL, \
&spi_gd32_data_##idx, &spi_gd32_config_##idx, \
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_gd32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GD32_SPI_INIT)
``` | /content/code_sandbox/drivers/spi/spi_gd32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,446 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_SPI_SPI_NXP_S32_H_
#define ZEPHYR_DRIVERS_SPI_SPI_NXP_S32_H_
#include <zephyr/drivers/spi.h>
#include <zephyr/logging/log.h>
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
LOG_MODULE_REGISTER(spi_nxp_s32);
#include "spi_context.h"
#include <Spi_Ip.h>
#define SPI_NXP_S32_NUM_PRESCALER 4U
#define SPI_NXP_S32_NUM_SCALER 16U
/* Modified SPI transfer format is not supported,
* the maximum baudrate is 25Mhz.
*/
#define SPI_NXP_S32_MIN_FREQ 100000U
#define SPI_NXP_S32_MAX_FREQ 25000000U
#define SPI_NXP_S32_BYTE_PER_FRAME(frame_size) \
(frame_size <= 8U) ? 1U : ((frame_size <= 16U) ? 2U : 4U)
#define SPI_NXP_S32_MAX_BYTES_PER_PACKAGE(bytes_per_frame) \
((UINT16_MAX / bytes_per_frame) * bytes_per_frame)
struct spi_nxp_s32_baudrate_param {
uint8_t scaler;
uint8_t prescaler;
uint32_t frequency;
};
struct spi_nxp_s32_data {
uint8_t bytes_per_frame;
uint32_t transfer_len;
struct spi_context ctx;
Spi_Ip_ExternalDeviceType transfer_cfg;
Spi_Ip_DeviceParamsType transfer_params;
};
struct spi_nxp_s32_config {
uint8_t num_cs;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
uint32_t sck_cs_delay;
uint32_t cs_sck_delay;
uint32_t cs_cs_delay;
Spi_Ip_ConfigType *spi_hw_cfg;
const struct pinctrl_dev_config *pincfg;
#ifdef CONFIG_NXP_S32_SPI_INTERRUPT
Spi_Ip_CallbackType cb;
void (*irq_config_func)(const struct device *dev);
#endif /* CONFIG_NXP_S32_SPI_INTERRUPT */
};
#endif /* ZEPHYR_DRIVERS_SPI_SPI_NXP_S32_H_ */
``` | /content/code_sandbox/drivers/spi/spi_nxp_s32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 446 |
```unknown
# Ambiq SDK SPI
#
#
#
menuconfig SPI_AMBIQ
bool "AMBIQ SPI driver"
default y
depends on DT_HAS_AMBIQ_SPI_ENABLED
select GPIO
select AMBIQ_HAL
select AMBIQ_HAL_USE_SPI
help
Enable driver for Ambiq SPI.
if SPI_AMBIQ
config SPI_AMBIQ_DMA
bool "AMBIQ APOLLO SPI DMA Support"
depends on SPI_AMBIQ
help
Enable DMA for Ambiq SPI.
config SPI_DMA_TCB_BUFFER_SIZE
int "DMA Transfer Control Buffer size in words."
default 1024
depends on SPI_AMBIQ_DMA
help
DMA Transfer Control Buffer size in words
endif # SPI_AMBIQ
config SPI_AMBIQ_BLEIF
bool "AMBIQ SPI-BLEIF driver"
default y
depends on DT_HAS_AMBIQ_SPI_BLEIF_ENABLED
select AMBIQ_HAL
select AMBIQ_HAL_USE_BLEIF
help
Enable driver for Ambiq Apollox Blue SOC (e.g. Apollo3 Blue)
which uses internal designed BLEIF module (different from the
general IOM module) for SPI transceiver. It is always used for
the Bluetooth HCI communication.
if SPI_AMBIQ_BLEIF
config SPI_AMBIQ_BLEIF_TIMING_TRACE
bool "Ambiq SPI-BLEIF timing trace"
help
The pins for the SPI transceiver are not exposed from the chips
and no need for user to confiugre them. But the chips design the
configurable BLEIF timing observation functions on other exposed
pins. The user can enable it to configure the pins for timing
trace purpose.
endif # SPI_AMBIQ_BLEIF
``` | /content/code_sandbox/drivers/spi/Kconfig.ambiq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 370 |
```c
/*
*
*/
#define DT_DRV_COMPAT telink_b91_spi
/* Redefine 'spi_read' and 'spi_write' functions names from HAL */
#define spi_read hal_spi_read
#define spi_write hal_spi_write
#include "spi.c"
#undef spi_read
#undef spi_write
#include "clock.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_telink);
#include <zephyr/drivers/spi.h>
#include "spi_context.h"
#include <zephyr/drivers/pinctrl.h>
#define CHIP_SELECT_COUNT 3u
#define SPI_WORD_SIZE 8u
#define SPI_WR_RD_CHUNK_SIZE_MAX 16u
/* SPI configuration structure */
struct spi_b91_cfg {
uint8_t peripheral_id;
gpio_pin_e cs_pin[CHIP_SELECT_COUNT];
const struct pinctrl_dev_config *pcfg;
};
#define SPI_CFG(dev) ((struct spi_b91_cfg *) ((dev)->config))
/* SPI data structure */
struct spi_b91_data {
struct spi_context ctx;
};
#define SPI_DATA(dev) ((struct spi_b91_data *) ((dev)->data))
/* disable hardware cs flow control */
static void spi_b91_hw_cs_disable(const struct spi_b91_cfg *config)
{
gpio_pin_e pin;
/* loop through all cs pins (cs0..cs2) */
for (int i = 0; i < CHIP_SELECT_COUNT; i++) {
/* get CS pin defined in device tree */
pin = config->cs_pin[i];
/* if CS pin is defined in device tree */
if (pin != 0) {
if (config->peripheral_id == PSPI_MODULE) {
/* disable CS pin for PSPI */
pspi_cs_pin_dis(pin);
} else {
/* disable CS pin for MSPI */
hspi_cs_pin_dis(pin);
}
}
}
}
/* config cs flow control: hardware or software */
static bool spi_b91_config_cs(const struct device *dev,
const struct spi_config *config)
{
pspi_csn_pin_def_e cs_pin = 0;
const struct spi_b91_cfg *b91_config = SPI_CFG(dev);
/* software flow control */
if (spi_cs_is_gpio(config)) {
/* disable all hardware CS pins */
spi_b91_hw_cs_disable(b91_config);
return true;
}
/* hardware flow control */
/* check for correct slave id */
if (config->slave >= CHIP_SELECT_COUNT) {
LOG_ERR("Slave %d not supported (max. %d)", config->slave, CHIP_SELECT_COUNT - 1);
return false;
}
/* loop through all cs pins: cs0, cs1 and cs2 */
for (int cs_id = 0; cs_id < CHIP_SELECT_COUNT; cs_id++) {
/* get cs pin defined in device tree */
cs_pin = b91_config->cs_pin[cs_id];
/* if cs pin is not defined for the selected slave, return error */
if ((cs_pin == 0) && (cs_id == config->slave)) {
LOG_ERR("cs%d-pin is not defined in device tree", config->slave);
return false;
}
/* disable cs pin if it is defined and is not requested */
if ((cs_pin != 0) && (cs_id != config->slave)) {
if (b91_config->peripheral_id == PSPI_MODULE) {
pspi_cs_pin_dis(cs_pin);
} else {
hspi_cs_pin_dis(cs_pin);
}
}
/* enable cs pin if it is defined and is requested */
if ((cs_pin != 0) && (cs_id == config->slave)) {
if (b91_config->peripheral_id == PSPI_MODULE) {
pspi_set_pin_mux(cs_pin);
pspi_cs_pin_en(cs_pin);
} else {
hspi_set_pin_mux(cs_pin);
hspi_cs_pin_en(cs_pin);
}
}
}
return true;
}
/* get spi transaction length */
static uint32_t spi_b91_get_txrx_len(const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
uint32_t len_tx = 0;
uint32_t len_rx = 0;
const struct spi_buf *tx_buf = tx_bufs->buffers;
const struct spi_buf *rx_buf = rx_bufs->buffers;
/* calculate tx len */
for (int i = 0; i < tx_bufs->count; i++) {
len_tx += tx_buf->len;
tx_buf++;
}
/* calculate rx len */
for (int i = 0; i < rx_bufs->count; i++) {
len_rx += rx_buf->len;
rx_buf++;
}
return MAX(len_tx, len_rx);
}
/* process tx data */
_attribute_ram_code_sec_
static void spi_b91_tx(uint8_t peripheral_id, struct spi_context *ctx, uint8_t len)
{
uint8_t tx;
for (int i = 0; i < len; i++) {
if (spi_context_tx_buf_on(ctx)) {
tx = *(uint8_t *)(ctx->tx_buf);
} else {
tx = 0;
}
spi_context_update_tx(ctx, 1, 1);
while (reg_spi_fifo_state(peripheral_id) & FLD_SPI_TXF_FULL) {
};
reg_spi_wr_rd_data(peripheral_id, i % 4) = tx;
}
}
/* process rx data */
_attribute_ram_code_sec_
static void spi_b91_rx(uint8_t peripheral_id, struct spi_context *ctx, uint8_t len)
{
uint8_t rx = 0;
for (int i = 0; i < len; i++) {
while (reg_spi_fifo_state(peripheral_id) & FLD_SPI_RXF_EMPTY) {
};
rx = reg_spi_wr_rd_data(peripheral_id, i % 4);
if (spi_context_rx_buf_on(ctx)) {
*ctx->rx_buf = rx;
}
spi_context_update_rx(ctx, 1, 1);
}
}
/* SPI transceive internal */
_attribute_ram_code_sec_
static void spi_b91_txrx(const struct device *dev, uint32_t len)
{
unsigned int chunk_size = SPI_WR_RD_CHUNK_SIZE_MAX;
struct spi_b91_cfg *cfg = SPI_CFG(dev);
struct spi_context *ctx = &SPI_DATA(dev)->ctx;
/* prepare SPI module */
spi_set_transmode(cfg->peripheral_id, SPI_MODE_WRITE_AND_READ);
spi_set_cmd(cfg->peripheral_id, 0);
spi_tx_cnt(cfg->peripheral_id, len);
spi_rx_cnt(cfg->peripheral_id, len);
/* write and read bytes in chunks */
for (int i = 0; i < len; i = i + chunk_size) {
/* check for tail */
if (chunk_size > (len - i)) {
chunk_size = len - i;
}
/* write bytes */
spi_b91_tx(cfg->peripheral_id, ctx, chunk_size);
/* read bytes */
if (len <= SPI_WR_RD_CHUNK_SIZE_MAX) {
/* read all bytes if len is less than chunk size */
spi_b91_rx(cfg->peripheral_id, ctx, chunk_size);
} else if (i == 0) {
/* head, read 1 byte less than is sent */
spi_b91_rx(cfg->peripheral_id, ctx, chunk_size - 1);
} else if ((len - i) > SPI_WR_RD_CHUNK_SIZE_MAX) {
/* body, read so many bytes as is sent*/
spi_b91_rx(cfg->peripheral_id, ctx, chunk_size);
} else {
/* tail, read the rest bytes */
spi_b91_rx(cfg->peripheral_id, ctx, chunk_size + 1);
}
/* clear TX and RX fifo */
BM_SET(reg_spi_fifo_state(cfg->peripheral_id), FLD_SPI_TXF_CLR);
BM_SET(reg_spi_fifo_state(cfg->peripheral_id), FLD_SPI_RXF_CLR);
}
/* wait for SPI is ready */
while (spi_is_busy(cfg->peripheral_id)) {
};
/* context complete */
spi_context_complete(ctx, dev, 0);
}
/* Check for supported configuration */
static bool spi_b91_is_config_supported(const struct spi_config *config,
struct spi_b91_cfg *b91_config)
{
if (config->operation & SPI_HALF_DUPLEX) {
LOG_ERR("Half-duplex not supported");
return false;
}
/* check for loop back */
if (config->operation & SPI_MODE_LOOP) {
LOG_ERR("Loop back mode not supported");
return false;
}
/* check for transfer LSB first */
if (config->operation & SPI_TRANSFER_LSB) {
LOG_ERR("LSB first not supported");
return false;
}
/* check word size */
if (SPI_WORD_SIZE_GET(config->operation) != SPI_WORD_SIZE) {
LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
return false;
}
/* check for CS active high */
if (config->operation & SPI_CS_ACTIVE_HIGH) {
LOG_ERR("CS active high not supported for HW flow control");
return false;
}
/* check for lines configuration */
if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES)) {
if ((config->operation & SPI_LINES_MASK) == SPI_LINES_OCTAL) {
LOG_ERR("SPI lines Octal is not supported");
return false;
} else if (((config->operation & SPI_LINES_MASK) ==
SPI_LINES_QUAD) &&
(b91_config->peripheral_id == PSPI_MODULE)) {
LOG_ERR("SPI lines Quad is not supported by PSPI");
return false;
}
}
/* check for slave configuration */
if (SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_SLAVE) {
LOG_ERR("SPI Slave is not implemented");
return -ENOTSUP;
}
return true;
}
/* SPI configuration */
static int spi_b91_config(const struct device *dev,
const struct spi_config *config)
{
int status = 0;
spi_mode_type_e mode = SPI_MODE0;
struct spi_b91_cfg *b91_config = SPI_CFG(dev);
struct spi_b91_data *b91_data = SPI_DATA(dev);
uint8_t clk_src = b91_config->peripheral_id == PSPI_MODULE ? sys_clk.pclk : sys_clk.hclk;
/* check for unsupported configuration */
if (!spi_b91_is_config_supported(config, b91_config)) {
return -ENOTSUP;
}
/* config slave selection (CS): hw or sw */
if (!spi_b91_config_cs(dev, config)) {
return -ENOTSUP;
}
/* get SPI mode */
if (((config->operation & SPI_MODE_CPHA) == 0) &&
((config->operation & SPI_MODE_CPOL) == 0)) {
mode = SPI_MODE0;
} else if (((config->operation & SPI_MODE_CPHA) == 0) &&
((config->operation & SPI_MODE_CPOL) == SPI_MODE_CPOL)) {
mode = SPI_MODE1;
} else if (((config->operation & SPI_MODE_CPHA) == SPI_MODE_CPHA) &&
((config->operation & SPI_MODE_CPOL) == 0)) {
mode = SPI_MODE2;
} else if (((config->operation & SPI_MODE_CPHA) == SPI_MODE_CPHA) &&
((config->operation & SPI_MODE_CPOL) == SPI_MODE_CPOL)) {
mode = SPI_MODE3;
}
/* init SPI master */
spi_master_init(b91_config->peripheral_id,
clk_src * 1000000 / (2 * config->frequency) - 1, mode);
spi_master_config(b91_config->peripheral_id, SPI_NOMAL);
/* set lines configuration */
if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES)) {
uint32_t lines = config->operation & SPI_LINES_MASK;
if (lines == SPI_LINES_SINGLE) {
spi_set_io_mode(b91_config->peripheral_id,
SPI_SINGLE_MODE);
} else if (lines == SPI_LINES_DUAL) {
spi_set_io_mode(b91_config->peripheral_id,
SPI_DUAL_MODE);
} else if (lines == SPI_LINES_QUAD) {
spi_set_io_mode(b91_config->peripheral_id,
HSPI_QUAD_MODE);
}
}
/* configure pins */
status = pinctrl_apply_state(b91_config->pcfg, PINCTRL_STATE_DEFAULT);
if (status < 0) {
LOG_ERR("Failed to configure SPI pins");
return status;
}
/* save context config */
b91_data->ctx.config = config;
return 0;
}
/* API implementation: init */
static int spi_b91_init(const struct device *dev)
{
int err;
struct spi_b91_data *data = SPI_DATA(dev);
err = spi_context_cs_configure_all(&data->ctx);
if (err < 0) {
return err;
}
spi_context_unlock_unconditionally(&data->ctx);
return 0;
}
/* API implementation: transceive */
static int spi_b91_transceive(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
int status = 0;
struct spi_b91_data *data = SPI_DATA(dev);
uint32_t txrx_len = spi_b91_get_txrx_len(tx_bufs, rx_bufs);
/* set configuration */
status = spi_b91_config(dev, config);
if (status) {
return status;
}
/* context setup */
spi_context_lock(&data->ctx, false, NULL, NULL, config);
spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
/* if cs is defined: software cs control, set active true */
if (spi_cs_is_gpio(config)) {
spi_context_cs_control(&data->ctx, true);
}
/* transceive data */
spi_b91_txrx(dev, txrx_len);
/* if cs is defined: software cs control, set active false */
if (spi_cs_is_gpio(config)) {
spi_context_cs_control(&data->ctx, false);
}
/* release context */
status = spi_context_wait_for_completion(&data->ctx);
spi_context_release(&data->ctx, status);
return status;
}
#ifdef CONFIG_SPI_ASYNC
/* API implementation: transceive_async */
static int spi_b91_transceive_async(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs,
spi_callback_t cb,
void *userdata)
{
ARG_UNUSED(dev);
ARG_UNUSED(config);
ARG_UNUSED(tx_bufs);
ARG_UNUSED(rx_bufs);
ARG_UNUSED(cb);
ARG_UNUSED(userdata);
return -ENOTSUP;
}
#endif /* CONFIG_SPI_ASYNC */
/* API implementation: release */
static int spi_b91_release(const struct device *dev,
const struct spi_config *config)
{
struct spi_b91_data *data = SPI_DATA(dev);
if (!spi_context_configured(&data->ctx, config)) {
return -EINVAL;
}
spi_context_unlock_unconditionally(&data->ctx);
return 0;
}
/* SPI driver APIs structure */
static const struct spi_driver_api spi_b91_api = {
.transceive = spi_b91_transceive,
.release = spi_b91_release,
#ifdef CONFIG_SPI_ASYNC
.transceive_async = spi_b91_transceive_async,
#endif /* CONFIG_SPI_ASYNC */
};
/* SPI driver registration */
#define SPI_B91_INIT(inst) \
\
PINCTRL_DT_INST_DEFINE(inst); \
\
static struct spi_b91_data spi_b91_data_##inst = { \
SPI_CONTEXT_INIT_LOCK(spi_b91_data_##inst, ctx), \
SPI_CONTEXT_INIT_SYNC(spi_b91_data_##inst, ctx), \
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(inst), ctx) \
}; \
\
static struct spi_b91_cfg spi_b91_cfg_##inst = { \
.peripheral_id = DT_INST_ENUM_IDX(inst, peripheral_id), \
.cs_pin[0] = DT_INST_STRING_TOKEN(inst, cs0_pin), \
.cs_pin[1] = DT_INST_STRING_TOKEN(inst, cs1_pin), \
.cs_pin[2] = DT_INST_STRING_TOKEN(inst, cs2_pin), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, spi_b91_init, \
NULL, \
&spi_b91_data_##inst, \
&spi_b91_cfg_##inst, \
POST_KERNEL, \
CONFIG_SPI_INIT_PRIORITY, \
&spi_b91_api);
DT_INST_FOREACH_STATUS_OKAY(SPI_B91_INIT)
``` | /content/code_sandbox/drivers/spi/spi_b91.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,707 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_mpfs_spi
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(mss_spi, CONFIG_SPI_LOG_LEVEL);
#include "spi_context.h"
/* MSS SPI Register offsets */
#define MSS_SPI_REG_CONTROL (0x00)
#define MSS_SPI_REG_TXRXDF_SIZE (0x04)
#define MSS_SPI_REG_STATUS (0x08)
#define MSS_SPI_REG_INT_CLEAR (0x0c)
#define MSS_SPI_REG_RX_DATA (0x10)
#define MSS_SPI_REG_TX_DATA (0x14)
#define MSS_SPI_REG_CLK_GEN (0x18)
#define MSS_SPI_REG_SS (0x1c)
#define MSS_SPI_REG_MIS (0x20)
#define MSS_SPI_REG_RIS (0x24)
#define MSS_SPI_REG_CONTROL2 (0x28)
#define MSS_SPI_REG_COMMAND (0x2c)
#define MSS_SPI_REG_PKTSIZE (0x30)
#define MSS_SPI_REG_CMD_SIZE (0x34)
#define MSS_SPI_REG_HWSTATUS (0x38)
#define MSS_SPI_REG_FRAMESUP (0x50)
/* SPICR bit definitions */
#define MSS_SPI_CONTROL_ENABLE BIT(0)
#define MSS_SPI_CONTROL_MASTER BIT(1)
#define MSS_SPI_CONTROL_PROTO_MSK BIT(2)
#define MSS_SPI_CONTROL_PROTO_MOTO (0 << 2)
#define MSS_SPI_CONTROL_RX_DATA_INT BIT(4)
#define MSS_SPI_CONTROL_TX_DATA_INT BIT(5)
#define MSS_SPI_CONTROL_RX_OVER_INT BIT(6)
#define MSS_SPI_CONTROL_TX_UNDER_INT BIT(7)
#define MSS_SPI_CONTROL_CNT_MSK (0xffff << 8)
#define MSS_SPI_CONTROL_CNT_SHF (8)
#define MSS_SPI_CONTROL_SPO BIT(24)
#define MSS_SPI_CONTROL_SPH BIT(25)
#define MSS_SPI_CONTROL_SPS BIT(26)
#define MSS_SPI_CONTROL_FRAMEURUN BIT(27)
#define MSS_SPI_CONTROL_CLKMODE BIT(28)
#define MSS_SPI_CONTROL_BIGFIFO BIT(29)
#define MSS_SPI_CONTROL_OENOFF BIT(30)
#define MSS_SPI_CONTROL_RESET BIT(31)
/* SPIFRAMESIZE bit definitions */
#define MSS_SPI_FRAMESIZE_DEFAULT (8)
/* SPISS bit definitions */
#define MSS_SPI_SSEL_MASK (0xff)
#define MSS_SPI_DIRECT (0x100)
#define MSS_SPI_SSELOUT (0x200)
#define MSS_SPI_MIN_SLAVE (0)
#define MSS_SPI_MAX_SLAVE (7)
/* SPIST bit definitions */
#define MSS_SPI_STATUS_ACTIVE BIT(14)
#define MSS_SPI_STATUS_SSEL BIT(13)
#define MSS_SPI_STATUS_FRAMESTART BIT(12)
#define MSS_SPI_STATUS_TXFIFO_EMPTY_NEXT_READ BIT(11)
#define MSS_SPI_STATUS_TXFIFO_EMPTY BIT(10)
#define MSS_SPI_STATUS_TXFIFO_FULL_NEXT_WRITE BIT(9)
#define MSS_SPI_STATUS_TXFIFO_FULL BIT(8)
#define MSS_SPI_STATUS_RXFIFO_EMPTY_NEXT_READ BIT(7)
#define MSS_SPI_STATUS_RXFIFO_EMPTY BIT(6)
#define MSS_SPI_STATUS_RXFIFO_FULL_NEXT_WRITE BIT(5)
#define MSS_SPI_STATUS_RXFIFO_FULL BIT(4)
#define MSS_SPI_STATUS_TX_UNDERRUN BIT(3)
#define MSS_SPI_STATUS_RX_OVERFLOW BIT(2)
#define MSS_SPI_STATUS_RXDAT_RCED BIT(1)
#define MSS_SPI_STATUS_TXDAT_SENT BIT(0)
/* SPIINT register defines */
#define MSS_SPI_INT_TXDONE BIT(0)
#define MSS_SPI_INT_RXRDY BIT(1)
#define MSS_SPI_INT_RX_CH_OVRFLW BIT(2)
#define MSS_SPI_INT_TX_CH_UNDRUN BIT(3)
#define MSS_SPI_INT_CMD BIT(4)
#define MSS_SPI_INT_SSEND BIT(5)
/* SPICOMMAND bit definitions */
#define MSS_SPI_COMMAND_FIFO_MASK (0xC)
/* SPIFRAMESUP bit definitions */
#define MSS_SPI_FRAMESUP_UP_BYTES_MSK (0xFFFF << 16)
#define MSS_SPI_FRAMESUP_LO_BYTES_MSK (0xFFFF << 0)
struct mss_spi_config {
mm_reg_t base;
uint8_t clk_gen;
int clock_freq;
};
struct mss_spi_transfer {
uint32_t rx_len;
uint32_t control;
};
struct mss_spi_data {
struct spi_context ctx;
struct mss_spi_transfer xfer;
};
static inline uint32_t mss_spi_read(const struct mss_spi_config *cfg, mm_reg_t offset)
{
return sys_read32(cfg->base + offset);
}
static inline void mss_spi_write(const struct mss_spi_config *cfg, mm_reg_t offset, uint32_t val)
{
sys_write32(val, cfg->base + offset);
}
static inline void mss_spi_hw_tfsz_set(const struct mss_spi_config *cfg, int len)
{
uint32_t control;
mss_spi_write(cfg, MSS_SPI_REG_FRAMESUP, (len & MSS_SPI_FRAMESUP_UP_BYTES_MSK));
control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
control &= ~MSS_SPI_CONTROL_CNT_MSK;
control |= ((len & MSS_SPI_FRAMESUP_LO_BYTES_MSK) << MSS_SPI_CONTROL_CNT_SHF);
mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
}
static inline void mss_spi_enable_controller(const struct mss_spi_config *cfg)
{
uint32_t control;
control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
control |= MSS_SPI_CONTROL_ENABLE;
mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
}
static inline void mss_spi_disable_controller(const struct mss_spi_config *cfg)
{
uint32_t control;
control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
control &= ~MSS_SPI_CONTROL_ENABLE;
mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
}
static void mss_spi_enable_ints(const struct mss_spi_config *cfg)
{
uint32_t control;
uint32_t mask = MSS_SPI_CONTROL_RX_DATA_INT | MSS_SPI_CONTROL_TX_DATA_INT |
MSS_SPI_CONTROL_RX_OVER_INT | MSS_SPI_CONTROL_TX_UNDER_INT;
control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
control |= mask;
mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
}
static void mss_spi_disable_ints(const struct mss_spi_config *cfg)
{
uint32_t control;
uint32_t mask = MSS_SPI_CONTROL_RX_DATA_INT | MSS_SPI_CONTROL_TX_DATA_INT |
MSS_SPI_CONTROL_RX_OVER_INT | MSS_SPI_CONTROL_TX_UNDER_INT;
mask = ~mask;
control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
control &= ~mask;
mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
}
static inline void mss_spi_readwr_fifo(const struct device *dev)
{
const struct mss_spi_config *cfg = dev->config;
struct mss_spi_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
struct mss_spi_transfer *xfer = &data->xfer;
uint32_t rx_raw = 0, rd_byte_size, tr_len;
uint32_t data8, transfer_idx = 0;
int count;
tr_len = spi_context_longest_current_buf(ctx);
count = spi_context_total_tx_len(ctx);
if (ctx->rx_buf) {
rd_byte_size = count - tr_len;
} else {
rd_byte_size = 0;
}
mss_spi_hw_tfsz_set(cfg, count);
mss_spi_enable_ints(cfg);
spi_context_update_rx(ctx, 1, xfer->rx_len);
while (transfer_idx < count) {
if (!(mss_spi_read(cfg, MSS_SPI_REG_STATUS) & MSS_SPI_STATUS_RXFIFO_EMPTY)) {
rx_raw = mss_spi_read(cfg, MSS_SPI_REG_RX_DATA);
if (transfer_idx >= tr_len) {
if (spi_context_rx_buf_on(ctx)) {
UNALIGNED_PUT(rx_raw, (uint8_t *)ctx->rx_buf);
spi_context_update_rx(ctx, 1, 1);
}
}
++transfer_idx;
}
if (!(mss_spi_read(cfg, MSS_SPI_REG_STATUS) & MSS_SPI_STATUS_TXFIFO_FULL)) {
if (spi_context_tx_buf_on(ctx)) {
data8 = ctx->tx_buf[0];
mss_spi_write(cfg, MSS_SPI_REG_TX_DATA, data8);
spi_context_update_tx(ctx, 1, 1);
} else {
mss_spi_write(cfg, MSS_SPI_REG_TX_DATA, 0x0);
}
}
}
}
static inline int mss_spi_select_slave(const struct mss_spi_config *cfg, int cs)
{
uint32_t slave;
uint32_t reg = mss_spi_read(cfg, MSS_SPI_REG_SS);
slave = (cs >= MSS_SPI_MIN_SLAVE && cs <= MSS_SPI_MAX_SLAVE) ? (1 << cs) : 0;
reg &= ~MSS_SPI_SSEL_MASK;
reg |= slave;
mss_spi_write(cfg, MSS_SPI_REG_SS, reg);
return 0;
}
static inline void mss_spi_activate_cs(struct mss_spi_config *cfg)
{
uint32_t reg = mss_spi_read(cfg, MSS_SPI_REG_SS);
reg |= MSS_SPI_SSELOUT;
mss_spi_write(cfg, MSS_SPI_REG_SS, reg);
}
static inline void mss_spi_deactivate_cs(const struct mss_spi_config *cfg)
{
uint32_t reg = mss_spi_read(cfg, MSS_SPI_REG_SS);
reg &= ~MSS_SPI_SSELOUT;
mss_spi_write(cfg, MSS_SPI_REG_SS, reg);
}
static inline int mss_spi_clk_gen_set(const struct mss_spi_config *cfg,
const struct spi_config *spi_cfg)
{
uint32_t idx, clkrate, val = 0, speed;
if (spi_cfg->frequency > cfg->clock_freq) {
speed = cfg->clock_freq / 2;
}
for (idx = 1; idx < 16; idx++) {
clkrate = cfg->clock_freq / (2 * idx);
if (clkrate <= spi_cfg->frequency) {
val = idx;
break;
}
}
mss_spi_write(cfg, MSS_SPI_REG_CLK_GEN, val);
return 0;
}
static inline int mss_spi_hw_mode_set(const struct mss_spi_config *cfg, unsigned int mode)
{
uint32_t control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
/* set the mode */
if (mode & SPI_MODE_CPHA) {
control |= MSS_SPI_CONTROL_SPH;
} else {
control &= ~MSS_SPI_CONTROL_SPH;
}
if (mode & SPI_MODE_CPOL) {
control |= MSS_SPI_CONTROL_SPO;
} else {
control &= ~MSS_SPI_CONTROL_SPO;
}
mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
return 0;
}
static void mss_spi_interrupt(const struct device *dev)
{
const struct mss_spi_config *cfg = dev->config;
struct mss_spi_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
int intfield = mss_spi_read(cfg, MSS_SPI_REG_MIS) & 0xf;
if (intfield == 0) {
return;
}
mss_spi_write(cfg, MSS_SPI_REG_INT_CLEAR, intfield);
spi_context_complete(ctx, dev, 0);
}
static int mss_spi_release(const struct device *dev, const struct spi_config *config)
{
const struct mss_spi_config *cfg = dev->config;
struct mss_spi_data *data = dev->data;
mss_spi_disable_ints(cfg);
/* release kernel resources */
spi_context_unlock_unconditionally(&data->ctx);
mss_spi_disable_controller(cfg);
return 0;
}
static int mss_spi_configure(const struct device *dev, const struct spi_config *spi_cfg)
{
const struct mss_spi_config *cfg = dev->config;
struct mss_spi_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
struct mss_spi_transfer *xfer = &data->xfer;
uint32_t control;
if (spi_cfg->operation & (SPI_TRANSFER_LSB | SPI_OP_MODE_SLAVE | SPI_MODE_LOOP)) {
LOG_WRN("not supported operation\n\r");
return -ENOTSUP;
}
if (SPI_WORD_SIZE_GET(spi_cfg->operation) != MSS_SPI_FRAMESIZE_DEFAULT) {
return -ENOTSUP;
}
ctx->config = spi_cfg;
mss_spi_select_slave(cfg, spi_cfg->slave);
control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
/*
* Fill up the default values
* Slave select behaviour set
* Fifo depth greater than 4 frames
* Methodology to calculate SPI Clock:
* 0: SPICLK = 1 / (2 CLK_GEN + 1) , CLK_GEN is from 0 to 15
* 1: SPICLK = 1 / (2 * (CLK_GEN + 1)) , CLK_GEN is from 0 to 255
*/
mss_spi_write(cfg, MSS_SPI_REG_CONTROL, xfer->control);
if (mss_spi_clk_gen_set(cfg, spi_cfg)) {
LOG_ERR("can't set clk divider\n");
return -EINVAL;
}
mss_spi_hw_mode_set(cfg, spi_cfg->operation);
mss_spi_write(cfg, MSS_SPI_REG_TXRXDF_SIZE, MSS_SPI_FRAMESIZE_DEFAULT);
mss_spi_enable_controller(cfg);
mss_spi_write(cfg, MSS_SPI_REG_COMMAND, MSS_SPI_COMMAND_FIFO_MASK);
return 0;
}
static int mss_spi_transceive(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
bool async, spi_callback_t cb, void *userdata)
{
const struct mss_spi_config *config = dev->config;
struct mss_spi_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
struct mss_spi_transfer *xfer = &data->xfer;
int ret = 0;
spi_context_lock(ctx, async, cb, userdata, spi_cfg);
ret = mss_spi_configure(dev, spi_cfg);
if (ret) {
LOG_ERR("Fail to configure\n\r");
goto out;
}
spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1);
xfer->rx_len = ctx->rx_len;
mss_spi_readwr_fifo(dev);
ret = spi_context_wait_for_completion(ctx);
out:
spi_context_release(ctx, ret);
mss_spi_disable_ints(config);
mss_spi_disable_controller(config);
return ret;
}
static int mss_spi_transceive_blocking(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
return mss_spi_transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
}
#ifdef CONFIG_SPI_ASYNC
static int mss_spi_transceive_async(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs, spi_callback_t cb,
void *userdata)
{
return mss_spi_transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
}
#endif /* CONFIG_SPI_ASYNC */
static int mss_spi_init(const struct device *dev)
{
const struct mss_spi_config *cfg = dev->config;
struct mss_spi_data *data = dev->data;
struct mss_spi_transfer *xfer = &data->xfer;
int ret = 0;
uint32_t control = 0;
/* Remove SPI from Reset */
control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
control &= ~MSS_SPI_CONTROL_RESET;
mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
/* Set master mode */
mss_spi_disable_controller(cfg);
xfer->control = (MSS_SPI_CONTROL_SPS | MSS_SPI_CONTROL_BIGFIFO | MSS_SPI_CONTROL_MASTER |
MSS_SPI_CONTROL_CLKMODE);
spi_context_unlock_unconditionally(&data->ctx);
return ret;
}
#define MICROCHIP_SPI_PM_OPS (NULL)
static const struct spi_driver_api mss_spi_driver_api = {
.transceive = mss_spi_transceive_blocking,
#ifdef CONFIG_SPI_ASYNC
.transceive_async = mss_spi_transceive_async,
#endif /* CONFIG_SPI_ASYNC */
.release = mss_spi_release,
};
#define MSS_SPI_INIT(n) \
static int mss_spi_init_##n(const struct device *dev) \
{ \
mss_spi_init(dev); \
\
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mss_spi_interrupt, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
\
return 0; \
} \
\
static const struct mss_spi_config mss_spi_config_##n = { \
.base = DT_INST_REG_ADDR(n), \
.clock_freq = DT_INST_PROP(n, clock_frequency), \
}; \
\
static struct mss_spi_data mss_spi_data_##n = { \
SPI_CONTEXT_INIT_LOCK(mss_spi_data_##n, ctx), \
SPI_CONTEXT_INIT_SYNC(mss_spi_data_##n, ctx), \
}; \
\
DEVICE_DT_INST_DEFINE(n, mss_spi_init_##n, NULL, &mss_spi_data_##n, &mss_spi_config_##n, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&mss_spi_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MSS_SPI_INIT)
``` | /content/code_sandbox/drivers/spi/spi_mchp_mss.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,869 |
```unknown
# LiteX SPI (LiteSPI) configuration option
config SPI_LITEX
bool "LiteX SPI controller driver"
default y
depends on DT_HAS_LITEX_SPI_ENABLED
help
Enable the SPI peripherals on LiteX
config SPI_LITEX_LITESPI
bool "LiteX SPI LiteSPI controller driver"
default y
depends on DT_HAS_LITEX_SPI_LITESPI_ENABLED
help
Enable the SPI peripherals on LiteX
``` | /content/code_sandbox/drivers/spi/Kconfig.litex | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```unknown
config SPI_MCUX_FLEXIO
bool "MCUX FlexIO SPI driver"
default y
depends on DT_HAS_NXP_FLEXIO_SPI_ENABLED
depends on CLOCK_CONTROL
select MCUX_FLEXIO
help
Enable support for MCUX FlexIO SPI driver.
``` | /content/code_sandbox/drivers/spi/Kconfig.mcux_flexio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```c
/*
*
*/
#include <zephyr/drivers/spi.h>
#include <zephyr/cache.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/mem_mgmt/mem_attr.h>
#include <soc.h>
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
#include <nrfx_ppi.h>
#endif
#ifdef CONFIG_SOC_NRF5340_CPUAPP
#include <hal/nrf_clock.h>
#endif
#include <nrfx_spim.h>
#include <string.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(spi_nrfx_spim, CONFIG_SPI_LOG_LEVEL);
#include "spi_context.h"
#include "spi_nrfx_common.h"
#if defined(CONFIG_SOC_NRF52832) && !defined(CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58)
#error This driver is not available by default for nRF52832 because of Product Anomaly 58 \
(SPIM: An additional byte is clocked out when RXD.MAXCNT == 1 and TXD.MAXCNT <= 1). \
Use CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58=y to override this limitation.
#endif
#if (CONFIG_SPI_NRFX_RAM_BUFFER_SIZE > 0)
#define SPI_BUFFER_IN_RAM 1
#endif
struct spi_nrfx_data {
struct spi_context ctx;
const struct device *dev;
size_t chunk_len;
bool busy;
bool initialized;
#ifdef SPI_BUFFER_IN_RAM
uint8_t *tx_buffer;
uint8_t *rx_buffer;
#endif
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
bool anomaly_58_workaround_active;
uint8_t ppi_ch;
uint8_t gpiote_ch;
#endif
};
struct spi_nrfx_config {
nrfx_spim_t spim;
uint32_t max_freq;
nrfx_spim_config_t def_config;
void (*irq_connect)(void);
uint16_t max_chunk_len;
const struct pinctrl_dev_config *pcfg;
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
bool anomaly_58_workaround;
#endif
uint32_t wake_pin;
nrfx_gpiote_t wake_gpiote;
#ifdef CONFIG_DCACHE
uint32_t mem_attr;
#endif
};
static void event_handler(const nrfx_spim_evt_t *p_event, void *p_context);
static inline void finalize_spi_transaction(const struct device *dev, bool deactivate_cs)
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
void *reg = dev_config->spim.p_reg;
if (deactivate_cs) {
spi_context_cs_control(&dev_data->ctx, false);
}
if (NRF_SPIM_IS_320MHZ_SPIM(reg) && !(dev_data->ctx.config->operation & SPI_HOLD_ON_CS)) {
nrfy_spim_disable(reg);
}
}
static inline uint32_t get_nrf_spim_frequency(uint32_t frequency)
{
/* Get the highest supported frequency not exceeding the requested one.
*/
if (frequency >= MHZ(32) && (NRF_SPIM_HAS_32_MHZ_FREQ || NRF_SPIM_HAS_PRESCALER)) {
return MHZ(32);
} else if (frequency >= MHZ(16) && (NRF_SPIM_HAS_16_MHZ_FREQ || NRF_SPIM_HAS_PRESCALER)) {
return MHZ(16);
} else if (frequency >= MHZ(8)) {
return MHZ(8);
} else if (frequency >= MHZ(4)) {
return MHZ(4);
} else if (frequency >= MHZ(2)) {
return MHZ(2);
} else if (frequency >= MHZ(1)) {
return MHZ(1);
} else if (frequency >= KHZ(500)) {
return KHZ(500);
} else if (frequency >= KHZ(250)) {
return KHZ(250);
} else {
return KHZ(125);
}
}
static inline nrf_spim_mode_t get_nrf_spim_mode(uint16_t operation)
{
if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
return NRF_SPIM_MODE_3;
} else {
return NRF_SPIM_MODE_2;
}
} else {
if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
return NRF_SPIM_MODE_1;
} else {
return NRF_SPIM_MODE_0;
}
}
}
static inline nrf_spim_bit_order_t get_nrf_spim_bit_order(uint16_t operation)
{
if (operation & SPI_TRANSFER_LSB) {
return NRF_SPIM_BIT_ORDER_LSB_FIRST;
} else {
return NRF_SPIM_BIT_ORDER_MSB_FIRST;
}
}
static int configure(const struct device *dev,
const struct spi_config *spi_cfg)
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_context *ctx = &dev_data->ctx;
uint32_t max_freq = dev_config->max_freq;
nrfx_spim_config_t config;
nrfx_err_t result;
if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
/* Already configured. No need to do it again. */
return 0;
}
if (spi_cfg->operation & SPI_HALF_DUPLEX) {
LOG_ERR("Half-duplex not supported");
return -ENOTSUP;
}
if (SPI_OP_MODE_GET(spi_cfg->operation) != SPI_OP_MODE_MASTER) {
LOG_ERR("Slave mode is not supported on %s", dev->name);
return -EINVAL;
}
if (spi_cfg->operation & SPI_MODE_LOOP) {
LOG_ERR("Loopback mode is not supported");
return -EINVAL;
}
if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
(spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
LOG_ERR("Only single line mode is supported");
return -EINVAL;
}
if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
LOG_ERR("Word sizes other than 8 bits are not supported");
return -EINVAL;
}
if (spi_cfg->frequency < 125000) {
LOG_ERR("Frequencies lower than 125 kHz are not supported");
return -EINVAL;
}
#if defined(CONFIG_SOC_NRF5340_CPUAPP)
/* On nRF5340, the 32 Mbps speed is supported by the application core
* when it is running at 128 MHz (see the Timing specifications section
* in the nRF5340 PS).
*/
if (max_freq > 16000000 &&
nrf_clock_hfclk_div_get(NRF_CLOCK) != NRF_CLOCK_HFCLK_DIV_1) {
max_freq = 16000000;
}
#endif
config = dev_config->def_config;
/* Limit the frequency to that supported by the SPIM instance. */
config.frequency = get_nrf_spim_frequency(MIN(spi_cfg->frequency,
max_freq));
config.mode = get_nrf_spim_mode(spi_cfg->operation);
config.bit_order = get_nrf_spim_bit_order(spi_cfg->operation);
nrfy_gpio_pin_write(nrfy_spim_sck_pin_get(dev_config->spim.p_reg),
spi_cfg->operation & SPI_MODE_CPOL ? 1 : 0);
if (dev_data->initialized) {
nrfx_spim_uninit(&dev_config->spim);
dev_data->initialized = false;
}
result = nrfx_spim_init(&dev_config->spim, &config,
event_handler, (void *)dev);
if (result != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize nrfx driver: %08x", result);
return -EIO;
}
dev_data->initialized = true;
ctx->config = spi_cfg;
return 0;
}
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
static const nrfx_gpiote_t gpiote = NRFX_GPIOTE_INSTANCE(0);
/*
* Brief Workaround for transmitting 1 byte with SPIM.
*
* Derived from the setup_workaround_for_ftpan_58() function from
* the nRF52832 Rev 1 Errata v1.6 document anomaly 58 workaround.
*
* Warning Must not be used when transmitting multiple bytes.
*
* Warning After this workaround is used, the user must reset the PPI
* channel and the GPIOTE channel before attempting to transmit multiple
* bytes.
*/
static void anomaly_58_workaround_setup(const struct device *dev)
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
NRF_SPIM_Type *spim = dev_config->spim.p_reg;
uint32_t ppi_ch = dev_data->ppi_ch;
uint32_t gpiote_ch = dev_data->gpiote_ch;
uint32_t eep = (uint32_t)&gpiote.p_reg->EVENTS_IN[gpiote_ch];
uint32_t tep = (uint32_t)&spim->TASKS_STOP;
dev_data->anomaly_58_workaround_active = true;
/* Create an event when SCK toggles */
nrf_gpiote_event_configure(gpiote.p_reg, gpiote_ch, spim->PSEL.SCK,
GPIOTE_CONFIG_POLARITY_Toggle);
nrf_gpiote_event_enable(gpiote.p_reg, gpiote_ch);
/* Stop the spim instance when SCK toggles */
nrf_ppi_channel_endpoint_setup(NRF_PPI, ppi_ch, eep, tep);
nrf_ppi_channel_enable(NRF_PPI, ppi_ch);
/* The spim instance cannot be stopped mid-byte, so it will finish
* transmitting the first byte and then stop. Effectively ensuring
* that only 1 byte is transmitted.
*/
}
static void anomaly_58_workaround_clear(struct spi_nrfx_data *dev_data)
{
uint32_t ppi_ch = dev_data->ppi_ch;
uint32_t gpiote_ch = dev_data->gpiote_ch;
if (dev_data->anomaly_58_workaround_active) {
nrf_ppi_channel_disable(NRF_PPI, ppi_ch);
nrf_gpiote_task_disable(gpiote.p_reg, gpiote_ch);
dev_data->anomaly_58_workaround_active = false;
}
}
static int anomaly_58_workaround_init(const struct device *dev)
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
nrfx_err_t err_code;
dev_data->anomaly_58_workaround_active = false;
if (dev_config->anomaly_58_workaround) {
err_code = nrfx_ppi_channel_alloc(&dev_data->ppi_ch);
if (err_code != NRFX_SUCCESS) {
LOG_ERR("Failed to allocate PPI channel");
return -ENODEV;
}
err_code = nrfx_gpiote_channel_alloc(&gpiote, &dev_data->gpiote_ch);
if (err_code != NRFX_SUCCESS) {
LOG_ERR("Failed to allocate GPIOTE channel");
return -ENODEV;
}
LOG_DBG("PAN 58 workaround enabled for %s: ppi %u, gpiote %u",
dev->name, dev_data->ppi_ch, dev_data->gpiote_ch);
}
return 0;
}
#endif
static void finish_transaction(const struct device *dev, int error)
{
struct spi_nrfx_data *dev_data = dev->data;
struct spi_context *ctx = &dev_data->ctx;
LOG_DBG("Transaction finished with status %d", error);
spi_context_complete(ctx, dev, error);
dev_data->busy = false;
finalize_spi_transaction(dev, true);
}
static void transfer_next_chunk(const struct device *dev)
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_context *ctx = &dev_data->ctx;
int error = 0;
size_t chunk_len = spi_context_max_continuous_chunk(ctx);
if (chunk_len > 0) {
nrfx_spim_xfer_desc_t xfer;
nrfx_err_t result;
const uint8_t *tx_buf = ctx->tx_buf;
uint8_t *rx_buf = ctx->rx_buf;
if (chunk_len > dev_config->max_chunk_len) {
chunk_len = dev_config->max_chunk_len;
}
#ifdef SPI_BUFFER_IN_RAM
if (spi_context_tx_buf_on(ctx) &&
!nrf_dma_accessible_check(&dev_config->spim.p_reg, tx_buf)) {
if (chunk_len > CONFIG_SPI_NRFX_RAM_BUFFER_SIZE) {
chunk_len = CONFIG_SPI_NRFX_RAM_BUFFER_SIZE;
}
memcpy(dev_data->tx_buffer, tx_buf, chunk_len);
#ifdef CONFIG_DCACHE
if (dev_config->mem_attr & DT_MEM_CACHEABLE) {
sys_cache_data_flush_range(dev_data->tx_buffer, chunk_len);
}
#endif
tx_buf = dev_data->tx_buffer;
}
if (spi_context_rx_buf_on(ctx) &&
!nrf_dma_accessible_check(&dev_config->spim.p_reg, rx_buf)) {
if (chunk_len > CONFIG_SPI_NRFX_RAM_BUFFER_SIZE) {
chunk_len = CONFIG_SPI_NRFX_RAM_BUFFER_SIZE;
}
rx_buf = dev_data->rx_buffer;
}
#endif
dev_data->chunk_len = chunk_len;
xfer.p_tx_buffer = tx_buf;
xfer.tx_length = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
xfer.p_rx_buffer = rx_buf;
xfer.rx_length = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
if (xfer.rx_length == 1 && xfer.tx_length <= 1) {
if (dev_config->anomaly_58_workaround) {
anomaly_58_workaround_setup(dev);
} else {
LOG_WRN("Transaction aborted since it would trigger "
"nRF52832 PAN 58");
error = -EIO;
}
}
#endif
if (error == 0) {
result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
if (result == NRFX_SUCCESS) {
return;
}
error = -EIO;
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
anomaly_58_workaround_clear(dev_data);
#endif
}
}
finish_transaction(dev, error);
}
static void event_handler(const nrfx_spim_evt_t *p_event, void *p_context)
{
const struct device *dev = p_context;
struct spi_nrfx_data *dev_data = dev->data;
#ifdef CONFIG_DCACHE
const struct spi_nrfx_config *dev_config = dev->config;
#endif
if (p_event->type == NRFX_SPIM_EVENT_DONE) {
/* Chunk length is set to 0 when a transaction is aborted
* due to a timeout.
*/
if (dev_data->chunk_len == 0) {
finish_transaction(dev_data->dev, -ETIMEDOUT);
return;
}
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
anomaly_58_workaround_clear(dev_data);
#endif
#ifdef SPI_BUFFER_IN_RAM
if (spi_context_rx_buf_on(&dev_data->ctx) &&
p_event->xfer_desc.p_rx_buffer != NULL &&
p_event->xfer_desc.p_rx_buffer != dev_data->ctx.rx_buf) {
#ifdef CONFIG_DCACHE
if (dev_config->mem_attr & DT_MEM_CACHEABLE) {
sys_cache_data_invd_range(dev_data->rx_buffer, dev_data->chunk_len);
}
#endif
(void)memcpy(dev_data->ctx.rx_buf,
dev_data->rx_buffer,
dev_data->chunk_len);
}
#endif
spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
spi_context_update_rx(&dev_data->ctx, 1, dev_data->chunk_len);
transfer_next_chunk(dev_data->dev);
}
}
static int transceive(const struct device *dev,
const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs,
bool asynchronous,
spi_callback_t cb,
void *userdata)
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
void *reg = dev_config->spim.p_reg;
int error;
spi_context_lock(&dev_data->ctx, asynchronous, cb, userdata, spi_cfg);
error = configure(dev, spi_cfg);
if (error == 0) {
dev_data->busy = true;
if (dev_config->wake_pin != WAKE_PIN_NOT_USED) {
error = spi_nrfx_wake_request(&dev_config->wake_gpiote,
dev_config->wake_pin);
if (error == -ETIMEDOUT) {
LOG_WRN("Waiting for WAKE acknowledgment timed out");
/* If timeout occurs, try to perform the transfer
* anyway, just in case the slave device was unable
* to signal that it was already awaken and prepared
* for the transfer.
*/
}
}
spi_context_buffers_setup(&dev_data->ctx, tx_bufs, rx_bufs, 1);
if (NRF_SPIM_IS_320MHZ_SPIM(reg)) {
nrfy_spim_enable(reg);
}
spi_context_cs_control(&dev_data->ctx, true);
transfer_next_chunk(dev);
error = spi_context_wait_for_completion(&dev_data->ctx);
if (error == -ETIMEDOUT) {
/* Set the chunk length to 0 so that event_handler()
* knows that the transaction timed out and is to be
* aborted.
*/
dev_data->chunk_len = 0;
/* Abort the current transfer by deinitializing
* the nrfx driver.
*/
nrfx_spim_uninit(&dev_config->spim);
dev_data->initialized = false;
/* Make sure the transaction is finished (it may be
* already finished if it actually did complete before
* the nrfx driver was deinitialized).
*/
finish_transaction(dev, -ETIMEDOUT);
/* Clean up the driver state. */
k_sem_reset(&dev_data->ctx.sync);
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
anomaly_58_workaround_clear(dev_data);
#endif
} else if (error) {
finalize_spi_transaction(dev, true);
}
}
spi_context_release(&dev_data->ctx, error);
return error;
}
static int spi_nrfx_transceive(const struct device *dev,
const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
}
#ifdef CONFIG_SPI_ASYNC
static int spi_nrfx_transceive_async(const struct device *dev,
const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs,
spi_callback_t cb,
void *userdata)
{
return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
}
#endif /* CONFIG_SPI_ASYNC */
static int spi_nrfx_release(const struct device *dev,
const struct spi_config *spi_cfg)
{
struct spi_nrfx_data *dev_data = dev->data;
if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
return -EINVAL;
}
if (dev_data->busy) {
return -EBUSY;
}
spi_context_unlock_unconditionally(&dev_data->ctx);
finalize_spi_transaction(dev, false);
return 0;
}
static const struct spi_driver_api spi_nrfx_driver_api = {
.transceive = spi_nrfx_transceive,
#ifdef CONFIG_SPI_ASYNC
.transceive_async = spi_nrfx_transceive_async,
#endif
.release = spi_nrfx_release,
};
#ifdef CONFIG_PM_DEVICE
static int spim_nrfx_pm_action(const struct device *dev,
enum pm_device_action action)
{
int ret = 0;
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = pinctrl_apply_state(dev_config->pcfg,
PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
/* nrfx_spim_init() will be called at configuration before
* the next transfer.
*/
break;
case PM_DEVICE_ACTION_SUSPEND:
if (dev_data->initialized) {
nrfx_spim_uninit(&dev_config->spim);
dev_data->initialized = false;
}
ret = pinctrl_apply_state(dev_config->pcfg,
PINCTRL_STATE_SLEEP);
if (ret < 0) {
return ret;
}
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static int spi_nrfx_init(const struct device *dev)
{
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_nrfx_data *dev_data = dev->data;
int err;
err = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {
return err;
}
if (dev_config->wake_pin != WAKE_PIN_NOT_USED) {
err = spi_nrfx_wake_init(&dev_config->wake_gpiote, dev_config->wake_pin);
if (err == -ENODEV) {
LOG_ERR("Failed to allocate GPIOTE channel for WAKE");
return err;
}
if (err == -EIO) {
LOG_ERR("Failed to configure WAKE pin");
return err;
}
}
dev_config->irq_connect();
err = spi_context_cs_configure_all(&dev_data->ctx);
if (err < 0) {
return err;
}
spi_context_unlock_unconditionally(&dev_data->ctx);
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
return anomaly_58_workaround_init(dev);
#else
return 0;
#endif
}
/*
* We use NODELABEL here because the nrfx API requires us to call
* functions which are named according to SoC peripheral instance
* being operated on. Since DT_INST() makes no guarantees about that,
* it won't work.
*/
#define SPIM(idx) DT_NODELABEL(spi##idx)
#define SPIM_PROP(idx, prop) DT_PROP(SPIM(idx), prop)
#define SPIM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(SPIM(idx), prop)
#define SPIM_MEM_REGION(idx) DT_PHANDLE(SPIM(idx), memory_regions)
#define SPI_NRFX_SPIM_EXTENDED_CONFIG(idx) \
IF_ENABLED(NRFX_SPIM_EXTENDED_ENABLED, \
(.dcx_pin = NRF_SPIM_PIN_NOT_CONNECTED, \
COND_CODE_1(SPIM_PROP(idx, rx_delay_supported), \
(.rx_delay = SPIM_PROP(idx, rx_delay),), \
()) \
))
#define SPIM_GET_MEM_ATTR(idx) \
COND_CODE_1(SPIM_HAS_PROP(idx, memory_regions), \
(COND_CODE_1(DT_NODE_HAS_PROP(SPIM_MEM_REGION(idx), zephyr_memory_attr), \
(DT_PROP(SPIM_MEM_REGION(idx), zephyr_memory_attr)), \
(0))), \
(0))
#define SPI_NRFX_SPIM_DEFINE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(SPIM(idx)); \
static void irq_connect##idx(void) \
{ \
IRQ_CONNECT(DT_IRQN(SPIM(idx)), DT_IRQ(SPIM(idx), priority), \
nrfx_isr, nrfx_spim_##idx##_irq_handler, 0); \
} \
IF_ENABLED(SPI_BUFFER_IN_RAM, \
(static uint8_t spim_##idx##_tx_buffer \
[CONFIG_SPI_NRFX_RAM_BUFFER_SIZE] \
SPIM_MEMORY_SECTION(idx); \
static uint8_t spim_##idx##_rx_buffer \
[CONFIG_SPI_NRFX_RAM_BUFFER_SIZE] \
SPIM_MEMORY_SECTION(idx);)) \
static struct spi_nrfx_data spi_##idx##_data = { \
SPI_CONTEXT_INIT_LOCK(spi_##idx##_data, ctx), \
SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx), \
SPI_CONTEXT_CS_GPIOS_INITIALIZE(SPIM(idx), ctx) \
IF_ENABLED(SPI_BUFFER_IN_RAM, \
(.tx_buffer = spim_##idx##_tx_buffer, \
.rx_buffer = spim_##idx##_rx_buffer,)) \
.dev = DEVICE_DT_GET(SPIM(idx)), \
.busy = false, \
}; \
PINCTRL_DT_DEFINE(SPIM(idx)); \
static const struct spi_nrfx_config spi_##idx##z_config = { \
.spim = { \
.p_reg = (NRF_SPIM_Type *)DT_REG_ADDR(SPIM(idx)), \
.drv_inst_idx = NRFX_SPIM##idx##_INST_IDX, \
}, \
.max_freq = SPIM_PROP(idx, max_frequency), \
.def_config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.ss_pin = NRF_SPIM_PIN_NOT_CONNECTED, \
.orc = SPIM_PROP(idx, overrun_character), \
SPI_NRFX_SPIM_EXTENDED_CONFIG(idx) \
}, \
.irq_connect = irq_connect##idx, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(SPIM(idx)), \
.max_chunk_len = BIT_MASK(SPIM_PROP(idx, easydma_maxcnt_bits)),\
COND_CODE_1(CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58, \
(.anomaly_58_workaround = \
SPIM_PROP(idx, anomaly_58_workaround),), \
()) \
.wake_pin = NRF_DT_GPIOS_TO_PSEL_OR(SPIM(idx), wake_gpios, \
WAKE_PIN_NOT_USED), \
.wake_gpiote = WAKE_GPIOTE_INSTANCE(SPIM(idx)), \
IF_ENABLED(CONFIG_DCACHE, \
(.mem_attr = SPIM_GET_MEM_ATTR(idx),)) \
}; \
BUILD_ASSERT(!SPIM_HAS_PROP(idx, wake_gpios) || \
!(DT_GPIO_FLAGS(SPIM(idx), wake_gpios) & GPIO_ACTIVE_LOW),\
"WAKE line must be configured as active high"); \
PM_DEVICE_DT_DEFINE(SPIM(idx), spim_nrfx_pm_action); \
DEVICE_DT_DEFINE(SPIM(idx), \
spi_nrfx_init, \
PM_DEVICE_DT_GET(SPIM(idx)), \
&spi_##idx##_data, \
&spi_##idx##z_config, \
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_nrfx_driver_api)
#define SPIM_MEMORY_SECTION(idx) \
COND_CODE_1(SPIM_HAS_PROP(idx, memory_regions), \
(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
SPIM_MEM_REGION(idx)))))), \
())
#ifdef CONFIG_HAS_HW_NRF_SPIM0
SPI_NRFX_SPIM_DEFINE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM1
SPI_NRFX_SPIM_DEFINE(1);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM2
SPI_NRFX_SPIM_DEFINE(2);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM3
SPI_NRFX_SPIM_DEFINE(3);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM4
SPI_NRFX_SPIM_DEFINE(4);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM00
SPI_NRFX_SPIM_DEFINE(00);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM20
SPI_NRFX_SPIM_DEFINE(20);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM21
SPI_NRFX_SPIM_DEFINE(21);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM22
SPI_NRFX_SPIM_DEFINE(22);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM30
SPI_NRFX_SPIM_DEFINE(30);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM120
SPI_NRFX_SPIM_DEFINE(120);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM121
SPI_NRFX_SPIM_DEFINE(121);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM130
SPI_NRFX_SPIM_DEFINE(130);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM131
SPI_NRFX_SPIM_DEFINE(131);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM132
SPI_NRFX_SPIM_DEFINE(132);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM133
SPI_NRFX_SPIM_DEFINE(133);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM134
SPI_NRFX_SPIM_DEFINE(134);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM135
SPI_NRFX_SPIM_DEFINE(135);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM136
SPI_NRFX_SPIM_DEFINE(136);
#endif
#ifdef CONFIG_HAS_HW_NRF_SPIM137
SPI_NRFX_SPIM_DEFINE(137);
#endif
``` | /content/code_sandbox/drivers/spi/spi_nrfx_spim.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,675 |
```unknown
config SPI_GRLIB_SPIMCTRL
bool "GRLIB SPI memory controller"
depends on SOC_SPARC_LEON
help
Enable the GRLIB SPIMCTRL
``` | /content/code_sandbox/drivers/spi/Kconfig.grlib_spimctrl | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```c
/*
*
*/
#define DT_DRV_COMPAT sifive_spi0
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_sifive);
#include "spi_sifive.h"
#include <soc.h>
#include <stdbool.h>
/* Helper Functions */
static ALWAYS_INLINE
void sys_set_mask(mem_addr_t addr, uint32_t mask, uint32_t value)
{
uint32_t temp = sys_read32(addr);
temp &= ~(mask);
temp |= value;
sys_write32(temp, addr);
}
static int spi_config(const struct device *dev, uint32_t frequency,
uint16_t operation)
{
uint32_t div;
uint32_t fmt_len;
if (operation & SPI_HALF_DUPLEX) {
return -ENOTSUP;
}
if (SPI_OP_MODE_GET(operation) != SPI_OP_MODE_MASTER) {
return -ENOTSUP;
}
if (operation & SPI_MODE_LOOP) {
return -ENOTSUP;
}
/* Set the SPI frequency */
div = (SPI_CFG(dev)->f_sys / (frequency * 2U)) - 1;
sys_write32((SF_SCKDIV_DIV_MASK & div), SPI_REG(dev, REG_SCKDIV));
/* Set the polarity */
if (operation & SPI_MODE_CPOL) {
/* If CPOL is set, then SCK idles at logical 1 */
sys_set_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_POL);
} else {
/* SCK idles at logical 0 */
sys_clear_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_POL);
}
/* Set the phase */
if (operation & SPI_MODE_CPHA) {
/*
* If CPHA is set, then data is sampled
* on the trailing SCK edge
*/
sys_set_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_PHA);
} else {
/* Data is sampled on the leading SCK edge */
sys_clear_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_PHA);
}
/* Get the frame length */
fmt_len = SPI_WORD_SIZE_GET(operation);
if (fmt_len > SF_FMT_LEN_MASK) {
return -ENOTSUP;
}
/* Set the frame length */
fmt_len = fmt_len << SF_FMT_LEN;
fmt_len &= SF_FMT_LEN_MASK;
sys_set_mask(SPI_REG(dev, REG_FMT), SF_FMT_LEN_MASK, fmt_len);
if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
(operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
return -ENOTSUP;
}
/* Set single line operation */
sys_set_mask(SPI_REG(dev, REG_FMT),
SF_FMT_PROTO_MASK,
SF_FMT_PROTO_SINGLE);
/* Set the endianness */
if (operation & SPI_TRANSFER_LSB) {
sys_set_bit(SPI_REG(dev, REG_FMT), SF_FMT_ENDIAN);
} else {
sys_clear_bit(SPI_REG(dev, REG_FMT), SF_FMT_ENDIAN);
}
return 0;
}
static ALWAYS_INLINE bool spi_sifive_send_available(const struct device *dev)
{
return !(sys_read32(SPI_REG(dev, REG_TXDATA)) & SF_TXDATA_FULL);
}
static ALWAYS_INLINE
void spi_sifive_send(const struct device *dev, uint8_t frame)
{
sys_write32((uint32_t) frame, SPI_REG(dev, REG_TXDATA));
}
static ALWAYS_INLINE
bool spi_sifive_recv(const struct device *dev, uint8_t *val)
{
uint32_t reg = sys_read32(SPI_REG(dev, REG_RXDATA));
if (reg & SF_RXDATA_EMPTY) {
return false;
}
*val = (uint8_t) reg;
return true;
}
static void spi_sifive_xfer(const struct device *dev, const bool hw_cs_control)
{
struct spi_context *ctx = &SPI_DATA(dev)->ctx;
uint8_t txd, rxd;
int queued_frames = 0;
while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx) || queued_frames > 0) {
bool send = false;
/* As long as frames remain to be sent, attempt to queue them on Tx FIFO. If
* the FIFO is full then another attempt will be made next pass. If Rx length
* > Tx length then queue dummy Tx in order to read the requested Rx data.
*/
if (spi_context_tx_buf_on(ctx)) {
send = true;
txd = *ctx->tx_buf;
} else if (queued_frames == 0) { /* Implies spi_context_rx_on(). */
send = true;
txd = 0U;
}
if (send && spi_sifive_send_available(dev)) {
spi_sifive_send(dev, txd);
queued_frames++;
spi_context_update_tx(ctx, 1, 1);
}
if (queued_frames > 0 && spi_sifive_recv(dev, &rxd)) {
if (spi_context_rx_buf_on(ctx)) {
*ctx->rx_buf = rxd;
}
queued_frames--;
spi_context_update_rx(ctx, 1, 1);
}
}
/* Deassert the CS line */
if (!hw_cs_control) {
spi_context_cs_control(&SPI_DATA(dev)->ctx, false);
} else {
sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE));
}
spi_context_complete(ctx, dev, 0);
}
/* API Functions */
static int spi_sifive_init(const struct device *dev)
{
int err;
#ifdef CONFIG_PINCTRL
struct spi_sifive_cfg *cfg = (struct spi_sifive_cfg *)dev->config;
#endif
/* Disable SPI Flash mode */
sys_clear_bit(SPI_REG(dev, REG_FCTRL), SF_FCTRL_EN);
err = spi_context_cs_configure_all(&SPI_DATA(dev)->ctx);
if (err < 0) {
return err;
}
#ifdef CONFIG_PINCTRL
err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {
return err;
}
#endif
/* Make sure the context is unlocked */
spi_context_unlock_unconditionally(&SPI_DATA(dev)->ctx);
return 0;
}
static int spi_sifive_transceive(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
int rc = 0;
bool hw_cs_control = false;
/* Lock the SPI Context */
spi_context_lock(&SPI_DATA(dev)->ctx, false, NULL, NULL, config);
/* Configure the SPI bus */
SPI_DATA(dev)->ctx.config = config;
/*
* If the chip select configuration is not present, we'll ask the
* SPI peripheral itself to control the CS line
*/
if (!spi_cs_is_gpio(config)) {
hw_cs_control = true;
}
if (!hw_cs_control) {
/*
* If the user has requested manual GPIO control, ask the
* context for control and disable HW control
*/
sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE));
} else {
/*
* Tell the hardware to control the requested CS pin.
* NOTE:
* For the SPI peripheral, the pin number is not the
* GPIO pin, but the index into the list of available
* CS lines for the SPI peripheral.
*/
sys_write32(config->slave, SPI_REG(dev, REG_CSID));
sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE));
}
rc = spi_config(dev, config->frequency, config->operation);
if (rc < 0) {
spi_context_release(&SPI_DATA(dev)->ctx, rc);
return rc;
}
spi_context_buffers_setup(&SPI_DATA(dev)->ctx, tx_bufs, rx_bufs, 1);
/* Assert the CS line */
if (!hw_cs_control) {
spi_context_cs_control(&SPI_DATA(dev)->ctx, true);
} else {
sys_write32(SF_CSMODE_HOLD, SPI_REG(dev, REG_CSMODE));
}
/* Perform transfer */
spi_sifive_xfer(dev, hw_cs_control);
rc = spi_context_wait_for_completion(&SPI_DATA(dev)->ctx);
spi_context_release(&SPI_DATA(dev)->ctx, rc);
return rc;
}
static int spi_sifive_release(const struct device *dev,
const struct spi_config *config)
{
spi_context_unlock_unconditionally(&SPI_DATA(dev)->ctx);
return 0;
}
/* Device Instantiation */
static const struct spi_driver_api spi_sifive_api = {
.transceive = spi_sifive_transceive,
.release = spi_sifive_release,
};
#define SPI_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static struct spi_sifive_data spi_sifive_data_##n = { \
SPI_CONTEXT_INIT_LOCK(spi_sifive_data_##n, ctx), \
SPI_CONTEXT_INIT_SYNC(spi_sifive_data_##n, ctx), \
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
}; \
static struct spi_sifive_cfg spi_sifive_cfg_##n = { \
.base = DT_INST_REG_ADDR_BY_NAME(n, control), \
.f_sys = SIFIVE_PERIPHERAL_CLOCK_FREQUENCY, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
DEVICE_DT_INST_DEFINE(n, \
spi_sifive_init, \
NULL, \
&spi_sifive_data_##n, \
&spi_sifive_cfg_##n, \
POST_KERNEL, \
CONFIG_SPI_INIT_PRIORITY, \
&spi_sifive_api);
DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)
``` | /content/code_sandbox/drivers/spi/spi_sifive.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,160 |
```unknown
# Cypress SCB[SPI] configuration
config SPI_PSOC6
bool "PSoC-6 MCU SCB spi driver"
default y
depends on DT_HAS_CYPRESS_PSOC6_SPI_ENABLED
select USE_INFINEON_SPI
select PINCTRL
help
This option enables the SCB[SPI] driver for PSoC-6 SoC family.
``` | /content/code_sandbox/drivers/spi/Kconfig.psoc6 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```objective-c
/* spi_pw.h - Penwell SPI driver definitions */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_SPI_SPI_PW_H_
#define ZEPHYR_DRIVERS_SPI_SPI_PW_H_
#include "spi_context.h"
/* lpss penwell spi registers */
#define PW_SPI_REG_CTRLR0 0x00
#define PW_SPI_REG_CTRLR1 0x04
#define PW_SPI_REG_SSSR 0x08
#define PW_SPI_REG_SSDR 0x10
#define PW_SPI_REG_SSTO 0x28
#define PW_SPI_REG_SITF 0x44
#define PW_SPI_REG_SIRF 0x48
#define PW_SPI_REG_CLKS 0x200
#define PW_SPI_REG_RESETS 0x204
#define PW_SPI_REG_ACTIVE_LTR 0x210
#define PW_SPI_REG_IDLE_LTR 0x217
#define PW_SPI_REG_TX_BIT_COUNT 0x218
#define PW_SPI_REG_RX_BIT_COUNT 0x21c
#define PW_SPI_REG_DMA_FINISH_DIS 0x220
#define PW_SPI_REG_CS_CTRL 0x224
#define PW_SPI_REG_SW_SCRATCH 0x228
#define PW_SPI_REG_CLK_GATE 0x238
#define PW_SPI_REG_REMAP_ADDR_LO 0x240
#define PW_SPI_REG_REMAP_ADDR_HI 0x244
#define PW_SPI_REG_DEV_IDLE_CTRL 0x24c
#define PW_SPI_REG_DEL_RX_CLK 0x250
#define PW_SPI_REG_CAP 0x2fc
/* CTRLR0 settings */
#define PW_SPI_CTRLR0_SSE_BIT BIT(7)
#define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
#define PW_SPI_CTRLR0_RIM_BIT BIT(22)
#define PW_SPI_CTRLR0_TIM_BIT BIT(23)
#define PW_SPI_CTRLR0_MOD_BIT BIT(31)
#define PW_SPI_CTRLR0_DATA_MASK (~(0xf << 0))
#define PW_SPI_CTRLR0_EDSS_MASK (~(0x1 << 20))
/* Data size set bits sscr0[3:0] */
#define PW_SPI_DATA_SIZE_4_BIT 0x3
#define PW_SPI_DATA_SIZE_8_BIT 0x7
#define PW_SPI_DATA_SIZE_16_BIT 0xf
#define PW_SPI_DATA_SIZE_32_BIT (PW_SPI_CTRLR0_EDSS_BIT | \
PW_SPI_DATA_SIZE_16_BIT)
/* Frame format sscr0[5:4] */
#define PW_SPI_FRF_MOTOROLA (~(0x3 << 4))
/* SSP Baud rate sscr0[19:8] */
#define PW_SPI_BR_2MHZ 0x31
#define PW_SPI_BR_4MHZ 0x18
#define PW_SPI_BR_5MHZ 0x13
#define PW_SPI_BR_10MHZ 0x9
#define PW_SPI_BR_20MHZ 0x5
#define PW_SPI_BR_MAX_FRQ 20000000 /* 20 MHz */
/* [19:8] 12 bits */
#define PW_SPI_SCR_MASK (BIT_MASK(12) << 8)
#define PW_SPI_SCR_SHIFT 0x8
/* CTRLR1 settings */
#define PW_SPI_CTRL1_RIE_BIT BIT(0)
#define PW_SPI_CTRL1_TIE_BIT BIT(1)
#define PW_SPI_CTRL1_LBM_BIT BIT(2)
#define PW_SPI_CTRL1_SPO_BIT BIT(3)
#define PW_SPI_CTRL1_SPH_BIT BIT(4)
#define PW_SPI_CTRL1_IFS_BIT BIT(16)
#define PW_SPI_CTRL1_TINTE_BIT BIT(19)
#define PW_SPI_CTRL1_RSRE_BIT BIT(20)
#define PW_SPI_CTRL1_TSRE_BIT BIT(21)
#define PW_SPI_CTRL1_TRAIL_BIT BIT(22)
#define PW_SPI_CTRL1_RWOT_BIT BIT(23)
/* [4:3] phase & polarity mask */
#define PW_SPI_CTRL1_SPO_SPH_MASK (BIT_MASK(2) << 3)
/* Status Register */
#define PW_SPI_SSSR_TNF_BIT BIT(2)
#define PW_SPI_SSSR_RNE_BIT BIT(3)
#define PW_SPI_SSSR_BSY_BIT BIT(4)
#define PW_SPI_SSSR_TFS_BIT BIT(5)
#define PW_SPI_SSSR_RFS_BIT BIT(6)
#define PW_SPI_SSSR_ROR_BIT BIT(7)
#define PW_SPI_SSSR_PINT_BIT BIT(18)
#define PW_SPI_SSSR_TINT_BIT BIT(19)
#define PW_SPI_SSSR_TUR_BIT BIT(21)
/* SPI Tx FIFO Higher Water Mark [5:0] */
#define PW_SPI_SITF_HWM_1_ENTRY 0x1
#define PW_SPI_SITF_HWM_4_ENTRY 0x4
#define PW_SPI_SITF_HWM_8_ENTRY 0x8
#define PW_SPI_SITF_HWM_16_ENTRY 0x10
#define PW_SPI_SITF_HWM_32_ENTRY 0x20
#define PW_SPI_SITF_HWM_64_ENTRY 0x40
/* SPI Tx FIFO Lower Water Mark[13:8] */
#define PW_SPI_SITF_LWM_2_ENTRY (BIT(0) << 8)
#define PW_SPI_SITF_LWM_3_ENTRY (BIT(1) << 8)
#define PW_SPI_SITF_LWM_4_ENTRY ((BIT(1) | BIT(0)) << 8)
/* SPI Tx FIFO Level SITF[21:16] */
#define PW_SPI_SITF_SITFL_MASK (BIT_MASK(6) << 16)
#define PW_SPI_SITF_SITFL_SHIFT 0x10
/* SPI Rx FIFO water mark */
#define PW_SPI_SIRF_WMRF_1_ENTRY 0x1
#define PW_SPI_SIRF_WMRF_2_ENTRY 0x2
#define PW_SPI_SIRF_WMRF_4_ENTRY 0x4
#define PW_SPI_SITF_WMRF_8_ENTRY 0x8
#define PW_SPI_SITF_WMRF_16_ENTRY 0x10
#define PW_SPI_SITF_WMRF_32_ENTRY 0x20
#define PW_SPI_SITF_WMRF_64_ENTRY 0x40
/* SPI Rx FIFO Level RITF[13:8] */
#define PW_SPI_SIRF_SIRFL_MASK (BIT_MASK(6) << 8)
#define PW_SPI_SIRF_SIRFL_SHIFT 0x8
/* Threshold default value */
#define PW_SPI_WM_MASK BIT_MASK(6)
#define PW_SPI_SITF_LWMTF_SHIFT 0x8
#define PW_SPI_SITF_LOW_WM_DFLT BIT(PW_SPI_SITF_LWMTF_SHIFT)
#define PW_SPI_SITF_HIGH_WM_DFLT 0x20
#define PW_SPI_SIRF_WM_DFLT 0x28
/* Clocks */
#define PW_SPI_CLKS_EN_BIT BIT(0)
#define PW_SPI_CLKS_MVAL BIT(1)
#define PW_SPI_CLKS_NVAL BIT(16)
#define PW_SPI_CLKS_UPDATE_BIT BIT(31)
/* mval mask [15:1] */
#define PW_SPI_CLKS_MVAL_MASK (BIT_MASK(15) << 1)
/* nval mask [30:16] */
#define PW_SPI_CLKS_NVAL_MASK (BIT_MASK(15) << 16)
/* SPI chip select control */
#define PW_SPI_CS_MODE_BIT 0
#define PW_SPI_CS_STATE_BIT 1
#define PW_SPI_CS0_POL_BIT 12
#define PW_SPI_CS1_POL_BIT 13
/* ssp interrupt error bits */
#define PW_SPI_INTR_ERRORS_MASK (PW_SPI_SSSR_TUR_BIT | \
PW_SPI_SSSR_ROR_BIT | \
PW_SPI_SSSR_TINT_BIT)
/* ssp interrupt bits */
#define PW_SPI_INTR_BITS (PW_SPI_CTRL1_TIE_BIT | \
PW_SPI_CTRL1_RIE_BIT | \
PW_SPI_CTRL1_TINTE_BIT)
#define PW_SPI_INTR_MASK_TX (~(PW_SPI_CTRL1_TIE_BIT | \
PW_SPI_CTRL1_TINTE_BIT))
#define PW_SPI_INTR_MASK_RX (PW_SPI_CTRL1_RIE_BIT)
/* SSP & DMA reset */
#define PW_SPI_INST_RESET 0x7
/* Chip select control */
#define PW_SPI_CS_CTRL_SW_MODE BIT(0)
#define PW_SPI_CS_HIGH BIT(1)
#define PW_SPI_CS_LOW (~(PW_SPI_CS_HIGH))
#define PW_SPI_CS_CTRL_CS_MASK 0x3
#define PW_SPI_CS_EN_SHIFT 0x8
#define PW_SPI_CS0_SELECT (~(BIT(PW_SPI_CS_EN_SHIFT)))
#define PW_SPI_CS1_SELECT BIT(PW_SPI_CS_EN_SHIFT)
#define PW_SPI_CS_CTRL_HW_MODE (~(PW_SPI_CS_CTRL_SW_MODE))
#define PW_SPI_WIDTH_8BITS 8
#define PW_SPI_FRAME_SIZE_1_BYTE 1
#define PW_SPI_FRAME_SIZE_2_BYTES 2
#define PW_SPI_FRAME_SIZE_4_BYTES 4
#define PW_SPI_CS1_OUTPUT_SELECT 1
enum spi_pw_spo_sph_mode {
SPI_PW_MODE0 = 0,
SPI_PW_MODE1,
SPI_PW_MODE2,
SPI_PW_MODE3,
};
enum spi_pw_cs_mode {
CS_HW_MODE = 0,
CS_SW_MODE,
CS_GPIO_MODE,
};
struct spi_pw_config {
uint32_t id;
#ifdef CONFIG_SPI_PW_INTERRUPT
void (*irq_config)(const struct device *dev);
#endif
uint32_t clock_freq;
uint8_t op_modes;
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
struct pcie_dev *pcie;
#endif
};
struct spi_pw_data {
DEVICE_MMIO_RAM;
struct spi_context ctx;
uint8_t dfs;
uint8_t fifo_diff;
uint8_t cs_mode;
uint8_t cs_output;
uint32_t id;
uint8_t fifo_depth;
};
#endif /* ZEPHYR_DRIVERS_SPI_SPI_PW_H_ */
``` | /content/code_sandbox/drivers/spi/spi_pw.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,190 |
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