text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```c
/*
*
*/
#include <zephyr/drivers/usb/usb_bc12.h>
#include <zephyr/internal/syscall_handler.h>
static inline int z_vrfy_bc12_set_role(const struct device *dev, enum bc12_role role)
{
K_OOPS(K_SYSCALL_DRIVER_BC12(dev, set_role));
return z_impl_bc12_set_role(dev, role);
}
static inline int z_vrfy_bc12_set_result_cb(const struct device *dev, bc12_callback_t cb,
void *user_data)
{
K_OOPS(K_SYSCALL_DRIVER_BC12(dev, set_result_cb));
K_OOPS(K_SYSCALL_VERIFY_MSG(cb == NULL, "callbacks may not be set from user mode"));
return z_impl_bc12_set_result_cb(dev, cb, user_data);
}
``` | /content/code_sandbox/drivers/usb/bc12/bc12_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 163 |
```unknown
config USB_BC12_PI3USB9201
bool "Diodes PI3USB9201"
default y
depends on DT_HAS_DIODES_PI3USB9201_ENABLED
help
This is a Dual-Role USB Charging-Type Detector. It can operate in
host or client mode. It supports Battery Charging Specification, rev
1.2 (BC1.2) with Standard/Charging/Dedicated downstream port
(SDP/CDP/DCP) advertisement when in host mode. In portable device or
client mode it starts BC1.2 detection to detect the attached host
type. It provides an I2C interface to report detection results.
config EMUL_BC12_PI3USB9201
bool "Emulate a Pericom PI3USB9201 USB charging detector"
default y
depends on ZTEST && DT_HAS_DIODES_PI3USB9201_ENABLED
help
This is an emulator for the Pericom PI3USB9201 USB charging detector.
The backend API allows test code to force the type of the partner
charginging device.
if USB_BC12_PI3USB9201
config USB_BC12_PI3USB9201_CDP_ERRATA
bool "PI3USB9201 CDP Errata"
default y
help
When this option is enabled and the charging mode is configured for
CDP (Charging Downstream Port), after successful CDP detection the
driver automatically sets the charging mode to SDP (Standard
Downstream Port).
This is a workaround for a glitch seen on the USB data lines when
operating in CDP mode. Note that the BC1.2 negotiation compeletes
before switching to SDP mode, so the attached portable device can
continue to draw up to 1.5 A.
endif # USB_BC12_PI3USB9201
``` | /content/code_sandbox/drivers/usb/bc12/Kconfig.pi3usb9201 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 399 |
```c
/*
*
*
* Emulator for Diodes PI3USB9201 Dual-Role USB Charging-Type Detector.
*/
#include <zephyr/device.h>
#include <zephyr/drivers/emul.h>
#include <zephyr/drivers/gpio/gpio_emul.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c_emul.h>
#include <zephyr/drivers/usb/emul_bc12.h>
#include <zephyr/drivers/usb/usb_bc12.h>
#include <zephyr/logging/log.h>
#include <zephyr/ztest.h>
#include <bc12_pi3usb9201.h>
#define DT_DRV_COMPAT diodes_pi3usb9201
LOG_MODULE_REGISTER(emul_pi3usb9201, LOG_LEVEL_DBG);
#define IS_I2C_MSG_WRITE(flags) ((flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE)
#define IS_I2C_MSG_READ(flags) ((flags & I2C_MSG_RW_MASK) == I2C_MSG_READ)
#define EMUL_REG_COUNT (PI3USB9201_REG_HOST_STS + 1)
#define EMUL_REG_IS_VALID(reg) (reg >= 0 && reg < EMUL_REG_COUNT)
#define DCP_DETECTED BIT(7)
#define SDP_DETECTED BIT(6)
#define CDP_DETECTED BIT(5)
#define PROPRIETARY_1A_DETECTED BIT(3)
#define PROPRIETARY_2A_DETECTED BIT(2)
#define PROPRIETARY_2_4A_DETECTED BIT(1)
/** Run-time data used by the emulator */
struct pi3usb9201_emul_data {
/** pi3usb9201 device being emulated */
const struct device *i2c;
/** Configuration information */
const struct pi3usb9201_emul_cfg *cfg;
/** Current state of all emulated pi3usb9201 registers */
uint8_t reg[EMUL_REG_COUNT];
/** The current charging partner type requested by the test */
uint8_t test_client_status;
};
/** Static configuration for the emulator */
struct pi3usb9201_emul_cfg {
/** Pointer to run-time data */
struct pi3usb9201_emul_data *data;
/** Address of pi3usb9201 on i2c bus */
uint16_t addr;
/** GPIO connected to the INTB signal */
struct gpio_dt_spec intb_gpio;
};
static bool pi3usb9201_emul_interrupt_is_pending(const struct emul *target)
{
struct pi3usb9201_emul_data *data = target->data;
if (data->reg[PI3USB9201_REG_CTRL_1] & PI3USB9201_REG_CTRL_1_INT_MASK) {
/* Interrupt is masked */
return false;
}
if ((data->reg[PI3USB9201_REG_CTRL_2] & PI3USB9201_REG_CTRL_2_START_DET) &&
data->reg[PI3USB9201_REG_CLIENT_STS]) {
/* Cient detection is enabled and there are bits set in the
* client status register
*/
return true;
}
if (data->reg[PI3USB9201_REG_HOST_STS]) {
/* Any bits set in the host status register generate an interrupt */
return true;
}
return false;
}
static int pi3usb9201_emul_set_reg(const struct emul *target, int reg, uint8_t val)
{
struct pi3usb9201_emul_data *data = target->data;
const struct pi3usb9201_emul_cfg *cfg = target->cfg;
if (!EMUL_REG_IS_VALID(reg)) {
return -EIO;
}
data->reg[reg] = val;
/* Once the driver sets the operating mode to client, update the
* client status register with tests requested charging partner type
*/
if (reg == PI3USB9201_REG_CTRL_1) {
enum pi3usb9201_mode mode = val >> PI3USB9201_REG_CTRL_1_MODE_SHIFT;
mode &= PI3USB9201_REG_CTRL_1_MODE_MASK;
if (mode == PI3USB9201_CLIENT_MODE) {
data->reg[PI3USB9201_REG_CLIENT_STS] = data->test_client_status;
}
}
/* Check if an interrupt should be asserted */
if (pi3usb9201_emul_interrupt_is_pending(target)) {
gpio_emul_input_set(cfg->intb_gpio.port, cfg->intb_gpio.pin, 0);
}
return 0;
}
static int pi3usb9201_emul_get_reg(const struct emul *target, int reg, uint8_t *val)
{
struct pi3usb9201_emul_data *data = target->data;
const struct pi3usb9201_emul_cfg *cfg = target->cfg;
if (!EMUL_REG_IS_VALID(reg)) {
return -EIO;
}
*val = data->reg[reg];
/* Client/host status register clear on I2C read */
if ((reg == PI3USB9201_REG_CLIENT_STS) || (reg == PI3USB9201_REG_HOST_STS)) {
data->reg[reg] = 0;
/* Deassert the interrupt line when both client and host status are clear */
if (data->reg[PI3USB9201_REG_CLIENT_STS] == 0 &&
data->reg[PI3USB9201_REG_HOST_STS] == 0) {
gpio_emul_input_set(cfg->intb_gpio.port, cfg->intb_gpio.pin, 1);
}
}
return 0;
}
static void pi3usb9201_emul_reset(const struct emul *target)
{
struct pi3usb9201_emul_data *data = target->data;
const struct pi3usb9201_emul_cfg *cfg = target->cfg;
data->reg[PI3USB9201_REG_CTRL_1] = 0;
data->reg[PI3USB9201_REG_CTRL_2] = 0;
data->reg[PI3USB9201_REG_CLIENT_STS] = 0;
data->reg[PI3USB9201_REG_HOST_STS] = 0;
data->test_client_status = 0;
gpio_emul_input_set(cfg->intb_gpio.port, cfg->intb_gpio.pin, 1);
}
#define PI3USB9201_EMUL_RESET_RULE_BEFORE(inst) \
pi3usb9201_emul_reset(&EMUL_DT_NAME_GET(DT_DRV_INST(inst)));
static void emul_pi3usb9201_reset_before(const struct ztest_unit_test *test, void *data)
{
ARG_UNUSED(test);
ARG_UNUSED(data);
DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL_RESET_RULE_BEFORE)
}
ZTEST_RULE(emul_isl923x_reset, emul_pi3usb9201_reset_before, NULL);
/**
* Emulate an I2C transfer to a pi3usb9201
*
* This handles simple reads and writes
*
* @param target I2C emulation information
* @param msgs List of messages to process
* @param num_msgs Number of messages to process
* @param addr Address of the I2C target device
*
* @retval 0 If successful
* @retval -EIO General input / output error
*/
static int pi3usb9201_emul_transfer(const struct emul *target, struct i2c_msg *msgs, int num_msgs,
int addr)
{
const struct pi3usb9201_emul_cfg *cfg;
struct pi3usb9201_emul_data *data;
data = target->data;
cfg = data->cfg;
if (cfg->addr != addr) {
LOG_ERR("Address mismatch, expected %02x, got %02x", cfg->addr, addr);
return -EIO;
}
i2c_dump_msgs(target->dev, msgs, num_msgs, addr);
/* Only single byte register access permitted. Write operations must
* consist of 2 write bytes: register offset, register data. Read
* operations must consist 1 write byte (register offset) and 1 read
* byte (register data).
*/
if (num_msgs == 1) {
if (!(IS_I2C_MSG_WRITE(msgs[0].flags) && (msgs[0].len == 2))) {
LOG_ERR("Unexpected write msgs");
return -EIO;
}
return pi3usb9201_emul_set_reg(target, msgs[0].buf[0], msgs[0].buf[1]);
} else if (num_msgs == 2) {
if (!(IS_I2C_MSG_WRITE(msgs[0].flags) && (msgs[0].len == 1) &&
IS_I2C_MSG_READ(msgs[1].flags) && (msgs[1].len == 1))) {
LOG_ERR("Unexpected read msgs");
return -EIO;
}
return pi3usb9201_emul_get_reg(target, msgs[0].buf[0], &(msgs[1].buf[0]));
}
LOG_ERR("Unexpected num_msgs");
return -EIO;
}
int pi3usb9201_emul_set_charging_partner(const struct emul *target, enum bc12_type partner_type)
{
struct pi3usb9201_emul_data *data = target->data;
/* Set the client status matching the requested partner type */
switch (partner_type) {
case BC12_TYPE_NONE:
data->test_client_status = 0;
break;
case BC12_TYPE_SDP:
data->test_client_status = SDP_DETECTED;
break;
case BC12_TYPE_DCP:
data->test_client_status = DCP_DETECTED;
break;
case BC12_TYPE_CDP:
data->test_client_status = CDP_DETECTED;
break;
case BC12_TYPE_PROPRIETARY:
data->test_client_status = PROPRIETARY_1A_DETECTED;
break;
default:
LOG_ERR("Unsupported partner mode");
return -EINVAL;
}
return 0;
}
static int pi3usb9201_emul_set_pd_partner_state(const struct emul *target, bool connected)
{
struct pi3usb9201_emul_data *data = target->data;
const struct pi3usb9201_emul_cfg *cfg = target->cfg;
uint8_t mode;
mode = data->reg[PI3USB9201_REG_CTRL_1];
mode >>= PI3USB9201_REG_CTRL_1_MODE_SHIFT;
mode &= PI3USB9201_REG_CTRL_1_MODE_MASK;
/* Driver must be configured for host mode SDP/CDP */
if (mode != PI3USB9201_SDP_HOST_MODE && mode != PI3USB9201_CDP_HOST_MODE) {
return -EACCES;
}
if (connected) {
data->reg[PI3USB9201_REG_HOST_STS] |= PI3USB9201_REG_HOST_STS_DEV_PLUG;
} else {
data->reg[PI3USB9201_REG_HOST_STS] |= PI3USB9201_REG_HOST_STS_DEV_UNPLUG;
}
/* Interrupt are enabled - assert the interrupt */
if (!(data->reg[PI3USB9201_REG_CTRL_1] & PI3USB9201_REG_CTRL_1_INT_MASK)) {
gpio_emul_input_set(cfg->intb_gpio.port, cfg->intb_gpio.pin, 0);
}
return 0;
}
/* Device instantiation */
static struct i2c_emul_api pi3usb9201_emul_bus_api = {
.transfer = pi3usb9201_emul_transfer,
};
static const struct bc12_emul_driver_api pi3usb9201_emul_backend_api = {
.set_charging_partner = pi3usb9201_emul_set_charging_partner,
.set_pd_partner = pi3usb9201_emul_set_pd_partner_state,
};
/**
* @brief Set up a new pi3usb9201 emulator
*
* This should be called for each pi3usb9201 device that needs to be
* emulated. It registers it with the I2C emulation controller.
*
* @param target Emulation information
* @param parent Device to emulate
*
* @return 0 indicating success (always)
*/
static int pi3usb9201_emul_init(const struct emul *target, const struct device *parent)
{
const struct pi3usb9201_emul_cfg *cfg = target->cfg;
struct pi3usb9201_emul_data *data = cfg->data;
data->i2c = parent;
data->cfg = cfg;
LOG_INF("init");
pi3usb9201_emul_reset(target);
return 0;
}
#define PI3USB9201_EMUL(n) \
static struct pi3usb9201_emul_data pi3usb9201_emul_data_##n = {}; \
static const struct pi3usb9201_emul_cfg pi3usb9201_emul_cfg_##n = { \
.data = &pi3usb9201_emul_data_##n, \
.addr = DT_INST_REG_ADDR(n), \
.intb_gpio = GPIO_DT_SPEC_INST_GET_OR(n, intb_gpios, {0}), \
}; \
EMUL_DT_INST_DEFINE(n, pi3usb9201_emul_init, &pi3usb9201_emul_data_##n, \
&pi3usb9201_emul_cfg_##n, &pi3usb9201_emul_bus_api, \
&pi3usb9201_emul_backend_api)
DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL)
``` | /content/code_sandbox/drivers/usb/bc12/emul_bc12_pi3usb9201.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,914 |
```unknown
#
config DAC_SAM
bool "Atmel SAM DAC driver"
default y
depends on DT_HAS_ATMEL_SAM_DAC_ENABLED
help
Enable Atmel SAM MCU Family Digital Audio Converter (DAC) driver.
``` | /content/code_sandbox/drivers/dac/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
# DAC configuration options
#
config DAC_MCUX_DAC
bool "NXP Kinetis MCUX DAC driver"
default y
depends on DT_HAS_NXP_KINETIS_DAC_ENABLED
help
Enable the driver for the NXP Kinetis MCUX DAC.
config DAC_MCUX_DAC32
bool "NXP Kinetis MCUX DAC32 driver"
default y
depends on DT_HAS_NXP_KINETIS_DAC32_ENABLED
select PINCTRL
help
Enable the driver for the NXP Kinetis MCUX DAC32.
config DAC_MCUX_LPDAC
bool "NXP MCUX LPDAC driver"
default y
depends on DT_HAS_NXP_LPDAC_ENABLED
help
Enable the driver for the NXP MCUX LPDAC.
config DAC_MCUX_DAC32_TESTOUT
bool "DAC test output"
depends on DAC_MCUX_DAC32
help
Enable the DAC test output.
config DAC_MCUX_GAU
bool "NXP GAU DAC driver"
default y
depends on DT_HAS_NXP_GAU_DAC_ENABLED
help
Enable the driver for the NXP GAU DAC.
``` | /content/code_sandbox/drivers/dac/Kconfig.mcux | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 243 |
```c
/*
*
*/
#define DT_DRV_COMPAT st_stm32_dac
#include <errno.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <soc.h>
#include <stm32_ll_dac.h>
#define LOG_LEVEL CONFIG_DAC_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dac_stm32);
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
/* some low-end MCUs have DAC with only one channel */
#ifdef LL_DAC_CHANNEL_2
#define STM32_CHANNEL_COUNT 2
#else
#define STM32_CHANNEL_COUNT 1
#endif
/* first channel always named 1 */
#define STM32_FIRST_CHANNEL 1
#define CHAN(n) LL_DAC_CHANNEL_##n
static const uint32_t table_channels[] = {
CHAN(1),
#ifdef LL_DAC_CHANNEL_2
CHAN(2),
#endif
};
/* Read-only driver configuration */
struct dac_stm32_cfg {
/* DAC instance. */
DAC_TypeDef *base;
/* Clock configuration. */
struct stm32_pclken pclken;
/* pinctrl configurations. */
const struct pinctrl_dev_config *pcfg;
};
/* Runtime driver data */
struct dac_stm32_data {
uint8_t channel_count;
uint8_t resolution;
};
static int dac_stm32_write_value(const struct device *dev,
uint8_t channel, uint32_t value)
{
struct dac_stm32_data *data = dev->data;
const struct dac_stm32_cfg *cfg = dev->config;
if (channel - STM32_FIRST_CHANNEL >= data->channel_count ||
channel < STM32_FIRST_CHANNEL) {
LOG_ERR("Channel %d is not valid", channel);
return -EINVAL;
}
if (value >= BIT(data->resolution)) {
LOG_ERR("Value %d is out of range", value);
return -EINVAL;
}
if (data->resolution == 8) {
LL_DAC_ConvertData8RightAligned(cfg->base,
table_channels[channel - STM32_FIRST_CHANNEL], value);
} else if (data->resolution == 12) {
LL_DAC_ConvertData12RightAligned(cfg->base,
table_channels[channel - STM32_FIRST_CHANNEL], value);
}
return 0;
}
static int dac_stm32_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
struct dac_stm32_data *data = dev->data;
const struct dac_stm32_cfg *cfg = dev->config;
uint32_t output_buffer;
if ((channel_cfg->channel_id - STM32_FIRST_CHANNEL >=
data->channel_count) ||
(channel_cfg->channel_id < STM32_FIRST_CHANNEL)) {
LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
return -EINVAL;
}
if ((channel_cfg->resolution == 8) ||
(channel_cfg->resolution == 12)) {
data->resolution = channel_cfg->resolution;
} else {
LOG_ERR("Resolution not supported");
return -ENOTSUP;
}
if (channel_cfg->buffered) {
output_buffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
} else {
output_buffer = LL_DAC_OUTPUT_BUFFER_DISABLE;
}
LL_DAC_SetOutputBuffer(cfg->base,
table_channels[channel_cfg->channel_id - STM32_FIRST_CHANNEL],
output_buffer);
LL_DAC_Enable(cfg->base,
table_channels[channel_cfg->channel_id - STM32_FIRST_CHANNEL]);
LOG_DBG("Channel setup succeeded!");
return 0;
}
static int dac_stm32_init(const struct device *dev)
{
const struct dac_stm32_cfg *cfg = dev->config;
int err;
/* enable clock for subsystem */
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
if (!device_is_ready(clk)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
if (clock_control_on(clk,
(clock_control_subsys_t) &cfg->pclken) != 0) {
return -EIO;
}
/* Configure dt provided device signals when available */
err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {
LOG_ERR("DAC pinctrl setup failed (%d)", err);
return err;
}
return 0;
}
static const struct dac_driver_api api_stm32_driver_api = {
.channel_setup = dac_stm32_channel_setup,
.write_value = dac_stm32_write_value
};
#define STM32_DAC_INIT(index) \
\
PINCTRL_DT_INST_DEFINE(index); \
\
static const struct dac_stm32_cfg dac_stm32_cfg_##index = { \
.base = (DAC_TypeDef *)DT_INST_REG_ADDR(index), \
.pclken = { \
.enr = DT_INST_CLOCKS_CELL(index, bits), \
.bus = DT_INST_CLOCKS_CELL(index, bus), \
}, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
}; \
\
static struct dac_stm32_data dac_stm32_data_##index = { \
.channel_count = STM32_CHANNEL_COUNT \
}; \
\
DEVICE_DT_INST_DEFINE(index, &dac_stm32_init, NULL, \
&dac_stm32_data_##index, \
&dac_stm32_cfg_##index, POST_KERNEL, \
CONFIG_DAC_INIT_PRIORITY, \
&api_stm32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(STM32_DAC_INIT)
``` | /content/code_sandbox/drivers/dac/dac_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,239 |
```unknown
# DAC configuration options
#
config DAC_AD56XX
bool "Analog Devices AD56xx DAC driver"
default y
select SPI
depends on DT_HAS_ADI_AD5628_ENABLED \
|| DT_HAS_ADI_AD5648_ENABLED \
|| DT_HAS_ADI_AD5668_ENABLED \
|| DT_HAS_ADI_AD5672_ENABLED \
|| DT_HAS_ADI_AD5674_ENABLED \
|| DT_HAS_ADI_AD5676_ENABLED \
|| DT_HAS_ADI_AD5679_ENABLED \
|| DT_HAS_ADI_AD5684_ENABLED \
|| DT_HAS_ADI_AD5686_ENABLED \
|| DT_HAS_ADI_AD5687_ENABLED \
|| DT_HAS_ADI_AD5689_ENABLED
help
Enable the driver for the Analog Devices AD56xx DAC
if DAC_AD56XX
config DAC_AD56XX_INIT_PRIORITY
int "Init priority"
default 80
help
Analog Devices AD56xx DAC device driver initialization priority.
endif # DAC_AD56XX
``` | /content/code_sandbox/drivers/dac/Kconfig.ad56xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 221 |
```c
/*
*
*/
#include <stdint.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
LOG_MODULE_REGISTER(dac_ad56xx, CONFIG_DAC_LOG_LEVEL);
/*
* These values are actually all way less than 1us, but we can only
* wait with 1us precision.
*
* This should be checked when new types of this series are added to
* this implementation.
*/
#define DAC_AD56XX_MINIMUM_PULSE_WIDTH_LOW_IN_US 1
#define DAC_AD56XX_PULSE_ACTIVATION_TIME_IN_US 1
enum ad56xx_command {
AD56XX_CMD_WRITE_UPDATE_CHANNEL = 3,
AD56XX_CMD_SOFTWARE_RESET = 6,
};
struct ad56xx_config {
struct spi_dt_spec bus;
const struct gpio_dt_spec gpio_reset;
uint8_t resolution;
const uint8_t *channel_addresses;
size_t channel_count;
};
struct ad56xx_data {
};
static int ad56xx_write_command(const struct device *dev, enum ad56xx_command command,
uint8_t address, uint16_t value)
{
const struct ad56xx_config *config = dev->config;
uint8_t buffer_tx[3];
uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
const struct spi_buf tx_buf[] = {{
.buf = buffer_tx,
.len = ARRAY_SIZE(buffer_tx),
}};
const struct spi_buf rx_buf[] = {{
.buf = buffer_rx,
.len = ARRAY_SIZE(buffer_rx),
}};
const struct spi_buf_set tx = {
.buffers = tx_buf,
.count = ARRAY_SIZE(tx_buf),
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = ARRAY_SIZE(rx_buf),
};
buffer_tx[0] = (command << 4) | address;
value = value << (16 - config->resolution);
sys_put_be16(value, buffer_tx + 1);
LOG_DBG("sending to DAC %s command 0x%02X, address 0x%02X and value 0x%04X", dev->name,
command, address, value);
int result = spi_transceive_dt(&config->bus, &tx, &rx);
if (result != 0) {
LOG_ERR("spi_transceive failed with error %i", result);
return result;
}
return 0;
}
static int ad56xx_channel_setup(const struct device *dev, const struct dac_channel_cfg *channel_cfg)
{
const struct ad56xx_config *config = dev->config;
if (channel_cfg->channel_id >= config->channel_count) {
LOG_ERR("invalid channel %i", channel_cfg->channel_id);
return -EINVAL;
}
if (channel_cfg->resolution != config->resolution) {
LOG_ERR("invalid resolution %i", channel_cfg->resolution);
return -EINVAL;
}
return 0;
}
static int ad56xx_write_value(const struct device *dev, uint8_t channel, uint32_t value)
{
const struct ad56xx_config *config = dev->config;
if (value > BIT(config->resolution) - 1) {
LOG_ERR("invalid value %i", value);
return -EINVAL;
}
if (channel >= config->channel_count) {
LOG_ERR("invalid channel %i", channel);
return -EINVAL;
}
return ad56xx_write_command(dev, AD56XX_CMD_WRITE_UPDATE_CHANNEL,
config->channel_addresses[channel], value);
}
static int ad56xx_init(const struct device *dev)
{
const struct ad56xx_config *config = dev->config;
int result;
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
return -ENODEV;
}
if (config->gpio_reset.port != NULL) {
LOG_DBG("reset %s with GPIO", dev->name);
result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
if (result != 0) {
LOG_ERR("failed to initialize GPIO for reset");
return result;
}
k_busy_wait(DAC_AD56XX_MINIMUM_PULSE_WIDTH_LOW_IN_US);
gpio_pin_set_dt(&config->gpio_reset, 0);
} else {
LOG_DBG("reset %s with command", dev->name);
result = ad56xx_write_command(dev, AD56XX_CMD_SOFTWARE_RESET, 0, 0);
if (result != 0) {
LOG_ERR("failed to send reset command");
return result;
}
}
/*
* The pulse activation time is actually defined to start together
* with the pulse start. To be on the safe side we add the wait time
* on top of the actual pulse.
*/
k_busy_wait(DAC_AD56XX_PULSE_ACTIVATION_TIME_IN_US);
return 0;
}
static const struct dac_driver_api ad56xx_driver_api = {
.channel_setup = ad56xx_channel_setup,
.write_value = ad56xx_write_value,
};
BUILD_ASSERT(CONFIG_DAC_AD56XX_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY,
"CONFIG_DAC_AD56XX_INIT_PRIORITY must be higher than CONFIG_SPI_INIT_PRIORITY");
#define DAC_AD56XX_INST_DEFINE(index, name, res, channels, channels_count) \
static struct ad56xx_data data_##name##_##index; \
static const struct ad56xx_config config_##name##_##index = { \
.bus = SPI_DT_SPEC_INST_GET( \
index, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
.resolution = res, \
.gpio_reset = GPIO_DT_SPEC_INST_GET_OR(index, reset_gpios, {0}), \
.channel_addresses = channels, \
.channel_count = channels_count, \
}; \
DEVICE_DT_INST_DEFINE(index, ad56xx_init, NULL, &data_##name##_##index, \
&config_##name##_##index, POST_KERNEL, \
CONFIG_DAC_AD56XX_INIT_PRIORITY, &ad56xx_driver_api);
#define DT_DRV_COMPAT adi_ad5628
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5628_channels[] = {
0, 1, 2, 3, 4, 5, 6, 7,
};
#define DAC_AD5628_RESOLUTION 12
#define DAC_AD5628_CHANNELS ad5628_channels
#define DAC_AD5628_CHANNEL_COUNT ARRAY_SIZE(ad5628_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5628_RESOLUTION,
DAC_AD5628_CHANNELS, DAC_AD5628_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5648
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5648_channels[] = {
0, 1, 2, 3, 4, 5, 6, 7,
};
#define DAC_AD5648_RESOLUTION 14
#define DAC_AD5648_CHANNELS ad5648_channels
#define DAC_AD5648_CHANNEL_COUNT ARRAY_SIZE(ad5648_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5648_RESOLUTION,
DAC_AD5648_CHANNELS, DAC_AD5648_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5668
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5668_channels[] = {
0, 1, 2, 3, 4, 5, 6, 7,
};
#define DAC_AD5668_RESOLUTION 16
#define DAC_AD5668_CHANNELS ad5668_channels
#define DAC_AD5668_CHANNEL_COUNT ARRAY_SIZE(ad5668_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5668_RESOLUTION,
DAC_AD5668_CHANNELS, DAC_AD5668_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5672
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5672_channels[] = {
0, 1, 2, 3, 4, 5, 6, 7,
};
#define DAC_AD5672_RESOLUTION 12
#define DAC_AD5672_CHANNELS ad5672_channels
#define DAC_AD5672_CHANNEL_COUNT ARRAY_SIZE(ad5672_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5672_RESOLUTION,
DAC_AD5672_CHANNELS, DAC_AD5672_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5674
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5674_channels[] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
};
#define DAC_AD5674_RESOLUTION 12
#define DAC_AD5674_CHANNELS ad5674_channels
#define DAC_AD5674_CHANNEL_COUNT ARRAY_SIZE(ad5674_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5674_RESOLUTION,
DAC_AD5674_CHANNELS, DAC_AD5674_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5676
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5676_channels[] = {
0, 1, 2, 3, 4, 5, 6, 7,
};
#define DAC_AD5676_RESOLUTION 16
#define DAC_AD5676_CHANNELS ad5676_channels
#define DAC_AD5676_CHANNEL_COUNT ARRAY_SIZE(ad5676_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5676_RESOLUTION,
DAC_AD5676_CHANNELS, DAC_AD5676_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5679
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5679_channels[] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
};
#define DAC_AD5679_RESOLUTION 16
#define DAC_AD5679_CHANNELS ad5679_channels
#define DAC_AD5679_CHANNEL_COUNT ARRAY_SIZE(ad5679_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5679_RESOLUTION,
DAC_AD5679_CHANNELS, DAC_AD5679_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5684
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5684_channels[] = {
1,
2,
4,
8,
};
#define DAC_AD5684_RESOLUTION 12
#define DAC_AD5684_CHANNELS ad5684_channels
#define DAC_AD5684_CHANNEL_COUNT ARRAY_SIZE(ad5684_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5684_RESOLUTION,
DAC_AD5684_CHANNELS, DAC_AD5684_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5686
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5686_channels[] = {
1,
2,
4,
8,
};
#define DAC_AD5686_RESOLUTION 16
#define DAC_AD5686_CHANNELS ad5686_channels
#define DAC_AD5686_CHANNEL_COUNT ARRAY_SIZE(ad5686_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5686_RESOLUTION,
DAC_AD5686_CHANNELS, DAC_AD5686_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5687
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5687_channels[] = {
1,
8,
};
#define DAC_AD5687_RESOLUTION 12
#define DAC_AD5687_CHANNELS ad5687_channels
#define DAC_AD5687_CHANNEL_COUNT ARRAY_SIZE(ad5687_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5687_RESOLUTION,
DAC_AD5687_CHANNELS, DAC_AD5687_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5689
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
static const uint8_t ad5689_channels[] = {
1,
8,
};
#define DAC_AD5689_RESOLUTION 16
#define DAC_AD5689_CHANNELS ad5689_channels
#define DAC_AD5689_CHANNEL_COUNT ARRAY_SIZE(ad5689_channels)
DT_INST_FOREACH_STATUS_OKAY_VARGS(DAC_AD56XX_INST_DEFINE, DT_DRV_COMPAT, DAC_AD5689_RESOLUTION,
DAC_AD5689_CHANNELS, DAC_AD5689_CHANNEL_COUNT)
#endif
#undef DT_DRV_COMPAT
``` | /content/code_sandbox/drivers/dac/dac_ad56xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,893 |
```unknown
# DAC configuration options
#
config DAC_STM32
bool "STM32 DAC driver"
default y
depends on DT_HAS_ST_STM32_DAC_ENABLED
help
Enable the driver implementation for the stm32xx DAC
``` | /content/code_sandbox/drivers/dac/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```c
/*
*
*/
/**
* @file
* @brief DAC shell commands.
*/
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/dac.h>
#include <stdlib.h>
struct args_index {
uint8_t device;
uint8_t channel;
uint8_t value;
uint8_t resolution;
};
static const struct args_index args_indx = {
.device = 1,
.channel = 2,
.value = 3,
.resolution = 3,
};
static int cmd_setup(const struct shell *sh, size_t argc, char **argv)
{
struct dac_channel_cfg cfg;
const struct device *dac;
int err;
dac = device_get_binding(argv[args_indx.device]);
if (!dac) {
shell_error(sh, "DAC device not found");
return -EINVAL;
}
cfg.channel_id = strtoul(argv[args_indx.channel], NULL, 0);
cfg.resolution = strtoul(argv[args_indx.resolution], NULL, 0);
err = dac_channel_setup(dac, &cfg);
if (err) {
shell_error(sh, "Failed to setup DAC channel (err %d)", err);
return err;
}
return 0;
}
static int cmd_write_value(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dac;
uint8_t channel;
uint32_t value;
int err;
dac = device_get_binding(argv[args_indx.device]);
if (!dac) {
shell_error(sh, "DAC device not found");
return -EINVAL;
}
channel = strtoul(argv[args_indx.channel], NULL, 0);
value = strtoul(argv[args_indx.value], NULL, 0);
err = dac_write_value(dac, channel, value);
if (err) {
shell_error(sh, "Failed to write DAC value (err %d)", err);
return err;
}
return 0;
}
SHELL_STATIC_SUBCMD_SET_CREATE(dac_cmds,
SHELL_CMD_ARG(setup, NULL, "<device> <channel> <resolution>",
cmd_setup, 4, 0),
SHELL_CMD_ARG(write_value, NULL, "<device> <channel> <value>",
cmd_write_value, 4, 0),
SHELL_SUBCMD_SET_END
);
SHELL_CMD_REGISTER(dac, &dac_cmds, "DAC shell commands", NULL);
``` | /content/code_sandbox/drivers/dac/dac_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 491 |
```c
/*
*/
/** @file
* @brief DAC driver for Atmel SAM MCU family.
*
* Remarks:
* Only SAME70, SAMV71 series devices are currently supported. Please submit a
* patch.
*/
#define DT_DRV_COMPAT atmel_sam_dac
#include <errno.h>
#include <zephyr/sys/__assert.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(dac_sam, CONFIG_DAC_LOG_LEVEL);
BUILD_ASSERT(IS_ENABLED(CONFIG_SOC_SERIES_SAME70) ||
IS_ENABLED(CONFIG_SOC_SERIES_SAMV71),
"Only SAME70, SAMV71 series devices are currently supported.");
#define DAC_CHANNEL_NO 2
/* Device constant configuration parameters */
struct dac_sam_dev_cfg {
Dacc *regs;
const struct atmel_sam_pmc_config clock_cfg;
const struct pinctrl_dev_config *pcfg;
void (*irq_config)(void);
uint8_t irq_id;
uint8_t prescaler;
};
struct dac_channel {
struct k_sem sem;
};
/* Device run time data */
struct dac_sam_dev_data {
struct dac_channel dac_channels[DAC_CHANNEL_NO];
};
static void dac_sam_isr(const struct device *dev)
{
const struct dac_sam_dev_cfg *const dev_cfg = dev->config;
struct dac_sam_dev_data *const dev_data = dev->data;
Dacc *const dac = dev_cfg->regs;
uint32_t int_stat;
/* Retrieve interrupt status */
int_stat = dac->DACC_ISR & dac->DACC_IMR;
if ((int_stat & DACC_ISR_TXRDY0) != 0) {
/* Disable Transmit Ready Interrupt */
dac->DACC_IDR = DACC_IDR_TXRDY0;
k_sem_give(&dev_data->dac_channels[0].sem);
}
if ((int_stat & DACC_ISR_TXRDY1) != 0) {
/* Disable Transmit Ready Interrupt */
dac->DACC_IDR = DACC_IDR_TXRDY1;
k_sem_give(&dev_data->dac_channels[1].sem);
}
}
static int dac_sam_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
const struct dac_sam_dev_cfg *const dev_cfg = dev->config;
Dacc *const dac = dev_cfg->regs;
if (channel_cfg->channel_id >= DAC_CHANNEL_NO) {
return -EINVAL;
}
if (channel_cfg->resolution != 12) {
return -ENOTSUP;
}
/* Enable Channel */
dac->DACC_CHER = DACC_CHER_CH0 << channel_cfg->channel_id;
return 0;
}
static int dac_sam_write_value(const struct device *dev, uint8_t channel,
uint32_t value)
{
struct dac_sam_dev_data *const dev_data = dev->data;
const struct dac_sam_dev_cfg *const dev_cfg = dev->config;
Dacc *const dac = dev_cfg->regs;
if (channel >= DAC_CHANNEL_NO) {
return -EINVAL;
}
if (dac->DACC_IMR & (DACC_IMR_TXRDY0 << channel)) {
/* Attempting to send data on channel that's already in use */
return -EINVAL;
}
if (value >= BIT(12)) {
LOG_ERR("value %d out of range", value);
return -EINVAL;
}
k_sem_take(&dev_data->dac_channels[channel].sem, K_FOREVER);
/* Trigger conversion */
dac->DACC_CDR[channel] = DACC_CDR_DATA0(value);
/* Enable Transmit Ready Interrupt */
dac->DACC_IER = DACC_IER_TXRDY0 << channel;
return 0;
}
static int dac_sam_init(const struct device *dev)
{
const struct dac_sam_dev_cfg *const dev_cfg = dev->config;
struct dac_sam_dev_data *const dev_data = dev->data;
Dacc *const dac = dev_cfg->regs;
int retval;
/* Configure interrupts */
dev_cfg->irq_config();
/* Initialize semaphores */
for (int i = 0; i < ARRAY_SIZE(dev_data->dac_channels); i++) {
k_sem_init(&dev_data->dac_channels[i].sem, 1, 1);
}
/* Enable DAC clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t)&dev_cfg->clock_cfg);
retval = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (retval < 0) {
return retval;
}
/* Set Mode Register */
dac->DACC_MR = DACC_MR_PRESCALER(dev_cfg->prescaler);
/* Enable module's IRQ */
irq_enable(dev_cfg->irq_id);
LOG_INF("Device %s initialized", dev->name);
return 0;
}
static const struct dac_driver_api dac_sam_driver_api = {
.channel_setup = dac_sam_channel_setup,
.write_value = dac_sam_write_value,
};
/* DACC */
static void dacc_irq_config(void)
{
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), dac_sam_isr,
DEVICE_DT_INST_GET(0), 0);
}
PINCTRL_DT_INST_DEFINE(0);
static const struct dac_sam_dev_cfg dacc_sam_config = {
.regs = (Dacc *)DT_INST_REG_ADDR(0),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
.irq_id = DT_INST_IRQN(0),
.irq_config = dacc_irq_config,
.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(0),
.prescaler = DT_INST_PROP(0, prescaler),
};
static struct dac_sam_dev_data dacc_sam_data;
DEVICE_DT_INST_DEFINE(0, dac_sam_init, NULL, &dacc_sam_data, &dacc_sam_config,
POST_KERNEL, CONFIG_DAC_INIT_PRIORITY,
&dac_sam_driver_api);
``` | /content/code_sandbox/drivers/dac/dac_sam.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,349 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_gau_dac
#include <zephyr/drivers/dac.h>
#include <fsl_dac.h>
#define LOG_LEVEL CONFIG_DAC_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(nxp_gau_dac);
struct nxp_gau_dac_config {
DAC_Type *base;
dac_conversion_rate_t conversion_rate : 2;
dac_reference_voltage_source_t voltage_ref : 1;
dac_output_voltage_range_t output_range : 2;
};
static inline dac_channel_id_t convert_channel_id(uint8_t channel_id)
{
switch (channel_id) {
case 0: return kDAC_ChannelA;
case 1: return kDAC_ChannelB;
default:
LOG_ERR("Invalid DAC channel ID");
return -EINVAL;
};
}
static int nxp_gau_dac_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
const struct nxp_gau_dac_config *config = dev->config;
dac_channel_config_t dac_channel_config = {0};
if (channel_cfg->resolution != 10) {
LOG_ERR("DAC only support 10 bit resolution");
return -EINVAL;
}
if (channel_cfg->buffered) {
/* External and internal output are mutually exclusive */
LOG_WRN("Note: buffering DAC output to pad disconnects internal output");
}
dac_channel_config.waveType = kDAC_WaveNormal;
dac_channel_config.outMode = channel_cfg->buffered ?
kDAC_ChannelOutputPAD : kDAC_ChannelOutputInternal;
dac_channel_config.timingMode = kDAC_NonTimingCorrelated;
dac_channel_config.enableTrigger = false;
dac_channel_config.enableDMA = false;
dac_channel_config.enableConversion = true;
DAC_SetChannelConfig(config->base,
(uint32_t)convert_channel_id(channel_cfg->channel_id),
&dac_channel_config);
return 0;
};
static int nxp_gau_dac_write_value(const struct device *dev,
uint8_t channel, uint32_t value)
{
const struct nxp_gau_dac_config *config = dev->config;
DAC_SetChannelData(config->base,
(uint32_t)convert_channel_id(channel),
(uint16_t)value);
return 0;
};
static const struct dac_driver_api nxp_gau_dac_driver_api = {
.channel_setup = nxp_gau_dac_channel_setup,
.write_value = nxp_gau_dac_write_value,
};
static int nxp_gau_dac_init(const struct device *dev)
{
const struct nxp_gau_dac_config *config = dev->config;
dac_config_t dac_cfg;
DAC_GetDefaultConfig(&dac_cfg);
dac_cfg.conversionRate = config->conversion_rate;
dac_cfg.refSource = config->voltage_ref;
dac_cfg.rangeSelect = config->output_range;
DAC_Init(config->base, &dac_cfg);
return 0;
};
#define NXP_GAU_DAC_INIT(inst) \
\
const struct nxp_gau_dac_config nxp_gau_dac_##inst##_config = { \
.base = (DAC_Type *) DT_INST_REG_ADDR(inst), \
.voltage_ref = DT_INST_ENUM_IDX(inst, nxp_dac_reference), \
.conversion_rate = DT_INST_ENUM_IDX(inst, nxp_conversion_rate), \
.output_range = DT_INST_ENUM_IDX(inst, \
nxp_output_voltage_range), \
}; \
\
\
DEVICE_DT_INST_DEFINE(inst, &nxp_gau_dac_init, NULL, \
NULL, \
&nxp_gau_dac_##inst##_config, \
POST_KERNEL, CONFIG_DAC_INIT_PRIORITY, \
&nxp_gau_dac_driver_api);
DT_INST_FOREACH_STATUS_OKAY(NXP_GAU_DAC_INIT)
``` | /content/code_sandbox/drivers/dac/dac_mcux_gau.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 852 |
```unknown
config DAC_AD559X
bool "AD559x DAC driver"
default y
depends on DT_HAS_ADI_AD559X_DAC_ENABLED
select MFD
help
Enable the AD559x DAC driver.
``` | /content/code_sandbox/drivers/dac/Kconfig.ad559x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
# ESP32 DAC configuration options
config DAC_ESP32
bool "ESP32 DAC driver"
default y
depends on DT_HAS_ESPRESSIF_ESP32_DAC_ENABLED
help
Enable the ESP32 DAC driver
``` | /content/code_sandbox/drivers/dac/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```c
/*
*
*/
#include <zephyr/drivers/dac.h>
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/kernel.h>
static inline int z_vrfy_dac_channel_setup(const struct device *dev,
const struct dac_channel_cfg *user_channel_cfg)
{
struct dac_channel_cfg channel_cfg;
K_OOPS(K_SYSCALL_DRIVER_DAC(dev, channel_setup));
K_OOPS(k_usermode_from_copy(&channel_cfg,
(struct dac_channel_cfg *)user_channel_cfg,
sizeof(struct dac_channel_cfg)));
return z_impl_dac_channel_setup((const struct device *)dev,
&channel_cfg);
}
#include <zephyr/syscalls/dac_channel_setup_mrsh.c>
static inline int z_vrfy_dac_write_value(const struct device *dev,
uint8_t channel, uint32_t value)
{
K_OOPS(K_SYSCALL_DRIVER_DAC(dev, write_value));
return z_impl_dac_write_value((const struct device *)dev, channel,
value);
}
#include <zephyr/syscalls/dac_write_value_mrsh.c>
``` | /content/code_sandbox/drivers/dac/dac_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 225 |
```c
/*
*
*/
#define DT_DRV_COMPAT gd_gd32_dac
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/dac.h>
#include <gd32_dac.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dac_gd32, CONFIG_DAC_LOG_LEVEL);
/**
* For some gd32 series which only have 1 DAC, their HAL name may not same as others.
* Below definitions help to unify the HAL name.
*/
#if defined(CONFIG_SOC_SERIES_GD32A50X)
#define DAC_CTL_DEN0 DAC_CTL_DEN
#define DAC0_R8DH OUT_R8DH
#define DAC0_R12DH OUT_R12DH
#elif defined(CONFIG_SOC_SERIES_GD32F3X0)
#define DAC_CTL_DEN0 DAC_CTL_DEN
#define DAC0_R8DH DAC_R8DH
#define DAC0_R12DH DAC_R12DH
#endif
struct dac_gd32_config {
uint32_t reg;
uint16_t clkid;
struct reset_dt_spec reset;
const struct pinctrl_dev_config *pcfg;
uint32_t num_channels;
uint32_t reset_val;
};
struct dac_gd32_data {
uint8_t resolutions[2];
};
static void dac_gd32_enable(uint8_t dacx)
{
switch (dacx) {
case 0U:
DAC_CTL |= DAC_CTL_DEN0;
break;
#if DT_INST_PROP(0, num_channels) == 2
case 1U:
DAC_CTL |= DAC_CTL_DEN1;
break;
#endif
}
}
static void dac_gd32_disable(uint8_t dacx)
{
switch (dacx) {
case 0U:
DAC_CTL &= ~DAC_CTL_DEN0;
break;
#if DT_INST_PROP(0, num_channels) == 2
case 1U:
DAC_CTL &= ~DAC_CTL_DEN1;
break;
#endif
}
}
static void dac_gd32_write(struct dac_gd32_data *data,
uint8_t dacx, uint32_t value)
{
switch (dacx) {
case 0U:
if (data->resolutions[dacx] == 8U) {
DAC0_R8DH = value;
} else {
DAC0_R12DH = value;
}
break;
#if DT_INST_PROP(0, num_channels) == 2
case 1U:
if (data->resolutions[dacx] == 8U) {
DAC1_R8DH = value;
} else {
DAC1_R12DH = value;
}
break;
#endif
}
}
static int dac_gd32_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
struct dac_gd32_data *data = dev->data;
const struct dac_gd32_config *config = dev->config;
uint8_t dacx = channel_cfg->channel_id;
if (dacx >= config->num_channels) {
return -ENOTSUP;
}
/* GD32 DAC only support 8 or 12 bits resolution */
if ((channel_cfg->resolution != 8U) &&
(channel_cfg->resolution != 12U)) {
LOG_ERR("Only 8 and 12 bits resolutions are supported!");
return -ENOTSUP;
}
data->resolutions[dacx] = channel_cfg->resolution;
dac_gd32_disable(dacx);
dac_gd32_write(data, dacx, config->reset_val);
dac_gd32_enable(dacx);
return 0;
}
static int dac_gd32_write_value(const struct device *dev,
uint8_t dacx, uint32_t value)
{
struct dac_gd32_data *data = dev->data;
const struct dac_gd32_config *config = dev->config;
if (dacx >= config->num_channels) {
return -ENOTSUP;
}
dac_gd32_write(data, dacx, value);
return 0;
}
struct dac_driver_api dac_gd32_driver_api = {
.channel_setup = dac_gd32_channel_setup,
.write_value = dac_gd32_write_value
};
static int dac_gd32_init(const struct device *dev)
{
const struct dac_gd32_config *cfg = dev->config;
int ret;
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("Failed to apply pinctrl state");
return ret;
}
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);
return 0;
}
PINCTRL_DT_INST_DEFINE(0);
static struct dac_gd32_data dac_gd32_data_0;
static const struct dac_gd32_config dac_gd32_cfg_0 = {
.reg = DT_INST_REG_ADDR(0),
.clkid = DT_INST_CLOCKS_CELL(0, id),
.reset = RESET_DT_SPEC_INST_GET(0),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
.num_channels = DT_INST_PROP(0, num_channels),
.reset_val = DT_INST_PROP(0, reset_val),
};
DEVICE_DT_INST_DEFINE(0, &dac_gd32_init, NULL, &dac_gd32_data_0,
&dac_gd32_cfg_0, POST_KERNEL, CONFIG_DAC_INIT_PRIORITY,
&dac_gd32_driver_api);
``` | /content/code_sandbox/drivers/dac/dac_gd32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,223 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_dac
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/drivers/clock_control.h>
#include <hal/rtc_io_types.h>
#include <hal/rtc_io_hal.h>
#include <hal/rtc_io_ll.h>
#include "driver/dac.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(esp32_dac, CONFIG_DAC_LOG_LEVEL);
struct dac_esp32_config {
int irq_source;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
};
static int dac_esp32_write_value(const struct device *dev,
uint8_t channel, uint32_t value)
{
ARG_UNUSED(dev);
dac_output_voltage(channel, value);
return 0;
}
static int dac_esp32_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
ARG_UNUSED(dev);
if (channel_cfg->channel_id > SOC_DAC_CHAN_NUM) {
LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
return -EINVAL;
}
dac_output_enable(channel_cfg->channel_id);
return 0;
}
static int dac_esp32_init(const struct device *dev)
{
const struct dac_esp32_config *cfg = dev->config;
if (!cfg->clock_dev) {
LOG_ERR("Clock device missing");
return -EINVAL;
}
if (!device_is_ready(cfg->clock_dev)) {
LOG_ERR("Clock device not ready");
return -ENODEV;
}
if (clock_control_on(cfg->clock_dev,
(clock_control_subsys_t) &cfg->clock_subsys) != 0) {
LOG_ERR("DAC clock setup failed (%d)", -EIO);
return -EIO;
}
return 0;
}
static const struct dac_driver_api dac_esp32_driver_api = {
.channel_setup = dac_esp32_channel_setup,
.write_value = dac_esp32_write_value
};
#define ESP32_DAC_INIT(id) \
\
static const struct dac_esp32_config dac_esp32_config_##id = { \
.irq_source = DT_INST_IRQN(id), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
.clock_subsys = (clock_control_subsys_t) DT_INST_CLOCKS_CELL(id, offset), \
}; \
\
DEVICE_DT_INST_DEFINE(id, \
&dac_esp32_init, \
NULL, \
NULL, \
&dac_esp32_config_##id, \
POST_KERNEL, \
CONFIG_DAC_INIT_PRIORITY, \
&dac_esp32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(ESP32_DAC_INIT);
``` | /content/code_sandbox/drivers/dac/dac_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 625 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam0_dac
#include <errno.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dac_sam0, CONFIG_DAC_LOG_LEVEL);
/*
* Maps between the DTS reference property names and register values. Note that
* the ASF uses the 09/2015 names which differ from the 03/2020 datasheet.
*
* TODO(#21273): replace once improved support for enum values lands.
*/
#define SAM0_DAC_REFSEL_0 DAC_CTRLB_REFSEL_INT1V_Val
#define SAM0_DAC_REFSEL_1 DAC_CTRLB_REFSEL_AVCC_Val
#define SAM0_DAC_REFSEL_2 DAC_CTRLB_REFSEL_VREFP_Val
struct dac_sam0_cfg {
Dac *regs;
const struct pinctrl_dev_config *pcfg;
uint8_t pm_apbc_bit;
uint8_t gclk_clkctrl_id;
uint8_t refsel;
};
/* Write to the DAC. */
static int dac_sam0_write_value(const struct device *dev, uint8_t channel,
uint32_t value)
{
const struct dac_sam0_cfg *const cfg = dev->config;
Dac *regs = cfg->regs;
if (value >= BIT(12)) {
LOG_ERR("value %d out of range", value);
return -EINVAL;
}
regs->DATA.reg = (uint16_t)value;
return 0;
}
/*
* Setup the channel. As the SAM0 has one fixed width channel, this validates
* the input and does nothing else.
*/
static int dac_sam0_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
if (channel_cfg->channel_id != 0) {
return -EINVAL;
}
if (channel_cfg->resolution != 10) {
return -ENOTSUP;
}
return 0;
}
/* Initialise and enable the DAC. */
static int dac_sam0_init(const struct device *dev)
{
const struct dac_sam0_cfg *const cfg = dev->config;
Dac *regs = cfg->regs;
int retval;
/* Enable the GCLK */
GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_CLKEN;
retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (retval < 0) {
return retval;
}
/* Enable the clock in PM */
PM->APBCMASK.reg |= 1 << cfg->pm_apbc_bit;
/* Reset then configure the DAC */
regs->CTRLA.bit.SWRST = 1;
while (regs->STATUS.bit.SYNCBUSY) {
}
regs->CTRLB.bit.REFSEL = cfg->refsel;
regs->CTRLB.bit.EOEN = 1;
/* Enable */
regs->CTRLA.bit.ENABLE = 1;
while (regs->STATUS.bit.SYNCBUSY) {
}
return 0;
}
static const struct dac_driver_api api_sam0_driver_api = {
.channel_setup = dac_sam0_channel_setup,
.write_value = dac_sam0_write_value
};
#define SAM0_DAC_REFSEL(n) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, reference), \
(DT_INST_ENUM_IDX(n, reference)), (0))
#define SAM0_DAC_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static const struct dac_sam0_cfg dac_sam0_cfg_##n = { \
.regs = (Dac *)DT_INST_REG_ADDR(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.pm_apbc_bit = DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit), \
.gclk_clkctrl_id = \
DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id), \
.refsel = UTIL_CAT(SAM0_DAC_REFSEL_, SAM0_DAC_REFSEL(n)), \
}; \
\
DEVICE_DT_INST_DEFINE(n, &dac_sam0_init, NULL, NULL, \
&dac_sam0_cfg_##n, POST_KERNEL, \
CONFIG_DAC_INIT_PRIORITY, \
&api_sam0_driver_api)
DT_INST_FOREACH_STATUS_OKAY(SAM0_DAC_INIT);
``` | /content/code_sandbox/drivers/dac/dac_sam0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 969 |
```unknown
# DAC configuration options
#
config DAC_DACX0501
bool "TI DACx0501 DAC driver"
default y
depends on DT_HAS_TI_DACX0501_ENABLED
select I2C
help
Enable the driver for the TI DACx0501.
if DAC_DACX0501
config DAC_DACX0501_INIT_PRIORITY
int "Init priority"
default 80
help
TI DACx0501 DAC device driver initialization priority. Must be greater than I2C_INIT_PRIORITY.
endif # DAC_DACX0501
``` | /content/code_sandbox/drivers/dac/Kconfig.dacx0501 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_mcp4725
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dac_mcp4725, CONFIG_DAC_LOG_LEVEL);
/* Information in this file comes from MCP4725 datasheet revision D
* found at path_to_url
*/
/* Defines for field values in MCP4725 DAC register */
#define MCP4725_DAC_MAX_VAL 0xFFF
#define MCP4725_FAST_MODE_POWER_DOWN_POS 4U
#define MCP4725_FAST_MODE_DAC_UPPER_VAL_POS 8U
#define MCP4725_FAST_MODE_DAC_UPPER_VAL_MASK 0xF
#define MCP4725_FAST_MODE_DAC_LOWER_VAL_MASK 0xFF
#define MCP4725_READ_RDY_POS 7U
#define MCP4725_READ_RDY_MASK (0x1 << MCP4725_READ_RDY_POS)
/* After writing eeprom, the MCP4725 can be in a busy state for 25 - 50ms
* See section 1.0 of MCP4725 datasheet, 'Electrical Characteristics'
*/
#define MCP4725_BUSY_TIMEOUT_MS 60U
struct mcp4725_config {
struct i2c_dt_spec i2c;
};
/* Read mcp4725 and check RDY status bit */
static int mcp4725_wait_until_ready(const struct device *dev)
{
const struct mcp4725_config *config = dev->config;
uint8_t rx_data[5];
bool mcp4725_ready = false;
int ret;
int32_t timeout = k_uptime_get_32() + MCP4725_BUSY_TIMEOUT_MS;
/* Wait until RDY bit is set or return error if timer exceeds MCP4725_BUSY_TIMEOUT_MS */
while (!mcp4725_ready) {
ret = i2c_read_dt(&config->i2c, rx_data, sizeof(rx_data));
if (ret == 0) {
mcp4725_ready = rx_data[0] & MCP4725_READ_RDY_MASK;
} else {
/* I2C error */
return ret;
}
if (k_uptime_get_32() > timeout) {
return -ETIMEDOUT;
}
}
return 0;
}
/* MCP4725 is a single channel 12 bit DAC */
static int mcp4725_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
if (channel_cfg->channel_id != 0) {
return -EINVAL;
}
if (channel_cfg->resolution != 12) {
return -ENOTSUP;
}
return 0;
}
static int mcp4725_write_value(const struct device *dev, uint8_t channel,
uint32_t value)
{
const struct mcp4725_config *config = dev->config;
uint8_t tx_data[2];
int ret;
if (channel != 0) {
return -EINVAL;
}
/* Check value isn't over 12 bits */
if (value > MCP4725_DAC_MAX_VAL) {
return -ENOTSUP;
}
/* WRITE_MODE_FAST message format (2 bytes):
*
* || 15 14 | 13 12 | 11 10 9 8 || 7 6 5 4 3 2 1 0 ||
* || Fast mode (0) | Power-down bits (0) | DAC value[11:8] || DAC value[7:0] ||
*/
tx_data[0] = ((value >> MCP4725_FAST_MODE_DAC_UPPER_VAL_POS) &
MCP4725_FAST_MODE_DAC_UPPER_VAL_MASK);
tx_data[1] = (value & MCP4725_FAST_MODE_DAC_LOWER_VAL_MASK);
ret = i2c_write_dt(&config->i2c, tx_data, sizeof(tx_data));
return ret;
}
static int dac_mcp4725_init(const struct device *dev)
{
const struct mcp4725_config *config = dev->config;
if (!device_is_ready(config->i2c.bus)) {
LOG_ERR("I2C device not found");
return -EINVAL;
}
/* Check we can read a 'RDY' bit from this device */
if (mcp4725_wait_until_ready(dev)) {
return -EBUSY;
}
return 0;
}
static const struct dac_driver_api mcp4725_driver_api = {
.channel_setup = mcp4725_channel_setup,
.write_value = mcp4725_write_value,
};
#define INST_DT_MCP4725(index) \
static const struct mcp4725_config mcp4725_config_##index = { \
.i2c = I2C_DT_SPEC_INST_GET(index), \
}; \
\
DEVICE_DT_INST_DEFINE(index, dac_mcp4725_init, \
NULL, \
NULL, \
&mcp4725_config_##index, POST_KERNEL, \
CONFIG_DAC_MCP4725_INIT_PRIORITY, \
&mcp4725_driver_api);
DT_INST_FOREACH_STATUS_OKAY(INST_DT_MCP4725);
``` | /content/code_sandbox/drivers/dac/dac_mcp4725.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,123 |
```c
/*
*/
#define DT_DRV_COMPAT adi_ad559x_dac
#include <zephyr/drivers/dac.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/mfd/ad559x.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dac_ad559x, CONFIG_DAC_LOG_LEVEL);
#define AD559X_DAC_RESOLUTION 12
#define AD559X_DAC_WR_POINTER 0x10
#define AD559X_DAC_WR_MSB_BIT BIT(15)
#define AD559X_DAC_CHANNEL_SHIFT_VAL 12
struct dac_ad559x_config {
const struct device *mfd_dev;
};
struct dac_ad559x_data {
uint8_t dac_conf;
};
static int dac_ad559x_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
const struct dac_ad559x_config *config = dev->config;
struct dac_ad559x_data *data = dev->data;
if (channel_cfg->channel_id >= AD559X_PIN_MAX) {
LOG_ERR("Invalid channel number %d", channel_cfg->channel_id);
return -EINVAL;
}
if (channel_cfg->resolution != AD559X_DAC_RESOLUTION) {
LOG_ERR("Invalid resolution %d", channel_cfg->resolution);
return -EINVAL;
}
data->dac_conf |= BIT(channel_cfg->channel_id);
return mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_LDAC_EN, data->dac_conf);
}
static int dac_ad559x_write_value(const struct device *dev, uint8_t channel, uint32_t value)
{
const struct dac_ad559x_config *config = dev->config;
uint16_t msg;
if (channel >= AD559X_PIN_MAX) {
LOG_ERR("Invalid channel number %d", channel);
return -EINVAL;
}
if (value >= (1 << AD559X_DAC_RESOLUTION)) {
LOG_ERR("Value %d out of range", value);
return -EINVAL;
}
if (mfd_ad559x_has_pointer_byte_map(config->mfd_dev)) {
return mfd_ad559x_write_reg(config->mfd_dev, AD559X_DAC_WR_POINTER | channel,
value);
} else {
msg = sys_cpu_to_be16(AD559X_DAC_WR_MSB_BIT |
channel << AD559X_DAC_CHANNEL_SHIFT_VAL | value);
return mfd_ad559x_write_raw(config->mfd_dev, (uint8_t *)&msg, sizeof(msg));
}
}
static const struct dac_driver_api dac_ad559x_api = {
.channel_setup = dac_ad559x_channel_setup,
.write_value = dac_ad559x_write_value,
};
static int dac_ad559x_init(const struct device *dev)
{
const struct dac_ad559x_config *config = dev->config;
int ret;
if (!device_is_ready(config->mfd_dev)) {
return -ENODEV;
}
ret = mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_PD_REF_CTRL, AD559X_EN_REF);
if (ret < 0) {
return ret;
}
return 0;
}
#define DAC_AD559X_DEFINE(inst) \
static const struct dac_ad559x_config dac_ad559x_config##inst = { \
.mfd_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
}; \
\
struct dac_ad559x_data dac_ad559x_data##inst; \
\
DEVICE_DT_INST_DEFINE(inst, dac_ad559x_init, NULL, &dac_ad559x_data##inst, \
&dac_ad559x_config##inst, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \
&dac_ad559x_api);
DT_INST_FOREACH_STATUS_OKAY(DAC_AD559X_DEFINE)
``` | /content/code_sandbox/drivers/dac/dac_ad559x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 813 |
```unknown
config DAC_AD569X
bool "Analog Devices AD5691 / AD5692 / AD5693 DAC driver"
default y
select I2C
depends on DT_HAS_ADI_AD5691_ENABLED || DT_HAS_ADI_AD5692_ENABLED || DT_HAS_ADI_AD5693_ENABLED
help
Enable the driver for the Analog Devices AD569X.
``` | /content/code_sandbox/drivers/dac/Kconfig.ad569x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
# DAC configuration options
#
config DAC_GD32
bool "GD32 DAC driver"
default y
depends on DT_HAS_GD_GD32_DAC_ENABLED
help
Enable GigaDevice GD32 DAC driver
``` | /content/code_sandbox/drivers/dac/Kconfig.gd32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/logging/log.h>
#include <zephyr/dt-bindings/dac/dacx0508.h>
LOG_MODULE_REGISTER(dac_dacx0508, CONFIG_DAC_LOG_LEVEL);
#define DACX0508_REG_DEVICE_ID 0x01U
#define DACX0508_REG_CONFIG 0x03U
#define DACX0508_REG_GAIN 0x04U
#define DACX0508_REG_TRIGGER 0x05U
#define DACX0508_REG_STATUS 0x07U
#define DACX0508_REG_DAC0 0x08U
#define DACX0508_MASK_DEVICE_ID_8CH BIT(11)
#define DACX0508_MASK_CONFIG_REF_PWDWN BIT(8)
#define DACX0508_MASK_GAIN_BUFF_GAIN(x) BIT(x)
#define DACX0508_MASK_GAIN_REFDIV_EN BIT(8)
#define DACX0508_MASK_TRIGGER_SOFT_RESET (BIT(1) | BIT(3))
#define DACX0508_MASK_STATUS_REF_ALM BIT(0)
#define DACX0508_READ_CMD 0x80
#define DACX0508_POR_DELAY 250
#define DACX0508_MAX_CHANNEL 8
struct dacx0508_config {
struct spi_dt_spec bus;
uint8_t resolution;
uint8_t reference;
uint8_t gain[8];
};
struct dacx0508_data {
uint8_t configured;
};
static int dacx0508_reg_read(const struct device *dev, uint8_t addr,
uint8_t *data)
{
const struct dacx0508_config *config = dev->config;
const struct spi_buf buf[2] = {
{
.buf = &addr,
.len = sizeof(addr)
},
{
.buf = data,
.len = 2
}
};
struct spi_buf_set tx = {
.buffers = buf,
.count = ARRAY_SIZE(buf),
};
struct spi_buf_set rx = {
.buffers = buf,
.count = ARRAY_SIZE(buf)
};
uint8_t tmp;
int ret;
if (k_is_in_isr()) {
/* Prevent SPI transactions from an ISR */
return -EWOULDBLOCK;
}
tmp = addr |= DACX0508_READ_CMD;
ret = spi_write_dt(&config->bus, &tx);
if (ret) {
return ret;
}
ret = spi_read_dt(&config->bus, &rx);
if (ret) {
return ret;
}
if (addr != tmp) {
return -EIO;
}
return 0;
}
static int dacx0508_reg_write(const struct device *dev, uint8_t addr,
uint8_t *data)
{
const struct dacx0508_config *config = dev->config;
const struct spi_buf buf[2] = {
{
.buf = &addr,
.len = sizeof(addr)
},
{
.buf = data,
.len = 2
}
};
struct spi_buf_set tx = {
.buffers = buf,
.count = ARRAY_SIZE(buf),
};
if (k_is_in_isr()) {
/* Prevent SPI transactions from an ISR */
return -EWOULDBLOCK;
}
return spi_write_dt(&config->bus, &tx);
}
int dacx0508_reg_update(const struct device *dev, uint8_t addr,
uint16_t mask, bool setting)
{
uint8_t regval[2] = {0, };
uint16_t tmp;
int ret;
ret = dacx0508_reg_read(dev, addr, regval);
if (ret < 0) {
return ret;
}
tmp = (regval[0] << 8) | regval[1];
if (setting) {
tmp |= mask;
} else {
tmp &= ~mask;
}
regval[0] = tmp >> 8;
regval[1] = tmp & 0xFF;
ret = dacx0508_reg_write(dev, addr, regval);
if (ret) {
return ret;
}
return 0;
}
static int dacx0508_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
const struct dacx0508_config *config = dev->config;
struct dacx0508_data *data = dev->data;
if (channel_cfg->channel_id > DACX0508_MAX_CHANNEL - 1) {
LOG_ERR("Unsupported channel %d", channel_cfg->channel_id);
return -ENOTSUP;
}
if (channel_cfg->resolution != config->resolution) {
LOG_ERR("Unsupported resolution %d", channel_cfg->resolution);
return -ENOTSUP;
}
data->configured |= BIT(channel_cfg->channel_id);
return 0;
}
static int dacx0508_write_value(const struct device *dev, uint8_t channel,
uint32_t value)
{
const struct dacx0508_config *config = dev->config;
struct dacx0508_data *data = dev->data;
uint8_t regval[2];
int ret;
if (channel > DACX0508_MAX_CHANNEL - 1) {
LOG_ERR("unsupported channel %d", channel);
return -ENOTSUP;
}
if (!(data->configured & BIT(channel))) {
LOG_ERR("Channel not initialized");
return -EINVAL;
}
if (value >= (1 << config->resolution)) {
LOG_ERR("Value %d out of range", value);
return -EINVAL;
}
value <<= (16 - config->resolution);
regval[0] = value >> 8;
regval[1] = value & 0xFF;
ret = dacx0508_reg_write(dev, DACX0508_REG_DAC0 + channel, regval);
if (ret) {
return -EIO;
}
return 0;
}
static int dacx0508_soft_reset(const struct device *dev)
{
uint8_t regval[2] = {0, DACX0508_MASK_TRIGGER_SOFT_RESET};
int ret;
ret = dacx0508_reg_write(dev, DACX0508_REG_TRIGGER, regval);
if (ret) {
return -EIO;
}
k_usleep(DACX0508_POR_DELAY);
return 0;
}
static int dacx0508_device_id_check(const struct device *dev)
{
const struct dacx0508_config *config = dev->config;
uint8_t regval[2] = {0, };
uint8_t resolution;
uint16_t dev_id;
int ret;
ret = dacx0508_reg_read(dev, DACX0508_REG_DEVICE_ID, regval);
if (ret) {
LOG_ERR("Unable to read Device ID");
return -EIO;
}
dev_id = (regval[0] << 8) | regval[1];
resolution = dev_id >> 12;
if (resolution != (16 - config->resolution) >> 1) {
LOG_ERR("Not match chip resolution");
return -EINVAL;
}
if ((dev_id & DACX0508_MASK_DEVICE_ID_8CH) !=
DACX0508_MASK_DEVICE_ID_8CH) {
LOG_ERR("Support channels mismatch");
return -EINVAL;
}
return 0;
}
static int dacx0508_setup(const struct device *dev)
{
const struct dacx0508_config *config = dev->config;
uint8_t regval[2] = {0, }, tmp = 0;
bool ref_pwdwn, refdiv_en;
int ret;
switch (config->reference) {
case DACX0508_REF_INTERNAL_1:
ref_pwdwn = false;
refdiv_en = false;
break;
case DACX0508_REF_INTERNAL_1_2:
ref_pwdwn = false;
refdiv_en = true;
break;
case DACX0508_REF_EXTERNAL_1:
ref_pwdwn = true;
refdiv_en = false;
break;
case DACX0508_REF_EXTERNAL_1_2:
ref_pwdwn = true;
refdiv_en = true;
break;
default:
LOG_ERR("unsupported channel reference type '%d'",
config->reference);
return -ENOTSUP;
}
ret = dacx0508_reg_update(dev, DACX0508_REG_CONFIG,
DACX0508_MASK_CONFIG_REF_PWDWN, ref_pwdwn);
if (ret) {
LOG_ERR("GAIN Register update failed");
return -EIO;
}
ret = dacx0508_reg_update(dev, DACX0508_REG_GAIN,
DACX0508_MASK_GAIN_REFDIV_EN, refdiv_en);
if (ret) {
LOG_ERR("GAIN Register update failed");
return -EIO;
}
for (int i = 0; i < 8; i++) {
tmp |= config->gain[i] << i;
}
ret = dacx0508_reg_read(dev, DACX0508_REG_GAIN, regval);
if (ret) {
LOG_ERR("Unable to read GAIN Register");
return -EIO;
}
regval[1] = tmp;
ret = dacx0508_reg_write(dev, DACX0508_REG_GAIN, regval);
if (ret) {
LOG_ERR("Unable to write GAIN Register");
return -EIO;
}
ret = dacx0508_reg_read(dev, DACX0508_REG_STATUS, regval);
if (ret) {
LOG_ERR("Unable to read STATUS Register");
return -EIO;
}
if ((regval[1] & DACX0508_MASK_STATUS_REF_ALM) ==
DACX0508_MASK_STATUS_REF_ALM) {
LOG_ERR("Difference between VREF/DIV and VDD is "
"below the required minimum analog threshold");
return -EIO;
}
return 0;
}
static int dacx0508_init(const struct device *dev)
{
const struct dacx0508_config *config = dev->config;
struct dacx0508_data *data = dev->data;
int ret;
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
return -ENODEV;
}
ret = dacx0508_soft_reset(dev);
if (ret) {
LOG_ERR("Soft-reset failed");
return ret;
}
ret = dacx0508_device_id_check(dev);
if (ret) {
return ret;
}
ret = dacx0508_setup(dev);
if (ret) {
return ret;
}
data->configured = 0;
return 0;
}
static const struct dac_driver_api dacx0508_driver_api = {
.channel_setup = dacx0508_channel_setup,
.write_value = dacx0508_write_value,
};
#define INST_DT_DACX0508(inst, t) DT_INST(inst, ti_dac##t)
#define DACX0508_DEVICE(t, n, res) \
static struct dacx0508_data dac##t##_data_##n; \
static const struct dacx0508_config dac##t##_config_##n = { \
.bus = SPI_DT_SPEC_GET(INST_DT_DACX0508(n, t), \
SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | \
SPI_WORD_SET(8) | SPI_MODE_CPHA, 0), \
.resolution = res, \
.reference = DT_PROP(INST_DT_DACX0508(n, t), \
voltage_reference), \
.gain[0] = DT_PROP(INST_DT_DACX0508(n, t), channel0_gain), \
.gain[1] = DT_PROP(INST_DT_DACX0508(n, t), channel1_gain), \
.gain[2] = DT_PROP(INST_DT_DACX0508(n, t), channel2_gain), \
.gain[3] = DT_PROP(INST_DT_DACX0508(n, t), channel3_gain), \
.gain[4] = DT_PROP(INST_DT_DACX0508(n, t), channel4_gain), \
.gain[5] = DT_PROP(INST_DT_DACX0508(n, t), channel5_gain), \
.gain[6] = DT_PROP(INST_DT_DACX0508(n, t), channel6_gain), \
.gain[7] = DT_PROP(INST_DT_DACX0508(n, t), channel7_gain), \
}; \
DEVICE_DT_DEFINE(INST_DT_DACX0508(n, t), \
&dacx0508_init, NULL, \
&dac##t##_data_##n, \
&dac##t##_config_##n, POST_KERNEL, \
CONFIG_DAC_DACX0508_INIT_PRIORITY, \
&dacx0508_driver_api);
/*
* DAC60508: 12-bit
*/
#define DAC60508_DEVICE(n) DACX0508_DEVICE(60508, n, 12)
/*
* DAC70508: 14-bit
*/
#define DAC70508_DEVICE(n) DACX0508_DEVICE(70508, n, 14)
/*
* DAC80508: 16-bit
*/
#define DAC80508_DEVICE(n) DACX0508_DEVICE(80508, n, 16)
#define CALL_WITH_ARG(arg, expr) expr(arg)
#define INST_DT_DACX0508_FOREACH(t, inst_expr) \
LISTIFY(DT_NUM_INST_STATUS_OKAY(ti_dac##t), \
CALL_WITH_ARG, (), inst_expr)
INST_DT_DACX0508_FOREACH(60508, DAC60508_DEVICE);
INST_DT_DACX0508_FOREACH(70508, DAC70508_DEVICE);
INST_DT_DACX0508_FOREACH(80508, DAC80508_DEVICE);
``` | /content/code_sandbox/drivers/dac/dac_dacx0508.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,981 |
```unknown
# DAC configuration options
#
config DAC_DACX0508
bool "TI DACx0508 DAC driver"
default y
select SPI
depends on DT_HAS_TI_DAC60508_ENABLED || DT_HAS_TI_DAC70508_ENABLED || \
DT_HAS_TI_DAC80508_ENABLED
help
Enable the driver for the TI DACx0508.
if DAC_DACX0508
config DAC_DACX0508_INIT_PRIORITY
int "Init priority"
default 80
help
TI DACx0508 DAC device driver initialization priority.
endif # DAC_DACX0508
``` | /content/code_sandbox/drivers/dac/Kconfig.dacx0508 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 120 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dac_dacx3608, CONFIG_DAC_LOG_LEVEL);
/* Register addresses */
#define DACX3608_REG_DEVICE_CONFIG 0x01U
#define DACX3608_REG_STATUS_TRIGGER 0x02U
#define DACX3608_REG_BRDCAST 0x03U
#define DACX3608_REG_DACA_DATA 0x08U
#define DAC43608_DEVICE_ID 0x500 /* STATUS_TRIGGER[DEVICE_ID] */
#define DAC53608_DEVICE_ID 0x300 /* STATUS_TRIGGER[DEVICE_ID] */
#define DACX3608_SW_RST 0x0A /* STATUS_TRIGGER[SW_RST] */
#define DACX3608_POR_DELAY 5
#define DACX3608_MAX_CHANNEL 8
struct dacx3608_config {
struct i2c_dt_spec bus;
uint8_t resolution;
};
struct dacx3608_data {
uint8_t configured;
};
static int dacx3608_reg_read(const struct device *dev, uint8_t reg,
uint16_t *val)
{
const struct dacx3608_config *cfg = dev->config;
if (i2c_burst_read_dt(&cfg->bus, reg, (uint8_t *) val, 2) < 0) {
LOG_ERR("I2C read failed");
return -EIO;
}
*val = sys_be16_to_cpu(*val);
return 0;
}
static int dacx3608_reg_write(const struct device *dev, uint8_t reg,
uint16_t val)
{
const struct dacx3608_config *cfg = dev->config;
uint8_t buf[3] = {reg, val >> 8, val & 0xFF};
return i2c_write_dt(&cfg->bus, buf, sizeof(buf));
}
int dacx3608_reg_update(const struct device *dev, uint8_t reg,
uint16_t mask, bool setting)
{
uint16_t regval;
int ret;
ret = dacx3608_reg_read(dev, reg, ®val);
if (ret) {
return -EIO;
}
if (setting) {
regval |= mask;
} else {
regval &= ~mask;
}
ret = dacx3608_reg_write(dev, reg, regval);
if (ret) {
return ret;
}
return 0;
}
static int dacx3608_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
const struct dacx3608_config *config = dev->config;
struct dacx3608_data *data = dev->data;
bool setting = false;
int ret;
if (channel_cfg->channel_id > DACX3608_MAX_CHANNEL - 1) {
LOG_ERR("Unsupported channel %d", channel_cfg->channel_id);
return -ENOTSUP;
}
if (channel_cfg->resolution != config->resolution) {
LOG_ERR("Unsupported resolution %d", channel_cfg->resolution);
return -ENOTSUP;
}
if (data->configured & BIT(channel_cfg->channel_id)) {
LOG_DBG("Channel %d already configured", channel_cfg->channel_id);
return 0;
}
/* Clear PDNn bit */
ret = dacx3608_reg_update(dev, DACX3608_REG_DEVICE_CONFIG,
BIT(channel_cfg->channel_id), setting);
if (ret) {
LOG_ERR("Unable to update DEVICE_CONFIG register");
return -EIO;
}
data->configured |= BIT(channel_cfg->channel_id);
LOG_DBG("Channel %d initialized", channel_cfg->channel_id);
return 0;
}
static int dacx3608_write_value(const struct device *dev, uint8_t channel,
uint32_t value)
{
const struct dacx3608_config *config = dev->config;
struct dacx3608_data *data = dev->data;
uint16_t regval;
int ret;
if (channel > DACX3608_MAX_CHANNEL - 1) {
LOG_ERR("Unsupported channel %d", channel);
return -ENOTSUP;
}
if (!(data->configured & BIT(channel))) {
LOG_ERR("Channel %d not initialized", channel);
return -EINVAL;
}
if (value >= (1 << (config->resolution))) {
LOG_ERR("Value %d out of range", value);
return -EINVAL;
}
/*
* Shift passed value two times left because first two bits are Don't Care
*
* DACn_DATA register format:
*
* | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 | 1 0 |
* |-------------|---------------------------------|------------|
* | Don't Care | DAC53608[9:0] / DAC43608[7:0] | Don't Care |
*/
regval = value << 2;
regval &= 0xFFFF;
ret = dacx3608_reg_write(dev, DACX3608_REG_DACA_DATA + channel, regval);
if (ret) {
LOG_ERR("Unable to set value %d on channel %d", value, channel);
return -EIO;
}
return 0;
}
static int dacx3608_soft_reset(const struct device *dev)
{
uint16_t regval = DACX3608_SW_RST;
int ret;
ret = dacx3608_reg_write(dev, DACX3608_REG_STATUS_TRIGGER, regval);
if (ret) {
return -EIO;
}
k_msleep(DACX3608_POR_DELAY);
return 0;
}
static int dacx3608_device_id_check(const struct device *dev)
{
uint16_t dev_id;
int ret;
ret = dacx3608_reg_read(dev, DACX3608_REG_STATUS_TRIGGER, &dev_id);
if (ret) {
LOG_ERR("Unable to read device ID");
return -EIO;
}
switch (dev_id) {
case DAC43608_DEVICE_ID:
case DAC53608_DEVICE_ID:
LOG_DBG("Device ID %#4x", dev_id);
break;
default:
LOG_ERR("Unknown Device ID %#4x", dev_id);
return -EIO;
}
return 0;
}
static int dacx3608_init(const struct device *dev)
{
const struct dacx3608_config *config = dev->config;
struct dacx3608_data *data = dev->data;
int ret;
if (!device_is_ready(config->bus.bus)) {
LOG_ERR("I2C device not ready");
return -ENODEV;
}
ret = dacx3608_soft_reset(dev);
if (ret) {
LOG_ERR("Soft-reset failed");
return ret;
}
ret = dacx3608_device_id_check(dev);
if (ret) {
return ret;
}
data->configured = 0;
LOG_DBG("Init complete");
return 0;
}
static const struct dac_driver_api dacx3608_driver_api = {
.channel_setup = dacx3608_channel_setup,
.write_value = dacx3608_write_value,
};
#define INST_DT_DACX3608(inst, t) DT_INST(inst, ti_dac##t)
#define DACX3608_DEVICE(t, n, res) \
static struct dacx3608_data dac##t##_data_##n; \
static const struct dacx3608_config dac##t##_config_##n = { \
.bus = I2C_DT_SPEC_GET(INST_DT_DACX3608(n, t)), \
.resolution = res, \
}; \
DEVICE_DT_DEFINE(INST_DT_DACX3608(n, t), \
&dacx3608_init, NULL, \
&dac##t##_data_##n, \
&dac##t##_config_##n, POST_KERNEL, \
CONFIG_DAC_DACX3608_INIT_PRIORITY, \
&dacx3608_driver_api)
/*
* DAC43608: 8-bit
*/
#define DAC43608_DEVICE(n) DACX3608_DEVICE(43608, n, 8)
/*
* DAC53608: 10-bit
*/
#define DAC53608_DEVICE(n) DACX3608_DEVICE(53608, n, 10)
#define CALL_WITH_ARG(arg, expr) expr(arg)
#define INST_DT_DACX3608_FOREACH(t, inst_expr) \
LISTIFY(DT_NUM_INST_STATUS_OKAY(ti_dac##t), \
CALL_WITH_ARG, (), inst_expr)
INST_DT_DACX3608_FOREACH(43608, DAC43608_DEVICE);
INST_DT_DACX3608_FOREACH(53608, DAC53608_DEVICE);
``` | /content/code_sandbox/drivers/dac/dac_dacx3608.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,916 |
```c
/*
* Driver for Linear Technology LTC1660/LTC1665 DAC
*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dac_ltc166x, CONFIG_DAC_LOG_LEVEL);
#define LTC166X_REG_MASK GENMASK(15, 12)
#define LTC166X_DATA8_MASK GENMASK(11, 4)
#define LTC166X_DATA10_MASK GENMASK(12, 2)
struct ltc166x_config {
struct spi_dt_spec bus;
uint8_t resolution;
uint8_t nchannels;
};
static int ltc166x_reg_write(const struct device *dev, uint8_t addr,
uint32_t data)
{
const struct ltc166x_config *config = dev->config;
uint16_t regval;
regval = FIELD_PREP(LTC166X_REG_MASK, addr);
if (config->resolution == 10) {
regval |= FIELD_PREP(LTC166X_DATA10_MASK, data);
} else {
regval |= FIELD_PREP(LTC166X_DATA8_MASK, data);
}
const struct spi_buf buf = {
.buf = ®val,
.len = sizeof(regval),
};
struct spi_buf_set tx = {
.buffers = &buf,
.count = 1,
};
return spi_write_dt(&config->bus, &tx);
}
static int ltc166x_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
const struct ltc166x_config *config = dev->config;
if (channel_cfg->channel_id > config->nchannels - 1) {
LOG_ERR("Unsupported channel %d", channel_cfg->channel_id);
return -ENOTSUP;
}
if (channel_cfg->resolution != config->resolution) {
LOG_ERR("Unsupported resolution %d", channel_cfg->resolution);
return -ENOTSUP;
}
return 0;
}
static int ltc166x_write_value(const struct device *dev, uint8_t channel,
uint32_t value)
{
const struct ltc166x_config *config = dev->config;
if (channel > config->nchannels - 1) {
LOG_ERR("unsupported channel %d", channel);
return -ENOTSUP;
}
if (value >= (1 << config->resolution)) {
LOG_ERR("Value %d out of range", value);
return -EINVAL;
}
return ltc166x_reg_write(dev, channel + 1, value);
}
static int ltc166x_init(const struct device *dev)
{
const struct ltc166x_config *config = dev->config;
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
return -ENODEV;
}
return 0;
}
static const struct dac_driver_api ltc166x_driver_api = {
.channel_setup = ltc166x_channel_setup,
.write_value = ltc166x_write_value,
};
#define INST_DT_LTC166X(inst, t) DT_INST(inst, lltc_ltc##t)
#define LTC166X_DEVICE(t, n, res, nchan) \
static const struct ltc166x_config ltc##t##_config_##n = { \
.bus = SPI_DT_SPEC_GET(INST_DT_LTC166X(n, t), \
SPI_OP_MODE_MASTER | \
SPI_WORD_SET(8), 0), \
.resolution = res, \
.nchannels = nchan, \
}; \
DEVICE_DT_DEFINE(INST_DT_LTC166X(n, t), \
<c166x_init, NULL, \
NULL, \
<c##t##_config_##n, POST_KERNEL, \
CONFIG_DAC_LTC166X_INIT_PRIORITY, \
<c166x_driver_api)
/*
* LTC1660: 10-bit
*/
#define LTC1660_DEVICE(n) LTC166X_DEVICE(1660, n, 10, 8)
/*
* LTC1665: 8-bit
*/
#define LTC1665_DEVICE(n) LTC166X_DEVICE(1665, n, 8, 8)
#define CALL_WITH_ARG(arg, expr) expr(arg)
#define INST_DT_LTC166X_FOREACH(t, inst_expr) \
LISTIFY(DT_NUM_INST_STATUS_OKAY(lltc_ltc##t), \
CALL_WITH_ARG, (), inst_expr)
INST_DT_LTC166X_FOREACH(1660, LTC1660_DEVICE);
INST_DT_LTC166X_FOREACH(1665, LTC1665_DEVICE);
``` | /content/code_sandbox/drivers/dac/dac_ltc166x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,001 |
```c
/*
*
*/
#include <stdint.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
LOG_MODULE_REGISTER(dac_ad569x, CONFIG_DAC_LOG_LEVEL);
#define AD569X_CTRL_GAIN(x) FIELD_PREP(BIT(11), x)
#define AD569X_CTRL_REF(x) FIELD_PREP(BIT(12), x)
#define AD569X_CTRL_PD(x) FIELD_PREP(BIT_MASK(2) << 13, x)
#define AD569X_CTRL_RESET(x) FIELD_PREP(BIT(15), x)
#define AD569X_CMD_WRITE 0x10
#define AD569X_CMD_UPDATE 0x20
#define AD569X_CMD_WRITE_AND_UPDATE 0x30
#define AD569X_CMD_CONFIGURE 0x40
#define AD569X_CTRL_NO_RESET 0x00
#define AD569X_CTRL_PERFORM_RESET 0x01
struct ad569x_config {
struct i2c_dt_spec bus;
uint8_t resolution;
uint8_t gain;
uint8_t voltage_reference;
uint8_t power_down_mode;
};
static int ad569x_write(const struct device *dev, uint8_t command, uint16_t value)
{
const struct ad569x_config *config = dev->config;
uint8_t tx_data[3];
tx_data[0] = command;
sys_put_be16(value, tx_data + 1);
return i2c_write_dt(&config->bus, tx_data, sizeof(tx_data));
}
static int ad569x_read(const struct device *dev, uint16_t *value)
{
const struct ad569x_config *config = dev->config;
uint8_t rx_data[2];
int ret;
ret = i2c_read_dt(&config->bus, rx_data, sizeof(rx_data));
if (ret != 0) {
return ret;
}
*value = sys_get_be16(rx_data);
return ret;
}
static int ad569x_channel_setup(const struct device *dev, const struct dac_channel_cfg *channel_cfg)
{
const struct ad569x_config *config = dev->config;
if (channel_cfg->channel_id > 0) {
LOG_ERR("invalid channel %d", channel_cfg->channel_id);
return -EINVAL;
}
if (channel_cfg->resolution != config->resolution) {
LOG_ERR("invalid resolution %d", channel_cfg->resolution);
return -EINVAL;
}
return 0;
}
static int ad569x_sw_reset(const struct device *dev)
{
uint16_t reg = AD569X_CTRL_RESET(AD569X_CTRL_PERFORM_RESET);
int ret;
LOG_DBG("reset %s", dev->name);
/* Ignore return value, since device gives NAK after receiving RESET request */
ad569x_write(dev, AD569X_CMD_CONFIGURE, reg);
/* Check that DAC output is reset */
ret = ad569x_read(dev, ®);
if (ret != 0) {
LOG_ERR("failed to read value");
return ret;
}
if (reg != 0) {
LOG_ERR("failed to reset DAC output");
return -EIO;
}
return 0;
}
static int ad569x_write_value(const struct device *dev, uint8_t channel, uint32_t value)
{
const struct ad569x_config *config = dev->config;
if (channel > 0) {
LOG_ERR("invalid channel %d", channel);
return -EINVAL;
}
if (value > (BIT(config->resolution) - 1)) {
LOG_ERR("invalid value %d", value);
return -EINVAL;
}
value <<= 16 - config->resolution;
return ad569x_write(dev, AD569X_CMD_WRITE_AND_UPDATE, value);
}
static int ad569x_init(const struct device *dev)
{
const struct ad569x_config *config = dev->config;
int ret;
if (!i2c_is_ready_dt(&config->bus)) {
return -ENODEV;
}
ret = ad569x_sw_reset(dev);
if (ret != 0) {
LOG_ERR("failed to perform sw reset");
return ret;
}
LOG_DBG("configure %s: gain %d, voltage reference %d, power down mode %d", dev->name,
config->gain, config->voltage_reference, config->power_down_mode);
uint16_t ctrl_reg = AD569X_CTRL_GAIN(config->gain) |
AD569X_CTRL_REF(config->voltage_reference) |
AD569X_CTRL_PD(config->power_down_mode);
ret = ad569x_write(dev, AD569X_CMD_CONFIGURE, ctrl_reg);
if (ret != 0) {
LOG_ERR("failed to configure the device");
return ret;
}
return 0;
}
static const struct dac_driver_api ad569x_driver_api = {
.channel_setup = ad569x_channel_setup,
.write_value = ad569x_write_value,
};
#define INST_DT_AD569X(index, name, res) \
static const struct ad569x_config config_##name##_##index = { \
.bus = I2C_DT_SPEC_INST_GET(index), \
.resolution = res, \
.gain = DT_INST_ENUM_IDX(index, gain), \
.voltage_reference = DT_INST_ENUM_IDX(index, voltage_reference), \
.power_down_mode = DT_INST_ENUM_IDX(index, power_down_mode), \
}; \
\
DEVICE_DT_INST_DEFINE(index, ad569x_init, NULL, NULL, &config_##name##_##index, \
POST_KERNEL, CONFIG_DAC_INIT_PRIORITY, &ad569x_driver_api);
#define DT_DRV_COMPAT adi_ad5691
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
#define DAC_AD5691_RESOLUTION 12
DT_INST_FOREACH_STATUS_OKAY_VARGS(INST_DT_AD569X, DT_DRV_COMPAT, DAC_AD5691_RESOLUTION)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5692
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
#define DAC_AD5692_RESOLUTION 14
DT_INST_FOREACH_STATUS_OKAY_VARGS(INST_DT_AD569X, DT_DRV_COMPAT, DAC_AD5692_RESOLUTION)
#endif
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT adi_ad5693
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
#define DAC_AD5693_RESOLUTION 16
DT_INST_FOREACH_STATUS_OKAY_VARGS(INST_DT_AD569X, DT_DRV_COMPAT, DAC_AD5693_RESOLUTION)
#endif
#undef DT_DRV_COMPAT
``` | /content/code_sandbox/drivers/dac/dac_ad569x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,415 |
```unknown
# DAC configuration options
#
config DAC_DACX3608
bool "TI DACX3608 DAC driver"
default y
select I2C
depends on DT_HAS_TI_DAC43608_ENABLED || DT_HAS_TI_DAC53608_ENABLED
help
Enable the driver for the TI DACX3608.
if DAC_DACX3608
config DAC_DACX3608_INIT_PRIORITY
int "Init priority"
default 80
help
TI DACX3608 DAC device driver initialization priority.
endif # DAC_DACX3608
``` | /content/code_sandbox/drivers/dac/Kconfig.dacx3608 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```unknown
# DAC configuration options
#
config DAC_LTC166X
bool "Linear Technology LTC166X DAC"
default y
select SPI
depends on DT_HAS_LLTC_LTC1660_ENABLED || DT_HAS_LLTC_LTC1665_ENABLED
help
Enable the driver for the Linear Technology LTC166X DAC
if DAC_LTC166X
config DAC_LTC166X_INIT_PRIORITY
int "Init priority"
default 80
help
Linear Technology LTC166X DAC device driver initialization priority.
endif # DAC_LTC166X
``` | /content/code_sandbox/drivers/dac/Kconfig.ltc166x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```unknown
# DAC configuration options
#
# DAC options
#
menuconfig DAC
bool "Digital-to-Analog Converter (DAC) drivers"
help
Enable DAC (Digital to Analog Converter) driver configuration.
if DAC
module = DAC
module-str = DAC
source "subsys/logging/Kconfig.template.log_config"
config DAC_SHELL
bool "DAC shell"
depends on SHELL
help
Enable DAC related shell commands.
config DAC_INIT_PRIORITY
int "DAC init priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
DAC driver device initialization priority.
source "drivers/dac/Kconfig.mcux"
source "drivers/dac/Kconfig.stm32"
source "drivers/dac/Kconfig.sam"
source "drivers/dac/Kconfig.sam0"
source "drivers/dac/Kconfig.dacx0501"
source "drivers/dac/Kconfig.dacx0508"
source "drivers/dac/Kconfig.dacx3608"
source "drivers/dac/Kconfig.ltc166x"
source "drivers/dac/Kconfig.mcp4725"
source "drivers/dac/Kconfig.mcp4728"
source "drivers/dac/Kconfig.gd32"
source "drivers/dac/Kconfig.esp32"
source "drivers/dac/Kconfig.ad56xx"
source "drivers/dac/Kconfig.ad559x"
source "drivers/dac/Kconfig.ad569x"
endif # DAC
``` | /content/code_sandbox/drivers/dac/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 289 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_kinetis_dac32
#include <zephyr/kernel.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/pinctrl.h>
#include <fsl_dac32.h>
LOG_MODULE_REGISTER(dac_mcux_dac32, CONFIG_DAC_LOG_LEVEL);
struct mcux_dac32_config {
DAC_Type *base;
dac32_reference_voltage_source_t reference;
bool buffered;
bool low_power;
const struct pinctrl_dev_config *pincfg;
};
struct mcux_dac32_data {
bool configured;
};
static int mcux_dac32_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
const struct mcux_dac32_config *config = dev->config;
struct mcux_dac32_data *data = dev->data;
dac32_config_t dac32_config;
if (channel_cfg->channel_id != 0) {
LOG_ERR("unsupported channel %d", channel_cfg->channel_id);
return -ENOTSUP;
}
if (channel_cfg->resolution != 12) {
LOG_ERR("unsupported resolution %d", channel_cfg->resolution);
return -ENOTSUP;
}
DAC32_GetDefaultConfig(&dac32_config);
dac32_config.enableLowPowerMode = config->low_power;
dac32_config.referenceVoltageSource = config->reference;
DAC32_Init(config->base, &dac32_config);
DAC32_EnableBufferOutput(config->base, config->buffered);
DAC32_EnableTestOutput(config->base,
IS_ENABLED(CONFIG_DAC_MCUX_DAC32_TESTOUT));
data->configured = true;
return 0;
}
static int mcux_dac32_write_value(const struct device *dev, uint8_t channel,
uint32_t value)
{
const struct mcux_dac32_config *config = dev->config;
struct mcux_dac32_data *data = dev->data;
if (!data->configured) {
LOG_ERR("channel not initialized");
return -EINVAL;
}
if (channel != 0) {
LOG_ERR("unsupported channel %d", channel);
return -ENOTSUP;
}
if (value >= 4096) {
LOG_ERR("value %d out of range", value);
return -EINVAL;
}
/* Static operation */
DAC32_EnableBuffer(config->base, false);
DAC32_SetBufferValue(config->base, 0, value);
DAC32_Enable(config->base, true);
return 0;
}
static int mcux_dac32_init(const struct device *dev)
{
const struct mcux_dac32_config *config = dev->config;
return pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
}
static const struct dac_driver_api mcux_dac32_driver_api = {
.channel_setup = mcux_dac32_channel_setup,
.write_value = mcux_dac32_write_value,
};
#define TO_DAC32_VREF_SRC(val) \
_DO_CONCAT(kDAC32_ReferenceVoltageSourceVref, val)
#define MCUX_DAC32_INIT(n) \
static struct mcux_dac32_data mcux_dac32_data_##n; \
\
PINCTRL_DT_INST_DEFINE(n); \
\
static const struct mcux_dac32_config mcux_dac32_config_##n = { \
.base = (DAC_Type *)DT_INST_REG_ADDR(n), \
.reference = \
TO_DAC32_VREF_SRC(DT_INST_PROP(n, voltage_reference)), \
.buffered = DT_INST_PROP(n, buffered), \
.low_power = DT_INST_PROP(n, low_power_mode), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, mcux_dac32_init, NULL, \
&mcux_dac32_data_##n, \
&mcux_dac32_config_##n, \
POST_KERNEL, CONFIG_DAC_INIT_PRIORITY, \
&mcux_dac32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MCUX_DAC32_INIT)
``` | /content/code_sandbox/drivers/dac/dac_mcux_dac32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 915 |
```unknown
# DAC configuration options
#
config DAC_MCP4725
bool "Microchip MCP4725 DAC driver"
default y
select I2C
depends on DT_HAS_MICROCHIP_MCP4725_ENABLED
help
Enable the driver for the Microchip MCP4725.
if DAC_MCP4725
config DAC_MCP4725_INIT_PRIORITY
int "Init priority"
default 80
help
Microchip MCP4725 DAC device driver initialization priority.
endif # DAC_MCP4725
``` | /content/code_sandbox/drivers/dac/Kconfig.mcp4725 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```c
/*
*
*/
/**
* @brief Driver for Texas Instruments DACx0501 series
*
* Device driver for the Texas Instruments DACx0501 series of devices: DAC60501, DAC70501 and
* DAC80501: Digital to Analog Converters with a single channel output and with 12, 14 and 16
* bits resolution respectively. Data sheet can be found here:
* path_to_url
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
LOG_MODULE_REGISTER(dac_dacx0501, CONFIG_DAC_LOG_LEVEL);
#define DACX0501_REG_DEVICE_ID 0x01U
#define DACX0501_REG_SYNC 0x02U
#define DACX0501_REG_CONFIG 0x03U
#define DACX0501_REG_GAIN 0x04U
#define DACX0501_REG_TRIGGER 0x05U
#define DACX0501_REG_STATUS 0x07U
#define DACX0501_REG_DAC 0x08U
#define DACX0501_MASK_DEVICE_ID_RES GENMASK(14, 12)
#define DACX0501_MASK_CONFIG_REF_PWDWN BIT(8)
#define DACX0501_MASK_CONFIG_DAC_PWDWN BIT(0)
#define DACX0501_MASK_GAIN_BUFF_GAIN BIT(0)
#define DACX0501_MASK_GAIN_REFDIV_EN BIT(8)
#define DACX0501_MASK_TRIGGER_SOFT_RESET (BIT(1) | BIT(3))
#define DACX0501_MASK_STATUS_REF_ALM BIT(0)
/* Specifies the source of the reference voltage. */
enum voltage_reference_source {
REF_INTERNAL, /* Internal 2.5V voltage reference. */
REF_EXTERNAL, /* External pin voltage reference. */
};
/* Specifies the reference voltage multiplier. */
enum output_gain {
VM_MUL2, /* Multiplies by 2. */
VM_MUL1, /* Multiplies by 1. */
VM_DIV2, /* Multiplies by 0.5 */
};
struct dacx0501_config {
struct i2c_dt_spec i2c_spec;
enum voltage_reference_source voltage_reference;
enum output_gain output_gain;
};
struct dacx0501_data {
/* Number of bits in the DAC register: Either 12, 14 or 16. */
uint8_t resolution;
};
static int dacx0501_reg_read(const struct device *dev, const uint8_t addr, uint16_t *data)
{
const struct dacx0501_config *config = dev->config;
uint8_t raw_data[2];
int status;
status = i2c_write_read_dt(&config->i2c_spec, &addr, sizeof(addr), raw_data,
sizeof(raw_data));
if (status != 0) {
return status;
}
/* DAC is big endian. */
*data = sys_get_be16(raw_data);
return 0;
}
static int dacx0501_reg_write(const struct device *dev, uint8_t addr, uint16_t data)
{
const struct dacx0501_config *config = dev->config;
uint8_t write_cmd[3] = {addr};
/* DAC is big endian. */
sys_put_be16(data, write_cmd + 1);
return i2c_write_dt(&config->i2c_spec, write_cmd, sizeof(write_cmd));
}
static int dacx0501_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
struct dacx0501_data *data = dev->data;
/* DACx0501 series only has a single output channel. */
if (channel_cfg->channel_id != 0) {
LOG_ERR("Unsupported channel %d", channel_cfg->channel_id);
return -ENOTSUP;
}
if (channel_cfg->resolution != data->resolution) {
LOG_ERR("Unsupported resolution %d. Actual: %d", channel_cfg->resolution,
data->resolution);
return -ENOTSUP;
}
return 0;
}
static int dacx0501_write_value(const struct device *dev, uint8_t channel, uint32_t value)
{
struct dacx0501_data *data = dev->data;
if (channel != 0) {
LOG_ERR("dacx0501: Unsupported channel %d", channel);
return -ENOTSUP;
}
if (value >= (1 << data->resolution)) {
LOG_ERR("dacx0501: Value %d out of range", value);
return -EINVAL;
}
value <<= (16 - data->resolution);
return dacx0501_reg_write(dev, DACX0501_REG_DAC, value);
}
static int dacx0501_init(const struct device *dev)
{
const struct dacx0501_config *config = dev->config;
struct dacx0501_data *data = dev->data;
uint16_t device_id;
int status;
if (!i2c_is_ready_dt(&config->i2c_spec)) {
LOG_ERR("I2C bus %s not ready", config->i2c_spec.bus->name);
return -ENODEV;
}
status = dacx0501_reg_read(dev, DACX0501_REG_DEVICE_ID, &device_id);
if (status != 0) {
LOG_ERR("read DEVICE_ID register failed");
return status;
}
/* See DEVICE_ID register RES field in the data sheet. */
data->resolution = 16 - 2 * FIELD_GET(DACX0501_MASK_DEVICE_ID_RES, device_id);
status = dacx0501_reg_write(dev, DACX0501_REG_CONFIG,
FIELD_PREP(DACX0501_MASK_CONFIG_REF_PWDWN,
config->voltage_reference == REF_EXTERNAL));
if (status != 0) {
LOG_ERR("write CONFIG register failed");
return status;
}
status = dacx0501_reg_write(
dev, DACX0501_REG_GAIN,
FIELD_PREP(DACX0501_MASK_GAIN_REFDIV_EN, config->output_gain == VM_DIV2) |
FIELD_PREP(DACX0501_MASK_GAIN_BUFF_GAIN, config->output_gain == VM_MUL2));
if (status != 0) {
LOG_ERR("GAIN Register update failed");
return status;
}
return 0;
}
static const struct dac_driver_api dacx0501_driver_api = {
.channel_setup = dacx0501_channel_setup,
.write_value = dacx0501_write_value,
};
#define DT_DRV_COMPAT ti_dacx0501
#define DACX0501_DEFINE(n) \
static struct dacx0501_data dacx0501_data_##n = {}; \
static const struct dacx0501_config dacx0501_config_##n = { \
.i2c_spec = I2C_DT_SPEC_INST_GET(n), \
.voltage_reference = \
_CONCAT(REF_, DT_STRING_UPPER_TOKEN(DT_DRV_INST(n), voltage_reference)), \
.output_gain = _CONCAT(VM_, DT_STRING_UPPER_TOKEN(DT_DRV_INST(n), output_gain)), \
}; \
DEVICE_DT_INST_DEFINE(n, &dacx0501_init, NULL, &dacx0501_data_##n, &dacx0501_config_##n, \
POST_KERNEL, CONFIG_DAC_DACX0501_INIT_PRIORITY, \
&dacx0501_driver_api);
DT_INST_FOREACH_STATUS_OKAY(DACX0501_DEFINE)
``` | /content/code_sandbox/drivers/dac/dac_dacx0501.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,607 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_kinetis_dac
#include <zephyr/kernel.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/logging/log.h>
#include <fsl_dac.h>
LOG_MODULE_REGISTER(dac_mcux_dac, CONFIG_DAC_LOG_LEVEL);
struct mcux_dac_config {
DAC_Type *base;
dac_reference_voltage_source_t reference;
bool low_power;
};
struct mcux_dac_data {
bool configured;
};
static int mcux_dac_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
const struct mcux_dac_config *config = dev->config;
struct mcux_dac_data *data = dev->data;
dac_config_t dac_config;
if (channel_cfg->channel_id != 0) {
LOG_ERR("unsupported channel %d", channel_cfg->channel_id);
return -ENOTSUP;
}
if (channel_cfg->resolution != 12) {
LOG_ERR("unsupported resolution %d", channel_cfg->resolution);
return -ENOTSUP;
}
DAC_GetDefaultConfig(&dac_config);
dac_config.enableLowPowerMode = config->low_power;
dac_config.referenceVoltageSource = config->reference;
DAC_Init(config->base, &dac_config);
data->configured = true;
return 0;
}
static int mcux_dac_write_value(const struct device *dev, uint8_t channel,
uint32_t value)
{
const struct mcux_dac_config *config = dev->config;
struct mcux_dac_data *data = dev->data;
if (!data->configured) {
LOG_ERR("channel not initialized");
return -EINVAL;
}
if (channel != 0) {
LOG_ERR("unsupported channel %d", channel);
return -ENOTSUP;
}
if (value >= 4096) {
LOG_ERR("value %d out of range", value);
return -EINVAL;
}
/* Static operation */
DAC_EnableBuffer(config->base, false);
DAC_SetBufferValue(config->base, 0, value);
DAC_Enable(config->base, true);
return 0;
}
static const struct dac_driver_api mcux_dac_driver_api = {
.channel_setup = mcux_dac_channel_setup,
.write_value = mcux_dac_write_value,
};
#define TO_DAC_VREF_SRC(val) \
_DO_CONCAT(kDAC_ReferenceVoltageSourceVref, val)
#define MCUX_DAC_INIT(n) \
static struct mcux_dac_data mcux_dac_data_##n; \
\
static const struct mcux_dac_config mcux_dac_config_##n = { \
.base = (DAC_Type *)DT_INST_REG_ADDR(n), \
.reference = \
TO_DAC_VREF_SRC(DT_INST_PROP(n, voltage_reference)), \
.low_power = DT_INST_PROP(n, low_power_mode), \
}; \
\
DEVICE_DT_INST_DEFINE(n, NULL, NULL, \
&mcux_dac_data_##n, \
&mcux_dac_config_##n, \
POST_KERNEL, CONFIG_DAC_INIT_PRIORITY, \
&mcux_dac_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MCUX_DAC_INIT)
``` | /content/code_sandbox/drivers/dac/dac_mcux_dac.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 714 |
```unknown
config DAC_SAM0
bool "Atmel SAM0 series DAC Driver"
default y
depends on DT_HAS_ATMEL_SAM0_DAC_ENABLED
help
Enables the Atmel SAM0 MCU Family Digital-to-Analog (DAC) driver.
``` | /content/code_sandbox/drivers/dac/Kconfig.sam0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpdac
#include <zephyr/kernel.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/logging/log.h>
#include <fsl_dac.h>
LOG_MODULE_REGISTER(dac_mcux_lpdac, CONFIG_DAC_LOG_LEVEL);
struct mcux_lpdac_config {
LPDAC_Type *base;
dac_reference_voltage_source_t ref_voltage;
bool low_power;
};
struct mcux_lpdac_data {
bool configured;
};
static int mcux_lpdac_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
const struct mcux_lpdac_config *config = dev->config;
struct mcux_lpdac_data *data = dev->data;
dac_config_t dac_config;
if (channel_cfg->channel_id != 0) {
LOG_ERR("unsupported channel %d", channel_cfg->channel_id);
return -ENOTSUP;
}
if (channel_cfg->resolution != 12) {
LOG_ERR("unsupported resolution %d", channel_cfg->resolution);
return -ENOTSUP;
}
DAC_GetDefaultConfig(&dac_config);
dac_config.referenceVoltageSource = config->ref_voltage;
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL
dac_config.enableLowerLowPowerMode = config->low_power;
#else
dac_config.enableLowPowerMode = config->low_power;
#endif
DAC_Init(config->base, &dac_config);
DAC_Enable(config->base, false);
data->configured = true;
return 0;
}
static int mcux_lpdac_write_value(const struct device *dev, uint8_t channel, uint32_t value)
{
const struct mcux_lpdac_config *config = dev->config;
struct mcux_lpdac_data *data = dev->data;
if (!data->configured) {
LOG_ERR("channel not initialized");
return -EINVAL;
}
if (channel != 0) {
LOG_ERR("unsupported channel %d", channel);
return -ENOTSUP;
}
if (value >= 4096) {
LOG_ERR("unsupported value %d", value);
return -EINVAL;
}
DAC_Enable(config->base, true);
DAC_SetData(config->base, value);
return 0;
}
static int mcux_lpdac_init(const struct device *dev)
{
return 0;
}
static const struct dac_driver_api mcux_lpdac_driver_api = {
.channel_setup = mcux_lpdac_channel_setup,
.write_value = mcux_lpdac_write_value,
};
#define MCUX_LPDAC_INIT(n) \
static struct mcux_lpdac_data mcux_lpdac_data_##n; \
\
static const struct mcux_lpdac_config mcux_lpdac_config_##n = { \
.base = (LPDAC_Type *)DT_INST_REG_ADDR(n), \
.ref_voltage = DT_INST_PROP(n, voltage_reference), \
.low_power = DT_INST_PROP(n, low_power_mode), \
}; \
\
DEVICE_DT_INST_DEFINE(n, mcux_lpdac_init, NULL, &mcux_lpdac_data_##n, \
&mcux_lpdac_config_##n, POST_KERNEL, CONFIG_DAC_INIT_PRIORITY, \
&mcux_lpdac_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MCUX_LPDAC_INIT)
``` | /content/code_sandbox/drivers/dac/dac_mcux_lpdac.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 750 |
```unknown
#
config DAC_MCP4728
bool "Microchip MCP4728 DAC driver"
default y
select I2C
depends on DT_HAS_MICROCHIP_MCP4728_ENABLED
help
Enable driver for the Microchip MCP4728.
if DAC_MCP4728
config DAC_MCP4728_INIT_PRIORITY
int "Init priority"
default 80
help
Microchip MCP4728 device driver initialization priority.
endif # DAC_MCP4728
``` | /content/code_sandbox/drivers/dac/Kconfig.mcp4728 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```unknown
# Atmel SAM TRNG configuration
config PWM_SAM
bool "Atmel SAM MCU Family PWM Driver"
default y
depends on DT_HAS_ATMEL_SAM_PWM_ENABLED
help
Enable PWM driver for Atmel SAM MCUs.
``` | /content/code_sandbox/drivers/pwm/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
# Organisation (CSIRO) ABN 41 687 119 230.
# Hidden option for turning on the dummy driver for vnd,pwm devices
# used in testing.
config PWM_TEST
def_bool DT_HAS_VND_PWM_ENABLED
depends on DT_HAS_VND_PWM_ENABLED
``` | /content/code_sandbox/drivers/pwm/Kconfig.test | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_mcp4728
#include <zephyr/kernel.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dac_mcp4728, CONFIG_DAC_LOG_LEVEL);
#define MCP4728_MAX_CHANNEL 4U
#define MCP4728_RESOLUTION 0xC
#define MCP4728_DAC_MAX_VAL ((1U << MCP4728_RESOLUTION) - 1U)
#define MCP4728_MULTI_WRITE_CMD_VAL 8U
#define MCP4728_MULTI_WRITE_CMD_POS 3U
#define MCP4728_MULTI_WRITE_CHANNEL_POS 1U
#define MCP4728_MULTI_WRITE_REFERENCE_POS 7U
#define MCP4728_MULTI_WRITE_POWER_DOWN_POS 5U
#define MCP4728_MULTI_WRITE_POWER_DOWN_MASK 0X3
#define MCP4728_MULTI_WRITE_GAIN_POS 4U
#define MCP4728_MULTI_WRITE_DAC_UPPER_VAL_POS 8U
#define MCP4728_MULTI_WRITE_DAC_UPPER_VAL_MASK 0xF
#define MCP4728_MULTI_WRITE_DAC_LOWER_VAL_MASK 0xFF
struct mcp4728_config {
struct i2c_dt_spec bus;
uint8_t power_down[MCP4728_MAX_CHANNEL];
uint8_t voltage_reference[MCP4728_MAX_CHANNEL];
uint8_t gain[MCP4728_MAX_CHANNEL];
};
static int mcp4728_channel_setup(const struct device *dev,
const struct dac_channel_cfg *channel_cfg)
{
if (channel_cfg->channel_id >= MCP4728_MAX_CHANNEL) {
return -ENOTSUP;
}
if (channel_cfg->resolution != MCP4728_RESOLUTION) {
return -ENOTSUP;
}
return 0;
}
static int mcp4728_write_value(const struct device *dev, uint8_t channel, uint32_t value)
{
const struct mcp4728_config *config = (struct mcp4728_config *)dev->config;
uint8_t tx_data[3];
int ret;
if (channel >= MCP4728_MAX_CHANNEL) {
return -ENOTSUP;
}
if (value > MCP4728_DAC_MAX_VAL) {
return -ENOTSUP;
}
/* Multi-Write Command: Write Multiple DAC Input Registers. */
tx_data[0] = (MCP4728_MULTI_WRITE_CMD_VAL << MCP4728_MULTI_WRITE_CMD_POS) |
(channel << MCP4728_MULTI_WRITE_CHANNEL_POS);
tx_data[1] = (config->voltage_reference[channel] << MCP4728_MULTI_WRITE_REFERENCE_POS) |
((config->power_down[channel] & MCP4728_MULTI_WRITE_POWER_DOWN_MASK)
<< MCP4728_MULTI_WRITE_POWER_DOWN_POS) |
((config->gain[channel] << MCP4728_MULTI_WRITE_GAIN_POS)) |
((value >> MCP4728_MULTI_WRITE_DAC_UPPER_VAL_POS) &
MCP4728_MULTI_WRITE_DAC_UPPER_VAL_MASK);
tx_data[2] = (value & MCP4728_MULTI_WRITE_DAC_LOWER_VAL_MASK);
ret = i2c_write_dt(&config->bus, tx_data, sizeof(tx_data));
return ret;
}
static int dac_mcp4728_init(const struct device *dev)
{
const struct mcp4728_config *config = dev->config;
if (!device_is_ready(config->bus.bus)) {
LOG_ERR("%s device not found", config->bus.bus->name);
return -ENODEV;
}
return 0;
}
static const struct dac_driver_api mcp4728_driver_api = {
.channel_setup = mcp4728_channel_setup,
.write_value = mcp4728_write_value,
};
#define INST_DT_MCP4728(index) \
static const struct mcp4728_config mcp4728_config_##index = { \
.bus = I2C_DT_SPEC_INST_GET(index), \
.power_down = DT_INST_PROP(index, power_down_mode), \
.voltage_reference = DT_INST_PROP(index, voltage_reference), \
.gain = DT_INST_PROP_OR(index, gain, {0}), \
}; \
\
DEVICE_DT_INST_DEFINE(index, dac_mcp4728_init, NULL, NULL, \
&mcp4728_config_##index, \
POST_KERNEL, \
CONFIG_DAC_MCP4728_INIT_PRIORITY, \
&mcp4728_driver_api);
DT_INST_FOREACH_STATUS_OKAY(INST_DT_MCP4728);
``` | /content/code_sandbox/drivers/dac/dac_mcp4728.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 959 |
```unknown
# STM32 PWM configuration options
config PWM_MCUX
bool "MCUX PWM driver"
default y
depends on DT_HAS_NXP_IMX_PWM_ENABLED
help
Enable mcux pwm driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.mcux | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_qtmr_pwm
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <fsl_qtmr.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_qtmr, CONFIG_PWM_LOG_LEVEL);
#define CHANNEL_COUNT TMR_CNTR_COUNT
struct pwm_mcux_qtmr_config {
TMR_Type *base;
uint32_t prescaler;
const struct pinctrl_dev_config *pincfg;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
};
struct pwm_mcux_qtmr_data {
struct k_mutex lock;
};
static int mcux_qtmr_pwm_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_mcux_qtmr_config *config = dev->config;
struct pwm_mcux_qtmr_data *data = dev->data;
uint32_t periodCount, highCount, lowCount;
uint16_t reg;
if (channel >= CHANNEL_COUNT) {
LOG_ERR("Invalid channel");
return -EINVAL;
}
/* Counter values to generate a PWM signal */
periodCount = period_cycles;
highCount = pulse_cycles;
lowCount = period_cycles - pulse_cycles;
if (highCount > 0U) {
highCount -= 1U;
}
if (lowCount > 0U) {
lowCount -= 1U;
}
if ((highCount > 0xFFFFU) || (lowCount > 0xFFFFU)) {
/* This should not be a 16-bit overflow value. If it is, change to a larger divider
* for clock source.
*/
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
/* Set OFLAG pin for output mode and force out a low on the pin */
config->base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK);
QTMR_StopTimer(config->base, channel);
/* Setup the compare registers for PWM output */
config->base->CHANNEL[channel].COMP1 = (uint16_t)lowCount;
config->base->CHANNEL[channel].COMP2 = (uint16_t)highCount;
/* Setup the pre-load registers for PWM output */
config->base->CHANNEL[channel].CMPLD1 = (uint16_t)lowCount;
config->base->CHANNEL[channel].CMPLD2 = (uint16_t)highCount;
reg = config->base->CHANNEL[channel].CSCTRL;
/* Setup the compare load control for COMP1 and COMP2.
* Load COMP1 when CSCTRL[TCF2] is asserted, load COMP2 when CSCTRL[TCF1] is asserted
*/
reg &= (uint16_t)(~(TMR_CSCTRL_CL1_MASK | TMR_CSCTRL_CL2_MASK));
reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1));
config->base->CHANNEL[channel].CSCTRL = reg;
reg = config->base->CHANNEL[channel].CTRL;
reg &= ~(uint16_t)TMR_CTRL_OUTMODE_MASK;
if (highCount == periodCount) {
/* Set OFLAG output on compare */
reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_SetOnCompare));
} else if (periodCount == 0U) {
/* Clear OFLAG output on compare */
reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ClearOnCompare));
} else {
/* Toggle OFLAG output using alternating compare register */
reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg));
}
config->base->CHANNEL[channel].CTRL = reg;
QTMR_StartTimer(config->base, channel, kQTMR_PriSrcRiseEdge);
k_mutex_unlock(&data->lock);
return 0;
}
static int mcux_qtmr_pwm_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
const struct pwm_mcux_qtmr_config *config = dev->config;
uint32_t clock_freq;
if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq)) {
return -EINVAL;
}
*cycles = clock_freq / config->prescaler;
return 0;
}
static int mcux_qtmr_pwm_init(const struct device *dev)
{
const struct pwm_mcux_qtmr_config *config = dev->config;
struct pwm_mcux_qtmr_data *data = dev->data;
qtmr_config_t qtmr_config;
int err;
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
k_mutex_init(&data->lock);
QTMR_GetDefaultConfig(&qtmr_config);
qtmr_config.primarySource = kQTMR_ClockDivide_1 + (31 - __builtin_clz(config->prescaler));
for (int i = 0; i < CHANNEL_COUNT; i++) {
QTMR_Init(config->base, i, &qtmr_config);
}
return 0;
}
static const struct pwm_driver_api pwm_mcux_qtmr_driver_api = {
.set_cycles = mcux_qtmr_pwm_set_cycles,
.get_cycles_per_sec = mcux_qtmr_pwm_get_cycles_per_sec,
};
#define PWM_MCUX_QTMR_DEVICE_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static struct pwm_mcux_qtmr_data pwm_mcux_qtmr_data_##n; \
\
static const struct pwm_mcux_qtmr_config pwm_mcux_qtmr_config_##n = { \
.base = (TMR_Type *)DT_INST_REG_ADDR(n), \
.prescaler = DT_INST_PROP(n, prescaler), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
}; \
\
DEVICE_DT_INST_DEFINE(n, mcux_qtmr_pwm_init, NULL, &pwm_mcux_qtmr_data_##n, \
&pwm_mcux_qtmr_config_##n, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&pwm_mcux_qtmr_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_MCUX_QTMR_DEVICE_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_mcux_qtmr.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,488 |
```unknown
# MCUXpresso SDK FTM PWM
config PWM_MCUX_FTM
bool "MCUX FTM PWM driver"
default y
depends on DT_HAS_NXP_KINETIS_FTM_PWM_ENABLED
select PINCTRL
help
Enable support for mcux ftm pwm driver.
config PWM_CAPTURE_MCUX_FTM_FILTER_VALUE
int "MCUX FTM PWM capture filter value"
depends on PWM_MCUX_FTM && PWM_CAPTURE
range 0 15
default 0
help
PWM capture filter value for channels 0 and 2.
``` | /content/code_sandbox/drivers/pwm/Kconfig.mcux_ftm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_pwm
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/clock_control.h>
#include <soc.h>
#include <fsl_pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux, CONFIG_PWM_LOG_LEVEL);
#define CHANNEL_COUNT 2
struct pwm_mcux_config {
PWM_Type *base;
uint8_t index;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
pwm_clock_prescale_t prescale;
pwm_register_reload_t reload;
pwm_mode_t mode;
bool run_wait;
bool run_debug;
const struct pinctrl_dev_config *pincfg;
};
struct pwm_mcux_data {
uint32_t period_cycles[CHANNEL_COUNT];
pwm_signal_param_t channel[CHANNEL_COUNT];
struct k_mutex lock;
};
static int mcux_pwm_set_cycles_internal(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_mcux_config *config = dev->config;
struct pwm_mcux_data *data = dev->data;
pwm_level_select_t level;
if (flags & PWM_POLARITY_INVERTED) {
level = kPWM_LowTrue;
} else {
level = kPWM_HighTrue;
}
if (period_cycles != data->period_cycles[channel]
|| level != data->channel[channel].level) {
uint32_t clock_freq;
status_t status;
data->period_cycles[channel] = period_cycles;
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
data->channel[channel].pwmchannelenable = true;
PWM_StopTimer(config->base, 1U << config->index);
/*
* We will directly write the duty cycle pulse width
* and full pulse width into the VALx registers to
* setup PWM with higher resolution.
* Therefore we use dummy values for the duty cycle
* and frequency.
*/
data->channel[channel].dutyCyclePercent = 0;
data->channel[channel].level = level;
status = PWM_SetupPwm(config->base, config->index,
&data->channel[channel], 1U,
config->mode, 1U, clock_freq);
if (status != kStatus_Success) {
LOG_ERR("Could not set up pwm");
return -ENOTSUP;
}
/* Setup VALx values directly for edge aligned PWM */
if (channel == 0) {
/* Side A */
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_0,
(uint16_t)(period_cycles / 2U));
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_1,
(uint16_t)(period_cycles - 1U));
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_2, 0U);
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_3,
(uint16_t)pulse_cycles);
} else {
/* Side B */
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_0,
(uint16_t)(period_cycles / 2U));
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_1,
(uint16_t)(period_cycles - 1U));
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_4, 0U);
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_5,
(uint16_t)pulse_cycles);
}
PWM_SetPwmLdok(config->base, 1U << config->index, true);
PWM_StartTimer(config->base, 1U << config->index);
} else {
/* Setup VALx values directly for edge aligned PWM */
if (channel == 0) {
/* Side A */
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_2, 0U);
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_3,
(uint16_t)pulse_cycles);
} else {
/* Side B */
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_4, 0U);
PWM_SetVALxValue(config->base, config->index,
kPWM_ValueRegister_5,
(uint16_t)pulse_cycles);
}
PWM_SetPwmLdok(config->base, 1U << config->index, true);
}
return 0;
}
static int mcux_pwm_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
struct pwm_mcux_data *data = dev->data;
int result;
if (channel >= CHANNEL_COUNT) {
LOG_ERR("Invalid channel");
return -EINVAL;
}
if (period_cycles == 0) {
LOG_ERR("Channel can not be set to inactive level");
return -ENOTSUP;
}
if (period_cycles > UINT16_MAX) {
/* 16-bit resolution */
LOG_ERR("Too long period (%u), adjust pwm prescaler!",
period_cycles);
/* TODO: dynamically adjust prescaler */
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
result = mcux_pwm_set_cycles_internal(dev, channel, period_cycles, pulse_cycles, flags);
k_mutex_unlock(&data->lock);
return result;
}
static int mcux_pwm_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct pwm_mcux_config *config = dev->config;
uint32_t clock_freq;
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
*cycles = clock_freq >> config->prescale;
return 0;
}
static int pwm_mcux_init(const struct device *dev)
{
const struct pwm_mcux_config *config = dev->config;
struct pwm_mcux_data *data = dev->data;
pwm_config_t pwm_config;
status_t status;
int i, err;
k_mutex_init(&data->lock);
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {
return err;
}
LOG_DBG("Set prescaler %d, reload mode %d",
1 << config->prescale, config->reload);
PWM_GetDefaultConfig(&pwm_config);
pwm_config.prescale = config->prescale;
pwm_config.reloadLogic = config->reload;
pwm_config.clockSource = kPWM_BusClock;
pwm_config.enableDebugMode = config->run_debug;
#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN)
pwm_config.enableWait = config->run_wait;
#endif
status = PWM_Init(config->base, config->index, &pwm_config);
if (status != kStatus_Success) {
LOG_ERR("Unable to init PWM");
return -EIO;
}
/* Disable fault sources */
for (i = 0; i < FSL_FEATURE_PWM_FAULT_CH_COUNT; i++) {
config->base->SM[config->index].DISMAP[i] = 0x0000;
}
data->channel[0].pwmChannel = kPWM_PwmA;
data->channel[0].level = kPWM_HighTrue;
data->channel[1].pwmChannel = kPWM_PwmB;
data->channel[1].level = kPWM_HighTrue;
return 0;
}
static const struct pwm_driver_api pwm_mcux_driver_api = {
.set_cycles = mcux_pwm_set_cycles,
.get_cycles_per_sec = mcux_pwm_get_cycles_per_sec,
};
#define PWM_DEVICE_INIT_MCUX(n) \
static struct pwm_mcux_data pwm_mcux_data_ ## n; \
PINCTRL_DT_INST_DEFINE(n); \
\
static const struct pwm_mcux_config pwm_mcux_config_ ## n = { \
.base = (PWM_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \
.index = DT_INST_PROP(n, index), \
.mode = kPWM_EdgeAligned, \
.prescale = _CONCAT(kPWM_Prescale_Divide_, DT_INST_PROP(n, nxp_prescaler)),\
.reload = DT_ENUM_IDX_OR(DT_DRV_INST(n), nxp_reload,\
kPWM_ReloadPwmFullCycle),\
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
.run_wait = DT_INST_PROP(n, run_in_wait), \
.run_debug = DT_INST_PROP(n, run_in_debug), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
pwm_mcux_init, \
NULL, \
&pwm_mcux_data_ ## n, \
&pwm_mcux_config_ ## n, \
POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&pwm_mcux_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT_MCUX)
``` | /content/code_sandbox/drivers/pwm/pwm_mcux.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,182 |
```unknown
#
#
#
menuconfig PWM_LITEX
bool "LiteX PWM driver"
default y
depends on DT_HAS_LITEX_PWM_ENABLED
help
Enable support for LiteX PWM driver
config PWM_LITEX_INIT_PRIORITY
int "Init priority"
default 70
depends on PWM_LITEX
help
PWM device driver initialization priority.
``` | /content/code_sandbox/drivers/pwm/Kconfig.litex | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```c
/*
*
*/
#define DT_DRV_COMPAT xlnx_xps_timer_1_00_a_pwm
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(xlnx_axi_timer_pwm, CONFIG_PWM_LOG_LEVEL);
/* AXI Timer v2.0 registers offsets (See Xilinx PG079 for details) */
#define TCSR0_OFFSET 0x00
#define TLR0_OFFSET 0x04
#define TCR0_OFFSET 0x08
#define TCSR1_OFFSET 0x10
#define TLR1_OFFSET 0x14
#define TCR1_OFFSET 0x18
/* TCSRx bit definitions */
#define TCSR_MDT BIT(0)
#define TCSR_UDT BIT(1)
#define TCSR_GENT BIT(2)
#define TCSR_CAPT BIT(3)
#define TCSR_ARHT BIT(4)
#define TCSR_LOAD BIT(5)
#define TCSR_ENIT BIT(6)
#define TCSR_ENT BIT(7)
#define TCSR_TINT BIT(8)
#define TCSR_PWMA BIT(9)
#define TCSR_ENALL BIT(10)
#define TCSR_CASC BIT(11)
/* Generate PWM mode, count-down, auto-reload */
#define TCSR_PWM (TCSR_UDT | TCSR_GENT | TCSR_ARHT | TCSR_PWMA)
struct xlnx_axi_timer_config {
mm_reg_t base;
uint32_t cycles_max;
uint32_t freq;
};
static inline uint32_t xlnx_axi_timer_read32(const struct device *dev,
mm_reg_t offset)
{
const struct xlnx_axi_timer_config *config = dev->config;
return sys_read32(config->base + offset);
}
static inline void xlnx_axi_timer_write32(const struct device *dev,
uint32_t value,
mm_reg_t offset)
{
const struct xlnx_axi_timer_config *config = dev->config;
sys_write32(value, config->base + offset);
}
static int xlnx_axi_timer_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles,
uint32_t pulse_cycles, pwm_flags_t flags)
{
const struct xlnx_axi_timer_config *config = dev->config;
uint32_t tcsr0 = TCSR_PWM;
uint32_t tcsr1 = TCSR_PWM;
uint32_t tlr0;
uint32_t tlr1;
if (channel != 0) {
return -ENOTSUP;
}
LOG_DBG("period = 0x%08x, pulse = 0x%08x", period_cycles, pulse_cycles);
if (pulse_cycles == 0) {
LOG_DBG("setting constant inactive level");
if (flags & PWM_POLARITY_INVERTED) {
tcsr0 |= TCSR_ENT;
} else {
tcsr1 |= TCSR_ENT;
}
} else if (pulse_cycles == period_cycles) {
LOG_DBG("setting constant active level");
if (flags & PWM_POLARITY_INVERTED) {
tcsr1 |= TCSR_ENT;
} else {
tcsr0 |= TCSR_ENT;
}
} else {
LOG_DBG("setting normal pwm");
if (period_cycles < 2) {
LOG_ERR("period cycles too narrow");
return -ENOTSUP;
}
/* PWM_PERIOD = (TLR0 + 2) * AXI_CLOCK_PERIOD */
tlr0 = period_cycles - 2;
if (tlr0 > config->cycles_max) {
LOG_ERR("tlr0 out of range (0x%08x > 0x%08x)", tlr0,
config->cycles_max);
return -ENOTSUP;
}
if (flags & PWM_POLARITY_INVERTED) {
/*
* Since this is a single-channel PWM controller (with
* no other channels to phase align with) inverse
* polarity can be achieved simply by inverting the
* pulse.
*/
if ((period_cycles - pulse_cycles) < 2) {
LOG_ERR("pulse cycles too narrow");
return -ENOTSUP;
}
/* PWM_HIGH_TIME = (TLR1 + 2) * AXI_CLOCK_PERIOD */
tlr1 = period_cycles - pulse_cycles - 2;
} else {
if (pulse_cycles < 2) {
LOG_ERR("pulse cycles too narrow");
return -ENOTSUP;
}
/* PWM_HIGH_TIME = (TLR1 + 2) * AXI_CLOCK_PERIOD */
tlr1 = pulse_cycles - 2;
}
LOG_DBG("tlr0 = 0x%08x, tlr1 = 0x%08x", tlr0, tlr1);
/* Stop both timers */
xlnx_axi_timer_write32(dev, TCSR_PWM, TCSR0_OFFSET);
xlnx_axi_timer_write32(dev, TCSR_PWM, TCSR1_OFFSET);
/* Load period cycles */
xlnx_axi_timer_write32(dev, tlr0, TLR0_OFFSET);
xlnx_axi_timer_write32(dev, TCSR_PWM | TCSR_LOAD, TCSR0_OFFSET);
/* Load pulse cycles */
xlnx_axi_timer_write32(dev, tlr1, TLR1_OFFSET);
xlnx_axi_timer_write32(dev, TCSR_PWM | TCSR_LOAD, TCSR1_OFFSET);
/* Start both timers */
tcsr1 |= TCSR_ENALL;
}
xlnx_axi_timer_write32(dev, tcsr0, TCSR0_OFFSET);
xlnx_axi_timer_write32(dev, tcsr1, TCSR1_OFFSET);
return 0;
}
static int xlnx_axi_timer_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct xlnx_axi_timer_config *config = dev->config;
ARG_UNUSED(channel);
*cycles = config->freq;
return 0;
}
static const struct pwm_driver_api xlnx_axi_timer_driver_api = {
.set_cycles = xlnx_axi_timer_set_cycles,
.get_cycles_per_sec = xlnx_axi_timer_get_cycles_per_sec,
};
#define XLNX_AXI_TIMER_ASSERT_PROP_VAL(n, prop, val, str) \
BUILD_ASSERT(DT_INST_PROP(n, prop) == val, str)
#define XLNX_AXI_TIMER_INIT(n) \
XLNX_AXI_TIMER_ASSERT_PROP_VAL(n, xlnx_gen0_assert, 1, \
"xlnx,gen0-assert must be 1 for pwm"); \
XLNX_AXI_TIMER_ASSERT_PROP_VAL(n, xlnx_gen1_assert, 1, \
"xlnx,gen1-assert must be 1 for pwm"); \
XLNX_AXI_TIMER_ASSERT_PROP_VAL(n, xlnx_one_timer_only, 0, \
"xlnx,one-timer-only must be 0 for pwm"); \
\
static struct xlnx_axi_timer_config xlnx_axi_timer_config_##n = { \
.base = DT_INST_REG_ADDR(n), \
.freq = DT_INST_PROP(n, clock_frequency), \
.cycles_max = \
GENMASK(DT_INST_PROP(n, xlnx_count_width) - 1, 0), \
}; \
\
DEVICE_DT_INST_DEFINE(n, NULL, NULL, NULL, \
&xlnx_axi_timer_config_##n, \
POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&xlnx_axi_timer_driver_api)
DT_INST_FOREACH_STATUS_OKAY(XLNX_AXI_TIMER_INIT);
``` | /content/code_sandbox/drivers/pwm/pwm_xlnx_axi_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,742 |
```c
/*
*
* Heavily based on pwm_mcux_ftm.c, which is:
*
*/
#define DT_DRV_COMPAT nxp_kinetis_tpm
#include <zephyr/drivers/clock_control.h>
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <soc.h>
#include <fsl_tpm.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_tpm, CONFIG_PWM_LOG_LEVEL);
#define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)
struct mcux_tpm_config {
TPM_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
tpm_clock_source_t tpm_clock_source;
tpm_clock_prescale_t prescale;
uint8_t channel_count;
tpm_pwm_mode_t mode;
const struct pinctrl_dev_config *pincfg;
};
struct mcux_tpm_data {
uint32_t clock_freq;
uint32_t period_cycles;
tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS];
};
static int mcux_tpm_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct mcux_tpm_config *config = dev->config;
struct mcux_tpm_data *data = dev->data;
uint8_t duty_cycle;
if (period_cycles == 0U) {
LOG_ERR("Channel can not be set to inactive level");
return -ENOTSUP;
}
if (channel >= config->channel_count) {
LOG_ERR("Invalid channel");
return -ENOTSUP;
}
duty_cycle = pulse_cycles * 100U / period_cycles;
data->channel[channel].dutyCyclePercent = duty_cycle;
if ((flags & PWM_POLARITY_INVERTED) == 0) {
data->channel[channel].level = kTPM_HighTrue;
} else {
data->channel[channel].level = kTPM_LowTrue;
}
LOG_DBG("pulse_cycles=%d, period_cycles=%d, duty_cycle=%d, flags=%d",
pulse_cycles, period_cycles, duty_cycle, flags);
if (period_cycles != data->period_cycles) {
uint32_t pwm_freq;
status_t status;
if (data->period_cycles != 0) {
/* Only warn when not changing from zero */
LOG_WRN("Changing period cycles from %d to %d"
" affects all %d channels in %s",
data->period_cycles, period_cycles,
config->channel_count, dev->name);
}
data->period_cycles = period_cycles;
pwm_freq = (data->clock_freq >> config->prescale) /
period_cycles;
LOG_DBG("pwm_freq=%d, clock_freq=%d", pwm_freq,
data->clock_freq);
if (pwm_freq == 0U) {
LOG_ERR("Could not set up pwm_freq=%d", pwm_freq);
return -EINVAL;
}
TPM_StopTimer(config->base);
status = TPM_SetupPwm(config->base, data->channel,
config->channel_count, config->mode,
pwm_freq, data->clock_freq);
if (status != kStatus_Success) {
LOG_ERR("Could not set up pwm");
return -ENOTSUP;
}
TPM_StartTimer(config->base, config->tpm_clock_source);
} else {
TPM_UpdateChnlEdgeLevelSelect(config->base, channel,
data->channel[channel].level);
TPM_UpdatePwmDutycycle(config->base, channel, config->mode,
duty_cycle);
}
return 0;
}
static int mcux_tpm_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct mcux_tpm_config *config = dev->config;
struct mcux_tpm_data *data = dev->data;
*cycles = data->clock_freq >> config->prescale;
return 0;
}
static int mcux_tpm_init(const struct device *dev)
{
const struct mcux_tpm_config *config = dev->config;
struct mcux_tpm_data *data = dev->data;
tpm_chnl_pwm_signal_param_t *channel = data->channel;
tpm_config_t tpm_config;
int i;
int err;
if (config->channel_count > ARRAY_SIZE(data->channel)) {
LOG_ERR("Invalid channel count");
return -EINVAL;
}
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
if (clock_control_on(config->clock_dev, config->clock_subsys)) {
LOG_ERR("Could not turn on clock");
return -EINVAL;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&data->clock_freq)) {
LOG_ERR("Could not get clock frequency");
return -EINVAL;
}
for (i = 0; i < config->channel_count; i++) {
channel->chnlNumber = i;
channel->level = kTPM_NoPwmSignal;
channel->dutyCyclePercent = 0;
channel->firstEdgeDelayPercent = 0;
channel++;
}
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
TPM_GetDefaultConfig(&tpm_config);
tpm_config.prescale = config->prescale;
TPM_Init(config->base, &tpm_config);
return 0;
}
static const struct pwm_driver_api mcux_tpm_driver_api = {
.set_cycles = mcux_tpm_set_cycles,
.get_cycles_per_sec = mcux_tpm_get_cycles_per_sec,
};
#define TPM_DEVICE(n) \
PINCTRL_DT_INST_DEFINE(n); \
static const struct mcux_tpm_config mcux_tpm_config_##n = { \
.base = (TPM_Type *) \
DT_INST_REG_ADDR(n), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = (clock_control_subsys_t) \
DT_INST_CLOCKS_CELL(n, name), \
.tpm_clock_source = kTPM_SystemClock, \
.prescale = kTPM_Prescale_Divide_16, \
.channel_count = FSL_FEATURE_TPM_CHANNEL_COUNTn((TPM_Type *) \
DT_INST_REG_ADDR(n)), \
.mode = kTPM_EdgeAlignedPwm, \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
static struct mcux_tpm_data mcux_tpm_data_##n; \
DEVICE_DT_INST_DEFINE(n, &mcux_tpm_init, NULL, \
&mcux_tpm_data_##n, \
&mcux_tpm_config_##n, \
POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&mcux_tpm_driver_api);
DT_INST_FOREACH_STATUS_OKAY(TPM_DEVICE)
``` | /content/code_sandbox/drivers/pwm/pwm_mcux_tpm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,545 |
```unknown
config PWM_NXP_S32_EMIOS
bool "NXP S32 PWM-eMIOS driver"
default y
depends on DT_HAS_NXP_S32_EMIOS_PWM_ENABLED
select NXP_S32_EMIOS
select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
help
Enable support for the NXP S32 PWM-eMIOS.
``` | /content/code_sandbox/drivers/pwm/Kconfig.nxp_s32_emios | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```unknown
# GECKO PWM configuration options
config PWM_GECKO
bool "GECKO MCU PWM driver"
default y
depends on DT_HAS_SILABS_GECKO_PWM_ENABLED
select SOC_GECKO_TIMER
help
This option enables the PWM driver for EXX32 GECKO family of
processors. Say y if you wish to use PWM port on EXX32
MCU.
``` | /content/code_sandbox/drivers/pwm/Kconfig.gecko | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```c
/*
*
*/
#include <nrfx_pwm.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <hal/nrf_gpio.h>
#include <stdbool.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL);
/* NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED can be undefined or defined
* to 0 or 1, hence the use of #if IS_ENABLED().
*/
#if IS_ENABLED(NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
#define ANOMALY_109_IRQ_CONNECT(...) IRQ_CONNECT(__VA_ARGS__)
#define ANOMALY_109_EGU_IRQ_CONNECT(idx) _EGU_IRQ_CONNECT(idx)
#define _EGU_IRQ_CONNECT(idx) \
extern void nrfx_egu_##idx##_irq_handler(void); \
IRQ_CONNECT(DT_IRQN(DT_NODELABEL(egu##idx)), \
DT_IRQ(DT_NODELABEL(egu##idx), priority), \
nrfx_isr, nrfx_egu_##idx##_irq_handler, 0)
#else
#define ANOMALY_109_IRQ_CONNECT(...)
#define ANOMALY_109_EGU_IRQ_CONNECT(idx)
#endif
#define PWM_NRFX_CH_POLARITY_MASK BIT(15)
#define PWM_NRFX_CH_COMPARE_MASK BIT_MASK(15)
#define PWM_NRFX_CH_VALUE(compare_value, inverted) \
(compare_value | (inverted ? 0 : PWM_NRFX_CH_POLARITY_MASK))
struct pwm_nrfx_config {
nrfx_pwm_t pwm;
nrfx_pwm_config_t initial_config;
nrf_pwm_sequence_t seq;
const struct pinctrl_dev_config *pcfg;
};
struct pwm_nrfx_data {
uint32_t period_cycles;
/* Bit mask indicating channels that need the PWM generation. */
uint8_t pwm_needed;
uint8_t prescaler;
bool stop_requested;
};
/* Ensure the pwm_needed bit mask can accommodate all available channels. */
#if (NRF_PWM_CHANNEL_COUNT > 8)
#error "Current implementation supports maximum 8 channels."
#endif
static uint16_t *seq_values_ptr_get(const struct device *dev)
{
const struct pwm_nrfx_config *config = dev->config;
return (uint16_t *)config->seq.values.p_raw;
}
static bool pwm_period_check_and_set(const struct device *dev,
uint32_t channel, uint32_t period_cycles)
{
const struct pwm_nrfx_config *config = dev->config;
struct pwm_nrfx_data *data = dev->data;
uint8_t prescaler;
uint32_t countertop;
/* If the currently configured period matches the requested one,
* nothing more needs to be done.
*/
if (period_cycles == data->period_cycles) {
return true;
}
/* If any other channel is driven by the PWM peripheral, the period
* that is currently set cannot be changed, as this would influence
* the output for that channel.
*/
if ((data->pwm_needed & ~BIT(channel)) != 0) {
LOG_ERR("Incompatible period.");
return false;
}
/* Try to find a prescaler that will allow setting the requested period
* after prescaling as the countertop value for the PWM peripheral.
*/
prescaler = 0;
countertop = period_cycles;
do {
if (countertop <= PWM_COUNTERTOP_COUNTERTOP_Msk) {
data->period_cycles = period_cycles;
data->prescaler = prescaler;
nrf_pwm_configure(config->pwm.p_reg,
data->prescaler,
config->initial_config.count_mode,
(uint16_t)countertop);
return true;
}
countertop >>= 1;
++prescaler;
} while (prescaler <= PWM_PRESCALER_PRESCALER_Msk);
LOG_ERR("Prescaler for period_cycles %u not found.", period_cycles);
return false;
}
static bool channel_psel_get(uint32_t channel, uint32_t *psel,
const struct pwm_nrfx_config *config)
{
*psel = nrf_pwm_pin_get(config->pwm.p_reg, (uint8_t)channel);
return (((*psel & PWM_PSEL_OUT_CONNECT_Msk) >> PWM_PSEL_OUT_CONNECT_Pos)
== PWM_PSEL_OUT_CONNECT_Connected);
}
static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
/* We assume here that period_cycles will always be 16MHz
* peripheral clock. Since pwm_nrfx_get_cycles_per_sec() function might
* be removed, see ISSUE #6958.
* TODO: Remove this comment when issue has been resolved.
*/
const struct pwm_nrfx_config *config = dev->config;
struct pwm_nrfx_data *data = dev->data;
uint16_t compare_value;
bool inverted = (flags & PWM_POLARITY_INVERTED);
bool needs_pwm = false;
if (channel >= NRF_PWM_CHANNEL_COUNT) {
LOG_ERR("Invalid channel: %u.", channel);
return -EINVAL;
}
/* If this PWM is in center-aligned mode, pulse and period lengths
* are effectively doubled by the up-down count, so halve them here
* to compensate.
*/
if (config->initial_config.count_mode == NRF_PWM_MODE_UP_AND_DOWN) {
period_cycles /= 2;
pulse_cycles /= 2;
}
if (pulse_cycles == 0) {
/* Constantly inactive (duty 0%). */
compare_value = 0;
} else if (pulse_cycles >= period_cycles) {
/* Constantly active (duty 100%). */
/* This value is always greater than or equal to COUNTERTOP. */
compare_value = PWM_NRFX_CH_COMPARE_MASK;
} else {
/* PWM generation needed. Check if the requested period matches
* the one that is currently set, or the PWM peripheral can be
* reconfigured accordingly.
*/
if (!pwm_period_check_and_set(dev, channel, period_cycles)) {
return -EINVAL;
}
compare_value = (uint16_t)(pulse_cycles >> data->prescaler);
needs_pwm = true;
}
seq_values_ptr_get(dev)[channel] = PWM_NRFX_CH_VALUE(compare_value, inverted);
LOG_DBG("channel %u, pulse %u, period %u, prescaler: %u.",
channel, pulse_cycles, period_cycles, data->prescaler);
/* If this channel does not need to be driven by the PWM peripheral
* because its state is to be constant (duty 0% or 100%), set properly
* the GPIO configuration for its output pin. This will provide
* the correct output state for this channel when the PWM peripheral
* is stopped.
*/
if (!needs_pwm) {
uint32_t psel;
if (channel_psel_get(channel, &psel, config)) {
uint32_t out_level = (pulse_cycles == 0) ? 0 : 1;
if (inverted) {
out_level ^= 1;
}
nrf_gpio_pin_write(psel, out_level);
}
data->pwm_needed &= ~BIT(channel);
} else {
data->pwm_needed |= BIT(channel);
}
/* If the PWM generation is not needed for any channel (all are set
* to constant inactive or active state), stop the PWM peripheral.
* Otherwise, request a playback of the defined sequence so that
* the PWM peripheral loads `seq_values` into its internal compare
* registers and drives its outputs accordingly.
*/
if (data->pwm_needed == 0) {
/* Don't wait here for the peripheral to actually stop. Instead,
* ensure it is stopped before starting the next playback.
*/
nrfx_pwm_stop(&config->pwm, false);
data->stop_requested = true;
} else {
if (data->stop_requested) {
data->stop_requested = false;
/* After a stop is requested, the PWM peripheral stops
* pulse generation at the end of the current period,
* and till that moment, it ignores any start requests,
* so ensure here that it is stopped.
*/
while (!nrfx_pwm_stopped_check(&config->pwm)) {
}
}
/* It is sufficient to play the sequence once without looping.
* The PWM generation will continue with the loaded values
* until another playback is requested (new values will be
* loaded then) or the PWM peripheral is stopped.
*/
nrfx_pwm_simple_playback(&config->pwm, &config->seq, 1, 0);
}
return 0;
}
static int pwm_nrfx_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
/* TODO: Since this function might be removed, we will always return
* 16MHz from this function and handle the conversion with prescaler,
* etc, in the pin set function. See issue #6958.
*/
*cycles = 16ul * 1000ul * 1000ul;
return 0;
}
static const struct pwm_driver_api pwm_nrfx_drv_api_funcs = {
.set_cycles = pwm_nrfx_set_cycles,
.get_cycles_per_sec = pwm_nrfx_get_cycles_per_sec,
};
static int pwm_nrfx_init(const struct device *dev)
{
const struct pwm_nrfx_config *config = dev->config;
uint8_t initially_inverted = 0;
int ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
ANOMALY_109_EGU_IRQ_CONNECT(NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE);
if (ret < 0) {
return ret;
}
for (size_t i = 0; i < NRF_PWM_CHANNEL_COUNT; i++) {
uint32_t psel;
if (channel_psel_get(i, &psel, config)) {
/* Mark channels as inverted according to what initial
* state of their outputs has been set by pinctrl (high
* idle state means that the channel is inverted).
*/
initially_inverted |= nrf_gpio_pin_out_read(psel) ?
BIT(i) : 0;
}
}
for (size_t i = 0; i < NRF_PWM_CHANNEL_COUNT; i++) {
bool inverted = initially_inverted & BIT(i);
seq_values_ptr_get(dev)[i] = PWM_NRFX_CH_VALUE(0, inverted);
}
nrfx_err_t result = nrfx_pwm_init(&config->pwm,
&config->initial_config,
NULL,
NULL);
if (result != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize device: %s", dev->name);
return -EBUSY;
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static void pwm_nrfx_uninit(const struct device *dev)
{
const struct pwm_nrfx_config *config = dev->config;
nrfx_pwm_uninit(&config->pwm);
memset(dev->data, 0, sizeof(struct pwm_nrfx_data));
}
static int pwm_nrfx_pm_action(const struct device *dev,
enum pm_device_action action)
{
const struct pwm_nrfx_config *config = dev->config;
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
ret = pwm_nrfx_init(dev);
break;
case PM_DEVICE_ACTION_SUSPEND:
pwm_nrfx_uninit(dev);
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
if (ret < 0) {
return ret;
}
break;
default:
return -ENOTSUP;
}
return ret;
}
#else
#define pwm_nrfx_pm_action NULL
#endif /* CONFIG_PM_DEVICE */
#define PWM(dev_idx) DT_NODELABEL(pwm##dev_idx)
#define PWM_PROP(dev_idx, prop) DT_PROP(PWM(dev_idx), prop)
#define PWM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(PWM(idx), prop)
#define PWM_MEMORY_SECTION(idx) \
COND_CODE_1(PWM_HAS_PROP(idx, memory_regions), \
(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
DT_PHANDLE(PWM(idx), memory_regions)))))), \
())
#define PWM_NRFX_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(PWM(idx)); \
static struct pwm_nrfx_data pwm_nrfx_##idx##_data; \
static uint16_t pwm_##idx##_seq_values[NRF_PWM_CHANNEL_COUNT] \
PWM_MEMORY_SECTION(idx); \
PINCTRL_DT_DEFINE(PWM(idx)); \
static const struct pwm_nrfx_config pwm_nrfx_##idx##_config = { \
.pwm = NRFX_PWM_INSTANCE(idx), \
.initial_config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.base_clock = NRF_PWM_CLK_1MHz, \
.count_mode = (PWM_PROP(idx, center_aligned) \
? NRF_PWM_MODE_UP_AND_DOWN \
: NRF_PWM_MODE_UP), \
.top_value = 1000, \
.load_mode = NRF_PWM_LOAD_INDIVIDUAL, \
.step_mode = NRF_PWM_STEP_TRIGGERED, \
}, \
.seq.values.p_raw = pwm_##idx##_seq_values, \
.seq.length = NRF_PWM_CHANNEL_COUNT, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(PWM(idx)), \
}; \
static int pwm_nrfx_init##idx(const struct device *dev) \
{ \
ANOMALY_109_IRQ_CONNECT( \
DT_IRQN(PWM(idx)), DT_IRQ(PWM(idx), priority), \
nrfx_isr, nrfx_pwm_##idx##_irq_handler, 0); \
return pwm_nrfx_init(dev); \
}; \
PM_DEVICE_DT_DEFINE(PWM(idx), pwm_nrfx_pm_action); \
DEVICE_DT_DEFINE(PWM(idx), \
pwm_nrfx_init##idx, PM_DEVICE_DT_GET(PWM(idx)), \
&pwm_nrfx_##idx##_data, \
&pwm_nrfx_##idx##_config, \
POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&pwm_nrfx_drv_api_funcs)
#ifdef CONFIG_HAS_HW_NRF_PWM0
PWM_NRFX_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM1
PWM_NRFX_DEVICE(1);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM2
PWM_NRFX_DEVICE(2);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM3
PWM_NRFX_DEVICE(3);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM20
PWM_NRFX_DEVICE(20);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM21
PWM_NRFX_DEVICE(21);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM22
PWM_NRFX_DEVICE(22);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM120
PWM_NRFX_DEVICE(120);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM130
PWM_NRFX_DEVICE(130);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM131
PWM_NRFX_DEVICE(131);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM132
PWM_NRFX_DEVICE(132);
#endif
#ifdef CONFIG_HAS_HW_NRF_PWM133
PWM_NRFX_DEVICE(133);
#endif
``` | /content/code_sandbox/drivers/pwm/pwm_nrfx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,479 |
```unknown
config PWM_NXP_FLEXIO
bool "NXP Flexio PWM driver"
default y
depends on DT_HAS_NXP_FLEXIO_ENABLED
depends on CLOCK_CONTROL
depends on DT_HAS_NXP_FLEXIO_PWM_ENABLED
select MCUX_FLEXIO
help
Enable flexio based pwm driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.nxp_flexio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
# STM32 PWM configuration options
config PWM_STM32
bool "STM32 MCU PWM driver"
default y
depends on DT_HAS_ST_STM32_PWM_ENABLED
select USE_STM32_LL_TIM
select USE_STM32_LL_RCC if SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X
select RESET
help
This option enables the PWM driver for STM32 family of
processors. Say y if you wish to use PWM port on STM32
MCU.
``` | /content/code_sandbox/drivers/pwm/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 120 |
```unknown
config PWM_CC13XX_CC26XX_TIMER
bool "TI SimpleLink CC13xx/CC26xx GPT timer PWM driver"
default y
depends on DT_HAS_TI_CC13XX_CC26XX_TIMER_PWM_ENABLED
help
Enables TI SimpleLink CC13xx/CC26xx GPT timer PWM driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.cc13xx_cc26xx_timer | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```c
/*
* Organisation (CSIRO) ABN 41 687 119 230.
*
*/
/*
* This is not a real PWM driver. It is used to instantiate struct
* devices for the "vnd,pwm" devicetree compatible used in test code.
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/pwm.h>
#define DT_DRV_COMPAT vnd_pwm
static int vnd_pwm_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
return -ENOTSUP;
}
#ifdef CONFIG_PWM_CAPTURE
static int vnd_pwm_configure_capture(const struct device *dev, uint32_t channel,
pwm_flags_t flags,
pwm_capture_callback_handler_t cb,
void *user_data)
{
return -ENOTSUP;
}
static int vnd_pwm_enable_capture(const struct device *dev, uint32_t channel)
{
return -ENOTSUP;
}
static int vnd_pwm_disable_capture(const struct device *dev, uint32_t channel)
{
return -ENOTSUP;
}
#endif /* CONFIG_PWM_CAPTURE */
static int vnd_pwm_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
return -ENOTSUP;
}
static const struct pwm_driver_api vnd_pwm_api = {
.set_cycles = vnd_pwm_set_cycles,
#ifdef CONFIG_PWM_CAPTURE
.configure_capture = vnd_pwm_configure_capture,
.enable_capture = vnd_pwm_enable_capture,
.disable_capture = vnd_pwm_disable_capture,
#endif /* CONFIG_PWM_CAPTURE */
.get_cycles_per_sec = vnd_pwm_get_cycles_per_sec,
};
#define VND_PWM_INIT(n) \
DEVICE_DT_INST_DEFINE(n, NULL, NULL, NULL, NULL, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, &vnd_pwm_api);
DT_INST_FOREACH_STATUS_OKAY(VND_PWM_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_test.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 405 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_flexio_pwm
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <fsl_flexio.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/misc/nxp_flexio/nxp_flexio.h>
LOG_MODULE_REGISTER(pwm_nxp_flexio, CONFIG_PWM_LOG_LEVEL);
#define FLEXIO_PWM_TIMER_CMP_MAX_VALUE (0xFFFFU)
#define FLEXIO_PWM_TIMCMP_CMP_UPPER_SHIFT (0x8U)
#define FLEXIO_MAX_PWM_CHANNELS 8
enum pwm_nxp_flexio_polarity {
FLEXIO_PWM_ACTIVE_HIGH = 0x0U,
FLEXIO_PWM_ACTIVE_LOW = 0x1U
};
enum pwm_nxp_flexio_timerinit {
/** Timer Initial output is logic one */
FLEXIO_PWM_TIMER_INIT_HIGH = 0x00U,
/** Timer Initial output is logic zero */
FLEXIO_PWM_TIMER_INIT_LOW = 0x1U
};
enum pwm_nxp_flexio_prescaler {
/* Decrement counter on Flexio clock */
FLEXIO_PWM_CLK_DIV_1 = 0U,
/* Decrement counter on Flexio clock divided by 16 */
FLEXIO_PWM_CLK_DIV_16 = 4U,
/* Decrement counter on Flexio clock divided by 256 */
FLEXIO_PWM_CLK_DIV_256 = 5U
};
enum pwm_nxp_flexio_timer_mode {
/** Timer disabled */
FLEXIO_PWM_TIMER_DISABLED = 0x00U,
/** Timer in 8 bit Pwm High mode */
FLEXIO_PWM_TIMER_PWM_HIGH = 0x02U,
/** Timer in 8 bit Pwm Low mode */
FLEXIO_PWM_TIMER_PWM_LOW = 0x06U
};
enum pwm_nxp_flexio_timer_pin {
/** Timer Pin output disabled */
FLEXIO_PWM_TIMER_PIN_OUTPUT_DISABLE = 0x00U,
/** Timer Pin Output mode */
FLEXIO_PWM_TIMER_PIN_OUTPUT_ENABLE = 0x03U
};
struct pwm_nxp_flexio_channel_config {
/** Flexio used pin index */
uint8_t pin_id;
/** Counter decrement clock prescaler */
enum pwm_nxp_flexio_prescaler prescaler;
/** Actual Prescaler divisor */
uint8_t prescaler_div;
};
struct pwm_nxp_flexio_pulse_info {
uint8_t pwm_pulse_channels;
struct pwm_nxp_flexio_channel_config *pwm_info;
};
struct pwm_nxp_flexio_config {
const struct device *flexio_dev;
FLEXIO_Type *flexio_base;
const struct pinctrl_dev_config *pincfg;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
const struct pwm_nxp_flexio_pulse_info *pulse_info;
const struct nxp_flexio_child *child;
};
struct pwm_nxp_flexio_data {
uint32_t period_cycles[FLEXIO_MAX_PWM_CHANNELS];
uint32_t flexio_clk;
};
static int pwm_nxp_flexio_set_cycles(const struct device *dev,
uint32_t channel, uint32_t period_cycles,
uint32_t pulse_cycles, pwm_flags_t flags)
{
const struct pwm_nxp_flexio_config *config = dev->config;
struct pwm_nxp_flexio_data *data = dev->data;
flexio_timer_config_t timerConfig;
struct pwm_nxp_flexio_channel_config *pwm_info;
FLEXIO_Type *flexio_base = (FLEXIO_Type *)(config->flexio_base);
struct nxp_flexio_child *child = (struct nxp_flexio_child *)(config->child);
enum pwm_nxp_flexio_polarity polarity;
/* Check received parameters for sanity */
if (channel >= config->pulse_info->pwm_pulse_channels) {
LOG_ERR("Invalid channel");
return -EINVAL;
}
if (period_cycles == 0) {
LOG_ERR("Channel can not be set to inactive level");
return -ENOTSUP;
}
if (FLEXIO_PWM_TIMER_CMP_MAX_VALUE <= (uint16_t)pulse_cycles) {
LOG_ERR("Duty cycle is out of range");
return -EINVAL;
}
if (FLEXIO_PWM_TIMER_CMP_MAX_VALUE <= (uint16_t)(period_cycles - pulse_cycles)) {
LOG_ERR("low period of the cycle is out of range");
return -EINVAL;
}
if (pulse_cycles > period_cycles) {
LOG_ERR("Duty cycle cannot be greater than 100 percent");
return -EINVAL;
}
pwm_info = &config->pulse_info->pwm_info[channel];
if ((flags & PWM_POLARITY_INVERTED) == 0) {
polarity = FLEXIO_PWM_ACTIVE_HIGH;
} else {
polarity = FLEXIO_PWM_ACTIVE_LOW;
}
if (polarity == FLEXIO_PWM_ACTIVE_HIGH) {
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitPWM;
} else {
timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitPWMLow;
}
data->period_cycles[channel] = period_cycles;
timerConfig.timerCompare = ((uint8_t)(pulse_cycles - 1U)) |
((uint8_t)(data->period_cycles[channel] - pulse_cycles - 1U)
<< FLEXIO_PWM_TIMCMP_CMP_UPPER_SHIFT);
timerConfig.timerDecrement = pwm_info->prescaler;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.timerEnable = kFLEXIO_TimerEnabledAlways;
timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
/* Enable the pin out for the selected timer */
timerConfig.pinConfig = FLEXIO_PWM_TIMER_PIN_OUTPUT_ENABLE;
timerConfig.pinPolarity = polarity;
/* Select the pin that the selected timer will output the signal on */
timerConfig.pinSelect = pwm_info->pin_id;
FLEXIO_SetTimerConfig(flexio_base, child->res.timer_index[channel], &timerConfig);
#if (defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER)
/* Disable pin override if active to support channels working in cases not 0% 100% */
if (FLEXIO_GetPinOverride(flexio_base, pwm_info->pin_id)) {
FLEXIO_ConfigPinOverride(flexio_base, pwm_info->pin_id, false);
}
#endif
return 0;
}
static int pwm_nxp_flexio_get_cycles_per_sec(const struct device *dev,
uint32_t channel,
uint64_t *cycles)
{
const struct pwm_nxp_flexio_config *config = dev->config;
struct pwm_nxp_flexio_data *data = dev->data;
struct pwm_nxp_flexio_channel_config *pwm_info;
/* If get_cycles is called directly after init */
if (data->period_cycles[channel] == 0) {
LOG_ERR("First set the period of this channel to a non zero value");
return -ENOTSUP;
}
pwm_info = &config->pulse_info->pwm_info[channel];
*cycles = (uint64_t)(((data->flexio_clk) * 2) /
((data->period_cycles[channel]) * (pwm_info->prescaler_div)));
return 0;
}
static int mcux_flexio_pwm_init(const struct device *dev)
{
const struct pwm_nxp_flexio_config *config = dev->config;
struct pwm_nxp_flexio_data *data = dev->data;
flexio_timer_config_t timerConfig;
uint8_t ch_id = 0;
int err;
struct pwm_nxp_flexio_channel_config *pwm_info;
FLEXIO_Type *flexio_base = (FLEXIO_Type *)(config->flexio_base);
struct nxp_flexio_child *child = (struct nxp_flexio_child *)(config->child);
if (!device_is_ready(config->clock_dev)) {
return -ENODEV;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&data->flexio_clk)) {
return -EINVAL;
}
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
err = nxp_flexio_child_attach(config->flexio_dev, child);
if (err < 0) {
return err;
}
for (ch_id = 0; ch_id < config->pulse_info->pwm_pulse_channels; ch_id++) {
pwm_info = &config->pulse_info->pwm_info[ch_id];
/* Reset timer settings */
(void)memset(&timerConfig, 0, sizeof(timerConfig));
FLEXIO_SetTimerConfig(flexio_base, child->res.timer_index[ch_id], &timerConfig);
#if (defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER)
/* Reset the value driven on the corresponding pin */
FLEXIO_SetPinLevel(flexio_base, pwm_info->pin_id, false);
FLEXIO_ConfigPinOverride(flexio_base, pwm_info->pin_id, false);
#endif
/* Timer output is logic one and is not affected by timer reset */
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
/* Set the timer mode to dual 8-bit counter PWM high */
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitPWM;
/* Timer scaling factor w.r.t Flexio Clock */
timerConfig.timerDecrement = pwm_info->prescaler;
/* Program the PWM pulse */
timerConfig.timerCompare = 0;
/* Configure Timer CFG and CTL bits to support PWM mode */
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.timerEnable = kFLEXIO_TimerEnabledAlways;
timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
/* Enable the pin out and set a default polarity for the selected timer */
timerConfig.pinConfig = FLEXIO_PWM_TIMER_PIN_OUTPUT_ENABLE;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
/* Select the pin that the selected timer will output the signal on */
timerConfig.pinSelect = pwm_info->pin_id;
FLEXIO_SetTimerConfig(flexio_base, child->res.timer_index[ch_id], &timerConfig);
}
return 0;
}
static const struct pwm_driver_api pwm_nxp_flexio_driver_api = {
.set_cycles = pwm_nxp_flexio_set_cycles,
.get_cycles_per_sec = pwm_nxp_flexio_get_cycles_per_sec,
};
#define _FLEXIO_PWM_PULSE_GEN_CONFIG(n) \
{ \
.pin_id = DT_PROP(n, pin_id), \
.prescaler = _CONCAT(FLEXIO_PWM_CLK_DIV_, DT_PROP(n, prescaler)), \
.prescaler_div = DT_PROP(n, prescaler), \
},
#define FLEXIO_PWM_PULSE_GEN_CONFIG(n) \
static struct pwm_nxp_flexio_channel_config flexio_pwm_##n##_init[] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, _FLEXIO_PWM_PULSE_GEN_CONFIG) \
}; \
static const struct pwm_nxp_flexio_pulse_info flexio_pwm_##n##_info = { \
.pwm_pulse_channels = ARRAY_SIZE(flexio_pwm_##n##_init), \
.pwm_info = flexio_pwm_##n##_init, \
};
#define FLEXIO_PWM_TIMER_INDEX_INIT(n) \
static uint8_t flexio_pwm_##n##_timer_index[ARRAY_SIZE(flexio_pwm_##n##_init)];
#define FLEXIO_PWM_CHILD_CONFIG(n) \
static const struct nxp_flexio_child mcux_flexio_pwm_child_##n = { \
.isr = NULL, \
.user_data = NULL, \
.res = { \
.shifter_index = NULL, \
.shifter_count = 0, \
.timer_index = (uint8_t *)flexio_pwm_##n##_timer_index, \
.timer_count = ARRAY_SIZE(flexio_pwm_##n##_init) \
} \
};
#define FLEXIO_PWM_PULSE_GEN_GET_CONFIG(n) \
.pulse_info = &flexio_pwm_##n##_info,
#define PWM_NXP_FLEXIO_PWM_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
FLEXIO_PWM_PULSE_GEN_CONFIG(n) \
FLEXIO_PWM_TIMER_INDEX_INIT(n) \
FLEXIO_PWM_CHILD_CONFIG(n) \
static const struct pwm_nxp_flexio_config pwm_nxp_flexio_config_##n = { \
.flexio_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), \
.flexio_base = (FLEXIO_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
.clock_subsys = (clock_control_subsys_t)DT_CLOCKS_CELL(DT_INST_PARENT(n), name),\
.child = &mcux_flexio_pwm_child_##n, \
FLEXIO_PWM_PULSE_GEN_GET_CONFIG(n) \
}; \
\
static struct pwm_nxp_flexio_data pwm_nxp_flexio_data_##n; \
DEVICE_DT_INST_DEFINE(n, \
&mcux_flexio_pwm_init, \
NULL, \
&pwm_nxp_flexio_data_##n, \
&pwm_nxp_flexio_config_##n, \
POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&pwm_nxp_flexio_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_NXP_FLEXIO_PWM_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_nxp_flexio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,218 |
```c
/*
*
*/
#define DT_DRV_COMPAT st_stm32_pwm
#include <errno.h>
#include <soc.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_tim.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(pwm_stm32, CONFIG_PWM_LOG_LEVEL);
/* L0 series MCUs only have 16-bit timers and don't have below macro defined */
#ifndef IS_TIM_32B_COUNTER_INSTANCE
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
#endif
#ifdef CONFIG_PWM_CAPTURE
/**
* @brief Capture state when in 4-channel support mode
*/
enum capture_state {
CAPTURE_STATE_IDLE = 0,
CAPTURE_STATE_WAIT_FOR_UPDATE_EVENT = 1,
CAPTURE_STATE_WAIT_FOR_PULSE_START = 2,
CAPTURE_STATE_WAIT_FOR_PERIOD_END = 3
};
/** Return the complimentary channel number
* that is used to capture the end of the pulse.
*/
static const uint32_t complimentary_channel[] = {0, 2, 1, 4, 3};
struct pwm_stm32_capture_data {
pwm_capture_callback_handler_t callback;
void *user_data;
uint32_t period;
uint32_t pulse;
uint32_t overflows;
uint8_t skip_irq;
bool capture_period;
bool capture_pulse;
bool continuous;
uint8_t channel;
/* only used when four_channel_capture_support */
enum capture_state state;
};
/* When PWM capture is done by resetting the counter with UIF then the
* first capture is always nonsense, second is nonsense when polarity changed
* This is not the case when using four-channel-support.
*/
#define SKIPPED_PWM_CAPTURES 2u
#endif /*CONFIG_PWM_CAPTURE*/
/** PWM data. */
struct pwm_stm32_data {
/** Timer clock (Hz). */
uint32_t tim_clk;
/* Reset controller device configuration */
const struct reset_dt_spec reset;
#ifdef CONFIG_PWM_CAPTURE
struct pwm_stm32_capture_data capture;
#endif /* CONFIG_PWM_CAPTURE */
};
/** PWM configuration. */
struct pwm_stm32_config {
TIM_TypeDef *timer;
uint32_t prescaler;
uint32_t countermode;
struct stm32_pclken pclken;
const struct pinctrl_dev_config *pcfg;
#ifdef CONFIG_PWM_CAPTURE
void (*irq_config_func)(const struct device *dev);
const bool four_channel_capture_support;
#endif /* CONFIG_PWM_CAPTURE */
};
/** Maximum number of timer channels : some stm32 soc have 6 else only 4 */
#if defined(LL_TIM_CHANNEL_CH6)
#define TIMER_HAS_6CH 1
#define TIMER_MAX_CH 6u
#else
#define TIMER_HAS_6CH 0
#define TIMER_MAX_CH 4u
#endif
/** Channel to LL mapping. */
static const uint32_t ch2ll[TIMER_MAX_CH] = {
LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2,
LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4,
#if TIMER_HAS_6CH
LL_TIM_CHANNEL_CH5, LL_TIM_CHANNEL_CH6
#endif
};
/** Some stm32 mcus have complementary channels : 3 or 4 */
static const uint32_t ch2ll_n[] = {
#if defined(LL_TIM_CHANNEL_CH1N)
LL_TIM_CHANNEL_CH1N,
LL_TIM_CHANNEL_CH2N,
LL_TIM_CHANNEL_CH3N,
#if defined(LL_TIM_CHANNEL_CH4N)
/** stm32g4x and stm32u5x have 4 complementary channels */
LL_TIM_CHANNEL_CH4N,
#endif /* LL_TIM_CHANNEL_CH4N */
#endif /* LL_TIM_CHANNEL_CH1N */
};
/** Maximum number of complemented timer channels is ARRAY_SIZE(ch2ll_n)*/
/** Channel to compare set function mapping. */
static void (*const set_timer_compare[TIMER_MAX_CH])(TIM_TypeDef *,
uint32_t) = {
LL_TIM_OC_SetCompareCH1, LL_TIM_OC_SetCompareCH2,
LL_TIM_OC_SetCompareCH3, LL_TIM_OC_SetCompareCH4,
#if TIMER_HAS_6CH
LL_TIM_OC_SetCompareCH5, LL_TIM_OC_SetCompareCH6
#endif
};
/** Channel to capture get function mapping. */
#if !defined(CONFIG_SOC_SERIES_STM32MP1X)
static uint32_t __maybe_unused (*const get_channel_capture[])(const TIM_TypeDef *) = {
#else
static uint32_t __maybe_unused (*const get_channel_capture[])(TIM_TypeDef *) = {
#endif
LL_TIM_IC_GetCaptureCH1, LL_TIM_IC_GetCaptureCH2,
LL_TIM_IC_GetCaptureCH3, LL_TIM_IC_GetCaptureCH4
};
/** Channel to enable capture interrupt mapping. */
static void __maybe_unused (*const enable_capture_interrupt[])(TIM_TypeDef *) = {
LL_TIM_EnableIT_CC1, LL_TIM_EnableIT_CC2,
LL_TIM_EnableIT_CC3, LL_TIM_EnableIT_CC4
};
/** Channel to disable capture interrupt mapping. */
static void __maybe_unused (*const disable_capture_interrupt[])(TIM_TypeDef *) = {
LL_TIM_DisableIT_CC1, LL_TIM_DisableIT_CC2,
LL_TIM_DisableIT_CC3, LL_TIM_DisableIT_CC4
};
/** Channel to is capture active flag mapping. */
#if !defined(CONFIG_SOC_SERIES_STM32MP1X)
static uint32_t __maybe_unused (*const is_capture_active[])(const TIM_TypeDef *) = {
#else
static uint32_t __maybe_unused (*const is_capture_active[])(TIM_TypeDef *) = {
#endif
LL_TIM_IsActiveFlag_CC1, LL_TIM_IsActiveFlag_CC2,
LL_TIM_IsActiveFlag_CC3, LL_TIM_IsActiveFlag_CC4
};
/** Channel to clearing capture flag mapping. */
static void __maybe_unused (*const clear_capture_interrupt[])(TIM_TypeDef *) = {
LL_TIM_ClearFlag_CC1, LL_TIM_ClearFlag_CC2,
LL_TIM_ClearFlag_CC3, LL_TIM_ClearFlag_CC4
};
/**
* Obtain LL polarity from PWM flags.
*
* @param flags PWM flags.
*
* @return LL polarity.
*/
static uint32_t get_polarity(pwm_flags_t flags)
{
if ((flags & PWM_POLARITY_MASK) == PWM_POLARITY_NORMAL) {
return LL_TIM_OCPOLARITY_HIGH;
}
return LL_TIM_OCPOLARITY_LOW;
}
/**
* @brief Check if LL counter mode is center-aligned.
*
* @param ll_countermode LL counter mode.
*
* @return `true` when center-aligned, otherwise `false`.
*/
static inline bool is_center_aligned(const uint32_t ll_countermode)
{
return ((ll_countermode == LL_TIM_COUNTERMODE_CENTER_DOWN) ||
(ll_countermode == LL_TIM_COUNTERMODE_CENTER_UP) ||
(ll_countermode == LL_TIM_COUNTERMODE_CENTER_UP_DOWN));
}
/**
* Obtain timer clock speed.
*
* @param pclken Timer clock control subsystem.
* @param tim_clk Where computed timer clock will be stored.
*
* @return 0 on success, error code otherwise.
*/
static int get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk)
{
int r;
const struct device *clk;
uint32_t bus_clk, apb_psc;
clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
r = clock_control_get_rate(clk, (clock_control_subsys_t)pclken,
&bus_clk);
if (r < 0) {
return r;
}
#if defined(CONFIG_SOC_SERIES_STM32H7X)
if (pclken->bus == STM32_CLOCK_BUS_APB1) {
apb_psc = STM32_D2PPRE1;
} else {
apb_psc = STM32_D2PPRE2;
}
#else
if (pclken->bus == STM32_CLOCK_BUS_APB1) {
#if defined(CONFIG_SOC_SERIES_STM32MP1X)
apb_psc = (uint32_t)(READ_BIT(RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV));
#else
apb_psc = STM32_APB1_PRESCALER;
#endif
}
#if !defined(CONFIG_SOC_SERIES_STM32C0X) && !defined(CONFIG_SOC_SERIES_STM32F0X) && \
!defined(CONFIG_SOC_SERIES_STM32G0X)
else {
#if defined(CONFIG_SOC_SERIES_STM32MP1X)
apb_psc = (uint32_t)(READ_BIT(RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV));
#else
apb_psc = STM32_APB2_PRESCALER;
#endif
}
#endif
#endif
#if defined(RCC_DCKCFGR_TIMPRE) || defined(RCC_DCKCFGR1_TIMPRE) || \
defined(RCC_CFGR_TIMPRE)
/*
* There are certain series (some F4, F7 and H7) that have the TIMPRE
* bit to control the clock frequency of all the timers connected to
* APB1 and APB2 domains.
*
* Up to a certain threshold value of APB{1,2} prescaler, timer clock
* equals to HCLK. This threshold value depends on TIMPRE setting
* (2 if TIMPRE=0, 4 if TIMPRE=1). Above threshold, timer clock is set
* to a multiple of the APB domain clock PCLK{1,2} (2 if TIMPRE=0, 4 if
* TIMPRE=1).
*/
if (LL_RCC_GetTIMPrescaler() == LL_RCC_TIM_PRESCALER_TWICE) {
/* TIMPRE = 0 */
if (apb_psc <= 2u) {
LL_RCC_ClocksTypeDef clocks;
LL_RCC_GetSystemClocksFreq(&clocks);
*tim_clk = clocks.HCLK_Frequency;
} else {
*tim_clk = bus_clk * 2u;
}
} else {
/* TIMPRE = 1 */
if (apb_psc <= 4u) {
LL_RCC_ClocksTypeDef clocks;
LL_RCC_GetSystemClocksFreq(&clocks);
*tim_clk = clocks.HCLK_Frequency;
} else {
*tim_clk = bus_clk * 4u;
}
}
#else
/*
* If the APB prescaler equals 1, the timer clock frequencies
* are set to the same frequency as that of the APB domain.
* Otherwise, they are set to twice (2) the frequency of the
* APB domain.
*/
if (apb_psc == 1u) {
*tim_clk = bus_clk;
} else {
*tim_clk = bus_clk * 2u;
}
#endif
return 0;
}
static int pwm_stm32_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_stm32_config *cfg = dev->config;
uint32_t ll_channel;
uint32_t current_ll_channel; /* complementary output if used */
uint32_t negative_ll_channel;
if (channel < 1u || channel > TIMER_MAX_CH) {
LOG_ERR("Invalid channel (%d)", channel);
return -EINVAL;
}
/*
* Non 32-bit timers count from 0 up to the value in the ARR register
* (16-bit). Thus period_cycles cannot be greater than UINT16_MAX + 1.
*/
if (!IS_TIM_32B_COUNTER_INSTANCE(cfg->timer) &&
(period_cycles > UINT16_MAX + 1)) {
LOG_ERR("Cannot set PWM output, value exceeds 16-bit timer limit.");
return -ENOTSUP;
}
#ifdef CONFIG_PWM_CAPTURE
if (LL_TIM_IsEnabledIT_CC1(cfg->timer) || LL_TIM_IsEnabledIT_CC2(cfg->timer) ||
LL_TIM_IsEnabledIT_CC3(cfg->timer) || LL_TIM_IsEnabledIT_CC4(cfg->timer)) {
LOG_ERR("Cannot set PWM output, capture in progress");
return -EBUSY;
}
#endif /* CONFIG_PWM_CAPTURE */
ll_channel = ch2ll[channel - 1u];
if (channel <= ARRAY_SIZE(ch2ll_n)) {
negative_ll_channel = ch2ll_n[channel - 1u];
} else {
negative_ll_channel = 0;
}
/* in LL_TIM_CC_DisableChannel and LL_TIM_CC_IsEnabledChannel,
* the channel param could be the complementary one
*/
if ((flags & STM32_PWM_COMPLEMENTARY_MASK) == STM32_PWM_COMPLEMENTARY) {
if (!negative_ll_channel) {
/* setting a flag on a channel that has not this capability */
LOG_ERR("Channel %d has NO complementary output", channel);
return -EINVAL;
}
current_ll_channel = negative_ll_channel;
} else {
current_ll_channel = ll_channel;
}
if (period_cycles == 0u) {
LL_TIM_CC_DisableChannel(cfg->timer, current_ll_channel);
return 0;
}
if (cfg->countermode == LL_TIM_COUNTERMODE_UP) {
/* remove 1 period cycle, accounts for 1 extra low cycle */
period_cycles -= 1U;
} else if (cfg->countermode == LL_TIM_COUNTERMODE_DOWN) {
/* remove 1 pulse cycle, accounts for 1 extra high cycle */
pulse_cycles -= 1U;
/* remove 1 period cycle, accounts for 1 extra low cycle */
period_cycles -= 1U;
} else if (is_center_aligned(cfg->countermode)) {
pulse_cycles /= 2U;
period_cycles /= 2U;
} else {
return -ENOTSUP;
}
if (!LL_TIM_CC_IsEnabledChannel(cfg->timer, current_ll_channel)) {
LL_TIM_OC_InitTypeDef oc_init;
LL_TIM_OC_StructInit(&oc_init);
oc_init.OCMode = LL_TIM_OCMODE_PWM1;
#if defined(LL_TIM_CHANNEL_CH1N)
/* the flags holds the STM32_PWM_COMPLEMENTARY information */
if ((flags & STM32_PWM_COMPLEMENTARY_MASK) == STM32_PWM_COMPLEMENTARY) {
oc_init.OCNState = LL_TIM_OCSTATE_ENABLE;
oc_init.OCNPolarity = get_polarity(flags);
/* inherit the polarity of the positive output */
oc_init.OCState = LL_TIM_CC_IsEnabledChannel(cfg->timer, ll_channel)
? LL_TIM_OCSTATE_ENABLE
: LL_TIM_OCSTATE_DISABLE;
oc_init.OCPolarity = LL_TIM_OC_GetPolarity(cfg->timer, ll_channel);
} else {
oc_init.OCState = LL_TIM_OCSTATE_ENABLE;
oc_init.OCPolarity = get_polarity(flags);
/* inherit the polarity of the negative output */
if (negative_ll_channel) {
oc_init.OCNState =
LL_TIM_CC_IsEnabledChannel(cfg->timer, negative_ll_channel)
? LL_TIM_OCSTATE_ENABLE
: LL_TIM_OCSTATE_DISABLE;
oc_init.OCNPolarity =
LL_TIM_OC_GetPolarity(cfg->timer, negative_ll_channel);
}
}
#else /* LL_TIM_CHANNEL_CH1N */
oc_init.OCState = LL_TIM_OCSTATE_ENABLE;
oc_init.OCPolarity = get_polarity(flags);
#endif /* LL_TIM_CHANNEL_CH1N */
oc_init.CompareValue = pulse_cycles;
#ifdef CONFIG_PWM_CAPTURE
if (IS_TIM_SLAVE_INSTANCE(cfg->timer)) {
LL_TIM_SetSlaveMode(cfg->timer,
LL_TIM_SLAVEMODE_DISABLED);
LL_TIM_SetTriggerInput(cfg->timer, LL_TIM_TS_ITR0);
LL_TIM_DisableMasterSlaveMode(cfg->timer);
}
#endif /* CONFIG_PWM_CAPTURE */
/* in LL_TIM_OC_Init, the channel is always the non-complementary */
if (LL_TIM_OC_Init(cfg->timer, ll_channel, &oc_init) != SUCCESS) {
LOG_ERR("Could not initialize timer channel output");
return -EIO;
}
LL_TIM_EnableARRPreload(cfg->timer);
/* in LL_TIM_OC_EnablePreload, the channel is always the non-complementary */
LL_TIM_OC_EnablePreload(cfg->timer, ll_channel);
LL_TIM_SetAutoReload(cfg->timer, period_cycles);
LL_TIM_GenerateEvent_UPDATE(cfg->timer);
} else {
/* in LL_TIM_OC_SetPolarity, the channel could be the complementary one */
LL_TIM_OC_SetPolarity(cfg->timer, current_ll_channel, get_polarity(flags));
set_timer_compare[channel - 1u](cfg->timer, pulse_cycles);
LL_TIM_SetAutoReload(cfg->timer, period_cycles);
}
return 0;
}
#ifdef CONFIG_PWM_CAPTURE
static int init_capture_channels(const struct device *dev, uint32_t channel,
pwm_flags_t flags)
{
const struct pwm_stm32_config *cfg = dev->config;
bool is_inverted = (flags & PWM_POLARITY_MASK) == PWM_POLARITY_INVERTED;
LL_TIM_IC_InitTypeDef ic;
LL_TIM_IC_StructInit(&ic);
ic.ICPrescaler = TIM_ICPSC_DIV1;
ic.ICFilter = LL_TIM_IC_FILTER_FDIV1;
/* Setup main channel */
ic.ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
ic.ICPolarity = is_inverted ? LL_TIM_IC_POLARITY_FALLING : LL_TIM_IC_POLARITY_RISING;
if (LL_TIM_IC_Init(cfg->timer, ch2ll[channel - 1], &ic) != SUCCESS) {
LOG_ERR("Could not initialize main channel for PWM capture");
return -EIO;
}
/* Setup complimentary channel */
ic.ICActiveInput = LL_TIM_ACTIVEINPUT_INDIRECTTI;
ic.ICPolarity = is_inverted ? LL_TIM_IC_POLARITY_RISING : LL_TIM_IC_POLARITY_FALLING;
if (LL_TIM_IC_Init(cfg->timer, ch2ll[complimentary_channel[channel] - 1], &ic) != SUCCESS) {
LOG_ERR("Could not initialize complimentary channel for PWM capture");
return -EIO;
}
return 0;
}
static int pwm_stm32_configure_capture(const struct device *dev,
uint32_t channel, pwm_flags_t flags,
pwm_capture_callback_handler_t cb,
void *user_data)
{
/*
* Capture is implemented in two different ways, depending on the
* four-channel-capture-support setting in the node.
* - Two Channel Support:
* Only two channels (1 and 2) are available for capture. It uses
* the slave mode controller to reset the counter on each edge.
* - Four Channel Support:
* All four channels are available for capture. Instead of the
* slave mode controller it uses the ISR to reset the counter.
* This is slightly less accurate, but still within acceptable
* bounds.
*/
const struct pwm_stm32_config *cfg = dev->config;
struct pwm_stm32_data *data = dev->data;
struct pwm_stm32_capture_data *cpt = &data->capture;
int ret;
if (!cfg->four_channel_capture_support) {
if ((channel != 1u) && (channel != 2u)) {
LOG_ERR("PWM capture only supported on first two channels");
return -ENOTSUP;
}
} else {
if ((channel < 1u) || (channel > 4u)) {
LOG_ERR("PWM capture only exists on channels 1, 2, 3 and 4.");
return -ENOTSUP;
}
}
if (LL_TIM_IsEnabledIT_CC1(cfg->timer) || LL_TIM_IsEnabledIT_CC2(cfg->timer) ||
LL_TIM_IsEnabledIT_CC3(cfg->timer) || LL_TIM_IsEnabledIT_CC4(cfg->timer)) {
LOG_ERR("PWM capture already in progress");
return -EBUSY;
}
if (!(flags & PWM_CAPTURE_TYPE_MASK)) {
LOG_ERR("No PWM capture type specified");
return -EINVAL;
}
if (!cfg->four_channel_capture_support && !IS_TIM_SLAVE_INSTANCE(cfg->timer)) {
/* slave mode is only used when not in four channel mode */
LOG_ERR("Timer does not support slave mode for PWM capture");
return -ENOTSUP;
}
cpt->callback = cb; /* even if the cb is reset, this is not an error */
cpt->user_data = user_data;
cpt->capture_period = (flags & PWM_CAPTURE_TYPE_PERIOD) ? true : false;
cpt->capture_pulse = (flags & PWM_CAPTURE_TYPE_PULSE) ? true : false;
cpt->continuous = (flags & PWM_CAPTURE_MODE_CONTINUOUS) ? true : false;
/* Prevents faulty behavior while making changes */
LL_TIM_SetSlaveMode(cfg->timer, LL_TIM_SLAVEMODE_DISABLED);
ret = init_capture_channels(dev, channel, flags);
if (ret < 0) {
return ret;
}
if (!cfg->four_channel_capture_support) {
if (channel == 1u) {
LL_TIM_SetTriggerInput(cfg->timer, LL_TIM_TS_TI1FP1);
} else {
LL_TIM_SetTriggerInput(cfg->timer, LL_TIM_TS_TI2FP2);
}
LL_TIM_SetSlaveMode(cfg->timer, LL_TIM_SLAVEMODE_RESET);
}
LL_TIM_EnableARRPreload(cfg->timer);
if (!IS_TIM_32B_COUNTER_INSTANCE(cfg->timer)) {
LL_TIM_SetAutoReload(cfg->timer, 0xffffu);
} else {
LL_TIM_SetAutoReload(cfg->timer, 0xffffffffu);
}
LL_TIM_EnableUpdateEvent(cfg->timer);
return 0;
}
static int pwm_stm32_enable_capture(const struct device *dev, uint32_t channel)
{
const struct pwm_stm32_config *cfg = dev->config;
struct pwm_stm32_data *data = dev->data;
struct pwm_stm32_capture_data *cpt = &data->capture;
if (!cfg->four_channel_capture_support) {
if ((channel != 1u) && (channel != 2u)) {
LOG_ERR("PWM capture only supported on first two channels");
return -ENOTSUP;
}
} else {
if ((channel < 1u) || (channel > 4u)) {
LOG_ERR("PWM capture only exists on channels 1, 2, 3 and 4.");
return -ENOTSUP;
}
}
if (LL_TIM_IsEnabledIT_CC1(cfg->timer) || LL_TIM_IsEnabledIT_CC2(cfg->timer) ||
LL_TIM_IsEnabledIT_CC3(cfg->timer) || LL_TIM_IsEnabledIT_CC4(cfg->timer)) {
LOG_ERR("PWM capture already active");
return -EBUSY;
}
if (!data->capture.callback) {
LOG_ERR("PWM capture not configured");
return -EINVAL;
}
cpt->channel = channel;
cpt->state = CAPTURE_STATE_WAIT_FOR_PULSE_START;
data->capture.skip_irq = cfg->four_channel_capture_support ? 0 : SKIPPED_PWM_CAPTURES;
data->capture.overflows = 0u;
clear_capture_interrupt[channel - 1](cfg->timer);
LL_TIM_ClearFlag_UPDATE(cfg->timer);
LL_TIM_SetUpdateSource(cfg->timer, LL_TIM_UPDATESOURCE_COUNTER);
enable_capture_interrupt[channel - 1](cfg->timer);
LL_TIM_CC_EnableChannel(cfg->timer, ch2ll[channel - 1]);
LL_TIM_CC_EnableChannel(cfg->timer, ch2ll[complimentary_channel[channel] - 1]);
LL_TIM_EnableIT_UPDATE(cfg->timer);
LL_TIM_GenerateEvent_UPDATE(cfg->timer);
return 0;
}
static int pwm_stm32_disable_capture(const struct device *dev, uint32_t channel)
{
const struct pwm_stm32_config *cfg = dev->config;
if (!cfg->four_channel_capture_support) {
if ((channel != 1u) && (channel != 2u)) {
LOG_ERR("PWM capture only supported on first two channels");
return -ENOTSUP;
}
} else {
if ((channel < 1u) || (channel > 4u)) {
LOG_ERR("PWM capture only exists on channels 1, 2, 3 and 4.");
return -ENOTSUP;
}
}
LL_TIM_SetUpdateSource(cfg->timer, LL_TIM_UPDATESOURCE_REGULAR);
disable_capture_interrupt[channel - 1](cfg->timer);
LL_TIM_DisableIT_UPDATE(cfg->timer);
LL_TIM_CC_DisableChannel(cfg->timer, ch2ll[channel - 1]);
LL_TIM_CC_DisableChannel(cfg->timer, ch2ll[complimentary_channel[channel] - 1]);
return 0;
}
static void pwm_stm32_isr(const struct device *dev)
{
const struct pwm_stm32_config *cfg = dev->config;
struct pwm_stm32_data *data = dev->data;
struct pwm_stm32_capture_data *cpt = &data->capture;
int status = 0;
if (cpt->skip_irq != 0u) {
if (LL_TIM_IsActiveFlag_UPDATE(cfg->timer)) {
LL_TIM_ClearFlag_UPDATE(cfg->timer);
}
if (LL_TIM_IsActiveFlag_CC1(cfg->timer)
|| LL_TIM_IsActiveFlag_CC2(cfg->timer)
|| LL_TIM_IsActiveFlag_CC3(cfg->timer)
|| LL_TIM_IsActiveFlag_CC4(cfg->timer)) {
LL_TIM_ClearFlag_CC1(cfg->timer);
LL_TIM_ClearFlag_CC2(cfg->timer);
LL_TIM_ClearFlag_CC3(cfg->timer);
LL_TIM_ClearFlag_CC4(cfg->timer);
cpt->skip_irq--;
}
return;
}
if (LL_TIM_IsActiveFlag_UPDATE(cfg->timer)) {
LL_TIM_ClearFlag_UPDATE(cfg->timer);
if (cfg->four_channel_capture_support &&
cpt->state == CAPTURE_STATE_WAIT_FOR_UPDATE_EVENT) {
/* Special handling of UPDATE event in case it's triggered */
cpt->state = CAPTURE_STATE_WAIT_FOR_PERIOD_END;
} else {
cpt->overflows++;
}
}
if (!cfg->four_channel_capture_support) {
if (is_capture_active[cpt->channel - 1](cfg->timer) ||
is_capture_active[complimentary_channel[cpt->channel] - 1](cfg->timer)) {
clear_capture_interrupt[cpt->channel - 1](cfg->timer);
clear_capture_interrupt
[complimentary_channel[cpt->channel] - 1](cfg->timer);
cpt->period = get_channel_capture[cpt->channel - 1](cfg->timer);
cpt->pulse = get_channel_capture
[complimentary_channel[cpt->channel] - 1](cfg->timer);
}
} else {
if (cpt->state == CAPTURE_STATE_WAIT_FOR_PULSE_START &&
is_capture_active[cpt->channel - 1](cfg->timer)) {
/* Reset the counter manually instead of automatically by HW
* This sets the pulse-start at 0 and makes the pulse-end
* and period related to that number. Sure we loose some
* accuracy but it's within acceptable range.
*
* This is done through an UPDATE event to also reset
* the prescalar. This could look like an overflow event
* and might therefore require special handling.
*/
cpt->state = CAPTURE_STATE_WAIT_FOR_UPDATE_EVENT;
LL_TIM_GenerateEvent_UPDATE(cfg->timer);
} else if ((cpt->state == CAPTURE_STATE_WAIT_FOR_UPDATE_EVENT ||
cpt->state == CAPTURE_STATE_WAIT_FOR_PERIOD_END) &&
is_capture_active[cpt->channel - 1](cfg->timer)) {
cpt->state = CAPTURE_STATE_IDLE;
/* The end of the period. Both capture channels should now contain
* the timer value when the pulse and period ended respectively.
*/
cpt->pulse = get_channel_capture[complimentary_channel[cpt->channel] - 1]
(cfg->timer);
cpt->period = get_channel_capture[cpt->channel - 1](cfg->timer);
}
clear_capture_interrupt[cpt->channel - 1](cfg->timer);
if (cpt->state != CAPTURE_STATE_IDLE) {
/* Still waiting for a complete capture */
return;
}
}
if (cpt->overflows) {
LOG_ERR("counter overflow during PWM capture");
status = -ERANGE;
}
if (!cpt->continuous) {
pwm_stm32_disable_capture(dev, cpt->channel);
} else {
cpt->overflows = 0u;
cpt->state = CAPTURE_STATE_WAIT_FOR_PULSE_START;
}
if (cpt->callback != NULL) {
cpt->callback(dev, cpt->channel, cpt->capture_period ? cpt->period : 0u,
cpt->capture_pulse ? cpt->pulse : 0u, status, cpt->user_data);
}
}
#endif /* CONFIG_PWM_CAPTURE */
static int pwm_stm32_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
struct pwm_stm32_data *data = dev->data;
const struct pwm_stm32_config *cfg = dev->config;
*cycles = (uint64_t)(data->tim_clk / (cfg->prescaler + 1));
return 0;
}
static const struct pwm_driver_api pwm_stm32_driver_api = {
.set_cycles = pwm_stm32_set_cycles,
.get_cycles_per_sec = pwm_stm32_get_cycles_per_sec,
#ifdef CONFIG_PWM_CAPTURE
.configure_capture = pwm_stm32_configure_capture,
.enable_capture = pwm_stm32_enable_capture,
.disable_capture = pwm_stm32_disable_capture,
#endif /* CONFIG_PWM_CAPTURE */
};
static int pwm_stm32_init(const struct device *dev)
{
struct pwm_stm32_data *data = dev->data;
const struct pwm_stm32_config *cfg = dev->config;
int r;
const struct device *clk;
LL_TIM_InitTypeDef init;
/* enable clock and store its speed */
clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
if (!device_is_ready(clk)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
r = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken);
if (r < 0) {
LOG_ERR("Could not initialize clock (%d)", r);
return r;
}
r = get_tim_clk(&cfg->pclken, &data->tim_clk);
if (r < 0) {
LOG_ERR("Could not obtain timer clock (%d)", r);
return r;
}
/* Reset timer to default state using RCC */
(void)reset_line_toggle_dt(&data->reset);
/* configure pinmux */
r = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (r < 0) {
LOG_ERR("PWM pinctrl setup failed (%d)", r);
return r;
}
/* initialize timer */
LL_TIM_StructInit(&init);
init.Prescaler = cfg->prescaler;
init.CounterMode = cfg->countermode;
init.Autoreload = 0u;
init.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
if (LL_TIM_Init(cfg->timer, &init) != SUCCESS) {
LOG_ERR("Could not initialize timer");
return -EIO;
}
#if !defined(CONFIG_SOC_SERIES_STM32L0X) && !defined(CONFIG_SOC_SERIES_STM32L1X)
/* enable outputs and counter */
if (IS_TIM_BREAK_INSTANCE(cfg->timer)) {
LL_TIM_EnableAllOutputs(cfg->timer);
}
#endif
LL_TIM_EnableCounter(cfg->timer);
#ifdef CONFIG_PWM_CAPTURE
cfg->irq_config_func(dev);
#endif /* CONFIG_PWM_CAPTURE */
return 0;
}
#define PWM(index) DT_INST_PARENT(index)
#ifdef CONFIG_PWM_CAPTURE
#define IRQ_CONNECT_AND_ENABLE_BY_NAME(index, name) \
{ \
IRQ_CONNECT(DT_IRQ_BY_NAME(PWM(index), name, irq), \
DT_IRQ_BY_NAME(PWM(index), name, priority), \
pwm_stm32_isr, DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_IRQ_BY_NAME(PWM(index), name, irq)); \
}
#define IRQ_CONNECT_AND_ENABLE_DEFAULT(index) \
{ \
IRQ_CONNECT(DT_IRQN(PWM(index)), \
DT_IRQ(PWM(index), priority), \
pwm_stm32_isr, DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_IRQN(PWM(index))); \
}
#define IRQ_CONFIG_FUNC(index) \
static void pwm_stm32_irq_config_func_##index(const struct device *dev) \
{ \
COND_CODE_1(DT_IRQ_HAS_NAME(PWM(index), cc), \
(IRQ_CONNECT_AND_ENABLE_BY_NAME(index, cc)), \
(IRQ_CONNECT_AND_ENABLE_DEFAULT(index)) \
); \
}
#define CAPTURE_INIT(index) \
.irq_config_func = pwm_stm32_irq_config_func_##index, \
.four_channel_capture_support = DT_INST_PROP(index, four_channel_capture_support)
#else
#define IRQ_CONFIG_FUNC(index)
#define CAPTURE_INIT(index)
#endif /* CONFIG_PWM_CAPTURE */
#define DT_INST_CLK(index, inst) \
{ \
.bus = DT_CLOCKS_CELL(PWM(index), bus), \
.enr = DT_CLOCKS_CELL(PWM(index), bits) \
}
#define PWM_DEVICE_INIT(index) \
static struct pwm_stm32_data pwm_stm32_data_##index = { \
.reset = RESET_DT_SPEC_GET(PWM(index)), \
}; \
\
IRQ_CONFIG_FUNC(index) \
\
PINCTRL_DT_INST_DEFINE(index); \
\
static const struct pwm_stm32_config pwm_stm32_config_##index = { \
.timer = (TIM_TypeDef *)DT_REG_ADDR(PWM(index)), \
.prescaler = DT_PROP(PWM(index), st_prescaler), \
.countermode = DT_PROP(PWM(index), st_countermode), \
.pclken = DT_INST_CLK(index, timer), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
CAPTURE_INIT(index) \
}; \
\
DEVICE_DT_INST_DEFINE(index, &pwm_stm32_init, NULL, \
&pwm_stm32_data_##index, \
&pwm_stm32_config_##index, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&pwm_stm32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,646 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_numaker_pwm
#include <zephyr/kernel.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#include <NuMicro.h>
LOG_MODULE_REGISTER(pwm_numaker, CONFIG_PWM_LOG_LEVEL);
/* 11-bit prescaler in Numaker EPWM modules */
#define NUMAKER_PWM_MAX_PRESCALER BIT(11)
#define NUMAKER_PWM_CHANNEL_COUNT 6
#define NUMAKER_PWM_RELOAD_CNT (0xFFFFU)
#define NUMAKER_SYSCLK_FREQ DT_PROP(DT_NODELABEL(sysclk), clock_frequency)
/* EPWM channel 0~5 mask */
#define NUMAKER_PWM_CHANNEL_MASK (0x3FU)
/* Device config */
struct pwm_numaker_config {
/* EPWM base address */
EPWM_T *epwm;
uint32_t prescale;
const struct reset_dt_spec reset;
/* clock configuration */
uint32_t clk_modidx;
uint32_t clk_src;
uint32_t clk_div;
const struct device *clk_dev;
const struct pinctrl_dev_config *pincfg;
void (*irq_config_func)(const struct device *dev);
};
struct pwm_numaker_capture_data {
pwm_capture_callback_handler_t callback;
void *user_data;
/* Only support either one of PWM_CAPTURE_TYPE_PULSE, PWM_CAPTURE_TYPE_PERIOD */
bool pulse_capture;
bool single_mode;
bool is_busy;
uint32_t curr_edge_mode;
uint32_t next_edge_mode;
};
/* Driver context/data */
struct pwm_numaker_data {
uint32_t clock_freq;
uint32_t cycles_per_sec;
#ifdef CONFIG_PWM_CAPTURE
uint32_t overflows;
struct pwm_numaker_capture_data capture[NUMAKER_PWM_CHANNEL_COUNT];
#endif /* CONFIG_PWM_CAPTURE */
};
static void pwm_numaker_configure(const struct device *dev)
{
const struct pwm_numaker_config *cfg = dev->config;
EPWM_T *epwm = cfg->epwm;
/* Disable EPWM channel 0~5 before config */
EPWM_ForceStop(epwm, NUMAKER_PWM_CHANNEL_MASK);
/* Set EPWM default normal polarity as inverse disabled */
epwm->POLCTL &= ~(NUMAKER_PWM_CHANNEL_MASK << EPWM_POLCTL_PINV0_Pos);
}
/* PWM api functions */
static int pwm_numaker_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles, pwm_flags_t flags)
{
const struct pwm_numaker_config *cfg = dev->config;
struct pwm_numaker_data *data = dev->data;
EPWM_T *epwm = cfg->epwm;
uint32_t channel_mask = BIT(channel);
LOG_DBG("Channel=0x%x, CAPIEN=0x%x, CAPIF=0x%x", channel, epwm->CAPIEN,
epwm->CAPIF);
/* Set EPWM polarity */
if (flags & PWM_POLARITY_INVERTED) {
epwm->POLCTL |= BIT(EPWM_POLCTL_PINV0_Pos + channel);
} else {
epwm->POLCTL &= ~BIT(EPWM_POLCTL_PINV0_Pos + channel);
}
/* Force disable EPWM channel as while pulse_cycles = 0 */
if (period_cycles == 0U) {
EPWM_Stop(epwm, channel_mask);
EPWM_ForceStop(epwm, channel_mask);
EPWM_DisableOutput(epwm, channel_mask);
return 0;
}
/* Set EPWM channel & output configuration */
EPWM_ConfigOutputChannel(epwm, channel, data->cycles_per_sec / period_cycles,
(100U * pulse_cycles) / period_cycles);
/* Enable EPWM Output path for EPWM channel */
EPWM_EnableOutput(epwm, channel_mask);
/* Enable Timer for EPWM channel */
EPWM_Start(epwm, channel_mask);
LOG_DBG("cycles_per_sec=0x%x, pulse_cycles=0x%x, period_cycles=0x%x",
data->cycles_per_sec, pulse_cycles, period_cycles);
LOG_DBG("CTL1=0x%x, POEN=0x%x, CNTEN=0x%x", epwm->CTL1, epwm->POEN, epwm->CNTEN);
LOG_DBG("Channel=0x%x, CAPIEN=0x%x, CAPIF=0x%x", channel, epwm->CAPIEN, epwm->CAPIF);
return 0;
}
static int pwm_numaker_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
const struct pwm_numaker_config *cfg = dev->config;
struct pwm_numaker_data *data = dev->data;
ARG_UNUSED(channel);
data->cycles_per_sec = data->clock_freq / (cfg->prescale + 1U);
*cycles = (uint64_t)data->cycles_per_sec;
return 0;
}
#ifdef CONFIG_PWM_CAPTURE
static int pwm_numaker_configure_capture(const struct device *dev, uint32_t channel,
pwm_flags_t flags, pwm_capture_callback_handler_t cb,
void *user_data)
{
struct pwm_numaker_data *data = dev->data;
uint32_t pair = channel;
LOG_DBG("");
data->capture[pair].callback = cb;
data->capture[pair].user_data = user_data;
if (data->capture[pair].is_busy) {
LOG_ERR("Capture already active on this channel %d", pair);
return -EBUSY;
}
if ((flags & PWM_CAPTURE_TYPE_MASK) == PWM_CAPTURE_TYPE_BOTH) {
LOG_ERR("Cannot capture both period and pulse width");
return -ENOTSUP;
}
if ((flags & PWM_CAPTURE_MODE_MASK) == PWM_CAPTURE_MODE_CONTINUOUS) {
data->capture[pair].single_mode = false;
} else {
data->capture[pair].single_mode = true;
}
if (flags & PWM_CAPTURE_TYPE_PERIOD) {
data->capture[pair].pulse_capture = false;
if (flags & PWM_POLARITY_INVERTED) {
data->capture[pair].curr_edge_mode = EPWM_CAPTURE_INT_FALLING_LATCH;
data->capture[pair].next_edge_mode = EPWM_CAPTURE_INT_FALLING_LATCH;
} else {
data->capture[pair].curr_edge_mode = EPWM_CAPTURE_INT_RISING_LATCH;
data->capture[pair].next_edge_mode = EPWM_CAPTURE_INT_RISING_LATCH;
}
} else {
data->capture[pair].pulse_capture = true;
if (flags & PWM_POLARITY_INVERTED) {
data->capture[pair].curr_edge_mode = EPWM_CAPTURE_INT_FALLING_LATCH;
data->capture[pair].next_edge_mode = EPWM_CAPTURE_INT_RISING_LATCH;
} else {
data->capture[pair].curr_edge_mode = EPWM_CAPTURE_INT_RISING_LATCH;
data->capture[pair].next_edge_mode = EPWM_CAPTURE_INT_FALLING_LATCH;
}
}
return 0;
}
static int pwm_numaker_enable_capture(const struct device *dev, uint32_t channel)
{
const struct pwm_numaker_config *cfg = dev->config;
struct pwm_numaker_data *data = dev->data;
EPWM_T *epwm = cfg->epwm;
uint32_t pair = channel;
uint32_t channel_mask = BIT(channel);
uint32_t unit_time_nsec = (1000000000U / data->cycles_per_sec);
LOG_DBG("");
if (!data->capture[pair].callback) {
LOG_ERR("PWM capture not configured");
return -EINVAL;
}
if (data->capture[pair].is_busy) {
LOG_ERR("Capture already active on this channel %d", pair);
return -EBUSY;
}
data->capture[pair].is_busy = true;
/* Set capture configuration */
EPWM_ConfigCaptureChannel(epwm, channel, unit_time_nsec, 0);
/* Enable Capture Function for EPWM */
EPWM_EnableCapture(epwm, channel_mask);
/* Enable Timer for EPWM */
EPWM_Start(epwm, channel_mask);
EPWM_ClearCaptureIntFlag(epwm, channel,
EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH);
/* EnableInterrupt */
EPWM_EnableCaptureInt(epwm, channel, data->capture[pair].curr_edge_mode);
LOG_DBG("Channel=0x%x, CAPIEN=0x%x, CAPIF=0x%x", channel, epwm->CAPIEN,
epwm->CAPIF);
return 0;
}
static int pwm_numaker_disable_capture(const struct device *dev, uint32_t channel)
{
const struct pwm_numaker_config *cfg = dev->config;
struct pwm_numaker_data *data = dev->data;
EPWM_T *epwm = cfg->epwm;
uint32_t channel_mask = BIT(channel);
LOG_DBG("");
data->capture[channel].is_busy = false;
EPWM_Stop(epwm, channel_mask);
EPWM_ForceStop(epwm, channel_mask);
EPWM_DisableCapture(epwm, channel_mask);
EPWM_DisableCaptureInt(epwm, channel,
EPWM_CAPTURE_INT_RISING_LATCH | EPWM_CAPTURE_INT_FALLING_LATCH);
EPWM_ClearCaptureIntFlag(epwm, channel,
EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH);
LOG_DBG("CAPIEN = 0x%x\n", epwm->CAPIEN);
return 0;
}
/*
* Get capture cycles between current channel edge until next chnannel edge.
* The capture period counter down count from 0x10000, and auto-reload to 0x10000
*/
static int pwm_numaker_get_cap_cycle(EPWM_T *epwm, uint32_t channel, uint32_t curr_edge,
uint32_t next_edge, uint32_t *cycles)
{
uint16_t curr_cnt;
uint16_t next_cnt;
uint32_t next_if_mask;
uint32_t capif_base;
uint32_t time_out_cnt;
int status = 0;
uint32_t period_reloads = 0;
/* PWM counter is timing critical, to avoid print msg from irq_isr until getting cycles */
LOG_DBG("");
EPWM_ClearPeriodIntFlag(epwm, channel);
capif_base = (next_edge == EPWM_CAPTURE_INT_FALLING_LATCH) ? EPWM_CAPIF_CFLIF0_Pos
: EPWM_CAPIF_CRLIF0_Pos;
next_if_mask = BIT(capif_base + channel);
time_out_cnt = NUMAKER_SYSCLK_FREQ / 2; /* 500 ms time-out */
LOG_DBG("Channel=0x%x, R-Cnt=0x%x, F-Cnt0x%x, CNT-0x%x", channel,
EPWM_GET_CAPTURE_RISING_DATA(epwm, channel),
EPWM_GET_CAPTURE_FALLING_DATA(epwm, channel), epwm->CNT[channel]);
curr_cnt = (curr_edge == EPWM_CAPTURE_INT_FALLING_LATCH)
? EPWM_GET_CAPTURE_FALLING_DATA(epwm, channel)
: (uint16_t)EPWM_GET_CAPTURE_RISING_DATA(epwm, channel);
/* Wait for Capture Next Indicator */
while ((epwm->CAPIF & next_if_mask) == 0) {
if (EPWM_GetPeriodIntFlag(epwm, channel)) {
EPWM_ClearPeriodIntFlag(epwm, channel);
period_reloads++;
}
if (--time_out_cnt == 0) {
status = -EAGAIN;
goto done;
}
}
/* Clear Capture Falling and Rising Indicator */
EPWM_ClearCaptureIntFlag(epwm, channel,
EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH);
/* Get Capture Latch Counter Data */
next_cnt = (next_edge == EPWM_CAPTURE_INT_FALLING_LATCH)
? (uint16_t)EPWM_GET_CAPTURE_FALLING_DATA(epwm, channel)
: (uint16_t)EPWM_GET_CAPTURE_RISING_DATA(epwm, channel);
*cycles = (period_reloads * NUMAKER_PWM_RELOAD_CNT) + curr_cnt - next_cnt;
LOG_DBG("cycles=0x%x, period_reloads=0x%x, CAPIF=0x%x, cur-0x%x ,next-0x%x",
*cycles, period_reloads, epwm->CAPIF, curr_cnt, next_cnt);
done:
return status;
}
static void pwm_numaker_channel_cap(const struct device *dev, EPWM_T *epwm, uint32_t channel)
{
struct pwm_numaker_data *data = dev->data;
struct pwm_numaker_capture_data *capture;
uint32_t cycles = 0;
int status;
EPWM_DisableCaptureInt(epwm, channel, EPWM_CAPTURE_INT_RISING_LATCH |
EPWM_CAPTURE_INT_FALLING_LATCH);
capture = &data->capture[channel];
/* Calculate cycles */
status = pwm_numaker_get_cap_cycle(
epwm, channel, data->capture[channel].curr_edge_mode,
data->capture[channel].next_edge_mode, &cycles);
if (capture->pulse_capture) {
/* For PWM_CAPTURE_TYPE_PULSE */
capture->callback(dev, channel, 0, cycles, status, capture->user_data);
} else {
/* For PWM_CAPTURE_TYPE_PERIOD */
capture->callback(dev, channel, cycles, 0, status, capture->user_data);
}
if (capture->single_mode) {
EPWM_DisableCaptureInt(epwm, channel, EPWM_CAPTURE_INT_RISING_LATCH |
EPWM_CAPTURE_INT_FALLING_LATCH);
data->capture[channel].is_busy = false;
} else {
EPWM_ClearCaptureIntFlag(epwm, channel, EPWM_CAPTURE_INT_FALLING_LATCH |
EPWM_CAPTURE_INT_RISING_LATCH);
EPWM_EnableCaptureInt(epwm, channel, data->capture[channel].curr_edge_mode);
/* data->capture[channel].is_busy = true; */
}
}
static void pwm_numaker_isr(const struct device *dev, uint32_t st_channel, uint32_t end_channel)
{
const struct pwm_numaker_config *cfg = dev->config;
struct pwm_numaker_data *data = dev->data;
EPWM_T *epwm = cfg->epwm;
struct pwm_numaker_capture_data *capture;
uint32_t int_status;
uint32_t cap_intsts;
int i;
uint32_t int_mask = (BIT(st_channel) | BIT(end_channel));
uint32_t cap_int_rise_mask, cap_int_fall_mask;
uint32_t cap_int_mask =
(EPWM_CAPIF_CFLIF0_Msk << st_channel | EPWM_CAPIF_CRLIF0_Msk << st_channel |
EPWM_CAPIF_CFLIF0_Msk << end_channel | EPWM_CAPIF_CRLIF0_Msk << end_channel);
/* Get Output int status */
int_status = epwm->AINTSTS & int_mask;
/* Clear Output int status */
if (int_status != 0x00) {
epwm->AINTSTS = int_status;
}
/* Get CAP int status */
cap_intsts = epwm->CAPIF & cap_int_mask;
/* PWM counter is timing critical, to avoid print msg from irq_isr
* until getting capture cycles.
*/
LOG_DBG("Channel=0x%x, CAPIEN=0x%x, CAPIF=0x%x, capIntMask=0x%x",
st_channel, epwm->CAPIEN, epwm->CAPIF, cap_int_mask);
if (cap_intsts != 0x00) { /* Capture Interrupt */
/* Clear CAP int status */
epwm->CAPIF = cap_intsts;
/* Rising latch or Falling latch */
for (i = st_channel; i <= end_channel; i++) {
capture = &data->capture[i];
if (capture == NULL) {
continue;
}
cap_int_rise_mask = (EPWM_CAPTURE_INT_RISING_LATCH << i);
cap_int_fall_mask = (EPWM_CAPTURE_INT_FALLING_LATCH << i);
if ((cap_int_rise_mask | cap_int_fall_mask) & cap_intsts) {
pwm_numaker_channel_cap(dev, epwm, i);
}
}
}
}
static void pwm_numaker_p0_isr(const struct device *dev)
{
/* Pair0 service channel 0, 1 */
pwm_numaker_isr(dev, 0, 1);
}
static void pwm_numaker_p1_isr(const struct device *dev)
{
/* Pair1 service channel 2, 3 */
pwm_numaker_isr(dev, 2, 3);
}
static void pwm_numaker_p2_isr(const struct device *dev)
{
/* Pair2 service channel 4, 5 */
pwm_numaker_isr(dev, 4, 5);
}
#endif /* CONFIG_PWM_CAPTURE */
/* PWM driver registration */
static const struct pwm_driver_api pwm_numaker_driver_api = {
.set_cycles = pwm_numaker_set_cycles,
.get_cycles_per_sec = pwm_numaker_get_cycles_per_sec,
#ifdef CONFIG_PWM_CAPTURE
.configure_capture = pwm_numaker_configure_capture,
.enable_capture = pwm_numaker_enable_capture,
.disable_capture = pwm_numaker_disable_capture,
#endif /* CONFIG_PWM_CAPTURE */
};
/* Alternative EPWM clock get rate before support standard clock_control_get_rate */
static int pwm_numaker_clk_get_rate(EPWM_T *epwm, uint32_t *rate)
{
uint32_t clk_src;
uint32_t epwm_clk_src;
if (epwm == EPWM0) {
clk_src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
} else if (epwm == EPWM1) {
clk_src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
} else {
LOG_ERR("Invalid EPWM node");
return -EINVAL;
}
if (clk_src == 0U) {
/* clock source is from PLL clock */
epwm_clk_src = CLK_GetPLLClockFreq();
} else {
/* clock source is from PCLK */
SystemCoreClockUpdate();
if (epwm == EPWM0) {
epwm_clk_src = CLK_GetPCLK0Freq();
} else { /* (epwm == EPWM1) */
epwm_clk_src = CLK_GetPCLK1Freq();
}
}
*rate = epwm_clk_src;
return 0;
}
static int pwm_numaker_init(const struct device *dev)
{
const struct pwm_numaker_config *cfg = dev->config;
struct pwm_numaker_data *data = dev->data;
EPWM_T *epwm = cfg->epwm;
uint32_t clock_freq;
int err;
struct numaker_scc_subsys scc_subsys;
/* Validate this module's reset object */
if (!device_is_ready(cfg->reset.dev)) {
LOG_ERR("reset controller not ready");
return -ENODEV;
}
SYS_UnlockReg();
/* CLK controller */
memset(&scc_subsys, 0x00, sizeof(scc_subsys));
scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC;
scc_subsys.pcc.clk_modidx = cfg->clk_modidx;
scc_subsys.pcc.clk_src = cfg->clk_src;
scc_subsys.pcc.clk_div = cfg->clk_div;
/* Equivalent to CLK_EnableModuleClock() */
err = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&scc_subsys);
if (err != 0) {
goto done;
}
/* Equivalent to CLK_SetModuleClock() */
err = clock_control_configure(cfg->clk_dev, (clock_control_subsys_t)&scc_subsys, NULL);
if (err != 0) {
goto done;
}
/* Not support standard clock_control_get_rate yet */
/* clock_control_get_rate(cfg->clk_dev,(clock_control_subsys_t)&scc_subsys,&clock_freq); */
err = pwm_numaker_clk_get_rate(epwm, &clock_freq);
if (err < 0) {
LOG_ERR("Get EPWM clock rate failure %d", err);
goto done;
}
data->clock_freq = clock_freq;
data->cycles_per_sec = data->clock_freq / (cfg->prescale + 1U);
err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
LOG_ERR("Failed to apply pinctrl state");
goto done;
}
/* Reset PWM to default state, same as BSP's SYS_ResetModule(id_rst) */
reset_line_toggle_dt(&cfg->reset);
/* Configure PWM device initially */
pwm_numaker_configure(dev);
#ifdef CONFIG_PWM_CAPTURE
/* Enable NVIC */
cfg->irq_config_func(dev);
#endif
done:
SYS_LockReg();
return err;
}
#ifdef CONFIG_PWM_CAPTURE
#define NUMAKER_PWM_IRQ_CONFIG_FUNC(n) \
static void pwm_numaker_irq_config_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, pair0, irq), \
DT_INST_IRQ_BY_NAME(n, pair0, priority), pwm_numaker_p0_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQ_BY_NAME(n, pair0, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, pair1, irq), \
DT_INST_IRQ_BY_NAME(n, pair1, priority), pwm_numaker_p1_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQ_BY_NAME(n, pair1, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, pair2, irq), \
DT_INST_IRQ_BY_NAME(n, pair2, priority), pwm_numaker_p2_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQ_BY_NAME(n, pair2, irq)); \
}
#define IRQ_FUNC_INIT(n) .irq_config_func = pwm_numaker_irq_config_##n
#else
#define NUMAKER_PWM_IRQ_CONFIG_FUNC(n)
#define IRQ_FUNC_INIT(n)
#endif
#define NUMAKER_PWM_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
NUMAKER_PWM_IRQ_CONFIG_FUNC(inst) \
\
static const struct pwm_numaker_config pwm_numaker_cfg_##inst = { \
.epwm = (EPWM_T *)DT_INST_REG_ADDR(inst), \
.prescale = DT_INST_PROP(inst, prescaler), \
.reset = RESET_DT_SPEC_INST_GET(inst), \
.clk_modidx = DT_INST_CLOCKS_CELL(inst, clock_module_index), \
.clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
.clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
.clk_dev = DEVICE_DT_GET(DT_PARENT(DT_INST_CLOCKS_CTLR(inst))), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
IRQ_FUNC_INIT(inst)}; \
\
static struct pwm_numaker_data pwm_numaker_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, &pwm_numaker_init, NULL, &pwm_numaker_data_##inst, \
&pwm_numaker_cfg_##inst, PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &pwm_numaker_driver_api);
DT_INST_FOREACH_STATUS_OKAY(NUMAKER_PWM_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_numaker.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,177 |
```unknown
# Nordic Semiconductor nRF5x s/w PWM configuration options
config PWM_NRF_SW
bool "Nordic Semiconductor nRF family S/W PWM"
default y if !PWM_NRFX
depends on DT_HAS_NORDIC_NRF_SW_PWM_ENABLED
select NRFX_GPIOTE
select NRFX_PPI if HAS_HW_NRF_PPI
select NRFX_DPPI if HAS_HW_NRF_DPPIC
help
Enable driver to utilize PWM on the Nordic Semiconductor nRF SoCs.
When used with HF timer, it provides up to 5 pins, utilizing one
GPIOTE channel and two PPI/DPPI channels and per pin.
When used with RTC, it provides up to 3 pins, utilizing one GPIOTE
channel and two or three (when the fork feature is not available)
PPI/DPPI channels per pin.
``` | /content/code_sandbox/drivers/pwm/Kconfig.nrf_sw | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 184 |
```unknown
# ESP32 PWM LED configuration options
config PWM_LED_ESP32
bool "ESP32 PWM LED driver"
default y
depends on DT_HAS_ESPRESSIF_ESP32_LEDC_ENABLED
help
This option enables the PWM LED driver for ESP32 family of
processors.
config MCPWM_ESP32
bool "ESP32 MCPWM driver"
default y
depends on DT_HAS_ESPRESSIF_ESP32_MCPWM_ENABLED
help
This option enables the MCPWM driver for ESP32 family of
processors.
``` | /content/code_sandbox/drivers/pwm/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```unknown
# Intel Blinky PWM configuration options
config PWM_INTEL_BLINKY
bool "Blinky PWM driver"
default y
depends on DT_HAS_INTEL_BLINKY_PWM_ENABLED
help
Enable the INTEL PCH PWM driver found on Intel SoCs
``` | /content/code_sandbox/drivers/pwm/Kconfig.intel_blinky | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#define DT_DRV_COMPAT gd_gd32_pwm
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/sys/util_macro.h>
#include <gd32_timer.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_gd32, CONFIG_PWM_LOG_LEVEL);
/** PWM data. */
struct pwm_gd32_data {
/** Timer clock (Hz). */
uint32_t tim_clk;
};
/** PWM configuration. */
struct pwm_gd32_config {
/** Timer register. */
uint32_t reg;
/** Number of channels */
uint8_t channels;
/** Flag to indicate if timer has 32-bit counter */
bool is_32bit;
/** Flag to indicate if timer is advanced */
bool is_advanced;
/** Prescaler. */
uint16_t prescaler;
/** Clock id. */
uint16_t clkid;
/** Reset. */
struct reset_dt_spec reset;
/** pinctrl configurations. */
const struct pinctrl_dev_config *pcfg;
};
/** Obtain channel enable bit for the given channel */
#define TIMER_CHCTL2_CHXEN(ch) BIT(4U * (ch))
/** Obtain polarity bit for the given channel */
#define TIMER_CHCTL2_CHXP(ch) BIT(1U + (4U * (ch)))
/** Obtain CHCTL0/1 mask for the given channel (0 or 1) */
#define TIMER_CHCTLX_MSK(ch) (0xFU << (8U * (ch)))
/** Obtain RCU register offset from RCU clock value */
#define RCU_CLOCK_OFFSET(rcu_clock) ((rcu_clock) >> 6U)
static int pwm_gd32_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_gd32_config *config = dev->config;
if (channel >= config->channels) {
return -EINVAL;
}
/* 16-bit timers can count up to UINT16_MAX */
if (!config->is_32bit && (period_cycles > UINT16_MAX)) {
return -ENOTSUP;
}
/* disable channel output if period is zero */
if (period_cycles == 0U) {
TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXEN(channel);
return 0;
}
/* update polarity */
if ((flags & PWM_POLARITY_INVERTED) != 0U) {
TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXP(channel);
} else {
TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXP(channel);
}
/* update pulse */
switch (channel) {
case 0U:
TIMER_CH0CV(config->reg) = pulse_cycles;
break;
case 1U:
TIMER_CH1CV(config->reg) = pulse_cycles;
break;
case 2U:
TIMER_CH2CV(config->reg) = pulse_cycles;
break;
case 3U:
TIMER_CH3CV(config->reg) = pulse_cycles;
break;
default:
__ASSERT_NO_MSG(NULL);
break;
}
/* update period */
TIMER_CAR(config->reg) = period_cycles;
/* channel not enabled: configure it */
if ((TIMER_CHCTL2(config->reg) & TIMER_CHCTL2_CHXEN(channel)) == 0U) {
volatile uint32_t *chctl;
/* select PWM1 mode, enable OC shadowing */
if (channel < 2U) {
chctl = &TIMER_CHCTL0(config->reg);
} else {
chctl = &TIMER_CHCTL1(config->reg);
}
*chctl &= ~TIMER_CHCTLX_MSK(channel);
*chctl |= (TIMER_OC_MODE_PWM1 | TIMER_OC_SHADOW_ENABLE) <<
(8U * (channel % 2U));
/* enable channel output */
TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXEN(channel);
/* generate update event (to load shadow values) */
TIMER_SWEVG(config->reg) |= TIMER_SWEVG_UPG;
}
return 0;
}
static int pwm_gd32_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
struct pwm_gd32_data *data = dev->data;
const struct pwm_gd32_config *config = dev->config;
*cycles = (uint64_t)(data->tim_clk / (config->prescaler + 1U));
return 0;
}
static const struct pwm_driver_api pwm_gd32_driver_api = {
.set_cycles = pwm_gd32_set_cycles,
.get_cycles_per_sec = pwm_gd32_get_cycles_per_sec,
};
static int pwm_gd32_init(const struct device *dev)
{
const struct pwm_gd32_config *config = dev->config;
struct pwm_gd32_data *data = dev->data;
int ret;
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&config->clkid);
(void)reset_line_toggle_dt(&config->reset);
/* apply pin configuration */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
/* cache timer clock value */
(void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&config->clkid,
&data->tim_clk);
/* basic timer operation: edge aligned, up counting, shadowed CAR */
TIMER_CTL0(config->reg) = TIMER_CKDIV_DIV1 | TIMER_COUNTER_EDGE |
TIMER_COUNTER_UP | TIMER_CTL0_ARSE;
TIMER_PSC(config->reg) = config->prescaler;
/* enable primary output for advanced timers */
if (config->is_advanced) {
TIMER_CCHP(config->reg) |= TIMER_CCHP_POEN;
}
/* enable timer counter */
TIMER_CTL0(config->reg) |= TIMER_CTL0_CEN;
return 0;
}
#define PWM_GD32_DEFINE(i) \
static struct pwm_gd32_data pwm_gd32_data_##i; \
\
PINCTRL_DT_INST_DEFINE(i); \
\
static const struct pwm_gd32_config pwm_gd32_config_##i = { \
.reg = DT_REG_ADDR(DT_INST_PARENT(i)), \
.clkid = DT_CLOCKS_CELL(DT_INST_PARENT(i), id), \
.reset = RESET_DT_SPEC_GET(DT_INST_PARENT(i)), \
.prescaler = DT_PROP(DT_INST_PARENT(i), prescaler), \
.channels = DT_PROP(DT_INST_PARENT(i), channels), \
.is_32bit = DT_PROP(DT_INST_PARENT(i), is_32bit), \
.is_advanced = DT_PROP(DT_INST_PARENT(i), is_advanced), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i), \
}; \
\
DEVICE_DT_INST_DEFINE(i, &pwm_gd32_init, NULL, &pwm_gd32_data_##i, \
&pwm_gd32_config_##i, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&pwm_gd32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_GD32_DEFINE)
``` | /content/code_sandbox/drivers/pwm/pwm_gd32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,652 |
```c
/*
*
*/
#define DT_DRV_COMPAT sifive_pwm0
#include <zephyr/arch/cpu.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
#include <soc.h>
LOG_MODULE_REGISTER(pwm_sifive, CONFIG_PWM_LOG_LEVEL);
/* Macros */
#define PWM_REG(z_config, _offset) ((mem_addr_t) ((z_config)->base + _offset))
/* Register Offsets */
#define REG_PWMCFG 0x00
#define REG_PWMCOUNT 0x08
#define REG_PWMS 0x10
#define REG_PWMCMP0 0x20
#define REG_PWMCMP(_channel) (REG_PWMCMP0 + ((_channel) * 0x4))
/* Number of PWM Channels */
#define SF_NUMCHANNELS 4
/* pwmcfg Bit Offsets */
#define SF_PWMSTICKY 8
#define SF_PWMZEROCMP 9
#define SF_PWMDEGLITCH 10
#define SF_PWMENALWAYS 12
#define SF_PWMENONESHOT 13
#define SF_PWMCMPCENTER(_channel) (16 + (_channel))
#define SF_PWMCMPGANG(_channel) (24 + (_channel))
#define SF_PWMCMPIP(_channel) (28 + (_channel))
/* pwmcount scale factor */
#define SF_PWMSCALEMASK 0xF
#define SF_PWMSCALE(_val) (SF_PWMSCALEMASK & (_val))
#define SF_PWMCOUNT_MIN_WIDTH 15
/* Structure Declarations */
struct pwm_sifive_data {};
struct pwm_sifive_cfg {
uint32_t base;
uint32_t f_sys;
uint32_t cmpwidth;
const struct pinctrl_dev_config *pcfg;
};
/* Helper Functions */
static inline void sys_set_mask(mem_addr_t addr, uint32_t mask, uint32_t value)
{
uint32_t temp = sys_read32(addr);
temp &= ~(mask);
temp |= value;
sys_write32(temp, addr);
}
/* API Functions */
static int pwm_sifive_init(const struct device *dev)
{
const struct pwm_sifive_cfg *config = dev->config;
#ifdef CONFIG_PINCTRL
int ret;
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
#endif
/* When pwms == pwmcmp0, reset the counter */
sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMZEROCMP);
/* Enable continuous operation */
sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMENALWAYS);
/* Clear IP config bits */
sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMSTICKY);
sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMDEGLITCH);
/* Clear all channels */
for (int i = 0; i < SF_NUMCHANNELS; i++) {
/* Clear the channel comparator */
sys_write32(0, PWM_REG(config, REG_PWMCMP(i)));
/* Clear the compare center and compare gang bits */
sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMCMPCENTER(i));
sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMCMPGANG(i));
}
return 0;
}
static int pwm_sifive_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_sifive_cfg *config = dev->config;
uint32_t count_max = 0U;
uint32_t max_cmp_val = 0U;
uint32_t pwmscale = 0U;
if (flags) {
/* PWM polarity not supported (yet?) */
return -ENOTSUP;
}
if (channel >= SF_NUMCHANNELS) {
LOG_ERR("The requested PWM channel %d is invalid\n", channel);
return -EINVAL;
}
/* Channel 0 sets the period, we can't output PWM with it */
if (channel == 0U) {
LOG_ERR("PWM channel 0 cannot be configured\n");
return -ENOTSUP;
}
/* We can't support periods greater than we can store in pwmcount */
count_max = (1 << (config->cmpwidth + SF_PWMCOUNT_MIN_WIDTH)) - 1;
if (period_cycles > count_max) {
LOG_ERR("Requested period is %d but maximum is %d\n",
period_cycles, count_max);
return -EIO;
}
/* Calculate the maximum value that pwmcmpX can be set to */
max_cmp_val = ((1 << config->cmpwidth) - 1);
/*
* Find the minimum value of pwmscale that will allow us to set the
* requested period
*/
while ((period_cycles >> pwmscale) > max_cmp_val) {
pwmscale++;
}
/* Make sure that we can scale that much */
if (pwmscale > SF_PWMSCALEMASK) {
LOG_ERR("Requested period is %d but maximum is %d\n",
period_cycles, max_cmp_val << pwmscale);
return -EIO;
}
/* Set the pwmscale field */
sys_set_mask(PWM_REG(config, REG_PWMCFG),
SF_PWMSCALEMASK,
SF_PWMSCALE(pwmscale));
/* Set the period by setting pwmcmp0 */
sys_write32((period_cycles >> pwmscale), PWM_REG(config, REG_PWMCMP0));
/* Set the duty cycle by setting pwmcmpX */
sys_write32((pulse_cycles >> pwmscale),
PWM_REG(config, REG_PWMCMP(channel)));
LOG_DBG("channel: %d, pwmscale: %d, pwmcmp0: %d, pwmcmp%d: %d",
channel,
pwmscale,
(period_cycles >> pwmscale),
channel,
(pulse_cycles >> pwmscale));
return 0;
}
static int pwm_sifive_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct pwm_sifive_cfg *config;
if (dev == NULL) {
LOG_ERR("The device instance pointer was NULL\n");
return -EFAULT;
}
config = dev->config;
if (config == NULL) {
LOG_ERR("The device configuration is NULL\n");
return -EFAULT;
}
/* Fail if we don't have that channel */
if (channel >= SF_NUMCHANNELS) {
return -EINVAL;
}
*cycles = config->f_sys;
return 0;
}
/* Device Instantiation */
static const struct pwm_driver_api pwm_sifive_api = {
.set_cycles = pwm_sifive_set_cycles,
.get_cycles_per_sec = pwm_sifive_get_cycles_per_sec,
};
#define PWM_SIFIVE_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static struct pwm_sifive_data pwm_sifive_data_##n; \
static const struct pwm_sifive_cfg pwm_sifive_cfg_##n = { \
.base = DT_INST_REG_ADDR(n), \
.f_sys = SIFIVE_PERIPHERAL_CLOCK_FREQUENCY, \
.cmpwidth = DT_INST_PROP(n, sifive_compare_width), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
DEVICE_DT_INST_DEFINE(n, \
pwm_sifive_init, \
NULL, \
&pwm_sifive_data_##n, \
&pwm_sifive_cfg_##n, \
POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&pwm_sifive_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_SIFIVE_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_sifive.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,706 |
```unknown
# (c) Meta Platforms, Inc. and affiliates.
config PWM_MCUX_CTIMER
bool "MCUX CTimer PWM driver"
default y
depends on DT_HAS_NXP_CTIMER_PWM_ENABLED
help
Enable ctimer based pwm driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.mcux_ctimer | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_pca9685_pwm
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/sys/util_macro.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_pca9685, CONFIG_PWM_LOG_LEVEL);
#define OSC_CLOCK_MAX 50000000
#define CHANNEL_CNT 16
#define ADDR_MODE1 0x00
#define SLEEP BIT(4)
#define AUTO_INC BIT(5)
#define RESTART BIT(7)
#define ADDR_MODE2 0x01
#define OUTDRV_TOTEM_POLE BIT(2)
#define OCH_ON_ACK BIT(3)
#define ADDR_LED0_ON_L 0x06
#define ADDR_LED_ON_L(n) (ADDR_LED0_ON_L + (4 * n))
#define LED_FULL_ON BIT(4)
#define LED_FULL_OFF BIT(4)
#define BYTE_N(word, n) ((word >> (8 * n)) & 0xFF)
#define ADDR_PRE_SCALE 0xFE
/* See PCA9585 datasheet Rev. 4 - 16 April 2015 section 7.3.5 */
#define OSC_CLOCK_INTERNAL 25000000
#define PWM_STEPS 4096
#define PRE_SCALE_MIN 0x03
#define PRE_SCALE_MAX 0xFF
#define PRE_SCALE_DEFAULT 0x1E
#define PWM_PERIOD_COUNT_PS(pre_scale) (PWM_STEPS * (pre_scale + 1))
/*
* When using the internal oscillator this corresponds to an
* update rate of 1526 Hz
*/
#define PWM_PERIOD_COUNT_MIN PWM_PERIOD_COUNT_PS(PRE_SCALE_MIN)
/*
* When using the internal oscillator this corresponds to an
* update rate of 24 Hz
*/
#define PWM_PERIOD_COUNT_MAX PWM_PERIOD_COUNT_PS(PRE_SCALE_MAX)
/*
* When using the internal oscillator this corresponds to an
* update rate of 200 Hz
*/
#define PWM_PERIOD_COUNT_DEFAULT PWM_PERIOD_COUNT_PS(PRE_SCALE_DEFAULT)
/*
* Time allowed for the oscillator to stabilize after the PCA9685's
* RESTART mode is used to wake the chip from SLEEP.
* See PCA9685 datasheet section 7.3.1.1
*/
#define OSCILLATOR_STABILIZE K_USEC(500)
struct pca9685_config {
struct i2c_dt_spec i2c;
bool outdrv_open_drain;
bool och_on_ack;
bool invrt;
};
struct pca9685_data {
struct k_mutex mutex;
uint8_t pre_scale;
};
static int set_reg(const struct device *dev, uint8_t addr, uint8_t value)
{
const struct pca9685_config *config = dev->config;
uint8_t buf[] = {addr, value};
int ret;
ret = i2c_write_dt(&config->i2c, buf, sizeof(buf));
if (ret != 0) {
LOG_ERR("I2C write [0x%02X]=0x%02X: %d", addr, value, ret);
} else {
LOG_DBG("[0x%02X]=0x%02X", addr, value);
}
return ret;
}
static int get_reg(const struct device *dev, uint8_t addr, uint8_t *value)
{
const struct pca9685_config *config = dev->config;
int ret;
ret = i2c_write_read_dt(&config->i2c, &addr, sizeof(addr), value,
sizeof(*value));
if (ret != 0) {
LOG_ERR("I2C write [0x%02X]=0x%02X: %d", addr, *value, ret);
}
return ret;
}
static int set_pre_scale(const struct device *dev, uint8_t value)
{
struct pca9685_data *data = dev->data;
uint8_t mode1;
int ret;
uint8_t restart = RESTART;
k_mutex_lock(&data->mutex, K_FOREVER);
/* Unblock write to PRE_SCALE by setting SLEEP bit to logic 1 */
ret = set_reg(dev, ADDR_MODE1, AUTO_INC | SLEEP);
if (ret != 0) {
goto out;
}
ret = get_reg(dev, ADDR_MODE1, &mode1);
if (ret != 0) {
goto out;
}
if ((mode1 & RESTART) == 0x00) {
restart = 0;
}
ret = set_reg(dev, ADDR_PRE_SCALE, value);
if (ret != 0) {
goto out;
}
/* Clear SLEEP bit - See datasheet section 7.3.1.1 */
ret = set_reg(dev, ADDR_MODE1, AUTO_INC);
if (ret != 0) {
goto out;
}
k_sleep(OSCILLATOR_STABILIZE);
ret = set_reg(dev, ADDR_MODE1, AUTO_INC | restart);
if (ret != 0) {
goto out;
}
out:
k_mutex_unlock(&data->mutex);
return ret;
}
static int pca9685_set_cycles(const struct device *dev,
uint32_t channel, uint32_t period_count,
uint32_t pulse_count, pwm_flags_t flags)
{
const struct pca9685_config *config = dev->config;
struct pca9685_data *data = dev->data;
uint8_t buf[5] = { 0 };
uint32_t led_off_count;
int32_t pre_scale;
int ret;
ARG_UNUSED(flags);
if (channel >= CHANNEL_CNT) {
LOG_WRN("channel out of range: %u", channel);
return -EINVAL;
}
pre_scale = DIV_ROUND_UP((int64_t)period_count, PWM_STEPS) - 1;
if (pre_scale < PRE_SCALE_MIN) {
LOG_ERR("period_count %u < %u (min)", period_count,
PWM_PERIOD_COUNT_MIN);
return -ENOTSUP;
} else if (pre_scale > PRE_SCALE_MAX) {
LOG_ERR("period_count %u > %u (max)", period_count,
PWM_PERIOD_COUNT_MAX);
return -ENOTSUP;
}
/* Only one output frequency - simple conversion to equivalent PWM */
if (pre_scale != data->pre_scale) {
data->pre_scale = pre_scale;
ret = set_pre_scale(dev, pre_scale);
if (ret != 0) {
return ret;
}
}
/* Adjust PWM output for the resolution of the PCA9685 */
led_off_count = DIV_ROUND_UP(pulse_count * PWM_STEPS, period_count);
buf[0] = ADDR_LED_ON_L(channel);
if (led_off_count == 0) {
buf[4] = LED_FULL_OFF;
} else if (led_off_count < PWM_STEPS) {
/* LED turns on at count 0 */
buf[3] = BYTE_N(led_off_count, 0);
buf[4] = BYTE_N(led_off_count, 1);
} else {
buf[2] = LED_FULL_ON;
}
return i2c_write_dt(&config->i2c, buf, sizeof(buf));
}
static int pca9685_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
ARG_UNUSED(dev);
ARG_UNUSED(channel);
*cycles = OSC_CLOCK_INTERNAL;
return 0;
}
static const struct pwm_driver_api pca9685_api = {
.set_cycles = pca9685_set_cycles,
.get_cycles_per_sec = pca9685_get_cycles_per_sec,
};
static int pca9685_init(const struct device *dev)
{
const struct pca9685_config *config = dev->config;
struct pca9685_data *data = dev->data;
uint8_t value;
int ret;
(void)k_mutex_init(&data->mutex);
if (!i2c_is_ready_dt(&config->i2c)) {
LOG_ERR("I2C device not ready");
return -ENODEV;
}
ret = set_reg(dev, ADDR_MODE1, AUTO_INC);
if (ret != 0) {
LOG_ERR("set_reg MODE1: %d", ret);
return ret;
}
value = 0x00;
if (!config->outdrv_open_drain) {
value |= OUTDRV_TOTEM_POLE;
}
if (config->och_on_ack) {
value |= OCH_ON_ACK;
}
ret = set_reg(dev, ADDR_MODE2, value);
if (ret != 0) {
LOG_ERR("set_reg MODE2: %d", ret);
return ret;
}
return 0;
}
#define PCA9685_INIT(inst) \
static const struct pca9685_config pca9685_##inst##_config = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.outdrv_open_drain = DT_INST_PROP(inst, open_drain), \
.och_on_ack = DT_INST_PROP(inst, och_on_ack), \
.invrt = DT_INST_PROP(inst, invert), \
}; \
\
static struct pca9685_data pca9685_##inst##_data; \
\
DEVICE_DT_INST_DEFINE(inst, pca9685_init, NULL, \
&pca9685_##inst##_data, \
&pca9685_##inst##_config, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&pca9685_api);
DT_INST_FOREACH_STATUS_OKAY(PCA9685_INIT);
``` | /content/code_sandbox/drivers/pwm/pwm_pca9685.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,050 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_pwm
#include <errno.h>
#include <stdlib.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#ifdef CONFIG_SOC_SERIES_MEC172X
#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
#endif
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <soc.h>
LOG_MODULE_REGISTER(pwm_mchp_xec, CONFIG_PWM_LOG_LEVEL);
/* Minimal on/off are 1 & 1 both are incremented, so 4.
* 0 cannot be set (used for full low/high output) so a
* combination of on_off of 2 is not possible.
*/
#define XEC_PWM_LOWEST_ON_OFF 4U
/* Maximal on/off are UINT16_T, both are incremented.
* Multiplied by the highest divider: 16
*/
#define XEC_PWM_HIGHEST_ON_OFF (2U * (UINT16_MAX + 1U) * 16U)
#define XEC_PWM_MIN_HIGH_CLK_FREQ \
(MCHP_PWM_INPUT_FREQ_HI / XEC_PWM_HIGHEST_ON_OFF)
#define XEC_PWM_MAX_LOW_CLK_FREQ \
(MCHP_PWM_INPUT_FREQ_LO / XEC_PWM_LOWEST_ON_OFF)
/* Precision factor for frequency calculation
* To mitigate frequency comparision up to the first digit after 0.
*/
#define XEC_PWM_FREQ_PF 10U
/* Precision factor for DC calculation
* To avoid losing some digits after 0.
*/
#define XEC_PWM_DC_PF 100000U
/* Lowest reachable frequency */
#define XEC_PWM_FREQ_LIMIT 1 /* 0.1hz * XEC_PWM_FREQ_PF */
struct pwm_xec_config {
struct pwm_regs * const regs;
uint8_t pcr_idx;
uint8_t pcr_pos;
const struct pinctrl_dev_config *pcfg;
};
struct xec_params {
uint32_t on;
uint32_t off;
uint8_t div;
};
struct pwm_xec_data {
uint32_t config;
};
#define NUM_DIV_ELEMS 16
static const uint32_t max_freq_high_on_div[NUM_DIV_ELEMS] = {
48000000,
24000000,
16000000,
12000000,
9600000,
8000000,
6857142,
6000000,
5333333,
4800000,
4363636,
4000000,
3692307,
3428571,
3200000,
3000000,
};
static const uint32_t max_freq_low_on_div[NUM_DIV_ELEMS] = {
100000,
50000,
33333,
25000,
20000,
16666,
14285,
12500,
11111,
10000,
9090,
8333,
7692,
7142,
6666,
6250,
};
static uint32_t xec_compute_frequency(uint32_t clk, uint32_t on, uint32_t off)
{
return ((clk * XEC_PWM_FREQ_PF)/((on + 1) + (off + 1)));
}
static uint16_t xec_select_div(uint32_t freq, const uint32_t max_freq[16])
{
uint8_t i;
if (freq >= max_freq[3]) {
return 0;
}
freq *= XEC_PWM_LOWEST_ON_OFF;
for (i = 0; i < 15; i++) {
if (freq >= max_freq[i]) {
break;
}
}
return i;
}
static void xec_compute_on_off(uint32_t freq, uint32_t dc, uint32_t clk,
uint32_t *on, uint32_t *off)
{
uint64_t on_off;
on_off = (clk * 10) / freq;
*on = ((on_off * dc) / XEC_PWM_DC_PF) - 1;
*off = on_off - *on - 2;
}
static uint32_t xec_compute_dc(uint32_t on, uint32_t off)
{
int dc = (on + 1) + (off + 1);
/* Make calculation in uint64_t since XEC_PWM_DC_PF is large */
dc = (((uint64_t)(on + 1) * XEC_PWM_DC_PF) / dc);
return (uint32_t)dc;
}
static uint16_t xec_compare_div_on_off(uint32_t target_freq, uint32_t dc,
const uint32_t max_freq[16],
uint8_t div_a, uint8_t div_b,
uint32_t *on_a, uint32_t *off_a)
{
uint32_t freq_a, freq_b, on_b, off_b;
xec_compute_on_off(target_freq, dc, max_freq[div_a],
on_a, off_a);
freq_a = xec_compute_frequency(max_freq[div_a], *on_a, *off_a);
xec_compute_on_off(target_freq, dc, max_freq[div_b],
&on_b, &off_b);
freq_b = xec_compute_frequency(max_freq[div_b], on_b, off_b);
if ((target_freq - freq_a) < (target_freq - freq_b)) {
if ((*on_a <= UINT16_MAX) && (*off_a <= UINT16_MAX)) {
return div_a;
}
}
if ((on_b <= UINT16_MAX) && (off_b <= UINT16_MAX)) {
*on_a = on_b;
*off_a = off_b;
return div_b;
}
return div_a;
}
static uint8_t xec_select_best_div_on_off(uint32_t target_freq, uint32_t dc,
const uint32_t max_freq[16],
uint32_t *on, uint32_t *off)
{
int div_comp;
uint8_t div;
div = xec_select_div(target_freq, max_freq);
for (div_comp = (int)div - 1; div_comp >= 0; div_comp--) {
div = xec_compare_div_on_off(target_freq, dc, max_freq,
div, div_comp, on, off);
}
return div;
}
static struct xec_params *xec_compare_params(uint32_t target_freq,
struct xec_params *hc_params,
struct xec_params *lc_params)
{
struct xec_params *params;
uint32_t freq_h = 0;
uint32_t freq_l = 0;
if (hc_params->div < NUM_DIV_ELEMS) {
freq_h = xec_compute_frequency(
max_freq_high_on_div[hc_params->div],
hc_params->on,
hc_params->off);
}
if (lc_params->div < NUM_DIV_ELEMS) {
freq_l = xec_compute_frequency(
max_freq_low_on_div[lc_params->div],
lc_params->on,
lc_params->off);
}
if (abs((int)target_freq - (int)freq_h) <
abs((int)target_freq - (int)freq_l)) {
params = hc_params;
} else {
params = lc_params;
}
LOG_DBG("\tFrequency (x%u): %u", XEC_PWM_FREQ_PF, freq_h);
LOG_DBG("\tOn %s clock, ON %u OFF %u DIV %u",
params == hc_params ? "High" : "Low",
params->on, params->off, params->div);
return params;
}
static void xec_compute_and_set_parameters(const struct device *dev,
uint32_t target_freq,
uint32_t on, uint32_t off)
{
const struct pwm_xec_config * const cfg = dev->config;
struct pwm_regs * const regs = cfg->regs;
bool compute_high, compute_low;
struct xec_params hc_params;
struct xec_params lc_params;
struct xec_params *params;
uint32_t dc, cfgval;
dc = xec_compute_dc(on, off);
compute_high = (target_freq >= XEC_PWM_MIN_HIGH_CLK_FREQ);
compute_low = (target_freq <= XEC_PWM_MAX_LOW_CLK_FREQ);
LOG_DBG("Target freq (x%u): %u and DC %u per-cent",
XEC_PWM_FREQ_PF, target_freq, (dc / 1000));
if (compute_high) {
if (!compute_low
&& (on <= UINT16_MAX)
&& (off <= UINT16_MAX)) {
hc_params.on = on;
hc_params.off = off;
hc_params.div = 0;
lc_params.div = UINT8_MAX;
goto done;
}
hc_params.div = xec_select_best_div_on_off(
target_freq, dc,
max_freq_high_on_div,
&hc_params.on,
&hc_params.off);
LOG_DBG("Best div high: %u (on/off: %u/%u)",
hc_params.div, hc_params.on, hc_params.off);
} else {
hc_params.div = UINT8_MAX;
}
if (compute_low) {
lc_params.div = xec_select_best_div_on_off(
target_freq, dc,
max_freq_low_on_div,
&lc_params.on,
&lc_params.off);
LOG_DBG("Best div low: %u (on/off: %u/%u)",
lc_params.div, lc_params.on, lc_params.off);
} else {
lc_params.div = UINT8_MAX;
}
done:
regs->CONFIG &= ~MCHP_PWM_CFG_ENABLE;
cfgval = regs->CONFIG;
params = xec_compare_params(target_freq, &hc_params, &lc_params);
if (params == &hc_params) {
cfgval &= ~MCHP_PWM_CFG_CLK_SEL_100K;
} else {
cfgval |= MCHP_PWM_CFG_CLK_SEL_100K;
}
regs->COUNT_ON = params->on;
regs->COUNT_OFF = params->off;
cfgval &= ~MCHP_PWM_CFG_CLK_PRE_DIV(0xF);
cfgval |= MCHP_PWM_CFG_CLK_PRE_DIV(params->div);
cfgval |= MCHP_PWM_CFG_ENABLE;
regs->CONFIG = cfgval;
}
static int pwm_xec_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_xec_config * const cfg = dev->config;
struct pwm_regs * const regs = cfg->regs;
uint32_t target_freq;
uint32_t on, off;
if (channel > 0) {
return -EIO;
}
if (flags & PWM_POLARITY_INVERTED)
regs->CONFIG |= MCHP_PWM_CFG_ON_POL_LO;
on = pulse_cycles;
off = period_cycles - pulse_cycles;
target_freq = xec_compute_frequency(MCHP_PWM_INPUT_FREQ_HI, on, off);
if (target_freq < XEC_PWM_FREQ_LIMIT) {
LOG_DBG("Target frequency below limit");
return -EINVAL;
}
if ((pulse_cycles == 0U) && (period_cycles == 0U)) {
regs->CONFIG &= ~MCHP_PWM_CFG_ENABLE;
} else if ((pulse_cycles == 0U) && (period_cycles > 0U)) {
regs->COUNT_ON = 0;
regs->COUNT_OFF = 1;
} else if ((pulse_cycles > 0U) && (period_cycles == 0U)) {
regs->COUNT_ON = 1;
regs->COUNT_OFF = 0;
} else {
xec_compute_and_set_parameters(dev, target_freq, on, off);
}
return 0;
}
static int pwm_xec_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
ARG_UNUSED(dev);
if (channel > 0) {
return -EIO;
}
if (cycles) {
/* User does not have to know about lowest clock,
* the driver will select the most relevant one.
*/
*cycles = MCHP_PWM_INPUT_FREQ_HI;
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int pwm_xec_pm_action(const struct device *dev, enum pm_device_action action)
{
const struct pwm_xec_config *const devcfg = dev->config;
struct pwm_regs * const regs = devcfg->regs;
struct pwm_xec_data * const data = dev->data;
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC PWM pinctrl setup failed (%d)", ret);
}
/* Turn on PWM only if it is ON before sleep */
if ((data->config & MCHP_PWM_CFG_ENABLE) == MCHP_PWM_CFG_ENABLE) {
regs->CONFIG |= MCHP_PWM_CFG_ENABLE;
data->config &= (~MCHP_PWM_CFG_ENABLE);
}
break;
case PM_DEVICE_ACTION_SUSPEND:
if ((regs->CONFIG & MCHP_PWM_CFG_ENABLE) == MCHP_PWM_CFG_ENABLE) {
/* Do copy first, then clear mode. */
data->config = regs->CONFIG;
regs->CONFIG &= ~(MCHP_PWM_CFG_ENABLE);
}
ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP);
/* pinctrl-1 does not exist. */
if (ret == -ENOENT) {
ret = 0;
}
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static const struct pwm_driver_api pwm_xec_driver_api = {
.set_cycles = pwm_xec_set_cycles,
.get_cycles_per_sec = pwm_xec_get_cycles_per_sec,
};
static int pwm_xec_init(const struct device *dev)
{
const struct pwm_xec_config * const cfg = dev->config;
int ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC PWM pinctrl init failed (%d)", ret);
return ret;
}
return 0;
}
#define XEC_PWM_CONFIG(inst) \
static struct pwm_xec_config pwm_xec_config_##inst = { \
.regs = (struct pwm_regs * const)DT_INST_REG_ADDR(inst), \
.pcr_idx = (uint8_t)DT_INST_PROP_BY_IDX(inst, pcrs, 0), \
.pcr_pos = (uint8_t)DT_INST_PROP_BY_IDX(inst, pcrs, 1), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
};
#define XEC_PWM_DEVICE_INIT(index) \
\
static struct pwm_xec_data pwm_xec_data_##index; \
\
PINCTRL_DT_INST_DEFINE(index); \
\
XEC_PWM_CONFIG(index); \
\
PM_DEVICE_DT_INST_DEFINE(index, pwm_xec_pm_action); \
\
DEVICE_DT_INST_DEFINE(index, &pwm_xec_init, \
PM_DEVICE_DT_INST_GET(index), \
&pwm_xec_data_##index, \
&pwm_xec_config_##index, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&pwm_xec_driver_api);
DT_INST_FOREACH_STATUS_OKAY(XEC_PWM_DEVICE_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,410 |
```c
/*
*
*/
#define DT_DRV_COMPAT intel_blinky_pwm
#include <errno.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pwm.h>
#define PWM_ENABLE 0x80000000
#define PWM_SWUP 0x40000000
#define PWM_FREQ_INT_SHIFT 8
#define PWM_BASE_UNIT_FRACTION 14
#define PWM_FREQ_MAX 0x100
#define PWM_DUTY_MAX 0x100
struct bk_intel_config {
DEVICE_MMIO_NAMED_ROM(reg_base);
uint32_t reg_offset;
uint32_t clock_freq;
uint32_t max_pins;
};
struct bk_intel_runtime {
DEVICE_MMIO_NAMED_RAM(reg_base);
};
static int bk_intel_set_cycles(const struct device *dev, uint32_t pin,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
struct bk_intel_runtime *rt = dev->data;
const struct bk_intel_config *cfg = dev->config;
uint32_t ret = 0;
uint32_t val = 0;
uint32_t duty;
float period;
float out_freq;
uint32_t base_unit;
if (pin >= cfg->max_pins) {
ret = -EINVAL;
goto err;
}
out_freq = cfg->clock_freq / (float) period_cycles;
period = (out_freq * PWM_FREQ_MAX) / cfg->clock_freq;
base_unit = (uint32_t) (period * (1 << PWM_BASE_UNIT_FRACTION));
duty = (pulse_cycles * PWM_DUTY_MAX) / period_cycles;
if (duty) {
val = PWM_DUTY_MAX - duty;
val |= (base_unit << PWM_FREQ_INT_SHIFT);
} else {
val = PWM_DUTY_MAX - 1;
}
val |= PWM_ENABLE | PWM_SWUP;
if (period >= PWM_FREQ_MAX) {
ret = -EINVAL;
goto err;
}
if (duty > PWM_DUTY_MAX) {
ret = -EINVAL;
goto err;
}
sys_write32(val, rt->reg_base + cfg->reg_offset);
err:
return ret;
}
static int bk_intel_get_cycles_per_sec(const struct device *dev, uint32_t pin,
uint64_t *cycles)
{
const struct bk_intel_config *cfg = dev->config;
if (pin >= cfg->max_pins) {
return -EINVAL;
}
*cycles = cfg->clock_freq;
return 0;
}
static const struct pwm_driver_api api_funcs = {
.set_cycles = bk_intel_set_cycles,
.get_cycles_per_sec = bk_intel_get_cycles_per_sec,
};
static int bk_intel_init(const struct device *dev)
{
struct bk_intel_runtime *runtime = dev->data;
const struct bk_intel_config *config = dev->config;
device_map(&runtime->reg_base,
config->reg_base.phys_addr & ~0xFFU,
config->reg_base.size,
K_MEM_CACHE_NONE);
return 0;
}
#define BK_INTEL_DEV_CFG(n) \
static const struct bk_intel_config bk_cfg_##n = { \
DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
.reg_offset = DT_INST_PROP(n, reg_offset), \
.max_pins = DT_INST_PROP(n, max_pins), \
.clock_freq = DT_INST_PROP(n, clock_frequency), \
}; \
\
static struct bk_intel_runtime bk_rt_##n; \
DEVICE_DT_INST_DEFINE(n, &bk_intel_init, NULL, \
&bk_rt_##n, &bk_cfg_##n, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&api_funcs); \
DT_INST_FOREACH_STATUS_OKAY(BK_INTEL_DEV_CFG)
``` | /content/code_sandbox/drivers/pwm/pwm_intel_blinky.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 862 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_pwm
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_sam, CONFIG_PWM_LOG_LEVEL);
/* Some SoCs use a slightly different naming scheme */
#if !defined(PWMCHNUM_NUMBER) && defined(PWMCH_NUM_NUMBER)
#define PWMCHNUM_NUMBER PWMCH_NUM_NUMBER
#endif
struct sam_pwm_config {
Pwm *regs;
const struct atmel_sam_pmc_config clock_cfg;
const struct pinctrl_dev_config *pcfg;
uint8_t prescaler;
uint8_t divider;
};
static int sam_pwm_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct sam_pwm_config *config = dev->config;
uint8_t prescaler = config->prescaler;
uint8_t divider = config->divider;
*cycles = SOC_ATMEL_SAM_MCK_FREQ_HZ /
((1 << prescaler) * divider);
return 0;
}
static int sam_pwm_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct sam_pwm_config *config = dev->config;
Pwm * const pwm = config->regs;
uint32_t cmr;
if (channel >= PWMCHNUM_NUMBER) {
return -EINVAL;
}
if (period_cycles == 0U) {
return -ENOTSUP;
}
if (period_cycles > 0xffff) {
return -ENOTSUP;
}
/* Select clock A */
cmr = PWM_CMR_CPRE_CLKA;
if ((flags & PWM_POLARITY_MASK) == PWM_POLARITY_NORMAL) {
cmr |= PWM_CMR_CPOL;
}
/* Disable the output if changing polarity (or clock) */
if (pwm->PWM_CH_NUM[channel].PWM_CMR != cmr) {
pwm->PWM_DIS = 1 << channel;
pwm->PWM_CH_NUM[channel].PWM_CMR = cmr;
pwm->PWM_CH_NUM[channel].PWM_CPRD = period_cycles;
pwm->PWM_CH_NUM[channel].PWM_CDTY = pulse_cycles;
} else {
/* Update period and pulse using the update registers, so that the
* change is triggered at the next PWM period.
*/
pwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period_cycles;
pwm->PWM_CH_NUM[channel].PWM_CDTYUPD = pulse_cycles;
}
/* Enable the output */
pwm->PWM_ENA = 1 << channel;
return 0;
}
static int sam_pwm_init(const struct device *dev)
{
const struct sam_pwm_config *config = dev->config;
Pwm * const pwm = config->regs;
uint8_t prescaler = config->prescaler;
uint8_t divider = config->divider;
int retval;
/* FIXME: way to validate prescaler & divider */
/* Enable PWM clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t)&config->clock_cfg);
retval = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (retval < 0) {
return retval;
}
/* Configure the clock A that will be used by all 4 channels */
pwm->PWM_CLK = PWM_CLK_PREA(prescaler) | PWM_CLK_DIVA(divider);
return 0;
}
static const struct pwm_driver_api sam_pwm_driver_api = {
.set_cycles = sam_pwm_set_cycles,
.get_cycles_per_sec = sam_pwm_get_cycles_per_sec,
};
#define SAM_INST_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
static const struct sam_pwm_config sam_pwm_config_##inst = { \
.regs = (Pwm *)DT_INST_REG_ADDR(inst), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(inst), \
.prescaler = DT_INST_PROP(inst, prescaler), \
.divider = DT_INST_PROP(inst, divider), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, \
&sam_pwm_init, NULL, \
NULL, &sam_pwm_config_##inst, \
POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&sam_pwm_driver_api);
DT_INST_FOREACH_STATUS_OKAY(SAM_INST_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_sam.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,029 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_kinetis_pwt
#include <zephyr/drivers/clock_control.h>
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <fsl_pwt.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_pwt, CONFIG_PWM_LOG_LEVEL);
/* Number of PWT input ports */
#define PWT_INPUTS 4U
struct mcux_pwt_config {
PWT_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
pwt_clock_source_t pwt_clock_source;
pwt_clock_prescale_t prescale;
void (*irq_config_func)(const struct device *dev);
const struct pinctrl_dev_config *pincfg;
};
struct mcux_pwt_data {
uint32_t clock_freq;
uint32_t period_cycles;
uint32_t high_overflows;
uint32_t low_overflows;
pwm_capture_callback_handler_t callback;
void *user_data;
pwt_config_t pwt_config;
bool continuous : 1;
bool inverted : 1;
bool overflowed : 1;
};
static inline bool mcux_pwt_is_active(const struct device *dev)
{
const struct mcux_pwt_config *config = dev->config;
return !!(config->base->CS & PWT_CS_PWTEN_MASK);
}
static int mcux_pwt_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
ARG_UNUSED(dev);
ARG_UNUSED(channel);
ARG_UNUSED(period_cycles);
ARG_UNUSED(pulse_cycles);
ARG_UNUSED(flags);
LOG_ERR("pwt only supports pwm capture");
return -ENOTSUP;
}
static int mcux_pwt_configure_capture(const struct device *dev,
uint32_t channel, pwm_flags_t flags,
pwm_capture_callback_handler_t cb,
void *user_data)
{
const struct mcux_pwt_config *config = dev->config;
struct mcux_pwt_data *data = dev->data;
if (channel >= PWT_INPUTS) {
LOG_ERR("invalid channel %d", channel);
return -EINVAL;
}
if (mcux_pwt_is_active(dev)) {
LOG_ERR("pwm capture in progress");
return -EBUSY;
}
#if defined(CONFIG_SOC_SERIES_KE1XZ)
if ((flags & PWM_CAPTURE_TYPE_MASK) == PWM_CAPTURE_TYPE_BOTH) {
LOG_ERR("Cannot capture both period and pulse width");
return -ENOTSUP;
}
if (((flags & PWM_CAPTURE_TYPE_MASK) == PWM_CAPTURE_TYPE_PERIOD) &&
((flags & PWM_POLARITY_MASK) == PWM_POLARITY_NORMAL)) {
LOG_ERR("Cannot capture period in normal polarity (active-high pulse)");
return -ENOTSUP;
}
#endif
data->callback = cb;
data->user_data = user_data;
data->pwt_config.inputSelect = channel;
data->continuous =
(flags & PWM_CAPTURE_MODE_MASK) == PWM_CAPTURE_MODE_CONTINUOUS;
data->inverted =
(flags & PWM_POLARITY_MASK) == PWM_POLARITY_INVERTED;
PWT_Init(config->base, &data->pwt_config);
PWT_EnableInterrupts(config->base,
kPWT_PulseWidthReadyInterruptEnable |
kPWT_CounterOverflowInterruptEnable);
return 0;
}
static int mcux_pwt_enable_capture(const struct device *dev, uint32_t channel)
{
const struct mcux_pwt_config *config = dev->config;
struct mcux_pwt_data *data = dev->data;
if (channel >= PWT_INPUTS) {
LOG_ERR("invalid channel %d", channel);
return -EINVAL;
}
if (!data->callback) {
LOG_ERR("PWM capture not configured");
return -EINVAL;
}
if (mcux_pwt_is_active(dev)) {
LOG_ERR("PWM capture already enabled");
return -EBUSY;
}
data->overflowed = false;
data->high_overflows = 0;
data->low_overflows = 0;
PWT_StartTimer(config->base);
return 0;
}
static int mcux_pwt_disable_capture(const struct device *dev, uint32_t channel)
{
const struct mcux_pwt_config *config = dev->config;
if (channel >= PWT_INPUTS) {
LOG_ERR("invalid channel %d", channel);
return -EINVAL;
}
PWT_StopTimer(config->base);
return 0;
}
static int mcux_pwt_calc_period(uint16_t ppw, uint16_t npw,
uint32_t high_overflows,
uint32_t low_overflows,
uint32_t *result)
{
uint32_t period;
/* Calculate sum of overflow counters */
if (u32_add_overflow(high_overflows, low_overflows, &period)) {
return -ERANGE;
}
/* Calculate cycles from sum of overflow counters */
if (u32_mul_overflow(period, 0xFFFFU, &period)) {
return -ERANGE;
}
/* Add positive pulse width */
if (u32_add_overflow(period, ppw, &period)) {
return -ERANGE;
}
/* Add negative pulse width */
if (u32_add_overflow(period, npw, &period)) {
return -ERANGE;
}
*result = period;
return 0;
}
static int mcux_pwt_calc_pulse(uint16_t pw, uint32_t overflows,
uint32_t *result)
{
uint32_t pulse;
/* Calculate cycles from overflow counter */
if (u32_mul_overflow(overflows, 0xFFFFU, &pulse)) {
return -ERANGE;
}
/* Add pulse width */
if (u32_add_overflow(pulse, pw, &pulse)) {
return -ERANGE;
}
*result = pulse;
return 0;
}
static void mcux_pwt_isr(const struct device *dev)
{
const struct mcux_pwt_config *config = dev->config;
struct mcux_pwt_data *data = dev->data;
uint32_t period = 0;
uint32_t pulse = 0;
uint32_t flags;
uint16_t ppw;
uint16_t npw;
int err;
flags = PWT_GetStatusFlags(config->base);
if (flags & kPWT_CounterOverflowFlag) {
if (config->base->CR & PWT_CR_LVL_MASK) {
data->overflowed |= u32_add_overflow(1,
data->high_overflows, &data->high_overflows);
} else {
data->overflowed |= u32_add_overflow(1,
data->low_overflows, &data->low_overflows);
}
PWT_ClearStatusFlags(config->base, kPWT_CounterOverflowFlag);
}
if (flags & kPWT_PulseWidthValidFlag) {
ppw = PWT_ReadPositivePulseWidth(config->base);
npw = PWT_ReadNegativePulseWidth(config->base);
if (!data->continuous) {
PWT_StopTimer(config->base);
}
if (data->inverted) {
err = mcux_pwt_calc_pulse(npw, data->low_overflows,
&pulse);
} else {
err = mcux_pwt_calc_pulse(ppw, data->high_overflows,
&pulse);
}
if (err == 0) {
err = mcux_pwt_calc_period(ppw, npw,
data->high_overflows,
data->low_overflows,
&period);
}
if (data->overflowed) {
err = -ERANGE;
}
LOG_DBG("period = %d, pulse = %d, err = %d", period, pulse,
err);
if (data->callback) {
data->callback(dev, data->pwt_config.inputSelect,
period, pulse, err, data->user_data);
}
data->overflowed = false;
data->high_overflows = 0;
data->low_overflows = 0;
PWT_ClearStatusFlags(config->base, kPWT_PulseWidthValidFlag);
}
}
static int mcux_pwt_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct mcux_pwt_config *config = dev->config;
struct mcux_pwt_data *data = dev->data;
ARG_UNUSED(channel);
*cycles = data->clock_freq >> config->prescale;
return 0;
}
static int mcux_pwt_init(const struct device *dev)
{
const struct mcux_pwt_config *config = dev->config;
struct mcux_pwt_data *data = dev->data;
pwt_config_t *pwt_config = &data->pwt_config;
int err;
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&data->clock_freq)) {
LOG_ERR("could not get clock frequency");
return -EINVAL;
}
PWT_GetDefaultConfig(pwt_config);
pwt_config->clockSource = config->pwt_clock_source;
pwt_config->prescale = config->prescale;
pwt_config->enableFirstCounterLoad = true;
PWT_Init(config->base, pwt_config);
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
config->irq_config_func(dev);
return 0;
}
static const struct pwm_driver_api mcux_pwt_driver_api = {
.set_cycles = mcux_pwt_set_cycles,
.get_cycles_per_sec = mcux_pwt_get_cycles_per_sec,
.configure_capture = mcux_pwt_configure_capture,
.enable_capture = mcux_pwt_enable_capture,
.disable_capture = mcux_pwt_disable_capture,
};
#define TO_PWT_PRESCALE_DIVIDE(val) _DO_CONCAT(kPWT_Prescale_Divide_, val)
#define PWT_DEVICE(n) \
static void mcux_pwt_config_func_##n(const struct device *dev); \
\
PINCTRL_DT_INST_DEFINE(n); \
\
static const struct mcux_pwt_config mcux_pwt_config_##n = { \
.base = (PWT_Type *)DT_INST_REG_ADDR(n), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = \
(clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
.pwt_clock_source = kPWT_BusClock, \
.prescale = \
TO_PWT_PRESCALE_DIVIDE(DT_INST_PROP(n, prescaler)), \
.irq_config_func = mcux_pwt_config_func_##n, \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
\
static struct mcux_pwt_data mcux_pwt_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, &mcux_pwt_init, \
NULL, &mcux_pwt_data_##n, \
&mcux_pwt_config_##n, \
POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&mcux_pwt_driver_api); \
\
static void mcux_pwt_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
mcux_pwt_isr, DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(PWT_DEVICE)
``` | /content/code_sandbox/drivers/pwm/pwm_mcux_pwt.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,606 |
```unknown
# NUMAKER PWM Driver configuration options
config PWM_NUMAKER
bool "Nuvoton NuMaker MCU PWM driver"
default y
select HAS_NUMAKER_PWM
depends on DT_HAS_NUVOTON_NUMAKER_PWM_ENABLED
help
This option enables the PWM driver for Nuvoton NuMaker family of
processors.
Say y if you wish to enable NuMaker PWM.
``` | /content/code_sandbox/drivers/pwm/Kconfig.numaker | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
# SiFive Freedom PWM configuration options
config PWM_SIFIVE
bool "SiFive Freedom PWM driver"
default y
depends on DT_HAS_SIFIVE_PWM0_ENABLED
help
Enable the PWM driver for the SiFive Freedom platform
``` | /content/code_sandbox/drivers/pwm/Kconfig.sifive | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
# Reneas R-Car PWM configuration options
config PWM_RCAR
bool "Renesas R-Car PWM Driver"
default y
depends on SOC_FAMILY_RENESAS_RCAR
depends on DT_HAS_RENESAS_PWM_RCAR_ENABLED
help
Enable Renesas R-Car PWM Driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.rcar | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```c
/*
*
*/
#define DT_DRV_COMPAT nordic_nrf_sw_pwm
#include <soc.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <nrfx_gpiote.h>
#include <helpers/nrfx_gppi.h>
#include <hal/nrf_gpio.h>
#include <hal/nrf_rtc.h>
#include <hal/nrf_timer.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_nrf_sw, CONFIG_PWM_LOG_LEVEL);
#define GENERATOR_NODE DT_INST_PHANDLE(0, generator)
#define GENERATOR_CC_NUM DT_PROP(GENERATOR_NODE, cc_num)
#if DT_NODE_HAS_COMPAT(GENERATOR_NODE, nordic_nrf_rtc)
#define USE_RTC 1
#define GENERATOR_ADDR ((NRF_RTC_Type *) DT_REG_ADDR(GENERATOR_NODE))
#define GENERATOR_BITS 24
BUILD_ASSERT(DT_INST_PROP(0, clock_prescaler) == 0,
"Only clock-prescaler = <0> is supported when used with RTC");
#else
#define USE_RTC 0
#define GENERATOR_ADDR ((NRF_TIMER_Type *) DT_REG_ADDR(GENERATOR_NODE))
#define GENERATOR_BITS DT_PROP(GENERATOR_NODE, max_bit_width)
#endif
#define PWM_0_MAP_SIZE DT_INST_PROP_LEN(0, channel_gpios)
/* One compare channel is needed to set the PWM period, hence +1. */
#if ((PWM_0_MAP_SIZE + 1) > GENERATOR_CC_NUM)
#error "Invalid number of PWM channels configured."
#endif
#if defined(PPI_FEATURE_FORKS_PRESENT) || defined(DPPI_PRESENT)
#define PPI_FORK_AVAILABLE 1
#else
#define PPI_FORK_AVAILABLE 0
#endif
/* When RTC is used, one more PPI task endpoint is required for clearing
* the counter, so when FORK feature is not available, one more PPI channel
* needs to be used.
*/
#if USE_RTC && !PPI_FORK_AVAILABLE
#define PPI_PER_CH 3
#else
#define PPI_PER_CH 2
#endif
struct pwm_config {
union {
NRF_RTC_Type *rtc;
NRF_TIMER_Type *timer;
};
nrfx_gpiote_t gpiote[PWM_0_MAP_SIZE];
uint8_t psel_ch[PWM_0_MAP_SIZE];
uint8_t initially_inverted;
uint8_t map_size;
uint8_t prescaler;
};
struct pwm_data {
uint32_t period_cycles;
uint32_t pulse_cycles[PWM_0_MAP_SIZE];
uint8_t ppi_ch[PWM_0_MAP_SIZE][PPI_PER_CH];
uint8_t gpiote_ch[PWM_0_MAP_SIZE];
};
static inline NRF_RTC_Type *pwm_config_rtc(const struct pwm_config *config)
{
#if USE_RTC
return config->rtc;
#else
return NULL;
#endif
}
static inline NRF_TIMER_Type *pwm_config_timer(const struct pwm_config *config)
{
#if !USE_RTC
return config->timer;
#else
return NULL;
#endif
}
static uint32_t pwm_period_check(struct pwm_data *data, uint8_t map_size,
uint32_t channel, uint32_t period_cycles,
uint32_t pulse_cycles)
{
uint8_t i;
/* allow 0% and 100% duty cycle, as it does not use PWM. */
if ((pulse_cycles == 0U) || (pulse_cycles == period_cycles)) {
return 0;
}
/* fail if requested period does not match already running period */
for (i = 0U; i < map_size; i++) {
if ((i != channel) &&
(data->pulse_cycles[i] != 0U) &&
(period_cycles != data->period_cycles)) {
return -EINVAL;
}
}
return 0;
}
static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_config *config = dev->config;
NRF_TIMER_Type *timer = pwm_config_timer(config);
NRF_RTC_Type *rtc = pwm_config_rtc(config);
NRF_GPIOTE_Type *gpiote;
struct pwm_data *data = dev->data;
uint32_t ppi_mask;
uint8_t active_level;
uint8_t psel_ch;
uint8_t gpiote_ch;
const uint8_t *ppi_chs;
int ret;
if (channel >= config->map_size) {
LOG_ERR("Invalid channel: %u.", channel);
return -EINVAL;
}
/* check if requested period is allowed while other channels are
* active.
*/
ret = pwm_period_check(data, config->map_size, channel, period_cycles,
pulse_cycles);
if (ret) {
LOG_ERR("Incompatible period");
return ret;
}
if (USE_RTC) {
/* pulse_cycles - 1 is written to 24-bit CC */
if (period_cycles > BIT_MASK(24) + 1) {
LOG_ERR("Too long period (%u)!", period_cycles);
return -EINVAL;
}
} else {
if (GENERATOR_BITS < 32 &&
period_cycles > BIT_MASK(GENERATOR_BITS)) {
LOG_ERR("Too long period (%u), adjust PWM prescaler!",
period_cycles);
return -EINVAL;
}
}
gpiote = config->gpiote[channel].p_reg;
psel_ch = config->psel_ch[channel];
gpiote_ch = data->gpiote_ch[channel];
ppi_chs = data->ppi_ch[channel];
LOG_DBG("channel %u, period %u, pulse %u",
channel, period_cycles, pulse_cycles);
/* clear PPI used */
ppi_mask = BIT(ppi_chs[0]) | BIT(ppi_chs[1]) |
(PPI_PER_CH > 2 ? BIT(ppi_chs[2]) : 0);
nrfx_gppi_channels_disable(ppi_mask);
active_level = (flags & PWM_POLARITY_INVERTED) ? 0 : 1;
/*
* If the duty cycle is 0% or 100%, there is no need to generate
* the PWM signal, just keep the output pin in inactive or active
* state, respectively.
*/
if (pulse_cycles == 0 || pulse_cycles == period_cycles) {
nrf_gpio_pin_write(psel_ch,
pulse_cycles == 0 ? !active_level
: active_level);
/* clear GPIOTE config */
nrf_gpiote_te_default(gpiote, gpiote_ch);
/* No PWM generation for this channel. */
data->pulse_cycles[channel] = 0U;
/* Check if PWM signal is generated on any channel. */
for (uint8_t i = 0; i < config->map_size; i++) {
if (data->pulse_cycles[i]) {
return 0;
}
}
/* No PWM generation needed, stop the timer. */
if (USE_RTC) {
nrf_rtc_task_trigger(rtc, NRF_RTC_TASK_STOP);
} else {
nrf_timer_task_trigger(timer, NRF_TIMER_TASK_STOP);
}
return 0;
}
/* configure RTC / TIMER */
if (USE_RTC) {
nrf_rtc_event_clear(rtc,
nrf_rtc_compare_event_get(1 + channel));
nrf_rtc_event_clear(rtc,
nrf_rtc_compare_event_get(0));
/*
* '- 1' adjusts pulse and period cycles to the fact that CLEAR
* task event is generated always one LFCLK cycle after period
* COMPARE value is reached.
*/
nrf_rtc_cc_set(rtc, 1 + channel, pulse_cycles - 1);
nrf_rtc_cc_set(rtc, 0, period_cycles - 1);
nrf_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR);
} else {
nrf_timer_event_clear(timer,
nrf_timer_compare_event_get(1 + channel));
nrf_timer_event_clear(timer,
nrf_timer_compare_event_get(0));
nrf_timer_cc_set(timer, 1 + channel, pulse_cycles);
nrf_timer_cc_set(timer, 0, period_cycles);
nrf_timer_task_trigger(timer, NRF_TIMER_TASK_CLEAR);
}
/* Configure GPIOTE - toggle task with proper initial output value. */
gpiote->CONFIG[gpiote_ch] =
(GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
((uint32_t)psel_ch << 8) |
(GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos) |
((uint32_t)active_level << GPIOTE_CONFIG_OUTINIT_Pos);
/* setup PPI */
uint32_t pulse_end_event_address, period_end_event_address;
nrf_gpiote_task_t pulse_end_task, period_end_task;
#if defined(GPIOTE_FEATURE_SET_PRESENT) && defined(GPIOTE_FEATURE_CLR_PRESENT)
if (active_level == 0) {
pulse_end_task = nrf_gpiote_set_task_get(gpiote_ch);
period_end_task = nrf_gpiote_clr_task_get(gpiote_ch);
} else {
pulse_end_task = nrf_gpiote_clr_task_get(gpiote_ch);
period_end_task = nrf_gpiote_set_task_get(gpiote_ch);
}
#else
pulse_end_task = period_end_task = nrf_gpiote_out_task_get(gpiote_ch);
#endif
uint32_t pulse_end_task_address =
nrf_gpiote_task_address_get(gpiote, pulse_end_task);
uint32_t period_end_task_address =
nrf_gpiote_task_address_get(gpiote, period_end_task);
if (USE_RTC) {
uint32_t clear_task_address =
nrf_rtc_event_address_get(rtc, NRF_RTC_TASK_CLEAR);
pulse_end_event_address =
nrf_rtc_event_address_get(rtc,
nrf_rtc_compare_event_get(1 + channel));
period_end_event_address =
nrf_rtc_event_address_get(rtc,
nrf_rtc_compare_event_get(0));
#if PPI_FORK_AVAILABLE
nrfx_gppi_fork_endpoint_setup(ppi_chs[1],
clear_task_address);
#else
nrfx_gppi_channel_endpoints_setup(ppi_chs[2],
period_end_event_address,
clear_task_address);
#endif
} else {
pulse_end_event_address =
nrf_timer_event_address_get(timer,
nrf_timer_compare_event_get(1 + channel));
period_end_event_address =
nrf_timer_event_address_get(timer,
nrf_timer_compare_event_get(0));
}
nrfx_gppi_channel_endpoints_setup(ppi_chs[0],
pulse_end_event_address,
pulse_end_task_address);
nrfx_gppi_channel_endpoints_setup(ppi_chs[1],
period_end_event_address,
period_end_task_address);
nrfx_gppi_channels_enable(ppi_mask);
/* start timer, hence PWM */
if (USE_RTC) {
nrf_rtc_task_trigger(rtc, NRF_RTC_TASK_START);
} else {
nrf_timer_task_trigger(timer, NRF_TIMER_TASK_START);
}
/* store the period and pulse cycles */
data->period_cycles = period_cycles;
data->pulse_cycles[channel] = pulse_cycles;
return 0;
}
static int pwm_nrf_sw_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct pwm_config *config = dev->config;
if (USE_RTC) {
/*
* RTC frequency is derived from 32768Hz source without any
* prescaler
*/
*cycles = 32768UL;
} else {
/*
* HF timer frequency is derived from 16MHz source with a
* prescaler
*/
*cycles = 16000000UL / BIT(config->prescaler);
}
return 0;
}
static const struct pwm_driver_api pwm_nrf_sw_drv_api_funcs = {
.set_cycles = pwm_nrf_sw_set_cycles,
.get_cycles_per_sec = pwm_nrf_sw_get_cycles_per_sec,
};
static int pwm_nrf_sw_init(const struct device *dev)
{
const struct pwm_config *config = dev->config;
struct pwm_data *data = dev->data;
NRF_TIMER_Type *timer = pwm_config_timer(config);
NRF_RTC_Type *rtc = pwm_config_rtc(config);
for (uint32_t i = 0; i < config->map_size; i++) {
nrfx_err_t err;
/* Allocate resources. */
for (uint32_t j = 0; j < PPI_PER_CH; j++) {
err = nrfx_gppi_channel_alloc(&data->ppi_ch[i][j]);
if (err != NRFX_SUCCESS) {
/* Do not free allocated resource. It is a fatal condition,
* system requires reconfiguration.
*/
LOG_ERR("Failed to allocate PPI channel");
return -ENOMEM;
}
}
err = nrfx_gpiote_channel_alloc(&config->gpiote[i],
&data->gpiote_ch[i]);
if (err != NRFX_SUCCESS) {
/* Do not free allocated resource. It is a fatal condition,
* system requires reconfiguration.
*/
LOG_ERR("Failed to allocate GPIOTE channel");
return -ENOMEM;
}
/* Set initial state of the output pins. */
nrf_gpio_pin_write(config->psel_ch[i],
(config->initially_inverted & BIT(i)) ? 1 : 0);
nrf_gpio_cfg_output(config->psel_ch[i]);
}
if (USE_RTC) {
/* setup RTC */
nrf_rtc_prescaler_set(rtc, 0);
nrf_rtc_event_enable(rtc, NRF_RTC_INT_COMPARE0_MASK |
NRF_RTC_INT_COMPARE1_MASK |
NRF_RTC_INT_COMPARE2_MASK |
NRF_RTC_INT_COMPARE3_MASK);
} else {
/* setup HF timer */
nrf_timer_mode_set(timer, NRF_TIMER_MODE_TIMER);
nrf_timer_prescaler_set(timer, config->prescaler);
nrf_timer_bit_width_set(timer,
GENERATOR_BITS == 32 ? NRF_TIMER_BIT_WIDTH_32
: NRF_TIMER_BIT_WIDTH_16);
nrf_timer_shorts_enable(timer,
NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK);
}
return 0;
}
#define PSEL_AND_COMMA(_node_id, _prop, _idx) \
NRF_DT_GPIOS_TO_PSEL_BY_IDX(_node_id, _prop, _idx),
#define ACTIVE_LOW_BITS(_node_id, _prop, _idx) \
((DT_GPIO_FLAGS_BY_IDX(_node_id, _prop, _idx) & GPIO_ACTIVE_LOW) \
? BIT(_idx) : 0) |
#define GPIOTE_AND_COMMA(_node_id, _prop, _idx) \
NRFX_GPIOTE_INSTANCE(NRF_DT_GPIOTE_INST_BY_IDX(_node_id, _prop, _idx)),
static const struct pwm_config pwm_nrf_sw_0_config = {
COND_CODE_1(USE_RTC, (.rtc), (.timer)) = GENERATOR_ADDR,
.gpiote = {
DT_INST_FOREACH_PROP_ELEM(0, channel_gpios, GPIOTE_AND_COMMA)
},
.psel_ch = {
DT_INST_FOREACH_PROP_ELEM(0, channel_gpios, PSEL_AND_COMMA)
},
.initially_inverted =
DT_INST_FOREACH_PROP_ELEM(0, channel_gpios, ACTIVE_LOW_BITS) 0,
.map_size = PWM_0_MAP_SIZE,
.prescaler = DT_INST_PROP(0, clock_prescaler),
};
static struct pwm_data pwm_nrf_sw_0_data;
DEVICE_DT_INST_DEFINE(0,
pwm_nrf_sw_init,
NULL,
&pwm_nrf_sw_0_data,
&pwm_nrf_sw_0_config,
POST_KERNEL,
CONFIG_PWM_INIT_PRIORITY,
&pwm_nrf_sw_drv_api_funcs);
``` | /content/code_sandbox/drivers/pwm/pwm_nrf_sw.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,515 |
```c
/*
*
*/
#define DT_DRV_COMPAT litex_pwm
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/types.h>
#include <soc.h>
#define REG_EN_ENABLE 0x1
#define REG_EN_DISABLE 0x0
/* PWM device in LiteX has only one channel */
#define NUMBER_OF_CHANNELS 1
struct pwm_litex_cfg {
uint32_t reg_en;
uint32_t reg_width;
uint32_t reg_period;
};
int pwm_litex_init(const struct device *dev)
{
const struct pwm_litex_cfg *cfg = dev->config;
litex_write8(REG_EN_ENABLE, cfg->reg_en);
return 0;
}
int pwm_litex_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles,
uint32_t pulse_cycles, pwm_flags_t flags)
{
const struct pwm_litex_cfg *cfg = dev->config;
if (channel >= NUMBER_OF_CHANNELS) {
return -EINVAL;
}
litex_write8(REG_EN_DISABLE, cfg->reg_en);
litex_write32(pulse_cycles, cfg->reg_width);
litex_write32(period_cycles, cfg->reg_period);
litex_write8(REG_EN_ENABLE, cfg->reg_en);
return 0;
}
int pwm_litex_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
if (channel >= NUMBER_OF_CHANNELS) {
return -EINVAL;
}
*cycles = sys_clock_hw_cycles_per_sec();
return 0;
}
static const struct pwm_driver_api pwm_litex_driver_api = {
.set_cycles = pwm_litex_set_cycles,
.get_cycles_per_sec = pwm_litex_get_cycles_per_sec,
};
/* Device Instantiation */
#define PWM_LITEX_INIT(n) \
static const struct pwm_litex_cfg pwm_litex_cfg_##n = { \
.reg_en = DT_INST_REG_ADDR_BY_NAME(n, enable), \
.reg_width = DT_INST_REG_ADDR_BY_NAME(n, width), \
.reg_period = DT_INST_REG_ADDR_BY_NAME(n, period), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
pwm_litex_init, \
NULL, \
NULL, \
&pwm_litex_cfg_##n, \
POST_KERNEL, \
CONFIG_PWM_LITEX_INIT_PRIORITY, \
&pwm_litex_driver_api \
);
DT_INST_FOREACH_STATUS_OKAY(PWM_LITEX_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_litex.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 547 |
```unknown
# IT8XXX2 PWM configuration options
config PWM_ITE_IT8XXX2
bool "ITE IT8XXX2 embedded controller (EC) PWM driver"
default y
depends on DT_HAS_ITE_IT8XXX2_PWM_ENABLED
help
Enable PWM driver for it8xxx2_evb.
Supports three 16-bit prescalers each with 8-bit cycle timer, and
eight PWM channels each with 8-bit duty cycle.
``` | /content/code_sandbox/drivers/pwm/Kconfig.it8xxx2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```c
/*
*
*/
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <device_imx.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_imx, CONFIG_PWM_LOG_LEVEL);
#define PWM_PWMSR_FIFOAV_4WORDS 0x4
#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) \
<<PWM_PWMCR_SWR_SHIFT))&PWM_PWMCR_SWR_MASK)
struct imx_pwm_config {
PWM_Type *base;
uint16_t prescaler;
const struct pinctrl_dev_config *pincfg;
};
struct imx_pwm_data {
uint32_t period_cycles;
};
static bool imx_pwm_is_enabled(PWM_Type *base)
{
return PWM_PWMCR_REG(base) & PWM_PWMCR_EN_MASK;
}
static int imx_pwm_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
{
const struct imx_pwm_config *config = dev->config;
*cycles = get_pwm_clock_freq(config->base) >> config->prescaler;
return 0;
}
static int imx_pwm_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct imx_pwm_config *config = dev->config;
struct imx_pwm_data *data = dev->data;
unsigned int period_ms;
bool enabled = imx_pwm_is_enabled(config->base);
int wait_count = 0, fifoav;
uint32_t cr, sr;
if (period_cycles == 0U) {
LOG_ERR("Channel can not be set to inactive level");
return -ENOTSUP;
}
if (flags) {
/* PWM polarity not supported (yet?) */
return -ENOTSUP;
}
LOG_DBG("enabled=%d, pulse_cycles=%d, period_cycles=%d,"
" duty_cycle=%d\n", enabled, pulse_cycles, period_cycles,
(pulse_cycles * 100U / period_cycles));
/*
* i.MX PWMv2 has a 4-word sample FIFO.
* In order to avoid FIFO overflow issue, we do software reset
* to clear all sample FIFO if the controller is disabled or
* wait for a full PWM cycle to get a relinquished FIFO slot
* when the controller is enabled and the FIFO is fully loaded.
*/
if (enabled) {
sr = PWM_PWMSR_REG(config->base);
fifoav = PWM_PWMSR_FIFOAV(sr);
if (fifoav == PWM_PWMSR_FIFOAV_4WORDS) {
period_ms = (get_pwm_clock_freq(config->base) >>
config->prescaler) * MSEC_PER_SEC;
k_sleep(K_MSEC(period_ms));
sr = PWM_PWMSR_REG(config->base);
if (fifoav == PWM_PWMSR_FIFOAV(sr)) {
LOG_WRN("there is no free FIFO slot\n");
}
}
} else {
PWM_PWMCR_REG(config->base) = PWM_PWMCR_SWR(1);
do {
k_sleep(K_MSEC(1));
cr = PWM_PWMCR_REG(config->base);
} while ((PWM_PWMCR_SWR(cr)) &&
(++wait_count < CONFIG_PWM_PWMSWR_LOOP));
if (PWM_PWMCR_SWR(cr)) {
LOG_WRN("software reset timeout\n");
}
}
/*
* according to imx pwm RM, the real period value should be
* PERIOD value in PWMPR plus 2.
*/
if (period_cycles > 2) {
period_cycles -= 2U;
} else {
return -EINVAL;
}
PWM_PWMSAR_REG(config->base) = pulse_cycles;
if (data->period_cycles != period_cycles) {
LOG_WRN("Changing period cycles from %d to %d in %s",
data->period_cycles, period_cycles,
dev->name);
data->period_cycles = period_cycles;
PWM_PWMPR_REG(config->base) = period_cycles;
}
cr = PWM_PWMCR_EN_MASK | PWM_PWMCR_PRESCALER(config->prescaler) |
PWM_PWMCR_DOZEN_MASK | PWM_PWMCR_WAITEN_MASK |
PWM_PWMCR_DBGEN_MASK | PWM_PWMCR_CLKSRC(2);
PWM_PWMCR_REG(config->base) = cr;
return 0;
}
static int imx_pwm_init(const struct device *dev)
{
const struct imx_pwm_config *config = dev->config;
struct imx_pwm_data *data = dev->data;
int err;
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
PWM_PWMPR_REG(config->base) = data->period_cycles;
return 0;
}
static const struct pwm_driver_api imx_pwm_driver_api = {
.set_cycles = imx_pwm_set_cycles,
.get_cycles_per_sec = imx_pwm_get_cycles_per_sec,
};
#define PWM_IMX_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static const struct imx_pwm_config imx_pwm_config_##n = { \
.base = (PWM_Type *)DT_INST_REG_ADDR(n), \
.prescaler = DT_INST_PROP(n, prescaler), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
\
static struct imx_pwm_data imx_pwm_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, &imx_pwm_init, NULL, \
&imx_pwm_data_##n, \
&imx_pwm_config_##n, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&imx_pwm_driver_api);
#if DT_HAS_COMPAT_STATUS_OKAY(fsl_imx27_pwm)
#define DT_DRV_COMPAT fsl_imx27_pwm
DT_INST_FOREACH_STATUS_OKAY(PWM_IMX_INIT)
#endif
``` | /content/code_sandbox/drivers/pwm/pwm_imx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,331 |
```unknown
# MCUX TPM PWM
config PWM_MCUX_TPM
bool "MCUX TPM PWM driver"
default y
depends on DT_HAS_NXP_KINETIS_TPM_ENABLED
depends on CLOCK_CONTROL
select PINCTRL
help
Enable the MCUX TPM PWM driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.mcux_tpm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_capture, CONFIG_PWM_LOG_LEVEL);
struct z_pwm_capture_cb_data {
uint32_t period;
uint32_t pulse;
struct k_sem sem;
int status;
};
static void z_pwm_capture_cycles_callback(const struct device *dev,
uint32_t channel,
uint32_t period_cycles,
uint32_t pulse_cycles, int status,
void *user_data)
{
struct z_pwm_capture_cb_data *data = user_data;
data->period = period_cycles;
data->pulse = pulse_cycles;
data->status = status;
k_sem_give(&data->sem);
}
int z_impl_pwm_capture_cycles(const struct device *dev, uint32_t channel,
pwm_flags_t flags, uint32_t *period,
uint32_t *pulse, k_timeout_t timeout)
{
struct z_pwm_capture_cb_data data;
int err;
if ((flags & PWM_CAPTURE_MODE_MASK) == PWM_CAPTURE_MODE_CONTINUOUS) {
LOG_ERR("continuous capture mode only supported via callback");
return -ENOTSUP;
}
flags |= PWM_CAPTURE_MODE_SINGLE;
k_sem_init(&data.sem, 0, 1);
err = pwm_configure_capture(dev, channel, flags,
z_pwm_capture_cycles_callback, &data);
if (err) {
LOG_ERR("failed to configure pwm capture");
return err;
}
err = pwm_enable_capture(dev, channel);
if (err) {
LOG_ERR("failed to enable pwm capture");
return err;
}
err = k_sem_take(&data.sem, timeout);
if (err == -EAGAIN) {
(void)pwm_disable_capture(dev, channel);
(void)pwm_configure_capture(dev, channel, flags, NULL, NULL);
LOG_WRN("pwm capture timed out");
return err;
}
if (data.status == 0) {
if (period != NULL) {
*period = data.period;
}
if (pulse != NULL) {
*pulse = data.pulse;
}
}
return data.status;
}
``` | /content/code_sandbox/drivers/pwm/pwm_capture.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 458 |
```unknown
# Xilinx AXI Timer
config PWM_XLNX_AXI_TIMER
bool "Xilinx AXI Timer driver"
default y
depends on DT_HAS_XLNX_XPS_TIMER_1_00_A_PWM_ENABLED
help
Enable PWM support for the Xilinx AXI Timer v2.0 IP.
``` | /content/code_sandbox/drivers/pwm/Kconfig.xlnx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
config PWM_XMC4XXX_CCU4
bool "Infineon XMC4XXX CCU4 driver"
default y
depends on DT_HAS_INFINEON_XMC4XXX_CCU4_PWM_ENABLED
help
Enables Infineon XMC4XXX CCU4 PWM driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.xmc4xxx_ccu4 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_mcpwm
#include <hal/mcpwm_hal.h>
#include <hal/mcpwm_ll.h>
#include <driver/mcpwm.h>
#include <soc.h>
#include <errno.h>
#include <string.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#ifdef CONFIG_PWM_CAPTURE
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#endif /* CONFIG_PWM_CAPTURE */
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mcpwm_esp32, CONFIG_PWM_LOG_LEVEL);
#define SOC_MCPWM_BASE_CLK_HZ (160000000U)
#ifdef CONFIG_PWM_CAPTURE
#define SKIP_IRQ_NUM 4U
#define MCPWM_INTR_CAP0 BIT(0)
#define MCPWM_INTR_CAP1 BIT(1)
#define MCPWM_INTR_CAP2 BIT(2)
#define MCPWM_CHANNEL_NUM 8U
#define CAPTURE_CHANNEL_IDX 6U
#else
#define MCPWM_CHANNEL_NUM 6U
#endif /* CONFIG_PWM_CAPTURE */
struct mcpwm_esp32_data {
mcpwm_hal_context_t hal;
mcpwm_hal_init_config_t init_config;
struct k_sem cmd_sem;
};
#ifdef CONFIG_PWM_CAPTURE
struct capture_data {
uint32_t value;
mcpwm_capture_on_edge_t edge;
};
struct mcpwm_esp32_capture_config {
uint8_t capture_signal;
pwm_capture_callback_handler_t callback;
void *user_data;
uint32_t period;
uint32_t pulse;
uint32_t overflows;
uint8_t skip_irq;
bool capture_period;
bool capture_pulse;
bool continuous;
struct capture_data capture_data[SKIP_IRQ_NUM];
};
#endif /* CONFIG_PWM_CAPTURE */
struct mcpwm_esp32_channel_config {
uint8_t idx;
uint8_t timer_id;
uint8_t operator_id;
uint8_t generator_id;
uint32_t freq;
uint32_t duty;
uint8_t prescale;
bool inverted;
#ifdef CONFIG_PWM_CAPTURE
struct mcpwm_esp32_capture_config capture;
#endif /* CONFIG_PWM_CAPTURE */
};
struct mcpwm_esp32_config {
const uint8_t index;
const struct pinctrl_dev_config *pincfg;
const struct device *clock_dev;
const clock_control_subsys_t clock_subsys;
uint8_t prescale;
uint8_t prescale_timer0;
uint8_t prescale_timer1;
uint8_t prescale_timer2;
struct mcpwm_esp32_channel_config channel_config[MCPWM_CHANNEL_NUM];
#ifdef CONFIG_PWM_CAPTURE
void (*irq_config_func)(const struct device *dev);
#endif /* CONFIG_PWM_CAPTURE */
};
static void mcpwm_esp32_duty_set(const struct device *dev,
struct mcpwm_esp32_channel_config *channel)
{
struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data;
mcpwm_duty_type_t duty_type;
uint32_t set_duty;
if (channel->inverted) {
duty_type = channel->duty == 0 ?
MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH : channel->duty == 100 ?
MCPWM_HAL_GENERATOR_MODE_FORCE_LOW : MCPWM_DUTY_MODE_1;
} else {
duty_type = channel->duty == 0 ?
MCPWM_HAL_GENERATOR_MODE_FORCE_LOW : channel->duty == 100 ?
MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH : MCPWM_DUTY_MODE_0;
}
set_duty = mcpwm_ll_timer_get_peak(data->hal.dev, channel->timer_id, false) *
channel->duty / 100;
mcpwm_ll_operator_connect_timer(data->hal.dev, channel->operator_id, channel->timer_id);
mcpwm_ll_operator_set_compare_value(data->hal.dev, channel->operator_id,
channel->generator_id, set_duty);
mcpwm_ll_operator_enable_update_compare_on_tez(data->hal.dev, channel->operator_id,
channel->generator_id, true);
if (duty_type == MCPWM_DUTY_MODE_0) {
mcpwm_ll_generator_set_action_on_timer_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_KEEP);
mcpwm_ll_generator_set_action_on_compare_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, channel->generator_id, MCPWM_ACTION_FORCE_LOW);
} else if (duty_type == MCPWM_DUTY_MODE_1) {
mcpwm_ll_generator_set_action_on_timer_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW);
mcpwm_ll_generator_set_action_on_timer_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_NO_CHANGE);
mcpwm_ll_generator_set_action_on_compare_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, channel->generator_id, MCPWM_ACTION_FORCE_HIGH);
} else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_LOW) {
mcpwm_ll_generator_set_action_on_timer_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_compare_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, channel->generator_id, MCPWM_ACTION_FORCE_LOW);
} else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH) {
mcpwm_ll_generator_set_action_on_timer_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_compare_event(
data->hal.dev, channel->operator_id, channel->generator_id,
MCPWM_TIMER_DIRECTION_UP, channel->generator_id, MCPWM_ACTION_FORCE_HIGH);
}
}
static int mcpwm_esp32_configure_pinctrl(const struct device *dev)
{
int ret;
struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config;
ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("PWM pinctrl setup failed (%d)", ret);
return ret;
}
return 0;
}
static int mcpwm_esp32_timer_set(const struct device *dev,
struct mcpwm_esp32_channel_config *channel)
{
struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data;
__ASSERT_NO_MSG(channel->freq > 0);
mcpwm_ll_timer_set_clock_prescale(data->hal.dev, channel->timer_id, channel->prescale);
mcpwm_ll_timer_set_count_mode(data->hal.dev, channel->timer_id, MCPWM_TIMER_COUNT_MODE_UP);
mcpwm_ll_timer_update_period_at_once(data->hal.dev, channel->timer_id);
int real_group_prescale = mcpwm_ll_group_get_clock_prescale(data->hal.dev);
uint32_t real_timer_clk_hz =
SOC_MCPWM_BASE_CLK_HZ / real_group_prescale /
mcpwm_ll_timer_get_clock_prescale(data->hal.dev, channel->timer_id);
mcpwm_ll_timer_set_peak(data->hal.dev, channel->timer_id, real_timer_clk_hz / channel->freq,
false);
return 0;
}
static int mcpwm_esp32_get_cycles_per_sec(const struct device *dev, uint32_t channel_idx,
uint64_t *cycles)
{
struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config;
struct mcpwm_esp32_channel_config *channel = &config->channel_config[channel_idx];
if (!channel) {
LOG_ERR("Error getting channel %d", channel_idx);
return -EINVAL;
}
#ifdef CONFIG_PWM_CAPTURE
if (channel->idx >= CAPTURE_CHANNEL_IDX) {
*cycles = (uint64_t)APB_CLK_FREQ;
return 0;
}
#endif /* CONFIG_PWM_CAPTURE */
*cycles =
(uint64_t)SOC_MCPWM_BASE_CLK_HZ / (config->prescale + 1) / (channel->prescale + 1);
return 0;
}
static int mcpwm_esp32_set_cycles(const struct device *dev, uint32_t channel_idx,
uint32_t period_cycles, uint32_t pulse_cycles, pwm_flags_t flags)
{
int ret = 0;
uint64_t clk_freq;
struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config;
struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data;
struct mcpwm_esp32_channel_config *channel = &config->channel_config[channel_idx];
if (!channel) {
LOG_ERR("Error getting channel %d", channel_idx);
return -EINVAL;
}
/* Update PWM frequency according to period_cycles */
mcpwm_esp32_get_cycles_per_sec(dev, channel_idx, &clk_freq);
channel->freq = (uint32_t)(clk_freq / period_cycles);
if (!channel->freq) {
return -EINVAL;
}
k_sem_take(&data->cmd_sem, K_FOREVER);
ret = mcpwm_esp32_timer_set(dev, channel);
if (ret < 0) {
k_sem_give(&data->cmd_sem);
return ret;
}
double duty_cycle = (double)pulse_cycles * 100 / (double)period_cycles;
channel->duty = (uint32_t)duty_cycle;
channel->inverted = (flags & PWM_POLARITY_INVERTED);
mcpwm_esp32_duty_set(dev, channel);
ret = mcpwm_esp32_configure_pinctrl(dev);
if (ret < 0) {
k_sem_give(&data->cmd_sem);
return ret;
}
mcpwm_ll_timer_set_start_stop_command(data->hal.dev, channel->timer_id,
MCPWM_TIMER_START_NO_STOP);
k_sem_give(&data->cmd_sem);
return ret;
}
#ifdef CONFIG_PWM_CAPTURE
static int mcpwm_esp32_configure_capture(const struct device *dev, uint32_t channel_idx,
pwm_flags_t flags, pwm_capture_callback_handler_t cb,
void *user_data)
{
struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config;
struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data;
struct mcpwm_esp32_channel_config *channel = &config->channel_config[channel_idx];
struct mcpwm_esp32_capture_config *capture = &channel->capture;
if (!channel) {
LOG_ERR("Error getting channel %d", channel_idx);
return -EINVAL;
}
if ((channel->idx < CAPTURE_CHANNEL_IDX) || (channel->idx > CAPTURE_CHANNEL_IDX + 2)) {
LOG_ERR("PWM capture only supported on channels 6, 7 and 8");
return -EINVAL;
}
if (data->hal.dev->cap_chn_cfg[capture->capture_signal].capn_en) {
LOG_ERR("PWM Capture already in progress");
return -EBUSY;
}
if (!(flags & PWM_CAPTURE_TYPE_MASK)) {
LOG_ERR("No PWM capture type specified");
return -EINVAL;
}
channel->inverted = (flags & PWM_POLARITY_INVERTED);
capture->capture_signal = channel->idx - CAPTURE_CHANNEL_IDX;
capture->callback = cb;
capture->user_data = user_data;
capture->capture_period = (flags & PWM_CAPTURE_TYPE_PERIOD);
capture->capture_pulse = (flags & PWM_CAPTURE_TYPE_PULSE);
capture->continuous = (flags & PWM_CAPTURE_MODE_CONTINUOUS);
return 0;
}
static int mcpwm_esp32_disable_capture(const struct device *dev, uint32_t channel_idx)
{
struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config;
struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data;
struct mcpwm_esp32_channel_config *channel = &config->channel_config[channel_idx];
struct mcpwm_esp32_capture_config *capture = &channel->capture;
if (!channel) {
LOG_ERR("Error getting channel %d", channel_idx);
return -EINVAL;
}
if ((channel->idx < CAPTURE_CHANNEL_IDX) || (channel->idx > CAPTURE_CHANNEL_IDX + 2)) {
LOG_ERR("PWM capture only supported on channels 6, 7 and 8");
return -EINVAL;
}
mcpwm_ll_capture_enable_channel(data->hal.dev, capture->capture_signal, false);
mcpwm_ll_intr_enable(data->hal.dev, MCPWM_LL_EVENT_CAPTURE(capture->capture_signal), false);
return 0;
}
static int mcpwm_esp32_enable_capture(const struct device *dev, uint32_t channel_idx)
{
struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config;
struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data;
struct mcpwm_esp32_channel_config *channel = &config->channel_config[channel_idx];
struct mcpwm_esp32_capture_config *capture = &channel->capture;
if (!channel) {
LOG_ERR("Error getting channel %d", channel_idx);
return -EINVAL;
}
if (!capture->callback) {
LOG_ERR("Capture not configured");
return -EINVAL;
}
if ((channel->idx < CAPTURE_CHANNEL_IDX) || (channel->idx > CAPTURE_CHANNEL_IDX + 2)) {
LOG_ERR("PWM capture only supported on channels 6, 7 and 8");
return -EINVAL;
}
if (data->hal.dev->cap_chn_cfg[capture->capture_signal].capn_en) {
LOG_ERR("PWM Capture already in progress");
return -EBUSY;
}
/**
* Capture prescale is different from other modules as it is applied to the input
* signal, not the timer source. It is disabled by default.
*/
mcpwm_capture_config_t cap_conf = {
.cap_edge = MCPWM_BOTH_EDGE,
.cap_prescale = 1,
};
mcpwm_hal_init(&data->hal, &data->init_config);
mcpwm_ll_group_set_clock_prescale(data->hal.dev, config->prescale);
mcpwm_ll_group_enable_shadow_mode(data->hal.dev);
mcpwm_ll_group_flush_shadow(data->hal.dev);
mcpwm_ll_capture_enable_timer(data->hal.dev, true);
mcpwm_ll_capture_enable_channel(data->hal.dev, capture->capture_signal, true);
mcpwm_ll_capture_enable_negedge(data->hal.dev, capture->capture_signal,
cap_conf.cap_edge & MCPWM_NEG_EDGE);
mcpwm_ll_capture_enable_posedge(data->hal.dev, capture->capture_signal,
cap_conf.cap_edge & MCPWM_POS_EDGE);
mcpwm_ll_capture_set_prescale(data->hal.dev, capture->capture_signal,
cap_conf.cap_prescale);
mcpwm_ll_intr_enable(data->hal.dev, MCPWM_LL_EVENT_CAPTURE(capture->capture_signal), true);
mcpwm_ll_intr_clear_capture_status(data->hal.dev, 1 << capture->capture_signal);
capture->skip_irq = 0;
return 0;
}
#endif /* CONFIG_PWM_CAPTURE */
static void channel_init(const struct device *dev)
{
struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config;
struct mcpwm_esp32_channel_config *channel;
for (uint8_t i = 0; i < MCPWM_CHANNEL_NUM; i++) {
channel = &config->channel_config[i];
channel->idx = i;
channel->timer_id = i < 2 ? 0 : i < 4 ? 1 : 2;
channel->operator_id = i < 2 ? 0 : i < 4 ? 1 : 2;
channel->generator_id = i % 2 ? 1 : 0;
channel->prescale = i < 2 ? config->prescale_timer0
: i < 4 ? config->prescale_timer1
: config->prescale_timer2;
}
}
int mcpwm_esp32_init(const struct device *dev)
{
int ret;
struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config;
struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data;
struct mcpwm_esp32_channel_config *channel;
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
/* Enable peripheral */
ret = clock_control_on(config->clock_dev, config->clock_subsys);
if (ret < 0) {
LOG_ERR("Could not initialize clock (%d)", ret);
return ret;
}
channel_init(dev);
mcpwm_hal_init(&data->hal, &data->init_config);
mcpwm_ll_group_set_clock_prescale(data->hal.dev, config->prescale);
mcpwm_ll_group_enable_shadow_mode(data->hal.dev);
mcpwm_ll_group_flush_shadow(data->hal.dev);
#ifdef CONFIG_PWM_CAPTURE
config->irq_config_func(dev);
#endif /* CONFIG_PWM_CAPTURE */
return 0;
}
#ifdef CONFIG_PWM_CAPTURE
static void IRAM_ATTR mcpwm_esp32_isr(const struct device *dev)
{
struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config;
struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data;
struct mcpwm_esp32_channel_config *channel;
struct mcpwm_esp32_capture_config *capture;
uint32_t mcpwm_intr_status;
struct capture_data cap_data;
mcpwm_intr_status = mcpwm_ll_intr_get_capture_status(data->hal.dev);
mcpwm_ll_intr_clear_capture_status(data->hal.dev, mcpwm_intr_status);
if (mcpwm_intr_status & MCPWM_INTR_CAP0) {
channel = &config->channel_config[CAPTURE_CHANNEL_IDX];
} else if (mcpwm_intr_status & MCPWM_INTR_CAP1) {
channel = &config->channel_config[CAPTURE_CHANNEL_IDX + 1];
} else if (mcpwm_intr_status & MCPWM_INTR_CAP2) {
channel = &config->channel_config[CAPTURE_CHANNEL_IDX + 2];
} else {
return;
}
if (!channel) {
return;
}
capture = &channel->capture;
/* We need to wait at least 4 (2 positive edges and 2 negative edges) interrupts to
* calculate the period
*/
if (capture->skip_irq < SKIP_IRQ_NUM) {
capture->capture_data[capture->skip_irq].value =
mcpwm_ll_capture_get_value(data->hal.dev, capture->capture_signal);
capture->capture_data[capture->skip_irq].edge =
mcpwm_ll_capture_get_edge(data->hal.dev, capture->capture_signal) ==
MCPWM_CAP_EDGE_NEG
? MCPWM_NEG_EDGE
: MCPWM_POS_EDGE;
capture->skip_irq++;
} else {
/**
* The capture timer is a 32-bit counter incrementing continuously, once enabled.
* On the input it has an APB clock running typically at 80 MHz
*/
capture->period = channel->inverted ?
capture->capture_data[0].edge == MCPWM_NEG_EDGE
? (capture->capture_data[2].value - capture->capture_data[0].value)
: (capture->capture_data[3].value - capture->capture_data[1].value)
: capture->capture_data[0].edge == MCPWM_POS_EDGE
? (capture->capture_data[2].value - capture->capture_data[0].value)
: (capture->capture_data[3].value - capture->capture_data[1].value);
capture->pulse = channel->inverted ?
capture->capture_data[0].edge == MCPWM_NEG_EDGE
? (capture->capture_data[1].value - capture->capture_data[0].value)
: (capture->capture_data[2].value - capture->capture_data[1].value)
: capture->capture_data[0].edge == MCPWM_POS_EDGE
? (capture->capture_data[1].value - capture->capture_data[0].value)
: (capture->capture_data[2].value - capture->capture_data[1].value);
capture->skip_irq = 0;
if (!capture->continuous) {
mcpwm_esp32_disable_capture(dev, channel->idx);
}
if (capture->callback) {
capture->callback(dev, capture->capture_signal + CAPTURE_CHANNEL_IDX,
capture->capture_period ? capture->period : 0u,
capture->capture_pulse ? capture->pulse : 0u, 0u,
capture->user_data);
}
}
}
#endif /* CONFIG_PWM_CAPTURE */
static const struct pwm_driver_api mcpwm_esp32_api = {
.set_cycles = mcpwm_esp32_set_cycles,
.get_cycles_per_sec = mcpwm_esp32_get_cycles_per_sec,
#ifdef CONFIG_PWM_CAPTURE
.configure_capture = mcpwm_esp32_configure_capture,
.enable_capture = mcpwm_esp32_enable_capture,
.disable_capture = mcpwm_esp32_disable_capture,
#endif /* CONFIG_PWM_CAPTURE */
};
#ifdef CONFIG_PWM_CAPTURE
#define IRQ_CONFIG_FUNC(idx) \
static void mcpwm_esp32_irq_config_func_##idx(const struct device *dev) \
{ \
esp_intr_alloc(DT_INST_IRQN(idx), 0, (intr_handler_t)mcpwm_esp32_isr, (void *)dev, \
NULL); \
}
#define CAPTURE_INIT(idx) .irq_config_func = mcpwm_esp32_irq_config_func_##idx
#else
#define IRQ_CONFIG_FUNC(idx)
#define CAPTURE_INIT(idx)
#endif /* CONFIG_PWM_CAPTURE */
#define ESP32_MCPWM_INIT(idx) \
PINCTRL_DT_INST_DEFINE(idx); \
IRQ_CONFIG_FUNC(idx); \
static struct mcpwm_esp32_data mcpwm_esp32_data_##idx = { \
.hal = \
{ \
.dev = (mcpwm_dev_t *)DT_INST_REG_ADDR(idx), \
}, \
.init_config = \
{ \
.group_id = idx, \
}, \
.cmd_sem = Z_SEM_INITIALIZER(mcpwm_esp32_data_##idx.cmd_sem, 1, 1), \
}; \
\
static struct mcpwm_esp32_config mcpwm_esp32_config_##idx = { \
.index = idx, \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
.prescale = DT_INST_PROP(idx, prescale), \
.prescale_timer0 = DT_INST_PROP_OR(idx, prescale_timer0, 0), \
.prescale_timer1 = DT_INST_PROP_OR(idx, prescale_timer1, 0), \
.prescale_timer2 = DT_INST_PROP_OR(idx, prescale_timer2, 0), \
CAPTURE_INIT(idx)}; \
\
DEVICE_DT_INST_DEFINE(idx, &mcpwm_esp32_init, NULL, &mcpwm_esp32_data_##idx, \
&mcpwm_esp32_config_##idx, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&mcpwm_esp32_api);
DT_INST_FOREACH_STATUS_OKAY(ESP32_MCPWM_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_mc_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,545 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_pwm_rcar
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
#include <soc.h>
#define LOG_LEVEL CONFIG_PWM_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_rcar);
/* PWM Controller capabilities */
#define RCAR_PWM_MAX_CYCLE 1023U
#define RCAR_PWM_MAX_DIV 24U
#define RCAR_PWM_MAX_CHANNEL 6
/* Registers */
#define RCAR_PWM_REG_SHIFT 0x1000
#define RCAR_PWM_CR(channel) \
((uint32_t)((channel * RCAR_PWM_REG_SHIFT)) + 0x00) /* PWM Control Register */
#define RCAR_PWM_CNT(channel) \
((uint32_t)((channel * RCAR_PWM_REG_SHIFT)) + 0x04) /* PWM Count Register */
/* PWMCR (PWM Control Register) */
#define RCAR_PWM_CR_CC_MASK 0x000f0000 /* Clock Control */
#define RCAR_PWM_CR_CC_SHIFT 16
#define RCAR_PWM_CR_CCMD BIT(15) /* Frequency Division Mode */
#define RCAR_PWM_CR_SYNC BIT(11)
#define RCAR_PWM_CR_SS BIT(4) /* Single Pulse Output */
#define RCAR_PWM_CR_EN BIT(0) /* Channel Enable */
/* PWM Diviser is on 5 bits (CC combined with CCMD) */
#define RCAR_PWM_DIVISER_MASK (RCAR_PWM_CR_CC_MASK | RCAR_PWM_CR_CCMD)
#define RCAR_PWM_DIVISER_SHIFT 15
/* PWMCNT (PWM Count Register) */
#define RCAR_PWM_CNT_CYC_MASK 0x03ff0000 /* PWM Cycle */
#define RCAR_PWM_CNT_CYC_SHIFT 16
#define RCAR_PWM_CNT_PH_MASK 0x000003ff /* PWM High-Level Period */
#define RCAR_PWM_CNT_PH_SHIFT 0
struct pwm_rcar_cfg {
uint32_t reg_addr;
const struct device *clock_dev;
struct rcar_cpg_clk core_clk;
struct rcar_cpg_clk mod_clk;
const struct pinctrl_dev_config *pcfg;
};
struct pwm_rcar_data {
uint32_t clk_rate;
};
static uint32_t pwm_rcar_read(const struct pwm_rcar_cfg *config, uint32_t offs)
{
return sys_read32(config->reg_addr + offs);
}
static void pwm_rcar_write(const struct pwm_rcar_cfg *config, uint32_t offs, uint32_t value)
{
sys_write32(value, config->reg_addr + offs);
}
static void pwm_rcar_write_bit(const struct pwm_rcar_cfg *config, uint32_t offs, uint32_t bits,
bool value)
{
uint32_t reg_val = pwm_rcar_read(config, offs);
if (value) {
reg_val |= bits;
} else {
reg_val &= ~(bits);
}
pwm_rcar_write(config, offs, reg_val);
}
static int pwm_rcar_update_clk(const struct pwm_rcar_cfg *config, uint32_t channel,
uint32_t *period_cycles, uint32_t *pulse_cycles)
{
uint32_t reg_val, power, diviser;
power = pwm_rcar_read(config, RCAR_PWM_CR(channel)) & RCAR_PWM_DIVISER_MASK;
power = power >> RCAR_PWM_DIVISER_SHIFT;
diviser = 1 << power;
LOG_DBG("Found old diviser : 2^%d=%d", power, diviser);
/* Looking for the best possible clock diviser */
if (*period_cycles > RCAR_PWM_MAX_CYCLE) {
/* Reducing clock speed */
while (*period_cycles > RCAR_PWM_MAX_CYCLE) {
diviser *= 2;
*period_cycles /= 2;
*pulse_cycles /= 2;
power++;
if (power > RCAR_PWM_MAX_DIV) {
return -ENOTSUP;
}
}
} else {
/* Increasing clock speed */
while (*period_cycles < (RCAR_PWM_MAX_CYCLE / 2)) {
if (power == 0) {
return -ENOTSUP;
}
diviser /= 2;
*period_cycles *= 2;
*pulse_cycles *= 2;
power--;
}
}
LOG_DBG("Found new diviser : 2^%d=%d\n", power, diviser);
/* Set new clock Diviser */
reg_val = pwm_rcar_read(config, RCAR_PWM_CR(channel));
reg_val &= ~RCAR_PWM_DIVISER_MASK;
reg_val |= (power << RCAR_PWM_DIVISER_SHIFT);
pwm_rcar_write(config, RCAR_PWM_CR(channel), reg_val);
return 0;
}
static int pwm_rcar_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles,
uint32_t pulse_cycles, pwm_flags_t flags)
{
const struct pwm_rcar_cfg *config = dev->config;
uint32_t reg_val;
int ret = 0;
if (channel > RCAR_PWM_MAX_CHANNEL) {
return -ENOTSUP;
}
if (flags != PWM_POLARITY_NORMAL) {
return -ENOTSUP;
}
/* Prohibited values */
if (period_cycles == 0U || pulse_cycles == 0U || pulse_cycles > period_cycles) {
return -EINVAL;
}
LOG_DBG("base_reg=0x%x, pulse_cycles=%d, period_cycles=%d,"
" duty_cycle=%d",
config->reg_addr, pulse_cycles, period_cycles,
(pulse_cycles * 100U / period_cycles));
/* Disable PWM */
pwm_rcar_write_bit(config, RCAR_PWM_CR(channel), RCAR_PWM_CR_EN, false);
/* Set continuous mode */
pwm_rcar_write_bit(config, RCAR_PWM_CR(channel), RCAR_PWM_CR_SS, false);
/* Enable SYNC mode */
pwm_rcar_write_bit(config, RCAR_PWM_CR(channel), RCAR_PWM_CR_SYNC, true);
/*
* Set clock counter according to the requested period_cycles
* if period_cycles is less than half of the counter, then the
* clock diviser could be updated as the diviser is a modulo 2.
*/
if (period_cycles > RCAR_PWM_MAX_CYCLE || period_cycles < (RCAR_PWM_MAX_CYCLE / 2)) {
LOG_DBG("Adapting frequency diviser...");
ret = pwm_rcar_update_clk(config, channel, &period_cycles, &pulse_cycles);
if (ret != 0) {
return ret;
}
}
/* Set total period cycle */
reg_val = pwm_rcar_read(config, RCAR_PWM_CNT(channel));
reg_val &= ~(RCAR_PWM_CNT_CYC_MASK);
reg_val |= (period_cycles << RCAR_PWM_CNT_CYC_SHIFT);
pwm_rcar_write(config, RCAR_PWM_CNT(channel), reg_val);
/* Set high level period cycle */
reg_val = pwm_rcar_read(config, RCAR_PWM_CNT(channel));
reg_val &= ~(RCAR_PWM_CNT_PH_MASK);
reg_val |= (pulse_cycles << RCAR_PWM_CNT_PH_SHIFT);
pwm_rcar_write(config, RCAR_PWM_CNT(channel), reg_val);
/* Enable PWM */
pwm_rcar_write_bit(config, RCAR_PWM_CR(channel), RCAR_PWM_CR_EN, true);
return ret;
}
static int pwm_rcar_get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles)
{
const struct pwm_rcar_cfg *config = dev->config;
struct pwm_rcar_data *data = dev->data;
uint32_t diviser;
if (channel > RCAR_PWM_MAX_CHANNEL) {
return -ENOTSUP;
}
diviser = pwm_rcar_read(config, RCAR_PWM_CR(channel)) & RCAR_PWM_DIVISER_MASK;
diviser = diviser >> RCAR_PWM_DIVISER_SHIFT;
*cycles = data->clk_rate >> diviser;
LOG_DBG("Actual division: %d and Frequency: %d Hz", diviser, (uint32_t)*cycles);
return 0;
}
static int pwm_rcar_init(const struct device *dev)
{
const struct pwm_rcar_cfg *config = dev->config;
struct pwm_rcar_data *data = dev->data;
int ret;
/* Configure dt provided device signals when available */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->mod_clk);
if (ret < 0) {
return ret;
}
ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->core_clk,
&data->clk_rate);
if (ret < 0) {
return ret;
}
return 0;
}
static const struct pwm_driver_api pwm_rcar_driver_api = {
.set_cycles = pwm_rcar_set_cycles,
.get_cycles_per_sec = pwm_rcar_get_cycles_per_sec,
};
/* Device Instantiation */
#define PWM_DEVICE_RCAR_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static const struct pwm_rcar_cfg pwm_rcar_cfg_##n = { \
.reg_addr = DT_INST_REG_ADDR(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.mod_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
.mod_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
.core_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
.core_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
}; \
static struct pwm_rcar_data pwm_rcar_data_##n; \
DEVICE_DT_INST_DEFINE(n, pwm_rcar_init, NULL, &pwm_rcar_data_##n, &pwm_rcar_cfg_##n, \
POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&pwm_rcar_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_RCAR_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_rcar.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,240 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_npcx_pwm
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/dt-bindings/clock/npcx_clock.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_npcx, LOG_LEVEL_ERR);
/* 16-bit period cycles/prescaler in NPCX PWM modules */
#define NPCX_PWM_MAX_PRESCALER (1UL << (16))
#define NPCX_PWM_MAX_PERIOD_CYCLES (1UL << (16))
/* PWM clock sources */
#define NPCX_PWM_CLOCK_APB2_LFCLK 0
#define NPCX_PWM_CLOCK_FX 1
#define NPCX_PWM_CLOCK_FR 2
#define NPCX_PWM_CLOCK_RESERVED 3
/* PWM heart-beat mode selection */
#define NPCX_PWM_HBM_NORMAL 0
#define NPCX_PWM_HBM_25 1
#define NPCX_PWM_HBM_50 2
#define NPCX_PWM_HBM_100 3
/* Device config */
struct pwm_npcx_config {
/* pwm controller base address */
struct pwm_reg *base;
/* clock configuration */
struct npcx_clk_cfg clk_cfg;
/* pinmux configuration */
const struct pinctrl_dev_config *pcfg;
};
/* Driver data */
struct pwm_npcx_data {
/* PWM cycles per second */
uint32_t cycles_per_sec;
};
/* PWM local functions */
static void pwm_npcx_configure(const struct device *dev, int clk_bus)
{
const struct pwm_npcx_config *config = dev->config;
struct pwm_reg *inst = config->base;
/* Disable PWM for module configuration first */
inst->PWMCTL &= ~BIT(NPCX_PWMCTL_PWR);
/* Set default PWM polarity to normal */
inst->PWMCTL &= ~BIT(NPCX_PWMCTL_INVP);
/* Turn off PWM heart-beat mode */
SET_FIELD(inst->PWMCTL, NPCX_PWMCTL_HB_DC_CTL_FIELD,
NPCX_PWM_HBM_NORMAL);
/* Select APB CLK/LFCLK clock sources to PWM module by default */
SET_FIELD(inst->PWMCTLEX, NPCX_PWMCTLEX_FCK_SEL_FIELD,
NPCX_PWM_CLOCK_APB2_LFCLK);
/* Select clock source to LFCLK by flag, otherwise APB clock source */
if (clk_bus == NPCX_CLOCK_BUS_LFCLK)
inst->PWMCTL |= BIT(NPCX_PWMCTL_CKSEL);
else
inst->PWMCTL &= ~BIT(NPCX_PWMCTL_CKSEL);
}
/* PWM api functions */
static int pwm_npcx_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
/* Single channel for each pwm device */
ARG_UNUSED(channel);
const struct pwm_npcx_config *config = dev->config;
struct pwm_npcx_data *const data = dev->data;
struct pwm_reg *inst = config->base;
int prescaler;
uint32_t ctl;
uint32_t ctr;
uint32_t dcr;
uint32_t prsc;
ctl = inst->PWMCTL | BIT(NPCX_PWMCTL_PWR);
/* Select PWM inverted polarity (ie. active-low pulse). */
if (flags & PWM_POLARITY_INVERTED) {
ctl |= BIT(NPCX_PWMCTL_INVP);
} else {
ctl &= ~BIT(NPCX_PWMCTL_INVP);
}
/* If pulse_cycles is 0, switch PWM off and return. */
if (pulse_cycles == 0) {
ctl &= ~BIT(NPCX_PWMCTL_PWR);
inst->PWMCTL = ctl;
return 0;
}
/*
* Calculate PWM prescaler that let period_cycles map to
* maximum pwm period cycles and won't exceed it.
* Then prescaler = ceil (period_cycles / pwm_max_period_cycles)
*/
prescaler = DIV_ROUND_UP(period_cycles, NPCX_PWM_MAX_PERIOD_CYCLES);
if (prescaler > NPCX_PWM_MAX_PRESCALER) {
return -EINVAL;
}
/* Set PWM prescaler. */
prsc = prescaler - 1;
/* Set PWM period cycles. */
ctr = (period_cycles / prescaler) - 1;
/* Set PWM pulse cycles. */
dcr = (pulse_cycles / prescaler) - 1;
LOG_DBG("freq %d, pre %d, period %d, pulse %d",
data->cycles_per_sec / period_cycles, prsc, ctr, dcr);
/* Reconfigure only if necessary. */
if (inst->PWMCTL != ctl || inst->PRSC != prsc || inst->CTR != ctr) {
/* Disable PWM before configuring. */
inst->PWMCTL &= ~BIT(NPCX_PWMCTL_PWR);
inst->PRSC = prsc;
inst->CTR = ctr;
inst->DCR = dcr;
/* Enable PWM now. */
inst->PWMCTL = ctl;
return 0;
}
inst->DCR = dcr;
return 0;
}
static int pwm_npcx_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
/* Single channel for each pwm device */
ARG_UNUSED(channel);
struct pwm_npcx_data *const data = dev->data;
*cycles = data->cycles_per_sec;
return 0;
}
/* PWM driver registration */
static const struct pwm_driver_api pwm_npcx_driver_api = {
.set_cycles = pwm_npcx_set_cycles,
.get_cycles_per_sec = pwm_npcx_get_cycles_per_sec
};
static int pwm_npcx_init(const struct device *dev)
{
const struct pwm_npcx_config *const config = dev->config;
struct pwm_npcx_data *const data = dev->data;
struct pwm_reg *const inst = config->base;
const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
int ret;
/*
* NPCX PWM module mixes byte and word registers together. Make sure
* word reg access via structure won't break into two byte reg accesses
* unexpectedly by toolchains options or attributes. If so, stall here.
*/
NPCX_REG_WORD_ACCESS_CHECK(inst->PRSC, 0xA55A);
if (!device_is_ready(clk_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
/* Turn on device clock first and get source clock freq. */
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on PWM clock fail %d", ret);
return ret;
}
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)
&config->clk_cfg, &data->cycles_per_sec);
if (ret < 0) {
LOG_ERR("Get PWM clock rate error %d", ret);
return ret;
}
/* Configure PWM device initially */
pwm_npcx_configure(dev, config->clk_cfg.bus);
/* Configure pin-mux for PWM device */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("PWM pinctrl setup failed (%d)", ret);
return ret;
}
return 0;
}
#define NPCX_PWM_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
\
static const struct pwm_npcx_config pwm_npcx_cfg_##inst = { \
.base = (struct pwm_reg *)DT_INST_REG_ADDR(inst), \
.clk_cfg = NPCX_DT_CLK_CFG_ITEM(inst), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
\
static struct pwm_npcx_data pwm_npcx_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, \
&pwm_npcx_init, NULL, \
&pwm_npcx_data_##inst, &pwm_npcx_cfg_##inst, \
PRE_KERNEL_1, CONFIG_PWM_INIT_PRIORITY, \
&pwm_npcx_driver_api);
DT_INST_FOREACH_STATUS_OKAY(NPCX_PWM_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_npcx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,799 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_ledc
/* Include esp-idf headers first to avoid redefining BIT() macro */
#include <hal/ledc_hal.h>
#include <hal/ledc_types.h>
#include <soc.h>
#include <errno.h>
#include <string.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_ledc_esp32, CONFIG_PWM_LOG_LEVEL);
struct pwm_ledc_esp32_data {
ledc_hal_context_t hal;
struct k_sem cmd_sem;
};
struct pwm_ledc_esp32_channel_config {
const uint8_t idx;
const uint8_t channel_num;
const uint8_t timer_num;
uint32_t freq;
const ledc_mode_t speed_mode;
uint8_t resolution;
ledc_clk_src_t clock_src;
uint32_t duty_val;
};
struct pwm_ledc_esp32_config {
const struct pinctrl_dev_config *pincfg;
const struct device *clock_dev;
const clock_control_subsys_t clock_subsys;
struct pwm_ledc_esp32_channel_config *channel_config;
const int channel_len;
};
static struct pwm_ledc_esp32_channel_config *get_channel_config(const struct device *dev,
int channel_id)
{
struct pwm_ledc_esp32_config *config =
(struct pwm_ledc_esp32_config *) dev->config;
for (uint8_t i = 0; i < config->channel_len; i++) {
if (config->channel_config[i].idx == channel_id) {
return &config->channel_config[i];
}
}
return NULL;
}
static void pwm_led_esp32_low_speed_update(const struct device *dev, int speed_mode, int channel)
{
uint32_t reg_addr;
struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
if (speed_mode == LEDC_LOW_SPEED_MODE) {
ledc_hal_ls_channel_update(&data->hal, channel);
}
}
static void pwm_led_esp32_update_duty(const struct device *dev, int speed_mode, int channel)
{
struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
ledc_hal_set_sig_out_en(&data->hal, channel, true);
ledc_hal_set_duty_start(&data->hal, channel, true);
pwm_led_esp32_low_speed_update(dev, speed_mode, channel);
}
static void pwm_led_esp32_duty_set(const struct device *dev,
struct pwm_ledc_esp32_channel_config *channel)
{
struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
ledc_hal_set_hpoint(&data->hal, channel->channel_num, 0);
ledc_hal_set_duty_int_part(&data->hal, channel->channel_num, channel->duty_val);
ledc_hal_set_duty_direction(&data->hal, channel->channel_num, 1);
ledc_hal_set_duty_num(&data->hal, channel->channel_num, 1);
ledc_hal_set_duty_cycle(&data->hal, channel->channel_num, 1);
ledc_hal_set_duty_scale(&data->hal, channel->channel_num, 0);
pwm_led_esp32_low_speed_update(dev, channel->speed_mode, channel->channel_num);
pwm_led_esp32_update_duty(dev, channel->speed_mode, channel->channel_num);
}
static int pwm_led_esp32_configure_pinctrl(const struct device *dev)
{
int ret;
struct pwm_ledc_esp32_config *config = (struct pwm_ledc_esp32_config *) dev->config;
ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("PWM pinctrl setup failed (%d)", ret);
return ret;
}
return 0;
}
static void pwm_led_esp32_bind_channel_timer(const struct device *dev,
struct pwm_ledc_esp32_channel_config *channel)
{
struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
ledc_hal_bind_channel_timer(&data->hal, channel->channel_num, channel->timer_num);
pwm_led_esp32_low_speed_update(dev, channel->speed_mode, channel->channel_num);
}
static int pwm_led_esp32_calculate_max_resolution(struct pwm_ledc_esp32_channel_config *channel)
{
/**
* Max duty resolution can be obtained with
* max_res = log2(CLK_FREQ/FREQ)
*/
#if SOC_LEDC_SUPPORT_APB_CLOCK
uint64_t clock_freq = channel->clock_src == LEDC_APB_CLK ? APB_CLK_FREQ : REF_CLK_FREQ;
#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
uint64_t clock_freq = SCLK_CLK_FREQ;
#endif
uint32_t max_precision_n = clock_freq/channel->freq;
for (uint8_t i = 0; i <= SOC_LEDC_TIMER_BIT_WIDTH; i++) {
max_precision_n /= 2;
if (!max_precision_n) {
channel->resolution = i;
return 0;
}
}
return -EINVAL;
}
static int pwm_led_esp32_timer_config(struct pwm_ledc_esp32_channel_config *channel)
{
/**
* Calculate max resolution based on the given frequency and the pwm clock.
*
* There are 2 clock resources for PWM:
*
* 1. APB_CLK (80MHz)
* 2. REF_TICK (1MHz)
*
* The low speed timers can be sourced from:
*
* 1. APB_CLK (80MHz)
* 2. RTC_CLK (8Mhz)
*
* The APB_CLK is mostly used
*
* First we try to find the largest resolution using the APB_CLK source.
* If the given frequency doesn't support it, we move to the next clock source.
*/
#if SOC_LEDC_SUPPORT_APB_CLOCK
channel->clock_src = LEDC_APB_CLK;
#endif
if (!pwm_led_esp32_calculate_max_resolution(channel)) {
return 0;
}
#if SOC_LEDC_SUPPORT_REF_TICK
channel->clock_src = LEDC_REF_TICK;
if (!pwm_led_esp32_calculate_max_resolution(channel)) {
return 0;
}
#endif
/**
* ESP32 - S2,S3 and C3 variants have only 14 bits counter.
* where as the plain ESP32 variant has 20 bits counter.
* application failed to set low frequency(1Hz) in S2, S3 and C3 variants.
* to get very low frequencies on these variants,
* frequency needs to be tuned with 18 bits clock divider.
* so select the slow clock source (1MHz) with highest counter resolution.
* this can be handled on the func 'pwm_led_esp32_timer_set' with 'prescaler'.
*/
channel->resolution = SOC_LEDC_TIMER_BIT_WIDTH;
return 0;
}
static int pwm_led_esp32_timer_set(const struct device *dev,
struct pwm_ledc_esp32_channel_config *channel)
{
int prescaler = 0;
uint32_t precision = (0x1 << channel->resolution);
struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
__ASSERT_NO_MSG(channel->freq > 0);
switch (channel->clock_src) {
#if SOC_LEDC_SUPPORT_APB_CLOCK
case LEDC_APB_CLK:
/** This expression comes from ESP32 Espressif's Technical Reference
* Manual chapter 13.2.2 Timers.
* div_num is a fixed point value (Q10.8).
*/
prescaler = ((uint64_t) APB_CLK_FREQ << 8) / channel->freq / precision;
break;
#endif
#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
case LEDC_SCLK:
prescaler = ((uint64_t) SCLK_CLK_FREQ << 8) / channel->freq / precision;
break;
#endif
#if SOC_LEDC_SUPPORT_REF_TICK
case LEDC_REF_TICK:
prescaler = ((uint64_t) REF_CLK_FREQ << 8) / channel->freq / precision;
break;
#endif
default:
LOG_ERR("Invalid clock source (%d)", channel->clock_src);
return -EINVAL;
}
if (prescaler < 0x100 || prescaler > 0x3FFFF) {
LOG_ERR("Prescaler out of range: %#X", prescaler);
return -EINVAL;
}
if (channel->speed_mode == LEDC_LOW_SPEED_MODE) {
ledc_hal_set_slow_clk_sel(&data->hal, channel->clock_src);
}
ledc_hal_set_clock_divider(&data->hal, channel->timer_num, prescaler);
ledc_hal_set_duty_resolution(&data->hal, channel->timer_num, channel->resolution);
ledc_hal_set_clock_source(&data->hal, channel->timer_num, channel->clock_src);
if (channel->speed_mode == LEDC_LOW_SPEED_MODE) {
ledc_hal_ls_timer_update(&data->hal, channel->timer_num);
}
/* reset low speed timer */
ledc_hal_timer_rst(&data->hal, channel->timer_num);
return 0;
}
static int pwm_led_esp32_get_cycles_per_sec(const struct device *dev,
uint32_t channel_idx, uint64_t *cycles)
{
struct pwm_ledc_esp32_config *config = (struct pwm_ledc_esp32_config *) dev->config;
struct pwm_ledc_esp32_channel_config *channel = get_channel_config(dev, channel_idx);
if (!channel) {
LOG_ERR("Error getting channel %d", channel_idx);
return -EINVAL;
}
#if SOC_LEDC_SUPPORT_APB_CLOCK
*cycles = channel->clock_src == LEDC_APB_CLK ? APB_CLK_FREQ : REF_CLK_FREQ;
#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
*cycles = SCLK_CLK_FREQ;
#endif
return 0;
}
static int pwm_led_esp32_set_cycles(const struct device *dev, uint32_t channel_idx,
uint32_t period_cycles,
uint32_t pulse_cycles, pwm_flags_t flags)
{
int ret;
uint64_t clk_freq;
struct pwm_ledc_esp32_config *config = (struct pwm_ledc_esp32_config *) dev->config;
struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
struct pwm_ledc_esp32_channel_config *channel = get_channel_config(dev, channel_idx);
if (!channel) {
LOG_ERR("Error getting channel %d", channel_idx);
return -EINVAL;
}
/* Update PWM frequency according to period_cycles */
ret = pwm_led_esp32_get_cycles_per_sec(dev, channel_idx, &clk_freq);
if (ret < 0) {
return ret;
}
channel->freq = (uint32_t) (clk_freq/period_cycles);
if (!channel->freq) {
channel->freq = 1;
}
k_sem_take(&data->cmd_sem, K_FOREVER);
ledc_hal_init(&data->hal, channel->speed_mode);
ret = pwm_led_esp32_timer_config(channel);
if (ret < 0) {
k_sem_give(&data->cmd_sem);
return ret;
}
ret = pwm_led_esp32_timer_set(dev, channel);
if (ret < 0) {
k_sem_give(&data->cmd_sem);
return ret;
}
pwm_led_esp32_bind_channel_timer(dev, channel);
/* Update PWM duty */
double duty_cycle = (double) pulse_cycles / (double) period_cycles;
channel->duty_val = (uint32_t)((double) (1 << channel->resolution) * duty_cycle);
pwm_led_esp32_duty_set(dev, channel);
ret = pwm_led_esp32_configure_pinctrl(dev);
if (ret < 0) {
k_sem_give(&data->cmd_sem);
return ret;
}
k_sem_give(&data->cmd_sem);
return ret;
}
int pwm_led_esp32_init(const struct device *dev)
{
int ret;
const struct pwm_ledc_esp32_config *config = dev->config;
struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
/* Enable peripheral */
clock_control_on(config->clock_dev, config->clock_subsys);
return 0;
}
static const struct pwm_driver_api pwm_led_esp32_api = {
.set_cycles = pwm_led_esp32_set_cycles,
.get_cycles_per_sec = pwm_led_esp32_get_cycles_per_sec,
};
PINCTRL_DT_INST_DEFINE(0);
#if SOC_LEDC_SUPPORT_APB_CLOCK
#define CLOCK_SOURCE LEDC_APB_CLK
#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
#define CLOCK_SOURCE LEDC_SCLK
#endif
#define CHANNEL_CONFIG(node_id) \
{ \
.idx = DT_REG_ADDR(node_id), \
.channel_num = DT_REG_ADDR(node_id) % 8, \
.timer_num = DT_PROP(node_id, timer), \
.speed_mode = DT_REG_ADDR(node_id) < SOC_LEDC_CHANNEL_NUM \
? LEDC_LOW_SPEED_MODE \
: !LEDC_LOW_SPEED_MODE, \
.clock_src = CLOCK_SOURCE, \
},
static struct pwm_ledc_esp32_channel_config channel_config[] = {
DT_INST_FOREACH_CHILD(0, CHANNEL_CONFIG)
};
static struct pwm_ledc_esp32_config pwm_ledc_esp32_config = {
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(0, offset),
.channel_config = channel_config,
.channel_len = ARRAY_SIZE(channel_config),
};
static struct pwm_ledc_esp32_data pwm_ledc_esp32_data = {
.hal = {
.dev = (ledc_dev_t *) DT_INST_REG_ADDR(0),
},
.cmd_sem = Z_SEM_INITIALIZER(pwm_ledc_esp32_data.cmd_sem, 1, 1),
};
DEVICE_DT_INST_DEFINE(0, &pwm_led_esp32_init, NULL,
&pwm_ledc_esp32_data,
&pwm_ledc_esp32_config,
POST_KERNEL,
CONFIG_PWM_INIT_PRIORITY,
&pwm_led_esp32_api);
``` | /content/code_sandbox/drivers/pwm/pwm_led_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,235 |
```unknown
# RV32M1 TPM PWM
config PWM_RV32M1_TPM
bool "RV32M1 TPM PWM driver"
default y
depends on DT_HAS_OPENISA_RV32M1_TPM_ENABLED
depends on CLOCK_CONTROL
select PINCTRL
help
Enable the RV32M1 TPM PWM driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.rv32m1_tpm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_kinetis_ftm_pwm
#include <zephyr/drivers/clock_control.h>
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <fsl_ftm.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_ftm, CONFIG_PWM_LOG_LEVEL);
#define MAX_CHANNELS ARRAY_SIZE(FTM0->CONTROLS)
/* PWM capture operates on channel pairs */
#define MAX_CAPTURE_PAIRS (MAX_CHANNELS / 2U)
#define PAIR_1ST_CH(pair) (pair * 2U)
#define PAIR_2ND_CH(pair) (PAIR_1ST_CH(pair) + 1)
struct mcux_ftm_config {
FTM_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
ftm_clock_source_t ftm_clock_source;
ftm_clock_prescale_t prescale;
uint8_t channel_count;
ftm_pwm_mode_t mode;
#ifdef CONFIG_PWM_CAPTURE
void (*irq_config_func)(const struct device *dev);
#endif /* CONFIG_PWM_CAPTURE */
const struct pinctrl_dev_config *pincfg;
};
struct mcux_ftm_capture_data {
ftm_dual_edge_capture_param_t param;
pwm_capture_callback_handler_t callback;
void *user_data;
uint32_t first_edge_overflows;
uint16_t first_edge_cnt;
bool first_edge_overflow;
bool pulse_capture;
};
struct mcux_ftm_data {
uint32_t clock_freq;
uint32_t period_cycles;
ftm_chnl_pwm_config_param_t channel[MAX_CHANNELS];
#ifdef CONFIG_PWM_CAPTURE
uint32_t overflows;
struct mcux_ftm_capture_data capture[MAX_CAPTURE_PAIRS];
#endif /* CONFIG_PWM_CAPTURE */
};
static int mcux_ftm_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
status_t status;
#ifdef CONFIG_PWM_CAPTURE
uint32_t pair = channel / 2U;
uint32_t irqs;
#endif /* CONFIG_PWM_CAPTURE */
if (period_cycles == 0U) {
LOG_ERR("Channel can not be set to inactive level");
return -ENOTSUP;
}
if (period_cycles > UINT16_MAX) {
LOG_ERR("Period cycles must be less or equal than %u", UINT16_MAX);
return -EINVAL;
}
if (channel >= config->channel_count) {
LOG_ERR("Invalid channel");
return -ENOTSUP;
}
#ifdef CONFIG_PWM_CAPTURE
irqs = FTM_GetEnabledInterrupts(config->base);
if (irqs & BIT(PAIR_2ND_CH(pair))) {
LOG_ERR("Cannot set PWM, capture in progress on pair %d", pair);
return -EBUSY;
}
#endif /* CONFIG_PWM_CAPTURE */
data->channel[channel].dutyValue = pulse_cycles;
if ((flags & PWM_POLARITY_INVERTED) == 0) {
data->channel[channel].level = kFTM_HighTrue;
} else {
data->channel[channel].level = kFTM_LowTrue;
}
LOG_DBG("pulse_cycles=%d, period_cycles=%d, flags=%d",
pulse_cycles, period_cycles, flags);
if (period_cycles != data->period_cycles) {
#ifdef CONFIG_PWM_CAPTURE
if (irqs & BIT_MASK(ARRAY_SIZE(data->channel))) {
LOG_ERR("Cannot change period, capture in progress");
return -EBUSY;
}
#endif /* CONFIG_PWM_CAPTURE */
if (data->period_cycles != 0) {
/* Only warn when not changing from zero */
LOG_WRN("Changing period cycles from %d to %d"
" affects all %d channels in %s",
data->period_cycles, period_cycles,
config->channel_count, dev->name);
}
data->period_cycles = period_cycles;
FTM_StopTimer(config->base);
FTM_SetTimerPeriod(config->base, period_cycles);
FTM_SetSoftwareTrigger(config->base, true);
FTM_StartTimer(config->base, config->ftm_clock_source);
}
status = FTM_SetupPwmMode(config->base, data->channel,
config->channel_count, config->mode);
if (status != kStatus_Success) {
LOG_ERR("Could not set up pwm");
return -ENOTSUP;
}
FTM_SetSoftwareTrigger(config->base, true);
return 0;
}
#ifdef CONFIG_PWM_CAPTURE
static int mcux_ftm_configure_capture(const struct device *dev,
uint32_t channel, pwm_flags_t flags,
pwm_capture_callback_handler_t cb,
void *user_data)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
ftm_dual_edge_capture_param_t *param;
uint32_t pair = channel / 2U;
if (channel & 0x1U) {
LOG_ERR("PWM capture only supported on even channels");
return -ENOTSUP;
}
if (pair >= ARRAY_SIZE(data->capture)) {
LOG_ERR("Invalid channel pair %d", pair);
return -EINVAL;
}
if (FTM_GetEnabledInterrupts(config->base) & BIT(PAIR_2ND_CH(pair))) {
LOG_ERR("Capture already active on channel pair %d", pair);
return -EBUSY;
}
if (!(flags & PWM_CAPTURE_TYPE_MASK)) {
LOG_ERR("No capture type specified");
return -EINVAL;
}
if ((flags & PWM_CAPTURE_TYPE_MASK) == PWM_CAPTURE_TYPE_BOTH) {
LOG_ERR("Cannot capture both period and pulse width");
return -ENOTSUP;
}
data->capture[pair].callback = cb;
data->capture[pair].user_data = user_data;
param = &data->capture[pair].param;
if ((flags & PWM_CAPTURE_MODE_MASK) == PWM_CAPTURE_MODE_CONTINUOUS) {
param->mode = kFTM_Continuous;
} else {
param->mode = kFTM_OneShot;
}
if (flags & PWM_CAPTURE_TYPE_PERIOD) {
data->capture[pair].pulse_capture = false;
if (flags & PWM_POLARITY_INVERTED) {
param->currChanEdgeMode = kFTM_FallingEdge;
param->nextChanEdgeMode = kFTM_FallingEdge;
} else {
param->currChanEdgeMode = kFTM_RisingEdge;
param->nextChanEdgeMode = kFTM_RisingEdge;
}
} else {
data->capture[pair].pulse_capture = true;
if (flags & PWM_POLARITY_INVERTED) {
param->currChanEdgeMode = kFTM_FallingEdge;
param->nextChanEdgeMode = kFTM_RisingEdge;
} else {
param->currChanEdgeMode = kFTM_RisingEdge;
param->nextChanEdgeMode = kFTM_FallingEdge;
}
}
return 0;
}
static int mcux_ftm_enable_capture(const struct device *dev, uint32_t channel)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
uint32_t pair = channel / 2U;
if (channel & 0x1U) {
LOG_ERR("PWM capture only supported on even channels");
return -ENOTSUP;
}
if (pair >= ARRAY_SIZE(data->capture)) {
LOG_ERR("Invalid channel pair %d", pair);
return -EINVAL;
}
if (!data->capture[pair].callback) {
LOG_ERR("PWM capture not configured");
return -EINVAL;
}
if (FTM_GetEnabledInterrupts(config->base) & BIT(PAIR_2ND_CH(pair))) {
LOG_ERR("Capture already active on channel pair %d", pair);
return -EBUSY;
}
FTM_ClearStatusFlags(config->base, BIT(PAIR_1ST_CH(pair)) |
BIT(PAIR_2ND_CH(pair)));
FTM_SetupDualEdgeCapture(config->base, pair, &data->capture[pair].param,
CONFIG_PWM_CAPTURE_MCUX_FTM_FILTER_VALUE);
FTM_EnableInterrupts(config->base, BIT(PAIR_1ST_CH(pair)) |
BIT(PAIR_2ND_CH(pair)));
return 0;
}
static int mcux_ftm_disable_capture(const struct device *dev, uint32_t channel)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
uint32_t pair = channel / 2U;
if (channel & 0x1U) {
LOG_ERR("PWM capture only supported on even channels");
return -ENOTSUP;
}
if (pair >= ARRAY_SIZE(data->capture)) {
LOG_ERR("Invalid channel pair %d", pair);
return -EINVAL;
}
FTM_DisableInterrupts(config->base, BIT(PAIR_1ST_CH(pair)) |
BIT(PAIR_2ND_CH(pair)));
/* Clear Dual Edge Capture Enable bit */
config->base->COMBINE &= ~(1UL << (FTM_COMBINE_DECAP0_SHIFT +
(FTM_COMBINE_COMBINE1_SHIFT * pair)));
return 0;
}
static void mcux_ftm_capture_first_edge(const struct device *dev, uint32_t channel,
uint16_t cnt, bool overflow)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
struct mcux_ftm_capture_data *capture;
uint32_t pair = channel / 2U;
__ASSERT_NO_MSG(pair < ARRAY_SIZE(data->capture));
capture = &data->capture[pair];
FTM_DisableInterrupts(config->base, BIT(PAIR_1ST_CH(pair)));
capture->first_edge_cnt = cnt;
capture->first_edge_overflows = data->overflows;
capture->first_edge_overflow = overflow;
LOG_DBG("pair = %d, 1st cnt = %u, 1st ovf = %d", pair, cnt, overflow);
}
static void mcux_ftm_capture_second_edge(const struct device *dev, uint32_t channel,
uint16_t cnt, bool overflow)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
uint32_t second_edge_overflows = data->overflows;
struct mcux_ftm_capture_data *capture;
uint32_t pair = channel / 2U;
uint32_t overflows;
uint32_t first_cnv;
uint32_t second_cnv;
uint32_t cycles = 0;
int status = 0;
__ASSERT_NO_MSG(pair < ARRAY_SIZE(data->capture));
capture = &data->capture[pair];
first_cnv = config->base->CONTROLS[PAIR_1ST_CH(pair)].CnV;
second_cnv = config->base->CONTROLS[PAIR_2ND_CH(pair)].CnV;
if (capture->pulse_capture) {
/* Clear both edge flags for pulse capture to capture first edge overflow counter */
FTM_ClearStatusFlags(config->base, BIT(PAIR_1ST_CH(pair)) | BIT(PAIR_2ND_CH(pair)));
} else {
/* Only clear second edge flag for period capture as next first edge is this edge */
FTM_ClearStatusFlags(config->base, BIT(PAIR_2ND_CH(pair)));
}
if (unlikely(capture->first_edge_overflow && first_cnv > capture->first_edge_cnt)) {
/* Compensate for the overflow registered in the same IRQ */
capture->first_edge_overflows--;
}
if (unlikely(overflow && second_cnv > cnt)) {
/* Compensate for the overflow registered in the same IRQ */
second_edge_overflows--;
}
overflows = second_edge_overflows - capture->first_edge_overflows;
/* Calculate cycles, check for overflows */
if (overflows > 0) {
if (u32_mul_overflow(overflows, config->base->MOD, &cycles)) {
LOG_ERR("overflow while calculating cycles");
status = -ERANGE;
} else {
cycles -= first_cnv;
if (u32_add_overflow(cycles, second_cnv, &cycles)) {
LOG_ERR("overflow while calculating cycles");
cycles = 0;
status = -ERANGE;
}
}
} else {
cycles = second_cnv - first_cnv;
}
LOG_DBG("pair = %d, 1st ovfs = %u, 2nd ovfs = %u, ovfs = %u, 1st cnv = %u, "
"2nd cnv = %u, cycles = %u, 2nd cnt = %u, 2nd ovf = %d",
pair, capture->first_edge_overflows, second_edge_overflows, overflows, first_cnv,
second_cnv, cycles, cnt, overflow);
if (capture->pulse_capture) {
capture->callback(dev, pair, 0, cycles, status,
capture->user_data);
} else {
capture->callback(dev, pair, cycles, 0, status,
capture->user_data);
}
if (capture->param.mode == kFTM_OneShot) {
/* One-shot capture done */
FTM_DisableInterrupts(config->base, BIT(PAIR_2ND_CH(pair)));
} else if (capture->pulse_capture) {
/* Prepare for first edge of next pulse capture */
FTM_EnableInterrupts(config->base, BIT(PAIR_1ST_CH(pair)));
} else {
/* First edge of next period capture is second edge of this capture (this edge) */
capture->first_edge_cnt = cnt;
capture->first_edge_overflows = second_edge_overflows;
capture->first_edge_overflow = false;
}
}
static bool mcux_ftm_handle_overflow(const struct device *dev)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
if (FTM_GetStatusFlags(config->base) & kFTM_TimeOverflowFlag) {
data->overflows++;
FTM_ClearStatusFlags(config->base, kFTM_TimeOverflowFlag);
return true;
}
return false;
}
static void mcux_ftm_irq_handler(const struct device *dev, uint32_t chan_start, uint32_t chan_end)
{
const struct mcux_ftm_config *config = dev->config;
bool overflow;
uint32_t flags;
uint32_t irqs;
uint16_t cnt;
uint32_t ch;
flags = FTM_GetStatusFlags(config->base);
irqs = FTM_GetEnabledInterrupts(config->base);
cnt = config->base->CNT;
overflow = mcux_ftm_handle_overflow(dev);
for (ch = chan_start; ch < chan_end; ch++) {
if ((flags & BIT(ch)) && (irqs & BIT(ch))) {
if (ch & 1) {
mcux_ftm_capture_second_edge(dev, ch, cnt, overflow);
} else {
mcux_ftm_capture_first_edge(dev, ch, cnt, overflow);
}
}
}
}
#endif /* CONFIG_PWM_CAPTURE */
static int mcux_ftm_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
*cycles = data->clock_freq >> config->prescale;
return 0;
}
static int mcux_ftm_init(const struct device *dev)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
ftm_chnl_pwm_config_param_t *channel = data->channel;
ftm_config_t ftm_config;
int i;
int err;
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err != 0) {
return err;
}
if (config->channel_count > ARRAY_SIZE(data->channel)) {
LOG_ERR("Invalid channel count");
return -EINVAL;
}
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&data->clock_freq)) {
LOG_ERR("Could not get clock frequency");
return -EINVAL;
}
for (i = 0; i < config->channel_count; i++) {
channel->chnlNumber = i;
channel->level = kFTM_NoPwmSignal;
channel->dutyValue = 0;
channel->firstEdgeValue = 0;
channel++;
}
FTM_GetDefaultConfig(&ftm_config);
ftm_config.prescale = config->prescale;
FTM_Init(config->base, &ftm_config);
#ifdef CONFIG_PWM_CAPTURE
config->irq_config_func(dev);
FTM_EnableInterrupts(config->base,
kFTM_TimeOverflowInterruptEnable);
data->period_cycles = 0xFFFFU;
FTM_SetTimerPeriod(config->base, data->period_cycles);
FTM_SetSoftwareTrigger(config->base, true);
FTM_StartTimer(config->base, config->ftm_clock_source);
#endif /* CONFIG_PWM_CAPTURE */
return 0;
}
static const struct pwm_driver_api mcux_ftm_driver_api = {
.set_cycles = mcux_ftm_set_cycles,
.get_cycles_per_sec = mcux_ftm_get_cycles_per_sec,
#ifdef CONFIG_PWM_CAPTURE
.configure_capture = mcux_ftm_configure_capture,
.enable_capture = mcux_ftm_enable_capture,
.disable_capture = mcux_ftm_disable_capture,
#endif /* CONFIG_PWM_CAPTURE */
};
#define TO_FTM_PRESCALE_DIVIDE(val) _DO_CONCAT(kFTM_Prescale_Divide_, val)
#ifdef CONFIG_PWM_CAPTURE
#if IS_EQ(DT_NUM_IRQS(DT_DRV_INST(0)), 1)
static void mcux_ftm_isr(const struct device *dev)
{
const struct mcux_ftm_config *cfg = dev->config;
mcux_ftm_irq_handler(dev, 0, cfg->channel_count);
}
#define FTM_CONFIG_FUNC(n) \
static void mcux_ftm_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
mcux_ftm_isr, DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}
#else /* Multiple interrupts */
#define FTM_ISR_FUNC_NAME(suffix) _DO_CONCAT(mcux_ftm_isr_, suffix)
#define FTM_ISR_FUNC(chan_start, chan_end) \
static void mcux_ftm_isr_##chan_start##_##chan_end(const struct device *dev) \
{ \
mcux_ftm_irq_handler(dev, chan_start, chan_end + 1); \
}
#define FTM_ISR_CONFIG(node_id, prop, idx) \
do { \
IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), \
DT_IRQ_BY_IDX(node_id, idx, priority), \
FTM_ISR_FUNC_NAME(DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)), \
DEVICE_DT_GET(node_id), \
0); \
irq_enable(DT_IRQ_BY_IDX(node_id, idx, irq)); \
} while (false);
#define FTM_CONFIG_FUNC(n) \
static void mcux_ftm_config_func_##n(const struct device *dev) \
{ \
DT_INST_FOREACH_PROP_ELEM(n, interrupt_names, FTM_ISR_CONFIG) \
}
#if DT_INST_IRQ_HAS_NAME(0, overflow)
static void mcux_ftm_isr_overflow(const struct device *dev)
{
mcux_ftm_handle_overflow(dev);
}
#endif
#if DT_INST_IRQ_HAS_NAME(0, 0_1)
FTM_ISR_FUNC(0, 1)
#endif
#if DT_INST_IRQ_HAS_NAME(0, 2_3)
FTM_ISR_FUNC(2, 3)
#endif
#if DT_INST_IRQ_HAS_NAME(0, 4_5)
FTM_ISR_FUNC(4, 5)
#endif
#if DT_INST_IRQ_HAS_NAME(0, 6_7)
FTM_ISR_FUNC(6, 7)
#endif
#endif /* IS_EQ(DT_NUM_IRQS(DT_DRV_INST(0)), 1) */
#define FTM_CFG_CAPTURE_INIT(n) \
.irq_config_func = mcux_ftm_config_func_##n
#define FTM_INIT_CFG(n) FTM_DECLARE_CFG(n, FTM_CFG_CAPTURE_INIT(n))
#else /* !CONFIG_PWM_CAPTURE */
#define FTM_CONFIG_FUNC(n)
#define FTM_CFG_CAPTURE_INIT
#define FTM_INIT_CFG(n) FTM_DECLARE_CFG(n, FTM_CFG_CAPTURE_INIT)
#endif /* !CONFIG_PWM_CAPTURE */
#define FTM_DECLARE_CFG(n, CAPTURE_INIT) \
static const struct mcux_ftm_config mcux_ftm_config_##n = { \
.base = (FTM_Type *)DT_INST_REG_ADDR(n),\
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = (clock_control_subsys_t) \
DT_INST_CLOCKS_CELL(n, name), \
.ftm_clock_source = (ftm_clock_source_t)(DT_INST_ENUM_IDX(n, clock_source) + 1U), \
.prescale = TO_FTM_PRESCALE_DIVIDE(DT_INST_PROP(n, prescaler)),\
.channel_count = FSL_FEATURE_FTM_CHANNEL_COUNTn((FTM_Type *) \
DT_INST_REG_ADDR(n)), \
.mode = kFTM_EdgeAlignedPwm, \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
CAPTURE_INIT \
}
#define FTM_DEVICE(n) \
PINCTRL_DT_INST_DEFINE(n); \
static struct mcux_ftm_data mcux_ftm_data_##n; \
static const struct mcux_ftm_config mcux_ftm_config_##n; \
DEVICE_DT_INST_DEFINE(n, &mcux_ftm_init, \
NULL, &mcux_ftm_data_##n, \
&mcux_ftm_config_##n, \
POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&mcux_ftm_driver_api); \
FTM_CONFIG_FUNC(n) \
FTM_INIT_CFG(n);
DT_INST_FOREACH_STATUS_OKAY(FTM_DEVICE)
``` | /content/code_sandbox/drivers/pwm/pwm_mcux_ftm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,922 |
```unknown
config PWM_GD32
bool "GigaDevice GD32 PWM driver"
default y
depends on DT_HAS_GD_GD32_PWM_ENABLED
help
Enable the GigaDevice GD32 PWM driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.gd32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_pwmbbled
#include <errno.h>
#include <stdlib.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#ifdef CONFIG_SOC_SERIES_MEC172X
#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
#endif
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <soc.h>
LOG_MODULE_REGISTER(pwmbbled_mchp_xec, CONFIG_PWM_LOG_LEVEL);
#define XEC_PWM_BBLED_MAX_FREQ_DIV 256U
/* We will choose frequency from Device Tree */
#define XEC_PWM_BBLED_INPUT_FREQ_HI 48000000
#define XEC_PWM_BBLED_INPUT_FREQ_LO 32768
/* Hardware blink mode equation is Fpwm = Fin / (256 * (LD + 1))
* The maximum Fpwm is actually Fin / 256
* LD in [0, 4095]
*/
#define XEC_PWM_BBLED_MAX_PWM_FREQ_HI (XEC_PWM_BBLED_INPUT_FREQ_HI / \
XEC_PWM_BBLED_MAX_FREQ_DIV)
#define XEC_PWM_BBLED_MAX_PWM_FREQ_LO (XEC_PWM_BBLED_INPUT_FREQ_LO / \
XEC_PWM_BBLED_MAX_FREQ_DIV)
#define XEC_PWM_BBLED_LD_MAX 4095
#define XEC_PWM_BBLED_DC_MIN 1u /* 0 full off */
#define XEC_PWM_BBLED_DC_MAX 254u /* 255 is full on */
/* BBLED PWM mode uses the duty cycle to set the PWM frequency:
* Fpwm = Fclock / (256 * (LD + 1)) OR
* Tpwm = (256 * (LD + 1)) / Fclock
* Fclock is 48MHz or 32KHz
* LD = Delay register, LOW_DELAY field: bits[11:0]
* Pulse_ON_width = (1/Fpwm) * (duty_cycle/256) seconds
* Puse_OFF_width = (1/Fpwm) * (256 - duty_cycle) seconds
* where duty_cycle is an 8-bit value 0 to 255.
* Prescale is derived from DELAY register LOW_DELAY 12-bit field
* Duty cycle is derived from LIMITS register MINIMUM 8-bit field
*
* Fc in Hz, Tp in seconds
* Fc / Fp = 256 * (LD+1)
* Tp / Tc = 256 * (LD+1)
*
* API passes pulse period and pulse width in nanoseconds.
* BBLED PWM mode duty cycle specified by 8-bit MIN field of the LIMITS register
* MIN=0 is OFF, pin driven low
* MIN=255 is ON, pin driven high
*/
/* Same BBLED hardware block in MEC15xx and MEC172x families
* Config register
*/
#define XEC_PWM_BBLED_CFG_MSK 0x1ffffu
#define XEC_PWM_BBLED_CFG_MODE_POS 0
#define XEC_PWM_BBLED_CFG_MODE_MSK 0x3u
#define XEC_PWM_BBLED_CFG_MODE_OFF 0
#define XEC_PWM_BBLED_CFG_MODE_PWM 0x2u
#define XEC_PWM_BBLED_CFG_MODE_ALWAYS_ON 0x3u
#define XEC_PWM_BBLED_CFG_CLK_SRC_48M_POS 2
#define XEC_PWM_BBLED_CFG_EN_UPDATE_POS 6
#define XEC_PWM_BBLED_CFG_RST_PWM_POS 7
#define XEC_PWM_BBLED_CFG_WDT_RLD_POS 8
#define XEC_PWM_BBLED_CFG_WDT_RLD_MSK0 0xffu
#define XEC_PWM_BBLED_CFG_WDT_RLD_MSK 0xff00u
#define XEC_PWM_BBLED_CFG_WDT_RLD_DFLT 0x1400u
/* Limits register */
#define XEC_PWM_BBLED_LIM_MSK 0xffffu
#define XEC_PWM_BBLED_LIM_MIN_POS 0
#define XEC_PWM_BBLED_LIM_MIN_MSK 0xffu
#define XEC_PWM_BBLED_LIM_MAX_POS 8
#define XEC_PWM_BBLED_LIM_MAX_MSK 0xff00u
/* Delay register */
#define XEC_PWM_BBLED_DLY_MSK 0xffffffu
#define XEC_PWM_BBLED_DLY_LO_POS 0
#define XEC_PWM_BBLED_DLY_LO_MSK 0xfffu
#define XEC_PWM_BBLED_DLY_HI_POS 12
#define XEC_PWM_BBLED_DLY_HI_MSK 0xfff000u
/* Output delay in clocks for initial enable and enable on resume from sleep
* Clocks are either 48MHz or 32KHz selected in CONFIG register.
*/
#define XEC_PWM_BBLED_OUT_DLY_MSK 0xffu
/* DT enum values */
#define XEC_PWM_BBLED_CLKSEL_32K 0
#define XEC_PWM_BBLED_CLKSEL_AHB_48M 1
#define XEC_PWM_BBLED_CLKSEL_0 XEC_PWM_BBLED_CLKSEL_32K
#define XEC_PWM_BBLED_CLKSEL_1 XEC_PWM_BBLED_CLKSEL_AHB_48M
struct bbled_regs {
volatile uint32_t config;
volatile uint32_t limits;
volatile uint32_t delay;
volatile uint32_t update_step_size;
volatile uint32_t update_interval;
volatile uint32_t output_delay;
};
#define XEC_PWM_BBLED_CLK_SEL_48M 0
#define XEC_PWM_BBLED_CLK_SEL_32K 1
struct pwm_bbled_xec_config {
struct bbled_regs * const regs;
const struct pinctrl_dev_config *pcfg;
uint8_t girq;
uint8_t girq_pos;
uint8_t pcr_idx;
uint8_t pcr_pos;
uint8_t clk_sel;
bool enable_low_power_32K;
};
struct bbled_xec_data {
uint32_t config;
};
/* Issue: two separate registers must be updated.
* LIMITS.MIN = duty cycle = [1, 254]
* LIMITS register update takes effect immediately.
* DELAY.LO = pre-scaler = [0, 4095]
* Writing DELAY stores value in an internal holding register.
* Writing bit[6]=1 causes HW to update DELAY at the beginning of
* the next HW PWM period.
*/
static void xec_pwmbb_progam_pwm(const struct device *dev, uint32_t ld, uint32_t dc)
{
const struct pwm_bbled_xec_config * const cfg = dev->config;
struct bbled_regs * const regs = cfg->regs;
uint32_t val;
val = regs->limits & ~(XEC_PWM_BBLED_LIM_MIN_MSK);
val |= ((dc << XEC_PWM_BBLED_LIM_MIN_POS) & XEC_PWM_BBLED_LIM_MIN_MSK);
regs->limits = val;
val = regs->delay & ~(XEC_PWM_BBLED_DLY_LO_MSK);
val |= ((ld << XEC_PWM_BBLED_DLY_LO_POS) & XEC_PWM_BBLED_DLY_LO_MSK);
regs->delay = val;
/* transfer new delay value from holding register */
regs->config |= BIT(XEC_PWM_BBLED_CFG_EN_UPDATE_POS);
val = regs->config & ~(XEC_PWM_BBLED_CFG_MODE_MSK);
val |= XEC_PWM_BBLED_CFG_MODE_PWM;
regs->config = val;
}
/* API implementation: Get the clock rate (cycles per second) for a single PWM output.
* BBLED in PWM mode (same as blink mode) PWM frequency = Source Frequency / (256 * (LP + 1))
* where Source Frequency is either 48 MHz or 32768 Hz and LP is the 12-bit low delay
* field of the DELAY register. We return the maximum PWM frequency which is configured
* hardware input frequency (32K or 48M) divided by 256.
*/
static int pwm_bbled_xec_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct pwm_bbled_xec_config * const cfg = dev->config;
struct bbled_regs * const regs = cfg->regs;
if (channel > 0) {
return -EIO;
}
if (cycles) {
if (regs->config & BIT(XEC_PWM_BBLED_CFG_CLK_SRC_48M_POS)) {
*cycles = XEC_PWM_BBLED_MAX_PWM_FREQ_HI; /* 187,500 Hz */
} else {
*cycles = XEC_PWM_BBLED_MAX_PWM_FREQ_LO; /* 128 Hz */
}
}
return 0;
}
/* API PWM set cycles:
* pulse == 0 -> pin should be constant inactive level
* pulse >= period -> pin should be constant active level
* hardware PWM (blink) mode: Fpwm = Fin_actual / (LD + 1)
* Fin_actual = XEC_PWM_BBLED_MAX_PWM_FREQ_HI or XEC_PWM_BBLED_MAX_PWM_FREQ_LO.
* period cycles and pulse cycles both zero is OFF
* pulse cycles == 0 is OFF
* pulse cycles > 0 and period cycles == 0 is OFF
* otherwise
* compute duty cycle = 256 * (pulse_cycles / period_cycles).
* compute (LD + 1) = Fin_actual / Fpwm
* program LD into bits[11:0] of Delay register
* program duty cycle info bits[7:0] of Limits register
* NOTE: flags parameter is currently used for pin invert and PWM capture.
* The BBLED HW does not support pin invert or PWM capture.
* NOTE 2: Pin invert is possible by using the MCHP function invert feature
* of the GPIO pin. This property can be set using PINCTRL at build time.
*/
static int pwm_bbled_xec_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_bbled_xec_config * const cfg = dev->config;
struct bbled_regs * const regs = cfg->regs;
uint32_t dc, ld;
if (channel > 0) {
LOG_ERR("Invalid channel: %u", channel);
return -EIO;
}
if (flags) {
return -ENOTSUP;
}
LOG_DBG("period_cycles = %u pulse_cycles = %u", period_cycles, pulse_cycles);
if (pulse_cycles == 0u) {
/* drive pin to inactive state */
regs->config = (regs->config & ~XEC_PWM_BBLED_CFG_MODE_MSK)
| XEC_PWM_BBLED_CFG_MODE_OFF;
regs->limits &= ~XEC_PWM_BBLED_LIM_MIN_MSK;
regs->delay &= ~(XEC_PWM_BBLED_DLY_LO_MSK);
} else if (pulse_cycles >= period_cycles) {
/* drive pin to active state */
regs->config = (regs->config & ~XEC_PWM_BBLED_CFG_MODE_MSK)
| XEC_PWM_BBLED_CFG_MODE_ALWAYS_ON;
regs->limits &= ~XEC_PWM_BBLED_LIM_MIN_MSK;
regs->delay &= ~(XEC_PWM_BBLED_DLY_LO_MSK);
} else {
ld = period_cycles;
if (ld) {
ld--;
if (ld > XEC_PWM_BBLED_LD_MAX) {
ld = XEC_PWM_BBLED_LD_MAX;
}
}
dc = ((XEC_PWM_BBLED_DC_MAX + 1) * pulse_cycles / period_cycles);
if (dc < XEC_PWM_BBLED_DC_MIN) {
dc = XEC_PWM_BBLED_DC_MIN;
} else if (dc > XEC_PWM_BBLED_DC_MAX) {
dc = XEC_PWM_BBLED_DC_MAX;
}
LOG_DBG("Program: ld = 0x%0x dc = 0x%0x", ld, dc);
xec_pwmbb_progam_pwm(dev, ld, dc);
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int pwm_bbled_xec_pm_action(const struct device *dev, enum pm_device_action action)
{
const struct pwm_bbled_xec_config *const devcfg = dev->config;
struct bbled_regs * const regs = devcfg->regs;
struct bbled_xec_data * const data = dev->data;
int ret = 0;
/* 32K core clock is not gated by PCR in sleep, so BBLED can blink the LED even
* in sleep, if it is configured to use 32K clock. If we want to control it
* we shall use flag "enable_low_power_32K".
* This flag dont have effect on 48M clock. Since it is gated by PCR in sleep, BBLED
* will not get clock during sleep.
*/
if ((!devcfg->enable_low_power_32K) &&
(!(regs->config & BIT(XEC_PWM_BBLED_CFG_CLK_SRC_48M_POS)))) {
return ret;
}
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC BBLED pinctrl setup failed (%d)", ret);
}
/* Turn on BBLED only if it is ON before sleep */
if ((data->config & XEC_PWM_BBLED_CFG_MODE_MSK) != XEC_PWM_BBLED_CFG_MODE_OFF) {
regs->config |= (data->config & XEC_PWM_BBLED_CFG_MODE_MSK);
regs->config |= BIT(XEC_PWM_BBLED_CFG_EN_UPDATE_POS);
data->config = XEC_PWM_BBLED_CFG_MODE_OFF;
}
break;
case PM_DEVICE_ACTION_SUSPEND:
if ((regs->config & XEC_PWM_BBLED_CFG_MODE_MSK) != XEC_PWM_BBLED_CFG_MODE_OFF) {
/* Do copy first, then clear mode. */
data->config = regs->config;
regs->config &= ~(XEC_PWM_BBLED_CFG_MODE_MSK);
}
ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP);
/* pinctrl-1 does not exist. */
if (ret == -ENOENT) {
ret = 0;
}
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static const struct pwm_driver_api pwm_bbled_xec_driver_api = {
.set_cycles = pwm_bbled_xec_set_cycles,
.get_cycles_per_sec = pwm_bbled_xec_get_cycles_per_sec,
};
static int pwm_bbled_xec_init(const struct device *dev)
{
const struct pwm_bbled_xec_config * const cfg = dev->config;
struct bbled_regs * const regs = cfg->regs;
int ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC PWM-BBLED pinctrl init failed (%d)", ret);
return ret;
}
/* BBLED PWM WDT is enabled by default. Disable it and select 32KHz */
regs->config = BIT(XEC_PWM_BBLED_CFG_RST_PWM_POS);
regs->config = 0U;
if (cfg->clk_sel == XEC_PWM_BBLED_CLKSEL_AHB_48M) {
regs->config |= BIT(XEC_PWM_BBLED_CFG_CLK_SRC_48M_POS);
}
return 0;
}
#define XEC_PWM_BBLED_CLKSEL(n) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, clock_select), \
(DT_INST_ENUM_IDX(n, clock_select)), (0))
#define XEC_PWM_BBLED_CONFIG(inst) \
static struct pwm_bbled_xec_config pwm_bbled_xec_config_##inst = { \
.regs = (struct bbled_regs * const)DT_INST_REG_ADDR(inst), \
.girq = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 0)), \
.girq_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 1)), \
.pcr_idx = (uint8_t)DT_INST_PROP_BY_IDX(inst, pcrs, 0), \
.pcr_pos = (uint8_t)DT_INST_PROP_BY_IDX(inst, pcrs, 1), \
.clk_sel = UTIL_CAT(XEC_PWM_BBLED_CLKSEL_, XEC_PWM_BBLED_CLKSEL(inst)), \
.enable_low_power_32K = DT_INST_PROP(inst, enable_low_power_32k),\
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
};
#define XEC_PWM_BBLED_DEVICE_INIT(index) \
\
static struct bbled_xec_data bbled_xec_data_##index; \
\
PINCTRL_DT_INST_DEFINE(index); \
\
XEC_PWM_BBLED_CONFIG(index); \
\
PM_DEVICE_DT_INST_DEFINE(index, pwm_bbled_xec_pm_action); \
\
DEVICE_DT_INST_DEFINE(index, &pwm_bbled_xec_init, \
PM_DEVICE_DT_INST_GET(index), \
&bbled_xec_data_##index, \
&pwm_bbled_xec_config_##index, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&pwm_bbled_xec_driver_api);
DT_INST_FOREACH_STATUS_OKAY(XEC_PWM_BBLED_DEVICE_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_mchp_xec_bbled.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,827 |
```c
/*
*
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_ccu8_pwm
#include <soc.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <xmc_ccu8.h>
#include <xmc_scu.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_xmc4xxx_ccu8, CONFIG_PWM_LOG_LEVEL);
#define NUM_SLICES 4
#define NUM_CHANNELS (NUM_SLICES * 2)
#define MAX_DEAD_TIME_VALUE 255
#define MAX_SLICE_PRESCALER 15
#define MAX_DEADTIME_PRESCALER 3
#define SLICE_ADDR_FROM_MODULE(module_ptr, idx) ((uint32_t)(module_ptr) + ((idx) + 1) * 0x100)
struct pwm_xmc4xxx_ccu8_config {
XMC_CCU8_MODULE_t *ccu8;
const struct pinctrl_dev_config *pcfg;
const uint8_t slice_prescaler[NUM_SLICES];
const uint8_t slice_deadtime_prescaler[NUM_SLICES];
const uint32_t deadtime_high_ns[NUM_CHANNELS];
const uint32_t deadtime_low_ns[NUM_CHANNELS];
};
static int pwm_xmc4xxx_ccu8_init(const struct device *dev)
{
const struct pwm_xmc4xxx_ccu8_config *config = dev->config;
/* enables the CCU8 clock and ungates clock to CCU8x */
XMC_CCU8_EnableModule(config->ccu8);
XMC_CCU8_StartPrescaler(config->ccu8);
for (int i = 0; i < NUM_SLICES; i++) {
XMC_CCU8_SLICE_t *slice;
XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t deadtime_conf = {0};
XMC_CCU8_SLICE_COMPARE_CONFIG_t slice_conf = {
.prescaler_initval = config->slice_prescaler[i],
.invert_out1 = 1,
.invert_out3 = 1,
};
if (config->slice_prescaler[i] > MAX_SLICE_PRESCALER) {
LOG_ERR("Invalid slice_prescaler value %d. Range [0, 15]",
config->slice_prescaler[i]);
return -EINVAL;
}
if (config->slice_deadtime_prescaler[i] > MAX_DEADTIME_PRESCALER) {
LOG_ERR("Invalid dead time prescaler value %d. Range [0, 3]",
config->slice_deadtime_prescaler[i]);
return -EINVAL;
}
slice = (XMC_CCU8_SLICE_t *)SLICE_ADDR_FROM_MODULE(config->ccu8, i);
XMC_CCU8_SLICE_CompareInit(slice, &slice_conf);
deadtime_conf.div = config->slice_deadtime_prescaler[i];
if (config->deadtime_high_ns[2*i] > 0 || config->deadtime_low_ns[2*i] > 0) {
deadtime_conf.enable_dead_time_channel1 = 1;
}
deadtime_conf.channel1_st_path = config->deadtime_high_ns[2*i] > 0;
deadtime_conf.channel1_inv_st_path = config->deadtime_low_ns[2*i] > 0;
if (config->deadtime_high_ns[2*i + 1] > 0 || config->deadtime_low_ns[2*i + 1] > 0) {
deadtime_conf.enable_dead_time_channel2 = 1;
}
deadtime_conf.channel2_st_path = config->deadtime_high_ns[2*i + 1] > 0;
deadtime_conf.channel2_inv_st_path = config->deadtime_low_ns[2*i + 1] > 0;
XMC_CCU8_SLICE_DeadTimeInit(slice, &deadtime_conf);
}
return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
}
static int pwm_xmc4xxx_ccu8_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_xmc4xxx_ccu8_config *config = dev->config;
XMC_CCU8_SLICE_t *slice;
uint32_t high_deadtime_value = 0, low_deadtime_value = 0;
uint64_t cycles;
int slice_idx = channel / 2;
if (channel >= NUM_CHANNELS) {
return -EINVAL;
}
if (period_cycles == 0 || period_cycles > UINT16_MAX + 1 || pulse_cycles > UINT16_MAX) {
return -EINVAL;
}
slice = (XMC_CCU8_SLICE_t *)SLICE_ADDR_FROM_MODULE(config->ccu8, slice_idx);
slice->PRS = period_cycles - 1;
if (channel & 0x1) {
slice->CR2S = period_cycles - pulse_cycles;
} else {
slice->CR1S = period_cycles - pulse_cycles;
}
slice->PSL = flags & PWM_POLARITY_INVERTED;
/* set channel dead time */
cycles = XMC_SCU_CLOCK_GetCcuClockFrequency() >> config->slice_prescaler[slice_idx];
cycles >>= config->slice_deadtime_prescaler[slice_idx];
high_deadtime_value = config->deadtime_high_ns[channel] * cycles / NSEC_PER_SEC;
low_deadtime_value = config->deadtime_low_ns[channel] * cycles / NSEC_PER_SEC;
if (high_deadtime_value > MAX_DEAD_TIME_VALUE || low_deadtime_value > MAX_DEAD_TIME_VALUE) {
return -EINVAL;
}
XMC_CCU8_SLICE_SetDeadTimeValue(slice, channel & 0x1, high_deadtime_value,
low_deadtime_value);
XMC_CCU8_EnableShadowTransfer(config->ccu8, BIT(slice_idx * 4));
/* start if not already running */
XMC_CCU8_EnableClock(config->ccu8, slice_idx);
XMC_CCU8_SLICE_StartTimer(slice);
return 0;
}
static int pwm_xmc4xxx_ccu8_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
const struct pwm_xmc4xxx_ccu8_config *config = dev->config;
if (channel >= NUM_CHANNELS) {
return -EINVAL;
}
*cycles = XMC_SCU_CLOCK_GetCcuClockFrequency() >> config->slice_prescaler[channel / 2];
return 0;
}
static const struct pwm_driver_api pwm_xmc4xxx_ccu8_driver_api = {
.set_cycles = pwm_xmc4xxx_ccu8_set_cycles,
.get_cycles_per_sec = pwm_xmc4xxx_ccu8_get_cycles_per_sec,
};
#define PWM_XMC4XXX_CCU8_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
\
static const struct pwm_xmc4xxx_ccu8_config config##n = { \
.ccu8 = (CCU8_GLOBAL_TypeDef *)DT_INST_REG_ADDR(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.slice_prescaler = DT_INST_PROP(n, slice_prescaler), \
.slice_deadtime_prescaler = DT_INST_PROP(n, slice_deadtime_prescaler), \
.deadtime_high_ns = DT_INST_PROP(n, channel_deadtime_high), \
.deadtime_low_ns = DT_INST_PROP(n, channel_deadtime_low), \
}; \
\
DEVICE_DT_INST_DEFINE(n, pwm_xmc4xxx_ccu8_init, NULL, NULL, &config##n, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, &pwm_xmc4xxx_ccu8_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_XMC4XXX_CCU8_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_xmc4xxx_ccu8.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,703 |
```unknown
# Microchip XEC PWM configuration options
config PWM_XEC
bool "Microchip XEC PWM"
default y
depends on DT_HAS_MICROCHIP_XEC_PWM_ENABLED
select PINCTRL
help
Enable driver to utilize PWM on the Microchip XEC IP block.
config PWM_BBLED_XEC
bool "Microchip XEC PWM-BBLED"
default y
depends on DT_HAS_MICROCHIP_XEC_PWMBBLED_ENABLED
select PINCTRL
help
Enable driver to utilize the Microchip XEC Breathing-Blinking LED
as a PWM
``` | /content/code_sandbox/drivers/pwm/Kconfig.xec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 125 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_timer_pwm
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
#include <driverlib/gpio.h>
#include <driverlib/prcm.h>
#include <driverlib/timer.h>
#include <inc/hw_memmap.h>
#include <inc/hw_types.h>
#include <ti/drivers/Power.h>
#include <ti/drivers/power/PowerCC26XX.h>
#include <zephyr/logging/log.h>
#define LOG_MODULE_NAME pwm_cc13xx_cc26xx_timer
LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL);
/* TODO: Clock frequency can be settable via KConfig, see TOP:PRCM:GPTCLKDIV */
#define CPU_FREQ ((uint32_t)DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency))
/* GPT peripherals in 16 bit mode have maximum 24 counter bits incl. the
* prescaler. Count is set to (2^24 - 2) to allow for a glitch free 100% duty
* cycle at max. period count.
*/
#define PWM_COUNT_MAX 0xFFFFFE
#define PWM_INITIAL_PERIOD PWM_COUNT_MAX
#define PWM_INITIAL_DUTY 0U /* initially off */
struct pwm_cc13xx_cc26xx_data {
};
struct pwm_cc13xx_cc26xx_config {
const uint32_t gpt_base; /* GPT register base address */
const struct pinctrl_dev_config *pcfg;
LOG_INSTANCE_PTR_DECLARE(log);
};
static void write_value(const struct pwm_cc13xx_cc26xx_config *config, uint32_t value,
uint32_t prescale_register, uint32_t value_register)
{
/* Upper byte represents the prescaler value. */
uint8_t prescaleValue = 0xff & (value >> 16);
HWREG(config->gpt_base + prescale_register) = prescaleValue;
/* The remaining bytes represent the load / match value. */
HWREG(config->gpt_base + value_register) = value & 0xffff;
}
static int set_period_and_pulse(const struct pwm_cc13xx_cc26xx_config *config, uint32_t period,
uint32_t pulse)
{
uint32_t match_value = pulse;
if (pulse == 0U) {
TimerDisable(config->gpt_base, TIMER_B);
#ifdef CONFIG_PM
Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY);
#endif
match_value = period + 1;
}
/* Fail if period is out of range */
if ((period > PWM_COUNT_MAX) || (period == 0)) {
LOG_ERR("Period (%d) is out of range.", period);
return -EINVAL;
}
/* Compare to new period and fail if invalid */
if (period < (match_value - 1) || (match_value < 0)) {
LOG_ERR("Period (%d) is shorter than pulse (%d).", period, pulse);
return -EINVAL;
}
/* Store new period and update timer */
write_value(config, period, GPT_O_TBPR, GPT_O_TBILR);
write_value(config, match_value, GPT_O_TBPMR, GPT_O_TBMATCHR);
if (pulse > 0U) {
#ifdef CONFIG_PM
Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY);
#endif
TimerEnable(config->gpt_base, TIMER_B);
}
LOG_DBG("Period and pulse successfully set.");
return 0;
}
static int set_cycles(const struct device *dev, uint32_t channel, uint32_t period, uint32_t pulse,
pwm_flags_t flags)
{
const struct pwm_cc13xx_cc26xx_config *config = dev->config;
if (channel != 0) {
return -EIO;
}
set_period_and_pulse(config, period, pulse);
return 0;
}
static int get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles)
{
if (channel > 0) {
return -EIO;
}
if (cycles) {
*cycles = CPU_FREQ;
}
return 0;
}
static const struct pwm_driver_api pwm_driver_api = {
.set_cycles = set_cycles,
.get_cycles_per_sec = get_cycles_per_sec,
};
#ifdef CONFIG_PM
static int get_timer_inst_number(const struct pwm_cc13xx_cc26xx_config *config)
{
switch (config->gpt_base) {
case GPT0_BASE:
return 0;
case GPT1_BASE:
return 1;
case GPT2_BASE:
return 2;
case GPT3_BASE:
return 3;
default:
CODE_UNREACHABLE;
}
}
#else
static int get_timer_peripheral(const struct pwm_cc13xx_cc26xx_config *config)
{
switch (config->gpt_base) {
case GPT0_BASE:
return PRCM_PERIPH_TIMER0;
case GPT1_BASE:
return PRCM_PERIPH_TIMER1;
case GPT2_BASE:
return PRCM_PERIPH_TIMER2;
case GPT3_BASE:
return PRCM_PERIPH_TIMER3;
default:
CODE_UNREACHABLE;
}
}
#endif /* CONFIG_PM */
static int init_pwm(const struct device *dev)
{
const struct pwm_cc13xx_cc26xx_config *config = dev->config;
pinctrl_soc_pin_t pin = config->pcfg->states[0].pins[0];
int ret;
#ifdef CONFIG_PM
/* Set dependency on gpio resource to turn on power domains */
Power_setDependency(get_timer_inst_number(config));
#else
/* Enable peripheral power domain. */
PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
/* Enable GPIO peripheral. */
PRCMPeripheralRunEnable(get_timer_peripheral(config));
PRCMPeripheralSleepEnable(get_timer_peripheral(config));
PRCMPeripheralDeepSleepEnable(get_timer_peripheral(config));
/* Load PRCM settings. */
PRCMLoadSet();
while (!PRCMLoadGet()) {
continue;
}
#endif /* CONFIG_PM */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("failed to setup PWM pinctrl");
return ret;
}
/* Configures the PWM idle output level.
*
* TODO: Make PWM idle high/low configurable via custom DT PWM flag.
*/
GPIO_writeDio(pin.pin, 0);
GPIO_setOutputEnableDio(pin.pin, GPIO_OUTPUT_ENABLE);
/* Peripheral should not be accessed until power domain is on. */
while (PRCMPowerDomainsAllOn(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_ON) {
continue;
}
TimerDisable(config->gpt_base, TIMER_B);
HWREG(config->gpt_base + GPT_O_CFG) = GPT_CFG_CFG_16BIT_TIMER;
/* Stall timer when debugging.
*
* TODO: Make debug stall configurable via custom DT prop.
*/
HWREG(config->gpt_base + GPT_O_CTL) |= GPT_CTL_TBSTALL;
/* TODO: Make PWM polarity configurable via DT PWM flag. */
HWREG(config->gpt_base + GPT_O_TBMR) = GPT_TBMR_TBAMS_PWM | GPT_TBMR_TBMRSU_TOUPDATE |
GPT_TBMR_TBPWMIE_EN | GPT_TBMR_TBMR_PERIODIC;
set_period_and_pulse(config, PWM_INITIAL_PERIOD, PWM_INITIAL_DUTY);
return 0;
}
#define DT_TIMER(idx) DT_INST_PARENT(idx)
#define DT_TIMER_BASE_ADDR(idx) (DT_REG_ADDR(DT_TIMER(idx)))
#define PWM_DEVICE_INIT(idx) \
PINCTRL_DT_INST_DEFINE(idx); \
LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_PWM_LOG_LEVEL); \
static const struct pwm_cc13xx_cc26xx_config pwm_cc13xx_cc26xx_##idx##_config = { \
.gpt_base = DT_TIMER_BASE_ADDR(idx), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx)}; \
\
static struct pwm_cc13xx_cc26xx_data pwm_cc13xx_cc26xx_##idx##_data; \
\
DEVICE_DT_INST_DEFINE(idx, init_pwm, NULL, &pwm_cc13xx_cc26xx_##idx##_data, \
&pwm_cc13xx_cc26xx_##idx##_config, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, &pwm_driver_api)
DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT);
``` | /content/code_sandbox/drivers/pwm/pwm_cc13xx_cc26xx_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,859 |
```c
/*
*
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_ccu4_pwm
#include <soc.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <xmc_ccu4.h>
#include <xmc_scu.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_xmc4xxx_ccu4, CONFIG_PWM_LOG_LEVEL);
#define NUM_SLICES 4
#define NUM_CHANNELS NUM_SLICES
#define SLICE_ADDR_FROM_MODULE(module_ptr, idx) ((uint32_t)(module_ptr) + ((idx) + 1) * 0x100)
struct pwm_xmc4xxx_ccu4_config {
XMC_CCU4_MODULE_t *ccu4;
const struct pinctrl_dev_config *pcfg;
const uint8_t slice_prescaler[NUM_SLICES];
};
static int pwm_xmc4xxx_ccu4_init(const struct device *dev)
{
const struct pwm_xmc4xxx_ccu4_config *config = dev->config;
/* enables the CCU4 clock and ungates clock to CCU4x */
XMC_CCU4_EnableModule(config->ccu4);
XMC_CCU4_StartPrescaler(config->ccu4);
for (int i = 0; i < NUM_SLICES; i++) {
XMC_CCU4_SLICE_t *slice;
XMC_CCU4_SLICE_COMPARE_CONFIG_t slice_conf = {
.prescaler_initval = config->slice_prescaler[i]
};
slice = (XMC_CCU4_SLICE_t *)SLICE_ADDR_FROM_MODULE(config->ccu4, i);
XMC_CCU4_SLICE_CompareInit(slice, &slice_conf);
}
return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
}
static int pwm_xmc4xxx_ccu4_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_xmc4xxx_ccu4_config *config = dev->config;
XMC_CCU4_SLICE_t *slice;
int slice_idx = channel;
if (channel >= NUM_CHANNELS) {
return -EINVAL;
}
if (period_cycles == 0 || period_cycles > UINT16_MAX + 1 || pulse_cycles > UINT16_MAX) {
return -EINVAL;
}
slice = (XMC_CCU4_SLICE_t *)SLICE_ADDR_FROM_MODULE(config->ccu4, slice_idx);
slice->PRS = period_cycles - 1;
slice->CRS = period_cycles - pulse_cycles;
slice->PSL = flags & PWM_POLARITY_INVERTED;
XMC_CCU4_EnableShadowTransfer(config->ccu4, BIT(slice_idx * 4));
/* start if not already running */
XMC_CCU4_EnableClock(config->ccu4, slice_idx);
XMC_CCU4_SLICE_StartTimer(slice);
return 0;
}
static int pwm_xmc4xxx_ccu4_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
const struct pwm_xmc4xxx_ccu4_config *config = dev->config;
int slice_idx = channel;
if (channel >= NUM_SLICES) {
return -EINVAL;
}
*cycles = XMC_SCU_CLOCK_GetCcuClockFrequency() >> config->slice_prescaler[slice_idx];
return 0;
}
static const struct pwm_driver_api pwm_xmc4xxx_ccu4_driver_api = {
.set_cycles = pwm_xmc4xxx_ccu4_set_cycles,
.get_cycles_per_sec = pwm_xmc4xxx_ccu4_get_cycles_per_sec,
};
#define PWM_XMC4XXX_CCU4_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
\
static const struct pwm_xmc4xxx_ccu4_config config##n = { \
.ccu4 = (CCU4_GLOBAL_TypeDef *)DT_INST_REG_ADDR(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.slice_prescaler = DT_INST_PROP(n, slice_prescaler)}; \
\
DEVICE_DT_INST_DEFINE(n, pwm_xmc4xxx_ccu4_init, NULL, NULL, &config##n, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, &pwm_xmc4xxx_ccu4_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_XMC4XXX_CCU4_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_xmc4xxx_ccu4.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 978 |
```c
/*
*
*/
#define DT_DRV_COMPAT maxim_max31790_pwm
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/mfd/max31790.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pwm/max31790.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_max31790, CONFIG_PWM_LOG_LEVEL);
struct max31790_pwm_config {
struct i2c_dt_spec i2c;
};
struct max31790_pwm_data {
struct k_mutex lock;
};
static void max31790_set_fandynamics_speedrange(uint8_t *destination, uint8_t value)
{
uint8_t length = MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH;
uint8_t pos = MAX37190_FANXDYNAMICS_SPEEDRANGE_POS;
*destination &= ~GENMASK(pos + length - 1, pos);
*destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value);
}
static void max31790_set_fandynamics_pwmrateofchange(uint8_t *destination, uint8_t value)
{
uint8_t length = MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_LENGTH;
uint8_t pos = MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_POS;
*destination &= ~GENMASK(pos + length - 1, pos);
*destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value);
}
static void max31790_set_pwmfrequency(uint8_t *destination, uint8_t channel, uint8_t value)
{
uint8_t length = MAX37190_PWMFREQUENCY_PWM_LENGTH;
uint8_t pos = (channel / 3) * 4;
*destination &= ~GENMASK(pos + length - 1, pos);
*destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value);
}
static uint8_t max31790_get_pwmfrequency(uint8_t value, uint8_t channel)
{
uint8_t length = MAX37190_PWMFREQUENCY_PWM_LENGTH;
uint8_t pos = (channel / 3) * 4;
return FIELD_GET(GENMASK(pos + length - 1, pos), value);
}
static void max31790_set_fanconfiguration_spinup(uint8_t *destination, uint8_t value)
{
uint8_t length = MAX37190_FANXCONFIGURATION_SPINUP_LENGTH;
uint8_t pos = MAX37190_FANXCONFIGURATION_SPINUP_POS;
*destination &= ~GENMASK(pos + length - 1, pos);
*destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value);
}
static bool max31790_convert_pwm_frequency_into_hz(uint16_t *result, uint8_t pwm_frequency)
{
switch (pwm_frequency) {
case 0:
*result = 25;
return true;
case 1:
*result = 30;
return true;
case 2:
*result = 35;
return true;
case 3:
*result = 100;
return true;
case 4:
*result = 125;
return true;
case 5:
*result = 150; /* actually 149.7, according to the datasheet */
return true;
case 6:
*result = 1250;
return true;
case 7:
*result = 1470;
return true;
case 8:
*result = 3570;
return true;
case 9:
*result = 5000;
return true;
case 10:
*result = 12500;
return true;
case 11:
*result = 25000;
return true;
default:
LOG_ERR("invalid value %i for PWM frequency register", pwm_frequency);
return false;
}
}
static bool max31790_convert_pwm_frequency_into_register(uint8_t *result, uint32_t pwm_frequency)
{
switch (pwm_frequency) {
case 25:
*result = 0;
return true;
case 30:
*result = 1;
return true;
case 35:
*result = 2;
return true;
case 100:
*result = 3;
return true;
case 125:
*result = 4;
return true;
case 150: /* actually 149.7, according to the datasheet */
*result = 5;
return true;
case 1250:
*result = 6;
return true;
case 1470:
*result = 7;
return true;
case 3570:
*result = 8;
return true;
case 5000:
*result = 9;
return true;
case 12500:
*result = 10;
return true;
case 25000:
*result = 11;
return true;
default:
LOG_ERR("invalid value %i for PWM frequency in Hz", pwm_frequency);
return false;
}
}
static int max31790_set_cycles_internal(const struct device *dev, uint32_t channel,
uint32_t period_count, uint32_t pulse_count,
pwm_flags_t flags)
{
const struct max31790_pwm_config *config = dev->config;
int result;
uint8_t pwm_frequency_channel_value;
uint8_t value_pwm_frequency;
uint8_t value_fan_configuration;
uint8_t value_fan_dynamics;
uint8_t value_speed_range = MAX31790_FLAG_SPEED_RANGE_GET(flags);
uint8_t value_pwm_rate_of_change = MAX31790_FLAG_PWM_RATE_OF_CHANGE_GET(flags);
uint8_t buffer[3];
if (!max31790_convert_pwm_frequency_into_register(&pwm_frequency_channel_value,
period_count)) {
return -EINVAL;
}
result = i2c_reg_read_byte_dt(&config->i2c, MAX37190_REGISTER_PWMFREQUENCY,
&value_pwm_frequency);
if (result != 0) {
return result;
}
max31790_set_pwmfrequency(&value_pwm_frequency, channel, pwm_frequency_channel_value);
result = i2c_reg_write_byte_dt(&config->i2c, MAX37190_REGISTER_PWMFREQUENCY,
value_pwm_frequency);
if (result != 0) {
return result;
}
value_fan_configuration = 0;
value_fan_dynamics = 0;
if (flags & PWM_MAX31790_FLAG_SPIN_UP) {
max31790_set_fanconfiguration_spinup(&value_fan_configuration, 2);
} else {
max31790_set_fanconfiguration_spinup(&value_fan_configuration, 0);
}
value_fan_configuration &= ~MAX37190_FANXCONFIGURATION_MONITOR_BIT;
value_fan_configuration &= ~MAX37190_FANXCONFIGURATION_LOCKEDROTOR_BIT;
value_fan_configuration &= ~MAX37190_FANXCONFIGURATION_LOCKEDROTORPOLARITY_BIT;
value_fan_configuration &= ~MAX37190_FANXCONFIGURATION_TACH_BIT;
value_fan_configuration |= MAX37190_FANXCONFIGURATION_TACHINPUTENABLED_BIT;
max31790_set_fandynamics_speedrange(&value_fan_dynamics, value_speed_range);
max31790_set_fandynamics_pwmrateofchange(&value_fan_dynamics, value_pwm_rate_of_change);
value_fan_dynamics |= MAX37190_FANXDYNAMICS_ASYMMETRICRATEOFCHANGE_BIT;
if ((flags & PWM_MAX31790_FLAG_RPM_MODE) == 0) {
LOG_DBG("PWM mode");
uint16_t tach_target_count = MAX31790_TACHTARGETCOUNT_MAXIMUM;
value_fan_configuration &= ~MAX37190_FANXCONFIGURATION_MODE_BIT;
buffer[0] = MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel);
sys_put_be16(tach_target_count << 5, buffer + 1);
result = i2c_write_dt(&config->i2c, buffer, sizeof(buffer));
} else {
LOG_DBG("RPM mode");
value_fan_configuration |= MAX37190_FANXCONFIGURATION_MODE_BIT;
buffer[0] = MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel);
sys_put_be16(pulse_count << 5, buffer + 1);
result = i2c_write_dt(&config->i2c, buffer, sizeof(buffer));
}
if (result != 0) {
return result;
}
result = i2c_reg_write_byte_dt(&config->i2c, MAX37190_REGISTER_FANCONFIGURATION(channel),
value_fan_configuration);
if (result != 0) {
return result;
}
result = i2c_reg_write_byte_dt(&config->i2c, MAX31790_REGISTER_FANDYNAMICS(channel),
value_fan_dynamics);
if (result != 0) {
return result;
}
if ((flags & PWM_MAX31790_FLAG_RPM_MODE) == 0) {
uint16_t pwm_target_duty_cycle =
pulse_count * MAX31790_PWMTARGETDUTYCYCLE_MAXIMUM / period_count;
buffer[0] = MAX31790_REGISTER_PWMOUTTARGETDUTYCYCLEMSB(channel);
sys_put_be16(pwm_target_duty_cycle << 7, buffer + 1);
result = i2c_write_dt(&config->i2c, buffer, sizeof(buffer));
if (result != 0) {
return result;
}
}
return 0;
}
static int max31790_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_count,
uint32_t pulse_count, pwm_flags_t flags)
{
struct max31790_pwm_data *data = dev->data;
int result;
LOG_DBG("set period %i with pulse %i for channel %i and flags 0x%04X", period_count,
pulse_count, channel, flags);
if (channel > MAX31790_CHANNEL_COUNT) {
LOG_ERR("invalid channel number %i", channel);
return -EINVAL;
}
if (period_count == 0) {
LOG_ERR("period count must be > 0");
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
result = max31790_set_cycles_internal(dev, channel, period_count, pulse_count, flags);
k_mutex_unlock(&data->lock);
return result;
}
static int max31790_get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles)
{
const struct max31790_pwm_config *config = dev->config;
struct max31790_pwm_data *data = dev->data;
int result;
bool success;
uint8_t pwm_frequency_register;
uint8_t pwm_frequency = 1;
uint16_t pwm_frequency_in_hz;
if (channel > MAX31790_CHANNEL_COUNT) {
LOG_ERR("invalid channel number %i", channel);
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
result = i2c_reg_read_byte_dt(&config->i2c, MAX37190_REGISTER_GLOBALCONFIGURATION,
&pwm_frequency_register);
if (result != 0) {
k_mutex_unlock(&data->lock);
return result;
}
pwm_frequency = max31790_get_pwmfrequency(pwm_frequency_register, channel);
success = max31790_convert_pwm_frequency_into_hz(&pwm_frequency_in_hz, pwm_frequency);
if (!success) {
k_mutex_unlock(&data->lock);
return -EINVAL;
}
*cycles = pwm_frequency_in_hz;
k_mutex_unlock(&data->lock);
return 0;
}
static const struct pwm_driver_api max31790_pwm_api = {
.set_cycles = max31790_set_cycles,
.get_cycles_per_sec = max31790_get_cycles_per_sec,
};
static int max31790_pwm_init(const struct device *dev)
{
const struct max31790_pwm_config *config = dev->config;
struct max31790_pwm_data *data = dev->data;
k_mutex_init(&data->lock);
if (!i2c_is_ready_dt(&config->i2c)) {
LOG_ERR("I2C device not ready");
return -ENODEV;
}
return 0;
}
#define MAX31790_PWM_INIT(inst) \
static const struct max31790_pwm_config max31790_pwm_##inst##_config = { \
.i2c = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \
}; \
\
static struct max31790_pwm_data max31790_pwm_##inst##_data; \
\
DEVICE_DT_INST_DEFINE(inst, max31790_pwm_init, NULL, &max31790_pwm_##inst##_data, \
&max31790_pwm_##inst##_config, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, &max31790_pwm_api);
DT_INST_FOREACH_STATUS_OKAY(MAX31790_PWM_INIT);
``` | /content/code_sandbox/drivers/pwm/pwm_max31790.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,819 |
```unknown
# NPCX PWM driver configuration options
config PWM_NPCX
bool "Nuvoton NPCX embedded controller (EC) PWM driver"
default y
depends on DT_HAS_NUVOTON_NPCX_PWM_ENABLED
help
This option enables the PWM driver for NPCX family of
processors.
Say y if you wish to use pwm ports on NPCX MCU.
``` | /content/code_sandbox/drivers/pwm/Kconfig.npcx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
# MCUX PWT PWM
config PWM_MCUX_PWT
bool "MCUX PWT PWM capture driver"
default y
depends on DT_HAS_NXP_KINETIS_PWT_ENABLED
depends on CLOCK_CONTROL && PWM_CAPTURE
select PINCTRL
help
Enable the MCUX Pulse Width Timer (PWT) PWM capture driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.mcux_pwt | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
config PWM_NRFX
bool "nRF PWM nrfx driver"
default y
depends on DT_HAS_NORDIC_NRF_PWM_ENABLED
select NRFX_PWM0 if HAS_HW_NRF_PWM0
select NRFX_PWM1 if HAS_HW_NRF_PWM1
select NRFX_PWM2 if HAS_HW_NRF_PWM2
select NRFX_PWM3 if HAS_HW_NRF_PWM3
select NRFX_PWM20 if HAS_HW_NRF_PWM20
select NRFX_PWM21 if HAS_HW_NRF_PWM21
select NRFX_PWM22 if HAS_HW_NRF_PWM22
select NRFX_PWM120 if HAS_HW_NRF_PWM120
select NRFX_PWM130 if HAS_HW_NRF_PWM130
select NRFX_PWM131 if HAS_HW_NRF_PWM131
select NRFX_PWM132 if HAS_HW_NRF_PWM132
select NRFX_PWM133 if HAS_HW_NRF_PWM133
select PINCTRL
help
Enable support for nrfx Hardware PWM driver for nRF52 MCU series.
``` | /content/code_sandbox/drivers/pwm/Kconfig.nrfx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 212 |
```c
/*
*
*/
#define DT_DRV_COMPAT ite_it8xxx2_pwm
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pwm/it8xxx2_pwm.h>
#include <errno.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <soc_dt.h>
#include <stdlib.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_ite_it8xxx2, CONFIG_PWM_LOG_LEVEL);
#define PWM_CTRX_MIN 100
#define PWM_FREQ EC_FREQ
#define PCSSG_MASK 0x3
struct pwm_it8xxx2_cfg {
/* PWM channel duty cycle register */
uintptr_t reg_dcr;
/* PWM channel clock source selection register */
uintptr_t reg_pcssg;
/* PWM channel clock source gating register */
uintptr_t reg_pcsgr;
/* PWM channel output polarity register */
uintptr_t reg_pwmpol;
/* PWM channel */
int channel;
/* PWM prescaler control register base */
struct pwm_it8xxx2_regs *base;
/* Select PWM prescaler that output to PWM channel */
int prs_sel;
/* PWM alternate configuration */
const struct pinctrl_dev_config *pcfg;
};
struct pwm_it8xxx2_data {
uint32_t ctr;
uint32_t cxcprs;
uint32_t target_freq_prev;
};
static void pwm_enable(const struct device *dev, int enabled)
{
const struct pwm_it8xxx2_cfg *config = dev->config;
volatile uint8_t *reg_pcsgr = (uint8_t *)config->reg_pcsgr;
int ch = config->channel;
if (enabled) {
/* PWM channel clock source not gating */
*reg_pcsgr &= ~BIT(ch);
} else {
/* PWM channel clock source gating */
*reg_pcsgr |= BIT(ch);
}
}
static int pwm_it8xxx2_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
ARG_UNUSED(channel);
/*
* There are three ways to call pwm_it8xxx2_set_cycles() from pwm api:
* 1) pwm_set_cycles_usec() -> pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles()
* target_freq = pwm_clk_src / period_cycles
* = cycles / (period * cycles / USEC_PER_SEC)
* = USEC_PER_SEC / period
* 2) pwm_set_cycles_nsec() -> pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles()
* target_freq = pwm_clk_src / period_cycles
* = cycles / (period * cycles / NSEC_PER_SEC)
* = NSEC_PER_SEC / period
* 3) pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles()
* target_freq = pwm_clk_src / period_cycles
* = cycles / period
*
* If we need to pwm output in EC power saving mode, then we will switch
* the prescaler clock source (cycles) from 8MHz to 32.768kHz. In order
* to get the same target_freq in the 3) case, we always return PWM_FREQ.
*/
*cycles = (uint64_t) PWM_FREQ;
return 0;
}
static int pwm_it8xxx2_set_cycles(const struct device *dev,
uint32_t channel, uint32_t period_cycles,
uint32_t pulse_cycles, pwm_flags_t flags)
{
const struct pwm_it8xxx2_cfg *config = dev->config;
struct pwm_it8xxx2_regs *const inst = config->base;
struct pwm_it8xxx2_data *data = dev->data;
volatile uint8_t *reg_dcr = (uint8_t *)config->reg_dcr;
volatile uint8_t *reg_pwmpol = (uint8_t *)config->reg_pwmpol;
int ch = config->channel;
int prs_sel = config->prs_sel;
uint32_t actual_freq = 0xffffffff, target_freq, deviation;
uint64_t pwm_clk_src;
/* Select PWM inverted polarity (ex. active-low pulse) */
if (flags & PWM_POLARITY_INVERTED) {
*reg_pwmpol |= BIT(ch);
} else {
*reg_pwmpol &= ~BIT(ch);
}
/* Enable PWM output open-drain */
if (flags & PWM_IT8XXX2_OPEN_DRAIN) {
inst->PWMODENR |= BIT(ch);
}
/* If pulse cycles is 0, set duty cycle 0 and enable pwm channel */
if (pulse_cycles == 0) {
*reg_dcr = 0;
pwm_enable(dev, 1);
return 0;
}
pwm_it8xxx2_get_cycles_per_sec(dev, channel, &pwm_clk_src);
target_freq = ((uint32_t) pwm_clk_src) / period_cycles;
/*
* Support PWM output frequency:
* 1) 8MHz clock source: 1Hz <= target_freq <= 79207Hz
* 2) 32.768KHz clock source: 1Hz <= target_freq <= 324Hz
* NOTE: PWM output signal maximum supported frequency comes from
* [8MHz or 32.768KHz] / 1 / (PWM_CTRX_MIN + 1).
* PWM output signal minimum supported frequency comes from
* [8MHz or 32.768KHz] / 65536 / 256, the minimum integer is 1.
*/
if (target_freq < 1) {
LOG_ERR("PWM output frequency is < 1 !");
return -EINVAL;
}
deviation = (target_freq / 100) + 1;
/*
* Default clock source setting is 8MHz, when ITE chip is in power
* saving mode, clock source 8MHz will be gated (32.768KHz won't).
* So if we still need pwm output in mode, then we should set frequency
* <=324Hz in board dts. Now change prescaler clock source from 8MHz to
* 32.768KHz to support pwm output in mode.
*/
if (target_freq <= 324) {
if (inst->PCFSR & BIT(prs_sel)) {
inst->PCFSR &= ~BIT(prs_sel);
}
pwm_clk_src = (uint64_t) 32768;
}
/*
* PWM output signal frequency is
* pwm_clk_src / ((CxCPRS[15:0] + 1) * (CTRx[7:0] + 1))
* NOTE: 1) define CTR minimum is 100 for more precisely when
* calculate DCR
* 2) CxCPRS[15:0] value 0001h results in a divisor 2
* CxCPRS[15:0] value FFFFh results in a divisor 65536
* CTRx[7:0] value 00h results in a divisor 1
* CTRx[7:0] value FFh results in a divisor 256
*/
if (target_freq != data->target_freq_prev) {
uint32_t ctr, cxcprs;
for (ctr = 0xFF; ctr >= PWM_CTRX_MIN; ctr--) {
cxcprs = (((uint32_t) pwm_clk_src) / (ctr + 1) / target_freq);
/*
* Make sure cxcprs isn't zero, or we will have
* divide-by-zero on calculating actual_freq.
*/
if (cxcprs != 0) {
actual_freq = ((uint32_t) pwm_clk_src) / (ctr + 1) / cxcprs;
if (abs(actual_freq - target_freq) < deviation) {
/* CxCPRS[15:0] = cxcprs - 1 */
cxcprs--;
break;
}
}
}
if (cxcprs > UINT16_MAX) {
LOG_ERR("PWM prescaler CxCPRS only support 2 bytes !");
return -EINVAL;
}
/* Store ctr and cxcprs with successful frequency change */
data->ctr = ctr;
data->cxcprs = cxcprs;
}
/* Set PWM prescaler clock divide and cycle time register */
if (prs_sel == PWM_PRESCALER_C4) {
inst->C4CPRS = data->cxcprs & 0xFF;
inst->C4MCPRS = (data->cxcprs >> 8) & 0xFF;
inst->CTR1 = data->ctr;
} else if (prs_sel == PWM_PRESCALER_C6) {
inst->C6CPRS = data->cxcprs & 0xFF;
inst->C6MCPRS = (data->cxcprs >> 8) & 0xFF;
inst->CTR2 = data->ctr;
} else if (prs_sel == PWM_PRESCALER_C7) {
inst->C7CPRS = data->cxcprs & 0xFF;
inst->C7MCPRS = (data->cxcprs >> 8) & 0xFF;
inst->CTR3 = data->ctr;
}
/* Set PWM channel duty cycle register */
*reg_dcr = (data->ctr * pulse_cycles) / period_cycles;
/* PWM channel clock source not gating */
pwm_enable(dev, 1);
/* Store the frequency to be compared */
data->target_freq_prev = target_freq;
LOG_DBG("clock source freq %d, target freq %d",
(uint32_t) pwm_clk_src, target_freq);
return 0;
}
static int pwm_it8xxx2_init(const struct device *dev)
{
const struct pwm_it8xxx2_cfg *config = dev->config;
struct pwm_it8xxx2_regs *const inst = config->base;
volatile uint8_t *reg_pcssg = (uint8_t *)config->reg_pcssg;
int ch = config->channel;
int prs_sel = config->prs_sel;
int pcssg_shift;
int pcssg_mask;
int status;
/* PWM channel clock source gating before configuring */
pwm_enable(dev, 0);
/* Select clock source 8MHz for prescaler */
inst->PCFSR |= BIT(prs_sel);
/* Bit shift and mask of prescaler clock source select group register */
pcssg_shift = (ch % 4) * 2;
pcssg_mask = (prs_sel & PCSSG_MASK) << pcssg_shift;
/* Select which prescaler output to PWM channel */
*reg_pcssg &= ~(PCSSG_MASK << pcssg_shift);
*reg_pcssg |= pcssg_mask;
/*
* The cycle timer1 of it8320 later series was enhanced from
* 8bits to 10bits resolution, and others are still 8bit resolution.
* Because the cycle timer1 high byte default value is not zero,
* we clear cycle timer1 high byte at init and use it as 8-bit
* resolution like others.
*/
inst->CTR1M = 0;
/* Enable PWMs clock counter */
inst->ZTIER |= IT8XXX2_PWM_PCCE;
/* Set alternate mode of PWM pin */
status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (status < 0) {
LOG_ERR("Failed to configure PWM pins");
return status;
}
return 0;
}
static const struct pwm_driver_api pwm_it8xxx2_api = {
.set_cycles = pwm_it8xxx2_set_cycles,
.get_cycles_per_sec = pwm_it8xxx2_get_cycles_per_sec,
};
/* Device Instance */
#define PWM_IT8XXX2_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
\
static const struct pwm_it8xxx2_cfg pwm_it8xxx2_cfg_##inst = { \
.reg_dcr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
.reg_pcssg = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
.reg_pcsgr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
.reg_pwmpol = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
.channel = DT_PROP(DT_INST(inst, ite_it8xxx2_pwm), channel), \
.base = (struct pwm_it8xxx2_regs *) DT_REG_ADDR(DT_NODELABEL(prs)), \
.prs_sel = DT_PROP(DT_INST(inst, ite_it8xxx2_pwm), prescaler_cx), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
\
static struct pwm_it8xxx2_data pwm_it8xxx2_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, \
&pwm_it8xxx2_init, \
NULL, \
&pwm_it8xxx2_data_##inst, \
&pwm_it8xxx2_cfg_##inst, \
PRE_KERNEL_1, \
CONFIG_PWM_INIT_PRIORITY, \
&pwm_it8xxx2_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_IT8XXX2_INIT)
``` | /content/code_sandbox/drivers/pwm/pwm_ite_it8xxx2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,941 |
```c
/*
* (c) Meta Platforms, Inc. and affiliates.
*
*/
#define DT_DRV_COMPAT nxp_ctimer_pwm
#include <errno.h>
#include <fsl_ctimer.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_ctimer, CONFIG_PWM_LOG_LEVEL);
#define CHANNEL_COUNT kCTIMER_Match_3 + 1
enum pwm_ctimer_channel_role {
PWM_CTIMER_CHANNEL_ROLE_NONE = 0,
PWM_CTIMER_CHANNEL_ROLE_PULSE,
PWM_CTIMER_CHANNEL_ROLE_PERIOD,
};
struct pwm_ctimer_channel_state {
enum pwm_ctimer_channel_role role;
uint32_t cycles;
};
struct pwm_mcux_ctimer_data {
struct pwm_ctimer_channel_state channel_states[CHANNEL_COUNT];
ctimer_match_t current_period_channel;
bool is_period_channel_set;
uint32_t num_active_pulse_chans;
};
struct pwm_mcux_ctimer_config {
CTIMER_Type *base;
uint32_t prescale;
uint32_t period_channel;
const struct device *clock_control;
clock_control_subsys_t clock_id;
const struct pinctrl_dev_config *pincfg;
};
/*
* All pwm signals generated from the same ctimer must have same period. To avoid this, we check
* if the new parameters will NOT change the period for a ctimer with active pulse channels
*/
static bool mcux_ctimer_pwm_is_period_valid(struct pwm_mcux_ctimer_data *data,
uint32_t new_pulse_channel, uint32_t new_period_cycles,
uint32_t current_period_channel)
{
/* if we aren't changing the period, we're ok */
if (data->channel_states[current_period_channel].cycles == new_period_cycles) {
return true;
}
/*
* if we are changing it but there aren't any pulse channels that depend on it, then we're
* ok too
*/
if (data->num_active_pulse_chans == 0) {
return true;
}
if (data->num_active_pulse_chans > 1) {
return false;
}
/*
* there is exactly one pulse channel that depends on existing period and its not the
* one we're changing now
*/
if (data->channel_states[new_pulse_channel].role != PWM_CTIMER_CHANNEL_ROLE_PULSE) {
return false;
}
return true;
}
/*
* Each ctimer channel can either be used as a pulse or period channel. Each channel has a counter.
* The duty cycle is counted by the pulse channel. When the period channel counts down, it resets
* the pulse channel (and all counters in the ctimer instance). The pwm api does not permit us to
* specify a period channel (only pulse channel). So we need to figure out an acceptable period
* channel in the driver (if that's even possible)
*/
static int mcux_ctimer_pwm_select_period_channel(struct pwm_mcux_ctimer_data *data,
uint32_t new_pulse_channel,
uint32_t new_period_cycles,
uint32_t *ret_period_channel)
{
if (data->is_period_channel_set) {
if (!mcux_ctimer_pwm_is_period_valid(data, new_pulse_channel, new_period_cycles,
data->current_period_channel)) {
LOG_ERR("Cannot set channel %u to %u as period channel",
*ret_period_channel, new_period_cycles);
return -EINVAL;
}
*ret_period_channel = data->current_period_channel;
if (new_pulse_channel != *ret_period_channel) {
/* the existing period channel will not conflict with new pulse_channel */
return 0;
}
}
/* we need to find an unused channel to use as period_channel */
*ret_period_channel = new_pulse_channel + 1;
*ret_period_channel %= CHANNEL_COUNT;
while (data->channel_states[*ret_period_channel].role != PWM_CTIMER_CHANNEL_ROLE_NONE) {
if (new_pulse_channel == *ret_period_channel) {
LOG_ERR("no available channel for period counter");
return -EBUSY;
}
(*ret_period_channel)++;
*ret_period_channel %= CHANNEL_COUNT;
}
return 0;
}
static void mcux_ctimer_pwm_update_state(struct pwm_mcux_ctimer_data *data, uint32_t pulse_channel,
uint32_t pulse_cycles, uint32_t period_channel,
uint32_t period_cycles)
{
if (data->channel_states[pulse_channel].role != PWM_CTIMER_CHANNEL_ROLE_PULSE) {
data->num_active_pulse_chans++;
}
data->channel_states[pulse_channel].role = PWM_CTIMER_CHANNEL_ROLE_PULSE;
data->channel_states[pulse_channel].cycles = pulse_cycles;
data->is_period_channel_set = true;
data->current_period_channel = period_channel;
data->channel_states[period_channel].role = PWM_CTIMER_CHANNEL_ROLE_PERIOD;
data->channel_states[period_channel].cycles = period_cycles;
}
static int mcux_ctimer_pwm_set_cycles(const struct device *dev, uint32_t pulse_channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_mcux_ctimer_config *config = dev->config;
struct pwm_mcux_ctimer_data *data = dev->data;
uint32_t period_channel = data->current_period_channel;
int ret = 0;
status_t status;
if (pulse_channel >= CHANNEL_COUNT) {
LOG_ERR("Invalid channel %u. muse be less than %u", pulse_channel, CHANNEL_COUNT);
return -EINVAL;
}
if (period_cycles == 0) {
LOG_ERR("Channel can not be set to zero");
return -ENOTSUP;
}
ret = mcux_ctimer_pwm_select_period_channel(data, pulse_channel, period_cycles,
&period_channel);
if (ret != 0) {
LOG_ERR("could not select valid period channel. ret=%d", ret);
return ret;
}
if (flags & PWM_POLARITY_INVERTED) {
if (pulse_cycles == 0) {
/* make pulse cycles greater than period so event never occurs */
pulse_cycles = period_cycles + 1;
} else {
pulse_cycles = period_cycles - pulse_cycles;
}
}
status = CTIMER_SetupPwmPeriod(config->base, period_channel, pulse_channel, period_cycles,
pulse_cycles, false);
if (kStatus_Success != status) {
LOG_ERR("failed setup pwm period. status=%d", status);
return -EIO;
}
mcux_ctimer_pwm_update_state(data, pulse_channel, pulse_cycles, period_channel,
period_cycles);
CTIMER_StartTimer(config->base);
return 0;
}
static int mcux_ctimer_pwm_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
const struct pwm_mcux_ctimer_config *config = dev->config;
int err = 0;
/* clean up upper word of return parameter */
*cycles &= 0xFFFFFFFF;
err = clock_control_get_rate(config->clock_control, config->clock_id, (uint32_t *)cycles);
if (err != 0) {
LOG_ERR("could not get clock rate");
return err;
}
if (config->prescale > 0) {
*cycles /= config->prescale;
}
return err;
}
static int mcux_ctimer_pwm_init(const struct device *dev)
{
const struct pwm_mcux_ctimer_config *config = dev->config;
ctimer_config_t pwm_config;
int err;
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
if (config->period_channel >= CHANNEL_COUNT) {
LOG_ERR("invalid period_channel: %d. must be less than %d", config->period_channel,
CHANNEL_COUNT);
return -EINVAL;
}
CTIMER_GetDefaultConfig(&pwm_config);
pwm_config.prescale = config->prescale;
CTIMER_Init(config->base, &pwm_config);
return 0;
}
static const struct pwm_driver_api pwm_mcux_ctimer_driver_api = {
.set_cycles = mcux_ctimer_pwm_set_cycles,
.get_cycles_per_sec = mcux_ctimer_pwm_get_cycles_per_sec,
};
#define PWM_MCUX_CTIMER_PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n);
#define PWM_MCUX_CTIMER_PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
#define PWM_MCUX_CTIMER_DEVICE_INIT_MCUX(n) \
static struct pwm_mcux_ctimer_data pwm_mcux_ctimer_data_##n = { \
.channel_states = \
{ \
[kCTIMER_Match_0] = {.role = PWM_CTIMER_CHANNEL_ROLE_NONE, \
.cycles = 0}, \
[kCTIMER_Match_1] = {.role = PWM_CTIMER_CHANNEL_ROLE_NONE, \
.cycles = 0}, \
[kCTIMER_Match_2] = {.role = PWM_CTIMER_CHANNEL_ROLE_NONE, \
.cycles = 0}, \
[kCTIMER_Match_3] = {.role = PWM_CTIMER_CHANNEL_ROLE_NONE, \
.cycles = 0}, \
}, \
.current_period_channel = kCTIMER_Match_0, \
.is_period_channel_set = false, \
}; \
PWM_MCUX_CTIMER_PINCTRL_DEFINE(n) \
static const struct pwm_mcux_ctimer_config pwm_mcux_ctimer_config_##n = { \
.base = (CTIMER_Type *)DT_INST_REG_ADDR(n), \
.prescale = DT_INST_PROP(n, prescaler), \
.clock_control = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_id = (clock_control_subsys_t)(DT_INST_CLOCKS_CELL(n, name)), \
PWM_MCUX_CTIMER_PINCTRL_INIT(n)}; \
\
DEVICE_DT_INST_DEFINE(n, mcux_ctimer_pwm_init, NULL, &pwm_mcux_ctimer_data_##n, \
&pwm_mcux_ctimer_config_##n, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &pwm_mcux_ctimer_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_MCUX_CTIMER_DEVICE_INIT_MCUX)
``` | /content/code_sandbox/drivers/pwm/pwm_mcux_ctimer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,279 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <Emios_Mcl_Ip.h>
#include <Emios_Pwm_Ip.h>
#ifdef CONFIG_PWM_CAPTURE
#include <Emios_Icu_Ip.h>
#endif
#define LOG_MODULE_NAME nxp_s32_emios_pwm
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL);
#define DT_DRV_COMPAT nxp_s32_emios_pwm
/*
* Need to fill to this array at runtime, cannot do at build time like
* the HAL over configuration tool due to limitation of the integration
*/
#if EMIOS_PWM_IP_USED
extern uint8 eMios_Pwm_Ip_IndexInChState[EMIOS_PWM_IP_INSTANCE_COUNT][EMIOS_PWM_IP_CHANNEL_COUNT];
#endif
#ifdef CONFIG_PWM_CAPTURE
extern uint8 eMios_Icu_Ip_IndexInChState[EMIOS_ICU_IP_INSTANCE_COUNT][EMIOS_ICU_IP_NUM_OF_CHANNELS];
/* We need maximum three edges for measure both period and cycle */
#define MAX_NUM_EDGE 3
struct pwm_nxp_s32_capture_data {
bool continuous;
bool inverted;
bool pulse_capture;
bool period_capture;
void *user_data;
pwm_capture_callback_handler_t callback;
eMios_Icu_ValueType edge_buff[MAX_NUM_EDGE];
};
#endif
struct pwm_nxp_s32_data {
uint32_t emios_clk;
#if EMIOS_PWM_IP_USED
uint8_t start_pwm_ch;
#endif
#ifdef CONFIG_PWM_CAPTURE
struct pwm_nxp_s32_capture_data capture[EMIOS_ICU_IP_NUM_OF_CHANNELS];
#endif
};
#if EMIOS_PWM_IP_USED
struct pwm_nxp_s32_pulse_info {
uint8_t pwm_pulse_channels;
Emios_Pwm_Ip_ChannelConfigType *pwm_info;
};
#endif
struct pwm_nxp_s32_config {
eMIOS_Type *base;
uint8_t instance;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
const struct pinctrl_dev_config *pincfg;
#if EMIOS_PWM_IP_USED
struct pwm_nxp_s32_pulse_info *pulse_info;
#endif
#ifdef CONFIG_PWM_CAPTURE
eMios_Icu_Ip_ConfigType * icu_cfg;
#endif
};
#if EMIOS_PWM_IP_USED
#ifdef EMIOS_PWM_IP_MODE_OPWFMB_USED
static int pwm_nxp_s32_set_cycles_internal_timebase(uint8_t instance, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles)
{
bool need_update = false;
if ((period_cycles > EMIOS_PWM_IP_MAX_CNT_VAL) ||
(period_cycles <= EMIOS_PWM_IP_MIN_CNT_VAL)) {
LOG_ERR("period_cycles is out of range");
return -EINVAL;
}
if (Emios_Pwm_Ip_GetPeriod(instance, channel) != period_cycles) {
Emios_Pwm_Ip_SetPeriod(instance, channel, period_cycles);
need_update = true;
}
if (Emios_Pwm_Ip_GetDutyCycle(instance, channel) != pulse_cycles) {
need_update = true;
if (Emios_Pwm_Ip_SetDutyCycle(instance, channel, pulse_cycles)) {
LOG_ERR("Cannot set pulse cycles");
return -EIO;
}
}
if (need_update) {
/* Force match so that the new period, duty cycle takes effect immediately */
Emios_Pwm_Ip_ForceMatchTrailingEdge(instance, channel, true);
}
return 0;
}
#endif
#if defined(EMIOS_PWM_IP_MODE_OPWMCB_USED) || defined(EMIOS_PWM_IP_MODE_OPWMB_USED)
static int pwm_nxp_s32_set_cycles_external_timebase(uint8_t instance, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles)
{
uint8_t master_channel;
if ((period_cycles > EMIOS_PWM_IP_MAX_CNT_VAL) ||
(period_cycles <= EMIOS_PWM_IP_MIN_CNT_VAL)) {
LOG_ERR("period_cycles is out of range");
return -EINVAL;
}
if (Emios_Pwm_Ip_GetPeriod(instance, channel) != period_cycles) {
/*
* This mode uses internal counter, so change period and cycle
* don't effect to the others
*/
master_channel = Emios_Pwm_Ip_GetMasterBusChannel(instance, channel);
if (Emios_Mcl_Ip_SetCounterBusPeriod(instance, master_channel, period_cycles)) {
LOG_ERR("Cannot set counter period");
return -EIO;
}
}
if (Emios_Pwm_Ip_GetDutyCycle(instance, channel) != pulse_cycles) {
if (Emios_Pwm_Ip_SetDutyCycle(instance, channel, pulse_cycles)) {
LOG_ERR("Cannot set pulse cycles");
return -EIO;
}
}
return 0;
}
#endif
static int pwm_nxp_s32_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_nxp_s32_config *config = dev->config;
struct pwm_nxp_s32_data *data = dev->data;
Emios_Pwm_Ip_ChannelConfigType *pwm_info;
uint8_t logic_ch;
if (channel >= EMIOS_PWM_IP_CHANNEL_COUNT) {
LOG_ERR("invalid channel %d", channel);
return -EINVAL;
}
if (eMios_Pwm_Ip_IndexInChState[config->instance][channel] >=
EMIOS_PWM_IP_NUM_OF_CHANNELS_USED) {
LOG_ERR("Channel %d is not configured for PWM", channel);
return -EINVAL;
}
logic_ch = eMios_Pwm_Ip_IndexInChState[config->instance][channel] - data->start_pwm_ch;
pwm_info = &config->pulse_info->pwm_info[logic_ch];
if ((flags & PWM_POLARITY_MASK) == pwm_info->OutputPolarity) {
LOG_ERR("Only support configuring output polarity at boot time");
return -ENOTSUP;
}
switch (pwm_info->Mode) {
#ifdef EMIOS_PWM_IP_MODE_OPWFMB_USED
case EMIOS_PWM_IP_MODE_OPWFMB_FLAG:
return pwm_nxp_s32_set_cycles_internal_timebase(config->instance, channel,
period_cycles, pulse_cycles);
#endif
#ifdef EMIOS_PWM_IP_MODE_OPWMCB_USED
case EMIOS_PWM_IP_MODE_OPWMCB_TRAIL_EDGE_FLAG:
case EMIOS_PWM_IP_MODE_OPWMCB_LEAD_EDGE_FLAG:
if ((period_cycles % 2)) {
LOG_ERR("OPWMCB mode: period must be an even number");
return -EINVAL;
}
return pwm_nxp_s32_set_cycles_external_timebase(config->instance, channel,
(period_cycles + 2) / 2,
pulse_cycles);
#endif
#if defined(EMIOS_PWM_IP_MODE_OPWMB_USED)
case EMIOS_PWM_IP_MODE_OPWMB_FLAG:
if ((Emios_Pwm_Ip_GetPhaseShift(config->instance, channel) +
pulse_cycles) > period_cycles) {
LOG_ERR("OPWMB mode: new duty cycle + phase shift must <= new period");
return -EINVAL;
}
return pwm_nxp_s32_set_cycles_external_timebase(config->instance, channel,
period_cycles, pulse_cycles);
#endif
default:
/* Never reach here */
break;
}
return 0;
}
#endif
#ifdef CONFIG_PWM_CAPTURE
static ALWAYS_INLINE eMios_Icu_ValueType pwm_nxp_s32_capture_calc(eMios_Icu_ValueType first_cnt,
eMios_Icu_ValueType second_cnt)
{
if (first_cnt < second_cnt) {
return second_cnt - first_cnt;
}
/* Counter top value is always 0xFFFF */
return EMIOS_ICU_IP_COUNTER_MASK - first_cnt + second_cnt;
}
static ALWAYS_INLINE eMios_Icu_ValueType pwm_nxp_s32_pulse_calc(bool inverted,
eMios_Icu_ValueType *edge_buff,
eMios_Icu_Ip_LevelType input_state)
{
eMios_Icu_ValueType first_cnt, second_cnt;
if (input_state ^ inverted) {
/* 3 edges captured is raise, fall, raise */
first_cnt = edge_buff[0];
second_cnt = edge_buff[1];
} else {
/* 3 edges captured is fall, raise, fall */
first_cnt = edge_buff[1];
second_cnt = edge_buff[2];
}
return pwm_nxp_s32_capture_calc(first_cnt, second_cnt);
}
static int pwm_nxp_s32_capture_configure(const struct device *dev,
uint32_t channel,
pwm_flags_t flags,
pwm_capture_callback_handler_t cb,
void *user_data)
{
const struct pwm_nxp_s32_config *config = dev->config;
struct pwm_nxp_s32_data *data = dev->data;
if (channel >= EMIOS_ICU_IP_NUM_OF_CHANNELS) {
LOG_ERR("Invalid channel %d", channel);
return -EINVAL;
}
if (!flags) {
LOG_ERR("Invalid PWM capture flag");
return -EINVAL;
}
if (eMios_Icu_Ip_IndexInChState[config->instance][channel] >=
EMIOS_ICU_IP_NUM_OF_CHANNELS_USED) {
LOG_ERR("Channel %d is not configured for PWM", channel);
return -EINVAL;
}
/* If interrupt is enabled --> channel is on-going */
if (config->base->CH.UC[channel].C & eMIOS_C_FEN_MASK) {
LOG_ERR("Channel %d is busy", channel);
return -EBUSY;
}
data->capture[channel].continuous = (flags & PWM_CAPTURE_MODE_MASK);
data->capture[channel].inverted = (flags & PWM_POLARITY_MASK);
data->capture[channel].pulse_capture = (flags & PWM_CAPTURE_TYPE_PULSE);
data->capture[channel].period_capture = (flags & PWM_CAPTURE_TYPE_PERIOD);
data->capture[channel].callback = cb;
data->capture[channel].user_data = user_data;
return 0;
}
static int pwm_nxp_s32_capture_enable(const struct device *dev, uint32_t channel)
{
const struct pwm_nxp_s32_config *config = dev->config;
struct pwm_nxp_s32_data *data = dev->data;
eMios_Icu_Ip_EdgeType edge;
uint8_t num_edge;
if (channel >= EMIOS_ICU_IP_NUM_OF_CHANNELS) {
LOG_ERR("Invalid channel %d", channel);
return -EINVAL;
}
if (eMios_Icu_Ip_IndexInChState[config->instance][channel] >=
EMIOS_ICU_IP_NUM_OF_CHANNELS_USED) {
LOG_ERR("Channel %d is not configured for PWM", channel);
return -EINVAL;
}
if (!data->capture[channel].callback) {
LOG_ERR("Callback is not configured");
return -EINVAL;
}
/* If interrupt is enabled --> channel is on-going */
if (config->base->CH.UC[channel].C & eMIOS_C_FEN_MASK) {
LOG_ERR("Channel %d is busy", channel);
return -EBUSY;
}
/* If just measure period, we just need 2 edges */
if (data->capture[channel].period_capture && !data->capture[channel].pulse_capture) {
num_edge = 2U;
edge = EMIOS_ICU_RISING_EDGE;
} else {
num_edge = 3U;
edge = EMIOS_ICU_BOTH_EDGES;
}
Emios_Icu_Ip_SetActivation(config->instance, channel, edge);
Emios_Icu_Ip_EnableNotification(config->instance, channel);
Emios_Icu_Ip_StartTimestamp(config->instance, channel,
data->capture[channel].edge_buff,
MAX_NUM_EDGE, num_edge);
return 0;
}
static int pwm_nxp_s32_capture_disable(const struct device *dev, uint32_t channel)
{
const struct pwm_nxp_s32_config *config = dev->config;
if (channel >= EMIOS_ICU_IP_NUM_OF_CHANNELS) {
LOG_ERR("Invalid channel %d", channel);
return -EINVAL;
}
if (eMios_Icu_Ip_IndexInChState[config->instance][channel] >=
EMIOS_ICU_IP_NUM_OF_CHANNELS_USED) {
LOG_ERR("Channel %d is not configured for PWM", channel);
return -EINVAL;
}
Emios_Icu_Ip_StopTimestamp(config->instance, channel);
return 0;
}
static int pwm_nxp_s32_get_master_bus(const struct device *dev, uint32_t channel)
{
const struct pwm_nxp_s32_config *config = dev->config;
uint8_t bus_select, master_bus;
bus_select = (config->base->CH.UC[channel].C & eMIOS_C_BSL_MASK) >> eMIOS_C_BSL_SHIFT;
switch (bus_select) {
case 0:
master_bus = 23U;
break;
case 1:
master_bus = (channel < 8U) ? 0U : ((channel < 16U) ? 8U : 16U);
break;
case 2:
master_bus = 22U;
break;
default:
/* Default is internal counter */
master_bus = channel;
break;
}
return master_bus;
}
#endif
static int pwm_nxp_s32_get_cycles_per_sec(const struct device *dev,
uint32_t channel,
uint64_t *cycles)
{
const struct pwm_nxp_s32_config *config = dev->config;
struct pwm_nxp_s32_data *data = dev->data;
uint8_t master_bus = 0xFFU;
uint8_t internal_prescaler, global_prescaler;
#if EMIOS_PWM_IP_USED
if (eMios_Pwm_Ip_IndexInChState[config->instance][channel] <
EMIOS_PWM_IP_NUM_OF_CHANNELS_USED) {
master_bus = Emios_Pwm_Ip_GetMasterBusChannel(config->instance, channel);
}
#endif
#ifdef CONFIG_PWM_CAPTURE
if (eMios_Icu_Ip_IndexInChState[config->instance][channel] <
EMIOS_ICU_IP_NUM_OF_CHANNELS_USED) {
master_bus = pwm_nxp_s32_get_master_bus(dev, channel);
}
#endif
if (master_bus == 0xFF) {
LOG_ERR("Channel %d is not configured for PWM", channel);
return -EINVAL;
}
internal_prescaler = (config->base->CH.UC[master_bus].C2 & eMIOS_C2_UCEXTPRE_MASK) >>
eMIOS_C2_UCEXTPRE_SHIFT;
/* Clock source for internal prescaler is from either eMIOS or eMIOS / global prescaler */
if (config->base->CH.UC[master_bus].C2 & eMIOS_C2_UCPRECLK_MASK) {
*cycles = data->emios_clk / (internal_prescaler + 1);
} else {
global_prescaler = (config->base->MCR & eMIOS_MCR_GPRE_MASK) >>
eMIOS_MCR_GPRE_SHIFT;
*cycles = data->emios_clk / ((internal_prescaler + 1) * (global_prescaler + 1));
}
return 0;
}
#if EMIOS_PWM_IP_USED
static int pwm_nxp_s32_pulse_gen_init(const struct device *dev)
{
const struct pwm_nxp_s32_config *config = dev->config;
struct pwm_nxp_s32_data *data = dev->data;
const Emios_Pwm_Ip_ChannelConfigType *pwm_info;
uint8_t ch_id;
static uint8_t logic_ch;
data->start_pwm_ch = logic_ch;
for (ch_id = 0; ch_id < config->pulse_info->pwm_pulse_channels; ch_id++) {
pwm_info = &config->pulse_info->pwm_info[ch_id];
eMios_Pwm_Ip_IndexInChState[config->instance][pwm_info->ChannelId] = logic_ch++;
Emios_Pwm_Ip_InitChannel(config->instance, pwm_info);
}
return 0;
}
#endif
#ifdef CONFIG_PWM_CAPTURE
static int pwm_nxp_s32_pulse_capture_init(const struct device *dev)
{
const struct pwm_nxp_s32_config *config = dev->config;
const eMios_Icu_Ip_ChannelConfigType *icu_info;
uint8_t ch_id;
static uint8_t logic_ch;
for (ch_id = 0; ch_id < config->icu_cfg->nNumChannels; ch_id++) {
icu_info = &(*config->icu_cfg->pChannelsConfig)[ch_id];
eMios_Icu_Ip_IndexInChState[config->instance][icu_info->hwChannel] = logic_ch++;
}
if (Emios_Icu_Ip_Init(config->instance, config->icu_cfg)) {
return -EINVAL;
}
return 0;
}
static void pwm_nxp_s32_capture_callback(const struct device *dev, uint32_t channel)
{
const struct pwm_nxp_s32_config *config = dev->config;
struct pwm_nxp_s32_data *data = dev->data;
uint32_t period = 0, pulse = 0;
if (data->capture[channel].period_capture && !data->capture[channel].pulse_capture) {
period = pwm_nxp_s32_capture_calc(data->capture[channel].edge_buff[0],
data->capture[channel].edge_buff[1]);
} else {
if (data->capture[channel].pulse_capture) {
pulse = pwm_nxp_s32_pulse_calc(data->capture[channel].inverted,
data->capture[channel].edge_buff,
Emios_Icu_Ip_GetInputLevel(config->instance,
channel));
}
if (data->capture[channel].period_capture) {
period = pwm_nxp_s32_capture_calc(data->capture[channel].edge_buff[0],
data->capture[channel].edge_buff[2]);
}
}
if (!data->capture[channel].continuous) {
Emios_Icu_Ip_StopTimestamp(config->instance, channel);
}
data->capture[channel].callback(dev, channel, period, pulse, 0,
data->capture[channel].user_data);
}
#endif
static int pwm_nxp_s32_init(const struct device *dev)
{
const struct pwm_nxp_s32_config *config = dev->config;
struct pwm_nxp_s32_data *data = dev->data;
int err = 0;
if (!device_is_ready(config->clock_dev)) {
return -ENODEV;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&data->emios_clk)) {
return -EINVAL;
}
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {
return err;
}
#if EMIOS_PWM_IP_USED
err = pwm_nxp_s32_pulse_gen_init(dev);
if (err < 0) {
return err;
}
#endif
#ifdef CONFIG_PWM_CAPTURE
err = pwm_nxp_s32_pulse_capture_init(dev);
if (err < 0) {
return err;
}
#endif
return err;
}
static const struct pwm_driver_api pwm_nxp_s32_driver_api = {
.set_cycles = pwm_nxp_s32_set_cycles,
.get_cycles_per_sec = pwm_nxp_s32_get_cycles_per_sec,
#ifdef CONFIG_PWM_CAPTURE
.configure_capture = pwm_nxp_s32_capture_configure,
.enable_capture = pwm_nxp_s32_capture_enable,
.disable_capture = pwm_nxp_s32_capture_disable,
#endif
};
/*
* If timebase is configured in MCB up/down count mode: pwm period = (2 * master bus's period - 2)
*/
#define EMIOS_PWM_PERIOD_TIME_BASE(node_id) \
COND_CODE_1(DT_ENUM_HAS_VALUE(node_id, mode, MCB_UP_DOWN_COUNTER), \
(2 * DT_PROP_BY_PHANDLE(node_id, master_bus, period) - 2), \
(DT_PROP_BY_PHANDLE(node_id, master_bus, period)))
#define EMIOS_PWM_IS_MODE_OPWFMB(node_id) \
DT_ENUM_HAS_VALUE(node_id, pwm_mode, OPWFMB)
#define EMIOS_PWM_IS_MODE_OPWMCB(node_id) \
UTIL_OR(DT_ENUM_HAS_VALUE(node_id, pwm_mode, OPWMCB_TRAIL_EDGE), \
DT_ENUM_HAS_VALUE(node_id, pwm_mode, OPWMCB_LEAD_EDGE)) \
#define EMIOS_PWM_IS_MODE_OPWMB(node_id) \
DT_ENUM_HAS_VALUE(node_id, pwm_mode, OPWMB)
#define EMIOS_PWM_IS_MODE_SAIC(node_id) \
DT_ENUM_HAS_VALUE(node_id, pwm_mode, SAIC)
#define EMIOS_PWM_IS_CAPTURE_MODE(node_id) \
EMIOS_PWM_IS_MODE_SAIC(node_id)
#define EMIOS_PWM_LOG(node_id, msg) \
DT_NODE_PATH(node_id) ": " DT_PROP(node_id, pwm_mode) ": " msg \
#define EMIOS_PWM_VERIFY_MASTER_BUS(node_id) \
BUILD_ASSERT(BIT(DT_PROP(node_id, channel)) & \
DT_PROP_BY_PHANDLE(node_id, master_bus, channel_mask), \
EMIOS_PWM_LOG(node_id, "invalid master bus"));
#define EMIOS_PWM_PULSE_GEN_COMMON_VERIFY(node_id) \
BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, duty_cycle), \
EMIOS_PWM_LOG(node_id, "duty-cycle must be configured")); \
BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, polarity), \
EMIOS_PWM_LOG(node_id, "polarity must be configured")); \
BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, input_filter), \
EMIOS_PWM_LOG(node_id, "input-filter is not used"));
#define EMIOS_PWM_VERIFY_MODE_OPWFMB(node_id) \
EMIOS_PWM_PULSE_GEN_COMMON_VERIFY(node_id) \
BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, period), \
EMIOS_PWM_LOG(node_id, "period must be configured")); \
BUILD_ASSERT(IN_RANGE(DT_PROP(node_id, period), EMIOS_PWM_IP_MIN_CNT_VAL + 1, \
EMIOS_PWM_IP_MAX_CNT_VAL), \
EMIOS_PWM_LOG(node_id, "period is out of range")); \
BUILD_ASSERT(DT_PROP(node_id, duty_cycle) <= DT_PROP(node_id, period), \
EMIOS_PWM_LOG(node_id, "duty-cycle must <= period")); \
BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, master_bus), \
EMIOS_PWM_LOG(node_id, "master-bus must not be configured")); \
BUILD_ASSERT(DT_PROP(node_id, dead_time) == 0, \
EMIOS_PWM_LOG(node_id, "dead-time is not used")); \
BUILD_ASSERT(DT_PROP(node_id, phase_shift) == 0, \
EMIOS_PWM_LOG(node_id, "phase-shift is not used"));
#define EMIOS_PWM_VERIFY_MODE_OPWMCB(node_id) \
EMIOS_PWM_PULSE_GEN_COMMON_VERIFY(node_id) \
BUILD_ASSERT(DT_ENUM_HAS_VALUE(DT_PHANDLE(node_id, master_bus), mode, \
MCB_UP_DOWN_COUNTER), \
EMIOS_PWM_LOG(node_id, "master-bus must be configured in MCB up-down")); \
BUILD_ASSERT((DT_PROP(node_id, duty_cycle) + DT_PROP(node_id, dead_time)) <= \
EMIOS_PWM_PERIOD_TIME_BASE(node_id), \
EMIOS_PWM_LOG(node_id, "duty-cycle + dead-time must <= period")); \
BUILD_ASSERT(DT_PROP(node_id, dead_time) <= DT_PROP(node_id, duty_cycle), \
EMIOS_PWM_LOG(node_id, "dead-time must <= duty-cycle")); \
BUILD_ASSERT(DT_PROP(node_id, phase_shift) == 0, \
EMIOS_PWM_LOG(node_id, "phase-shift is not used")); \
BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, period), \
EMIOS_PWM_LOG(node_id, "period is not used," \
" driver takes the value from master bus")); \
BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, prescaler), \
EMIOS_PWM_LOG(node_id, "prescaler is not used," \
" driver takes the value from master bus")); \
BUILD_ASSERT(DT_ENUM_HAS_VALUE(node_id, prescaler_src, PRESCALED_CLOCK), \
EMIOS_PWM_LOG(node_id, "prescaler-src is not used," \
" always use prescalered source")); \
#define EMIOS_PWM_VERIFY_MODE_OPWMB(node_id) \
EMIOS_PWM_PULSE_GEN_COMMON_VERIFY(node_id) \
BUILD_ASSERT(DT_ENUM_HAS_VALUE(DT_PHANDLE(node_id, master_bus), mode, MCB_UP_COUNTER), \
EMIOS_PWM_LOG(node_id, "master-bus must be configured in MCB up")); \
BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, period), \
EMIOS_PWM_LOG(node_id, "period is not used," \
" driver takes the value from master bus")); \
BUILD_ASSERT((DT_PROP(node_id, duty_cycle) + DT_PROP(node_id, phase_shift)) <= \
EMIOS_PWM_PERIOD_TIME_BASE(node_id), \
EMIOS_PWM_LOG(node_id, "duty-cycle + phase-shift must <= period")); \
BUILD_ASSERT(DT_PROP(node_id, dead_time) == 0, \
EMIOS_PWM_LOG(node_id, "dead-time is not used")); \
BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, prescaler), \
EMIOS_PWM_LOG(node_id, "prescaler is not used")); \
BUILD_ASSERT(DT_ENUM_HAS_VALUE(node_id, prescaler_src, PRESCALED_CLOCK), \
EMIOS_PWM_LOG(node_id, "prescaler-src is not used," \
" always use prescalered source")); \
#define EMIOS_PWM_VERIFY_MODE_SAIC(node_id) \
IF_ENABLED(DT_NODE_HAS_PROP(node_id, master_bus), \
(BUILD_ASSERT( \
DT_ENUM_HAS_VALUE(DT_PHANDLE(node_id, master_bus), mode, MCB_UP_COUNTER), \
EMIOS_PWM_LOG(node_id, "master-bus must be configured in MCB up"));)) \
IF_ENABLED(DT_NODE_HAS_PROP(node_id, master_bus), \
(BUILD_ASSERT(DT_PROP_BY_PHANDLE(node_id, master_bus, period) == 0xFFFF, \
EMIOS_PWM_LOG(node_id, "master-bus period must be 0xFFFF"));)) \
IF_ENABLED(UTIL_NOT(DT_NODE_HAS_PROP(node_id, master_bus)), \
(BUILD_ASSERT( \
BIT(DT_PROP(node_id, channel)) & DT_PROP(DT_GPARENT(node_id), internal_cnt),\
EMIOS_PWM_LOG(node_id, "master-bus must be chosen," \
" channel do not have has counter")))); \
IF_ENABLED(UTIL_NOT(DT_NODE_HAS_PROP(node_id, master_bus)), \
(BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, prescaler), \
EMIOS_PWM_LOG(node_id, "if use internal counter, prescaler must" \
" be configured")))); \
BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, duty_cycle), \
EMIOS_PWM_LOG(node_id, "duty-cycle is not used")); \
BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, polarity), \
EMIOS_PWM_LOG(node_id, "polarity is not used")); \
BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, period), \
EMIOS_PWM_LOG(node_id, "period is not used")); \
BUILD_ASSERT(DT_ENUM_HAS_VALUE(node_id, prescaler_src, PRESCALED_CLOCK), \
EMIOS_PWM_LOG(node_id, "prescaler-src is not used," \
" always use prescalered source"));
#define _EMIOS_PWM_VERIFY_CONFIG(node_id) \
IF_ENABLED(DT_NODE_HAS_PROP(node_id, master_bus), \
(EMIOS_PWM_VERIFY_MASTER_BUS(node_id))) \
IF_ENABLED(EMIOS_PWM_IS_MODE_OPWFMB(node_id), \
(EMIOS_PWM_VERIFY_MODE_OPWFMB(node_id))) \
IF_ENABLED(EMIOS_PWM_IS_MODE_OPWMCB(node_id), \
(EMIOS_PWM_VERIFY_MODE_OPWMCB(node_id))) \
IF_ENABLED(EMIOS_PWM_IS_MODE_OPWMB(node_id), \
(EMIOS_PWM_VERIFY_MODE_OPWMB(node_id))) \
IF_ENABLED(EMIOS_PWM_IS_MODE_SAIC(node_id), \
(EMIOS_PWM_VERIFY_MODE_SAIC(node_id)))
#if EMIOS_PWM_IP_USED
/* Macros used to glue devicetree with RTD's definition */
#define EMIOS_PWM_BUS_A EMIOS_PWM_IP_BUS_A
#define EMIOS_PWM_BUS_B EMIOS_PWM_IP_BUS_BCDE
#define EMIOS_PWM_BUS_C EMIOS_PWM_IP_BUS_BCDE
#define EMIOS_PWM_BUS_D EMIOS_PWM_IP_BUS_BCDE
#define EMIOS_PWM_BUS_E EMIOS_PWM_IP_BUS_BCDE
#define EMIOS_PWM_BUS_F EMIOS_PWM_IP_BUS_F
#define EMIOS_PWM_BUS(mode) DT_CAT(EMIOS_PWM_, mode)
#define EMIOS_PWM_MODE(mode) DT_CAT3(EMIOS_PWM_IP_MODE_, mode, _FLAG)
#define EMIOS_PWM_POLARITY(mode) DT_CAT(EMIOS_PWM_IP_, mode)
#define EMIOS_PWM_PS_SRC(mode) DT_CAT(EMIOS_PWM_IP_PS_SRC_, mode)
#define _EMIOS_PWM_PULSE_GEN_CONFIG(node_id) \
IF_ENABLED(UTIL_NOT(EMIOS_PWM_IS_CAPTURE_MODE(node_id)), \
({ \
.ChannelId = DT_PROP(node_id, channel), \
.Mode = EMIOS_PWM_MODE(DT_STRING_TOKEN(node_id, pwm_mode)), \
.InternalPsSrc = EMIOS_PWM_PS_SRC(DT_STRING_TOKEN(node_id, prescaler_src)), \
.InternalPs = DT_PROP_OR(node_id, prescaler, \
DT_PROP_BY_PHANDLE(node_id, master_bus, prescaler)) - 1,\
.Timebase = COND_CODE_1(DT_NODE_HAS_PROP(node_id, master_bus), \
(EMIOS_PWM_BUS(DT_STRING_TOKEN( \
DT_PHANDLE(node_id, master_bus), bus_type))), \
(EMIOS_PWM_IP_BUS_INTERNAL)), \
.PhaseShift = DT_PROP(node_id, phase_shift), \
.DeadTime = DT_PROP(node_id, dead_time), \
.OutputDisableSource = EMIOS_PWM_IP_OUTPUT_DISABLE_NONE, \
.OutputPolarity = EMIOS_PWM_POLARITY(DT_STRING_TOKEN(node_id, polarity)), \
.DebugMode = DT_PROP(node_id, freeze), \
.PeriodCount = DT_PROP_OR(node_id, period, EMIOS_PWM_PERIOD_TIME_BASE(node_id)),\
.DutyCycle = DT_PROP(node_id, duty_cycle), \
},))
#define EMIOS_PWM_PULSE_GEN_CONFIG(n) \
const Emios_Pwm_Ip_ChannelConfigType emios_pwm_##n##_init[] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, _EMIOS_PWM_PULSE_GEN_CONFIG) \
}; \
const struct pwm_nxp_s32_pulse_info emios_pwm_##n##_info = { \
.pwm_pulse_channels = ARRAY_SIZE(emios_pwm_##n##_init), \
.pwm_info = (Emios_Pwm_Ip_ChannelConfigType *)emios_pwm_##n##_init, \
};
#define EMIOS_PWM_PULSE_GEN_GET_CONFIG(n) \
.pulse_info = (struct pwm_nxp_s32_pulse_info *)&emios_pwm_##n##_info,
#else
#define EMIOS_PWM_PULSE_GEN_CONFIG(n)
#define EMIOS_PWM_PULSE_GEN_GET_CONFIG(n)
#endif
#ifdef CONFIG_PWM_CAPTURE
/* Macros used to glue devicetree with RTD's definition */
#define EMIOS_ICU_BUS_A EMIOS_ICU_BUS_A
#define EMIOS_ICU_BUS_B EMIOS_ICU_BUS_DIVERSE
#define EMIOS_ICU_BUS_C EMIOS_ICU_BUS_DIVERSE
#define EMIOS_ICU_BUS_D EMIOS_ICU_BUS_DIVERSE
#define EMIOS_ICU_BUS_E EMIOS_ICU_BUS_DIVERSE
#define EMIOS_ICU_BUS_F EMIOS_ICU_BUS_F
#define DIGITAL_FILTER_0 EMIOS_DIGITAL_FILTER_BYPASSED
#define DIGITAL_FILTER_2 EMIOS_DIGITAL_FILTER_02
#define DIGITAL_FILTER_4 EMIOS_DIGITAL_FILTER_04
#define DIGITAL_FILTER_8 EMIOS_DIGITAL_FILTER_08
#define DIGITAL_FILTER_16 EMIOS_DIGITAL_FILTER_16
#define EMIOS_PWM_CAPTURE_FILTER(filter) DT_CAT(DIGITAL_FILTER_, filter)
#define EMIOS_PWM_CAPTURE_MODE(mode) DT_CAT(EMIOS_ICU_, mode)
#define EMIOS_PWM_CAPTURE_BUS(mode) DT_CAT(EMIOS_ICU_, mode)
#define EMIOS_PWM_CAPTURE_CB(n, ch) \
DT_CAT5(pwm_nxp_s32_, n, _channel_, ch, _capture_callback)
#define EMIOS_PWM_CALLBACK_DECLARE(node_id, n) \
void EMIOS_PWM_CAPTURE_CB(n, DT_PROP(node_id, channel))(void) \
{ \
pwm_nxp_s32_capture_callback(DEVICE_DT_INST_GET(n), DT_PROP(node_id, channel)); \
} \
#define _EMIOS_PWM_PULSE_CAPTURE_CONFIG(node_id, n) \
IF_ENABLED(EMIOS_PWM_IS_CAPTURE_MODE(node_id), \
({ \
.hwChannel = DT_PROP(node_id, channel), \
.ucMode = EMIOS_PWM_CAPTURE_MODE(DT_STRING_TOKEN(node_id, pwm_mode)), \
.FreezeEn = DT_PROP(node_id, freeze), \
.Prescaler = COND_CODE_1(DT_NODE_HAS_PROP(node_id, master_bus), \
(DT_PROP_BY_PHANDLE(node_id, master_bus, prescaler)), \
(DT_PROP(node_id, prescaler))) - 1, \
.CntBus = COND_CODE_1(DT_NODE_HAS_PROP(node_id, master_bus), \
(EMIOS_PWM_CAPTURE_BUS(DT_STRING_TOKEN( \
DT_PHANDLE(node_id, master_bus), bus_type))),\
(EMIOS_ICU_BUS_INTERNAL_COUNTER)), \
.chMode = EMIOS_ICU_MODE_TIMESTAMP, \
.chSubMode = EMIOS_ICU_MODE_WITHOUT_DMA, \
.measurementMode = EMIOS_ICU_NO_MEASUREMENT, \
.edgeAlignement = EMIOS_ICU_BOTH_EDGES, \
.Filter = EMIOS_PWM_CAPTURE_FILTER(DT_PROP(node_id, input_filter)), \
.callback = NULL_PTR, \
.logicChStateCallback = NULL_PTR, \
.callbackParams = 255U, \
.bWithoutInterrupt = FALSE, \
.timestampBufferType = EMIOS_ICU_CIRCULAR_BUFFER, \
.eMiosChannelNotification = EMIOS_PWM_CAPTURE_CB(n, DT_PROP(node_id, channel)), \
.eMiosOverflowNotification = NULL_PTR, \
},))
#define EMIOS_PWM_PULSE_CAPTURE_CONFIG(n) \
DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(n, EMIOS_PWM_CALLBACK_DECLARE, n) \
const eMios_Icu_Ip_ChannelConfigType emios_pwm_##n##_capture_init[] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(n, _EMIOS_PWM_PULSE_CAPTURE_CONFIG, n) \
}; \
const eMios_Icu_Ip_ConfigType emios_pwm_##n##_capture_info = { \
.nNumChannels = ARRAY_SIZE(emios_pwm_##n##_capture_init), \
.pChannelsConfig = &emios_pwm_##n##_capture_init, \
};
#define EMIOS_PWM_PULSE_CAPTURE_GET_CONFIG(n) \
.icu_cfg = (eMios_Icu_Ip_ConfigType *)&emios_pwm_##n##_capture_info,
#else
#define EMIOS_PWM_PULSE_CAPTURE_CONFIG(n)
#define EMIOS_PWM_PULSE_CAPTURE_GET_CONFIG(n)
#endif
#define EMIOS_PWM_VERIFY_CONFIG(n) \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, _EMIOS_PWM_VERIFY_CONFIG)
#define EMIOS_NXP_S32_INSTANCE_CHECK(idx, node_id) \
((DT_REG_ADDR(node_id) == IP_EMIOS_##idx##_BASE) ? idx : 0)
#define EMIOS_NXP_S32_GET_INSTANCE(node_id) \
LISTIFY(__DEBRACKET eMIOS_INSTANCE_COUNT, EMIOS_NXP_S32_INSTANCE_CHECK, (|), node_id)
#define PWM_NXP_S32_INIT_DEVICE(n) \
PINCTRL_DT_INST_DEFINE(n); \
EMIOS_PWM_VERIFY_CONFIG(n) \
EMIOS_PWM_PULSE_GEN_CONFIG(n) \
EMIOS_PWM_PULSE_CAPTURE_CONFIG(n) \
static const struct pwm_nxp_s32_config pwm_nxp_s32_config_##n = { \
.base = (eMIOS_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \
.instance = EMIOS_NXP_S32_GET_INSTANCE(DT_INST_PARENT(n)), \
.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
.clock_subsys = (clock_control_subsys_t)DT_CLOCKS_CELL(DT_INST_PARENT(n), name),\
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
EMIOS_PWM_PULSE_GEN_GET_CONFIG(n) \
EMIOS_PWM_PULSE_CAPTURE_GET_CONFIG(n) \
}; \
static struct pwm_nxp_s32_data pwm_nxp_s32_data_##n; \
DEVICE_DT_INST_DEFINE(n, \
&pwm_nxp_s32_init, \
NULL, \
&pwm_nxp_s32_data_##n, \
&pwm_nxp_s32_config_##n, \
POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, \
&pwm_nxp_s32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PWM_NXP_S32_INIT_DEVICE)
``` | /content/code_sandbox/drivers/pwm/pwm_nxp_s32_emios.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,706 |
```unknown
#
#
#
config PWM_MAX31790
bool "MAX31790 6-channel I2C-bus PWM controller"
default y
depends on DT_HAS_MAXIM_MAX31790_PWM_ENABLED
select MFD
help
Enable driver for MAX31790 6-channel I2C-bus PWM controller.
``` | /content/code_sandbox/drivers/pwm/Kconfig.max31790 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
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