text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
#
#
#
config PWM_PCA9685
bool "PCA9685 16-channel, 12-bit PWM Fm+ I2C-bus LED controller"
default y
depends on DT_HAS_NXP_PCA9685_PWM_ENABLED
select I2C
help
Enable driver for PCA9685 16-channel, 12-bit PWM Fm+ I2C-bus LED
controller.
``` | /content/code_sandbox/drivers/pwm/Kconfig.pca9685 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```unknown
config PWM_XMC4XXX_CCU8
bool "Infineon XMC4XXX CCU4 driver"
default y
depends on DT_HAS_INFINEON_XMC4XXX_CCU8_PWM_ENABLED
help
Enables Infineon XMC4XXX CCU8 PWM driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.xmc4xxx_ccu8 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```c
/*
*
*/
/**
* @file
* @brief PWM shell commands.
*/
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/pwm.h>
#include <stdlib.h>
struct args_index {
uint8_t device;
uint8_t channel;
uint8_t period;
uint8_t pulse;
uint8_t flags;
};
static const struct args_index args_indx = {
.device = 1,
.ch... | /content/code_sandbox/drivers/pwm/pwm_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 912 |
```unknown
# i.MX PWM Config
menuconfig PWM_IMX
bool "i.MX PWM Driver"
default y
depends on DT_HAS_FSL_IMX27_PWM_ENABLED
help
Enable support for i.MX pwm driver.
config PWM_PWMSWR_LOOP
int "Loop count for PWM Software Reset"
default 5
depends on PWM_IMX
help
Loop count for PWM Software Reset when disab... | /content/code_sandbox/drivers/pwm/Kconfig.imx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```unknown
# PWM configuration options
menuconfig PWM
bool "Pulse Width Modulation (PWM) drivers"
help
Enable config options for PWM drivers.
if PWM
module = PWM
module-str = pwm
source "subsys/logging/Kconfig.template.log_config"
config PWM_INIT_PRIORITY
int "PWM initialization priority"
default KERNEL_INI... | /content/code_sandbox/drivers/pwm/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 575 |
```unknown
config PWM_MCUX_SCTIMER
bool "MCUX SCTimer PWM driver"
default y
depends on DT_HAS_NXP_SCTIMER_PWM_ENABLED
depends on CLOCK_CONTROL && PINCTRL
help
Enable sctimer based pwm driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.mcux_sctimer | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```c
/*
*
*/
#define DT_DRV_COMPAT ene_kb1200_pwm
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <reg/pwm.h>
/* Device config */
struct pwm_kb1200_config {
/* pwm controller base address */
struct pwm_regs *pwm;
const struct pinctrl_dev_config *pcfg;
};
/* Driver data */
struct pw... | /content/code_sandbox/drivers/pwm/pwm_ene_kb1200.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 895 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_sctimer_pwm
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <fsl_sctimer.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_sctimer, CONFIG_PWM_LOG_... | /content/code_sandbox/drivers/pwm/pwm_mcux_sctimer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,247 |
```c
/*
*
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/pwm.h>
static inline int z_vrfy_pwm_set_cycles(const struct device *dev,
uint32_t channel, uint32_t period,
uint32_t pulse, pwm_flags_t flags)
{
K_OOPS(K_SYSCALL_DRIVER_PWM(dev, set_cycles));
return z_impl_pwm_set_cycles(... | /content/code_sandbox/drivers/pwm/pwm_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 577 |
```c
/*
*
*/
#define DT_DRV_COMPAT raspberrypi_pico_pwm
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_rpi_pico, CONFIG_PWM_LOG_LEVEL);
... | /content/code_sandbox/drivers/pwm/pwm_rpi_pico.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,650 |
```c
/*
*
*/
/*
* PWM driver using the SAM0 Timer/Counter (TCC) in Normal PWM (NPWM) mode.
* Supports the SAMD21 and SAMD5x series.
*/
#define DT_DRV_COMPAT atmel_sam0_tcc_pwm
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
/* S... | /content/code_sandbox/drivers/pwm/pwm_sam0_tcc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,351 |
```c
/*
*
*/
#define DT_DRV_COMPAT silabs_gecko_pwm
#include <zephyr/drivers/pwm.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <em_cmu.h>
#include <em_timer.h>
/** PWM configuration. */
struct pwm_gecko_config {
TIMER_TypeDef *timer;
CMU_Clock_TypeDef clock;
uint16_t prescaler;
TIMER_Prescale_TypeDef pre... | /content/code_sandbox/drivers/pwm/pwm_gecko.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 951 |
```c
/*
*
*/
#define DT_DRV_COMPAT telink_b91_pwm
#include <pwm.h>
#include <clock.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
struct pwm_b91_config {
const struct pinctrl_dev_config *pcfg;
uint32_t clock_frequency;
uint8_t channels;
uint8_t clk32k_ch_enable;
};
/* API implementatio... | /content/code_sandbox/drivers/pwm/pwm_b91.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,180 |
```unknown
# Atmel SAM0 TCC as PWM configuration
config PWM_SAM0_TCC
bool "Atmel SAM0 MCU Family TCC PWM Driver"
default y
depends on DT_HAS_ATMEL_SAM0_TCC_PWM_ENABLED
help
Enable PWM driver for Atmel SAM0 MCUs using the TCC timer/counter.
``` | /content/code_sandbox/drivers/pwm/Kconfig.sam0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
config PWM_ENE_KB1200
bool "ENE KB1200 PWM driver"
default y
depends on DT_HAS_ENE_KB1200_PWM_ENABLED
select PINCTRL
help
This option enables the PWM driver for KB1200 processors.
``` | /content/code_sandbox/drivers/pwm/Kconfig.ene | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
config PWM_MCUX_QTMR
bool "MCUX QMTR PWM driver"
default y
depends on DT_HAS_NXP_QTMR_PWM_ENABLED
depends on CLOCK_CONTROL && PINCTRL
help
Enable QTMR based pwm driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.mcux_qtmr | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config PWM_TELINK_B91
bool "Telink Semiconductor B91 PWM driver"
default y
depends on DT_HAS_TELINK_B91_PWM_ENABLED
help
Enables Telink B91 PWM driver.
``` | /content/code_sandbox/drivers/pwm/Kconfig.b91 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```c
/*
*
* Heavily based on pwm_mcux_ftm.c, which is:
*
*/
#define DT_DRV_COMPAT openisa_rv32m1_tpm
#include <zephyr/drivers/clock_control.h>
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <soc.h>
#include <fsl_tpm.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/loggi... | /content/code_sandbox/drivers/pwm/pwm_rv32m1_tpm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,594 |
```unknown
config PWM_RPI_PICO
bool "RPi Pico PWM"
default y
depends on DT_HAS_RASPBERRYPI_PICO_PWM_ENABLED
depends on RESET
select PICOSDK_USE_PWM
help
Enable PWM driver for RPi Pico family of MCUs
``` | /content/code_sandbox/drivers/pwm/Kconfig.rpi_pico | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
/*
*
*/
/**
* @brief Assembler-hooks specific to Nuclei's Extended Core Interrupt Controller
*/
#include <zephyr/arch/cpu.h>
GTEXT(__soc_handle_irq)
/*
* In an ECLIC, pending interrupts don't have to be cleared by hand.
* In vectored mode, interrupts are cleared automatically.
* In non-vectored mo... | /content/code_sandbox/drivers/interrupt_controller/intc_nuclei_eclic.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 497 |
```c
/*
*
*/
#define DT_DRV_COMPAT shared_irq
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/shared_irq.h>
#include <zephyr/init.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/irq.h>
#ifdef CONFIG_IOAPIC
#include <zephyr/drivers/interrupt_controller/ioapic.h>
#endif
... | /content/code_sandbox/drivers/interrupt_controller/intc_shared_irq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,350 |
```c
/*
*
*/
/**
* @brief Driver for External interrupt/event controller in STM32 MCUs
*/
#define EXTI_NODE DT_INST(0, st_stm32_exti)
#include <zephyr/device.h>
#include <soc.h>
#include <stm32_ll_exti.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/interrupt_controller/... | /content/code_sandbox/drivers/interrupt_controller/intc_exti_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,027 |
```c
/*
*
*/
/**
* @file
* @brief ARCv2 Interrupt Unit device driver
*
* The ARCv2 interrupt unit has 16 allocated exceptions associated with
* vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
* The interrupt unit is optional in the ARCv2-based processors. When
* building a processor, you... | /content/code_sandbox/drivers/interrupt_controller/intc_arcv2_irq_unit.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,241 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/printk.h>
#include <zephyr/sw_isr_table.h>
#include "intc_ite_it8xxx2.h"
LOG_MODULE_REGISTER(intc_it8xxx2_v2, LOG_LEVEL_DBG);
#define IT8XXX2_INTC_BASE DT_REG_ADDR(DT_N... | /content/code_sandbox/drivers/interrupt_controller/intc_ite_it8xxx2_v2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,977 |
```c
/*
* Systems, Inc.
*
*/
#define DT_DRV_COMPAT intel_ioapic
/**
* @file
* @brief Intel IO APIC/xAPIC driver
*
* This module is a driver for the IO APIC/xAPIC (Advanced Programmable
* Interrupt Controller) for P6 (PentiumPro, II, III) family processors
* and P7 (Pentium4) family processors. The IO APIC/x... | /content/code_sandbox/drivers/interrupt_controller/intc_ioapic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,312 |
```c
/*
*/
#define DT_DRV_COMPAT intel_loapic
/*
* driver for x86 CPU local APIC (as an interrupt controller)
*/
#include <zephyr/kernel.h>
#include <zephyr/kernel_structs.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/pm/device.h>
#include <zephyr/types.h>
#include <string.h>
#include <zephyr/sys/__assert.h>
... | /content/code_sandbox/drivers/interrupt_controller/intc_loapic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,593 |
```unknown
/*
*/
#include <zephyr/toolchain.h>
/* Exports */
GTEXT(__soc_handle_irq)
/*
* No need to clear anything, pending bit is cleared by HW.
*/
SECTION_FUNC(exception.other, __soc_handle_irq)
ret
``` | /content/code_sandbox/drivers/interrupt_controller/intc_nrfx_clic.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
# STM32 EXTI configuration
if SOC_FAMILY_STM32
config EXTI_STM32
bool "External Interrupt/Event Controller (EXTI) Driver for STM32 family of MCUs"
default y
depends on DT_HAS_ST_STM32_EXTI_ENABLED
help
Enable EXTI driver for STM32 line of MCUs
endif # SOC_FAMILY_STM32
``` | /content/code_sandbox/drivers/interrupt_controller/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
menuconfig LOAPIC
bool "LOAPIC"
depends on X86
help
This option selects local APIC as the interrupt controller.
if LOAPIC
config X2APIC
bool "Access local APIC in x2APIC mode"
help
If your local APIC supports x2APIC mode, turn this on.
config LOAPIC_SPURIOUS_VECTOR
bool "Handle LOAPIC spuriou... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.loapic | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 489 |
```c
/*
*
*/
#define DT_DRV_COMPAT snps_designware_intc
/* This implementation supports only the regular irqs
* No support for priority filtering
* No support for vectored interrupts
* Firqs are also not supported
* This implementation works only when sw_isr_table is enabled in zephyr
*/
#include <zephyr/devi... | /content/code_sandbox/drivers/interrupt_controller/intc_dw.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,230 |
```c
/*
*
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <string.h>
#include <soc/periph_defs.h>
#include <limits.h>
#include <assert.h>
#include "soc/soc.h"
#include <soc.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#include... | /content/code_sandbox/drivers/interrupt_controller/intc_esp32c3.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,328 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H_
#define ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H_
/* Offsets from GICD base or GICR(n) SGI_base */
#define GIC_DIST_IGROUPR 0x0080
#define GIC_DIST_ISENABLER 0x0100
#define GIC_DIST_ICENABLER 0x0180
#define GIC_DIST_ISPENDR 0x020... | /content/code_sandbox/drivers/interrupt_controller/intc_gic_common_priv.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 611 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_ra_interrupt_controller_unit
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
#include <zephyr/sw_isr_table.h>
#include <errno.h>
#define IELSRn_REG(n) (DT_INST_REG_ADDR(0) + IELSRn_OFFSET + (... | /content/code_sandbox/drivers/interrupt_controller/intc_renesas_ra_icu.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 918 |
```unknown
/*
*
*/
/**
* @file
* @brief LOAPIC spurious interrupt handler
*/
#include <zephyr/kernel_structs.h>
#include <zephyr/arch/x86/ia32/asm.h>
GTEXT(z_loapic_spurious_handler)
SECTION_FUNC(PINNED_TEXT, z_loapic_spurious_handler)
iret
``` | /content/code_sandbox/drivers/interrupt_controller/intc_loapic_spurious.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
# Configuration for NXP S32 external interrupt controller
config NXP_S32_EIRQ
bool "External interrupt controller driver for NXP S32 MCUs"
default y
depends on DT_HAS_NXP_S32_SIUL2_EIRQ_ENABLED
select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
help
External interrupt controller driver for NX... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.nxp_s32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 338 |
```unknown
# Espressif's Interrupt Allocator driver for Xtensa SoCs
config INTC_ESP32
bool "Interrupt allocator for Xtensa-based Espressif SoCs"
default y
depends on SOC_FAMILY_ESPRESSIF_ESP32
depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
help
Enable custom interrupt allocator f... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 189 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_
#define ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <zephyr/sys/atomic.h>
/* Cache and Share ability for ITS & Redistributor LPI state tables */
#define GIC_BASER_CACHE_NGNRNE 0x0UL... | /content/code_sandbox/drivers/interrupt_controller/intc_gicv3_priv.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,470 |
```unknown
# shared_irq configuration options
menuconfig SHARED_IRQ
bool "Shared interrupt driver"
default y
depends on DT_HAS_SHARED_IRQ_ENABLED
help
Include shared interrupt support in system. Shared interrupt
support is NOT required in most systems. If in doubt answer no.
config SHARED_IRQ_INIT_PRIORITY... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.shared_irq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```unknown
config RENESAS_RA_ICU
bool "Renesas RA series interrupt controller unit"
default y
depends on DT_HAS_RENESAS_RA_INTERRUPT_CONTROLLER_UNIT_ENABLED
select GEN_ISR_TABLES
help
Renesas RA series interrupt controller unit
``` | /content/code_sandbox/drivers/interrupt_controller/Kconfig.renesas_ra | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#define DT_DRV_COMPAT litex_vexriscv_intc0
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/irq.h>
#include <zephyr/device.h>
#include <zephyr/types.h>
#include <zephyr/arch/riscv/irq.h>
#define IRQ_MASK DT_INST_REG_ADDR_BY_NAME(0, irq_mask)
#define IRQ_PENDING DT_INST_REG_AD... | /content/code_sandbox/drivers/interrupt_controller/intc_vexriscv_litex.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 749 |
```c
/*
*/
#define DT_DRV_COMPAT intel_vt_d
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <string.h>
#include <zephyr/cache.h>
#include <zephyr/arch/x86/intel_vtd.h>
#include <zephyr/drivers/interrupt_cont... | /content/code_sandbox/drivers/interrupt_controller/intc_intel_vtd.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,046 |
```c
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#define DT_DRV_COMPAT mediatek_adsp_intc
struct intc_mtk_cfg {
uint32_t xtensa_irq;
uint32_t irq_mask;
uint32_t sw_isr_off;
volatile uint32_t *enable_reg;
volatile uint32_t *status_reg;
};
bool intc_mtk_adsp_get_enable(const struct device *dev, in... | /content/code_sandbox/drivers/interrupt_controller/intc_mtk_adsp.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 625 |
```unknown
# CAVS interrupt controller configuration
config CAVS_ICTL
bool "CAVS Interrupt Logic"
default y
depends on DT_HAS_INTEL_CAVS_INTC_ENABLED
depends on MULTI_LEVEL_INTERRUPTS
help
These are 4 in number supporting a max of 32 interrupts each.
if CAVS_ICTL
config CAVS_ISR_TBL_OFFSET
int "Offset in t... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.cavs | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 274 |
```c
/*
*
*/
#define DT_DRV_COMPAT swerv_pic
/**
* @brief SweRV EH1 PIC driver
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/sw_isr_table.h>
#include <zephyr/irq.h>
#include <zephyr/arch/riscv/irq.h>
#define SWERV_PIC_MAX_NUM CONFIG_NUM_IRQS
#define SWERV... | /content/code_sandbox/drivers/interrupt_controller/intc_swerv_pic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,772 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_npcx_miwu
/**
* @file
* @brief Nuvoton NPCX MIWU driver
*
* The device Multi-Input Wake-Up Unit (MIWU) supports the Nuvoton embedded
* controller (EC) to exit 'Sleep' or 'Deep Sleep' power state which allows chip
* has better power consumption. Also, it provides sign... | /content/code_sandbox/drivers/interrupt_controller/intc_miwu.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,323 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(intc_it8xxx2, LOG_LEVEL_DBG);
#include <zephyr/sys/printk.h>
#include <zephyr/sw_isr_table.h>
#include "intc_ite_it8xxx2.h"
#define MAX_REGISR_IRQ_NUM 8
#define IVECT_OF... | /content/code_sandbox/drivers/interrupt_controller/intc_ite_it8xxx2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,618 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
#include <hal/nrf_vpr_clic.h>
void riscv_clic_irq_enable(uint32_t irq)
{
nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, true);
}
void riscv_clic_irq_disable(uint32_t irq)
{
nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, ... | /content/code_sandbox/drivers/interrupt_controller/intc_nrfx_clic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 234 |
```c
/*
*
*/
#define DT_DRV_COMPAT openisa_rv32m1_intmux
/**
* @file
* @brief RV32M1 INTMUX (interrupt multiplexer) driver
*
* This driver provides support for level 2 interrupts on the RV32M1
* SoC using the INTMUX peripheral.
*
* Each of the RI5CY and ZERO-RISCY cores has an INTMUX peripheral;
* INTMUX0 i... | /content/code_sandbox/drivers/interrupt_controller/intc_rv32m1_intmux.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,972 |
```unknown
# Intel VT-D interrupt remapping controller configuration
menuconfig INTEL_VTD_ICTL
bool "Intel VT-D interrupt remapping controller"
default y
depends on DT_HAS_INTEL_VT_D_ENABLED
depends on !BOARD_QEMU_X86_64 && ACPI && X86 && 64BIT && PCIE_MSI_MULTI_VECTOR
select CACHE_MANAGEMENT
help
Such inter... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.intel_vtd | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 290 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32_wkpu
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/math_extras.h>
#include <zephyr/drivers/interrupt_controller/intc_wkpu_nxp_s32.h>
/* NMI Status Flag Register */
#define WKPU_NSR 0... | /content/code_sandbox/drivers/interrupt_controller/intc_wkpu_nxp_s32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,193 |
```unknown
config HAS_ITE_INTC
bool
help
This option is selected when ITE_IT8XXX2_INTC or
ITE_IT8XXX2_INTC_V2 is enabled.
config ITE_IT8XXX2_INTC
def_bool DT_HAS_ITE_IT8XXX2_INTC_ENABLED
depends on DT_HAS_ITE_IT8XXX2_INTC_ENABLED
select HAS_ITE_INTC
help
Configures the maximum number of clients allowed ... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.it8xxx2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 281 |
```objective-c
/* ioapic_priv.h - private IOAPIC APIs */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_IOAPIC_PRIV_H_
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_IOAPIC_PRIV_H_
/* IO APIC direct register offsets */
#define IOAPIC_IND 0x00 /* Index Register */
#define IOAPIC_DATA 0x10 /* IO wind... | /content/code_sandbox/drivers/interrupt_controller/intc_ioapic_priv.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 481 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CAVS_H_
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CAVS_H_
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*cavs_ictl_config_irq_t)(const struct device *port);
struct cavs_ictl_config {
uint32_t irq_num;... | /content/code_sandbox/drivers/interrupt_controller/intc_cavs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 226 |
```c
/*
*
*/
#define DT_DRV_COMPAT ite_it8xxx2_wuc
#include <zephyr/device.h>
#include <zephyr/drivers/interrupt_controller/wuc_ite_it8xxx2.h>
#include <zephyr/dt-bindings/interrupt-controller/it8xxx2-wuc.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <soc_common.h>
#include <stdlib.h>
#include <zephyr/lo... | /content/code_sandbox/drivers/interrupt_controller/wuc_ite_it8xxx2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 997 |
```c
*
*/
#define DT_DRV_COMPAT ti_vim
#include <stdint.h>
#include <zephyr/arch/arm/irq.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/interrupt_controller/intc_vim.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util_macro.h>
LOG_MODULE... | /content/code_sandbox/drivers/interrupt_controller/intc_vim.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,067 |
```c
/*
*
*/
/*
* This is a driver for the GRLIB IRQMP interrupt controller common in LEON
* systems.
*
* Interrupt level 1..15 are SPARC interrupts. Interrupt level 16..31, if
* implemented in the interrupt controller, are IRQMP "extended interrupts".
*
* For more information about IRQMP, see the GRLIB IP Co... | /content/code_sandbox/drivers/interrupt_controller/intc_irqmp.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 945 |
```unknown
config PLIC
bool "Platform Level Interrupt Controller (PLIC)"
default y
depends on DT_HAS_SIFIVE_PLIC_1_0_0_ENABLED
select MULTI_LEVEL_INTERRUPTS
select 2ND_LEVEL_INTERRUPTS
help
Platform Level Interrupt Controller provides support
for external interrupt lines defined by the RISC-V SoC.
if PLIC... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.plic | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```objective-c
/*
*/
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_
#define VTD_INT_SHV BIT(3)
#define VTD_INT_FORMAT BIT(4)
/* We don't care about int_idx[15], since the size is fixed to 256,
* it's always 0
*/
#define VTD_MSI_MAP(int_i... | /content/code_sandbox/drivers/interrupt_controller/intc_intel_vtd.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,152 |
```unknown
config NXP_IRQSTEER
bool "IRQ_STEER interrupt controller for NXP chips"
default y
depends on DT_HAS_NXP_IRQSTEER_INTC_ENABLED
depends on MULTI_LEVEL_INTERRUPTS
depends on XTENSA
help
The IRQSTEER INTC provides support for MUX-ing
multiple interrupts from peripheral to one or
more CPU interrupt l... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.nxp_irqsteer | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <string.h>
#include <soc.h>
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#include <esp_memory_utils.h>
#include <esp_attr.h>
#include <esp_cpu.h>
#include <esp_private/rtc_c... | /content/code_sandbox/drivers/interrupt_controller/intc_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,214 |
```unknown
config $(cur-level)_LVL_INTR_0$(aggregator)_OFFSET
int "Level $(prev-level-num) IRQ line for $(cur-level) level aggregator $(aggregator)"
default 0
depends on $(cur-level)_LEVEL_INTERRUPTS
help
This is the level $(prev-level-num) interrupt number for level
$(cur-level-num) interrupt aggregator $(a... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.multilevel.aggregator_template | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
config NUCLEI_ECLIC
bool "Enhanced Core Local Interrupt Controller (ECLIC)"
default y
depends on DT_HAS_NUCLEI_ECLIC_ENABLED
select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING if !RISCV_VECTORED_MODE
help
Interrupt controller for Nuclei SoC core.
config NRFX_CLIC
bool "VPR Core Local Interrpt Controller (CL... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.clic | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 202 |
```unknown
config NXP_PINT
bool "Pin interrupt and pattern match engine (PINT) for NXP MCUs"
default y
depends on DT_HAS_NXP_PINT_ENABLED
help
Enable PINT driver for NXP MCUs
``` | /content/code_sandbox/drivers/interrupt_controller/Kconfig.nxp_pint | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```c
/*
*
*/
/*
* NOTE: This driver implements the GICv1 and GICv2 interfaces.
*/
#include <zephyr/device.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/sw_isr_table.h>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/drivers/interrupt_controller/gic.h... | /content/code_sandbox/drivers/interrupt_controller/intc_gic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,161 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32_siul2_eirq
#include <soc.h>
#include <zephyr/irq.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/math_extras.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/interrupt_controller/intc_eirq_nxp_s32.h>
/* SIUL2 External Interrupt Controller registers (... | /content/code_sandbox/drivers/interrupt_controller/intc_eirq_nxp_s32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,616 |
```viml
#
if CPU_CORTEX_R5
config VIM
bool "TI Vectored Interrupt Manager"
default y
depends on DT_HAS_TI_VIM_ENABLED
help
The TI Vectored Interrupt Manager provides hardware assistance for prioritizing
and aggregating the interrupt sources for ARM Cortex-R5 processor cores.
endif # CPU_CORTEX_R5
``` | /content/code_sandbox/drivers/interrupt_controller/Kconfig.vim | viml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```c
/*
*
*/
/* Based on STM32 EXTI driver, which is (c) 2016 Open-RnD Sp. z o.o. */
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <errno.h>
#include <zephyr/drivers/interrupt_controller/nxp_pint.h>
#include <fsl_inputmux.h>
#include <fsl_power.h>
#define DT_DRV_COMPAT nxp_pint
static PINT_Type *pi... | /content/code_sandbox/drivers/interrupt_controller/intc_nxp_pint.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,585 |
```unknown
# RV32M1 INTMUX config
config RV32M1_INTMUX
bool "OpenISA RV32M1 INTMUX interrupt controller support"
default y
depends on DT_HAS_OPENISA_RV32M1_INTMUX_ENABLED
depends on MULTI_LEVEL_INTERRUPTS
help
Select this option to enable support for the RV32M1 INTMUX
driver. This provides a level 2 interr... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.rv32m1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 445 |
```unknown
# Microchip XEC ECIA configuration
config MCHP_ECIA_XEC
bool "External EC Interrupt Aggregator (ECIA) Driver for MCHP MEC family of MCUs"
default y
depends on DT_HAS_MICROCHIP_XEC_ECIA_ENABLED
help
Enable XEC ECIA driver for Microchip MEC line of MCUs
``` | /content/code_sandbox/drivers/interrupt_controller/Kconfig.xec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam0_eic
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/drivers/interrupt_controller/sam0_eic.h>
#include "intc_sam0_eic_priv.h"
struct sam0_eic_line_assignment {
uint8_t pin : 5;
uint8_t port : 2;
uint8_t enabled : 1;
};
struct sam... | /content/code_sandbox/drivers/interrupt_controller/intc_sam0_eic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,674 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_DW_H_
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_DW_H_
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*dw_ictl_config_irq_t)(const struct device *dev);
struct dw_ictl_config {
uint32_t base_addr;
uint3... | /content/code_sandbox/drivers/interrupt_controller/intc_dw.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 967 |
```unknown
# NPCX GPIO driver configuration options
config NPCX_MIWU
bool "Nuvoton NPCX embedded controller (EC) miwu driver"
default y
depends on DT_HAS_NUVOTON_NPCX_MIWU_ENABLED
help
This option enables the Multi-Input Wake-Up Unit (MIWU) driver
for NPCX family of processors.
This is required for GPIO,... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.npcx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 151 |
```unknown
config DW_ICTL_ACE
bool "Designware Interrupt Controller for ACE"
default y
depends on DT_HAS_INTEL_ACE_INTC_ENABLED
depends on MULTI_LEVEL_INTERRUPTS
help
Designware Interrupt Controller used by ACE.
menuconfig DW_ICTL
bool "Designware Interrupt Controller"
default y
depends on DT_HAS_SNPS_DESI... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.dw | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 259 |
```c
/*
*
*/
/**
* @file
* @brief Driver for NXP's IRQ_STEER IP.
*
* Below you may find some useful information that will help you better understand how the
* driver works. The ">" sign is used to mark ideas that are considered important and should
* be taken note of.
*
* 1) What is the IRQ_STEER IP?
* - in... | /content/code_sandbox/drivers/interrupt_controller/intc_nxp_irqsteer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,449 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_ITE_IT8XXX2_H_
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_ITE_IT8XXX2_H_
#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
#include <ilm.h>
#include <soc.h>
#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_ITE_IT8XXX2_H_ */
... | /content/code_sandbox/drivers/interrupt_controller/intc_ite_it8xxx2.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```unknown
config INTC_MTK_ADSP
bool "MediaTek Audio DSP Interrupt Controller"
help
Very simple cascaded interrupt controller consisting of two
bitfield registers (status and enable) and one mask value
defining valid interrupts.
``` | /content/code_sandbox/drivers/interrupt_controller/Kconfig.mtk_adsp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```c
/*
*
*/
/**
* @file
* @brief system module for variants with LOAPIC
*
*/
#include <zephyr/sys/__assert.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/interrupt_controller/ioapic.h>
#include <zephyr/drivers/interrupt_controller/loapic.h>
#include <zephyr/drivers/interru... | /content/code_sandbox/drivers/interrupt_controller/intc_system_apic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 702 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sw_isr_table.h>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/drivers/interrupt_controller/gic.h>
#include <zephyr/sys/barrier.h>
#include ... | /content/code_sandbox/drivers/interrupt_controller/intc_gicv3.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,318 |
```c
/*
*
*/
#define DT_DRV_COMPAT intel_cavs_intc
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/devicetree/interrupt_controller.h>
#include <zephyr/irq.h>
#include <zephyr/irq_nextlevel.h>
#include <zephyr/arch/arch_interface.h>
#include <zephyr/sw_isr_table.h>
#include "intc_cavs.h"
#i... | /content/code_sandbox/drivers/interrupt_controller/intc_cavs.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,296 |
```c
/*
*
*/
#define DT_DRV_COMPAT intel_ace_intc
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/devicetree/interrupt_controller.h>
#include <zephyr/irq_nextlevel.h>
#include <zephyr/arch/xtensa/irq.h>
#include <zephyr/sw_isr_table.h>
#include <zephyr/drivers/interrupt_controller/dw_ace.... | /content/code_sandbox/drivers/interrupt_controller/intc_dw_ace.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,612 |
```unknown
# interrupt controller configuration options
menu "Interrupt controller drivers"
config ARCV2_INTERRUPT_UNIT
bool "ARCv2 Interrupt Unit"
default y
depends on ARC
help
The ARCv2 interrupt unit has 16 allocated exceptions associated with
vectors 0 to 15 and 240 interrupts associated with vectors 1... | /content/code_sandbox/drivers/interrupt_controller/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 698 |
```unknown
# ARM Generic Interrupt Controller (GIC) configuration
if CPU_CORTEX
config GIC
bool
config GIC_V1
def_bool DT_HAS_ARM_GIC_V1_ENABLED
select GIC
help
The ARM Generic Interrupt Controller v1 (e.g. PL390) works with the
ARM Cortex-family processors.
config GIC_V2
def_bool DT_HAS_ARM_GIC_V2_ENAB... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.gic | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 440 |
```c
/*
*
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(intc_gicv3_its, LOG_LEVEL_ERR);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/interrupt_controller/gicv3_its.h>
#include <zephyr/sys/barrier.h>
#include "intc_gic_common_priv.h"
#include "intc_gicv3_priv.h"
#define D... | /content/code_sandbox/drivers/interrupt_controller/intc_gicv3_its.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,557 |
```c
/*
*
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_intc
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
#include <zephyr/irq.h>
#include <xmc_eru.h>
/* In Infineon XMC4XXX SoCs, gpio interrupts a... | /content/code_sandbox/drivers/interrupt_controller/intc_xmc4xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,217 |
```unknown
# XMC4XXX INTC configuration
config XMC4XXX_INTC
bool "Interrupt Controller Driver for XMC4XXX series devices"
default y
depends on DT_HAS_INFINEON_XMC4XXX_INTC_ENABLED
help
Enable interrupt controller driver for XMC4XXX series of devices. This is required for
GPIO interrupt support.
``` | /content/code_sandbox/drivers/interrupt_controller/Kconfig.xmc4xxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
# SAM0 EIC configuration
config SAM0_EIC
bool "External Interrupt Controller (EIC) Driver for SAM0 series devices"
default y
depends on DT_HAS_ATMEL_SAM0_EIC_ENABLED
help
Enable EIC driver for SAM0 series of devices. This is required for
GPIO interrupt support.
``` | /content/code_sandbox/drivers/interrupt_controller/Kconfig.sam0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
config GD32_EXTI
bool "GD32 Extended Interrupts and Events (EXTI) Controller"
default y
depends on DT_HAS_GD_GD32_EXTI_ENABLED
help
Enable the GigaDevice GD32 Extended Interrupts and Events (EXTI)
controller driver.
``` | /content/code_sandbox/drivers/interrupt_controller/Kconfig.gd32_exti | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
config INTC_ESP32C3
bool "ESP32C3 interrupt controller driver"
depends on SOC_FAMILY_ESPRESSIF_ESP32
depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
default y
help
Enables the esp32c3 interrupt controller driver to handle ISR
management at SoC level.
config INTC_ESP32C3... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.esp32c3 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 177 |
```c
/*
*
*/
/**
* @brief Driver for Nuclie's Extended Core Interrupt Controller
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/sys/util.h>
#include <zephyr/device.h>
#include <zephyr/sw_isr_table.h>
#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
#define DT_DRV_COMPAT n... | /content/code_sandbox/drivers/interrupt_controller/intc_nuclei_eclic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,318 |
```unknown
# Multilevel interrupt configuration
config MULTI_LEVEL_INTERRUPTS
bool "Multi-level interrupt support"
depends on GEN_SW_ISR_TABLE
help
Multiple levels of interrupts are normally used to increase the
number of addressable interrupts in a system. For example, if two
levels are used, a second le... | /content/code_sandbox/drivers/interrupt_controller/Kconfig.multilevel | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,089 |
```c
/*
*
*/
/**
* @brief Driver for External interrupt controller in Microchip XEC devices
*
* Driver is currently implemented to support MEC172x ECIA GIRQs
*/
#define DT_DRV_COMPAT microchip_xec_ecia
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/device.h>
#include <soc.h>
#include <ze... | /content/code_sandbox/drivers/interrupt_controller/intc_mchp_ecia_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,451 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_SAM0_EIC_PRIV_H_
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_SAM0_EIC_PRIV_H_
#include <errno.h>
#include <zephyr/types.h>
#include <soc.h>
/*
* Used in the ASF headers, but not always defined by them (looks like they
* sometimes define... | /content/code_sandbox/drivers/interrupt_controller/intc_sam0_eic_priv.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,156 |
```c
/*
*
*/
#define DT_DRV_COMPAT gd_gd32_exti
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/interrupt_controller/gd32_exti.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util_macro.h>
#include <gd32_exti.h>
/** Unsupported line indicator */
#define EXT... | /content/code_sandbox/drivers/interrupt_controller/intc_gd32_exti.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,713 |
```objective-c
/*
*
*/
#ifndef BDMA_STM32_H_
#define BDMA_STM32_H_
#include <soc.h>
#include <stm32_ll_bdma.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/dma/dma_stm32.h>
/* Maximum data sent in single transfer (Bytes) */
#define BDMA_STM3... | /content/code_sandbox/drivers/dma/dma_stm32_bdma.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 879 |
```objective-c
/*
*
*/
#ifndef DMA_IPROC_PAX_V1
#define DMA_IPROC_PAX_V1
#include "dma_iproc_pax.h"
/* Register RM_CONTROL fields */
#define RM_COMM_MSI_INTERRUPT_STATUS_MASK 0x30d0
#define RM_COMM_MSI_INTERRUPT_STATUS_CLEAR 0x30d4
#define RM_COMM_CONTROL_MODE_MASK 0x3
#define RM_COMM_CONTROL_MODE_SHIFT 0
#de... | /content/code_sandbox/drivers/dma/dma_iproc_pax_v1.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,079 |
```c
/*
* Contributors: 2018 Antmicro <www.antmicro.com>
*
*/
#define DT_DRV_COMPAT sifive_plic_1_0_0
/**
* @brief Platform Level Interrupt Controller (PLIC) driver
* for RISC-V processors
*/
#include <stdlib.h>
#include "sw_isr_common.h"
#include <zephyr/debug/symtab.h>
#include <zephyr/kernel.h>
#in... | /content/code_sandbox/drivers/interrupt_controller/intc_plic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,712 |
```objective-c
/*
*
*/
#ifndef DMA_IPROC_PAX_V2
#define DMA_IPROC_PAX_V2
#include "dma_iproc_pax.h"
#define RING_COMPLETION_INTERRUPT_STAT_MASK 0x088
#define RING_COMPLETION_INTERRUPT_STAT_CLEAR 0x08c
#define RING_COMPLETION_INTERRUPT_STAT 0x090
#define RING_DISABLE_MSI_TIMEOUT 0x0a4
/* Register RM_COMM_CONTROL... | /content/code_sandbox/drivers/dma/dma_iproc_pax_v2.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,038 |
```objective-c
/*
*
*/
/** @file
* @brief Atmel SAM MCU family Direct Memory Access (XDMAC) driver.
*/
#ifndef ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_
#define ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* XDMA_MBR_UBC */
#define XDMA_UBC_NDE (0x1u << 24)
#define ... | /content/code_sandbox/drivers/dma/dma_sam_xdmac.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 974 |
```unknown
# Intel ADSP HDA configuration options
config DMA_INTEL_ADSP_HDA_HOST_IN
bool "Intel ADSP HDA Host In DMA drivers"
default y
depends on DT_HAS_INTEL_ADSP_HDA_HOST_IN_ENABLED
depends on DMA
select DMA_INTEL_ADSP_HDA
help
Intel ADSP Host HDA DMA driver.
config DMA_INTEL_ADSP_HDA_HOST_OUT
bool "Int... | /content/code_sandbox/drivers/dma/Kconfig.intel_adsp_hda | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 420 |
```unknown
config MCUX_PXP
bool "MCUX PXP DMA driver"
default y
depends on DT_HAS_NXP_PXP_ENABLED
depends on DISPLAY
help
PXP DMA driver for NXP SOCs
``` | /content/code_sandbox/drivers/dma/Kconfig.mcux_pxp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
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