text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
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```objective-c
/*
*
*/
/**
* @file
* @brief API for NXP SJA1000 (and compatible) CAN controller frontend drivers.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_SJA1000_H_
#define ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_SJA1000_H_
#include <zephyr/drivers/can.h>
/**
* @name SJA1000 Output Control Register (OCR) bits
*
* @{
*/
#define CAN_SJA1000_OCR_OCMODE_MASK GENMASK(1, 0)
#define CAN_SJA1000_OCR_OCPOL0 BIT(2)
#define CAN_SJA1000_OCR_OCTN0 BIT(3)
#define CAN_SJA1000_OCR_OCTP0 BIT(4)
#define CAN_SJA1000_OCR_OCPOL1 BIT(5)
#define CAN_SJA1000_OCR_OCTN1 BIT(6)
#define CAN_SJA1000_OCR_OCTP1 BIT(7)
#define CAN_SJA1000_OCR_OCMODE_BIPHASE FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 0U)
#define CAN_SJA1000_OCR_OCMODE_TEST FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 1U)
#define CAN_SJA1000_OCR_OCMODE_NORMAL FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 2U)
#define CAN_SJA1000_OCR_OCMODE_CLOCK FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 3U)
/** @} */
/**
* @name SJA1000 Clock Divider Register (CDR) bits
*
* @{
*/
#define CAN_SJA1000_CDR_CD_MASK GENMASK(2, 0)
#define CAN_SJA1000_CDR_CLOCK_OFF BIT(3)
#define CAN_SJA1000_CDR_RXINTEN BIT(5)
#define CAN_SJA1000_CDR_CBP BIT(6)
#define CAN_SJA1000_CDR_CAN_MODE BIT(7)
#define CAN_SJA1000_CDR_CD_DIV1 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 7U)
#define CAN_SJA1000_CDR_CD_DIV2 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 0U)
#define CAN_SJA1000_CDR_CD_DIV4 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 1U)
#define CAN_SJA1000_CDR_CD_DIV6 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 2U)
#define CAN_SJA1000_CDR_CD_DIV8 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 3U)
#define CAN_SJA1000_CDR_CD_DIV10 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 4U)
#define CAN_SJA1000_CDR_CD_DIV12 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 5U)
#define CAN_SJA1000_CDR_CD_DIV14 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 6U)
/** @} */
/**
* @brief SJA1000 specific static initializer for a minimum @p can_timing struct
*/
#define CAN_SJA1000_TIMING_MIN_INITIALIZER \
{ \
.sjw = 1, \
.prop_seg = 0, \
.phase_seg1 = 1, \
.phase_seg2 = 1, \
.prescaler = 1 \
}
/**
* @brief SJA1000 specific static initializer for a maximum @p can_timing struct
*/
#define CAN_SJA1000_TIMING_MAX_INITIALIZER \
{ \
.sjw = 4, \
.prop_seg = 0, \
.phase_seg1 = 16, \
.phase_seg2 = 8, \
.prescaler = 64 \
}
/**
* @brief SJA1000 driver front-end callback for writing a register value
*
* @param dev Pointer to the device structure for the driver instance.
* @param reg Register offset
* @param val Register value
*/
typedef void (*can_sja1000_write_reg_t)(const struct device *dev, uint8_t reg, uint8_t val);
/**
* @brief SJA1000 driver front-end callback for reading a register value
*
* @param dev Pointer to the device structure for the driver instance.
* @param reg Register offset
* @retval Register value
*/
typedef uint8_t (*can_sja1000_read_reg_t)(const struct device *dev, uint8_t reg);
/**
* @brief SJA1000 driver internal configuration structure.
*/
struct can_sja1000_config {
const struct can_driver_config common;
can_sja1000_read_reg_t read_reg;
can_sja1000_write_reg_t write_reg;
uint8_t ocr;
uint8_t cdr;
const void *custom;
};
/**
* @brief Static initializer for @p can_sja1000_config struct
*
* @param node_id Devicetree node identifier
* @param _custom Pointer to custom driver frontend configuration structure
* @param _read_reg Driver frontend SJA100 register read function
* @param _write_reg Driver frontend SJA100 register write function
* @param _ocr Initial SJA1000 Output Control Register (OCR) value
* @param _cdr Initial SJA1000 Clock Divider Register (CDR) value
* @param _min_bitrate minimum bitrate supported by the CAN controller
*/
#define CAN_SJA1000_DT_CONFIG_GET(node_id, _custom, _read_reg, _write_reg, _ocr, _cdr, \
_min_bitrate) \
{ \
.common = CAN_DT_DRIVER_CONFIG_GET(node_id, _min_bitrate, 1000000), \
.read_reg = _read_reg, \
.write_reg = _write_reg, \
.ocr = _ocr, \
.cdr = _cdr, \
.custom = _custom, \
}
/**
* @brief Static initializer for @p can_sja1000_config struct from a DT_DRV_COMPAT instance
*
* @param inst DT_DRV_COMPAT instance number
* @param _custom Pointer to custom driver frontend configuration structure
* @param _read_reg Driver frontend SJA100 register read function
* @param _write_reg Driver frontend SJA100 register write function
* @param _ocr Initial SJA1000 Output Control Register (OCR) value
* @param _cdr Initial SJA1000 Clock Divider Register (CDR) value
* @param _min_bitrate minimum bitrate supported by the CAN controller
* @see CAN_SJA1000_DT_CONFIG_GET()
*/
#define CAN_SJA1000_DT_CONFIG_INST_GET(inst, _custom, _read_reg, _write_reg, _ocr, _cdr, \
_min_bitrate) \
CAN_SJA1000_DT_CONFIG_GET(DT_DRV_INST(inst), _custom, _read_reg, _write_reg, _ocr, _cdr, \
_min_bitrate)
/**
* @brief SJA1000 driver internal RX filter structure.
*/
struct can_sja1000_rx_filter {
struct can_filter filter;
can_rx_callback_t callback;
void *user_data;
};
/**
* @brief SJA1000 driver internal data structure.
*/
struct can_sja1000_data {
struct can_driver_data common;
ATOMIC_DEFINE(rx_allocs, CONFIG_CAN_MAX_FILTER);
struct can_sja1000_rx_filter filters[CONFIG_CAN_MAX_FILTER];
struct k_mutex mod_lock;
enum can_state state;
struct k_sem tx_idle;
can_tx_callback_t tx_callback;
void *tx_user_data;
void *custom;
};
/**
* @brief Initializer for a @a can_sja1000_data struct
* @param _custom Pointer to custom driver frontend data structure
*/
#define CAN_SJA1000_DATA_INITIALIZER(_custom) \
{ \
.custom = _custom, \
}
/**
* @brief SJA1000 callback API upon setting CAN bus timing
* See @a can_set_timing() for argument description
*/
int can_sja1000_set_timing(const struct device *dev, const struct can_timing *timing);
/**
* @brief SJA1000 callback API upon getting CAN controller capabilities
* See @a can_get_capabilities() for argument description
*/
int can_sja1000_get_capabilities(const struct device *dev, can_mode_t *cap);
/**
* @brief SJA1000 callback API upon starting CAN controller
* See @a can_start() for argument description
*/
int can_sja1000_start(const struct device *dev);
/**
* @brief SJA1000 callback API upon stopping CAN controller
* See @a can_stop() for argument description
*/
int can_sja1000_stop(const struct device *dev);
/**
* @brief SJA1000 callback API upon setting CAN controller mode
* See @a can_set_mode() for argument description
*/
int can_sja1000_set_mode(const struct device *dev, can_mode_t mode);
/**
* @brief SJA1000 callback API upon sending a CAN frame
* See @a can_send() for argument description
*/
int can_sja1000_send(const struct device *dev, const struct can_frame *frame, k_timeout_t timeout,
can_tx_callback_t callback, void *user_data);
/**
* @brief SJA1000 callback API upon adding an RX filter
* See @a can_add_rx_callback() for argument description
*/
int can_sja1000_add_rx_filter(const struct device *dev, can_rx_callback_t callback, void *user_data,
const struct can_filter *filter);
/**
* @brief SJA1000 callback API upon removing an RX filter
* See @a can_remove_rx_filter() for argument description
*/
void can_sja1000_remove_rx_filter(const struct device *dev, int filter_id);
#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
/**
* @brief SJA1000 callback API upon recovering the CAN bus
* See @a can_recover() for argument description
*/
int can_sja1000_recover(const struct device *dev, k_timeout_t timeout);
#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
/**
* @brief SJA1000 callback API upon getting the CAN controller state
* See @a can_get_state() for argument description
*/
int can_sja1000_get_state(const struct device *dev, enum can_state *state,
struct can_bus_err_cnt *err_cnt);
/**
* @brief SJA1000 callback API upon setting a state change callback
* See @a can_set_state_change_callback() for argument description
*/
void can_sja1000_set_state_change_callback(const struct device *dev,
can_state_change_callback_t callback, void *user_data);
/**
* @brief SJA1000 callback API upon getting the maximum number of concurrent CAN RX filters
* See @a can_get_max_filters() for argument description
*/
int can_sja1000_get_max_filters(const struct device *dev, bool ide);
/**
* @brief SJA1000 IRQ handler callback.
*
* @param dev Pointer to the device structure for the driver instance.
*/
void can_sja1000_isr(const struct device *dev);
/**
* @brief SJA1000 driver initialization callback.
*
* @param dev Pointer to the device structure for the driver instance.
*/
int can_sja1000_init(const struct device *dev);
#endif /* ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_SJA1000_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/can/can_sja1000.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,513 |
```objective-c
/*
*
*/
/**
* @file
* @brief Backend API for emulated UART
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SERIAL_UART_EMUL_H_
#define ZEPHYR_INCLUDE_DRIVERS_SERIAL_UART_EMUL_H_
#include <zephyr/device.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Define the application callback function signature for
* uart_emul_callback_tx_data_ready_set() function.
*
* @param dev UART device instance
* @param size Number of available bytes in TX buffer
* @param user_data Arbitrary user data
*/
typedef void (*uart_emul_callback_tx_data_ready_t)(const struct device *dev, size_t size,
void *user_data);
/**
* @brief Set the TX data ready callback
*
* This sets up the callback that is called every time data
* was appended to the TX buffer.
*
* @param dev The emulated UART device instance
* @param cb Pointer to the callback function
* @param user_data Data to pass to callback function
*/
void uart_emul_callback_tx_data_ready_set(const struct device *dev,
uart_emul_callback_tx_data_ready_t cb, void *user_data);
/**
* @brief Write (copy) data to RX buffer
*
* @param dev The emulated UART device instance
* @param data The data to append
* @param size Number of bytes to append
*
* @return Number of bytes appended
*/
uint32_t uart_emul_put_rx_data(const struct device *dev, const uint8_t *data, size_t size);
/**
* @brief Read data from TX buffer
*
* @param dev The emulated UART device instance
* @param data The address of the output buffer
* @param size Number of bytes to read
*
* @return Number of bytes written to the output buffer
*/
uint32_t uart_emul_get_tx_data(const struct device *dev, uint8_t *data, size_t size);
/**
* @brief Clear RX buffer content
*
* @param dev The emulated UART device instance
*
* @return Number of cleared bytes
*/
uint32_t uart_emul_flush_rx_data(const struct device *dev);
/**
* @brief Clear TX buffer content
*
* @param dev The emulated UART device instance
*
* @return Number of cleared bytes
*/
uint32_t uart_emul_flush_tx_data(const struct device *dev);
/**
* @brief Sets one or more driver errors
*
* @param dev The emulated UART device instance
* @param errors The @ref uart_rx_stop_reason errors to set
*/
void uart_emul_set_errors(const struct device *dev, int errors);
/**
* @brief Configures if rx buffer should be released on timeout, even when only partially filled.
*
* @param dev The emulated UART device instance
* @param release_on_timeout When true, buffer will be released on timeout
*/
void uart_emul_set_release_buffer_on_timeout(const struct device *dev, bool release_on_timeout);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SERIAL_UART_EMUL_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/serial/uart_emul.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 658 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_SERIAL_UART_ASYNC_TO_IRQ_H_
#define ZEPHYR_DRIVERS_SERIAL_UART_ASYNC_TO_IRQ_H_
#include <zephyr/drivers/uart.h>
#include <zephyr/logging/log.h>
#include <zephyr/spinlock.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/serial/uart_async_rx.h>
/**
* @brief UART Asynchronous to Interrupt driven API adaptation layer
* @ingroup uart_interface
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/* Forward declarations. */
/** @brief Data structure used by the adaptation layer.
*
* Pointer to that data must be the first element of the UART device data structure.
*/
struct uart_async_to_irq_data;
/** @brief Configuration structure used by the adaptation layer.
*
* Pointer to this data must be the first element of the UART device configuration structure.
*/
struct uart_async_to_irq_config;
/* @brief Function that triggers trampoline to the interrupt context.
*
* This context is used to call user UART interrupt handler. It is to used to
* fulfill the requirement that UART interrupt driven API shall be called from
* the UART interrupt. Trampoline context shall have the same priority as UART.
*
* One option may be to use k_timer configured to expire immediately.
*/
typedef void (*uart_async_to_irq_trampoline)(const struct device *dev);
/** @brief Callback to be called from trampoline context.
*
* @param dev UART device.
*/
void uart_async_to_irq_trampoline_cb(const struct device *dev);
/** @brief Interrupt driven API initializer.
*
* It should be used in the initialization of the UART API structure in the
* driver to provide interrupt driven API functions.
*/
#define UART_ASYNC_TO_IRQ_API_INIT() \
.fifo_fill = z_uart_async_to_irq_fifo_fill, \
.fifo_read = z_uart_async_to_irq_fifo_read, \
.irq_tx_enable = z_uart_async_to_irq_irq_tx_enable, \
.irq_tx_disable = z_uart_async_to_irq_irq_tx_disable, \
.irq_tx_ready = z_uart_async_to_irq_irq_tx_ready, \
.irq_rx_enable = z_uart_async_to_irq_irq_rx_enable, \
.irq_rx_disable = z_uart_async_to_irq_irq_rx_disable, \
.irq_tx_complete = z_uart_async_to_irq_irq_tx_complete,\
.irq_rx_ready = z_uart_async_to_irq_irq_rx_ready, \
.irq_err_enable = z_uart_async_to_irq_irq_err_enable, \
.irq_err_disable = z_uart_async_to_irq_irq_err_disable,\
.irq_is_pending = z_uart_async_to_irq_irq_is_pending, \
.irq_update = z_uart_async_to_irq_irq_update, \
.irq_callback_set = z_uart_async_to_irq_irq_callback_set
/** @brief Configuration structure initializer.
*
* @param _api Structure with UART asynchronous API.
* @param _trampoline Function that trampolines to the interrupt context.
* @param _baudrate UART baudrate.
* @param _tx_buf TX buffer.
* @param _tx_len TX buffer length.
* @param _rx_buf RX buffer.
* @param _rx_len RX buffer length.
* @param _rx_cnt Number of chunks into which RX buffer is divided.
* @param _log Logging instance, if not provided (empty) then default is used.
*/
#define UART_ASYNC_TO_IRQ_API_CONFIG_INITIALIZER(_api, _trampoline, _baudrate, _tx_buf, \
_tx_len, _rx_buf, _rx_len, _rx_cnt, _log) \
{ \
.tx_buf = _tx_buf, \
.tx_len = _tx_len, \
.async_rx = { \
.buffer = _rx_buf, \
.length = _rx_len, \
.buf_cnt = _rx_cnt \
}, \
.api = _api, \
.trampoline = _trampoline, \
.baudrate = _baudrate, \
LOG_OBJECT_PTR_INIT(log, \
COND_CODE_1(IS_EMPTY(_log), \
(LOG_OBJECT_PTR(UART_ASYNC_TO_IRQ_LOG_NAME)), \
(_log) \
) \
) \
}
/** @brief Initialize the adaptation layer.
*
* @param data Data associated with the given adaptation layer instance.
* @param config Configuration structure. Must be persistent.
*
* @retval 0 On successful initialization.
*/
int uart_async_to_irq_init(struct uart_async_to_irq_data *data,
const struct uart_async_to_irq_config *config);
/* @brief Enable RX for interrupt driven API.
*
* @param dev UART device. Device must support asynchronous API.
*
* @retval 0 on successful operation.
* @retval -EINVAL if adaption layer has wrong configuration.
* @retval negative value Error reported by the UART API.
*/
int uart_async_to_irq_rx_enable(const struct device *dev);
/* @brief Disable RX for interrupt driven API.
*
* @param dev UART device. Device must support asynchronous API.
*
* @retval 0 on successful operation.
* @retval -EINVAL if adaption layer has wrong configuration.
* @retval negative value Error reported by the UART API.
*/
int uart_async_to_irq_rx_disable(const struct device *dev);
/* Starting from here API is internal only. */
/** @cond INTERNAL_HIDDEN
* @brief Structure used by the adaptation layer.
*/
struct uart_async_to_irq_config {
/** Pointer to the TX buffer. */
uint8_t *tx_buf;
/** TX buffer length. */
size_t tx_len;
/** UART Asynchronous RX helper configuration. */
struct uart_async_rx_config async_rx;
/** Async API used by the a2i layer. */
const struct uart_async_to_irq_async_api *api;
/** Trampoline callback. */
uart_async_to_irq_trampoline trampoline;
/** Initial baudrate. */
uint32_t baudrate;
/** Instance logging handler. */
LOG_INSTANCE_PTR_DECLARE(log);
};
/** @brief Asynchronous API used by the adaptation layer. */
struct uart_async_to_irq_async_api {
int (*callback_set)(const struct device *dev,
uart_callback_t callback,
void *user_data);
int (*tx)(const struct device *dev, const uint8_t *buf, size_t len,
int32_t timeout);
int (*tx_abort)(const struct device *dev);
int (*rx_enable)(const struct device *dev, uint8_t *buf, size_t len,
int32_t timeout);
int (*rx_buf_rsp)(const struct device *dev, uint8_t *buf, size_t len);
int (*rx_disable)(const struct device *dev);
};
/** @brief Structure holding receiver data. */
struct uart_async_to_irq_rx_data {
/** Asynchronous RX helper data. */
struct uart_async_rx async_rx;
/** Semaphore for pending on RX disable. */
struct k_sem sem;
/** Number of pending buffer requests which weren't handled because lack of free buffers. */
atomic_t pending_buf_req;
};
/** @brief Structure holding transmitter data. */
struct uart_async_to_irq_tx_data {
/** TX buffer. */
uint8_t *buf;
/** Length of the buffer. */
size_t len;
};
/** @briref Data associated with the asynchronous to the interrupt driven API adaptation layer. */
struct uart_async_to_irq_data {
/** User callback for interrupt driven API. */
uart_irq_callback_user_data_t callback;
/** User data. */
void *user_data;
/** Interrupt request counter. */
atomic_t irq_req;
/** RX specific data. */
struct uart_async_to_irq_rx_data rx;
/** TX specific data. */
struct uart_async_to_irq_tx_data tx;
/** Spinlock. */
struct k_spinlock lock;
/** Internally used flags for holding the state of the a2i layer. */
atomic_t flags;
};
/** Interrupt driven FIFO fill function. */
int z_uart_async_to_irq_fifo_fill(const struct device *dev,
const uint8_t *buf,
int len);
/** Interrupt driven FIFO read function. */
int z_uart_async_to_irq_fifo_read(const struct device *dev,
uint8_t *buf,
const int len);
/** Interrupt driven transfer enabling function. */
void z_uart_async_to_irq_irq_tx_enable(const struct device *dev);
/** Interrupt driven transfer disabling function */
void z_uart_async_to_irq_irq_tx_disable(const struct device *dev);
/** Interrupt driven transfer ready function */
int z_uart_async_to_irq_irq_tx_ready(const struct device *dev);
/** Interrupt driven receiver enabling function */
void z_uart_async_to_irq_irq_rx_enable(const struct device *dev);
/** Interrupt driven receiver disabling function */
void z_uart_async_to_irq_irq_rx_disable(const struct device *dev);
/** Interrupt driven transfer complete function */
int z_uart_async_to_irq_irq_tx_complete(const struct device *dev);
/** Interrupt driven receiver ready function */
int z_uart_async_to_irq_irq_rx_ready(const struct device *dev);
/** Interrupt driven error enabling function */
void z_uart_async_to_irq_irq_err_enable(const struct device *dev);
/** Interrupt driven error disabling function */
void z_uart_async_to_irq_irq_err_disable(const struct device *dev);
/** Interrupt driven pending status function */
int z_uart_async_to_irq_irq_is_pending(const struct device *dev);
/** Interrupt driven interrupt update function */
int z_uart_async_to_irq_irq_update(const struct device *dev);
/** Set the irq callback function */
void z_uart_async_to_irq_irq_callback_set(const struct device *dev,
uart_irq_callback_user_data_t cb,
void *user_data);
/** @endcond */
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_ASYNC_TO_IRQ_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/serial/uart_async_to_irq.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,084 |
```objective-c
/*
*
*/
/**
* Header file for the ALTERA UART
*/
#ifndef ZEPHYR_DRIVERS_SERIAL_UART_ALTERA_H_
#define ZEPHYR_DRIVERS_SERIAL_UART_ALTERA_H_
/* End of packet feature.
* Driver will trigger interrupt upon receiving end of package character.
* Please enable CONFIG_UART_DRV_CMD and CONFIG_UART_ALTERA_EOP to use this feature.
* Use the api: uart_drv_cmd with CMD_ENABLE_EOP to enable the feature.
* This cmd will write the ip register and also set a flag to the driver.
* The flag will modify uart_irq_callback_user_data_set
* to set call back function for eop interrupt.
* Flag is cleared after uart_irq_callback_user_data_set is called.
*/
#define CMD_ENABLE_EOP 0x01
#define CMD_DISABLE_EOP 0x02
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_ALTERA_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/serial/uart_altera.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 190 |
```objective-c
/*
*
*/
/**
* Header file for the INTEL LW UART
*/
#ifndef ZEPHYR_DRIVERS_SERIAL_UART_INTEL_LW_H_
#define ZEPHYR_DRIVERS_SERIAL_UART_INTEL_LW_H_
/* End of packet feature.
* Driver will trigger interrupt upon receiving end of package character.
* Please enable CONFIG_UART_INTEL_LW_EOP to use this feature.
* Use the api: uart_drv_cmd with CMD_ENABLE_EOP to enable the feature.
* This cmd will write the ip register and also set a flag to the driver.
* The flag will modify uart_irq_callback_user_data_set
* to set call back function for eop interrupt.
* Flag is cleared after uart_irq_callback_user_data_set is called.
*/
#define CMD_ENABLE_EOP 0x01
#define CMD_DISABLE_EOP 0x02
/* Transmit break feature.
* Use uart_drv_cmd with CMD_TRBK_EN to break ongoing transmit.
* After this cmd, uart is unable to transmit any data.
* Please use CMD_TRBK_DIS to resume normal operation.
* Please also call uart_intel_lw_err_check, to clear the error caused
* by transmit break.
*/
#define CMD_TRBK_EN 0x03
#define CMD_TRBK_DIS 0x04
/* This driver supports interrupt driven api.
* Polling for data under normal operation, might cause unexpected behaviour.
* If users wish to poll for data, please use the api:
* uart_drv_cmd with CMD_POLL_ASSERT_RTS before polling out/in.
* Then use CMD_POLL_DEASSERT_RTS to resume normal operation after polling.
*/
#define CMD_POLL_ASSERT_RTS 0x05
#define CMD_POLL_DEASSERT_RTS 0x06
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_INTEL_LW_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/serial/uart_intel_lw.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 376 |
```objective-c
/*
*
*/
/**
* @file
*
* @brief Public header file for the NS16550 UART
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SERIAL_UART_NS16550_H_
#define ZEPHYR_INCLUDE_DRIVERS_SERIAL_UART_NS16550_H_
/**
* @brief Set DLF
*
* @note This only applies to Synopsys Designware UART IP block.
*/
#define CMD_SET_DLF 0x01
#endif /* ZEPHYR_INCLUDE_DRIVERS_SERIAL_UART_NS16550_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/serial/uart_ns16550.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```objective-c
/*
*
*/
/**
* @file
* @brief Helper module for receiving using UART Asynchronous API.
*/
#ifndef ZEPHYR_DRIVERS_SERIAL_UART_ASYNC_RX_H_
#define ZEPHYR_DRIVERS_SERIAL_UART_ASYNC_RX_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/kernel.h>
/* @brief RX buffer structure which holds the buffer and its state. */
struct uart_async_rx_buf {
/* Write index which is incremented whenever new data is reported to be
* received to that buffer.
*/
uint8_t wr_idx:7;
/* Set to one if buffer is released by the driver. */
uint8_t completed:1;
/* Location which is passed to the UART driver. */
uint8_t buffer[];
};
/** @brief UART asynchronous RX helper structure. */
struct uart_async_rx {
/* Pointer to the configuration structure. Structure must be persistent. */
const struct uart_async_rx_config *config;
/* Total amount of pending bytes. Bytes may be spread across multiple RX buffers. */
atomic_t pending_bytes;
/* Number of buffers which are free. */
atomic_t free_buf_cnt;
/* Single buffer size. */
uint8_t buf_len;
/* Index of the next buffer to be provided to the driver. */
uint8_t drv_buf_idx;
/* Current buffer from which data is being consumed. */
uint8_t rd_buf_idx;
/* Current read index in the buffer from which data is being consumed.
* Read index which is incremented whenever data is consumed from the buffer.
*/
uint8_t rd_idx;
};
/** @brief UART asynchronous RX helper configuration structure. */
struct uart_async_rx_config {
/* Pointer to the buffer. */
uint8_t *buffer;
/* Buffer length. */
size_t length;
/* Number of buffers into provided space shall be split. */
uint8_t buf_cnt;
};
/** @brief Get RX buffer length.
*
* @param async_rx Pointer to the helper instance.
*
* @return Buffer length.
*/
static inline uint8_t uart_async_rx_get_buf_len(struct uart_async_rx *async_rx)
{
return async_rx->buf_len;
}
/** @brief Get amount of space dedicated for managing each buffer state.
*
* User buffer provided during the initialization is split into chunks and each
* chunk has overhead. This overhead can be used to calculate actual space used
* for UART data.
*
* @return Overhead space in bytes.
*/
#define UART_ASYNC_RX_BUF_OVERHEAD offsetof(struct uart_async_rx_buf, buffer)
/** @brief Initialize the helper instance.
*
* @param async_rx Pointer to the helper instance.
* @param config Configuration. Must be persistent.
*
* @retval 0 on successful initialization.
*/
int uart_async_rx_init(struct uart_async_rx *async_rx,
const struct uart_async_rx_config *config);
/** @brief Reset state of the helper instance.
*
* Helper can be reset after RX abort to discard all received data and bring
* the helper to its initial state.
*
* @param async_rx Pointer to the helper instance.
*/
void uart_async_rx_reset(struct uart_async_rx *async_rx);
/** @brief Indicate received data.
*
* Function shall be called from @ref UART_RX_RDY context.
*
* @param async_rx Pointer to the helper instance.
* @param buffer Buffer received in the UART driver event.
* @param length Length received in the UART driver event.
*/
void uart_async_rx_on_rdy(struct uart_async_rx *async_rx, uint8_t *buffer, size_t length);
/** @brief Get next RX buffer.
*
* Returned pointer shall be provided to @ref uart_rx_buf_rsp or @ref uart_rx_enable.
* If null is returned that indicates that there are no available buffers since all
* buffers are used by the driver or contain not consumed data.
*
* @param async_rx Pointer to the helper instance.
*
* @return Pointer to the next RX buffer or null if no buffer available.
*/
uint8_t *uart_async_rx_buf_req(struct uart_async_rx *async_rx);
/** @brief Indicate that buffer is no longer used by the UART driver.
*
* Function shall be called on @ref UART_RX_BUF_RELEASED event.
*
* @param async_rx Pointer to the helper instance.
* @param buf Buffer pointer received in the UART driver event.
*/
void uart_async_rx_on_buf_rel(struct uart_async_rx *async_rx, uint8_t *buf);
/** @brief Claim received data for processing.
*
* Helper module works in the zero copy mode. It provides a pointer to the buffer
* that was directly used by the UART driver. Since received data is spread across
* multiple buffers there is no possibility to read all data at once. It can only be
* consumed in chunks. After data is processed, @ref uart_async_rx_data_consume is
* used to indicate that data is consumed.
*
* @param async_rx Pointer to the helper instance.
* @param data Location where address to the buffer is written. Untouched if no data to claim.
* @param length Amount of requested data.
*
* @return Amount valid of data in the @p data buffer. 0 is returned when there is no data.
*/
size_t uart_async_rx_data_claim(struct uart_async_rx *async_rx, uint8_t **data, size_t length);
/** @brief Consume claimed data.
*
* It pairs with @ref uart_async_rx_data_claim.
*
* @param async_rx Pointer to the helper instance.
* @param length Amount of data to consume. It must be less or equal than amount of claimed data.
*
* @retval true If there are free buffers in the pool after data got consumed.
* @retval false If there are no free buffers.
*/
bool uart_async_rx_data_consume(struct uart_async_rx *async_rx, size_t length);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_ASYNC_RX_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/serial/uart_async_rx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,231 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_LED_LP50XX_H_
#define ZEPHYR_INCLUDE_DRIVERS_LED_LP50XX_H_
#define LP50XX_COLORS_PER_LED 3
#define LP5009_MAX_LEDS 3
#define LP5012_MAX_LEDS 4
#define LP5018_MAX_LEDS 6
#define LP5024_MAX_LEDS 8
#define LP5030_MAX_LEDS 10
#define LP5036_MAX_LEDS 12
/*
* LED channels mapping.
*/
/* Bank channels */
#define LP50XX_BANK_CHAN_BASE 0
#define LP50XX_BANK_BRIGHT_CHAN LP50XX_BANK_CHAN_BASE
#define LP50XX_BANK_COL1_CHAN(led) (LP50XX_BANK_CHAN_BASE + 1)
#define LP50XX_BANK_COL2_CHAN(led) (LP50XX_BANK_CHAN_BASE + 2)
#define LP50XX_BANK_COL3_CHAN(led) (LP50XX_BANK_CHAN_BASE + 3)
/* LED brightness channels. */
#define LP50XX_LED_BRIGHT_CHAN_BASE 4
#define LP50XX_LED_BRIGHT_CHAN(led) (LP50XX_LED_BRIGHT_CHAN_BASE + led)
/*
* LED color channels.
*
* Each channel definition is compatible with the following chips:
* - LP5012_XXX => LP5009 / LP5012
* - LP5024_XXX => LP5018 / LP5024
* - LP5036_XXX => LP5030 / LP5036
*/
#define LP5012_LED_COL_CHAN_BASE 8
#define LP5012_LED_COL1_CHAN(led) \
(LP5012_LED_COL_CHAN_BASE + led * LP50XX_COLORS_PER_LED)
#define LP5012_LED_COL2_CHAN(led) \
(LP5012_LED_COL_CHAN_BASE + led * LP50XX_COLORS_PER_LED + 1)
#define LP5012_LED_COL3_CHAN(led) \
(LP5012_LED_COL_CHAN_BASE + led * LP50XX_COLORS_PER_LED + 2)
#define LP5024_LED_COL_CHAN_BASE 12
#define LP5024_LED_COL1_CHAN(led) \
(LP5024_LED_COL_CHAN_BASE + led * LP50XX_COLORS_PER_LED)
#define LP5024_LED_COL2_CHAN(led) \
(LP5024_LED_COL_CHAN_BASE + led * LP50XX_COLORS_PER_LED + 1)
#define LP5024_LED_COL3_CHAN(led) \
(LP5024_LED_COL_CHAN_BASE + led * LP50XX_COLORS_PER_LED + 2)
#define LP5036_LED_COL_CHAN_BASE 16
#define LP5036_LED_COL1_CHAN(led) \
(LP5036_LED_COL_CHAN_BASE + led * LP50XX_COLORS_PER_LED)
#define LP5036_LED_COL2_CHAN(led) \
(LP5036_LED_COL_CHAN_BASE + led * LP50XX_COLORS_PER_LED + 1)
#define LP5036_LED_COL3_CHAN(led) \
(LP5036_LED_COL_CHAN_BASE + led * LP50XX_COLORS_PER_LED + 2)
#endif /* ZEPHYR_INCLUDE_DRIVERS_LED_LP50XX_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/led/lp50xx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 660 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_LED_IS31FL3733_H_
#define ZEPHYR_INCLUDE_DRIVERS_LED_IS31FL3733_H_
/**
* @brief Blanks IS31FL3733 LED display.
*
* When blank_en is set, the LED display will be disabled. This can be used for
* flicker-free display updates, or power saving.
*
* @param dev: LED device structure
* @param blank_en: should blanking be enabled
* @return 0 on success, or negative value on error.
*/
int is31fl3733_blank(const struct device *dev, bool blank_en);
/**
* @brief Sets led current limit
*
* Sets the current limit for the LED driver. This is a separate value
* from per-led brightness, and applies to all LEDs.
* This value sets the output current limit according
* to the following formula: (840/R_ISET) * (limit/256)
* See table 14 of the datasheet for additional details.
* @param dev: LED device structure
* @param limit: current limit to apply
* @return 0 on success, or negative value on error.
*/
int is31fl3733_current_limit(const struct device *dev, uint8_t limit);
#endif /* ZEPHYR_INCLUDE_DRIVERS_LED_IS31FL3733_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/led/is31fl3733.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 286 |
```objective-c
/*
*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_MCAN_H_
#define ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_MCAN_H_
#include <zephyr/cache.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/can.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/util.h>
/*
* The Bosch M_CAN register definitions correspond to those found in the Bosch M_CAN Controller Area
* Network User's Manual, Revision 3.3.0.
*/
/* Core Release register */
#define CAN_MCAN_CREL 0x000
#define CAN_MCAN_CREL_REL GENMASK(31, 28)
#define CAN_MCAN_CREL_STEP GENMASK(27, 24)
#define CAN_MCAN_CREL_SUBSTEP GENMASK(23, 20)
#define CAN_MCAN_CREL_YEAR GENMASK(19, 16)
#define CAN_MCAN_CREL_MON GENMASK(15, 8)
#define CAN_MCAN_CREL_DAY GENMASK(7, 0)
/* Endian register */
#define CAN_MCAN_ENDN 0x004
#define CAN_MCAN_ENDN_ETV GENMASK(31, 0)
/* Customer register */
#define CAN_MCAN_CUST 0x008
#define CAN_MCAN_CUST_CUST GENMASK(31, 0)
/* Data Bit Timing & Prescaler register */
#define CAN_MCAN_DBTP 0x00C
#define CAN_MCAN_DBTP_TDC BIT(23)
#define CAN_MCAN_DBTP_DBRP GENMASK(20, 16)
#define CAN_MCAN_DBTP_DTSEG1 GENMASK(12, 8)
#define CAN_MCAN_DBTP_DTSEG2 GENMASK(7, 4)
#define CAN_MCAN_DBTP_DSJW GENMASK(3, 0)
/* Test register */
#define CAN_MCAN_TEST 0x010
#define CAN_MCAN_TEST_SVAL BIT(21)
#define CAN_MCAN_TEST_TXBNS GENMASK(20, 16)
#define CAN_MCAN_TEST_PVAL BIT(13)
#define CAN_MCAN_TEST_TXBNP GENMASK(12, 8)
#define CAN_MCAN_TEST_RX BIT(7)
#define CAN_MCAN_TEST_TX GENMASK(6, 5)
#define CAN_MCAN_TEST_LBCK BIT(4)
/* RAM Watchdog register */
#define CAN_MCAN_RWD 0x014
#define CAN_MCAN_RWD_WDV GENMASK(15, 8)
#define CAN_MCAN_RWD_WDC GENMASK(7, 0)
/* CC Control register */
#define CAN_MCAN_CCCR 0x018
#define CAN_MCAN_CCCR_NISO BIT(15)
#define CAN_MCAN_CCCR_TXP BIT(14)
#define CAN_MCAN_CCCR_EFBI BIT(13)
#define CAN_MCAN_CCCR_PXHD BIT(12)
#define CAN_MCAN_CCCR_WMM BIT(11)
#define CAN_MCAN_CCCR_UTSU BIT(10)
#define CAN_MCAN_CCCR_BRSE BIT(9)
#define CAN_MCAN_CCCR_FDOE BIT(8)
#define CAN_MCAN_CCCR_TEST BIT(7)
#define CAN_MCAN_CCCR_DAR BIT(6)
#define CAN_MCAN_CCCR_MON BIT(5)
#define CAN_MCAN_CCCR_CSR BIT(4)
#define CAN_MCAN_CCCR_CSA BIT(3)
#define CAN_MCAN_CCCR_ASM BIT(2)
#define CAN_MCAN_CCCR_CCE BIT(1)
#define CAN_MCAN_CCCR_INIT BIT(0)
/* Nominal Bit Timing & Prescaler register */
#define CAN_MCAN_NBTP 0x01C
#define CAN_MCAN_NBTP_NSJW GENMASK(31, 25)
#define CAN_MCAN_NBTP_NBRP GENMASK(24, 16)
#define CAN_MCAN_NBTP_NTSEG1 GENMASK(15, 8)
#define CAN_MCAN_NBTP_NTSEG2 GENMASK(6, 0)
/* Timestamp Counter Configuration register */
#define CAN_MCAN_TSCC 0x020
#define CAN_MCAN_TSCC_TCP GENMASK(19, 16)
#define CAN_MCAN_TSCC_TSS GENMASK(1, 0)
/* Timestamp Counter Value register */
#define CAN_MCAN_TSCV 0x024
#define CAN_MCAN_TSCV_TSC GENMASK(15, 0)
/* Timeout Counter Configuration register */
#define CAN_MCAN_TOCC 0x028
#define CAN_MCAN_TOCC_TOP GENMASK(31, 16)
#define CAN_MCAN_TOCC_TOS GENMASK(2, 1)
#define CAN_MCAN_TOCC_ETOC BIT(1)
/* Timeout Counter Value register */
#define CAN_MCAN_TOCV 0x02C
#define CAN_MCAN_TOCV_TOC GENMASK(15, 0)
/* Error Counter register */
#define CAN_MCAN_ECR 0x040
#define CAN_MCAN_ECR_CEL GENMASK(23, 16)
#define CAN_MCAN_ECR_RP BIT(15)
#define CAN_MCAN_ECR_REC GENMASK(14, 8)
#define CAN_MCAN_ECR_TEC GENMASK(7, 0)
/* Protocol Status register */
#define CAN_MCAN_PSR 0x044
#define CAN_MCAN_PSR_TDCV GENMASK(22, 16)
#define CAN_MCAN_PSR_PXE BIT(14)
#define CAN_MCAN_PSR_RFDF BIT(13)
#define CAN_MCAN_PSR_RBRS BIT(12)
#define CAN_MCAN_PSR_RESI BIT(11)
#define CAN_MCAN_PSR_DLEC GENMASK(10, 8)
#define CAN_MCAN_PSR_BO BIT(7)
#define CAN_MCAN_PSR_EW BIT(6)
#define CAN_MCAN_PSR_EP BIT(5)
#define CAN_MCAN_PSR_ACT GENMASK(4, 3)
#define CAN_MCAN_PSR_LEC GENMASK(2, 0)
enum can_mcan_psr_lec {
CAN_MCAN_PSR_LEC_NO_ERROR = 0,
CAN_MCAN_PSR_LEC_STUFF_ERROR = 1,
CAN_MCAN_PSR_LEC_FORM_ERROR = 2,
CAN_MCAN_PSR_LEC_ACK_ERROR = 3,
CAN_MCAN_PSR_LEC_BIT1_ERROR = 4,
CAN_MCAN_PSR_LEC_BIT0_ERROR = 5,
CAN_MCAN_PSR_LEC_CRC_ERROR = 6,
CAN_MCAN_PSR_LEC_NO_CHANGE = 7
};
/* Transmitter Delay Compensation register */
#define CAN_MCAN_TDCR 0x048
#define CAN_MCAN_TDCR_TDCO GENMASK(14, 8)
#define CAN_MCAN_TDCR_TDCF GENMASK(6, 0)
/* Interrupt register */
#define CAN_MCAN_IR 0x050
#define CAN_MCAN_IR_ARA BIT(29)
#define CAN_MCAN_IR_PED BIT(28)
#define CAN_MCAN_IR_PEA BIT(27)
#define CAN_MCAN_IR_WDI BIT(26)
#define CAN_MCAN_IR_BO BIT(25)
#define CAN_MCAN_IR_EW BIT(24)
#define CAN_MCAN_IR_EP BIT(23)
#define CAN_MCAN_IR_ELO BIT(22)
#define CAN_MCAN_IR_BEU BIT(21)
#define CAN_MCAN_IR_BEC BIT(20)
#define CAN_MCAN_IR_DRX BIT(19)
#define CAN_MCAN_IR_TOO BIT(18)
#define CAN_MCAN_IR_MRAF BIT(17)
#define CAN_MCAN_IR_TSW BIT(16)
#define CAN_MCAN_IR_TEFL BIT(15)
#define CAN_MCAN_IR_TEFF BIT(14)
#define CAN_MCAN_IR_TEFW BIT(13)
#define CAN_MCAN_IR_TEFN BIT(12)
#define CAN_MCAN_IR_TFE BIT(11)
#define CAN_MCAN_IR_TCF BIT(10)
#define CAN_MCAN_IR_TC BIT(9)
#define CAN_MCAN_IR_HPM BIT(8)
#define CAN_MCAN_IR_RF1L BIT(7)
#define CAN_MCAN_IR_RF1F BIT(6)
#define CAN_MCAN_IR_RF1W BIT(5)
#define CAN_MCAN_IR_RF1N BIT(4)
#define CAN_MCAN_IR_RF0L BIT(3)
#define CAN_MCAN_IR_RF0F BIT(2)
#define CAN_MCAN_IR_RF0W BIT(1)
#define CAN_MCAN_IR_RF0N BIT(0)
/* Interrupt Enable register */
#define CAN_MCAN_IE 0x054
#define CAN_MCAN_IE_ARAE BIT(29)
#define CAN_MCAN_IE_PEDE BIT(28)
#define CAN_MCAN_IE_PEAE BIT(27)
#define CAN_MCAN_IE_WDIE BIT(26)
#define CAN_MCAN_IE_BOE BIT(25)
#define CAN_MCAN_IE_EWE BIT(24)
#define CAN_MCAN_IE_EPE BIT(23)
#define CAN_MCAN_IE_ELOE BIT(22)
#define CAN_MCAN_IE_BEUE BIT(21)
#define CAN_MCAN_IE_BECE BIT(20)
#define CAN_MCAN_IE_DRXE BIT(19)
#define CAN_MCAN_IE_TOOE BIT(18)
#define CAN_MCAN_IE_MRAFE BIT(17)
#define CAN_MCAN_IE_TSWE BIT(16)
#define CAN_MCAN_IE_TEFLE BIT(15)
#define CAN_MCAN_IE_TEFFE BIT(14)
#define CAN_MCAN_IE_TEFWE BIT(13)
#define CAN_MCAN_IE_TEFNE BIT(12)
#define CAN_MCAN_IE_TFEE BIT(11)
#define CAN_MCAN_IE_TCFE BIT(10)
#define CAN_MCAN_IE_TCE BIT(9)
#define CAN_MCAN_IE_HPME BIT(8)
#define CAN_MCAN_IE_RF1LE BIT(7)
#define CAN_MCAN_IE_RF1FE BIT(6)
#define CAN_MCAN_IE_RF1WE BIT(5)
#define CAN_MCAN_IE_RF1NE BIT(4)
#define CAN_MCAN_IE_RF0LE BIT(3)
#define CAN_MCAN_IE_RF0FE BIT(2)
#define CAN_MCAN_IE_RF0WE BIT(1)
#define CAN_MCAN_IE_RF0NE BIT(0)
/* Interrupt Line Select register */
#define CAN_MCAN_ILS 0x058
#define CAN_MCAN_ILS_ARAL BIT(29)
#define CAN_MCAN_ILS_PEDL BIT(28)
#define CAN_MCAN_ILS_PEAL BIT(27)
#define CAN_MCAN_ILS_WDIL BIT(26)
#define CAN_MCAN_ILS_BOL BIT(25)
#define CAN_MCAN_ILS_EWL BIT(24)
#define CAN_MCAN_ILS_EPL BIT(23)
#define CAN_MCAN_ILS_ELOL BIT(22)
#define CAN_MCAN_ILS_BEUL BIT(21)
#define CAN_MCAN_ILS_BECL BIT(20)
#define CAN_MCAN_ILS_DRXL BIT(19)
#define CAN_MCAN_ILS_TOOL BIT(18)
#define CAN_MCAN_ILS_MRAFL BIT(17)
#define CAN_MCAN_ILS_TSWL BIT(16)
#define CAN_MCAN_ILS_TEFLL BIT(15)
#define CAN_MCAN_ILS_TEFFL BIT(14)
#define CAN_MCAN_ILS_TEFWL BIT(13)
#define CAN_MCAN_ILS_TEFNL BIT(12)
#define CAN_MCAN_ILS_TFEL BIT(11)
#define CAN_MCAN_ILS_TCFL BIT(10)
#define CAN_MCAN_ILS_TCL BIT(9)
#define CAN_MCAN_ILS_HPML BIT(8)
#define CAN_MCAN_ILS_RF1LL BIT(7)
#define CAN_MCAN_ILS_RF1FL BIT(6)
#define CAN_MCAN_ILS_RF1WL BIT(5)
#define CAN_MCAN_ILS_RF1NL BIT(4)
#define CAN_MCAN_ILS_RF0LL BIT(3)
#define CAN_MCAN_ILS_RF0FL BIT(2)
#define CAN_MCAN_ILS_RF0WL BIT(1)
#define CAN_MCAN_ILS_RF0NL BIT(0)
/* Interrupt Line Enable register */
#define CAN_MCAN_ILE 0x05C
#define CAN_MCAN_ILE_EINT1 BIT(1)
#define CAN_MCAN_ILE_EINT0 BIT(0)
/* Global filter configuration register */
#define CAN_MCAN_GFC 0x080
#define CAN_MCAN_GFC_ANFS GENMASK(5, 4)
#define CAN_MCAN_GFC_ANFE GENMASK(3, 2)
#define CAN_MCAN_GFC_RRFS BIT(1)
#define CAN_MCAN_GFC_RRFE BIT(0)
/* Standard ID Filter Configuration register */
#define CAN_MCAN_SIDFC 0x084
#define CAN_MCAN_SIDFC_LSS GENMASK(23, 16)
#define CAN_MCAN_SIDFC_FLSSA GENMASK(15, 2)
/* Extended ID Filter Configuration register */
#define CAN_MCAN_XIDFC 0x088
#define CAN_MCAN_XIDFC_LSS GENMASK(22, 16)
#define CAN_MCAN_XIDFC_FLESA GENMASK(15, 2)
/* Extended ID AND Mask register */
#define CAN_MCAN_XIDAM 0x090
#define CAN_MCAN_XIDAM_EIDM GENMASK(28, 0)
/* High Priority Message Status register */
#define CAN_MCAN_HPMS 0x094
#define CAN_MCAN_HPMS_FLST BIT(15)
#define CAN_MCAN_HPMS_FIDX GENMASK(14, 8)
#define CAN_MCAN_HPMS_MSI GENMASK(7, 6)
#define CAN_MCAN_HPMS_BIDX GENMASK(5, 0)
/* New Data 1 register */
#define CAN_MCAN_NDAT1 0x098
#define CAN_MCAN_NDAT1_ND GENMASK(31, 0)
/* New Data 2 register */
#define CAN_MCAN_NDAT2 0x09C
#define CAN_MCAN_NDAT2_ND GENMASK(31, 0)
/* Rx FIFO 0 Configuration register */
#define CAN_MCAN_RXF0C 0x0A0
#define CAN_MCAN_RXF0C_F0OM BIT(31)
#define CAN_MCAN_RXF0C_F0WM GENMASK(30, 24)
#define CAN_MCAN_RXF0C_F0S GENMASK(22, 16)
#define CAN_MCAN_RXF0C_F0SA GENMASK(15, 2)
/* Rx FIFO 0 Status register */
#define CAN_MCAN_RXF0S 0x0A4
#define CAN_MCAN_RXF0S_RF0L BIT(25)
#define CAN_MCAN_RXF0S_F0F BIT(24)
#define CAN_MCAN_RXF0S_F0PI GENMASK(21, 16)
#define CAN_MCAN_RXF0S_F0GI GENMASK(13, 8)
#define CAN_MCAN_RXF0S_F0FL GENMASK(6, 0)
/* Rx FIFO 0 Acknowledge register */
#define CAN_MCAN_RXF0A 0x0A8
#define CAN_MCAN_RXF0A_F0AI GENMASK(5, 0)
/* Rx Buffer Configuration register */
#define CAN_MCAN_RXBC 0x0AC
#define CAN_MCAN_RXBC_RBSA GENMASK(15, 2)
/* Rx FIFO 1 Configuration register */
#define CAN_MCAN_RXF1C 0x0B0
#define CAN_MCAN_RXF1C_F1OM BIT(31)
#define CAN_MCAN_RXF1C_F1WM GENMASK(30, 24)
#define CAN_MCAN_RXF1C_F1S GENMASK(22, 16)
#define CAN_MCAN_RXF1C_F1SA GENMASK(15, 2)
/* Rx FIFO 1 Status register */
#define CAN_MCAN_RXF1S 0x0B4
#define CAN_MCAN_RXF1S_RF1L BIT(25)
#define CAN_MCAN_RXF1S_F1F BIT(24)
#define CAN_MCAN_RXF1S_F1PI GENMASK(21, 16)
#define CAN_MCAN_RXF1S_F1GI GENMASK(13, 8)
#define CAN_MCAN_RXF1S_F1FL GENMASK(6, 0)
/* Rx FIFO 1 Acknowledge register */
#define CAN_MCAN_RXF1A 0x0B8
#define CAN_MCAN_RXF1A_F1AI GENMASK(5, 0)
/* Rx Buffer/FIFO Element Size Configuration register */
#define CAN_MCAN_RXESC 0x0BC
#define CAN_MCAN_RXESC_RBDS GENMASK(10, 8)
#define CAN_MCAN_RXESC_F1DS GENMASK(6, 4)
#define CAN_MCAN_RXESC_F0DS GENMASK(2, 0)
/* Tx Buffer Configuration register */
#define CAN_MCAN_TXBC 0x0C0
#define CAN_MCAN_TXBC_TFQM BIT(30)
#define CAN_MCAN_TXBC_TFQS GENMASK(29, 24)
#define CAN_MCAN_TXBC_NDTB GENMASK(21, 16)
#define CAN_MCAN_TXBC_TBSA GENMASK(15, 2)
/* Tx FIFO/Queue Status register */
#define CAN_MCAN_TXFQS 0x0C4
#define CAN_MCAN_TXFQS_TFQF BIT(21)
#define CAN_MCAN_TXFQS_TFQPI GENMASK(20, 16)
#define CAN_MCAN_TXFQS_TFGI GENMASK(12, 8)
#define CAN_MCAN_TXFQS_TFFL GENMASK(5, 0)
/* Tx Buffer Element Size Configuration register */
#define CAN_MCAN_TXESC 0x0C8
#define CAN_MCAN_TXESC_TBDS GENMASK(2, 0)
/* Tx Buffer Request Pending register */
#define CAN_MCAN_TXBRP 0x0CC
#define CAN_MCAN_TXBRP_TRP GENMASK(31, 0)
/* Tx Buffer Add Request register */
#define CAN_MCAN_TXBAR 0x0D0
#define CAN_MCAN_TXBAR_AR GENMASK(31, 0)
/* Tx Buffer Cancellation Request register */
#define CAN_MCAN_TXBCR 0x0D4
#define CAN_MCAN_TXBCR_CR GENMASK(31, 0)
/* Tx Buffer Transmission Occurred register */
#define CAN_MCAN_TXBTO 0x0D8
#define CAN_MCAN_TXBTO_TO GENMASK(31, 0)
/* Tx Buffer Cancellation Finished register */
#define CAN_MCAN_TXBCF 0x0DC
#define CAN_MCAN_TXBCF_CF GENMASK(31, 0)
/* Tx Buffer Transmission Interrupt Enable register */
#define CAN_MCAN_TXBTIE 0x0E0
#define CAN_MCAN_TXBTIE_TIE GENMASK(31, 0)
/* Tx Buffer Cancellation Finished Interrupt Enable register */
#define CAN_MCAN_TXBCIE 0x0E4
#define CAN_MCAN_TXBCIE_CFIE GENMASK(31, 0)
/* Tx Event FIFO Configuration register */
#define CAN_MCAN_TXEFC 0x0F0
#define CAN_MCAN_TXEFC_EFWM GENMASK(29, 24)
#define CAN_MCAN_TXEFC_EFS GENMASK(21, 16)
#define CAN_MCAN_TXEFC_EFSA GENMASK(15, 2)
/* Tx Event FIFO Status register */
#define CAN_MCAN_TXEFS 0x0F4
#define CAN_MCAN_TXEFS_TEFL BIT(25)
#define CAN_MCAN_TXEFS_EFF BIT(24)
#define CAN_MCAN_TXEFS_EFPI GENMASK(20, 16)
#define CAN_MCAN_TXEFS_EFGI GENMASK(12, 8)
#define CAN_MCAN_TXEFS_EFFL GENMASK(5, 0)
/* Tx Event FIFO Acknowledge register */
#define CAN_MCAN_TXEFA 0x0F8
#define CAN_MCAN_TXEFA_EFAI GENMASK(4, 0)
/**
* @name Indexes for the cells in the devicetree bosch,mram-cfg property
* @anchor CAN_MCAN_MRAM_CFG
* These match the description of the cells in the bosch,m_can-base devicetree binding.
*
* @{
*/
/** offset cell index */
#define CAN_MCAN_MRAM_CFG_OFFSET 0
/** std-filter-elements cell index */
#define CAN_MCAN_MRAM_CFG_STD_FILTER 1
/** ext-filter-elements cell index */
#define CAN_MCAN_MRAM_CFG_EXT_FILTER 2
/** rx-fifo0-elements cell index */
#define CAN_MCAN_MRAM_CFG_RX_FIFO0 3
/** rx-fifo1-elements cell index */
#define CAN_MCAN_MRAM_CFG_RX_FIFO1 4
/** rx-buffer-elements cell index */
#define CAN_MCAN_MRAM_CFG_RX_BUFFER 5
/** tx-event-fifo-elements cell index */
#define CAN_MCAN_MRAM_CFG_TX_EVENT_FIFO 6
/** tx-buffer-elements cell index */
#define CAN_MCAN_MRAM_CFG_TX_BUFFER 7
/** Total number of cells in bosch,mram-cfg property */
#define CAN_MCAN_MRAM_CFG_NUM_CELLS 8
/** @} */
/**
* @brief Get the Bosch M_CAN Message RAM offset
*
* @param node_id node identifier
* @return the Message RAM offset in bytes
*/
#define CAN_MCAN_DT_MRAM_OFFSET(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_OFFSET)
/**
* @brief Get the number of standard (11-bit) filter elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of standard (11-bit) filter elements
*/
#define CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_STD_FILTER)
/**
* @brief Get the number of extended (29-bit) filter elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of extended (29-bit) filter elements
*/
#define CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_EXT_FILTER)
/**
* @brief Get the number of Rx FIFO 0 elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Rx FIFO 0 elements
*/
#define CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_RX_FIFO0)
/**
* @brief Get the number of Rx FIFO 1 elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Rx FIFO 1 elements
*/
#define CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_RX_FIFO1)
/**
* @brief Get the number of Rx Buffer elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Rx Buffer elements
*/
#define CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_RX_BUFFER)
/**
* @brief Get the number of Tx Event FIFO elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Tx Event FIFO elements
*/
#define CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_TX_EVENT_FIFO)
/**
* @brief Get the number of Tx Buffer elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Tx Buffer elements
*/
#define CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_TX_BUFFER)
/**
* @brief Get the base offset of standard (11-bit) filter elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of standard (11-bit) filter elements in bytes
*/
#define CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET(node_id) (0U)
/**
* @brief Get the base offset of extended (29-bit) filter elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of extended (29-bit) filter elements in bytes
*/
#define CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(node_id) * sizeof(struct can_mcan_std_filter))
/**
* @brief Get the base offset of Rx FIFO 0 elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Rx FIFO 0 elements in bytes
*/
#define CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(node_id) * sizeof(struct can_mcan_ext_filter))
/**
* @brief Get the base offset of Rx FIFO 1 elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Rx FIFO 1 elements in bytes
*/
#define CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(node_id) * sizeof(struct can_mcan_rx_fifo))
/**
* @brief Get the base offset of Rx Buffer elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Rx Buffer elements in bytes
*/
#define CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(node_id) * sizeof(struct can_mcan_rx_fifo))
/**
* @brief Get the base offset of Tx Event FIFO elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Tx Event FIFO elements in bytes
*/
#define CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(node_id) * sizeof(struct can_mcan_rx_fifo))
/**
* @brief Get the base offset of Tx Buffer elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Tx Buffer elements in bytes
*/
#define CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(node_id) * sizeof(struct can_mcan_tx_event_fifo))
/**
* @brief Get the Bosch M_CAN register base address
*
* For devicetree nodes with just one register block, this macro returns the base address of that
* register block.
*
* If a devicetree node has more than one register block, this macros returns the base address of
* the register block named "m_can".
*
* @param node_id node identifier
* @return the Bosch M_CAN register base address
*/
#define CAN_MCAN_DT_MCAN_ADDR(node_id) \
COND_CODE_1(DT_NUM_REGS(node_id), ((mm_reg_t)DT_REG_ADDR(node_id)), \
((mm_reg_t)DT_REG_ADDR_BY_NAME(node_id, m_can)))
/**
* @brief Get the Bosch M_CAN Message RAM base address
*
* For devicetree nodes with dedicated Message RAM area defined via devicetree, this macro returns
* the base address of the Message RAM.
*
* @param node_id node identifier
* @return the Bosch M_CAN Message RAM base address (MRBA)
*/
#define CAN_MCAN_DT_MRBA(node_id) \
(mem_addr_t)DT_REG_ADDR_BY_NAME(node_id, message_ram)
/**
* @brief Get the Bosch M_CAN Message RAM address
*
* For devicetree nodes with dedicated Message RAM area defined via devicetree, this macro returns
* the address of the Message RAM, taking in the Message RAM offset into account.
*
* @param node_id node identifier
* @return the Bosch M_CAN Message RAM address
*/
#define CAN_MCAN_DT_MRAM_ADDR(node_id) \
(mem_addr_t)(CAN_MCAN_DT_MRBA(node_id) + CAN_MCAN_DT_MRAM_OFFSET(node_id))
/**
* @brief Get the Bosch M_CAN Message RAM size
*
* For devicetree nodes with dedicated Message RAM area defined via devicetree, this macro returns
* the size of the Message RAM, taking in the Message RAM offset into account.
*
* @param node_id node identifier
* @return the Bosch M_CAN Message RAM base address
* @see CAN_MCAN_DT_MRAM_ELEMENTS_SIZE()
*/
#define CAN_MCAN_DT_MRAM_SIZE(node_id) \
(mem_addr_t)(DT_REG_SIZE_BY_NAME(node_id, message_ram) - CAN_MCAN_DT_MRAM_OFFSET(node_id))
/**
* @brief Get the total size of all Bosch M_CAN Message RAM elements
*
* @param node_id node identifier
* @return the total size of all Message RAM elements in bytes
* @see CAN_MCAN_DT_MRAM_SIZE()
*/
#define CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(node_id) \
(CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(node_id) * sizeof(struct can_mcan_tx_buffer))
/**
* @brief Define a RAM buffer for Bosch M_CAN Message RAM
*
* For devicetree nodes without dedicated Message RAM area, this macro defines a suitable RAM buffer
* to hold the Message RAM elements. Since this buffer cannot be shared between multiple Bosch M_CAN
* instances, the Message RAM offset must be set to 0x0.
*
* @param node_id node identifier
* @param _name buffer variable name
*/
#define CAN_MCAN_DT_MRAM_DEFINE(node_id, _name) \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_OFFSET(node_id) == 0, "offset must be 0"); \
static char __nocache_noinit __aligned(4) _name[CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(node_id)];
/**
* @brief Assert that the Message RAM configuration meets the Bosch M_CAN IP core restrictions
*
* @param node_id node identifier
*/
#define CAN_MCAN_DT_BUILD_ASSERT_MRAM_CFG(node_id) \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(node_id) <= 128, \
"Maximum Standard filter elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(node_id) <= 64, \
"Maximum Extended filter elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(node_id) <= 64, \
"Maximum Rx FIFO 0 elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(node_id) <= 64, \
"Maximum Rx FIFO 1 elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(node_id) <= 64, \
"Maximum Rx Buffer elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(node_id) <= 32, \
"Maximum Tx Buffer elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(node_id) <= 32, \
"Maximum Tx Buffer elements exceeded");
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Message RAM offset in bytes
* @see CAN_MCAN_DT_MRAM_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_OFFSET(inst) CAN_MCAN_DT_MRAM_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of standard (11-bit) elements
* @see CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_STD_FILTER_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of extended (29-bit) elements
* @see CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_EXT_FILTER_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Rx FIFO 0 elements
* @see CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_FIFO0_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Rx FIFO 1 elements
* @see CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_FIFO1_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Rx Buffer elements
* @see CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_BUFFER_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Tx Event FIFO elements
* @see CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_TX_EVENT_FIFO_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Tx Buffer elements
* @see CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_TX_BUFFER_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of standard (11-bit) filter elements in bytes
* @see CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_STD_FILTER_OFFSET(inst) \
CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of extended (29-bit) filter elements in bytes
* @see CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_EXT_FILTER_OFFSET(inst) \
CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Rx FIFO 0 elements in bytes
* @see CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_FIFO0_OFFSET(inst) \
CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Rx FIFO 1 elements in bytes
* @see CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_FIFO1_OFFSET(inst) \
CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Rx Buffer elements in bytes
* @see CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_BUFFER_OFFSET(inst) \
CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Tx Event FIFO elements in bytes
* @see CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_TX_EVENT_FIFO_OFFSET(inst) \
CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Tx Buffer elements in bytes
* @see CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_TX_BUFFER_OFFSET(inst) \
CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MCAN_ADDR(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Bosch M_CAN register base address
* @see CAN_MCAN_DT_MRAM_ADDR()
*/
#define CAN_MCAN_DT_INST_MCAN_ADDR(inst) CAN_MCAN_DT_MCAN_ADDR(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRBA(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Bosch M_CAN Message RAM Base Address (MRBA)
* @see CAN_MCAN_DT_MRBA()
*/
#define CAN_MCAN_DT_INST_MRBA(inst) CAN_MCAN_DT_MRBA(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_ADDR(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Bosch M_CAN Message RAM address
* @see CAN_MCAN_DT_MRAM_ADDR()
*/
#define CAN_MCAN_DT_INST_MRAM_ADDR(inst) CAN_MCAN_DT_MRAM_ADDR(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_SIZE(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Bosch M_CAN Message RAM size in bytes
* @see CAN_MCAN_DT_MRAM_SIZE()
*/
#define CAN_MCAN_DT_INST_MRAM_SIZE(inst) CAN_MCAN_DT_MRAM_SIZE(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the total size of all Message RAM elements in bytes
* @see CAN_MCAN_DT_MRAM_ELEMENTS_SIZE()
*/
#define CAN_MCAN_DT_INST_MRAM_ELEMENTS_SIZE(inst) CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_DEFINE(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @param _name buffer variable name
* @see CAN_MCAN_DT_MRAM_DEFINE()
*/
#define CAN_MCAN_DT_INST_MRAM_DEFINE(inst, _name) CAN_MCAN_DT_MRAM_DEFINE(DT_DRV_INST(inst), _name)
/**
* @brief Bosch M_CAN specific static initializer for a minimum nominal @p can_timing struct
*/
#define CAN_MCAN_TIMING_MIN_INITIALIZER \
{ \
.sjw = 1, \
.prop_seg = 0, \
.phase_seg1 = 2, \
.phase_seg2 = 2, \
.prescaler = 1 \
}
/**
* @brief Bosch M_CAN specific static initializer for a maximum nominal @p can_timing struct
*/
#define CAN_MCAN_TIMING_MAX_INITIALIZER \
{ \
.sjw = 128, \
.prop_seg = 0, \
.phase_seg1 = 256, \
.phase_seg2 = 128, \
.prescaler = 512 \
}
/**
* @brief Bosch M_CAN specific static initializer for a minimum data phase @p can_timing struct
*/
#define CAN_MCAN_TIMING_DATA_MIN_INITIALIZER \
{ \
.sjw = 1, \
.prop_seg = 0, \
.phase_seg1 = 1, \
.phase_seg2 = 1, \
.prescaler = 1 \
}
/**
* @brief Bosch M_CAN specific static initializer for a maximum data phase @p can_timing struct
*/
#define CAN_MCAN_TIMING_DATA_MAX_INITIALIZER \
{ \
.sjw = 16, \
.prop_seg = 0, \
.phase_seg1 = 32, \
.phase_seg2 = 16, \
.prescaler = 32 \
}
/**
* @brief Equivalent to CAN_MCAN_DT_BUILD_ASSERT_MRAM_CFG(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @see CAN_MCAN_DT_BUILD_ASSERT_MRAM_CFG()
*/
#define CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(inst) \
CAN_MCAN_DT_BUILD_ASSERT_MRAM_CFG(DT_DRV_INST(inst))
/**
* @brief Bosch M_CAN Rx Buffer and FIFO Element header
*
* See Bosch M_CAN Users Manual section 2.4.2 for details.
*/
struct can_mcan_rx_fifo_hdr {
union {
struct {
uint32_t ext_id: 29;
uint32_t rtr: 1;
uint32_t xtd: 1;
uint32_t esi: 1;
};
struct {
uint32_t pad1: 18;
uint32_t std_id: 11;
uint32_t pad2: 3;
};
};
uint32_t rxts: 16;
uint32_t dlc: 4;
uint32_t brs: 1;
uint32_t fdf: 1;
uint32_t res: 2;
uint32_t fidx: 7;
uint32_t anmf: 1;
} __packed __aligned(4);
/**
* @brief Bosch M_CAN Rx Buffer and FIFO Element
*
* See Bosch M_CAN Users Manual section 2.4.2 for details.
*/
struct can_mcan_rx_fifo {
struct can_mcan_rx_fifo_hdr hdr;
union {
uint8_t data[64];
uint32_t data_32[16];
};
} __packed __aligned(4);
/**
* @brief Bosch M_CAN Tx Buffer Element header
*
* See Bosch M_CAN Users Manual section 2.4.3 for details.
*/
struct can_mcan_tx_buffer_hdr {
union {
struct {
uint32_t ext_id: 29;
uint32_t rtr: 1;
uint32_t xtd: 1;
uint32_t esi: 1;
};
struct {
uint32_t pad1: 18;
uint32_t std_id: 11;
uint32_t pad2: 3;
};
};
uint16_t res1;
uint8_t dlc: 4;
uint8_t brs: 1;
uint8_t fdf: 1;
uint8_t tsce: 1;
uint8_t efc: 1;
uint8_t mm;
} __packed __aligned(4);
/**
* @brief Bosch M_CAN Tx Buffer Element
*
* See Bosch M_CAN Users Manual section 2.4.3 for details.
*/
struct can_mcan_tx_buffer {
struct can_mcan_tx_buffer_hdr hdr;
union {
uint8_t data[64];
uint32_t data_32[16];
};
} __packed __aligned(4);
/**
* @brief Bosch M_CAN Tx Event FIFO Element
*
* See Bosch M_CAN Users Manual section 2.4.4 for details.
*/
struct can_mcan_tx_event_fifo {
union {
struct {
uint32_t ext_id: 29;
uint32_t rtr: 1;
uint32_t xtd: 1;
uint32_t esi: 1;
};
struct {
uint32_t pad1: 18;
uint32_t std_id: 11;
uint32_t pad2: 3;
};
};
uint16_t txts;
uint8_t dlc: 4;
uint8_t brs: 1;
uint8_t fdf: 1;
uint8_t et: 2;
uint8_t mm;
} __packed __aligned(4);
/* Bosch M_CAN Standard/Extended Filter Element Configuration (SFEC/EFEC) */
#define CAN_MCAN_XFEC_DISABLE 0x0
#define CAN_MCAN_XFEC_FIFO0 0x1
#define CAN_MCAN_XFEC_FIFO1 0x2
#define CAN_MCAN_XFEC_REJECT 0x3
#define CAN_MCAN_XFEC_PRIO 0x4
#define CAN_MCAN_XFEC_PRIO_FIFO0 0x5
#define CAN_MCAN_XFEC_PRIO_FIFO1 0x7
/* Bosch M_CAN Standard Filter Type (SFT) */
#define CAN_MCAN_SFT_RANGE 0x0
#define CAN_MCAN_SFT_DUAL 0x1
#define CAN_MCAN_SFT_CLASSIC 0x2
#define CAN_MCAN_SFT_DISABLED 0x3
/**
* @brief Bosch M_CAN Standard Message ID Filter Element
*
* See Bosch M_CAN Users Manual section 2.4.5 for details.
*/
struct can_mcan_std_filter {
uint32_t sfid2: 11;
uint32_t res: 5;
uint32_t sfid1: 11;
uint32_t sfec: 3;
uint32_t sft: 2;
} __packed __aligned(4);
/* Bosch M_CAN Extended Filter Type (EFT) */
#define CAN_MCAN_EFT_RANGE_XIDAM 0x0
#define CAN_MCAN_EFT_DUAL 0x1
#define CAN_MCAN_EFT_CLASSIC 0x2
#define CAN_MCAN_EFT_RANGE 0x3
/**
* @brief Bosch M_CAN Extended Message ID Filter Element
*
* See Bosch M_CAN Users Manual section 2.4.6 for details.
*/
struct can_mcan_ext_filter {
uint32_t efid1: 29;
uint32_t efec: 3;
uint32_t efid2: 29;
uint32_t esync: 1;
uint32_t eft: 2;
} __packed __aligned(4);
/**
* @brief Bosch M_CAN driver internal data structure.
*/
struct can_mcan_data {
struct can_driver_data common;
struct k_mutex lock;
struct k_sem tx_sem;
struct k_mutex tx_mtx;
void *custom;
} __aligned(4);
/**
* @brief Bosch M_CAN driver front-end callback for reading a register value
*
* @param dev Pointer to the device structure for the driver instance.
* @param reg Register offset
* @param[out] val Register value
*
* @retval 0 If successful.
* @retval -ENOTSUP Register not supported.
* @retval -EIO General input/output error.
*/
typedef int (*can_mcan_read_reg_t)(const struct device *dev, uint16_t reg, uint32_t *val);
/**
* @brief Bosch M_CAN driver front-end callback for writing a register value
*
* @param dev Pointer to the device structure for the driver instance.
* @param reg Register offset
* @param val Register value
*
* @retval 0 If successful.
* @retval -ENOTSUP Register not supported.
* @retval -EIO General input/output error.
*/
typedef int (*can_mcan_write_reg_t)(const struct device *dev, uint16_t reg, uint32_t val);
/**
* @brief Bosch M_CAN driver front-end callback for reading from Message RAM
*
* @param dev Pointer to the device structure for the driver instance.
* @param offset Offset from the start of the Message RAM for the given Bosch M_CAN instance. The
* offset must be 32-bit aligned.
* @param[out] dst Destination for the data read. The destination address must be 32-bit aligned.
* @param len Number of bytes to read. Must be a multiple of 4.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
typedef int (*can_mcan_read_mram_t)(const struct device *dev, uint16_t offset, void *dst,
size_t len);
/**
* @brief Bosch M_CAN driver front-end callback for writing to Message RAM
*
* @param dev Pointer to the device structure for the driver instance.
* @param offset Offset from the start of the Message RAM for the given Bosch M_CAN instance. The
* offset must be 32-bit aligned.
* @param src Source for the data to be written. The source address must be 32-bit aligned.
* @param len Number of bytes to write. Must be a multiple of 4.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
typedef int (*can_mcan_write_mram_t)(const struct device *dev, uint16_t offset, const void *src,
size_t len);
/**
* @brief Bosch M_CAN driver front-end callback for clearing Message RAM
*
* Clear Message RAM by writing 0 to all words.
*
* @param dev Pointer to the device structure for the driver instance.
* @param offset Offset from the start of the Message RAM for the given Bosch M_CAN instance. The
* offset must be 32-bit aligned.
* @param len Number of bytes to clear. Must be a multiple of 4.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
typedef int (*can_mcan_clear_mram_t)(const struct device *dev, uint16_t offset, size_t len);
/**
* @brief Bosch M_CAN driver front-end operations.
*/
struct can_mcan_ops {
can_mcan_read_reg_t read_reg;
can_mcan_write_reg_t write_reg;
can_mcan_read_mram_t read_mram;
can_mcan_write_mram_t write_mram;
can_mcan_clear_mram_t clear_mram;
};
/**
* @brief Bosch M_CAN driver internal Tx callback structure.
*/
struct can_mcan_tx_callback {
can_tx_callback_t function;
void *user_data;
};
/**
* @brief Bosch M_CAN driver internal Rx callback structure.
*/
struct can_mcan_rx_callback {
can_rx_callback_t function;
void *user_data;
};
/**
* @brief Bosch M_CAN driver internal Tx + Rx callbacks structure.
*/
struct can_mcan_callbacks {
struct can_mcan_tx_callback *tx;
struct can_mcan_rx_callback *std;
struct can_mcan_rx_callback *ext;
uint8_t num_tx;
uint8_t num_std;
uint8_t num_ext;
};
/**
* @brief Define Bosch M_CAN TX and RX callbacks
*
* This macro allows a Bosch M_CAN driver frontend using a fixed Message RAM configuration to limit
* the required software resources (e.g. limit the number of the standard (11-bit) or extended
* (29-bit) filters in use).
*
* Frontend drivers supporting dynamic Message RAM configuration should use @ref
* CAN_MCAN_DT_CALLBACKS_DEFINE() or @ref CAN_MCAN_DT_INST_CALLBACKS_DEFINE() instead.
*
* @param _name callbacks variable name
* @param _tx Number of Tx callbacks
* @param _std Number of standard (11-bit) filter callbacks
* @param _ext Number of extended (29-bit) filter callbacks
* @see CAN_MCAN_DT_CALLBACKS_DEFINE()
*/
#define CAN_MCAN_CALLBACKS_DEFINE(_name, _tx, _std, _ext) \
static struct can_mcan_tx_callback _name##_tx_cbs[_tx]; \
static struct can_mcan_rx_callback _name##_std_cbs[_std]; \
static struct can_mcan_rx_callback _name##_ext_cbs[_ext]; \
static const struct can_mcan_callbacks _name = { \
.tx = _name##_tx_cbs, \
.std = _name##_std_cbs, \
.ext = _name##_ext_cbs, \
.num_tx = _tx, \
.num_std = _std, \
.num_ext = _ext, \
}
/**
* @brief Define Bosch M_CAN TX and RX callbacks
* @param node_id node identifier
* @param _name callbacks variable name
* @see CAN_MCAN_CALLBACKS_DEFINE()
*/
#define CAN_MCAN_DT_CALLBACKS_DEFINE(node_id, _name) \
CAN_MCAN_CALLBACKS_DEFINE(_name, CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(node_id), \
CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(node_id), \
CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(node_id))
/**
* @brief Equivalent to CAN_MCAN_DT_CALLBACKS_DEFINE(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @param _name callbacks variable name
* @see CAN_MCAN_DT_CALLBACKS_DEFINE()
*/
#define CAN_MCAN_DT_INST_CALLBACKS_DEFINE(inst, _name) \
CAN_MCAN_DT_CALLBACKS_DEFINE(DT_DRV_INST(inst), _name)
/**
* @brief Bosch M_CAN driver internal configuration structure.
*/
struct can_mcan_config {
const struct can_driver_config common;
const struct can_mcan_ops *ops;
const struct can_mcan_callbacks *callbacks;
uint16_t mram_elements[CAN_MCAN_MRAM_CFG_NUM_CELLS];
uint16_t mram_offsets[CAN_MCAN_MRAM_CFG_NUM_CELLS];
size_t mram_size;
const void *custom;
};
/**
* @brief Get an array containing the number of elements in Bosch M_CAN Message RAM
*
* The order of the array entries is given by the @ref CAN_MCAN_MRAM_CFG definitions.
*
* @param node_id node identifier
* @return array of number of elements
*/
#define CAN_MCAN_DT_MRAM_ELEMENTS_GET(node_id) \
{ \
0, /* offset cell */ \
CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(node_id), \
CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(node_id), \
CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(node_id), \
CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(node_id), \
CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(node_id), \
CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(node_id), \
CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(node_id) \
}
/**
* @brief Get an array containing the base offsets for element in Bosch M_CAN Message RAM
*
* The order of the array entries is given by the @ref CAN_MCAN_MRAM_CFG definitions.
*
* @param node_id node identifier
* @return array of base offsets for elements
*/
#define CAN_MCAN_DT_MRAM_OFFSETS_GET(node_id) \
{ \
0, /* offset cell */ \
CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET(node_id), \
CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET(node_id), \
CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET(node_id), \
CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET(node_id), \
CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET(node_id), \
CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET(node_id), \
CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET(node_id) \
}
/**
* @brief Static initializer for @p can_mcan_config struct
*
* @param node_id Devicetree node identifier
* @param _custom Pointer to custom driver frontend configuration structure
* @param _ops Pointer to front-end @a can_mcan_ops
* @param _cbs Pointer to front-end @a can_mcan_callbacks
*/
#ifdef CONFIG_CAN_FD_MODE
#define CAN_MCAN_DT_CONFIG_GET(node_id, _custom, _ops, _cbs) \
{ \
.common = CAN_DT_DRIVER_CONFIG_GET(node_id, 0, 8000000), \
.ops = _ops, \
.callbacks = _cbs, \
.mram_elements = CAN_MCAN_DT_MRAM_ELEMENTS_GET(node_id), \
.mram_offsets = CAN_MCAN_DT_MRAM_OFFSETS_GET(node_id), \
.mram_size = CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(node_id), \
.custom = _custom, \
}
#else /* CONFIG_CAN_FD_MODE */
#define CAN_MCAN_DT_CONFIG_GET(node_id, _custom, _ops, _cbs) \
{ \
.common = CAN_DT_DRIVER_CONFIG_GET(node_id, 0, 1000000), \
.ops = _ops, \
.callbacks = _cbs, \
.mram_elements = CAN_MCAN_DT_MRAM_ELEMENTS_GET(node_id), \
.mram_offsets = CAN_MCAN_DT_MRAM_OFFSETS_GET(node_id), \
.mram_size = CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(node_id), \
.custom = _custom, \
}
#endif /* !CONFIG_CAN_FD_MODE */
/**
* @brief Static initializer for @p can_mcan_config struct from DT_DRV_COMPAT instance
*
* @param inst DT_DRV_COMPAT instance number
* @param _custom Pointer to custom driver frontend configuration structure
* @param _ops Pointer to front-end @a can_mcan_ops
* @param _cbs Pointer to front-end @a can_mcan_callbacks
* @see CAN_MCAN_DT_CONFIG_GET()
*/
#define CAN_MCAN_DT_CONFIG_INST_GET(inst, _custom, _ops, _cbs) \
CAN_MCAN_DT_CONFIG_GET(DT_DRV_INST(inst), _custom, _ops, _cbs)
/**
* @brief Initializer for a @a can_mcan_data struct
* @param _custom Pointer to custom driver frontend data structure
*/
#define CAN_MCAN_DATA_INITIALIZER(_custom) \
{ \
.custom = _custom, \
}
/**
* @brief Bosch M_CAN driver front-end callback helper for reading a memory mapped register
*
* @param base Register base address
* @param reg Register offset
* @param[out] val Register value
*
* @retval 0 Memory mapped register read always succeeds.
*/
static inline int can_mcan_sys_read_reg(mm_reg_t base, uint16_t reg, uint32_t *val)
{
*val = sys_read32(base + reg);
return 0;
}
/**
* @brief Bosch M_CAN driver front-end callback helper for writing a memory mapped register
*
* @param base Register base address
* @param reg Register offset
* @param val Register value
*
* @retval 0 Memory mapped register write always succeeds.
*/
static inline int can_mcan_sys_write_reg(mm_reg_t base, uint16_t reg, uint32_t val)
{
sys_write32(val, base + reg);
return 0;
}
/**
* @brief Bosch M_CAN driver front-end callback helper for reading from memory mapped Message RAM
*
* @param base Base address of the Message RAM for the given Bosch M_CAN instance. The base address
* must be 32-bit aligned.
* @param offset Offset from the start of the Message RAM for the given Bosch M_CAN instance. The
* offset must be 32-bit aligned.
* @param[out] dst Destination for the data read. The destination address must be 32-bit aligned.
* @param len Number of bytes to read. Must be a multiple of 4.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
static inline int can_mcan_sys_read_mram(mem_addr_t base, uint16_t offset, void *dst, size_t len)
{
volatile uint32_t *src32 = (volatile uint32_t *)(base + offset);
uint32_t *dst32 = (uint32_t *)dst;
size_t len32 = len / sizeof(uint32_t);
__ASSERT(base % 4U == 0U, "base must be a multiple of 4");
__ASSERT(offset % 4U == 0U, "offset must be a multiple of 4");
__ASSERT(POINTER_TO_UINT(dst) % 4U == 0U, "dst must be 32-bit aligned");
__ASSERT(len % 4U == 0U, "len must be a multiple of 4");
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
int err;
err = sys_cache_data_invd_range((void *)(base + offset), len);
if (err != 0) {
return err;
}
#endif /* !defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE) */
while (len32-- > 0) {
*dst32++ = *src32++;
}
return 0;
}
/**
* @brief Bosch M_CAN driver front-end callback helper for writing to memory mapped Message RAM
*
* @param base Base address of the Message RAM for the given Bosch M_CAN instance. The base address
* must be 32-bit aligned.
* @param offset Offset from the start of the Message RAM for the given Bosch M_CAN instance. The
* offset must be 32-bit aligned.
* @param src Source for the data to be written. The source address must be 32-bit aligned.
* @param len Number of bytes to write. Must be a multiple of 4.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
static inline int can_mcan_sys_write_mram(mem_addr_t base, uint16_t offset, const void *src,
size_t len)
{
volatile uint32_t *dst32 = (volatile uint32_t *)(base + offset);
const uint32_t *src32 = (const uint32_t *)src;
size_t len32 = len / sizeof(uint32_t);
__ASSERT(base % 4U == 0U, "base must be a multiple of 4");
__ASSERT(offset % 4U == 0U, "offset must be a multiple of 4");
__ASSERT(POINTER_TO_UINT(src) % 4U == 0U, "src must be 32-bit aligned");
__ASSERT(len % 4U == 0U, "len must be a multiple of 4");
while (len32-- > 0) {
*dst32++ = *src32++;
}
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
return sys_cache_data_flush_range((void *)(base + offset), len);
#else /* defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE) */
return 0;
#endif /* !defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE) */
}
/**
* @brief Bosch M_CAN driver front-end callback helper for clearing memory mapped Message RAM
*
* Clear Message RAM by writing 0 to all words.
*
* @param base Base address of the Message RAM for the given Bosch M_CAN instance. The base address
* must be 32-bit aligned.
* @param offset Offset from the start of the Message RAM for the given Bosch M_CAN instance. The
* offset must be 32-bit aligned.
* @param len Number of bytes to clear. Must be a multiple of 4.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
static inline int can_mcan_sys_clear_mram(mem_addr_t base, uint16_t offset, size_t len)
{
volatile uint32_t *dst32 = (volatile uint32_t *)(base + offset);
size_t len32 = len / sizeof(uint32_t);
__ASSERT(base % 4U == 0U, "base must be a multiple of 4");
__ASSERT(offset % 4U == 0U, "offset must be a multiple of 4");
__ASSERT(len % 4U == 0U, "len must be a multiple of 4");
while (len32-- > 0) {
*dst32++ = 0U;
}
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
return sys_cache_data_flush_range((void *)(base + offset), len);
#else /* defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE) */
return 0;
#endif /* !defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE) */
}
/**
* @brief Read a Bosch M_CAN register
*
* @param dev Pointer to the device structure for the driver instance.
* @param reg Register offset
* @param[out] val Register value
*
* @retval 0 If successful.
* @retval -ENOTSUP Register not supported.
* @retval -EIO General input/output error.
*/
int can_mcan_read_reg(const struct device *dev, uint16_t reg, uint32_t *val);
/**
* @brief Write a Bosch M_CAN register
*
* @param dev Pointer to the device structure for the driver instance.
* @param reg Register offset
* @param val Register value
*
* @retval 0 If successful.
* @retval -ENOTSUP Register not supported.
* @retval -EIO General input/output error.
*/
int can_mcan_write_reg(const struct device *dev, uint16_t reg, uint32_t val);
/**
* @brief Read from Bosch M_CAN Message RAM
*
* @param dev Pointer to the device structure for the driver instance.
* @param offset Offset from the start of the Message RAM for the given Bosch M_CAN instance. The
* offset must be 32-bit aligned.
* @param[out] dst Destination for the data read.
* @param len Number of bytes to read. Must be a multiple of 4.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
static inline int can_mcan_read_mram(const struct device *dev, uint16_t offset, void *dst,
size_t len)
{
const struct can_mcan_config *config = dev->config;
return config->ops->read_mram(dev, offset, dst, len);
}
/**
* @brief Write to Bosch M_CAN Message RAM
*
* @param dev Pointer to the device structure for the driver instance.
* @param offset Offset from the start of the Message RAM for the given Bosch M_CAN instance. The
* offset must be 32-bit aligned.
* @param src Source for the data to be written
* @param len Number of bytes to write. Must be a multiple of 4.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
static inline int can_mcan_write_mram(const struct device *dev, uint16_t offset, const void *src,
size_t len)
{
const struct can_mcan_config *config = dev->config;
return config->ops->write_mram(dev, offset, src, len);
}
/**
* @brief Clear Bosch M_CAN Message RAM
*
* Clear Message RAM by writing 0 to all words.
*
* @param dev Pointer to the device structure for the driver instance.
* @param offset Offset from the start of the Message RAM for the given Bosch M_CAN instance. The
* offset must be 32-bit aligned.
* @param len Number of bytes to clear. Must be a multiple of 4.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
static inline int can_mcan_clear_mram(const struct device *dev, uint16_t offset, size_t len)
{
const struct can_mcan_config *config = dev->config;
return config->ops->clear_mram(dev, offset, len);
}
/**
* @brief Configure Bosch M_MCAN Message RAM start addresses.
*
* Bosch M_CAN driver front-end callback helper function for configuring the start addresses of the
* Bosch M_CAN Rx FIFO0 (RXFOC), Rx FIFO1 (RXF1C), Rx Buffer (RXBCC), Tx Buffer (TXBC), and Tx Event
* FIFO (TXEFC) in Message RAM.
*
* The start addresses (containing bits 15:2 since Bosch M_CAN message RAM is accessed as 32 bit
* words) are calculated relative to the provided Message RAM Base Address (mrba).
*
* Some Bosch M_CAN implementations use a fixed Message RAM configuration, other use a fixed memory
* area and relative addressing, others again have custom registers for configuring the Message
* RAM. It is the responsibility of the front-end driver to call this function during driver
* initialization as needed.
*
* @param dev Pointer to the device structure for the driver instance.
* @param mrba Message RAM Base Address.
* @param mram Message RAM Address.
*
* @retval 0 If successful.
* @retval -EIO General input/output error.
*/
int can_mcan_configure_mram(const struct device *dev, uintptr_t mrba, uintptr_t mram);
/**
* @brief Bosch M_CAN driver initialization callback.
*
* @param dev Pointer to the device structure for the driver instance.
*/
int can_mcan_init(const struct device *dev);
/**
* @brief Bosch M_CAN driver m_can_int0 IRQ handler.
*
* @param dev Pointer to the device structure for the driver instance.
*/
void can_mcan_line_0_isr(const struct device *dev);
/**
* @brief Bosch M_CAN driver m_can_int1 IRQ handler.
*
* @param dev Pointer to the device structure for the driver instance.
*/
void can_mcan_line_1_isr(const struct device *dev);
/**
* @brief Enable Bosch M_CAN configuration change.
*
* @param dev Pointer to the device structure for the driver instance.
*/
void can_mcan_enable_configuration_change(const struct device *dev);
/**
* @brief Bosch M_CAN driver callback API upon getting CAN controller capabilities
* See @a can_get_capabilities() for argument description
*/
int can_mcan_get_capabilities(const struct device *dev, can_mode_t *cap);
/**
* @brief Bosch M_CAN driver callback API upon starting CAN controller
* See @a can_start() for argument description
*/
int can_mcan_start(const struct device *dev);
/**
* @brief Bosch M_CAN driver callback API upon stopping CAN controller
* See @a can_stop() for argument description
*/
int can_mcan_stop(const struct device *dev);
/**
* @brief Bosch M_CAN driver callback API upon setting CAN controller mode
* See @a can_set_mode() for argument description
*/
int can_mcan_set_mode(const struct device *dev, can_mode_t mode);
/**
* @brief Bosch M_CAN driver callback API upon setting CAN bus timing
* See @a can_set_timing() for argument description
*/
int can_mcan_set_timing(const struct device *dev, const struct can_timing *timing);
/**
* @brief Bosch M_CAN driver callback API upon setting CAN bus data phase timing
* See @a can_set_timing_data() for argument description
*/
int can_mcan_set_timing_data(const struct device *dev, const struct can_timing *timing_data);
#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
/**
* @brief Bosch M_CAN driver callback API upon recovering the CAN bus
* See @a can_recover() for argument description
*/
int can_mcan_recover(const struct device *dev, k_timeout_t timeout);
#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
int can_mcan_send(const struct device *dev, const struct can_frame *frame, k_timeout_t timeout,
can_tx_callback_t callback, void *user_data);
int can_mcan_get_max_filters(const struct device *dev, bool ide);
/**
* @brief Bosch M_CAN driver callback API upon adding an RX filter
* See @a can_add_rx_callback() for argument description
*/
int can_mcan_add_rx_filter(const struct device *dev, can_rx_callback_t callback, void *user_data,
const struct can_filter *filter);
/**
* @brief Bosch M_CAN driver callback API upon removing an RX filter
* See @a can_remove_rx_filter() for argument description
*/
void can_mcan_remove_rx_filter(const struct device *dev, int filter_id);
/**
* @brief Bosch M_CAN driver callback API upon getting the CAN controller state
* See @a can_get_state() for argument description
*/
int can_mcan_get_state(const struct device *dev, enum can_state *state,
struct can_bus_err_cnt *err_cnt);
/**
* @brief Bosch M_CAN driver callback API upon setting a state change callback
* See @a can_set_state_change_callback() for argument description
*/
void can_mcan_set_state_change_callback(const struct device *dev,
can_state_change_callback_t callback, void *user_data);
#endif /* ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_MCAN_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/can/can_mcan.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16,017 |
```objective-c
/*
*/
/**
* @file
* @brief USB-C VBUS device APIs
*
* This file contains the USB-C VBUS device APIs.
* All USB-C VBUS measurement and control device drivers should
* implement the APIs described in this file.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_USBC_VBUS_H_
#define ZEPHYR_INCLUDE_DRIVERS_USBC_VBUS_H_
/**
* @brief USB-C VBUS API
* @defgroup usbc_vbus_api USB-C VBUS API
* @since 3.3
* @version 0.1.0
* @ingroup io_interfaces
* @{
*/
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <zephyr/drivers/usb_c/usbc_tc.h>
#ifdef __cplusplus
extern "C" {
#endif
__subsystem struct usbc_vbus_driver_api {
bool (*check_level)(const struct device *dev, enum tc_vbus_level level);
int (*measure)(const struct device *dev, int *vbus_meas);
int (*discharge)(const struct device *dev, bool enable);
int (*enable)(const struct device *dev, bool enable);
};
/**
* @brief Checks if VBUS is at a particular level
*
* @param dev Runtime device structure
* @param level The level voltage to check against
*
* @retval true if VBUS is at the level voltage
* @retval false if VBUS is not at that level voltage
*/
static inline bool usbc_vbus_check_level(const struct device *dev, enum tc_vbus_level level)
{
const struct usbc_vbus_driver_api *api = (const struct usbc_vbus_driver_api *)dev->api;
return api->check_level(dev, level);
}
/**
* @brief Reads and returns VBUS measured in mV
*
* @param dev Runtime device structure
* @param meas pointer where the measured VBUS voltage is stored
*
* @retval 0 on success
* @retval -EIO on failure
*/
static inline int usbc_vbus_measure(const struct device *dev, int *meas)
{
const struct usbc_vbus_driver_api *api = (const struct usbc_vbus_driver_api *)dev->api;
return api->measure(dev, meas);
}
/**
* @brief Controls a pin that discharges VBUS
*
* @param dev Runtime device structure
* @param enable Discharge VBUS when true
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOENT if discharge pin isn't defined
*/
static inline int usbc_vbus_discharge(const struct device *dev, bool enable)
{
const struct usbc_vbus_driver_api *api = (const struct usbc_vbus_driver_api *)dev->api;
return api->discharge(dev, enable);
}
/**
* @brief Controls a pin that enables VBUS measurements
*
* @param dev Runtime device structure
* @param enable enable VBUS measurements when true
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOENT if enable pin isn't defined
*/
static inline int usbc_vbus_enable(const struct device *dev, bool enable)
{
const struct usbc_vbus_driver_api *api = (const struct usbc_vbus_driver_api *)dev->api;
return api->enable(dev, enable);
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_USBC_VBUS_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/usb_c/usbc_vbus.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 750 |
```objective-c
/*
*/
/**
* @file
* @brief USB-C Power Delivery API used for USB-C drivers
*
* The information in this file was taken from the USB PD
* Specification Revision 3.0, Version 2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_PD_H_
#define ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_PD_H_
/**
* @brief USB Power Delivery
* @defgroup usb_power_delivery USB Power Delivery
* @ingroup io_interfaces
* @{
*/
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Maximum length of a non-Extended Message in bytes.
* See Table 6-75 Value Parameters
* Parameter Name: MaxExtendedMsgLegacyLen
*/
#define PD_MAX_EXTENDED_MSG_LEGACY_LEN 26
/**
* @brief Maximum length of an Extended Message in bytes.
* See Table 6-75 Value Parameters
* Parameter Name: MaxExtendedMsgLen
*/
#define PD_MAX_EXTENDED_MSG_LEN 260
/**
* @brief Maximum length of a Chunked Message in bytes.
* When one of both Port Partners do not support Extended
* Messages of Data Size greater than PD_MAX_EXTENDED_MSG_LEGACY_LEN
* then the Protocol Layer supports a Chunking mechanism to
* break larger Messages into smaller Chunks of size
* PD_MAX_EXTENDED_MSG_CHUNK_LEN.
* See Table 6-75 Value Parameters
* Parameter Name: MaxExtendedMsgChunkLen
*/
#define PD_MAX_EXTENDED_MSG_CHUNK_LEN 26
/**
* @name USB PD 3.1 Rev 1.6, Table 6-70 Counter Parameters
* @{
*/
/**
* @brief The CapsCounter is used to count the number of Source_Capabilities
* Messages which have been sent by a Source at power up or after a
* Hard Reset.
* Parameter Name: nCapsCounter
*/
#define PD_N_CAPS_COUNT 50
/**
* @brief The HardResetCounter is used to retry the Hard Reset whenever there
* is no response from the remote device (see Section 6.6.6)
* Parameter Name: nHardResetCounter
*/
#define PD_N_HARD_RESET_COUNT 2
/** @} */
/**
* @name USB PD 3.1 Rev 1.6, Table 6-68 Time Values
* @{
*/
/**
* @brief The NoResponseTimer is used by the Policy Engine in a Source to
* determine that its Port Partner is not responding after a Hard Reset.
* Parameter Name: tNoResponseTimer
*/
#define PD_T_NO_RESPONSE_MIN_MS 4500
/**
* @brief The NoResponseTimer is used by the Policy Engine in a Source to
* determine that its Port Partner is not responding after a Hard Reset.
* Parameter Name: tNoResponseTimer
*/
#define PD_T_NO_RESPONSE_MAX_MS 5500
/**
* @brief Min time the Source waits to ensure that the Sink has had
* sufficient time to process Hard Reset Signaling before
* turning off its power supply to VBUS
* Parameter Name: tPSHardReset
*/
#define PD_T_PS_HARD_RESET_MIN_MS 25
/**
* @brief Max time the Source waits to ensure that the Sink has had
* sufficient time to process Hard Reset Signaling before
* turning off its power supply to VBUS
* Parameter Name: tPSHardReset
*/
#define PD_T_PS_HARD_RESET_MAX_MS 35
/**
* @brief Minimum time a Source waits after changing Rp from SinkTxOk to SinkTxNG
* before initiating an AMS by sending a Message.
* Parameter Name: tSinkTx
*/
#define PD_T_SINK_TX_MIN_MS 16
/**
* @brief Maximum time a Source waits after changing Rp from SinkTxOk to SinkTxNG
* before initiating an AMS by sending a Message.
* Parameter Name: tSinkTx
*/
#define PD_T_SINK_TX_MAX_MS 20
/**
* @brief Minimum time a source shall wait before sending a
* Source_Capabilities message while the following is true:
* 1) The Port is Attached.
* 2) The Source is not in an active connection with a PD Sink Port.
* Parameter Name: tTypeCSendSourceCap
*/
#define PD_T_TYPEC_SEND_SOURCE_CAP_MIN_MS 100
/**
* @brief Maximum time a source shall wait before sending a
* Source_Capabilities message while the following is true:
* 1) The Port is Attached.
* 2) The Source is not in an active connection with a PD Sink Port.
* Parameter Name: tTypeCSendSourceCap
*/
#define PD_T_TYPEC_SEND_SOURCE_CAP_MAX_MS 200
/** @} */
/**
* @brief Minimum time a sink shall wait for a Source_Capabilities message
* before sending a Hard Reset
* See Table 6-61 Time Values
* Parameter Name: tTypeCSinkWaitCap
*/
#define PD_T_TYPEC_SINK_WAIT_CAP_MIN_MS 310
/**
* @brief Minimum time a sink shall wait for a Source_Capabilities message
* before sending a Hard Reset
* See Table 6-61 Time Values
* Parameter Name: tTypeCSinkWaitCap
*/
#define PD_T_TYPEC_SINK_WAIT_CAP_MAX_MS 620
/**
* @brief VBUS maximum safe operating voltage at "zero volts".
* See Table 7-24 Common Source/Sink Electrical Parameters
* Parameter Name: vSafe0V
*/
#define PD_V_SAFE_0V_MAX_MV 800
/**
* @brief VBUS minimum safe operating voltage at 5V.
* See Table 7-24 Common Source/Sink Electrical Parameters
* Parameter Name: vSafe5V
*/
#define PD_V_SAFE_5V_MIN_MV 4750
/**
* @brief Time to reach PD_V_SAFE_0V_MV max in milliseconds.
* See Table 7-24 Common Source/Sink Electrical Parameters
* Parameter Name: tSafe0V
*/
#define PD_T_SAFE_0V_MAX_MS 650
/**
* @brief Time to reach PD_V_SAFE_5V_MV max in milliseconds.
* See Table 7-24 Common Source/Sink Electrical Parameters
* Parameter Name: tSafe5V
*/
#define PD_T_SAFE_5V_MAX_MS 275
/**
* @brief Time to wait for TCPC to complete transmit
*/
#define PD_T_TX_TIMEOUT_MS 100
/**
* @brief Minimum time a Hard Reset must complete.
* See Table 6-68 Time Values
*/
#define PD_T_HARD_RESET_COMPLETE_MIN_MS 4
/**
* @brief Maximum time a Hard Reset must complete.
* See Table 6-68 Time Values
*/
#define PD_T_HARD_RESET_COMPLETE_MAX_MS 5
/**
* @brief Minimum time a response must be sent from a Port Partner
* See Table 6-68 Time Values
*/
#define PD_T_SENDER_RESPONSE_MIN_MS 24
/**
* @brief Nomiminal time a response must be sent from a Port Partner
* See Table 6-68 Time Values
*/
#define PD_T_SENDER_RESPONSE_NOM_MS 27
/**
* @brief Maximum time a response must be sent from a Port Partner
* See Table 6-68 Time Values
*/
#define PD_T_SENDER_RESPONSE_MAX_MS 30
/**
* @brief Minimum SPR Mode time for a power supply to transition to a new level
* See Table 6-68 Time Values
*/
#define PD_T_SPR_PS_TRANSITION_MIN_MS 450
/**
* @brief Nominal SPR Mode time for a power supply to transition to a new level
* See Table 6-68 Time Values
*/
#define PD_T_SPR_PS_TRANSITION_NOM_MS 500
/**
* @brief Maximum SPR Mode time for a power supply to transition to a new level
* See Table 6-68 Time Values
*/
#define PD_T_SPR_PS_TRANSITION_MAX_MS 550
/**
* @brief Minimum EPR Mode time for a power supply to transition to a new level
* See Table 6-68 Time Values
*/
#define PD_T_EPR_PS_TRANSITION_MIN_MS 830
/**
* @brief Nominal EPR Mode time for a power supply to transition to a new level
* See Table 6-68 Time Values
*/
#define PD_T_EPR_PS_TRANSITION_NOM_MS 925
/**
* @brief Maximum EPR Mode time for a power supply to transition to a new level
* See Table 6-68 Time Values
*/
#define PD_T_EPR_PS_TRANSITION_MAX_MS 1020
/**
* @brief Minimum time to wait before sending another request after receiving a Wait message
* See Table 6-68 Time Values
*/
#define PD_T_SINK_REQUEST_MIN_MS 100
/**
* @brief Minimum time to wait before sending a Not_Supported message after receiving a
* Chunked message
* See Table 6-68 Time Values
*/
#define PD_T_CHUNKING_NOT_SUPPORTED_MIN_MS 40
/**
* @brief Nominal time to wait before sending a Not_Supported message after receiving a
* Chunked message
* See Table 6-68 Time Values
*/
#define PD_T_CHUNKING_NOT_SUPPORTED_NOM_MS 45
/**
* @brief Maximum time to wait before sending a Not_Supported message after receiving a
* Chunked message
* See Table 6-68 Time Values
*/
#define PD_T_CHUNKING_NOT_SUPPORTED_MAX_MS 50
/**
* @brief Convert bytes to PD Header data object count, where a
* data object is 4-bytes.
*
* @param c number of bytes to convert
*/
#define PD_CONVERT_BYTES_TO_PD_HEADER_COUNT(c) ((c) >> 2)
/**
* @brief Convert PD Header data object count to bytes
*
* @param c number of PD Header data objects
*/
#define PD_CONVERT_PD_HEADER_COUNT_TO_BYTES(c) ((c) << 2)
/**
* @brief Collision avoidance Rp values in REV 3.0
* Sink Transmit "OK"
*/
#define SINK_TX_OK TC_RP_3A0
/**
* @brief Collision avoidance Rp values in REV 3.0
* Sink Transmit "NO GO"
*/
#define SINK_TX_NG TC_RP_1A5
/**
* @brief Build a PD message header
* See Table 6-1 Message Header
*/
union pd_header {
struct {
/** Type of message */
uint16_t message_type : 5;
/** Port Data role */
uint16_t port_data_role : 1;
/** Specification Revision */
uint16_t specification_revision : 2;
/** Port Power Role */
uint16_t port_power_role : 1;
/** Message ID */
uint16_t message_id : 3;
/** Number of Data Objects */
uint16_t number_of_data_objects : 3;
/** Extended Message */
uint16_t extended : 1;
};
uint16_t raw_value;
};
/**
* @brief Used to get extended header from the first 32-bit word of the message
*
* @param c first 32-bit word of the message
*/
#define PD_GET_EXT_HEADER(c) ((c) & 0xffff)
/**
* @brief Build an extended message header
* See Table 6-3 Extended Message Header
*/
union pd_ext_header {
struct {
/** Number of total bytes in data block */
uint16_t data_size : 9;
/** Reserved */
uint16_t reserved0 : 1;
/** 1 for a chunked message, else 0 */
uint16_t request_chunk : 1;
/** Chunk number when chkd = 1, else 0 */
uint16_t chunk_number : 4;
/** 1 for chunked messages */
uint16_t chunked : 1;
};
/** Raw PD Ext Header value */
uint16_t raw_value;
};
/**
* PDO - Power Data Object
* RDO - Request Data Object
*/
/**
* @brief Maximum number of 32-bit data objects sent in a single request
*/
#define PDO_MAX_DATA_OBJECTS 7
/**
* @brief Power Data Object Type
* Table 6-7 Power Data Object
*/
enum pdo_type {
/** Fixed supply (Vmin = Vmax) */
PDO_FIXED = 0,
/** Battery */
PDO_BATTERY = 1,
/** Variable Supply (non-Battery) */
PDO_VARIABLE = 2,
/** Augmented Power Data Object (APDO) */
PDO_AUGMENTED = 3
};
/**
* @brief Convert milliamps to Fixed PDO Current in 10mA units.
*
* @param c Current in milliamps
*/
#define PD_CONVERT_MA_TO_FIXED_PDO_CURRENT(c) ((c) / 10)
/**
* @brief Convert millivolts to Fixed PDO Voltage in 50mV units
*
* @param v Voltage in millivolts
*/
#define PD_CONVERT_MV_TO_FIXED_PDO_VOLTAGE(v) ((v) / 50)
/**
* @brief Convert a Fixed PDO Current from 10mA units to milliamps.
*
* @param c Fixed PDO current in 10mA units.
*/
#define PD_CONVERT_FIXED_PDO_CURRENT_TO_MA(c) ((c) * 10)
/**
* @brief Convert a Fixed PDO Voltage from 50mV units to millivolts.
* Used for converting pd_fixed_supply_pdo_source.voltage and
* pd_fixed_supply_pdo_sink.voltage
*
* @param v Fixed PDO voltage in 50mV units.
*/
#define PD_CONVERT_FIXED_PDO_VOLTAGE_TO_MV(v) ((v) * 50)
/**
* @brief Create a Fixed Supply PDO Source value
* See Table 6-9 Fixed Supply PDO - Source
*/
union pd_fixed_supply_pdo_source {
struct {
/** Maximum Current in 10mA units */
uint32_t max_current : 10;
/** Voltage in 50mV units */
uint32_t voltage : 10;
/** Peak Current */
uint32_t peak_current : 2;
/** Reserved Shall be set to zero. */
uint32_t reserved0 : 2;
/** Unchunked Extended Messages Supported */
uint32_t unchunked_ext_msg_supported : 1;
/** Dual-Role Data */
uint32_t dual_role_data : 1;
/** USB Communications Capable */
uint32_t usb_comms_capable : 1;
/** Unconstrained Power */
uint32_t unconstrained_power : 1;
/** USB Suspend Supported */
uint32_t usb_suspend_supported : 1;
/** Dual-Role Power */
uint32_t dual_role_power : 1;
/** Fixed supply. SET TO PDO_FIXED */
enum pdo_type type : 2;
};
/** Raw PDO value */
uint32_t raw_value;
};
/**
* @brief Fast Role Swap Required for USB Type-C current
*/
enum pd_frs_type {
/** Fast Swap not supported */
FRS_NOT_SUPPORTED,
/** Default USB Power */
FRS_DEFAULT_USB_POWER,
/** 1.5A @ 5V */
FRS_1P5A_5V,
/** 3.0A @ 5V */
FRS_3P0A_5V
};
/**
* @brief Create a Fixed Supply PDO Sink value
* See Table 6-14 Fixed Supply PDO - Sink
*/
union pd_fixed_supply_pdo_sink {
struct {
/** Operational Current in 10mA units */
uint32_t operational_current : 10;
/** Voltage in 50mV units */
uint32_t voltage : 10;
/** Reserved Shall be set to zero. */
uint32_t reserved0 : 3;
/** Fast Role Swap required USB Type-C Current */
enum pd_frs_type frs_required : 2;
/** Dual-Role Data */
uint32_t dual_role_data : 1;
/** USB Communications Capable */
uint32_t usb_comms_capable : 1;
/** Unconstrained Power */
uint32_t unconstrained_power : 1;
/** Higher Capability */
uint32_t higher_capability : 1;
/** Dual-Role Power */
uint32_t dual_role_power : 1;
/** Fixed supply. SET TO PDO_FIXED */
enum pdo_type type : 2;
};
/** Raw PDO value */
uint32_t raw_value;
};
/**
* @brief Convert milliamps to Variable PDO Current in 10ma units.
*
* @param c Current in milliamps
*/
#define PD_CONVERT_MA_TO_VARIABLE_PDO_CURRENT(c) ((c) / 10)
/**
* @brief Convert millivolts to Variable PDO Voltage in 50mV units
*
* @param v Voltage in millivolts
*/
#define PD_CONVERT_MV_TO_VARIABLE_PDO_VOLTAGE(v) ((v) / 50)
/**
* @brief Convert a Variable PDO Current from 10mA units to milliamps.
*
* @param c Variable PDO current in 10mA units.
*/
#define PD_CONVERT_VARIABLE_PDO_CURRENT_TO_MA(c) ((c) * 10)
/**
* @brief Convert a Variable PDO Voltage from 50mV units to millivolts.
*
* @param v Variable PDO voltage in 50mV units.
*/
#define PD_CONVERT_VARIABLE_PDO_VOLTAGE_TO_MV(v) ((v) * 50)
/**
* @brief Create a Variable Supply PDO Source value
* See Table 6-11 Variable Supply (non-Battery) PDO - Source
*/
union pd_variable_supply_pdo_source {
struct {
/** Maximum Current in 10mA units */
uint32_t max_current : 10;
/** Minimum Voltage in 50mV units */
uint32_t min_voltage : 10;
/** Maximum Voltage in 50mV units */
uint32_t max_voltage : 10;
/** Variable supply. SET TO PDO_VARIABLE */
enum pdo_type type : 2;
};
/** Raw PDO value */
uint32_t raw_value;
};
/**
* @brief Create a Variable Supply PDO Sink value
* See Table 6-15 Variable Supply (non-Battery) PDO - Sink
*/
union pd_variable_supply_pdo_sink {
struct {
/** operational Current in 10mA units */
uint32_t operational_current : 10;
/** Minimum Voltage in 50mV units */
uint32_t min_voltage : 10;
/** Maximum Voltage in 50mV units */
uint32_t max_voltage : 10;
/** Variable supply. SET TO PDO_VARIABLE */
enum pdo_type type : 2;
};
/** Raw PDO value */
uint32_t raw_value;
};
/**
* @brief Convert milliwatts to Battery PDO Power in 250mW units
*
* @param c Power in milliwatts
*/
#define PD_CONVERT_MW_TO_BATTERY_PDO_POWER(c) ((c) / 250)
/**
* @brief Convert milliwatts to Battery PDO Voltage in 50mV units
*
* @param v Voltage in millivolts
*/
#define PD_CONVERT_MV_TO_BATTERY_PDO_VOLTAGE(v) ((v) / 50)
/**
* @brief Convert a Battery PDO Power from 250mW units to milliwatts
*
* @param c Power in 250mW units.
*/
#define PD_CONVERT_BATTERY_PDO_POWER_TO_MW(c) ((c) * 250)
/**
* @brief Convert a Battery PDO Voltage from 50mV units to millivolts
*
* @param v Voltage in 50mV units.
*/
#define PD_CONVERT_BATTERY_PDO_VOLTAGE_TO_MV(v) ((v) * 50)
/**
* @brief Create a Battery Supply PDO Source value
* See Table 6-12 Battery Supply PDO - Source
*/
union pd_battery_supply_pdo_source {
struct {
/** Maximum Allowable Power in 250mW units */
uint32_t max_power : 10;
/** Minimum Voltage in 50mV units */
uint32_t min_voltage : 10;
/** Maximum Voltage in 50mV units */
uint32_t max_voltage : 10;
/** Battery supply. SET TO PDO_BATTERY */
enum pdo_type type : 2;
};
/** Raw PDO value */
uint32_t raw_value;
};
/**
* @brief Create a Battery Supply PDO Sink value
* See Table 6-16 Battery Supply PDO - Sink
*/
union pd_battery_supply_pdo_sink {
struct {
/** Operational Power in 250mW units */
uint32_t operational_power : 10;
/** Minimum Voltage in 50mV units */
uint32_t min_voltage : 10;
/** Maximum Voltage in 50mV units */
uint32_t max_voltage : 10;
/** Battery supply. SET TO PDO_BATTERY */
enum pdo_type type : 2;
};
/** Raw PDO value */
uint32_t raw_value;
};
/**
* @brief Convert milliamps to Augmented PDO Current in 50mA units
*
* @param c Current in milliamps
*/
#define PD_CONVERT_MA_TO_AUGMENTED_PDO_CURRENT(c) ((c) / 50)
/**
* @brief Convert millivolts to Augmented PDO Voltage in 100mV units
*
* @param v Voltage in millivolts
*/
#define PD_CONVERT_MV_TO_AUGMENTED_PDO_VOLTAGE(v) ((v) / 100)
/**
* @brief Convert an Augmented PDO Current from 50mA units to milliamps
*
* @param c Augmented PDO current in 50mA units.
*/
#define PD_CONVERT_AUGMENTED_PDO_CURRENT_TO_MA(c) ((c) * 50)
/**
* @brief Convert an Augmented PDO Voltage from 100mV units to millivolts
*
* @param v Augmented PDO voltage in 100mV units.
*/
#define PD_CONVERT_AUGMENTED_PDO_VOLTAGE_TO_MV(v) ((v) * 100)
/**
* @brief Create Augmented Supply PDO Source value
* See Table 6-13 Programmable Power Supply APDO - Source
*/
union pd_augmented_supply_pdo_source {
struct {
/** Maximum Current in 50mA increments */
uint32_t max_current : 7;
/** Reserved Shall be set to zero */
uint32_t reserved0 : 1;
/** Minimum Voltage in 100mV increments */
uint32_t min_voltage : 8;
/** Reserved Shall be set to zero */
uint32_t reserved1 : 1;
/** Maximum Voltage in 100mV increments */
uint32_t max_voltage : 8;
/** Reserved Shall be set to zero */
uint32_t reserved2 : 2;
/** PPS Power Limited */
uint32_t pps_power_limited : 1;
/**
* 00b Programmable Power Supply
* 01b11b - Reserved, Shall Not be used
* Setting as reserved because it defaults to 0 when not set.
*/
uint32_t reserved3 : 2;
/** Augmented Power Data Object (APDO). SET TO PDO_AUGMENTED */
enum pdo_type type : 2;
};
/** Raw PDO value */
uint32_t raw_value;
};
/**
* @brief Create Augmented Supply PDO Sink value
* See Table 6-17 Programmable Power Supply APDO - Sink
*/
union pd_augmented_supply_pdo_sink {
struct {
/** Maximum Current in 50mA increments */
uint32_t max_current : 7;
/** Reserved Shall be set to zero */
uint32_t reserved0 : 1;
/** Minimum Voltage in 100mV increments */
uint32_t min_voltage : 8;
/** Reserved Shall be set to zero */
uint32_t reserved1 : 1;
/** Maximum Voltage in 100mV increments */
uint32_t max_voltage : 8;
/** Reserved Shall be set to zero */
uint32_t reserved2 : 3;
/**
* 00b Programmable Power Supply
* 01b11b - Reserved, Shall Not be used
* Setting as reserved because it defaults to 0 when not set.
*/
uint32_t reserved3 : 2;
/** Augmented Power Data Object (APDO). SET TO PDO_AUGMENTED */
enum pdo_type type : 2;
};
/** Raw PDO value */
uint32_t raw_value;
};
/**
* @brief The Request Data Object (RDO) Shall be returned by the Sink making
* a request for power.
* See Section 6.4.2 Request Message
*/
union pd_rdo {
/**
* @brief Create a Fixed RDO value
* See Table 6-19 Fixed and Variable Request Data Object
*/
struct {
/**
* Operating Current 10mA units
* NOTE: If Give Back Flag is zero, this field is
* the Maximum Operating Current.
* If Give Back Flag is one, this field is
* the Minimum Operating Current.
*/
uint32_t min_or_max_operating_current : 10;
/** Operating current in 10mA units */
uint32_t operating_current : 10;
/** Reserved - Shall be set to zero. */
uint32_t reserved0 : 3;
/** Unchunked Extended Messages Supported */
uint32_t unchunked_ext_msg_supported : 1;
/** No USB Suspend */
uint32_t no_usb_suspend : 1;
/** USB Communications Capable */
uint32_t usb_comm_capable : 1;
/** Capability Mismatch */
uint32_t cap_mismatch : 1;
/** Give Back Flag */
uint32_t giveback : 1;
/** Object Position (000b is Reserved and Shall Not be used) */
uint32_t object_pos : 3;
/** Reserved - Shall be set to zero. */
uint32_t reserved1 : 1;
} fixed;
/**
* @brief Create a Variable RDO value
* See Table 6-19 Fixed and Variable Request Data Object
*/
struct {
/**
* Operating Current 10mA units
* NOTE: If Give Back Flag is zero, this field is
* the Maximum Operating Current.
* If Give Back Flag is one, this field is
* the Minimum Operating Current.
*/
uint32_t min_or_max_operating_current : 10;
/** Operating current in 10mA units */
uint32_t operating_current : 10;
/** Reserved - Shall be set to zero. */
uint32_t reserved0 : 3;
/** Unchunked Extended Messages Supported */
uint32_t unchunked_ext_msg_supported : 1;
/** No USB Suspend */
uint32_t no_usb_suspend : 1;
/** USB Communications Capable */
uint32_t usb_comm_capable : 1;
/** Capability Mismatch */
uint32_t cap_mismatch : 1;
/** Give Back Flag */
uint32_t giveback : 1;
/** Object Position (000b is Reserved and Shall Not be used) */
uint32_t object_pos : 3;
/** Reserved - Shall be set to zero. */
uint32_t reserved1 : 1;
} variable;
/**
* @brief Create a Battery RDO value
* See Table 6-20 Battery Request Data Object
*/
struct {
/** Minimum Operating Power in 250mW units */
uint32_t min_operating_power : 10;
/** Operating power in 250mW units */
uint32_t operating_power : 10;
/** Reserved - Shall be set to zero. */
uint32_t reserved0 : 3;
/** Unchunked Extended Messages Supported */
uint32_t unchunked_ext_msg_supported : 1;
/** No USB Suspend */
uint32_t no_usb_suspend : 1;
/** USB Communications Capable */
uint32_t usb_comm_capable : 1;
/** Capability Mismatch */
uint32_t cap_mismatch : 1;
/** Give Back Flag */
uint32_t giveback : 1;
/** Object Position (000b is Reserved and Shall Not be used) */
uint32_t object_pos : 3;
/** Reserved - Shall be set to zero. */
uint32_t reserved1 : 1;
} battery;
/**
* @brief Create an Augmented RDO value
* See Table 6-22 Programmable Request Data Object
*/
struct {
/** Operating Current 50mA units */
uint32_t operating_current : 7;
/** Reserved - Shall be set to zero. */
uint32_t reserved0 : 2;
/** Output Voltage in 20mV units */
uint32_t output_voltage : 11;
/** Reserved - Shall be set to zero. */
uint32_t reserved1 : 3;
/** Unchunked Extended Messages Supported */
uint32_t unchunked_ext_msg_supported : 1;
/** No USB Suspend */
uint32_t no_usb_suspend : 1;
/** USB Communications Capable */
uint32_t usb_comm_capable : 1;
/** Capability Mismatch */
uint32_t cap_mismatch : 1;
/** Reserved - Shall be set to zero */
uint32_t reserved2 : 1;
/** Object Position (000b is Reserved and Shall Not be used) */
uint32_t object_pos : 3;
/** Reserved - Shall be set to zero. */
uint32_t reserved3 : 1;
} augmented;
/** Raw RDO value */
uint32_t raw_value;
};
/**
* @brief Protocol revision
*/
enum pd_rev_type {
/** PD revision 1.0 */
PD_REV10 = 0,
/** PD revision 2.0 */
PD_REV20 = 1,
/** PD revision 3.0 */
PD_REV30 = 2,
};
/**
* @brief Power Delivery packet type
* See USB Type-C Port Controller Interface Specification,
* Revision 2.0, Version 1.2, Table 4-38 TRANSMIT Register Definition
*/
enum pd_packet_type {
/** Port Partner message */
PD_PACKET_SOP = 0,
/** Cable Plug message */
PD_PACKET_SOP_PRIME = 1,
/** Cable Plug message far end*/
PD_PACKET_PRIME_PRIME = 2,
/** Currently undefined in the PD specification */
PD_PACKET_DEBUG_PRIME = 3,
/** Currently undefined in the PD specification */
PD_PACKET_DEBUG_PRIME_PRIME = 4,
/** Hard Reset message to the Port Partner */
PD_PACKET_TX_HARD_RESET = 5,
/** Cable Reset message to the Cable */
PD_PACKET_CABLE_RESET = 6,
/** BIST_MODE_2 message to the Port Partner */
PD_PACKET_TX_BIST_MODE_2 = 7,
/** USED ONLY FOR RECEPTION OF UNKNOWN MSG TYPES */
PD_PACKET_MSG_INVALID = 0xf
};
/**
* @brief Number of valid Transmit Types
*/
#define NUM_SOP_STAR_TYPES (PD_PACKET_DEBUG_PRIME_PRIME + 1)
/**
* @brief Control Message type
* See Table 6-5 Control Message Types
*/
enum pd_ctrl_msg_type {
/** 0 Reserved */
/** GoodCRC Message */
PD_CTRL_GOOD_CRC = 1,
/** GotoMin Message */
PD_CTRL_GOTO_MIN = 2,
/** Accept Message */
PD_CTRL_ACCEPT = 3,
/** Reject Message */
PD_CTRL_REJECT = 4,
/** Ping Message */
PD_CTRL_PING = 5,
/** PS_RDY Message */
PD_CTRL_PS_RDY = 6,
/** Get_Source_Cap Message */
PD_CTRL_GET_SOURCE_CAP = 7,
/** Get_Sink_Cap Message */
PD_CTRL_GET_SINK_CAP = 8,
/** DR_Swap Message */
PD_CTRL_DR_SWAP = 9,
/** PR_Swap Message */
PD_CTRL_PR_SWAP = 10,
/** VCONN_Swap Message */
PD_CTRL_VCONN_SWAP = 11,
/** Wait Message */
PD_CTRL_WAIT = 12,
/** Soft Reset Message */
PD_CTRL_SOFT_RESET = 13,
/** Used for REV 3.0 */
/** Data_Reset Message */
PD_CTRL_DATA_RESET = 14,
/** Data_Reset_Complete Message */
PD_CTRL_DATA_RESET_COMPLETE = 15,
/** Not_Supported Message */
PD_CTRL_NOT_SUPPORTED = 16,
/** Get_Source_Cap_Extended Message */
PD_CTRL_GET_SOURCE_CAP_EXT = 17,
/** Get_Status Message */
PD_CTRL_GET_STATUS = 18,
/** FR_Swap Message */
PD_CTRL_FR_SWAP = 19,
/** Get_PPS_Status Message */
PD_CTRL_GET_PPS_STATUS = 20,
/** Get_Country_Codes Message */
PD_CTRL_GET_COUNTRY_CODES = 21,
/** Get_Sink_Cap_Extended Message */
PD_CTRL_GET_SINK_CAP_EXT = 22
/** 23-31 Reserved */
};
/**
* @brief Data message type
* See Table 6-6 Data Message Types
*/
enum pd_data_msg_type {
/** 0 Reserved */
/** Source_Capabilities Message */
PD_DATA_SOURCE_CAP = 1,
/** Request Message */
PD_DATA_REQUEST = 2,
/** BIST Message */
PD_DATA_BIST = 3,
/** Sink Capabilities Message */
PD_DATA_SINK_CAP = 4,
/** 5-14 Reserved for REV 2.0 */
PD_DATA_BATTERY_STATUS = 5,
/** Alert Message */
PD_DATA_ALERT = 6,
/** Get Country Info Message */
PD_DATA_GET_COUNTRY_INFO = 7,
/** 8-14 Reserved for REV 3.0 */
/** Enter USB message */
PD_DATA_ENTER_USB = 8,
/** Vendor Defined Message */
PD_DATA_VENDOR_DEF = 15,
};
/**
* @brief Extended message type for REV 3.0
* See Table 6-48 Extended Message Types
*/
enum pd_ext_msg_type {
/** 0 Reserved */
/** Source_Capabilities_Extended Message */
PD_EXT_SOURCE_CAP = 1,
/** Status Message */
PD_EXT_STATUS = 2,
/** Get_Battery_Cap Message */
PD_EXT_GET_BATTERY_CAP = 3,
/** Get_Battery_Status Message */
PD_EXT_GET_BATTERY_STATUS = 4,
/** Battery_Capabilities Message */
PD_EXT_BATTERY_CAP = 5,
/** Get_Manufacturer_Info Message */
PD_EXT_GET_MANUFACTURER_INFO = 6,
/** Manufacturer_Info Message */
PD_EXT_MANUFACTURER_INFO = 7,
/** Security_Request Message */
PD_EXT_SECURITY_REQUEST = 8,
/** Security_Response Message */
PD_EXT_SECURITY_RESPONSE = 9,
/** Firmware_Update_Request Message */
PD_EXT_FIRMWARE_UPDATE_REQUEST = 10,
/** Firmware_Update_Response Message */
PD_EXT_FIRMWARE_UPDATE_RESPONSE = 11,
/** PPS_Status Message */
PD_EXT_PPS_STATUS = 12,
/** Country_Codes Message */
PD_EXT_COUNTRY_INFO = 13,
/** Country_Info Message */
PD_EXT_COUNTRY_CODES = 14,
/*8 15-31 Reserved */
};
/**
* @brief Active PD CC pin
*/
enum usbpd_cc_pin {
/** PD is active on CC1 */
USBPD_CC_PIN_1 = 0,
/** PD is active on CC2 */
USBPD_CC_PIN_2 = 1,
};
/**
* @brief Power Delivery message
*/
struct pd_msg {
/** Type of this packet */
enum pd_packet_type type;
/** Header of this message */
union pd_header header;
/** Length of bytes in data */
uint32_t len;
/** Message data */
uint8_t data[PD_MAX_EXTENDED_MSG_LEN];
};
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_PD_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/usb_c/usbc_pd.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,962 |
```objective-c
/*
*/
/**
* @file
* @brief USBC Type-C Port Controller device APIs
*
* This file contains the USB Type-C Port Controller device APIs.
* All Type-C Port Controller device drivers should implement the
* APIs described in this file.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_TCPC_H_
#define ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_TCPC_H_
/**
* @brief USB Type-C Port Controller API
* @defgroup usb_type_c_port_controller_api USB Type-C Port Controller API
* @since 3.1
* @version 0.1.0
* @ingroup io_interfaces
* @{
*/
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <errno.h>
#include "usbc_tc.h"
#include "usbc_pd.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief TCPC Alert bits
*/
enum tcpc_alert {
/** CC status changed */
TCPC_ALERT_CC_STATUS,
/** Power status changed */
TCPC_ALERT_POWER_STATUS,
/** Receive Buffer register changed */
TCPC_ALERT_MSG_STATUS,
/** Received Hard Reset message */
TCPC_ALERT_HARD_RESET_RECEIVED,
/** SOP* message transmission not successful */
TCPC_ALERT_TRANSMIT_MSG_FAILED,
/**
* Reset or SOP* message transmission not sent
* due to an incoming receive message
*/
TCPC_ALERT_TRANSMIT_MSG_DISCARDED,
/** Reset or SOP* message transmission successful */
TCPC_ALERT_TRANSMIT_MSG_SUCCESS,
/** A high-voltage alarm has occurred */
TCPC_ALERT_VBUS_ALARM_HI,
/** A low-voltage alarm has occurred */
TCPC_ALERT_VBUS_ALARM_LO,
/** A fault has occurred. Read the FAULT_STATUS register */
TCPC_ALERT_FAULT_STATUS,
/** TCPC RX buffer has overflowed */
TCPC_ALERT_RX_BUFFER_OVERFLOW,
/** The TCPC in Attached.SNK state has detected a sink disconnect */
TCPC_ALERT_VBUS_SNK_DISCONNECT,
/** Receive buffer register changed */
TCPC_ALERT_BEGINNING_MSG_STATUS,
/** Extended status changed */
TCPC_ALERT_EXTENDED_STATUS,
/**
* An extended interrupt event has occurred. Read the alert_extended
* register
*/
TCPC_ALERT_EXTENDED,
/** A vendor defined alert has been detected */
TCPC_ALERT_VENDOR_DEFINED
};
/**
* @brief TCPC Status register
*/
enum tcpc_status_reg {
/** The CC Status register */
TCPC_CC_STATUS,
/** The Power Status register */
TCPC_POWER_STATUS,
/** The Fault Status register */
TCPC_FAULT_STATUS,
/** The Extended Status register */
TCPC_EXTENDED_STATUS,
/** The Extended Alert Status register */
TCPC_EXTENDED_ALERT_STATUS,
/** The Vendor Defined Status register */
TCPC_VENDOR_DEFINED_STATUS
};
/**
* @brief TCPC Chip Information
*/
struct tcpc_chip_info {
/** Vendor Id */
uint16_t vendor_id;
/** Product Id */
uint16_t product_id;
/** Device Id */
uint16_t device_id;
/** Firmware version number */
uint64_t fw_version_number;
union {
/** Minimum Required firmware version string */
uint8_t min_req_fw_version_string[8];
/** Minimum Required firmware version number */
uint64_t min_req_fw_version_number;
};
};
typedef int (*tcpc_vconn_control_cb_t)(const struct device *dev,
enum tc_cc_polarity pol, bool enable);
typedef int (*tcpc_vconn_discharge_cb_t)(const struct device *dev,
enum tc_cc_polarity pol, bool enable);
typedef void (*tcpc_alert_handler_cb_t)(const struct device *dev, void *data,
enum tcpc_alert alert);
__subsystem struct tcpc_driver_api {
int (*init)(const struct device *dev);
int (*get_cc)(const struct device *dev, enum tc_cc_voltage_state *cc1,
enum tc_cc_voltage_state *cc2);
int (*select_rp_value)(const struct device *dev, enum tc_rp_value rp);
int (*get_rp_value)(const struct device *dev, enum tc_rp_value *rp);
int (*set_cc)(const struct device *dev, enum tc_cc_pull pull);
void (*set_vconn_discharge_cb)(const struct device *dev, tcpc_vconn_discharge_cb_t cb);
void (*set_vconn_cb)(const struct device *dev, tcpc_vconn_control_cb_t vconn_cb);
int (*vconn_discharge)(const struct device *dev, bool enable);
int (*set_vconn)(const struct device *dev, bool enable);
int (*set_roles)(const struct device *dev, enum tc_power_role power_role,
enum tc_data_role data_role);
int (*get_rx_pending_msg)(const struct device *dev, struct pd_msg *msg);
int (*set_rx_enable)(const struct device *dev, bool enable);
int (*set_cc_polarity)(const struct device *dev, enum tc_cc_polarity polarity);
int (*transmit_data)(const struct device *dev, struct pd_msg *msg);
int (*dump_std_reg)(const struct device *dev);
void (*alert_handler_cb)(const struct device *dev, void *data, enum tcpc_alert alert);
int (*get_status_register)(const struct device *dev, enum tcpc_status_reg reg,
int32_t *status);
int (*clear_status_register)(const struct device *dev, enum tcpc_status_reg reg,
uint32_t mask);
int (*mask_status_register)(const struct device *dev, enum tcpc_status_reg reg,
uint32_t mask);
int (*set_debug_accessory)(const struct device *dev, bool enable);
int (*set_debug_detach)(const struct device *dev);
int (*set_drp_toggle)(const struct device *dev, bool enable);
int (*get_snk_ctrl)(const struct device *dev);
int (*set_snk_ctrl)(const struct device *dev, bool enable);
int (*get_src_ctrl)(const struct device *dev);
int (*set_src_ctrl)(const struct device *dev, bool enable);
int (*get_chip_info)(const struct device *dev, struct tcpc_chip_info *chip_info);
int (*set_low_power_mode)(const struct device *dev, bool enable);
int (*sop_prime_enable)(const struct device *dev, bool enable);
int (*set_bist_test_mode)(const struct device *dev, bool enable);
int (*set_alert_handler_cb)(const struct device *dev, tcpc_alert_handler_cb_t handler,
void *data);
};
/**
* @brief Returns whether the sink has detected a Rp resistor on the other side
*/
static inline int tcpc_is_cc_rp(enum tc_cc_voltage_state cc)
{
return (cc == TC_CC_VOLT_RP_DEF) || (cc == TC_CC_VOLT_RP_1A5) ||
(cc == TC_CC_VOLT_RP_3A0);
}
/**
* @brief Returns true if both CC lines are completely open
*/
static inline int tcpc_is_cc_open(enum tc_cc_voltage_state cc1,
enum tc_cc_voltage_state cc2)
{
return (cc1 < TC_CC_VOLT_RD) && (cc2 < TC_CC_VOLT_RD);
}
/**
* @brief Returns true if we detect the port partner is a snk debug accessory
*/
static inline int tcpc_is_cc_snk_dbg_acc(enum tc_cc_voltage_state cc1,
enum tc_cc_voltage_state cc2)
{
return cc1 == TC_CC_VOLT_RD && cc2 == TC_CC_VOLT_RD;
}
/**
* @brief Returns true if we detect the port partner is a src debug accessory
*/
static inline int tcpc_is_cc_src_dbg_acc(enum tc_cc_voltage_state cc1,
enum tc_cc_voltage_state cc2)
{
return tcpc_is_cc_rp(cc1) && tcpc_is_cc_rp(cc2);
}
/**
* @brief Returns true if the port partner is an audio accessory
*/
static inline int tcpc_is_cc_audio_acc(enum tc_cc_voltage_state cc1,
enum tc_cc_voltage_state cc2)
{
return cc1 == TC_CC_VOLT_RA && cc2 == TC_CC_VOLT_RA;
}
/**
* @brief Returns true if the port partner is presenting at least one Rd
*/
static inline int tcpc_is_cc_at_least_one_rd(enum tc_cc_voltage_state cc1,
enum tc_cc_voltage_state cc2)
{
return cc1 == TC_CC_VOLT_RD || cc2 == TC_CC_VOLT_RD;
}
/**
* @brief Returns true if the port partner is presenting Rd on only one CC line
*/
static inline int tcpc_is_cc_only_one_rd(enum tc_cc_voltage_state cc1,
enum tc_cc_voltage_state cc2)
{
return tcpc_is_cc_at_least_one_rd(cc1, cc2) && cc1 != cc2;
}
/**
* @brief Initializes the TCPC
*
* @param dev Runtime device structure
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -EAGAIN if initialization should be postponed
*/
static inline int tcpc_init(const struct device *dev)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
__ASSERT(api->init != NULL,
"Callback pointer should not be NULL");
return api->init(dev);
}
/**
* @brief Reads the status of the CC lines
*
* @param dev Runtime device structure
* @param cc1 A pointer where the CC1 status is written
* @param cc2 A pointer where the CC2 status is written
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_get_cc(const struct device *dev,
enum tc_cc_voltage_state *cc1,
enum tc_cc_voltage_state *cc2)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->get_cc == NULL) {
return -ENOSYS;
}
return api->get_cc(dev, cc1, cc2);
}
/**
* @brief Sets the value of CC pull up resistor used when operating as a Source
*
* @param dev Runtime device structure
* @param rp Value of the Pull-Up Resistor.
*
* @retval 0 on success
* @retval -ENOSYS
* @retval -EIO on failure
*/
static inline int tcpc_select_rp_value(const struct device *dev, enum tc_rp_value rp)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->select_rp_value == NULL) {
return -ENOSYS;
}
return api->select_rp_value(dev, rp);
}
/**
* @brief Gets the value of the CC pull up resistor used when operating as a Source
*
* @param dev Runtime device structure
* @param rp pointer where the value of the Pull-Up Resistor is stored
*
* @retval 0 on success
* @retval -ENOSYS
* @retval -EIO on failure
*/
static inline int tcpc_get_rp_value(const struct device *dev, enum tc_rp_value *rp)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->get_rp_value == NULL) {
return -ENOSYS;
}
return api->get_rp_value(dev, rp);
}
/**
* @brief Sets the CC pull resistor and sets the role as either Source or Sink
*
* @param dev Runtime device structure
* @param pull The pull resistor to set
*
* @retval 0 on success
* @retval -EIO on failure
*/
static inline int tcpc_set_cc(const struct device *dev, enum tc_cc_pull pull)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
__ASSERT(api->set_cc != NULL,
"Callback pointer should not be NULL");
return api->set_cc(dev, pull);
}
/**
* @brief Sets a callback that can enable or disable VCONN if the TCPC is
* unable to or the system is configured in a way that does not use
* the VCONN control capabilities of the TCPC
*
* The callback is called in the tcpc_set_vconn function if vconn_cb isn't NULL
*
* @param dev Runtime device structure
* @param vconn_cb pointer to the callback function that controls vconn
*/
static inline void tcpc_set_vconn_cb(const struct device *dev,
tcpc_vconn_control_cb_t vconn_cb)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
__ASSERT(api->set_vconn_cb != NULL,
"Callback pointer should not be NULL");
return api->set_vconn_cb(dev, vconn_cb);
}
/**
* @brief Sets a callback that can enable or discharge VCONN if the TCPC is
* unable to or the system is configured in a way that does not use
* the VCONN control capabilities of the TCPC
*
* The callback is called in the tcpc_vconn_discharge function if cb isn't NULL
*
* @param dev Runtime device structure
* @param cb pointer to the callback function that discharges vconn
*/
static inline void tcpc_set_vconn_discharge_cb(const struct device *dev,
tcpc_vconn_discharge_cb_t cb)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
__ASSERT(api->set_vconn_discharge_cb != NULL,
"Callback pointer should not be NULL");
return api->set_vconn_discharge_cb(dev, cb);
}
/**
* @brief Discharges VCONN
*
* This function uses the TCPC to discharge VCONN if possible or calls the
* callback function set by tcpc_set_vconn_cb
*
* @param dev Runtime device structure
* @param enable VCONN discharge is enabled when true, it's disabled
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_vconn_discharge(const struct device *dev, bool enable)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->vconn_discharge == NULL) {
return -ENOSYS;
}
return api->vconn_discharge(dev, enable);
}
/**
* @brief Enables or disables VCONN
*
* This function uses the TCPC to measure VCONN if possible or calls the
* callback function set by tcpc_set_vconn_cb
*
* @param dev Runtime device structure
* @param enable VCONN is enabled when true, it's disabled
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_vconn(const struct device *dev, bool enable)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->set_vconn == NULL) {
return -ENOSYS;
}
return api->set_vconn(dev, enable);
}
/**
* @brief Sets the Power and Data Role of the PD message header
*
* This function only needs to be called once per data / power role change
*
* @param dev Runtime device structure
* @param power_role current power role
* @param data_role current data role
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_roles(const struct device *dev,
enum tc_power_role power_role,
enum tc_data_role data_role)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->set_roles == NULL) {
return -ENOSYS;
}
return api->set_roles(dev, power_role, data_role);
}
/**
* @brief Retrieves the Power Delivery message from the TCPC.
* If buf is NULL, then only the status is returned, where 0 means there is a message pending and
* -ENODATA means there is no pending message.
*
* @param dev Runtime device structure
* @param buf pointer where the pd_buf pointer is written, NULL if only checking the status
*
* @retval Greater or equal to 0 is the number of bytes received if buf parameter is provided
* @retval 0 if there is a message pending and buf parameter is NULL
* @retval -EIO on failure
* @retval -ENODATA if no message is pending
*/
static inline int tcpc_get_rx_pending_msg(const struct device *dev, struct pd_msg *buf)
{
const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api;
__ASSERT(api->get_rx_pending_msg != NULL, "Callback pointer should not be NULL");
return api->get_rx_pending_msg(dev, buf);
}
/**
* @brief Enables the reception of SOP* message types
*
* @param dev Runtime device structure
* @param enable Enable Power Delivery when true, else it's
* disabled
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_rx_enable(const struct device *dev, bool enable)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->set_rx_enable == NULL) {
return -ENOSYS;
}
return api->set_rx_enable(dev, enable);
}
/**
* @brief Sets the polarity of the CC lines
*
* @param dev Runtime device structure
* @param polarity Polarity of the cc line
*
* @retval 0 on success
* @retval -EIO on failure
*/
static inline int tcpc_set_cc_polarity(const struct device *dev,
enum tc_cc_polarity polarity)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
__ASSERT(api->set_cc_polarity != NULL,
"Callback pointer should not be NULL");
return api->set_cc_polarity(dev, polarity);
}
/**
* @brief Transmits a Power Delivery message
*
* @param dev Runtime device structure
* @param msg Power Delivery message to transmit
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_transmit_data(const struct device *dev,
struct pd_msg *msg)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->transmit_data == NULL) {
return -ENOSYS;
}
return api->transmit_data(dev, msg);
}
/**
* @brief Dump a set of TCPC registers
*
* @param dev Runtime device structure
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_dump_std_reg(const struct device *dev)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->dump_std_reg == NULL) {
return -ENOSYS;
}
return api->dump_std_reg(dev);
}
/**
* @brief Sets the alert function that's called when an interrupt is triggered
* due to an alert bit
*
* Calling this function enables the particular alert bit
*
* @param dev Runtime device structure
* @param handler The callback function called when the bit is set
* @param data user data passed to the callback
*
* @retval 0 on success
* @retval -EINVAL on failure
*/
static inline int tcpc_set_alert_handler_cb(const struct device *dev,
tcpc_alert_handler_cb_t handler,
void *data)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
__ASSERT(api->set_alert_handler_cb != NULL,
"Callback pointer should not be NULL");
return api->set_alert_handler_cb(dev, handler, data);
}
/**
* @brief Gets a status register
*
* @param dev Runtime device structure
* @param reg The status register to read
* @param status Pointer where the status is stored
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_get_status_register(const struct device *dev,
enum tcpc_status_reg reg,
int32_t *status)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->get_status_register == NULL) {
return -ENOSYS;
}
return api->get_status_register(dev, reg, status);
}
/**
* @brief Clears a TCPC status register
*
* @param dev Runtime device structure
* @param reg The status register to read
* @param mask A bit mask of the status register to clear.
* A status bit is cleared when it's set to 1.
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_clear_status_register(const struct device *dev,
enum tcpc_status_reg reg,
uint32_t mask)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->clear_status_register == NULL) {
return -ENOSYS;
}
return api->clear_status_register(dev, reg, mask);
}
/**
* @brief Sets the mask of a TCPC status register
*
* @param dev Runtime device structure
* @param reg The status register to read
* @param mask A bit mask of the status register to mask.
* The status bit is masked if it's 0, else it's unmasked.
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_mask_status_register(const struct device *dev,
enum tcpc_status_reg reg,
uint32_t mask)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->mask_status_register == NULL) {
return -ENOSYS;
}
return api->mask_status_register(dev, reg, mask);
}
/**
* @brief Manual control of TCPC DebugAccessory control
*
* @param dev Runtime device structure
* @param enable Enable Debug Accessory when true, else it's disabled
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_debug_accessory(const struct device *dev,
bool enable)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->set_debug_accessory == NULL) {
return -ENOSYS;
}
return api->set_debug_accessory(dev, enable);
}
/**
* @brief Detach from a debug connection
*
* @param dev Runtime device structure
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_debug_detach(const struct device *dev)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->set_debug_detach == NULL) {
return -ENOSYS;
}
return api->set_debug_detach(dev);
}
/**
* @brief Enable TCPC auto dual role toggle
*
* @param dev Runtime device structure
* @param enable Auto dual role toggle is active when true, else it's disabled
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_drp_toggle(const struct device *dev, bool enable)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->set_drp_toggle == NULL) {
return -ENOSYS;
}
return api->set_drp_toggle(dev, enable);
}
/**
* @brief Queries the current sinking state of the TCPC
*
* @param dev Runtime device structure
*
* @retval true if sinking power
* @retval false if not sinking power
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_get_snk_ctrl(const struct device *dev)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->get_snk_ctrl == NULL) {
return -ENOSYS;
}
return api->get_snk_ctrl(dev);
}
/**
* @brief Set the VBUS sinking state of the TCPC
*
* @param dev Runtime device structure
* @param enable True if sinking should be enabled, false if disabled
* @retval 0 on success
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_snk_ctrl(const struct device *dev, bool enable)
{
const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api;
if (api->set_snk_ctrl == NULL) {
return -ENOSYS;
}
return api->set_snk_ctrl(dev, enable);
}
/**
* @brief Queries the current sourcing state of the TCPC
*
* @param dev Runtime device structure
*
* @retval true if sourcing power
* @retval false if not sourcing power
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_get_src_ctrl(const struct device *dev)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->get_src_ctrl == NULL) {
return -ENOSYS;
}
return api->get_src_ctrl(dev);
}
/**
* @brief Set the VBUS sourcing state of the TCPC
*
* @param dev Runtime device structure
* @param enable True if sourcing should be enabled, false if disabled
* @retval 0 on success
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_src_ctrl(const struct device *dev, bool enable)
{
const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api;
if (api->set_src_ctrl == NULL) {
return -ENOSYS;
}
return api->set_src_ctrl(dev, enable);
}
/**
* @brief Controls the BIST Mode of the TCPC. It disables RX alerts while the
* mode is active.
*
* @param dev Runtime device structure
* @param enable The TCPC enters BIST TEST Mode when true
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_bist_test_mode(const struct device *dev,
bool enable)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->set_bist_test_mode == NULL) {
return -ENOSYS;
}
return api->set_bist_test_mode(dev, enable);
}
/**
* @brief Gets the TCPC firmware version
*
* @param dev Runtime device structure
* @param chip_info Pointer to TCPC chip info where the version is stored
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_get_chip_info(const struct device *dev,
struct tcpc_chip_info *chip_info)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->get_chip_info == NULL) {
return -ENOSYS;
}
return api->get_chip_info(dev, chip_info);
}
/**
* @brief Instructs the TCPC to enter or exit low power mode
*
* @param dev Runtime device structure
* @param enable The TCPC enters low power mode when true, else it exits it
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_set_low_power_mode(const struct device *dev,
bool enable)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->set_low_power_mode == NULL) {
return -ENOSYS;
}
return api->set_low_power_mode(dev, enable);
}
/**
* @brief Enables the reception of SOP Prime messages
*
* @param dev Runtime device structure
* @param enable Can receive SOP Prime messages when true, else it can not
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOSYS if not implemented
*/
static inline int tcpc_sop_prime_enable(const struct device *dev,
bool enable)
{
const struct tcpc_driver_api *api =
(const struct tcpc_driver_api *)dev->api;
if (api->sop_prime_enable == NULL) {
return -ENOSYS;
}
return api->sop_prime_enable(dev, enable);
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_TCPC_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/usb_c/usbc_tcpc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,424 |
```objective-c
/*
*/
/**
* @file
* @brief USB Type-C Power Path Controller device API
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_PPC_H_
#define ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_PPC_H_
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <errno.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Type of event being notified by Power Path Controller */
enum usbc_ppc_event {
/** Exit from dead-battery mode failed */
USBC_PPC_EVENT_DEAD_BATTERY_ERROR = 0,
/** Overvoltage detected while being in a source role */
USBC_PPC_EVENT_SRC_OVERVOLTAGE,
/** Reverse current detected while being in a source role */
USBC_PPC_EVENT_SRC_REVERSE_CURRENT,
/** Overcurrent detected while being in a source role */
USBC_PPC_EVENT_SRC_OVERCURRENT,
/** VBUS short detected while being in a source role */
USBC_PPC_EVENT_SRC_SHORT,
/** Chip over temperature detected */
USBC_PPC_EVENT_OVER_TEMPERATURE,
/** Sink and source paths enabled simultaneously */
USBC_PPC_EVENT_BOTH_SNKSRC_ENABLED,
/** Reverse current detected while being in a sink role */
USBC_PPC_EVENT_SNK_REVERSE_CURRENT,
/** VBUS short detected while being in a sink role */
USBC_PPC_EVENT_SNK_SHORT,
/** Overvoltage detected while being in a sink role */
USBC_PPC_EVENT_SNK_OVERVOLTAGE,
};
typedef void (*usbc_ppc_event_cb_t)(const struct device *dev, void *data, enum usbc_ppc_event ev);
/** Structure with pointers to the functions implemented by driver */
__subsystem struct usbc_ppc_driver_api {
int (*is_dead_battery_mode)(const struct device *dev);
int (*exit_dead_battery_mode)(const struct device *dev);
int (*is_vbus_source)(const struct device *dev);
int (*is_vbus_sink)(const struct device *dev);
int (*set_snk_ctrl)(const struct device *dev, bool enable);
int (*set_src_ctrl)(const struct device *dev, bool enable);
int (*set_vbus_discharge)(const struct device *dev, bool enable);
int (*is_vbus_present)(const struct device *dev);
int (*set_event_handler)(const struct device *dev, usbc_ppc_event_cb_t handler, void *data);
int (*dump_regs)(const struct device *dev);
};
/*
* API functions
*/
/**
* @brief Check if PPC is in the dead battery mode
*
* @param dev PPC device structure
* @retval 1 if PPC is in the dead battery mode
* @retval 0 if PPC is not in the dead battery mode
* @retval -EIO if I2C communication failed
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_is_dead_battery_mode(const struct device *dev)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->is_dead_battery_mode == NULL) {
return -ENOSYS;
}
return api->is_dead_battery_mode(dev);
}
/**
* @brief Request the PPC to exit from the dead battery mode
* Return from this call doesn't mean that the PPC is not in the dead battery anymore.
* In the case of error, the driver should execute the callback with
* USBC_PPC_EVENT_DEAD_BATTERY_ERROR enum. To check if the PPC disabled the dead battery mode,
* the call to ppc_is_dead_battery_mode should be done.
*
* @param dev PPC device structure
* @retval 0 if request was successfully sent
* @retval -EIO if I2C communication failed
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_exit_dead_battery_mode(const struct device *dev)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->exit_dead_battery_mode == NULL) {
return -ENOSYS;
}
return api->exit_dead_battery_mode(dev);
}
/**
* @brief Check if the PPC is sourcing the VBUS
*
* @param dev PPC device structure
* @retval 1 if the PPC is sourcing the VBUS
* @retval 0 if the PPC is not sourcing the VBUS
* @retval -EIO if I2C communication failed
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_is_vbus_source(const struct device *dev)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->is_vbus_source == NULL) {
return -ENOSYS;
}
return api->is_vbus_source(dev);
}
/**
* @brief Check if the PPC is sinking the VBUS
*
* @param dev PPC device structure
* @retval 1 if the PPC is sinking the VBUS
* @retval 0 if the PPC is not sinking the VBUS
* @retval -EIO if I2C communication failed
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_is_vbus_sink(const struct device *dev)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->is_vbus_sink == NULL) {
return -ENOSYS;
}
return api->is_vbus_sink(dev);
}
/**
* @brief Set the state of VBUS sinking
*
* @param dev PPC device structure
* @param enable True if sinking VBUS should be enabled, false if should be disabled
* @retval 0 if success
* @retval -EIO if I2C communication failed
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_set_snk_ctrl(const struct device *dev, bool enable)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->set_snk_ctrl == NULL) {
return -ENOSYS;
}
return api->set_snk_ctrl(dev, enable);
}
/**
* @brief Set the state of VBUS sourcing
*
* @param dev PPC device structure
* @param enable True if sourcing VBUS should be enabled, false if should be disabled
* @retval 0 if success
* @retval -EIO if I2C communication failed
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_set_src_ctrl(const struct device *dev, bool enable)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->set_src_ctrl == NULL) {
return -ENOSYS;
}
return api->set_src_ctrl(dev, enable);
}
/**
* @brief Set the state of VBUS discharging
*
* @param dev PPC device structure
* @param enable True if VBUS discharging should be enabled, false if should be disabled
* @retval 0 if success
* @retval -EIO if I2C communication failed
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_set_vbus_discharge(const struct device *dev, bool enable)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->set_vbus_discharge == NULL) {
return -ENOSYS;
}
return api->set_vbus_discharge(dev, enable);
}
/**
* @brief Check if VBUS is present
*
* @param dev PPC device structure
* @retval 1 if VBUS voltage is present
* @retval 0 if no VBUS voltage is detected
* @retval -EIO if I2C communication failed
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_is_vbus_present(const struct device *dev)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->is_vbus_present == NULL) {
return -ENOSYS;
}
return api->is_vbus_present(dev);
}
/**
* @brief Set the callback used to notify about PPC events
*
* @param dev PPC device structure
* @param handler Handler that will be called with events notifications
* @param data Pointer used as an argument to the callback
* @retval 0 if success
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_set_event_handler(const struct device *dev,
usbc_ppc_event_cb_t handler, void *data)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->set_event_handler == NULL) {
return -ENOSYS;
}
return api->set_event_handler(dev, handler, data);
}
/**
* @brief Print the values or PPC registers
*
* @param dev PPC device structure
* @retval 0 if success
* @retval -EIO if I2C communication failed
* @retval -ENOSYS if this function is not supported by the driver
*/
static inline int ppc_dump_regs(const struct device *dev)
{
const struct usbc_ppc_driver_api *api = (const struct usbc_ppc_driver_api *)dev->api;
if (api->dump_regs == NULL) {
return -ENOSYS;
}
return api->dump_regs(dev);
}
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_PPC_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/usb_c/usbc_ppc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,143 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_REGULATOR_PCA9420_H_
#define ZEPHYR_INCLUDE_DRIVERS_REGULATOR_PCA9420_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup regulator_parent_pca9420 PCA9420 Utilities.
* @ingroup regulator_parent_interface
* @{
*/
/** @brief DVS state 'MODE0' */
#define REGULATOR_PCA9420_DVS_MODE0 0
/** @brief DVS state 'MODE1' */
#define REGULATOR_PCA9420_DVS_MODE1 1
/** @brief DVS state 'MODE2' */
#define REGULATOR_PCA9420_DVS_MODE2 2
/** @brief DVS state 'MODE3' */
#define REGULATOR_PCA9420_DVS_MODE3 3
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_REGULATOR_PCA9420_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/regulator/pca9420.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```objective-c
/*
*/
#ifndef ZEPHYR_DRIVERS_REGULATOR_FAKE_H_
#define ZEPHYR_DRIVERS_REGULATOR_FAKE_H_
#include <zephyr/drivers/regulator.h>
#include <zephyr/fff.h>
#ifdef __cplusplus
extern "C" {
#endif
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_enable, const struct device *);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_disable, const struct device *);
DECLARE_FAKE_VALUE_FUNC(unsigned int, regulator_fake_count_voltages,
const struct device *);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_list_voltage, const struct device *,
unsigned int, int32_t *);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_set_voltage, const struct device *,
int32_t, int32_t);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_get_voltage, const struct device *,
int32_t *);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_set_current_limit,
const struct device *, int32_t, int32_t);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_get_current_limit,
const struct device *, int32_t *);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_set_mode, const struct device *,
regulator_mode_t);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_get_mode, const struct device *,
regulator_mode_t *);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_set_active_discharge, const struct device *,
bool);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_get_active_discharge, const struct device *,
bool *);
DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_get_error_flags,
const struct device *, regulator_error_flags_t *);
DECLARE_FAKE_VALUE_FUNC(int, regulator_parent_fake_dvs_state_set,
const struct device *, regulator_dvs_state_t);
DECLARE_FAKE_VALUE_FUNC(int, regulator_parent_fake_ship_mode,
const struct device *);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_TESTS_DRIVERS_CAN_SHELL_FAKE_CAN_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/regulator/fake.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 405 |
```objective-c
/*
*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_I2C_STM32_H_
#define ZEPHYR_INCLUDE_DRIVERS_I2C_STM32_H_
#include <zephyr/device.h>
enum i2c_stm32_mode {
I2CSTM32MODE_I2C,
I2CSTM32MODE_SMBUSHOST,
I2CSTM32MODE_SMBUSDEVICE,
I2CSTM32MODE_SMBUSDEVICEARP,
};
void i2c_stm32_set_smbus_mode(const struct device *dev, enum i2c_stm32_mode mode);
#ifdef CONFIG_SMBUS_STM32_SMBALERT
typedef void (*i2c_stm32_smbalert_cb_func_t)(const struct device *dev);
void i2c_stm32_smbalert_set_callback(const struct device *dev, i2c_stm32_smbalert_cb_func_t func,
const struct device *cb_dev);
void i2c_stm32_smbalert_enable(const struct device *dev);
void i2c_stm32_smbalert_disable(const struct device *dev);
#endif /* CONFIG_SMBUS_STM32_SMBALERT */
#endif /* ZEPHYR_INCLUDE_DRIVERS_I2C_STM32_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/i2c/stm32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 268 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_I2C_RTIO_H_
#define ZEPHYR_DRIVERS_I2C_RTIO_H_
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/rtio/rtio.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Driver context for implementing i2c with rtio
*/
struct i2c_rtio {
struct k_sem lock;
struct k_spinlock slock;
struct rtio *r;
struct mpsc io_q;
struct rtio_iodev iodev;
struct rtio_iodev_sqe *txn_head;
struct rtio_iodev_sqe *txn_curr;
struct i2c_dt_spec dt_spec;
};
/**
* @brief Statically define an i2c_rtio context
*
* @param _name Symbolic name of the context
* @param _sq_sz Submission queue entry pool size
* @param _cq_sz Completion queue entry pool size
*/
#define I2C_RTIO_DEFINE(_name, _sq_sz, _cq_sz) \
RTIO_DEFINE(CONCAT(_name, _r), _sq_sz, _cq_sz); \
static struct i2c_rtio _name = { \
.r = &CONCAT(_name, _r), \
};
/**
* @brief Copy an array of i2c_msgs to rtio submissions and a transaction
*
* @retval sqe Last sqe setup in the copy
* @retval NULL Not enough memory to copy the transaction
*/
struct rtio_sqe *i2c_rtio_copy(struct rtio *r, struct rtio_iodev *iodev, const struct i2c_msg *msgs,
uint8_t num_msgs);
/**
* @brief Initialize an i2c rtio context
*
* @param ctx I2C RTIO driver context
* @param dev I2C bus
*/
void i2c_rtio_init(struct i2c_rtio *ctx, const struct device *dev);
/**
* @brief Signal that the current (ctx->txn_curr) submission has been completed
*
* @param ctx I2C RTIO driver context
* @param status Completion status, negative values are errors
*
* @retval true Next submission is ready to start
* @retval false No more submissions to work on
*/
bool i2c_rtio_complete(struct i2c_rtio *ctx, int status);
/**
* @brief Submit, atomically, a submission to work on at some point
*
* @retval true Next submission is ready to start
* @retval false No new submission to start or submissions are in progress already
*/
bool i2c_rtio_submit(struct i2c_rtio *ctx, struct rtio_iodev_sqe *iodev_sqe);
/**
* @brief Configure the I2C bus controller
*
* Provides a compatible API for the existing i2c_configure API, and blocks the
* caller until the transfer completes.
*
* See i2c_configure().
*/
int i2c_rtio_configure(struct i2c_rtio *ctx, uint32_t i2c_config);
/**
* @brief Transfer i2c messages in a blocking call
*
* Provides a compatible API for the existing i2c_transfer API, and blocks the caller
* until the transfer completes.
*
* See i2c_transfer().
*/
int i2c_rtio_transfer(struct i2c_rtio *ctx, struct i2c_msg *msgs, uint8_t num_msgs, uint16_t addr);
/**
* @brief Perform an I2C bus recovery in a blocking call
*
* Provides a compatible API for the existing i2c_recover API, and blocks the caller
* until the process completes.
*
* See i2c_recover().
*/
int i2c_rtio_recover(struct i2c_rtio *ctx);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRVIERS_I2C_RTIO_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/i2c/rtio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 855 |
```objective-c
/**
* @file
*
* @brief Public APIs for the I2C EEPROM Target driver.
*/
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_I2C_TARGET_EEPROM_H_
#define ZEPHYR_INCLUDE_DRIVERS_I2C_TARGET_EEPROM_H_
/**
* @brief I2C EEPROM Target Driver API
* @defgroup i2c_eeprom_target_api I2C EEPROM Target Driver API
* @since 1.13
* @version 1.0.0
* @ingroup io_interfaces
* @{
*/
/**
* @brief Program memory of the virtual EEPROM
*
* @param dev Pointer to the device structure for the driver instance.
* @param eeprom_data Pointer of data to program into the virtual eeprom memory
* @param length Length of data to program into the virtual eeprom memory
*
* @retval 0 If successful.
* @retval -EINVAL Invalid data size
*/
int eeprom_target_program(const struct device *dev, const uint8_t *eeprom_data,
unsigned int length);
/**
* @brief Read single byte of virtual EEPROM memory
*
* @param dev Pointer to the device structure for the driver instance.
* @param eeprom_data Pointer of byte where to store the virtual eeprom memory
* @param offset Offset into EEPROM memory where to read the byte
*
* @retval 0 If successful.
* @retval -EINVAL Invalid data pointer or offset
*/
int eeprom_target_read(const struct device *dev, uint8_t *eeprom_data,
unsigned int offset);
/**
* @brief Change the address of eeprom target at runtime
*
* @param dev Pointer to the device structure for the driver instance.
* @param addr New address to assign to the eeprom target device
*
* @retval 0 Is successful
* @retval -EINVAL If parameters are invalid
* @retval -EIO General input / output error during i2c_taget_register
* @retval -ENOSYS If target mode is not implemented
*/
int eeprom_target_set_addr(const struct device *dev, uint8_t addr);
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DRIVERS_I2C_TARGET_EEPROM_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/i2c/target/eeprom.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 459 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_NCT38XX_H_
#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_NCT38XX_H_
/**
* @brief Dispatch all GPIO ports ISR in the NCT38XX device.
*
* @param dev NCT38XX device.
*/
void nct38xx_gpio_alert_handler(const struct device *dev);
#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_NCT38XX_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/gpio/gpio_nct38xx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```objective-c
/*
*/
/**
* @file
* @brief USB Type-C Cable and Connector API used for USB-C drivers
*
* The information in this file was taken from the USB Type-C
* Cable and Connector Specification Release 2.1
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_TC_H_
#define ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_TC_H_
/**
* @brief USB Type-C
* @defgroup usb_type_c USB Type-C
* @ingroup io_interfaces
* @{
*/
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief VBUS minimum for a sink disconnect detection.
* See Table 4-3 VBUS Sink Characteristics
*/
#define TC_V_SINK_DISCONNECT_MIN_MV 800
/**
* @brief VBUS maximum for a sink disconnect detection.
* See Table 4-3 VBUS Sink Characteristics
*/
#define TC_V_SINK_DISCONNECT_MAX_MV 3670
/**
* @brief From entry to Attached.SRC until VBUS reaches the minimum vSafe5V threshold as
* measured at the sources receptacle
* See Table 4-29 VBUS and VCONN Timing Parameters
*/
#define TC_T_VBUS_ON_MAX_MS 275
/**
* @brief From the time the Sink is detached until the Source removes VBUS and reaches
* vSafe0V (See USB PD).
* See Table 4-29 VBUS and VCONN Timing Parameters
*/
#define TC_T_VBUS_OFF_MAX_MS 650
/**
* @brief From the time the Source supplied VBUS in the Attached.SRC state.
* See Table 4-29 VBUS and VCONN Timing Parameters
*/
#define TC_T_VCONN_ON_MAX_MS 2
/**
* @brief From the time a Sink with accessory support enters the PoweredAccessory state
* until the Sink sources minimum VCONN voltage (see Table 4-5)
* See Table 4-29 VBUS and VCONN Timing Parameters
*/
#define TC_T_VCONN_ON_PA_MAX_MS 100
/**
* @brief From the time that a Sink is detached or as directed until the VCONN supply is
* disconnected.
* See Table 4-29 VBUS and VCONN Timing Parameters
*/
#define TC_T_VCONN_OFF_MAX_MS 35
/**
* @brief Response time for a Sink to adjust its current consumption to be in the specified
* range due to a change in USB Type-C Current advertisement
* See Table 4-29 VBUS and VCONN Timing Parameters
*/
#define TC_T_SINK_ADJ_MAX_MS 60
/**
* @brief The minimum period a DRP shall complete a Source to Sink and back advertisement
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_DRP_MIN_MS 50
/**
* @brief The maximum period a DRP shall complete a Source to Sink and back advertisement
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_DRP_MAX_MS 100
/**
* @brief The minimum time a DRP shall complete transitions between Source and Sink roles
* during role resolution
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_DRP_TRANSITION_MIN_MS 0
/**
* @brief The maximum time a DRP shall complete transitions between Source and Sink roles
* during role resolution
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_DRP_TRANSITION_MAX_MS 1
/**
* @brief Minimum wait time associated with the Try.SRC state.
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_DRP_TRY_MIN_MS 75
/**
* @brief Maximum wait time associated with the Try.SRC state.
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_DRP_TRY_MAX_MS 150
/**
* @brief Minimum wait time associated with the Try.SNK state.
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_DRP_TRY_WAIT_MIN_MS 400
/**
* @brief Maximum wait time associated with the Try.SNK state.
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_DRP_TRY_WAIT_MAX_MS 800
/**
* @brief Minimum timeout for transition from Try.SRC to TryWait.SNK.
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_TRY_TIMEOUT_MIN_MS 550
/**
* @brief Maximum timeout for transition from Try.SRC to TryWait.SNK.
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_TRY_TIMEOUT_MAX_MS 1100
/**
* @brief Minimum Time for a DRP to detect that the connected Charge-Through VCONNPowered
* USB Device has been detached, after VBUS has been removed.
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_VPD_DETACH_MIN_MS 10
/**
* @brief Maximum Time for a DRP to detect that the connected Charge-Through VCONNPowered
* USB Device has been detached, after VBUS has been removed.
* See Table 4-30 DRP Timing Parameters
*/
#define TC_T_VPD_DETACH_MAX_MS 20
/**
* @brief Minimum time a port shall wait before it can determine it is attached
* See Table 4-31 CC Timing
*/
#define TC_T_CC_DEBOUNCE_MIN_MS 100
/**
* @brief Maximum time a port shall wait before it can determine it is attached
* See Table 4-31 CC Timing
*/
#define TC_T_CC_DEBOUNCE_MAX_MS 200
/**
* @brief Minimum time a Sink port shall wait before it can determine it is detached due to
* the potential for USB PD signaling on CC as described in the state definitions.
* See Table 4-31 CC Timing
*/
#define TC_T_PD_DEBOUNCE_MIN_MS 10
/**
* @brief Maximum time a Sink port shall wait before it can determine it is detached due to
* the potential for USB PD signaling on CC as described in the state definitions.
* See Table 4-31 CC Timing
*/
#define TC_T_PD_DEBOUNCE_MAX_MS 20
/**
* @brief Minimum Time a port shall wait before it can determine it is re-attached during
* the try-wait process.
* See Table 4-31 CC Timing
*/
#define TC_T_TRY_CC_DEBOUNCE_MIN_MS 10
/**
* @brief Maximum Time a port shall wait before it can determine it is re-attached during
* the try-wait process.
* See Table 4-31 CC Timing
*/
#define TC_T_TRY_CC_DEBOUNCE_MAX_MS 10
/**
* @brief Minimum time a self-powered port shall remain in the ErrorRecovery state.
* See Table 4-31 CC Timing
*/
#define TC_T_ERROR_RECOVERY_SELF_POWERED_MIN_MS 25
/**
* @brief Minimum time a source shall remain in the ErrorRecovery state if it was sourcing
* VCONN in the previous state.
* See Table 4-31 CC Timing
*/
#define TC_T_ERROR_RECOVERY_SOURCE_MIN_MS 240
/**
* @brief Minimum time a Sink port shall wait before it can determine there has been a change
* in Rp where CC is not BMC Idle or the port is unable to detect BMC Idle.
* See Table 4-31 CC Timing
*/
#define TC_T_RP_VALUE_CHANGE_MIN_MS 10
/**
* @brief Maximum time a Sink port shall wait before it can determine there has been a change
* in Rp where CC is not BMC Idle or the port is unable to detect BMC Idle.
* See Table 4-31 CC Timing
*/
#define TC_T_RP_VALUE_CHANGE_MAX_MS 20
/**
* @brief Minimum time a Source shall detect the SRC.Open state. The Source should detect the
* SRC.Open state as quickly as practical.
* See Table 4-31 CC Timing
*/
#define TC_T_SRC_DISCONNECT_MIN_MS 0
/**
* @brief Maximum time a Source shall detect the SRC.Open state. The Source should detect the
* SRC.Open state as quickly as practical.
* See Table 4-31 CC Timing
*/
#define TC_T_SRC_DISCONNECT_MAX_MS 20
/**
* @brief Minimum time to detect connection when neither Port Partner is toggling.
* See Table 4-31 CC Timing
*/
#define TC_T_NO_TOGGLE_CONNECT_MIN_MS 0
/**
* @brief Maximum time to detect connection when neither Port Partner is toggling.
* See Table 4-31 CC Timing
*/
#define TC_T_NO_TOGGLE_CONNECT_MAX_MS 5
/**
* @brief Minimum time to detect connection when one Port Partner is toggling
* 0ms dcSRC.DRP max * tDRP max + 2 * tNoToggleConnect).
* See Table 4-31 CC Timing
*/
#define TC_T_ONE_PORT_TOGGLE_CONNECT_MIN_MS 0
/**
* @brief Maximum time to detect connection when one Port Partner is toggling
* 0ms dcSRC.DRP max * tDRP max + 2 * tNoToggleConnect).
* See Table 4-31 CC Timing
*/
#define TC_T_ONE_PORT_TOGGLE_CONNECT_MAX_MS 80
/**
* @brief Minimum time to detect connection when both Port Partners are toggling
* (0ms 5 * tDRP max + 2 * tNoToggleConnect).
* See Table 4-31 CC Timing
*/
#define TC_T_TWO_PORT_TOGGLE_CONNECT_MIN_MS 0
/**
* @brief Maximum time to detect connection when both Port Partners are toggling
* (0ms 5 * tDRP max + 2 * tNoToggleConnect).
* See Table 4-31 CC Timing
*/
#define TC_T_TWO_PORT_TOGGLE_CONNECT_MAX_MS 510
/**
* @brief Minimum time for a Charge-Through VCONN-Powered USB Device to detect that the
* Charge-Through source has disconnected from CC after VBUS has been removed,
* transition to CTUnattached.VPD, and re-apply its Rp termination advertising
* 3.0 A on the host port CC.
* See Table 4-31 CC Timing
*/
#define TC_T_VPDCTDD_MIN_US 30
/**
* @brief Maximum time for a Charge-Through VCONN-Powered USB Device to detect that the
* Charge-Through source has disconnected from CC after VBUS has been removed,
* transition to CTUnattached.VPD, and re-apply its Rp termination advertising
* 3.0 A on the host port CC.
* See Table 4-31 CC Timing
*/
#define TC_T_VPDCTDD_MAX_MS 5
/**
* @brief Minimum time for a Charge-Through VCONN-Powered USB Device shall remain
* in CTDisabled.VPD state.
* See Table 4-31 CC Timing
*/
#define TC_T_VPDDISABLE_MIN_MS 25
/**
* @brief CC Voltage status
*/
enum tc_cc_voltage_state {
/** No port partner connection */
TC_CC_VOLT_OPEN = 0,
/** Port partner is applying Ra */
TC_CC_VOLT_RA = 1,
/** Port partner is applying Rd */
TC_CC_VOLT_RD = 2,
/** Port partner is applying Rp (0.5A) */
TC_CC_VOLT_RP_DEF = 5,
/*8 Port partner is applying Rp (1.5A) */
TC_CC_VOLT_RP_1A5 = 6,
/** Port partner is applying Rp (3.0A) */
TC_CC_VOLT_RP_3A0 = 7,
};
/**
* @brief VBUS level voltages
*/
enum tc_vbus_level {
/** VBUS is less than vSafe0V max */
TC_VBUS_SAFE0V = 0,
/** VBUS is at least vSafe5V min */
TC_VBUS_PRESENT = 1,
/** VBUS is less than vSinkDisconnect max */
TC_VBUS_REMOVED = 2
};
/**
* @brief Pull-Up resistor values
*/
enum tc_rp_value {
/** Pull-Up resistor for a current of 900mA */
TC_RP_USB = 0,
/** Pull-Up resistor for a current of 1.5A */
TC_RP_1A5 = 1,
/** Pull-Up resistor for a current of 3.0A */
TC_RP_3A0 = 2,
/** No Pull-Up resistor is applied */
TC_RP_RESERVED = 3
};
/**
* @brief CC pull resistors
*/
enum tc_cc_pull {
/** Ra Pull-Down resistor */
TC_CC_RA = 0,
/** Rp Pull-Up resistor */
TC_CC_RP = 1,
/** Rd Pull-Down resistor */
TC_CC_RD = 2,
/** No CC resistor */
TC_CC_OPEN = 3,
/** Ra and Rd Pull-Down resistor */
TC_RA_RD = 4
};
/**
* @brief Cable plug. See 6.2.1.1.7 Cable Plug. Only applies to SOP' and SOP".
* Replaced by pd_power_role for SOP packets.
*/
enum tc_cable_plug {
/* Message originated from a DFP or UFP */
PD_PLUG_FROM_DFP_UFP = 0,
/* Message originated from a Cable Plug or VPD */
PD_PLUG_FROM_CABLE_VPD = 1
};
/**
* @brief Power Delivery Power Role
*/
enum tc_power_role {
/** Power role is a sink */
TC_ROLE_SINK = 0,
/** Power role is a source */
TC_ROLE_SOURCE = 1
};
/**
* @brief Power Delivery Data Role
*/
enum tc_data_role {
/** Data role is an Upstream Facing Port */
TC_ROLE_UFP = 0,
/** Data role is a Downstream Facing Port */
TC_ROLE_DFP = 1,
/** Port is disconnected */
TC_ROLE_DISCONNECTED = 2
};
/**
* @brief Polarity of the CC lines
*/
enum tc_cc_polarity {
/** Use CC1 IO for Power Delivery communication */
TC_POLARITY_CC1 = 0,
/** Use CC2 IO for Power Delivery communication */
TC_POLARITY_CC2 = 1
};
/**
* @brief Possible port partner connections based on CC line states
*/
enum tc_cc_states {
/** No port partner attached */
TC_CC_NONE = 0,
/** From DFP perspective */
/** No UFP accessory connected */
TC_CC_UFP_NONE = 1,
/** UFP Audio accessory connected */
TC_CC_UFP_AUDIO_ACC = 2,
/** UFP Debug accessory connected */
TC_CC_UFP_DEBUG_ACC = 3,
/** Plain UFP attached */
TC_CC_UFP_ATTACHED = 4,
/** From UFP perspective */
/** Plain DFP attached */
TC_CC_DFP_ATTACHED = 5,
/** DFP debug accessory connected */
TC_CC_DFP_DEBUG_ACC = 6
};
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_TC_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/usb_c/usbc_tc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,296 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_UTILS_H_
#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_UTILS_H_
#include <stdbool.h>
#include <stdint.h>
#include <errno.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/slist.h>
#define GPIO_PORT_PIN_MASK_FROM_NGPIOS(ngpios) \
((gpio_port_pins_t)(((uint64_t)1 << (ngpios)) - 1U))
/**
* @brief Makes a bitmask of allowed GPIOs from the @p "gpio-reserved-ranges"
* and @p "ngpios" DT properties values
*
* @param node_id GPIO controller node identifier.
* @return the bitmask of allowed gpios
* @see GPIO_DT_PORT_PIN_MASK_NGPIOS_EXC()
*/
#define GPIO_PORT_PIN_MASK_FROM_DT_NODE(node_id) \
GPIO_DT_PORT_PIN_MASK_NGPIOS_EXC(node_id, DT_PROP(node_id, ngpios))
/**
* @brief Make a bitmask of allowed GPIOs from a DT_DRV_COMPAT instance's GPIO
* @p "gpio-reserved-ranges" and @p "ngpios" DT properties values
*
* @param inst DT_DRV_COMPAT instance number
* @return the bitmask of allowed gpios
* @see GPIO_DT_PORT_PIN_MASK_NGPIOS_EXC()
*/
#define GPIO_PORT_PIN_MASK_FROM_DT_INST(inst) \
GPIO_PORT_PIN_MASK_FROM_DT_NODE(DT_DRV_INST(inst))
/**
* @brief Generic function to insert or remove a callback from a callback list
*
* @param callbacks A pointer to the original list of callbacks (can be NULL)
* @param callback A pointer of the callback to insert or remove from the list
* @param set A boolean indicating insertion or removal of the callback
*
* @return 0 on success, negative errno otherwise.
*/
static inline int gpio_manage_callback(sys_slist_t *callbacks,
struct gpio_callback *callback,
bool set)
{
__ASSERT(callback, "No callback!");
__ASSERT(callback->handler, "No callback handler!");
if (!sys_slist_is_empty(callbacks)) {
if (!sys_slist_find_and_remove(callbacks, &callback->node)) {
if (!set) {
return -EINVAL;
}
}
} else if (!set) {
return -EINVAL;
}
if (set) {
sys_slist_prepend(callbacks, &callback->node);
}
return 0;
}
/**
* @brief Generic function to go through and fire callback from a callback list
*
* @param list A pointer on the gpio callback list
* @param port A pointer on the gpio driver instance
* @param pins The actual pin mask that triggered the interrupt
*/
static inline void gpio_fire_callbacks(sys_slist_t *list,
const struct device *port,
uint32_t pins)
{
struct gpio_callback *cb, *tmp;
SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
if (cb->pin_mask & pins) {
__ASSERT(cb->handler, "No callback handler!");
cb->handler(port, cb, cb->pin_mask & pins);
}
}
}
#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_UTILS_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/gpio/gpio_utils.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 720 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_CMSDK_AHB_H_
#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_CMSDK_AHB_H_
#include <zephyr/drivers/gpio.h>
#ifdef __cplusplus
extern "C" {
#endif
/* ARM LTD CMSDK AHB General Purpose Input/Output (GPIO) */
struct gpio_cmsdk_ahb {
/* Offset: 0x000 (r/w) data register */
volatile uint32_t data;
/* Offset: 0x004 (r/w) data output latch register */
volatile uint32_t dataout;
volatile uint32_t reserved0[2];
/* Offset: 0x010 (r/w) output enable set register */
volatile uint32_t outenableset;
/* Offset: 0x014 (r/w) output enable clear register */
volatile uint32_t outenableclr;
/* Offset: 0x018 (r/w) alternate function set register */
volatile uint32_t altfuncset;
/* Offset: 0x01c (r/w) alternate function clear register */
volatile uint32_t altfuncclr;
/* Offset: 0x020 (r/w) interrupt enable set register */
volatile uint32_t intenset;
/* Offset: 0x024 (r/w) interrupt enable clear register */
volatile uint32_t intenclr;
/* Offset: 0x028 (r/w) interrupt type set register */
volatile uint32_t inttypeset;
/* Offset: 0x02c (r/w) interrupt type clear register */
volatile uint32_t inttypeclr;
/* Offset: 0x030 (r/w) interrupt polarity set register */
volatile uint32_t intpolset;
/* Offset: 0x034 (r/w) interrupt polarity clear register */
volatile uint32_t intpolclr;
union {
/* Offset: 0x038 (r/ ) interrupt status register */
volatile uint32_t intstatus;
/* Offset: 0x038 ( /w) interrupt clear register */
volatile uint32_t intclear;
};
volatile uint32_t reserved1[241];
/* Offset: 0x400 - 0x7fc lower byte masked access register (r/w) */
volatile uint32_t lb_masked[256];
/* Offset: 0x800 - 0xbfc upper byte masked access register (r/w) */
volatile uint32_t ub_masked[256];
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_CMSDK_AHB_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/gpio/gpio_cmsdk_ahb.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 543 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_
#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/types.h>
extern const struct gpio_driver_api gpio_mmio32_api;
struct gpio_mmio32_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
volatile uint32_t *reg;
uint32_t mask;
};
struct gpio_mmio32_context {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
const struct gpio_mmio32_config *config;
};
int gpio_mmio32_init(const struct device *dev);
#ifdef CONFIG_GPIO_MMIO32
/**
* Create a device object for accessing a simple 32-bit i/o register using the
* same APIs as GPIO drivers.
*
* @param node_id The devicetree node identifier.
* @param _address The address of the 32-bit i/o register the device will
* provide access to.
* @param _mask Mask of bits in the register that it is valid to access.
* E.g. 0xffffffffu to allow access to all of them.
*
*/
#define GPIO_MMIO32_INIT(node_id, _address, _mask) \
static struct gpio_mmio32_context _CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _ctx); \
\
static const struct gpio_mmio32_config _CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _cfg) = { \
.common = { \
.port_pin_mask = _mask, \
}, \
.reg = (volatile uint32_t *)_address, \
.mask = _mask, \
}; \
\
DEVICE_DT_DEFINE(node_id, \
&gpio_mmio32_init, \
NULL, \
&_CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _ctx), \
&_CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _cfg), \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&gpio_mmio32_api)
#else /* CONFIG_GPIO_MMIO32 */
/* Null definition for when support not configured into kernel */
#define GPIO_MMIO32_INIT(node_id, _address, _mask)
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/gpio/gpio_mmio32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 531 |
```objective-c
/*
*
*/
struct gpio_acpi_res {
uint8_t num_pins;
uint32_t pad_base;
uint32_t host_owner_reg;
uint32_t pad_owner_reg;
uint32_t intr_stat_reg;
uint16_t base_num;
uintptr_t reg_base;
};
``` | /content/code_sandbox/include/zephyr/drivers/gpio/gpio_intel.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```objective-c
/*
*
*/
/**
* @file
* @brief Backend API for emulated GPIO
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_EMUL_H_
#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_EMUL_H_
#include <zephyr/types.h>
#include <zephyr/drivers/gpio.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Emulated GPIO backend API
* @defgroup gpio_emul Emulated GPIO
* @ingroup gpio_interface
* @{
*
* Behaviour of emulated GPIO is application-defined. As-such, each
* application may
*
* - define a Device Tree overlay file to indicate the number of GPIO
* controllers as well as the number of pins for each controller
* - register a callback with the GPIO controller using
* @ref gpio_add_callback to emulate "wiring"
* - asynchronously call @ref gpio_emul_input_set and / or
* @ref gpio_emul_input_set_masked in order to emulate GPIO events
*
* An example of an appropriate Device Tree overlay file is in
* tests/drivers/gpio/gpio_basic_api/boards/native_sim.overlay.
*
* An example of registering a callback to emulate "wiring" as well as
* an example of calling @ref gpio_emul_input_set is in the file
* tests/drivers/gpio/gpio_basic_api/src/main.c .
*/
/**
* @brief Modify the values of one or more emulated GPIO input @p pins
*
* @param port The emulated GPIO port
* @param pins The mask of pins that have changed
* @param values New values to assign to @p pins
*
* @return 0 on success
* @return -EINVAL if an invalid argument is provided
*/
int gpio_emul_input_set_masked(const struct device *port, gpio_port_pins_t pins,
gpio_port_value_t values);
/**
* @brief Modify the value of one emulated GPIO input @p pin
*
* @param port The emulated GPIO port
* @param pin The pin to modify
* @param value New values to assign to @p pin
*
* @return 0 on success
* @return -EINVAL if an invalid argument is provided
*/
static inline int gpio_emul_input_set(const struct device *port, gpio_pin_t pin,
int value)
{
return gpio_emul_input_set_masked(port, BIT(pin), value ? BIT(pin) : 0);
}
/**
* @brief Read the value of one or more emulated GPIO output @p pins
*
* @param port The emulated GPIO port
* @param pins The mask of pins that have changed
* @param values A pointer to where the value of @p pins will be stored
*
* @return 0 on success
* @return -EINVAL if an invalid argument is provided
*/
int gpio_emul_output_get_masked(const struct device *port, gpio_port_pins_t pins,
gpio_port_value_t *values);
/**
* @brief Read the value of one emulated GPIO output @p pin
*
* @param port The emulated GPIO port
* @param pin The pin to read
*
* @return 0 or 1 on success
* @return -EINVAL if an invalid argument is provided
*/
static inline int gpio_emul_output_get(const struct device *port, gpio_pin_t pin)
{
int ret;
gpio_port_value_t values;
ret = gpio_emul_output_get_masked(port, BIT(pin), &values);
if (ret == 0) {
ret = (values & BIT(pin)) ? 1 : 0;
}
return ret;
}
/**
* @brief Get @p flags for a given emulated GPIO @p pin
*
* For more information on available flags, see @ref gpio_interface.
*
* @param port The emulated GPIO port
* @param pin The pin to retrieve @p flags for
* @param flags a pointer to where the flags for @p pin will be stored
*
* @return 0 on success
* @return -EINVAL if an invalid argument is provided
*/
int gpio_emul_flags_get(const struct device *port, gpio_pin_t pin, gpio_flags_t *flags);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_EMUL_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/gpio/gpio_emul.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 905 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_SX1509B_H_
#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_SX1509B_H_
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
/**
* @brief Configure a pin for LED intensity.
*
* Configure a pin to be controlled by SX1509B LED driver using
* the LED intensity functionality.
* To get back normal GPIO functionality, configure the pin using
* the standard GPIO API.
*
* @param dev Pointer to the device structure for the driver instance.
* @param pin Pin number.
*
* @retval 0 If successful.
* @retval -EWOULDBLOCK if function is called from an ISR.
* @retval -ERANGE if pin number is out of range.
* @retval -EIO if I2C fails.
*/
int sx1509b_led_intensity_pin_configure(const struct device *dev,
gpio_pin_t pin);
/**
* @brief Set LED intensity of selected pin.
*
* @param dev Pointer to the device structure for the driver instance.
* @param pin Pin number.
* @param intensity_val Intensity value.
*
* @retval 0 If successful.
* @retval -EIO if I2C fails.
*/
int sx1509b_led_intensity_pin_set(const struct device *dev, gpio_pin_t pin,
uint8_t intensity_val);
#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_SX1509B_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/gpio/gpio_sx1509b.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 314 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_TIMER_ARM_ARCH_TIMER_H_
#define ZEPHYR_INCLUDE_DRIVERS_TIMER_ARM_ARCH_TIMER_H_
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/types.h>
#define ARM_TIMER_NODE DT_INST(0, arm_armv8_timer)
#define ARM_TIMER_SECURE_IRQ DT_IRQ_BY_IDX(ARM_TIMER_NODE, 0, irq)
#define ARM_TIMER_NON_SECURE_IRQ DT_IRQ_BY_IDX(ARM_TIMER_NODE, 1, irq)
#define ARM_TIMER_VIRTUAL_IRQ DT_IRQ_BY_IDX(ARM_TIMER_NODE, 2, irq)
#define ARM_TIMER_HYP_IRQ DT_IRQ_BY_IDX(ARM_TIMER_NODE, 3, irq)
#define ARM_TIMER_SECURE_PRIO DT_IRQ_BY_IDX(ARM_TIMER_NODE, 0,\
priority)
#define ARM_TIMER_NON_SECURE_PRIO DT_IRQ_BY_IDX(ARM_TIMER_NODE, 1,\
priority)
#define ARM_TIMER_VIRTUAL_PRIO DT_IRQ_BY_IDX(ARM_TIMER_NODE, 2,\
priority)
#define ARM_TIMER_HYP_PRIO DT_IRQ_BY_IDX(ARM_TIMER_NODE, 3,\
priority)
#define ARM_TIMER_SECURE_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 0, flags)
#define ARM_TIMER_NON_SECURE_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 1, flags)
#define ARM_TIMER_VIRTUAL_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 2, flags)
#define ARM_TIMER_HYP_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 3, flags)
#endif /* ZEPHYR_INCLUDE_DRIVERS_TIMER_ARM_ARCH_TIMER_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/timer/arm_arch_timer.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 355 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_TIMER_NRF_GRTC_TIMER_H
#define ZEPHYR_INCLUDE_DRIVERS_TIMER_NRF_GRTC_TIMER_H
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/sys_clock.h>
/** @brief GRTC timer compare event handler.
*
* Called from GRTC ISR context when processing a compare event.
*
* @param id Compare channel ID.
*
* @param expire_time An actual absolute expiration time set for a compare
* channel. It can differ from the requested target time
* and the difference can be used to determine whether the
* time set was delayed.
*
* @param user_data Pointer to a user context data.
*/
typedef void (*z_nrf_grtc_timer_compare_handler_t)(int32_t id, uint64_t expire_time,
void *user_data);
/** @brief Allocate GRTC capture/compare channel.
*
* @retval >=0 Non-negative indicates allocated channel ID.
* @retval -ENOMEM if channel cannot be allocated.
*/
int32_t z_nrf_grtc_timer_chan_alloc(void);
/** @brief Free GRTC capture/compare channel.
*
* @param chan Previously allocated channel ID.
*/
void z_nrf_grtc_timer_chan_free(int32_t chan);
/** @brief Read current absolute time.
*
* @return Current absolute time.
*/
uint64_t z_nrf_grtc_timer_read(void);
/** @brief Check COMPARE event state.
*
* @param chan Channel ID.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
bool z_nrf_grtc_timer_compare_evt_check(int32_t chan);
/** @brief Get COMPARE event register address.
*
* Address can be used for DPPIC.
*
* @param chan Channel ID.
*
* @return Register address.
*/
uint32_t z_nrf_grtc_timer_compare_evt_address_get(int32_t chan);
/** @brief Get CAPTURE task register address.
*
* Address can be used for DPPIC.
*
* @param chan Channel ID.
*
* @return Register address.
*/
uint32_t z_nrf_grtc_timer_capture_task_address_get(int32_t chan);
/** @brief Safely disable compare event interrupt.
*
* Function returns key indicating whether interrupt was already disabled.
*
* @param chan Channel ID.
*
* @return key passed to z_nrf_grtc_timer_compare_int_unlock().
*/
bool z_nrf_grtc_timer_compare_int_lock(int32_t chan);
/** @brief Safely enable compare event interrupt.
*
* Event interrupt is conditionally enabled based on @p key.
*
* @param chan Channel ID.
*
* @param key Key returned by z_nrf_grtc_timer_compare_int_lock().
*/
void z_nrf_grtc_timer_compare_int_unlock(int32_t chan, bool key);
/** @brief Read compare register value.
*
* @param chan Channel ID.
*
* @param val Pointer to store the value.
*
* @retval 0 if the compare register was read successfully.
* @retval -EAGAIN if compare for given channel is not set.
* @retval -EPERM if either channel is unavailable or SYSCOUNTER is not running.
*/
int z_nrf_grtc_timer_compare_read(int32_t chan, uint64_t *val);
/** @brief Set compare channel to given value.
*
* @param chan Channel ID.
*
* @param target_time Absolute target time in GRTC ticks.
*
* @param handler User function called in the context of the GRTC interrupt.
*
* @param user_data Data passed to the handler.
*
* @retval 0 if the compare channel was set successfully.
* @retval -EPERM if either channel is unavailable or SYSCOUNTER is not running.
*/
int z_nrf_grtc_timer_set(int32_t chan, uint64_t target_time,
z_nrf_grtc_timer_compare_handler_t handler, void *user_data);
/** @brief Abort a timer requested with z_nrf_grtc_timer_set().
*
* If an abort operation is performed too late it is still possible for an event
* to fire. The user can detect a spurious event by comparing absolute time
* provided in callback and a result of z_nrf_grtc_timer_read(). During this
* operation interrupt from that compare channel is disabled. Other interrupts
* are not locked during this operation.
*
* @param chan Channel ID between 1 and CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT.
*/
void z_nrf_grtc_timer_abort(int32_t chan);
/** @brief Convert system clock time to GRTC ticks.
*
* @p t can be absolute or relative.
*
* @retval >=0 Positive value represents @p t in GRTC tick value.
* @retval -EINVAL if @p t is out of range.
*/
uint64_t z_nrf_grtc_timer_get_ticks(k_timeout_t t);
/** @brief Prepare channel for timestamp capture.
*
* Use z_nrf_grtc_timer_capture_task_address_get() to determine the register
* address that is used to trigger capture.
*
* @note Capture and compare are mutually exclusive features - they cannot be
* used simultaneously on the same GRTC channel.
*
* @param chan Channel ID.
*
* @retval 0 if the channel was successfully prepared.
* @retval -EPERM if either channel is unavailable or SYSCOUNTER is not running.
*/
int z_nrf_grtc_timer_capture_prepare(int32_t chan);
/** @brief Read timestamp value captured on the channel.
*
* The @p chan must be prepared using z_nrf_grtc_timer_capture_prepare().
*
* @param chan Channel ID.
*
* @param captured_time Pointer to store the value.
*
* @retval 0 if the timestamp was successfully caught and read.
* @retval -EBUSY if capturing has not been triggered.
* @retval -EPERM if either channel is unavailable or SYSCOUNTER is not running.
*/
int z_nrf_grtc_timer_capture_read(int32_t chan, uint64_t *captured_time);
/** @brief Prepare GRTC as a source of wake up event and set the wake up time.
*
* @note Calling this function should be immediately followed by low-power mode enter
* (if it executed successfully).
*
* @param wake_time_us Relative wake up time in microseconds.
*
* @retval 0 if wake up time was successfully set.
* @retval -EPERM if the SYSCOUNTER is not running.
* @retval -ENOMEM if no available GRTC channels were found.
* @retval -EINVAL if @p wake_time_us is too low.
*/
int z_nrf_grtc_wakeup_prepare(uint64_t wake_time_us);
/**
* @brief Initialize the GRTC clock timer driver from an application-
* defined function.
*
* @retval 0 on success.
* @retval -errno Negative error code on failure.
*/
int nrf_grtc_timer_clock_driver_init(void);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_TIMER_NRF_GRTC_TIMER_H */
``` | /content/code_sandbox/include/zephyr/drivers/timer/nrf_grtc_timer.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,470 |
```objective-c
/*
*
*/
/**
* @file
* @brief Timer driver API
*
* Declare API implemented by system timer driver and used by kernel components.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SYSTEM_TIMER_H_
#define ZEPHYR_INCLUDE_DRIVERS_SYSTEM_TIMER_H_
#include <stdbool.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief System Clock APIs
* @defgroup clock_apis System Clock APIs
* @{
*/
/**
* @brief Set system clock timeout
*
* Informs the system clock driver that the next needed call to
* sys_clock_announce() will not be until the specified number of ticks
* from the current time have elapsed. Note that spurious calls
* to sys_clock_announce() are allowed (i.e. it's legal to announce
* every tick and implement this function as a noop), the requirement
* is that one tick announcement should occur within one tick BEFORE
* the specified expiration (that is, passing ticks==1 means "announce
* the next tick", this convention was chosen to match legacy usage).
* Similarly a ticks value of zero (or even negative) is legal and
* treated identically: it simply indicates the kernel would like the
* next tick announcement as soon as possible.
*
* Note that ticks can also be passed the special value K_TICKS_FOREVER,
* indicating that no future timer interrupts are expected or required
* and that the system is permitted to enter an indefinite sleep even
* if this could cause rollover of the internal counter (i.e. the
* system uptime counter is allowed to be wrong
*
* Note also that it is conventional for the kernel to pass INT_MAX
* for ticks if it wants to preserve the uptime tick count but doesn't
* have a specific event to await. The intent here is that the driver
* will schedule any needed timeout as far into the future as
* possible. For the specific case of INT_MAX, the next call to
* sys_clock_announce() may occur at any point in the future, not just
* at INT_MAX ticks. But the correspondence between the announced
* ticks and real-world time must be correct.
*
* A final note about SMP: note that the call to sys_clock_set_timeout()
* is made on any CPU, and reflects the next timeout desired globally.
* The resulting calls(s) to sys_clock_announce() must be properly
* serialized by the driver such that a given tick is announced
* exactly once across the system. The kernel does not (cannot,
* really) attempt to serialize things by "assigning" timeouts to
* specific CPUs.
*
* @param ticks Timeout in tick units
* @param idle Hint to the driver that the system is about to enter
* the idle state immediately after setting the timeout
*/
void sys_clock_set_timeout(int32_t ticks, bool idle);
/**
* @brief Timer idle exit notification
*
* This notifies the timer driver that the system is exiting the idle
* and allows it to do whatever bookkeeping is needed to restore timer
* operation and compute elapsed ticks.
*
* @note Legacy timer drivers also use this opportunity to call back
* into sys_clock_announce() to notify the kernel of expired ticks.
* This is allowed for compatibility, but not recommended. The kernel
* will figure that out on its own.
*/
void sys_clock_idle_exit(void);
/**
* @brief Announce time progress to the kernel
*
* Informs the kernel that the specified number of ticks have elapsed
* since the last call to sys_clock_announce() (or system startup for
* the first call). The timer driver is expected to delivery these
* announcements as close as practical (subject to hardware and
* latency limitations) to tick boundaries.
*
* @param ticks Elapsed time, in ticks
*/
void sys_clock_announce(int32_t ticks);
/**
* @brief Ticks elapsed since last sys_clock_announce() call
*
* Queries the clock driver for the current time elapsed since the
* last call to sys_clock_announce() was made. The kernel will call
* this with appropriate locking, the driver needs only provide an
* instantaneous answer.
*/
uint32_t sys_clock_elapsed(void);
/**
* @brief Disable system timer.
*
* @note Not all system timer drivers has the capability of being disabled.
* The config @kconfig{CONFIG_SYSTEM_TIMER_HAS_DISABLE_SUPPORT} can be used to
* check if the system timer has the capability of being disabled.
*/
void sys_clock_disable(void);
/**
* @brief Hardware cycle counter
*
* Timer drivers are generally responsible for the system cycle
* counter as well as the tick announcements. This function is
* generally called out of the architecture layer (@see
* arch_k_cycle_get_32()) to implement the cycle counter, though the
* user-facing API is owned by the architecture, not the driver. The
* rate must match CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
*
* @note
* If the counter clock is large enough for this to wrap its full range
* within a few seconds (i.e. CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is greater
* than 50Mhz) then it is recommended to also implement
* sys_clock_cycle_get_64().
*
* @return The current cycle time. This should count up monotonically
* through the full 32 bit space, wrapping at 0xffffffff. Hardware
* with fewer bits of precision in the timer is expected to synthesize
* a 32 bit count.
*/
uint32_t sys_clock_cycle_get_32(void);
/**
* @brief 64 bit hardware cycle counter
*
* As for sys_clock_cycle_get_32(), but with a 64 bit return value.
* Not all hardware has 64 bit counters. This function need be
* implemented only if CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER is set.
*
* @note
* If the counter clock is large enough for sys_clock_cycle_get_32() to wrap
* its full range within a few seconds (i.e. CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
* is greater than 50Mhz) then it is recommended to implement this API.
*
* @return The current cycle time. This should count up monotonically
* through the full 64 bit space, wrapping at 2^64-1. Hardware with
* fewer bits of precision in the timer is generally not expected to
* implement this API.
*/
uint64_t sys_clock_cycle_get_64(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SYSTEM_TIMER_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/timer/system_timer.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,408 |
```objective-c
*
*/
#ifndef ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_
#define ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_
#include <zephyr/devicetree.h>
#define TI_DM_TIMER_TIDR (0x00)
#define TI_DM_TIMER_TIOCP_CFG (0x10)
#define TI_DM_TIMER_IRQ_EOI (0x20)
#define TI_DM_TIMER_IRQSTATUS_RAW (0x24)
#define TI_DM_TIMER_IRQSTATUS (0x28) /* Interrupt status register */
#define TI_DM_TIMER_IRQENABLE_SET (0x2c) /* Interrupt enable register */
#define TI_DM_TIMER_IRQENABLE_CLR (0x30) /* Interrupt disable register */
#define TI_DM_TIMER_IRQWAKEEN (0x34)
#define TI_DM_TIMER_TCLR (0x38) /* Control register */
#define TI_DM_TIMER_TCRR (0x3c) /* Counter register */
#define TI_DM_TIMER_TLDR (0x40) /* Load register */
#define TI_DM_TIMER_TTGR (0x44)
#define TI_DM_TIMER_TWPS (0x48)
#define TI_DM_TIMER_TMAR (0x4c) /* Match register */
#define TI_DM_TIMER_TCAR1 (0x50)
#define TI_DM_TIMER_TSICR (0x54)
#define TI_DM_TIMER_TCAR2 (0x58)
#define TI_DM_TIMER_TPIR (0x5c)
#define TI_DM_TIMER_TNIR (0x60)
#define TI_DM_TIMER_TCVR (0x64)
#define TI_DM_TIMER_TOCR (0x68)
#define TI_DM_TIMER_TOWR (0x6c)
#define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_SHIFT (0)
#define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_MASK (0x00000001)
#define TI_DM_TIMER_IRQSTATUS_OVF_IT_FLAG_SHIFT (1)
#define TI_DM_TIMER_IRQSTATUS_OVF_IT_FLAG_MASK (0x00000002)
#define TI_DM_TIMER_IRQSTATUS_TCAR_IT_FLAG_SHIFT (2)
#define TI_DM_TIMER_IRQSTATUS_TCAR_IT_FLAG_MASK (0x00000004)
#define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_SHIFT (0)
#define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_MASK (0x00000001)
#define TI_DM_TIMER_IRQENABLE_SET_OVF_EN_FLAG_SHIFT (1)
#define TI_DM_TIMER_IRQENABLE_SET_OVF_EN_FLAG_MASK (0x00000002)
#define TI_DM_TIMER_IRQENABLE_SET_TCAR_EN_FLAG_SHIFT (2)
#define TI_DM_TIMER_IRQENABLE_SET_TCAR_EN_FLAG_MASK (0x00000004)
#define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_SHIFT (0)
#define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_MASK (0x00000001)
#define TI_DM_TIMER_IRQENABLE_CLR_OVF_EN_FLAG_SHIFT (1)
#define TI_DM_TIMER_IRQENABLE_CLR_OVF_EN_FLAG_MASK (0x00000002)
#define TI_DM_TIMER_IRQENABLE_CLR_TCAR_EN_FLAG_SHIFT (2)
#define TI_DM_TIMER_IRQENABLE_CLR_TCAR_EN_FLAG_MASK (0x00000004)
#define TI_DM_TIMER_TCLR_ST_SHIFT (0)
#define TI_DM_TIMER_TCLR_ST_MASK (0x00000001)
#define TI_DM_TIMER_TCLR_AR_SHIFT (1)
#define TI_DM_TIMER_TCLR_AR_MASK (0x00000002)
#define TI_DM_TIMER_TCLR_PTV_SHIFT (2)
#define TI_DM_TIMER_TCLR_PTV_MASK (0x0000001c)
#define TI_DM_TIMER_TCLR_PRE_SHIFT (5)
#define TI_DM_TIMER_TCLR_PRE_MASK (0x00000020)
#define TI_DM_TIMER_TCLR_CE_SHIFT (6)
#define TI_DM_TIMER_TCLR_CE_MASK (0x00000040)
#define TI_DM_TIMER_TCLR_SCPWM_SHIFT (7)
#define TI_DM_TIMER_TCLR_SCPWM_MASK (0x00000080)
#define TI_DM_TIMER_TCLR_TCM_SHIFT (8)
#define TI_DM_TIMER_TCLR_TCM_MASK (0x00000300)
#define TI_DM_TIMER_TCLR_TRG_SHIFT (10)
#define TI_DM_TIMER_TCLR_TRG_MASK (0x00000c00)
#define TI_DM_TIMER_TCLR_PT_SHIFT (12)
#define TI_DM_TIMER_TCLR_PT_MASK (0x00001000)
#define TI_DM_TIMER_TCLR_CAPT_MODE_SHIFT (13)
#define TI_DM_TIMER_TCLR_CAPT_MODE_MASK (0x00002000)
#define TI_DM_TIMER_TCLR_GPO_CFG_SHIFT (14)
#define TI_DM_TIMER_TCLR_GPO_CFG_MASK (0x00004000)
#define TI_DM_TIMER_TCRR_TIMER_COUNTER_SHIFT (0)
#define TI_DM_TIMER_TCRR_TIMER_COUNTER_MASK (0xffffffff)
#define TI_DM_TIMER_TLDR_LOAD_VALUE_SHIFT (0)
#define TI_DM_TIMER_TLDR_LOAD_VALUE_MASK (0xffffffff)
#define TI_DM_TIMER_TMAR_COMPARE_VALUE_SHIFT (0)
#define TI_DM_TIMER_TMAR_COMPARE_VALUE_MASK (0xffffffff)
#endif /* ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/timer/ti_dmtimer.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,101 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_TIMER_NRF_RTC_TIMER_H
#define ZEPHYR_INCLUDE_DRIVERS_TIMER_NRF_RTC_TIMER_H
#include <zephyr/sys_clock.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @brief Maximum allowed time span that is considered to be in the future.
*/
#define NRF_RTC_TIMER_MAX_SCHEDULE_SPAN BIT(23)
/** @brief RTC timer compare event handler.
*
* Called from RTC ISR context when processing a compare event.
*
* @param id Compare channel ID.
*
* @param expire_time An actual absolute expiration time set for a compare
* channel. It can differ from the requested target time
* and the difference can be used to determine whether the
* time set was delayed.
*
* @param user_data Pointer to a user context data.
*/
typedef void (*z_nrf_rtc_timer_compare_handler_t)(int32_t id,
uint64_t expire_time,
void *user_data);
/** @brief Allocate RTC compare channel.
*
* Channel 0 is used for the system clock.
*
* @retval Non-negative indicates allocated channel ID.
* @retval -ENOMEM if channel cannot be allocated.
*/
int32_t z_nrf_rtc_timer_chan_alloc(void);
/** @brief Free RTC compare channel.
*
* @param chan Previously allocated channel ID.
*/
void z_nrf_rtc_timer_chan_free(int32_t chan);
/** @brief Read current absolute time.
*
* @return Current absolute time.
*/
uint64_t z_nrf_rtc_timer_read(void);
/** @brief Get COMPARE event register address.
*
* Address can be used for (D)PPI.
*
* @param chan Channel ID between 0 and @kconfig{CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT}.
*
* @return Register address.
*/
uint32_t z_nrf_rtc_timer_compare_evt_address_get(int32_t chan);
/** @brief Get CAPTURE task register address.
*
* Address can be used for (D)PPI.
*
* @note Not all platforms have CAPTURE task.
*
* @param chan Channel ID between 1 and @kconfig{CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT}.
*
* @return Register address.
*/
uint32_t z_nrf_rtc_timer_capture_task_address_get(int32_t chan);
/** @brief Safely disable compare event interrupt.
*
* Function returns key indicating whether interrupt was already disabled.
*
* @param chan Channel ID between 1 and @kconfig{CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT}.
*
* @return key passed to @ref z_nrf_rtc_timer_compare_int_unlock.
*/
bool z_nrf_rtc_timer_compare_int_lock(int32_t chan);
/** @brief Safely enable compare event interrupt.
*
* Event interrupt is conditionally enabled based on @p key.
*
* @param chan Channel ID between 1 and @kconfig{CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT}.
*
* @param key Key returned by @ref z_nrf_rtc_timer_compare_int_lock.
*/
void z_nrf_rtc_timer_compare_int_unlock(int32_t chan, bool key);
/** @brief Read compare register value.
*
* @param chan Channel ID between 0 and @kconfig{CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT}.
*
* @return Value set in the compare register.
*/
uint32_t z_nrf_rtc_timer_compare_read(int32_t chan);
/** @brief Try to set compare channel to given value.
*
* Provided value is absolute and cannot be further in the future than
* @c NRF_RTC_TIMER_MAX_SCHEDULE_SPAN. If given value is in the past then an RTC
* interrupt is triggered immediately. Otherwise function continuously retries
* to set compare register until value that is written is far enough in the
* future and will generate an event. Because of that, compare register value
* may be different than the one requested. During this operation interrupt
* from that compare channel is disabled. Other interrupts are not locked during
* this operation.
*
* @param chan Channel ID between 1 and @kconfig{CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT}.
*
* @param target_time Absolute target time in ticks.
*
* @param handler User function called in the context of the RTC interrupt.
*
* @param user_data Data passed to the handler.
*
* @retval 0 if the compare channel was set successfully.
* @retval -EINVAL if provided target time was further than
* @c NRF_RTC_TIMER_MAX_SCHEDULE_SPAN ticks in the future.
*
* @sa @ref z_nrf_rtc_timer_exact_set
*/
int z_nrf_rtc_timer_set(int32_t chan, uint64_t target_time,
z_nrf_rtc_timer_compare_handler_t handler,
void *user_data);
/** @brief Try to set compare channel exactly to given value.
*
* @note This function is similar to @ref z_nrf_rtc_timer_set, but the compare
* channel will be set to expected value only when it can be guaranteed that
* the hardware event will be generated exactly at expected @c target_time in
* the future. If the @c target_time is in the past or so close in the future
* that the reliable generation of event would require adjustment of compare
* value (as would @ref z_nrf_rtc_timer_set function do), neither the hardware
* event nor interrupt will be generated and the function fails.
*
* @param chan Channel ID between 1 and @kconfig{CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT}.
*
* @param target_time Absolute target time in ticks.
*
* @param handler User function called in the context of the RTC interrupt.
*
* @param user_data Data passed to the handler.
*
* @retval 0 if the compare channel was set successfully.
* @retval -EINVAL if provided target time was further than
* @c NRF_RTC_TIMER_MAX_SCHEDULE_SPAN ticks in the future
* or the target time is in the past or is so close in the future that
* event generation could not be guaranteed without adjusting
* compare value of that channel.
*/
int z_nrf_rtc_timer_exact_set(int32_t chan, uint64_t target_time,
z_nrf_rtc_timer_compare_handler_t handler,
void *user_data);
/** @brief Abort a timer requested with @ref z_nrf_rtc_timer_set.
*
* If an abort operation is performed too late it is still possible for an event
* to fire. The user can detect a spurious event by comparing absolute time
* provided in callback and a result of @ref z_nrf_rtc_timer_read. During this
* operation interrupt from that compare channel is disabled. Other interrupts
* are not locked during this operation.
*
* @param chan Channel ID between 1 and @kconfig{CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT}.
*/
void z_nrf_rtc_timer_abort(int32_t chan);
/** @brief Convert system clock time to RTC ticks.
*
* @p t can be absolute or relative. @p t cannot be further into the future
* from now than the RTC range (e.g. 512 seconds if RTC is running at 32768 Hz).
*
* @retval Positive value represents @p t in RTC tick value.
* @retval -EINVAL if @p t is out of range.
*/
uint64_t z_nrf_rtc_timer_get_ticks(k_timeout_t t);
/** @brief Get offset between nrf53 network cpu system clock and application cpu
* system clock.
*
* Returned value added to the current system tick on network cpu gives current
* application cpu system tick. Function can only be used on network cpu. It
* requires @kconfig{CONFIG_NRF53_SYNC_RTC} being enabled.
*
* @retval Non-negative offset given in RTC ticks.
* @retval -ENOSYS if operation is not supported.
* @retval -EBUSY if synchronization is not yet completed.
*/
int z_nrf_rtc_timer_nrf53net_offset_get(void);
/** @brief Move RTC counter forward using TRIGOVRFLW hardware feature.
*
* RTC has a hardware feature which can force counter to jump to 0xFFFFF0 value
* which is close to overflow. Function is using this feature and updates
* driver internal to perform time shift to the future. Operation can only be
* performed when there are no active alarms set. It should be used for testing
* only.
*
* @retval 0 on successful shift.
* @retval -EBUSY if there are active alarms.
* @retval -EAGAIN if current counter value is too close to overflow.
* @retval -ENOTSUP if option is disabled in Kconfig or additional channels are enabled.
*/
int z_nrf_rtc_timer_trigger_overflow(void);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_TIMER_NRF_RTC_TIMER_H */
``` | /content/code_sandbox/include/zephyr/drivers/timer/nrf_rtc_timer.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,859 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_GNSS_GNSS_H_
#define ZEPHYR_DRIVERS_GNSS_GNSS_H_
#include <zephyr/drivers/gnss.h>
/** Internal function used by GNSS drivers to publish GNSS data */
void gnss_publish_data(const struct device *dev, const struct gnss_data *data);
/** Internal function used by GNSS drivers to publish GNSS satellites */
void gnss_publish_satellites(const struct device *dev, const struct gnss_satellite *satellites,
uint16_t size);
#endif /* ZEPHYR_DRIVERS_GNSS_GNSS_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/gnss/gnss_publish.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_VC_H_
#define ZEPHYR_INCLUDE_DRIVERS_PCIE_VC_H_
/**
* @brief PCIe Virtual Channel Host Interface
* @defgroup pcie_vc_host_interface PCIe Virtual Channel Host Interface
* @ingroup pcie_host_interface
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/kernel.h>
#include <zephyr/types.h>
#include <stdbool.h>
#include <zephyr/drivers/pcie/pcie.h>
/*
* 1 default VC + 7 extended VCs
*/
#define PCIE_VC_MAX_COUNT 8U
#define PCIE_VC_SET_TC0 BIT(0)
#define PCIE_VC_SET_TC1 BIT(1)
#define PCIE_VC_SET_TC2 BIT(2)
#define PCIE_VC_SET_TC3 BIT(3)
#define PCIE_VC_SET_TC4 BIT(4)
#define PCIE_VC_SET_TC5 BIT(5)
#define PCIE_VC_SET_TC6 BIT(6)
#define PCIE_VC_SET_TC7 BIT(7)
struct pcie_vctc_map {
/*
* Map the TCs for each VC by setting bits relevantly
* Note: one bit cannot be set more than once among the VCs
*/
uint8_t vc_tc[PCIE_VC_MAX_COUNT];
/*
* Number of VCs being addressed
*/
int vc_count;
};
/**
* @brief Enable PCIe Virtual Channel handling
* @param bdf the target PCI endpoint
* @return 0 on success, a negative error code otherwise
*
* Note: Not being able to enable such feature is a non-fatal error
* and any code using it should behave accordingly (displaying some info,
* and ignoring it for instance).
*/
int pcie_vc_enable(pcie_bdf_t bdf);
/**
* @brief Disable PCIe Virtual Channel handling
* @param bdf the target PCI endpoint
* @return 0 on success, a negative error code otherwise
*/
int pcie_vc_disable(pcie_bdf_t bdf);
/**
* @brief Map PCIe TC/VC
* @param bdf the target PCI endpoint
* @param map the tc/vc map to apply
* @return 0 on success, a negative error code otherwise
*
* Note: VC must be disabled prior to call this function and
* enabled afterward in order for the endpoint to take advandage of the map.
*
* Note: Not being able to enable such feature is a non-fatal error
* and any code using it should behave accordingly (displaying some info,
* and ignoring it for instance).
*/
int pcie_vc_map_tc(pcie_bdf_t bdf, struct pcie_vctc_map *map);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_VC_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/pcie/vc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 600 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MSPI_DEVICETREE_H_
#define ZEPHYR_INCLUDE_DRIVERS_MSPI_DEVICETREE_H_
/**
* @brief MSPI Devicetree related macros
* @defgroup mspi_devicetree MSPI Devicetree related macros
* @ingroup io_interfaces
* @{
*/
#include <zephyr/drivers/gpio.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Structure initializer for <tt>struct mspi_dev_cfg</tt> from devicetree
*
* This helper macro expands to a static initializer for a <tt>struct
* mspi_dev_cfg</tt> by reading the relevant data from the devicetree.
*
* @param mspi_dev Devicetree node identifier for the MSPI device whose
* struct mspi_dev_cfg to create an initializer for
*/
#define MSPI_DEVICE_CONFIG_DT(mspi_dev) \
{ \
.ce_num = DT_PROP_OR(mspi_dev, mspi_hardware_ce_num, 0), \
.freq = DT_PROP(mspi_dev, mspi_max_frequency), \
.io_mode = DT_ENUM_IDX_OR(mspi_dev, mspi_io_mode, \
MSPI_IO_MODE_SINGLE), \
.data_rate = DT_ENUM_IDX_OR(mspi_dev, mspi_data_rate, \
MSPI_DATA_RATE_SINGLE), \
.cpp = DT_ENUM_IDX_OR(mspi_dev, mspi_cpp_mode, MSPI_CPP_MODE_0), \
.endian = DT_ENUM_IDX_OR(mspi_dev, mspi_endian, \
MSPI_XFER_LITTLE_ENDIAN), \
.ce_polarity = DT_ENUM_IDX_OR(mspi_dev, mspi_ce_polarity, \
MSPI_CE_ACTIVE_LOW), \
.dqs_enable = DT_PROP(mspi_dev, mspi_dqs_enable), \
.rx_dummy = DT_PROP_OR(mspi_dev, rx_dummy, 0), \
.tx_dummy = DT_PROP_OR(mspi_dev, tx_dummy, 0), \
.read_cmd = DT_PROP_OR(mspi_dev, read_command, 0), \
.write_cmd = DT_PROP_OR(mspi_dev, write_command, 0), \
.cmd_length = DT_ENUM_IDX_OR(mspi_dev, command_length, 0), \
.addr_length = DT_ENUM_IDX_OR(mspi_dev, address_length, 0), \
.mem_boundary = COND_CODE_1(DT_NODE_HAS_PROP(mspi_dev, ce_break_config), \
(DT_PROP_BY_IDX(mspi_dev, ce_break_config, 0)), \
(0)), \
.time_to_break = COND_CODE_1(DT_NODE_HAS_PROP(mspi_dev, ce_break_config), \
(DT_PROP_BY_IDX(mspi_dev, ce_break_config, 1)), \
(0)), \
}
/**
* @brief Structure initializer for <tt>struct mspi_dev_cfg</tt> from devicetree instance
*
* This is equivalent to
* <tt>MSPI_DEVICE_CONFIG_DT(DT_DRV_INST(inst))</tt>.
*
* @param inst Devicetree instance number
*/
#define MSPI_DEVICE_CONFIG_DT_INST(inst) MSPI_DEVICE_CONFIG_DT(DT_DRV_INST(inst))
/**
* @brief Structure initializer for <tt>struct mspi_xip_cfg</tt> from devicetree
*
* This helper macro expands to a static initializer for a <tt>struct
* mspi_xip_cfg</tt> by reading the relevant data from the devicetree.
*
* @param mspi_dev Devicetree node identifier for the MSPI device whose
* struct mspi_xip_cfg to create an initializer for
*/
#define MSPI_XIP_CONFIG_DT_NO_CHECK(mspi_dev) \
{ \
.enable = DT_PROP_BY_IDX(mspi_dev, xip_config, 0), \
.address_offset = DT_PROP_BY_IDX(mspi_dev, xip_config, 1), \
.size = DT_PROP_BY_IDX(mspi_dev, xip_config, 2), \
.permission = DT_PROP_BY_IDX(mspi_dev, xip_config, 3), \
}
/**
* @brief Structure initializer for <tt>struct mspi_xip_cfg</tt> from devicetree
*
* This helper macro check whether <tt>xip_config</tt> binding exist first
* before calling <tt>MSPI_XIP_CONFIG_DT_NO_CHECK</tt>.
*
* @param mspi_dev Devicetree node identifier for the MSPI device whose
* struct mspi_xip_cfg to create an initializer for
*/
#define MSPI_XIP_CONFIG_DT(mspi_dev) \
COND_CODE_1(DT_NODE_HAS_PROP(mspi_dev, xip_config), \
(MSPI_XIP_CONFIG_DT_NO_CHECK(mspi_dev)), \
({}))
/**
* @brief Structure initializer for <tt>struct mspi_xip_cfg</tt> from devicetree instance
*
* This is equivalent to
* <tt>MSPI_XIP_CONFIG_DT(DT_DRV_INST(inst))</tt>.
*
* @param inst Devicetree instance number
*/
#define MSPI_XIP_CONFIG_DT_INST(inst) MSPI_XIP_CONFIG_DT(DT_DRV_INST(inst))
/**
* @brief Structure initializer for <tt>struct mspi_scramble_cfg</tt> from devicetree
*
* This helper macro expands to a static initializer for a <tt>struct
* mspi_scramble_cfg</tt> by reading the relevant data from the devicetree.
*
* @param mspi_dev Devicetree node identifier for the MSPI device whose
* struct mspi_scramble_cfg to create an initializer for
*/
#define MSPI_SCRAMBLE_CONFIG_DT_NO_CHECK(mspi_dev) \
{ \
.enable = DT_PROP_BY_IDX(mspi_dev, scramble_config, 0), \
.address_offset = DT_PROP_BY_IDX(mspi_dev, scramble_config, 1), \
.size = DT_PROP_BY_IDX(mspi_dev, scramble_config, 2), \
}
/**
* @brief Structure initializer for <tt>struct mspi_scramble_cfg</tt> from devicetree
*
* This helper macro check whether <tt>scramble_config</tt> binding exist first
* before calling <tt>MSPI_SCRAMBLE_CONFIG_DT_NO_CHECK</tt>.
*
* @param mspi_dev Devicetree node identifier for the MSPI device whose
* struct mspi_scramble_cfg to create an initializer for
*/
#define MSPI_SCRAMBLE_CONFIG_DT(mspi_dev) \
COND_CODE_1(DT_NODE_HAS_PROP(mspi_dev, scramble_config), \
(MSPI_SCRAMBLE_CONFIG_DT_NO_CHECK(mspi_dev)), \
({}))
/**
* @brief Structure initializer for <tt>struct mspi_scramble_cfg</tt> from devicetree instance
*
* This is equivalent to
* <tt>MSPI_SCRAMBLE_CONFIG_DT(DT_DRV_INST(inst))</tt>.
*
* @param inst Devicetree instance number
*/
#define MSPI_SCRAMBLE_CONFIG_DT_INST(inst) MSPI_SCRAMBLE_CONFIG_DT(DT_DRV_INST(inst))
/**
* @brief Structure initializer for <tt>struct mspi_dev_id</tt> from devicetree
*
* This helper macro expands to a static initializer for a <tt>struct
* mspi_dev_id</tt> by reading the relevant data from the devicetree.
*
* @param mspi_dev Devicetree node identifier for the MSPI device whose
* struct mspi_dev_id to create an initializer for
*/
#define MSPI_DEVICE_ID_DT(mspi_dev) \
{ \
.ce = MSPI_DEV_CE_GPIOS_DT_SPEC_GET(mspi_dev), \
.dev_idx = DT_REG_ADDR(mspi_dev), \
}
/**
* @brief Structure initializer for <tt>struct mspi_dev_id</tt> from devicetree instance
*
* This is equivalent to
* <tt>MSPI_DEVICE_ID_DT(DT_DRV_INST(inst))</tt>.
*
* @param inst Devicetree instance number
*/
#define MSPI_DEVICE_ID_DT_INST(inst) MSPI_DEVICE_ID_DT(DT_DRV_INST(inst))
/**
* @brief Get a <tt>struct gpio_dt_spec</tt> for a MSPI device's chip enable pin
*
* Example devicetree fragment:
*
* @code{.devicetree}
* gpio1: gpio@abcd0001 { ... };
*
* gpio2: gpio@abcd0002 { ... };
*
* mspi@abcd0003 {
* compatible = "ambiq,mspi";
* ce-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
* <&gpio2 20 GPIO_ACTIVE_LOW>;
*
* a: mspi-dev-a@0 {
* reg = <0>;
* };
*
* b: mspi-dev-b@1 {
* reg = <1>;
* };
* };
* @endcode
*
* Example usage:
*
* @code{.c}
* MSPI_DEV_CE_GPIOS_DT_SPEC_GET(DT_NODELABEL(a)) \
* // { DEVICE_DT_GET(DT_NODELABEL(gpio1)), 10, GPIO_ACTIVE_LOW }
* MSPI_DEV_CE_GPIOS_DT_SPEC_GET(DT_NODELABEL(b)) \
* // { DEVICE_DT_GET(DT_NODELABEL(gpio2)), 20, GPIO_ACTIVE_LOW }
* @endcode
*
* @param mspi_dev a MSPI device node identifier
* @return #gpio_dt_spec struct corresponding with mspi_dev's chip enable
*/
#define MSPI_DEV_CE_GPIOS_DT_SPEC_GET(mspi_dev) \
GPIO_DT_SPEC_GET_BY_IDX_OR(DT_BUS(mspi_dev), ce_gpios, DT_REG_ADDR(mspi_dev), {})
/**
* @brief Get a <tt>struct gpio_dt_spec</tt> for a MSPI device's chip enable pin
*
* This is equivalent to
* <tt>MSPI_DEV_CE_GPIOS_DT_SPEC_GET(DT_DRV_INST(inst))</tt>.
*
* @param inst Devicetree instance number
* @return #gpio_dt_spec struct corresponding with mspi_dev's chip enable
*/
#define MSPI_DEV_CE_GPIOS_DT_SPEC_INST_GET(inst) \
MSPI_DEV_CE_GPIOS_DT_SPEC_GET(DT_DRV_INST(inst))
/**
* @brief Get an array of <tt>struct gpio_dt_spec</tt> from devicetree for a MSPI controller
*
* This helper macro check whether <tt>ce_gpios</tt> binding exist first
* before calling <tt>GPIO_DT_SPEC_GET_BY_IDX</tt> and expand to an array of
* gpio_dt_spec.
*
* @param node_id Devicetree node identifier for the MSPI controller
* @return an array of gpio_dt_spec struct corresponding with mspi_dev's chip enables
*/
#define MSPI_CE_GPIOS_DT_SPEC_GET(node_id) \
{ \
COND_CODE_1(DT_NODE_HAS_PROP(node_id, ce_gpios), \
(DT_FOREACH_PROP_ELEM_SEP(node_id, ce_gpios, GPIO_DT_SPEC_GET_BY_IDX, (,))), \
()) \
}
/**
* @brief Get an array of <tt>struct gpio_dt_spec</tt> for a MSPI controller
*
* This is equivalent to
* <tt>MSPI_CE_GPIOS_DT_SPEC_GET(DT_DRV_INST(inst))</tt>.
*
* @param inst Devicetree instance number
* @return an array of gpio_dt_spec struct corresponding with mspi_dev's chip enables
*/
#define MSPI_CE_GPIOS_DT_SPEC_INST_GET(inst) \
MSPI_CE_GPIOS_DT_SPEC_GET(DT_DRV_INST(inst))
/**
* @brief Initialize and get a pointer to a @p mspi_ce_control from a
* devicetree node identifier
*
* This helper is useful for initializing a device on a MSPI bus. It
* initializes a struct mspi_ce_control and returns a pointer to it.
* Here, @p node_id is a node identifier for a MSPI device, not a MSPI
* controller.
*
* Example devicetree fragment:
*
* @code{.devicetree}
* mspi@abcd0001 {
* ce-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
* mspidev: mspi-device@0 { ... };
* };
* @endcode
*
* Example usage:
*
* @code{.c}
* struct mspi_ce_control ctrl =
* MSPI_CE_CONTROL_INIT(DT_NODELABEL(mspidev), 2);
* @endcode
*
* This example is equivalent to:
*
* @code{.c}
* struct mspi_ce_control ctrl = {
* .gpio = MSPI_DEV_CE_GPIOS_DT_SPEC_GET(DT_NODELABEL(mspidev)),
* .delay = 2,
* };
* @endcode
*
* @param node_id Devicetree node identifier for a device on a MSPI bus
* @param delay_ The @p delay field to set in the @p mspi_ce_control
* @return a pointer to the @p mspi_ce_control structure
*/
#define MSPI_CE_CONTROL_INIT(node_id, delay_) \
{ \
.gpio = MSPI_DEV_CE_GPIOS_DT_SPEC_GET(node_id), .delay = (delay_), \
}
/**
* @brief Get a pointer to a @p mspi_ce_control from a devicetree node
*
* This is equivalent to
* <tt>MSPI_CE_CONTROL_INIT(DT_DRV_INST(inst), delay)</tt>.
*
* Therefore, @p DT_DRV_COMPAT must already be defined before using
* this macro.
*
* @param inst Devicetree node instance number
* @param delay_ The @p delay field to set in the @p mspi_ce_control
* @return a pointer to the @p mspi_ce_control structure
*/
#define MSPI_CE_CONTROL_INIT_INST(inst, delay_) MSPI_CE_CONTROL_INIT(DT_DRV_INST(inst), delay_)
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DRIVERS_MSPI_DEVICETREE_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mspi/devicetree.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,172 |
```objective-c
/**
* @file
*
* @brief Public APIs for the PCIe Controllers drivers.
*/
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_
#define ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_
#include <zephyr/types.h>
#include <zephyr/device.h>
#ifdef CONFIG_PCIE_MSI
#include <zephyr/drivers/pcie/msi.h>
#endif
/**
* @brief PCI Express Controller Interface
* @defgroup pcie_controller_interface PCI Express Controller Interface
* @ingroup io_interfaces
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Function called to read a 32-bit word from an endpoint's configuration space.
*
* Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
* configuration space access method (I/O port, memory mapped or custom method)
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param reg the configuration word index (not address)
* @return the word read (0xFFFFFFFFU if nonexistent endpoint or word)
*/
typedef uint32_t (*pcie_ctrl_conf_read_t)(const struct device *dev, pcie_bdf_t bdf,
unsigned int reg);
/**
* @brief Function called to write a 32-bit word to an endpoint's configuration space.
*
* Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
* configuration space access method (I/O port, memory mapped or custom method)
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param reg the configuration word index (not address)
* @param data the value to write
*/
typedef void (*pcie_ctrl_conf_write_t)(const struct device *dev, pcie_bdf_t bdf,
unsigned int reg, uint32_t data);
/**
* @brief Function called to allocate a memory region subset for an endpoint Base Address Register.
*
* When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
* via the Base Address Registers from I/O or Memory types.
*
* This call allocates such zone in the PCI Express Controller memory regions if
* such region is available and space is still available.
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param mem True if the BAR is of memory type
* @param mem64 True if the BAR is of 64bit memory type
* @param bar_size Size in bytes of the Base Address Register as returned by HW
* @param bar_bus_addr bus-centric address allocated to be written in the BAR register
* @return True if allocation was possible, False if allocation failed
*/
typedef bool (*pcie_ctrl_region_allocate_t)(const struct device *dev, pcie_bdf_t bdf,
bool mem, bool mem64, size_t bar_size,
uintptr_t *bar_bus_addr);
/**
* @brief Function called to get the current allocation base of a memory region subset
* for an endpoint Base Address Register.
*
* When enumerating PCIe Endpoints, Type1 bridge endpoints requires a range of memory
* allocated by all endpoints in the bridged bus.
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param mem True if the BAR is of memory type
* @param mem64 True if the BAR is of 64bit memory type
* @param align size to take in account for alignment
* @param bar_base_addr bus-centric address allocation base
* @return True if allocation was possible, False if allocation failed
*/
typedef bool (*pcie_ctrl_region_get_allocate_base_t)(const struct device *dev, pcie_bdf_t bdf,
bool mem, bool mem64, size_t align,
uintptr_t *bar_base_addr);
/**
* @brief Function called to translate an endpoint Base Address Register bus-centric address
* into Physical address.
*
* When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
* via the Base Address Registers from I/O or Memory types.
*
* The bus-centric address set in this BAR register is not necessarily accessible from the CPU,
* thus must be translated by using the PCI Express Controller memory regions translation
* ranges to permit mapping from the CPU.
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param mem True if the BAR is of memory type
* @param mem64 True if the BAR is of 64bit memory type
* @param bar_bus_addr bus-centric address written in the BAR register
* @param bar_addr CPU-centric address translated from the bus-centric address
* @return True if translation was possible, False if translation failed
*/
typedef bool (*pcie_ctrl_region_translate_t)(const struct device *dev, pcie_bdf_t bdf,
bool mem, bool mem64, uintptr_t bar_bus_addr,
uintptr_t *bar_addr);
#ifdef CONFIG_PCIE_MSI
typedef uint8_t (*pcie_ctrl_msi_device_setup_t)(const struct device *dev, unsigned int priority,
msi_vector_t *vectors, uint8_t n_vector);
#endif
/**
* @brief Read a 32-bit word from a Memory-Mapped endpoint's configuration space.
*
* Read a 32-bit word from an endpoint's configuration space from a Memory-Mapped
* configuration space access method, known as PCI Control Access Method (CAM) or
* PCIe Extended Control Access Method (ECAM).
*
* @param cfg_addr Logical address of Memory-Mapped configuration space
* @param bdf PCI(e) endpoint
* @param reg the configuration word index (not address)
* @return the word read (0xFFFFFFFFU if nonexistent endpoint or word)
*/
uint32_t pcie_generic_ctrl_conf_read(mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg);
/**
* @brief Write a 32-bit word to a Memory-Mapped endpoint's configuration space.
*
* Write a 32-bit word to an endpoint's configuration space from a Memory-Mapped
* configuration space access method, known as PCI Control Access Method (CAM) or
* PCIe Extended Control Access Method (ECAM).
*
* @param cfg_addr Logical address of Memory-Mapped configuration space
* @param bdf PCI(e) endpoint
* @param reg the configuration word index (not address)
* @param data the value to write
*/
void pcie_generic_ctrl_conf_write(mm_reg_t cfg_addr, pcie_bdf_t bdf,
unsigned int reg, uint32_t data);
/**
* @brief Start PCIe Endpoints enumeration.
*
* Start a PCIe Endpoints enumeration from a Bus number.
* When on non-x86 architecture or when firmware didn't setup the PCIe Bus hierarchy,
* the PCIe bus complex must be enumerated to setup the Endpoints Base Address Registers.
*
* @param dev PCI Express Controller device pointer
* @param bdf_start PCI(e) start endpoint (only bus & dev are used to start enumeration)
*/
void pcie_generic_ctrl_enumerate(const struct device *dev, pcie_bdf_t bdf_start);
/** @brief Structure providing callbacks to be implemented for devices
* that supports the PCI Express Controller API
*/
__subsystem struct pcie_ctrl_driver_api {
pcie_ctrl_conf_read_t conf_read;
pcie_ctrl_conf_write_t conf_write;
pcie_ctrl_region_allocate_t region_allocate;
pcie_ctrl_region_get_allocate_base_t region_get_allocate_base;
pcie_ctrl_region_translate_t region_translate;
#ifdef CONFIG_PCIE_MSI
pcie_ctrl_msi_device_setup_t msi_device_setup;
#endif
};
/**
* @brief Read a 32-bit word from an endpoint's configuration space.
*
* Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
* configuration space access method (I/O port, memory mapped or custom method)
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param reg the configuration word index (not address)
* @return the word read (0xFFFFFFFFU if nonexistent endpoint or word)
*/
static inline uint32_t pcie_ctrl_conf_read(const struct device *dev, pcie_bdf_t bdf,
unsigned int reg)
{
const struct pcie_ctrl_driver_api *api =
(const struct pcie_ctrl_driver_api *)dev->api;
return api->conf_read(dev, bdf, reg);
}
/**
* @brief Write a 32-bit word to an endpoint's configuration space.
*
* Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
* configuration space access method (I/O port, memory mapped or custom method)
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param reg the configuration word index (not address)
* @param data the value to write
*/
static inline void pcie_ctrl_conf_write(const struct device *dev, pcie_bdf_t bdf,
unsigned int reg, uint32_t data)
{
const struct pcie_ctrl_driver_api *api =
(const struct pcie_ctrl_driver_api *)dev->api;
api->conf_write(dev, bdf, reg, data);
}
/**
* @brief Allocate a memory region subset for an endpoint Base Address Register.
*
* When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
* via the Base Address Registers from I/O or Memory types.
*
* This call allocates such zone in the PCI Express Controller memory regions if
* such region is available and space is still available.
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param mem True if the BAR is of memory type
* @param mem64 True if the BAR is of 64bit memory type
* @param bar_size Size in bytes of the Base Address Register as returned by HW
* @param bar_bus_addr bus-centric address allocated to be written in the BAR register
* @return True if allocation was possible, False if allocation failed
*/
static inline bool pcie_ctrl_region_allocate(const struct device *dev, pcie_bdf_t bdf,
bool mem, bool mem64, size_t bar_size,
uintptr_t *bar_bus_addr)
{
const struct pcie_ctrl_driver_api *api =
(const struct pcie_ctrl_driver_api *)dev->api;
return api->region_allocate(dev, bdf, mem, mem64, bar_size, bar_bus_addr);
}
/**
* @brief Function called to get the current allocation base of a memory region subset
* for an endpoint Base Address Register.
*
* When enumerating PCIe Endpoints, Type1 bridge endpoints requires a range of memory
* allocated by all endpoints in the bridged bus.
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param mem True if the BAR is of memory type
* @param mem64 True if the BAR is of 64bit memory type
* @param align size to take in account for alignment
* @param bar_base_addr bus-centric address allocation base
* @return True if allocation was possible, False if allocation failed
*/
static inline bool pcie_ctrl_region_get_allocate_base(const struct device *dev, pcie_bdf_t bdf,
bool mem, bool mem64, size_t align,
uintptr_t *bar_base_addr)
{
const struct pcie_ctrl_driver_api *api =
(const struct pcie_ctrl_driver_api *)dev->api;
return api->region_get_allocate_base(dev, bdf, mem, mem64, align, bar_base_addr);
}
/**
* @brief Translate an endpoint Base Address Register bus-centric address into Physical address.
*
* When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
* via the Base Address Registers from I/O or Memory types.
*
* The bus-centric address set in this BAR register is not necessarily accessible from the CPU,
* thus must be translated by using the PCI Express Controller memory regions translation
* ranges to permit mapping from the CPU.
*
* @param dev PCI Express Controller device pointer
* @param bdf PCI(e) endpoint
* @param mem True if the BAR is of memory type
* @param mem64 True if the BAR is of 64bit memory type
* @param bar_bus_addr bus-centric address written in the BAR register
* @param bar_addr CPU-centric address translated from the bus-centric address
* @return True if translation was possible, False if translation failed
*/
static inline bool pcie_ctrl_region_translate(const struct device *dev, pcie_bdf_t bdf,
bool mem, bool mem64, uintptr_t bar_bus_addr,
uintptr_t *bar_addr)
{
const struct pcie_ctrl_driver_api *api =
(const struct pcie_ctrl_driver_api *)dev->api;
if (!api->region_translate) {
*bar_addr = bar_bus_addr;
return true;
} else {
return api->region_translate(dev, bdf, mem, mem64, bar_bus_addr, bar_addr);
}
}
#ifdef CONFIG_PCIE_MSI
static inline uint8_t pcie_ctrl_msi_device_setup(const struct device *dev, unsigned int priority,
msi_vector_t *vectors, uint8_t n_vector)
{
const struct pcie_ctrl_driver_api *api =
(const struct pcie_ctrl_driver_api *)dev->api;
return api->msi_device_setup(dev, priority, vectors, n_vector);
}
#endif
/** @brief Structure describing a device that supports the PCI Express Controller API
*/
struct pcie_ctrl_config {
#ifdef CONFIG_PCIE_MSI
const struct device *msi_parent;
#endif
/* Configuration space physical address */
uintptr_t cfg_addr;
/* Configuration space physical size */
size_t cfg_size;
/* BAR regions translation ranges count */
size_t ranges_count;
/* BAR regions translation ranges table */
struct {
/* Flags as defined in the PCI Bus Binding to IEEE Std 1275-1994 */
uint32_t flags;
/* bus-centric offset from the start of the region */
uintptr_t pcie_bus_addr;
/* CPU-centric offset from the start of the region */
uintptr_t host_map_addr;
/* region size */
size_t map_length;
} ranges[];
};
/*
* Fills the pcie_ctrl_config.ranges table from DT
*/
#define PCIE_RANGE_FORMAT(node_id, idx) \
{ \
.flags = DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx), \
.pcie_bus_addr = DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(node_id, idx), \
.host_map_addr = DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(node_id, idx), \
.map_length = DT_RANGES_LENGTH_BY_IDX(node_id, idx), \
},
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/pcie/controller.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,177 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_PTM_H_
#define ZEPHYR_INCLUDE_DRIVERS_PCIE_PTM_H_
/**
* @brief PCIe Host PTM Interface
* @defgroup pcie_host_ptm_interface PCIe Host PTM Interface
* @ingroup pcie_host_interface
* @{
*/
#include <stddef.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable PTM on endpoint
*
* @param bdf the PCI(e) endpoint
* @return true if that was successful, false otherwise
*/
bool pcie_ptm_enable(pcie_bdf_t bdf);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_PTM_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/pcie/ptm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 166 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_MSI_H_
#define ZEPHYR_INCLUDE_DRIVERS_PCIE_MSI_H_
/**
* @brief PCIe Host MSI Interface
* @defgroup pcie_host_msi_interface PCIe Host MSI Interface
* @ingroup pcie_host_interface
* @{
*/
#include <zephyr/kernel.h>
#include <zephyr/types.h>
#include <stdbool.h>
#include <zephyr/drivers/pcie/pcie.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_PCIE_CONTROLLER
struct msi_vector_generic {
unsigned int irq;
uint32_t address;
uint16_t eventid;
unsigned int priority;
};
typedef struct msi_vector_generic arch_msi_vector_t;
#define PCI_DEVID(bus, dev, fn) ((((bus) & 0xff) << 8) | (((dev) & 0x1f) << 3) | ((fn) & 0x07))
#define PCI_BDF_TO_DEVID(bdf) PCI_DEVID(PCIE_BDF_TO_BUS(bdf), \
PCIE_BDF_TO_DEV(bdf), \
PCIE_BDF_TO_FUNC(bdf))
#endif
struct msix_vector {
uint32_t msg_addr;
uint32_t msg_up_addr;
uint32_t msg_data;
uint32_t vector_ctrl;
} __packed;
struct msi_vector {
pcie_bdf_t bdf;
arch_msi_vector_t arch;
#ifdef CONFIG_PCIE_MSI_X
struct msix_vector *msix_vector;
bool msix;
#endif /* CONFIG_PCIE_MSI_X */
};
typedef struct msi_vector msi_vector_t;
#ifdef CONFIG_PCIE_MSI_MULTI_VECTOR
/**
* @brief Allocate vector(s) for the endpoint MSI message(s)
*
* @param bdf the target PCI endpoint
* @param priority the MSI vectors base interrupt priority
* @param vectors an array for storing allocated MSI vectors
* @param n_vector the size of the MSI vectors array
*
* @return the number of allocated MSI vectors.
*/
extern uint8_t pcie_msi_vectors_allocate(pcie_bdf_t bdf,
unsigned int priority,
msi_vector_t *vectors,
uint8_t n_vector);
/**
* @brief Connect the MSI vector to the handler
*
* @param bdf the target PCI endpoint
* @param vector the MSI vector to connect
* @param routine Interrupt service routine
* @param parameter ISR parameter
* @param flags Arch-specific IRQ configuration flag
*
* @return True on success, false otherwise
*/
extern bool pcie_msi_vector_connect(pcie_bdf_t bdf,
msi_vector_t *vector,
void (*routine)(const void *parameter),
const void *parameter,
uint32_t flags);
#endif /* CONFIG_PCIE_MSI_MULTI_VECTOR */
/**
* @brief Compute the target address for an MSI posted write.
*
* This function is exported by the arch, board or SoC code.
*
* @param irq The IRQ we wish to trigger via MSI.
* @param vector The vector for which you want the address (or NULL)
* @param n_vector the size of the vector array
* @return A (32-bit) value for the MSI MAP register.
*/
extern uint32_t pcie_msi_map(unsigned int irq,
msi_vector_t *vector,
uint8_t n_vector);
/**
* @brief Compute the data for an MSI posted write.
*
* This function is exported by the arch, board or SoC code.
*
* @param irq The IRQ we wish to trigger via MSI.
* @param vector The vector for which you want the data (or NULL)
* @return A (16-bit) value for MSI MDR register.
*/
extern uint16_t pcie_msi_mdr(unsigned int irq,
msi_vector_t *vector);
/**
* @brief Configure the given PCI endpoint to generate MSIs.
*
* @param bdf the target PCI endpoint
* @param vectors an array of allocated vector(s)
* @param n_vector the size of the vector array
* @param irq The IRQ we wish to trigger via MSI.
* @return true if the endpoint supports MSI, false otherwise.
*/
extern bool pcie_msi_enable(pcie_bdf_t bdf,
msi_vector_t *vectors,
uint8_t n_vector,
unsigned int irq);
/**
* @brief Check if the given PCI endpoint supports MSI/MSI-X
*
* @param bdf the target PCI endpoint
* @return true if the endpoint support MSI/MSI-X
*/
extern bool pcie_is_msi(pcie_bdf_t bdf);
/*
* The first word of the MSI capability is shared with the
* capability ID and list link. The high 16 bits are the MCR.
*/
#define PCIE_MSI_MCR 0U
#define PCIE_MSI_MCR_EN 0x00010000U /* enable MSI */
#define PCIE_MSI_MCR_MMC 0x000E0000U /* Multi Messages Capable mask */
#define PCIE_MSI_MCR_MMC_SHIFT 17
#define PCIE_MSI_MCR_MME 0x00700000U /* mask of # of enabled IRQs */
#define PCIE_MSI_MCR_MME_SHIFT 20
#define PCIE_MSI_MCR_64 0x00800000U /* 64-bit MSI */
/*
* The MAP follows the MCR. If PCIE_MSI_MCR_64, then the MAP
* is two words long. The MDR follows immediately after the MAP.
*/
#define PCIE_MSI_MAP0 1U
#define PCIE_MSI_MAP1_64 2U
#define PCIE_MSI_MDR_32 2U
#define PCIE_MSI_MDR_64 3U
/*
* As for MSI, he first word of the MSI-X capability is shared
* with the capability ID and list link. The high 16 bits are the MCR.
*/
#define PCIE_MSIX_MCR 0U
#define PCIE_MSIX_MCR_EN 0x80000000U /* Enable MSI-X */
#define PCIE_MSIX_MCR_FMASK 0x40000000U /* Function Mask */
#define PCIE_MSIX_MCR_TSIZE 0x07FF0000U /* Table size mask */
#define PCIE_MSIX_MCR_TSIZE_SHIFT 16
#define PCIE_MSIR_TABLE_ENTRY_SIZE 16
#define PCIE_MSIX_TR 1U
#define PCIE_MSIX_TR_BIR 0x00000007U /* Table BIR mask */
#define PCIE_MSIX_TR_OFFSET 0xFFFFFFF8U /* Offset mask */
#define PCIE_MSIX_PBA 2U
#define PCIE_MSIX_PBA_BIR 0x00000007U /* PBA BIR mask */
#define PCIE_MSIX_PBA_OFFSET 0xFFFFFFF8U /* Offset mask */
#define PCIE_VTBL_MA 0U /* Msg Address offset */
#define PCIE_VTBL_MUA 4U /* Msg Upper Address offset */
#define PCIE_VTBL_MD 8U /* Msg Data offset */
#define PCIE_VTBL_VCTRL 12U /* Vector control offset */
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_MSI_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/pcie/msi.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,569 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_
#define ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_
/**
* @brief PCIe Host Interface
* @defgroup pcie_host_interface PCIe Host Interface
* @ingroup io_interfaces
* @{
*/
#include <stddef.h>
#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/pcie/pcie.h>
#include <zephyr/types.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/iterable_sections.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @typedef pcie_bdf_t
* @brief A unique PCI(e) endpoint (bus, device, function).
*
* A PCI(e) endpoint is uniquely identified topologically using a
* (bus, device, function) tuple. The internal structure is documented
* in include/dt-bindings/pcie/pcie.h: see PCIE_BDF() and friends, since
* these tuples are referenced from devicetree.
*/
typedef uint32_t pcie_bdf_t;
/**
* @typedef pcie_id_t
* @brief A unique PCI(e) identifier (vendor ID, device ID).
*
* The PCIE_CONF_ID register for each endpoint is a (vendor ID, device ID)
* pair, which is meant to tell the system what the PCI(e) endpoint is. Again,
* look to PCIE_ID_* macros in include/dt-bindings/pcie/pcie.h for more.
*/
typedef uint32_t pcie_id_t;
/* Helper macro to exclude invalid PCIe identifiers. We should really only
* need to look for PCIE_ID_NONE, but because of some broken PCI host controllers
* we have try cases where both VID & DID are zero or just one of them is
* zero (0x0000) and the other is all ones (0xFFFF).
*/
#define PCIE_ID_IS_VALID(id) ((id != PCIE_ID_NONE) && \
(id != PCIE_ID(0x0000, 0x0000)) && \
(id != PCIE_ID(0xFFFF, 0x0000)) && \
(id != PCIE_ID(0x0000, 0xFFFF)))
struct pcie_dev {
pcie_bdf_t bdf;
pcie_id_t id;
uint32_t class_rev;
uint32_t class_rev_mask;
};
#define Z_DEVICE_PCIE_NAME(node_id) _CONCAT(pcie_dev_, DT_DEP_ORD(node_id))
/**
* @brief Get the PCIe Vendor and Device ID for a node
*
* @param node_id DTS node identifier
* @return The VID/DID combination as pcie_id_t
*/
#define PCIE_DT_ID(node_id) PCIE_ID(DT_PROP_OR(node_id, vendor_id, 0xffff), \
DT_PROP_OR(node_id, device_id, 0xffff))
/**
* @brief Get the PCIe Vendor and Device ID for a node
*
* This is equivalent to
* <tt>PCIE_DT_ID(DT_DRV_INST(inst))</tt>
*
* @param inst Devicetree instance number
* @return The VID/DID combination as pcie_id_t
*/
#define PCIE_DT_INST_ID(inst) PCIE_DT_ID(DT_DRV_INST(inst))
/**
* @brief Declare a PCIe context variable for a DTS node
*
* Declares a PCIe context for a DTS node. This must be done before
* using the DEVICE_PCIE_INIT() macro for the same node.
*
* @param node_id DTS node identifier
*/
#define DEVICE_PCIE_DECLARE(node_id) \
STRUCT_SECTION_ITERABLE(pcie_dev, Z_DEVICE_PCIE_NAME(node_id)) = { \
.bdf = PCIE_BDF_NONE, \
.id = PCIE_DT_ID(node_id), \
.class_rev = DT_PROP_OR(node_id, class_rev, 0), \
.class_rev_mask = DT_PROP_OR(node_id, class_rev_mask, 0), \
}
/**
* @brief Declare a PCIe context variable for a DTS node
*
* This is equivalent to
* <tt>DEVICE_PCIE_DECLARE(DT_DRV_INST(inst))</tt>
*
* @param inst Devicetree instance number
*/
#define DEVICE_PCIE_INST_DECLARE(inst) DEVICE_PCIE_DECLARE(DT_DRV_INST(inst))
/**
* @brief Initialize a named struct member to point at a PCIe context
*
* Initialize PCIe-related information within a specific instance of
* a device config struct, using information from DTS. Using the macro
* requires having first created PCIe context struct using the
* DEVICE_PCIE_DECLARE() macro.
*
* Example for an instance of a driver belonging to the "foo" subsystem
*
* struct foo_config {
* struct pcie_dev *pcie;
* ...
*};
*
* DEVICE_PCIE_ID_DECLARE(DT_DRV_INST(...));
* struct foo_config my_config = {
DEVICE_PCIE_INIT(pcie, DT_DRV_INST(...)),
* ...
* };
*
* @param node_id DTS node identifier
* @param name Member name within config for the MMIO region
*/
#define DEVICE_PCIE_INIT(node_id, name) .name = &Z_DEVICE_PCIE_NAME(node_id)
/**
* @brief Initialize a named struct member to point at a PCIe context
*
* This is equivalent to
* <tt>DEVICE_PCIE_INIT(DT_DRV_INST(inst), name)</tt>
*
* @param inst Devicetree instance number
* @param name Name of the struct member (of type struct pcie_dev *)
*/
#define DEVICE_PCIE_INST_INIT(inst, name) \
DEVICE_PCIE_INIT(DT_DRV_INST(inst), name)
struct pcie_bar {
uintptr_t phys_addr;
size_t size;
};
/*
* These functions are arch-, board-, or SoC-specific.
*/
/**
* @brief Read a 32-bit word from an endpoint's configuration space.
*
* This function is exported by the arch/SoC/board code.
*
* @param bdf PCI(e) endpoint
* @param reg the configuration word index (not address)
* @return the word read (0xFFFFFFFFU if nonexistent endpoint or word)
*/
extern uint32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg);
/**
* @brief Write a 32-bit word to an endpoint's configuration space.
*
* This function is exported by the arch/SoC/board code.
*
* @param bdf PCI(e) endpoint
* @param reg the configuration word index (not address)
* @param data the value to write
*/
extern void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data);
/** Callback type used for scanning for PCI endpoints
*
* @param bdf BDF value for a found endpoint.
* @param id Vendor & Device ID for the found endpoint.
* @param cb_data Custom, use case specific data.
*
* @return true to continue scanning, false to stop scanning.
*/
typedef bool (*pcie_scan_cb_t)(pcie_bdf_t bdf, pcie_id_t id, void *cb_data);
enum {
/** Scan all available PCI host controllers and sub-busses */
PCIE_SCAN_RECURSIVE = BIT(0),
/** Do the callback for all endpoint types, including bridges */
PCIE_SCAN_CB_ALL = BIT(1),
};
/** Options for performing a scan for PCI devices */
struct pcie_scan_opt {
/** Initial bus number to scan */
uint8_t bus;
/** Function to call for each found endpoint */
pcie_scan_cb_t cb;
/** Custom data to pass to the scan callback */
void *cb_data;
/** Scan flags */
uint32_t flags;
};
/** Scan for PCIe devices.
*
* Scan the PCI bus (or buses) for available endpoints.
*
* @param opt Options determining how to perform the scan.
* @return 0 on success, negative POSIX error number on failure.
*/
int pcie_scan(const struct pcie_scan_opt *opt);
/**
* @brief Get the MBAR at a specific BAR index
* @param bdf the PCI(e) endpoint
* @param bar_index 0-based BAR index
* @param mbar Pointer to struct pcie_bar
* @return true if the mbar was found and is valid, false otherwise
*/
extern bool pcie_get_mbar(pcie_bdf_t bdf,
unsigned int bar_index,
struct pcie_bar *mbar);
/**
* @brief Probe the nth MMIO address assigned to an endpoint.
* @param bdf the PCI(e) endpoint
* @param index (0-based) index
* @param mbar Pointer to struct pcie_bar
* @return true if the mbar was found and is valid, false otherwise
*
* A PCI(e) endpoint has 0 or more memory-mapped regions. This function
* allows the caller to enumerate them by calling with index=0..n.
* Value of n has to be below 6, as there is a maximum of 6 BARs. The indices
* are order-preserving with respect to the endpoint BARs: e.g., index 0
* will return the lowest-numbered memory BAR on the endpoint.
*/
extern bool pcie_probe_mbar(pcie_bdf_t bdf,
unsigned int index,
struct pcie_bar *mbar);
/**
* @brief Get the I/O BAR at a specific BAR index
* @param bdf the PCI(e) endpoint
* @param bar_index 0-based BAR index
* @param iobar Pointer to struct pcie_bar
* @return true if the I/O BAR was found and is valid, false otherwise
*/
extern bool pcie_get_iobar(pcie_bdf_t bdf,
unsigned int bar_index,
struct pcie_bar *iobar);
/**
* @brief Probe the nth I/O BAR address assigned to an endpoint.
* @param bdf the PCI(e) endpoint
* @param index (0-based) index
* @param iobar Pointer to struct pcie_bar
* @return true if the I/O BAR was found and is valid, false otherwise
*
* A PCI(e) endpoint has 0 or more I/O regions. This function
* allows the caller to enumerate them by calling with index=0..n.
* Value of n has to be below 6, as there is a maximum of 6 BARs. The indices
* are order-preserving with respect to the endpoint BARs: e.g., index 0
* will return the lowest-numbered I/O BAR on the endpoint.
*/
extern bool pcie_probe_iobar(pcie_bdf_t bdf,
unsigned int index,
struct pcie_bar *iobar);
/**
* @brief Set or reset bits in the endpoint command/status register.
*
* @param bdf the PCI(e) endpoint
* @param bits the powerset of bits of interest
* @param on use true to set bits, false to reset them
*/
extern void pcie_set_cmd(pcie_bdf_t bdf, uint32_t bits, bool on);
#ifndef CONFIG_PCIE_CONTROLLER
/**
* @brief Allocate an IRQ for an endpoint.
*
* This function first checks the IRQ register and if it contains a valid
* value this is returned. If the register does not contain a valid value
* allocation of a new one is attempted.
* Such function is only exposed if CONFIG_PCIE_CONTROLLER is unset.
* It is thus available where architecture tied dynamic IRQ allocation for
* PCIe device makes sense.
*
* @param bdf the PCI(e) endpoint
* @return the IRQ number, or PCIE_CONF_INTR_IRQ_NONE if allocation failed.
*/
extern unsigned int pcie_alloc_irq(pcie_bdf_t bdf);
#endif /* CONFIG_PCIE_CONTROLLER */
/**
* @brief Return the IRQ assigned by the firmware/board to an endpoint.
*
* @param bdf the PCI(e) endpoint
* @return the IRQ number, or PCIE_CONF_INTR_IRQ_NONE if unknown.
*/
extern unsigned int pcie_get_irq(pcie_bdf_t bdf);
/**
* @brief Enable the PCI(e) endpoint to generate the specified IRQ.
*
* @param bdf the PCI(e) endpoint
* @param irq the IRQ to generate
*
* If MSI is enabled and the endpoint supports it, the endpoint will
* be configured to generate the specified IRQ via MSI. Otherwise, it
* is assumed that the IRQ has been routed by the boot firmware
* to the specified IRQ, and the IRQ is enabled (at the I/O APIC, or
* wherever appropriate).
*/
extern void pcie_irq_enable(pcie_bdf_t bdf, unsigned int irq);
/**
* @brief Find a PCI(e) capability in an endpoint's configuration space.
*
* @param bdf the PCI endpoint to examine
* @param cap_id the capability ID of interest
* @return the index of the configuration word, or 0 if no capability.
*/
extern uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id);
/**
* @brief Find an Extended PCI(e) capability in an endpoint's configuration space.
*
* @param bdf the PCI endpoint to examine
* @param cap_id the capability ID of interest
* @return the index of the configuration word, or 0 if no capability.
*/
extern uint32_t pcie_get_ext_cap(pcie_bdf_t bdf, uint32_t cap_id);
/**
* @brief Dynamically connect a PCIe endpoint IRQ to an ISR handler
*
* @param bdf the PCI endpoint to examine
* @param irq the IRQ to connect (see pcie_alloc_irq())
* @param priority priority of the IRQ
* @param routine the ISR handler to connect to the IRQ
* @param parameter the parameter to provide to the handler
* @param flags IRQ connection flags
* @return true if connected, false otherwise
*/
extern bool pcie_connect_dynamic_irq(pcie_bdf_t bdf,
unsigned int irq,
unsigned int priority,
void (*routine)(const void *parameter),
const void *parameter,
uint32_t flags);
/**
* @brief Get the BDF for a given PCI host controller
*
* This macro is useful when the PCI host controller behind PCIE_BDF(0, 0, 0)
* indicates a multifunction device. In such a case each function of this
* endpoint is a potential host controller itself.
*
* @param n Bus number
* @return BDF value of the given host controller
*/
#define PCIE_HOST_CONTROLLER(n) PCIE_BDF(0, 0, n)
/*
* Configuration word 13 contains the head of the capabilities list.
*/
#define PCIE_CONF_CAPPTR 13U /* capabilities pointer */
#define PCIE_CONF_CAPPTR_FIRST(w) (((w) >> 2) & 0x3FU)
/*
* The first word of every capability contains a capability identifier,
* and a link to the next capability (or 0) in configuration space.
*/
#define PCIE_CONF_CAP_ID(w) ((w) & 0xFFU)
#define PCIE_CONF_CAP_NEXT(w) (((w) >> 10) & 0x3FU)
/*
* The extended PCI Express capabilities lie at the end of the PCI configuration space
*/
#define PCIE_CONF_EXT_CAPPTR 64U
/*
* The first word of every capability contains an extended capability identifier,
* and a link to the next capability (or 0) in the extended configuration space.
*/
#define PCIE_CONF_EXT_CAP_ID(w) ((w) & 0xFFFFU)
#define PCIE_CONF_EXT_CAP_VER(w) (((w) >> 16) & 0xFU)
#define PCIE_CONF_EXT_CAP_NEXT(w) (((w) >> 20) & 0xFFFU)
/*
* Configuration word 0 aligns directly with pcie_id_t.
*/
#define PCIE_CONF_ID 0U
/*
* Configuration word 1 contains command and status bits.
*/
#define PCIE_CONF_CMDSTAT 1U /* command/status register */
#define PCIE_CONF_CMDSTAT_IO 0x00000001U /* I/O access enable */
#define PCIE_CONF_CMDSTAT_MEM 0x00000002U /* mem access enable */
#define PCIE_CONF_CMDSTAT_MASTER 0x00000004U /* bus master enable */
#define PCIE_CONF_CMDSTAT_INTERRUPT 0x00080000U /* interrupt status */
#define PCIE_CONF_CMDSTAT_CAPS 0x00100000U /* capabilities list */
/*
* Configuration word 2 has additional function identification that
* we only care about for debug output (PCIe shell commands).
*/
#define PCIE_CONF_CLASSREV 2U /* class/revision register */
#define PCIE_CONF_CLASSREV_CLASS(w) (((w) >> 24) & 0xFFU)
#define PCIE_CONF_CLASSREV_SUBCLASS(w) (((w) >> 16) & 0xFFU)
#define PCIE_CONF_CLASSREV_PROGIF(w) (((w) >> 8) & 0xFFU)
#define PCIE_CONF_CLASSREV_REV(w) ((w) & 0xFFU)
/*
* The only part of configuration word 3 that is of interest to us is
* the header type, as we use it to distinguish functional endpoints
* from bridges (which are, for our purposes, transparent).
*/
#define PCIE_CONF_TYPE 3U
#define PCIE_CONF_MULTIFUNCTION(w) (((w) & 0x00800000U) != 0U)
#define PCIE_CONF_TYPE_BRIDGE(w) (((w) & 0x007F0000U) != 0U)
#define PCIE_CONF_TYPE_GET(w) (((w) >> 16) & 0x7F)
#define PCIE_CONF_TYPE_STANDARD 0x0U
#define PCIE_CONF_TYPE_PCI_BRIDGE 0x1U
#define PCIE_CONF_TYPE_CARDBUS_BRIDGE 0x2U
/*
* Words 4-9 are BARs are I/O or memory decoders. Memory decoders may
* be 64-bit decoders, in which case the next configuration word holds
* the high-order bits (and is, thus, not a BAR itself).
*/
#define PCIE_CONF_BAR0 4U
#define PCIE_CONF_BAR1 5U
#define PCIE_CONF_BAR2 6U
#define PCIE_CONF_BAR3 7U
#define PCIE_CONF_BAR4 8U
#define PCIE_CONF_BAR5 9U
#define PCIE_CONF_BAR_IO(w) (((w) & 0x00000001U) == 0x00000001U)
#define PCIE_CONF_BAR_MEM(w) (((w) & 0x00000001U) != 0x00000001U)
#define PCIE_CONF_BAR_64(w) (((w) & 0x00000006U) == 0x00000004U)
#define PCIE_CONF_BAR_ADDR(w) ((w) & ~0xfUL)
#define PCIE_CONF_BAR_IO_ADDR(w) ((w) & ~0x3UL)
#define PCIE_CONF_BAR_FLAGS(w) ((w) & 0xfUL)
#define PCIE_CONF_BAR_NONE 0U
#define PCIE_CONF_BAR_INVAL 0xFFFFFFF0U
#define PCIE_CONF_BAR_INVAL64 0xFFFFFFFFFFFFFFF0UL
#define PCIE_CONF_BAR_INVAL_FLAGS(w) \
((((w) & 0x00000006U) == 0x00000006U) || \
(((w) & 0x00000006U) == 0x00000002U))
/*
* Type 1 Header has files related to bus management
*/
#define PCIE_BUS_NUMBER 6U
#define PCIE_BUS_PRIMARY_NUMBER(w) ((w) & 0xffUL)
#define PCIE_BUS_SECONDARY_NUMBER(w) (((w) >> 8) & 0xffUL)
#define PCIE_BUS_SUBORDINATE_NUMBER(w) (((w) >> 16) & 0xffUL)
#define PCIE_SECONDARY_LATENCY_TIMER(w) (((w) >> 24) & 0xffUL)
#define PCIE_BUS_NUMBER_VAL(prim, sec, sub, lat) \
(((prim) & 0xffUL) | \
(((sec) & 0xffUL) << 8) | \
(((sub) & 0xffUL) << 16) | \
(((lat) & 0xffUL) << 24))
/*
* Type 1 words 7 to 12 setups Bridge Memory base and limits
*/
#define PCIE_IO_SEC_STATUS 7U
#define PCIE_IO_BASE(w) ((w) & 0xffUL)
#define PCIE_IO_LIMIT(w) (((w) >> 8) & 0xffUL)
#define PCIE_SEC_STATUS(w) (((w) >> 16) & 0xffffUL)
#define PCIE_IO_SEC_STATUS_VAL(iob, iol, sec_status) \
(((iob) & 0xffUL) | \
(((iol) & 0xffUL) << 8) | \
(((sec_status) & 0xffffUL) << 16))
#define PCIE_MEM_BASE_LIMIT 8U
#define PCIE_MEM_BASE(w) ((w) & 0xffffUL)
#define PCIE_MEM_LIMIT(w) (((w) >> 16) & 0xffffUL)
#define PCIE_MEM_BASE_LIMIT_VAL(memb, meml) \
(((memb) & 0xffffUL) | \
(((meml) & 0xffffUL) << 16))
#define PCIE_PREFETCH_BASE_LIMIT 9U
#define PCIE_PREFETCH_BASE(w) ((w) & 0xffffUL)
#define PCIE_PREFETCH_LIMIT(w) (((w) >> 16) & 0xffffUL)
#define PCIE_PREFETCH_BASE_LIMIT_VAL(pmemb, pmeml) \
(((pmemb) & 0xffffUL) | \
(((pmeml) & 0xffffUL) << 16))
#define PCIE_PREFETCH_BASE_UPPER 10U
#define PCIE_PREFETCH_LIMIT_UPPER 11U
#define PCIE_IO_BASE_LIMIT_UPPER 12U
#define PCIE_IO_BASE_UPPER(w) ((w) & 0xffffUL)
#define PCIE_IO_LIMIT_UPPER(w) (((w) >> 16) & 0xffffUL)
#define PCIE_IO_BASE_LIMIT_UPPER_VAL(iobu, iolu) \
(((iobu) & 0xffffUL) | \
(((iolu) & 0xffffUL) << 16))
/*
* Word 15 contains information related to interrupts.
*
* We're only interested in the low byte, which is [supposed to be] set by
* the firmware to indicate which wire IRQ the device interrupt is routed to.
*/
#define PCIE_CONF_INTR 15U
#define PCIE_CONF_INTR_IRQ(w) ((w) & 0xFFU)
#define PCIE_CONF_INTR_IRQ_NONE 0xFFU /* no interrupt routed */
#define PCIE_MAX_BUS (0xFFFFFFFFU & PCIE_BDF_BUS_MASK)
#define PCIE_MAX_DEV (0xFFFFFFFFU & PCIE_BDF_DEV_MASK)
#define PCIE_MAX_FUNC (0xFFFFFFFFU & PCIE_BDF_FUNC_MASK)
/**
* @brief Initialize an interrupt handler for a PCIe endpoint IRQ
*
* This routine is only meant to be used by drivers using PCIe bus and having
* fixed or MSI based IRQ (so no runtime detection of the IRQ). In case
* of runtime detection see pcie_connect_dynamic_irq()
*
* @param bdf_p PCIe endpoint BDF
* @param irq_p IRQ line number.
* @param priority_p Interrupt priority.
* @param isr_p Address of interrupt service routine.
* @param isr_param_p Parameter passed to interrupt service routine.
* @param flags_p Architecture-specific IRQ configuration flags..
*/
#define PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, \
isr_p, isr_param_p, flags_p) \
ARCH_PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, \
isr_p, isr_param_p, flags_p)
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/pcie/pcie.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,203 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_CAP_H_
#define ZEPHYR_INCLUDE_DRIVERS_PCIE_CAP_H_
/**
* @file
* @brief PCIe Capabilities
* @defgroup pcie_capabilities PCIe Capabilities
* @ingroup pcie_host_interface
* @{
*/
/**
* @name PCI & PCI Express Capabilities
*
* From PCI Code and ID Assignment Specification Revision 1.11
* @{
*/
#define PCI_CAP_ID_NULL 0x00U /**< Null Capability */
#define PCI_CAP_ID_PM 0x01U /**< Power Management */
#define PCI_CAP_ID_AGP 0x02U /**< Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03U /**< Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04U /**< Slot Identification */
#define PCI_CAP_ID_MSI 0x05U /**< Message Signalled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06U /**< CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07U /**< PCI-X */
#define PCI_CAP_ID_HT 0x08U /**< HyperTransport */
#define PCI_CAP_ID_VNDR 0x09U /**< Vendor-Specific */
#define PCI_CAP_ID_DBG 0x0AU /**< Debug port */
#define PCI_CAP_ID_CCRC 0x0BU /**< CompactPCI Central Resource Control */
#define PCI_CAP_ID_SHPC 0x0CU /**< PCI Standard Hot-Plug Controller */
#define PCI_CAP_ID_SSVID 0x0DU /**< Bridge subsystem vendor/device ID */
#define PCI_CAP_ID_AGP3 0x0EU /**< AGP 8x */
#define PCI_CAP_ID_SECDEV 0x0FU /**< Secure Device */
#define PCI_CAP_ID_EXP 0x10U /**< PCI Express */
#define PCI_CAP_ID_MSIX 0x11U /**< MSI-X */
#define PCI_CAP_ID_SATA 0x12U /**< Serial ATA Data/Index Configuration */
#define PCI_CAP_ID_AF 0x13U /**< PCI Advanced Features */
#define PCI_CAP_ID_EA 0x14U /**< PCI Enhanced Allocation */
#define PCI_CAP_ID_FPB 0x14U /**< Flattening Portal Bridge */
/**
* @}
*/
/**
* @name PCI Express Extended Capabilities
* @{
*/
#define PCIE_EXT_CAP_ID_NULL 0x0000U /**< Null Capability */
#define PCIE_EXT_CAP_ID_ERR 0x0001U /**< Advanced Error Reporting */
#define PCIE_EXT_CAP_ID_VC 0x0002U /**< Virtual Channel when no MFVC */
#define PCIE_EXT_CAP_ID_DSN 0x0003U /**< Device Serial Number */
#define PCIE_EXT_CAP_ID_PWR 0x0004U /**< Power Budgeting */
#define PCIE_EXT_CAP_ID_RCLD 0x0005U /**< Root Complex Link Declaration */
#define PCIE_EXT_CAP_ID_RCILC 0x0006U /**< Root Complex Internal Link Control */
#define PCIE_EXT_CAP_ID_RCEC 0x0007U /**< Root Complex Event Collector Endpoint Association */
#define PCIE_EXT_CAP_ID_MFVC 0x0008U /**< Multi-Function VC Capability */
#define PCIE_EXT_CAP_ID_MFVC_VC 0x0009U /**< Virtual Channel used with MFVC */
#define PCIE_EXT_CAP_ID_RCRB 0x000AU /**< Root Complex Register Block */
#define PCIE_EXT_CAP_ID_VNDR 0x000BU /**< Vendor-Specific Extended Capability */
#define PCIE_EXT_CAP_ID_CAC 0x000CU /**< Config Access Correlation - obsolete */
#define PCIE_EXT_CAP_ID_ACS 0x000DU /**< Access Control Services */
#define PCIE_EXT_CAP_ID_ARI 0x000EU /**< Alternate Routing-ID Interpretation */
#define PCIE_EXT_CAP_ID_ATS 0x000FU /**< Address Translation Services */
#define PCIE_EXT_CAP_ID_SRIOV 0x0010U /**< Single Root I/O Virtualization */
#define PCIE_EXT_CAP_ID_MRIOV 0x0011U /**< Multi Root I/O Virtualization */
#define PCIE_EXT_CAP_ID_MCAST 0x0012U /**< Multicast */
#define PCIE_EXT_CAP_ID_PRI 0x0013U /**< Page Request Interface */
#define PCIE_EXT_CAP_ID_AMD_XXX 0x0014U /**< Reserved for AMD */
#define PCIE_EXT_CAP_ID_REBAR 0x0015U /**< Resizable BAR */
#define PCIE_EXT_CAP_ID_DPA 0x0016U /**< Dynamic Power Allocation */
#define PCIE_EXT_CAP_ID_TPH 0x0017U /**< TPH Requester */
#define PCIE_EXT_CAP_ID_LTR 0x0018U /**< Latency Tolerance Reporting */
#define PCIE_EXT_CAP_ID_SECPCI 0x0019U /**< Secondary PCIe Capability */
#define PCIE_EXT_CAP_ID_PMUX 0x001AU /**< Protocol Multiplexing */
#define PCIE_EXT_CAP_ID_PASID 0x001BU /**< Process Address Space ID */
#define PCIE_EXT_CAP_ID_DPC 0x001DU /**< DPC: Downstream Port Containment */
#define PCIE_EXT_CAP_ID_L1SS 0x001EU /**< L1 PM Substates */
#define PCIE_EXT_CAP_ID_PTM 0x001FU /**< Precision Time Measurement */
#define PCIE_EXT_CAP_ID_DVSEC 0x0023U /**< Designated Vendor-Specific Extended Capability */
#define PCIE_EXT_CAP_ID_DLF 0x0025U /**< Data Link Feature */
#define PCIE_EXT_CAP_ID_PL_16GT 0x0026U /**< Physical Layer 16.0 GT/s */
#define PCIE_EXT_CAP_ID_LMR 0x0027U /**< Lane Margining at the Receiver */
#define PCIE_EXT_CAP_ID_HID 0x0028U /**< Hierarchy ID */
#define PCIE_EXT_CAP_ID_NPEM 0x0029U /**< Native PCIe Enclosure Management */
#define PCIE_EXT_CAP_ID_PL_32GT 0x002AU /**< Physical Layer 32.0 GT/s */
#define PCIE_EXT_CAP_ID_AP 0x002BU /**< Alternate Protocol */
#define PCIE_EXT_CAP_ID_SFI 0x002CU /**< System Firmware Intermediary */
/**
* @}
*/
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_CAP_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/pcie/cap.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,386 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MODEM_SIMCOM_SIM7080_H
#define ZEPHYR_INCLUDE_DRIVERS_MODEM_SIMCOM_SIM7080_H
#include <zephyr/types.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define SIM7080_GNSS_DATA_UTC_LEN 20
#define SIM7080_SMS_MAX_LEN 160
struct sim7080_gnss_data {
/**
* Whether gnss is powered or not.
*/
bool run_status;
/**
* Whether fix is acquired or not.
*/
bool fix_status;
/**
* UTC in format yyyyMMddhhmmss.sss
*/
char utc[SIM7080_GNSS_DATA_UTC_LEN];
/**
* Latitude in 10^-7 degree.
*/
int32_t lat;
/**
* Longitude in 10^-7 degree.
*/
int32_t lon;
/**
* Altitude in mm.
*/
int32_t alt;
/**
* Horizontal dilution of precision in 10^-2.
*/
uint16_t hdop;
/**
* Course over ground un 10^-2 degree.
*/
uint16_t cog;
/**
* Speed in 10^-1 km/h.
*/
uint16_t kmh;
};
/**
* Possible sms states in memory.
*/
enum sim7080_sms_stat {
SIM7080_SMS_STAT_REC_UNREAD = 0,
SIM7080_SMS_STAT_REC_READ,
SIM7080_SMS_STAT_STO_UNSENT,
SIM7080_SMS_STAT_STO_SENT,
SIM7080_SMS_STAT_ALL,
};
/**
* Possible ftp return codes.
*/
enum sim7080_ftp_rc {
/* Operation finished correctly. */
SIM7080_FTP_RC_OK = 0,
/* Session finished. */
SIM7080_FTP_RC_FINISHED,
/* An error occurred. */
SIM7080_FTP_RC_ERROR,
};
/**
* Buffer structure for sms.
*/
struct sim7080_sms {
/* First octet of the sms. */
uint8_t first_octet;
/* Message protocol identifier. */
uint8_t tp_pid;
/* Status of the sms in memory. */
enum sim7080_sms_stat stat;
/* Index of the sms in memory. */
uint16_t index;
/* Time the sms was received. */
struct {
uint8_t year;
uint8_t month;
uint8_t day;
uint8_t hour;
uint8_t minute;
uint8_t second;
uint8_t timezone;
} time;
/* Buffered sms. */
char data[SIM7080_SMS_MAX_LEN + 1];
/* Length of the sms in buffer. */
uint8_t data_len;
};
/**
* Buffer structure for sms reads.
*/
struct sim7080_sms_buffer {
/* sms structures to read to. */
struct sim7080_sms *sms;
/* Number of sms structures. */
uint8_t nsms;
};
/**
* @brief Power on the Sim7080.
*
* @return 0 on success. Otherwise -1 is returned.
*/
int mdm_sim7080_power_on(void);
/**
* @brief Power off the Sim7080.
*
* @return 0 on success. Otherwise -1 is returned.
*/
int mdm_sim7080_power_off(void);
/**
* @brief Starts the modem in network operation mode.
*
* @return 0 on success. Otherwise <0 is returned.
*/
int mdm_sim7080_start_network(void);
/**
* @brief Starts the modem in gnss operation mode.
*
* @return 0 on success. Otherwise <0 is returned.
*/
int mdm_sim7080_start_gnss(void);
/**
* @brief Query gnss position form the modem.
*
* @return 0 on success. If no fix is acquired yet -EAGAIN is returned.
* Otherwise <0 is returned.
*/
int mdm_sim7080_query_gnss(struct sim7080_gnss_data *data);
/**
* Get the sim7080 manufacturer.
*/
const char *mdm_sim7080_get_manufacturer(void);
/**
* Get the sim7080 model information.
*/
const char *mdm_sim7080_get_model(void);
/**
* Get the sim7080 revision.
*/
const char *mdm_sim7080_get_revision(void);
/**
* Get the sim7080 imei number.
*/
const char *mdm_sim7080_get_imei(void);
/**
* Read sms from sim module.
*
* @param buffer Buffer structure for sms.
* @return Number of sms read on success. Otherwise -1 is returned.
*
* @note The buffer structure needs to be initialized to
* the size of the sms buffer. When this function finishes
* successful, nsms will be set to the number of sms read.
* If the whole structure is filled a subsequent read may
* be needed.
*/
int mdm_sim7080_read_sms(struct sim7080_sms_buffer *buffer);
/**
* Delete a sms at a given index.
*
* @param index The index of the sms in memory.
* @return 0 on success. Otherwise -1 is returned.
*/
int mdm_sim7080_delete_sms(uint16_t index);
/**
* Start a ftp get session.
*
* @param server The ftp servers address.
* @param user User name for the ftp server.
* @param passwd Password for the ftp user.
* @param file File to be downloaded.
* @param path Path to the file on the server.
* @return 0 if the session was started. Otherwise -1 is returned.
*/
int mdm_sim7080_ftp_get_start(const char *server, const char *user, const char *passwd,
const char *file, const char *path);
/**
* Read data from a ftp get session.
*
* @param dst The destination buffer.
* @param size Initialize to the size of dst. Gets set to the number
* of bytes actually read.
* @return According sim7080_ftp_rc.
*/
int mdm_sim7080_ftp_get_read(char *dst, size_t *size);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_MODEM_SIMCOM_SIM7080_H */
``` | /content/code_sandbox/include/zephyr/drivers/modem/simcom-sim7080.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,315 |
```objective-c
/**
* @file
*
* @brief Public APIs for the PCIe EP drivers.
*/
/*
*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_EP_H_
#define ZEPHYR_INCLUDE_DRIVERS_PCIE_EP_H_
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <stdint.h>
enum pcie_ob_mem_type {
PCIE_OB_ANYMEM, /**< PCIe OB window within any address range */
PCIE_OB_LOWMEM, /**< PCIe OB window within 32-bit address range */
PCIE_OB_HIGHMEM, /**< PCIe OB window above 32-bit address range */
};
enum pci_ep_irq_type {
PCIE_EP_IRQ_LEGACY, /**< Raise Legacy interrupt */
PCIE_EP_IRQ_MSI, /**< Raise MSI interrupt */
PCIE_EP_IRQ_MSIX, /**< Raise MSIX interrupt */
};
enum xfer_direction {
HOST_TO_DEVICE, /**< Read from Host */
DEVICE_TO_HOST, /**< Write to Host */
};
enum pcie_reset {
PCIE_PERST, /**< Cold reset */
PCIE_PERST_INB, /**< Inband hot reset */
PCIE_FLR, /**< Functional Level Reset */
PCIE_RESET_MAX
};
/**
* @typedef pcie_ep_reset_callback_t
* @brief Callback API for PCIe reset interrupts
*
* These callbacks execute in interrupt context. Therefore, use only
* interrupt-safe APIS. Registration of callbacks is done via
* @a pcie_ep_register_reset_cb
*
* @param arg Pointer provided at registration time, later to be
* passed back as argument to callback function
*/
typedef void (*pcie_ep_reset_callback_t)(void *arg);
__subsystem struct pcie_ep_driver_api {
int (*conf_read)(const struct device *dev, uint32_t offset,
uint32_t *data);
void (*conf_write)(const struct device *dev, uint32_t offset,
uint32_t data);
int (*map_addr)(const struct device *dev, uint64_t pcie_addr,
uint64_t *mapped_addr, uint32_t size,
enum pcie_ob_mem_type ob_mem_type);
void (*unmap_addr)(const struct device *dev, uint64_t mapped_addr);
int (*raise_irq)(const struct device *dev,
enum pci_ep_irq_type irq_type,
uint32_t irq_num);
int (*register_reset_cb)(const struct device *dev,
enum pcie_reset reset,
pcie_ep_reset_callback_t cb, void *arg);
int (*dma_xfer)(const struct device *dev, uint64_t mapped_addr,
uintptr_t local_addr, uint32_t size,
enum xfer_direction dir);
};
/**
* @brief Read PCIe EP configuration space
*
* @details This API reads EP's own configuration space
*
* @param dev Pointer to the device structure for the driver instance
* @param offset Offset within configuration space
* @param data Pointer to data read from the offset
*
* @return 0 if successful, negative errno code if failure.
*/
static inline int pcie_ep_conf_read(const struct device *dev,
uint32_t offset, uint32_t *data)
{
const struct pcie_ep_driver_api *api =
(const struct pcie_ep_driver_api *)dev->api;
return api->conf_read(dev, offset, data);
}
/**
* @brief Write PCIe EP configuration space
*
* @details This API writes EP's own configuration space
*
* @param dev Pointer to the device structure for the driver instance
* @param offset Offset within configuration space
* @param data Data to be written at the offset
*/
static inline void pcie_ep_conf_write(const struct device *dev,
uint32_t offset, uint32_t data)
{
const struct pcie_ep_driver_api *api =
(const struct pcie_ep_driver_api *)dev->api;
api->conf_write(dev, offset, data);
}
/**
* @brief Map a host memory buffer to PCIe outbound region
*
* @details This API maps a host memory buffer to PCIe outbound region,
* It is left to EP driver to manage multiple mappings through
* multiple PCIe outbound regions if supported by SoC
*
* @param dev Pointer to the device structure for the driver instance
* @param pcie_addr Host memory buffer address to be mapped
* @param mapped_addr Mapped PCIe outbound region address
* @param size Host memory buffer size (bytes)
* @param ob_mem_type Hint if lowmem/highmem outbound region has to be used,
* this is useful in cases where bus master cannot generate
* more than 32-bit address; it becomes essential to use
* lowmem outbound region
*
* @return Mapped size : If mapped size is less than requested size,
* then requester has to call the same API again to map
* the unmapped host buffer after data transfer is done with
* mapped size. This situation may arise because of the
* mapping alignment requirements.
*
* @return Negative errno code if failure.
*/
static inline int pcie_ep_map_addr(const struct device *dev,
uint64_t pcie_addr,
uint64_t *mapped_addr, uint32_t size,
enum pcie_ob_mem_type ob_mem_type)
{
const struct pcie_ep_driver_api *api =
(const struct pcie_ep_driver_api *)dev->api;
return api->map_addr(dev, pcie_addr, mapped_addr, size, ob_mem_type);
}
/**
* @brief Remove mapping to PCIe outbound region
*
* @details This API removes mapping to PCIe outbound region.
* Mapped PCIe outbound region address is given as argument
* to figure out the outbound region to be unmapped
*
* @param dev Pointer to the device structure for the driver instance
* @param mapped_addr PCIe outbound region address
*/
static inline void pcie_ep_unmap_addr(const struct device *dev,
uint64_t mapped_addr)
{
const struct pcie_ep_driver_api *api =
(const struct pcie_ep_driver_api *)dev->api;
api->unmap_addr(dev, mapped_addr);
}
/**
* @brief Raise interrupt to Host
*
* @details This API raises interrupt to Host
*
* @param dev Pointer to the device structure for the driver instance
* @param irq_type Type of Interrupt be raised (legacy, MSI or MSI-X)
* @param irq_num MSI or MSI-X interrupt number
*
* @return 0 if successful, negative errno code if failure.
*/
static inline int pcie_ep_raise_irq(const struct device *dev,
enum pci_ep_irq_type irq_type,
uint32_t irq_num)
{
const struct pcie_ep_driver_api *api =
(const struct pcie_ep_driver_api *)dev->api;
return api->raise_irq(dev, irq_type, irq_num);
}
/**
* @brief Register callback function for reset interrupts
*
* @details If reset interrupts are handled by device, this API can be
* used to register callback function, which will be
* executed part of corresponding PCIe reset handler
*
* @param dev Pointer to the device structure for the driver instance
* @param reset Reset interrupt type
* @param cb Callback function being registered
* @param arg Argument to be passed back to callback function
*
* @return 0 if successful, negative errno code if failure.
*/
static inline int pcie_ep_register_reset_cb(const struct device *dev,
enum pcie_reset reset,
pcie_ep_reset_callback_t cb,
void *arg)
{
const struct pcie_ep_driver_api *api =
(const struct pcie_ep_driver_api *)dev->api;
if (api->register_reset_cb) {
return api->register_reset_cb(dev, reset, cb, arg);
}
return -ENOTSUP;
}
/**
* @brief Data transfer between mapped Host memory and device memory with
* "System DMA". The term "System DMA" is used to clarify that we
* are not talking about dedicated "PCIe DMA"; rather the one
* which does not understand PCIe address directly, and
* uses the mapped Host memory.
*
* @details If DMA controller is available in the EP device, this API can be
* used to achieve data transfer between mapped Host memory,
* i.e. outbound memory and EP device's local memory with DMA
*
* @param dev Pointer to the device structure for the driver instance
* @param mapped_addr Mapped Host memory address
* @param local_addr Device memory address
* @param size DMA transfer length (bytes)
* @param dir Direction of DMA transfer
*
* @return 0 if successful, negative errno code if failure.
*/
static inline int pcie_ep_dma_xfer(const struct device *dev,
uint64_t mapped_addr,
uintptr_t local_addr, uint32_t size,
const enum xfer_direction dir)
{
const struct pcie_ep_driver_api *api =
(const struct pcie_ep_driver_api *)dev->api;
if (api->dma_xfer) {
return api->dma_xfer(dev, mapped_addr, local_addr, size, dir);
}
return -ENOTSUP;
}
/**
* @brief Data transfer using memcpy
*
* @details Helper API to achieve data transfer with memcpy
* through PCIe outbound memory
*
* @param dev Pointer to the device structure for the driver instance
* @param pcie_addr Host memory buffer address
* @param local_addr Local memory buffer address
* @param size Data transfer size (bytes)
* @param ob_mem_type Hint if lowmem/highmem outbound region has to be used
* (PCIE_OB_LOWMEM / PCIE_OB_HIGHMEM / PCIE_OB_ANYMEM),
* should be PCIE_OB_LOWMEM if bus master cannot generate
* more than 32-bit address
* @param dir Data transfer direction (HOST_TO_DEVICE / DEVICE_TO_HOST)
*
* @return 0 if successful, negative errno code if failure.
*/
int pcie_ep_xfer_data_memcpy(const struct device *dev, uint64_t pcie_addr,
uintptr_t *local_addr, uint32_t size,
enum pcie_ob_mem_type ob_mem_type,
enum xfer_direction dir);
/**
* @brief Data transfer using system DMA
*
* @details Helper API to achieve data transfer with system DMA through PCIe
* outbound memory, this API is based off pcie_ep_xfer_data_memcpy,
* here we use "system dma" instead of memcpy
*
* @param dev Pointer to the device structure for the driver instance
* @param pcie_addr Host memory buffer address
* @param local_addr Local memory buffer address
* @param size Data transfer size (bytes)
* @param ob_mem_type Hint if lowmem/highmem outbound region has to be used
* (PCIE_OB_LOWMEM / PCIE_OB_HIGHMEM / PCIE_OB_ANYMEM)
* @param dir Data transfer direction (HOST_TO_DEVICE / DEVICE_TO_HOST)
*
* @return 0 if successful, negative errno code if failure.
*/
int pcie_ep_xfer_data_dma(const struct device *dev, uint64_t pcie_addr,
uintptr_t *local_addr, uint32_t size,
enum pcie_ob_mem_type ob_mem_type,
enum xfer_direction dir);
#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_EP_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/pcie/endpoint/pcie_ep.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,460 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_LM95234_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_LM95234_H_
#include <zephyr/drivers/sensor.h>
enum sensor_channel_lm95234 {
/* External temperature inputs */
SENSOR_CHAN_LM95234_REMOTE_TEMP_1 = SENSOR_CHAN_PRIV_START,
SENSOR_CHAN_LM95234_REMOTE_TEMP_2,
SENSOR_CHAN_LM95234_REMOTE_TEMP_3,
SENSOR_CHAN_LM95234_REMOTE_TEMP_4
};
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_LM95234_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/lm95234.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 128 |
```objective-c
/*
*
*/
#ifndef _MAX31865_PUB_H
#define _MAX31865_PUB_H
#define SENSOR_ATTR_MAX31865_THREE_WIRE SENSOR_ATTR_PRIV_START
#endif /* _MAX31865_PUB_H */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/max31865.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP116_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP116_H_
#include <zephyr/device.h>
#include <sys/types.h>
#define EEPROM_TMP116_SIZE (4 * sizeof(uint16_t))
int tmp116_eeprom_read(const struct device *dev, off_t offset, void *data,
size_t len);
int tmp116_eeprom_write(const struct device *dev, off_t offset,
const void *data, size_t len);
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP116_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/tmp116.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_FCX_MLDX5_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_FCX_MLDX5_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
enum sensor_attribute_fcx_mldx5 {
SENSOR_ATTR_FCX_MLDX5_STATUS = SENSOR_ATTR_PRIV_START,
SENSOR_ATTR_FCX_MLDX5_RESET,
};
enum fcx_mldx5_status {
FCX_MLDX5_STATUS_STANDBY = 2,
FCX_MLDX5_STATUS_RAMP_UP = 3,
FCX_MLDX5_STATUS_RUN = 4,
FCX_MLDX5_STATUS_ERROR = 5,
/* Unknown is not sent by the sensor */
FCX_MLDX5_STATUS_UNKNOWN,
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_FCX_MLDX5_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/fcx_mldx5.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 210 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TCS3400_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TCS3400_H_
#include <zephyr/drivers/sensor.h>
enum sensor_attribute_tcs3400 {
/** RGBC Integration Cycles */
SENSOR_ATTR_TCS3400_INTEGRATION_CYCLES = SENSOR_ATTR_PRIV_START,
};
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TCS3400_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/tcs3400.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMAG5273_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMAG5273_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
/* --- Additional TMAG5273 definitions */
/** Additional channels supported by the TMAG5273 */
enum tmag5273_sensor_channel {
/**
* Magnitude measurement result between two axis in Gs.
*/
TMAG5273_CHAN_MAGNITUDE = SENSOR_CHAN_PRIV_START,
/**
* Magnitude measurement MSB as returned by the sensor.
*/
TMAG5273_CHAN_MAGNITUDE_MSB,
/**
* Angle result in deg, magnitude result in Gs and magnitude MSB between two axis.
*/
TMAG5273_CHAN_ANGLE_MAGNITUDE,
};
/** Additional attributes supported by the TMAG5273 */
enum tmag5273_attribute {
/**
* Define axis relation measurements.
* Supported values are:
* - \c TMAG5273_DT_ANGLE_MAG_NONE (0)
* - \c TMAG5273_DT_ANGLE_MAG_XY (1)
* - \c TMAG5273_DT_ANGLE_MAG_YZ (2)
* - \c TMAG5273_DT_ANGLE_MAG_XZ (3)
*
* Only available if calculation source can be changed during runtime.
*/
TMAG5273_ATTR_ANGLE_MAG_AXIS = SENSOR_ATTR_PRIV_START,
};
/**
* Supported values
*/
#define TMAG5273_ANGLE_CALC_NONE 0
#define TMAG5273_ANGLE_CALC_XY 1
#define TMAG5273_ANGLE_CALC_YZ 2
#define TMAG5273_ANGLE_CALC_XZ 3
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMAG5273_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/tmag5273.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 396 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for MH-Z19B CO2 Sensor
*
* Some capabilities and operational requirements for this sensor
* cannot be expressed within the sensor driver abstraction.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_MHZ19B_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_MHZ19B_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
enum sensor_attribute_mhz19b {
/** Automatic Baseline Correction Self Calibration Function. */
SENSOR_ATTR_MHZ19B_ABC = SENSOR_ATTR_PRIV_START,
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_MHZ19B_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/mhz19b.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 155 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for the Texas Instruments FDC2X1X
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_FDC2X1X_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_FDC2X1X_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
enum sensor_channel_fdc2x1x {
/** CH0 Capacitance, in Picofarad **/
SENSOR_CHAN_FDC2X1X_CAPACITANCE_CH0 = SENSOR_CHAN_PRIV_START,
/** CH1 Capacitance, in Picofarad **/
SENSOR_CHAN_FDC2X1X_CAPACITANCE_CH1,
/** CH2 Capacitance, in Picofarad **/
SENSOR_CHAN_FDC2X1X_CAPACITANCE_CH2,
/** CH3 Capacitance, in Picofarad **/
SENSOR_CHAN_FDC2X1X_CAPACITANCE_CH3,
/** CH0 Frequency, in MHz **/
SENSOR_CHAN_FDC2X1X_FREQ_CH0,
/** CH1 Frequency, in MHz **/
SENSOR_CHAN_FDC2X1X_FREQ_CH1,
/** CH2 Frequency, in MHz **/
SENSOR_CHAN_FDC2X1X_FREQ_CH2,
/** CH3 Frequency, in MHz **/
SENSOR_CHAN_FDC2X1X_FREQ_CH3,
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_FDC2X1X_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/fdc2x1x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 331 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_MAX17055_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_MAX17055_H_
#include <zephyr/drivers/sensor.h>
enum sensor_channel_max17055 {
/** Battery Open Circuit Voltage. */
SENSOR_CHAN_MAX17055_VFOCV = SENSOR_CHAN_PRIV_START,
};
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_MAX17055_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/max17055.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 89 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for 1-Wire Sensors
*
* This header file exposes an attribute an helper function to allow the
* runtime configuration of ROM IDs for 1-Wire Sensors.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_W1_SENSOR_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_W1_SENSOR_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
#include <zephyr/drivers/w1.h>
/**
* @brief 1-Wire Sensor API
* @defgroup w1_sensor 1-Wire Sensor API
* @ingroup w1_interface
* @{
*/
enum sensor_attribute_w1 {
/** Device unique 1-Wire ROM */
SENSOR_ATTR_W1_ROM = SENSOR_ATTR_PRIV_START,
};
/**
* @brief Function to write a w1_rom struct to an sensor value ptr.
*
* @param rom Pointer to the rom struct.
* @param val Pointer to the sensor value.
*/
static inline void w1_rom_to_sensor_value(const struct w1_rom *rom,
struct sensor_value *val)
{
val->val1 = sys_get_be64((uint8_t *)rom) & BIT64_MASK(32);
val->val2 = sys_get_be64((uint8_t *)rom) >> 32;
}
/**
* @brief Function to write an rom id stored in a sensor value to a struct w1_rom ptr.
*
* @param val Sensor_value representing the rom.
* @param rom The rom struct ptr.
*/
static inline void w1_sensor_value_to_rom(const struct sensor_value *val,
struct w1_rom *rom)
{
uint64_t temp64 = ((uint64_t)((uint32_t)val->val2) << 32)
| (uint32_t)val->val1;
sys_put_be64(temp64, (uint8_t *)rom);
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_W1_SENSOR_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/w1_sensor.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 434 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_IT8XXX2_VCMP_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_IT8XXX2_VCMP_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
enum it8xxx2_vcmp_sensor_attribute {
SENSOR_ATTR_LOWER_VOLTAGE_THRESH = SENSOR_ATTR_PRIV_START,
SENSOR_ATTR_UPPER_VOLTAGE_THRESH,
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_IT8XXX2_VCMP_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/it8xxx2_vcmp.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```objective-c
/** @file
* @brief HL7800 modem public API header file.
*
* Allows an application to control the HL7800 modem.
*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MODEM_HL7800_H_
#define ZEPHYR_INCLUDE_DRIVERS_MODEM_HL7800_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/types.h>
#include <time.h>
/* The size includes the NUL character, the strlen doesn't */
#define MDM_HL7800_REVISION_MAX_SIZE 29
#define MDM_HL7800_REVISION_MAX_STRLEN (MDM_HL7800_REVISION_MAX_SIZE - 1)
#define MDM_HL7800_IMEI_SIZE 16
#define MDM_HL7800_IMEI_STRLEN (MDM_HL7800_IMEI_SIZE - 1)
#define MDM_HL7800_ICCID_MAX_SIZE 21
#define MDM_HL7800_ICCID_MAX_STRLEN (MDM_HL7800_ICCID_MAX_SIZE - 1)
#define MDM_HL7800_SERIAL_NUMBER_SIZE 15
#define MDM_HL7800_SERIAL_NUMBER_STRLEN (MDM_HL7800_SERIAL_NUMBER_SIZE - 1)
#define MDM_HL7800_APN_MAX_SIZE 64
#define MDM_HL7800_APN_USERNAME_MAX_SIZE 65
#define MDM_HL7800_APN_PASSWORD_MAX_SIZE 65
#define MDM_HL7800_APN_MAX_STRLEN (MDM_HL7800_APN_MAX_SIZE - 1)
#define MDM_HL7800_APN_USERNAME_MAX_STRLEN \
(MDM_HL7800_APN_USERNAME_MAX_SIZE - 1)
#define MDM_HL7800_APN_PASSWORD_MAX_STRLEN \
(MDM_HL7800_APN_PASSWORD_MAX_SIZE - 1)
#define MDM_HL7800_APN_CMD_MAX_SIZE \
(32 + MDM_HL7800_APN_USERNAME_MAX_STRLEN + \
MDM_HL7800_APN_PASSWORD_MAX_STRLEN)
#define MDM_HL7800_APN_CMD_MAX_STRLEN (MDM_HL7800_APN_CMD_MAX_SIZE - 1)
struct mdm_hl7800_apn {
char value[MDM_HL7800_APN_MAX_SIZE];
char username[MDM_HL7800_APN_USERNAME_MAX_SIZE];
char password[MDM_HL7800_APN_PASSWORD_MAX_SIZE];
};
#define MDM_HL7800_LTE_BAND_STR_SIZE 21
#define MDM_HL7800_LTE_BAND_STRLEN (MDM_HL7800_LTE_BAND_STR_SIZE - 1)
#define MDM_HL7800_OPERATOR_INDEX_SIZE 3
#define MDM_HL7800_OPERATOR_INDEX_STRLEN (MDM_HL7800_OPERATOR_INDEX_SIZE - 1)
#define MDM_HL7800_IMSI_MIN_STR_SIZE 15
#define MDM_HL7800_IMSI_MAX_STR_SIZE 16
#define MDM_HL7800_IMSI_MAX_STRLEN (MDM_HL7800_IMSI_MAX_STR_SIZE - 1)
#define MDM_HL7800_MODEM_FUNCTIONALITY_SIZE 2
#define MDM_HL7800_MODEM_FUNCTIONALITY_STRLEN \
(MDM_HL7800_MODEM_FUNCTIONALITY_SIZE - 1)
#define MDM_HL7800_MAX_GPS_STR_SIZE 33
#define MDM_HL7800_MAX_POLTE_USER_ID_SIZE 16
#define MDM_HL7800_MAX_POLTE_PASSWORD_SIZE 16
#define MDM_HL7800_MAX_POLTE_LOCATION_STR_SIZE 33
/* Assign the server error code (location response) to a value
* that isn't used by locate response so that a single status
* callback can be used.
*/
#define MDM_HL7800_POLTE_SERVER_ERROR 10
#define MDM_HL7800_SET_POLTE_USER_AND_PASSWORD_FMT_STR "AT%%POLTECMD=\"SERVERAUTH\",\"%s\",\"%s\""
struct mdm_hl7800_site_survey {
uint32_t earfcn; /* EUTRA Absolute Radio Frequency Channel Number */
uint32_t cell_id;
int rsrp;
int rsrq;
};
enum mdm_hl7800_radio_mode { MDM_RAT_CAT_M1 = 0, MDM_RAT_CAT_NB1 };
enum mdm_hl7800_event {
HL7800_EVENT_RESERVED = 0,
HL7800_EVENT_NETWORK_STATE_CHANGE,
HL7800_EVENT_APN_UPDATE,
HL7800_EVENT_RSSI,
HL7800_EVENT_SINR,
HL7800_EVENT_STARTUP_STATE_CHANGE,
HL7800_EVENT_SLEEP_STATE_CHANGE,
HL7800_EVENT_RAT,
HL7800_EVENT_BANDS,
HL7800_EVENT_ACTIVE_BANDS,
HL7800_EVENT_FOTA_STATE,
HL7800_EVENT_FOTA_COUNT,
HL7800_EVENT_REVISION,
HL7800_EVENT_GPS,
HL7800_EVENT_GPS_POSITION_STATUS,
HL7800_EVENT_POLTE_REGISTRATION,
HL7800_EVENT_POLTE_LOCATE_STATUS,
HL7800_EVENT_POLTE,
HL7800_EVENT_SITE_SURVEY,
};
enum mdm_hl7800_startup_state {
HL7800_STARTUP_STATE_READY = 0,
HL7800_STARTUP_STATE_WAITING_FOR_ACCESS_CODE,
HL7800_STARTUP_STATE_SIM_NOT_PRESENT,
HL7800_STARTUP_STATE_SIMLOCK,
HL7800_STARTUP_STATE_UNRECOVERABLE_ERROR,
HL7800_STARTUP_STATE_UNKNOWN,
HL7800_STARTUP_STATE_INACTIVE_SIM
};
enum mdm_hl7800_network_state {
HL7800_NOT_REGISTERED = 0,
HL7800_HOME_NETWORK,
HL7800_SEARCHING,
HL7800_REGISTRATION_DENIED,
HL7800_OUT_OF_COVERAGE,
HL7800_ROAMING,
HL7800_EMERGENCY = 8,
/* Laird defined states */
HL7800_UNABLE_TO_CONFIGURE = 0xf0
};
enum mdm_hl7800_sleep {
HL7800_SLEEP_UNINITIALIZED = 0,
HL7800_SLEEP_HIBERNATE,
HL7800_SLEEP_AWAKE,
HL7800_SLEEP_LITE_HIBERNATE,
HL7800_SLEEP_SLEEP,
};
enum mdm_hl7800_fota_state {
HL7800_FOTA_IDLE,
HL7800_FOTA_START,
HL7800_FOTA_WIP,
HL7800_FOTA_PAD,
HL7800_FOTA_SEND_EOT,
HL7800_FOTA_FILE_ERROR,
HL7800_FOTA_INSTALL,
HL7800_FOTA_REBOOT_AND_RECONFIGURE,
HL7800_FOTA_COMPLETE,
};
enum mdm_hl7800_functionality {
HL7800_FUNCTIONALITY_MINIMUM = 0,
HL7800_FUNCTIONALITY_FULL = 1,
HL7800_FUNCTIONALITY_AIRPLANE = 4
};
/* The modem reports state values as an enumeration and a string.
* GPS values are reported with a type of value and string.
*/
struct mdm_hl7800_compound_event {
uint8_t code;
char *string;
};
enum mdm_hl7800_gnss_event {
HL7800_GNSS_EVENT_INVALID = -1,
HL7800_GNSS_EVENT_INIT,
HL7800_GNSS_EVENT_START,
HL7800_GNSS_EVENT_STOP,
HL7800_GNSS_EVENT_POSITION,
};
enum mdm_hl7800_gnss_status {
HL7800_GNSS_STATUS_INVALID = -1,
HL7800_GNSS_STATUS_FAILURE,
HL7800_GNSS_STATUS_SUCCESS,
};
enum mdm_hl7800_gnss_position_event {
HL7800_GNSS_POSITION_EVENT_INVALID = -1,
HL7800_GNSS_POSITION_EVENT_LOST_OR_NOT_AVAILABLE_YET,
HL7800_GNSS_POSITION_EVENT_PREDICTION_AVAILABLE,
HL7800_GNSS_POSITION_EVENT_2D_AVAILABLE,
HL7800_GNSS_POSITION_EVENT_3D_AVAILABLE,
HL7800_GNSS_POSITION_EVENT_FIXED_TO_INVALID,
};
enum mdm_hl7800_gps_string_types {
HL7800_GPS_STR_LATITUDE,
HL7800_GPS_STR_LONGITUDE,
HL7800_GPS_STR_GPS_TIME,
HL7800_GPS_STR_FIX_TYPE,
HL7800_GPS_STR_HEPE,
HL7800_GPS_STR_ALTITUDE,
HL7800_GPS_STR_ALT_UNC,
HL7800_GPS_STR_DIRECTION,
HL7800_GPS_STR_HOR_SPEED,
HL7800_GPS_STR_VER_SPEED
};
/* status: negative errno, 0 on success
* user and password aren't valid if status is non-zero.
*/
struct mdm_hl7800_polte_registration_event_data {
int status;
char *user;
char *password;
};
/* status: negative errno, 0 on success, non-zero error code
* Data is not valid if status is non-zero.
*/
struct mdm_hl7800_polte_location_data {
uint32_t timestamp;
int status;
char latitude[MDM_HL7800_MAX_POLTE_LOCATION_STR_SIZE];
char longitude[MDM_HL7800_MAX_POLTE_LOCATION_STR_SIZE];
char confidence_in_meters[MDM_HL7800_MAX_POLTE_LOCATION_STR_SIZE];
};
/**
* event - The type of event
* event_data - Pointer to event specific data structure
* HL7800_EVENT_NETWORK_STATE_CHANGE - compound event
* HL7800_EVENT_APN_UPDATE - struct mdm_hl7800_apn
* HL7800_EVENT_RSSI - int
* HL7800_EVENT_SINR - int
* HL7800_EVENT_STARTUP_STATE_CHANGE - compound event
* HL7800_EVENT_SLEEP_STATE_CHANGE - compound event
* HL7800_EVENT_RAT - int
* HL7800_EVENT_BANDS - string
* HL7800_EVENT_ACTIVE_BANDS - string
* HL7800_EVENT_FOTA_STATE - compound event
* HL7800_EVENT_FOTA_COUNT - uint32_t
* HL7800_EVENT_REVISION - string
* HL7800_EVENT_GPS - compound event
* HL7800_EVENT_GPS_POSITION_STATUS int
* HL7800_EVENT_POLTE_REGISTRATION mdm_hl7800_polte_registration_event_data
* HL7800_EVENT_POLTE mdm_hl7800_polte_location_data
* HL7800_EVENT_POLTE_LOCATE_STATUS int
* HL7800_EVENT_SITE_SURVEY mdm_hl7800_site_survey
*/
typedef void (*mdm_hl7800_event_callback_t)(enum mdm_hl7800_event event,
void *event_data);
struct mdm_hl7800_callback_agent {
sys_snode_t node;
mdm_hl7800_event_callback_t event_callback;
};
/**
* @brief Power off the HL7800
*
* @return int32_t 0 for success
*/
int32_t mdm_hl7800_power_off(void);
/**
* @brief Reset the HL7800 (and allow it to reconfigure).
*
* @return int32_t 0 for success
*/
int32_t mdm_hl7800_reset(void);
/**
* @brief Control the wake signals to the HL7800.
* @note this API should only be used for debug purposes.
*
* @param awake True to keep the HL7800 awake, False to allow sleep
*/
void mdm_hl7800_wakeup(bool awake);
/**
* @brief Send an AT command to the HL7800.
* @note this API should only be used for debug purposes.
*
* @param data AT command string
* @return int32_t 0 for success
*/
int32_t mdm_hl7800_send_at_cmd(const uint8_t *data);
/**
* @brief Get the signal quality of the HL7800.
* If CONFIG_MODEM_HL7800_RSSI_RATE_SECONDS is non-zero, then
* this function returns the value from the last periodic read.
* If CONFIG_MODEM_HL7800_RSSI_RATE_SECONDS is 0, then this
* may cause the modem to be woken so that the values can be queried.
*
* @param rsrp Reference Signals Received Power (dBm)
* Range = -140 dBm to -44 dBm
* @param sinr Signal to Interference plus Noise Ratio (dB)
* Range = -128 dB to 40 dB
*/
void mdm_hl7800_get_signal_quality(int *rsrp, int *sinr);
/**
* @brief Get the SIM card ICCID
*
*/
char *mdm_hl7800_get_iccid(void);
/**
* @brief Get the HL7800 serial number
*
*/
char *mdm_hl7800_get_sn(void);
/**
* @brief Get the HL7800 IMEI
*
*/
char *mdm_hl7800_get_imei(void);
/**
* @brief Get the HL7800 firmware version
*
*/
char *mdm_hl7800_get_fw_version(void);
/**
* @brief Get the IMSI
*
*/
char *mdm_hl7800_get_imsi(void);
/**
* @brief Update the Access Point Name in the modem.
*
* @retval 0 on success, negative on failure.
*/
int32_t mdm_hl7800_update_apn(char *access_point_name);
/**
* @brief Update the Radio Access Technology (mode).
*
* @retval 0 on success, negative on failure.
*/
int32_t mdm_hl7800_update_rat(enum mdm_hl7800_radio_mode value);
/**
* @retval true if RAT value is valid
*/
bool mdm_hl7800_valid_rat(uint8_t value);
/**
* @brief Register a function that is called when a modem event occurs.
* Multiple users registering for callbacks is supported.
*
* @param agent event callback agent
*
* @retval 0 on success, negative on failure
*/
int mdm_hl7800_register_event_callback(struct mdm_hl7800_callback_agent *agent);
/**
* @brief Unregister a callback event function
*
* @param agent event callback agent
*
* @retval 0 on success, negative on failure
*/
int mdm_hl7800_unregister_event_callback(struct mdm_hl7800_callback_agent *agent);
/**
* @brief Force modem module to generate status events.
*
* @note This can be used to get the current state when a module initializes
* later than the modem.
*/
void mdm_hl7800_generate_status_events(void);
/**
* @brief Get the local time from the modem's real time clock.
*
* @param tm time structure
* @param offset The amount the local time is offset from GMT/UTC in seconds.
* @return int32_t 0 if successful
*/
int32_t mdm_hl7800_get_local_time(struct tm *tm, int32_t *offset);
#ifdef CONFIG_MODEM_HL7800_FW_UPDATE
/**
* @brief Update the HL7800 via XMODEM protocol. During the firmware update
* no other modem functions will be available.
*
* @param file_path Absolute path of the update file
*
* @param 0 if successful
*/
int32_t mdm_hl7800_update_fw(char *file_path);
#endif
/**
* @brief Read the operator index from the modem.
*
* @retval negative error code, 0 on success
*/
int32_t mdm_hl7800_get_operator_index(void);
/**
* @brief Get modem functionality
*
* @return int32_t negative errno on failure, else mdm_hl7800_functionality
*/
int32_t mdm_hl7800_get_functionality(void);
/**
* @brief Set airplane, normal, or reduced functionality mode.
* Airplane mode persists when reset.
*
* @note Boot functionality is also controlled by Kconfig
* MODEM_HL7800_BOOT_IN_AIRPLANE_MODE.
*
* @param mode
* @return int32_t negative errno, 0 on success
*/
int32_t mdm_hl7800_set_functionality(enum mdm_hl7800_functionality mode);
/**
* @brief When rate is non-zero: Put modem into Airplane mode. Enable GPS and
* generate HL7800_EVENT_GPS events.
* When zero: Disable GPS and put modem into normal mode.
*
* @note Airplane mode isn't cleared when the modem is reset.
*
* @param rate in seconds to query location
* @return int32_t negative errno, 0 on success
*/
int32_t mdm_hl7800_set_gps_rate(uint32_t rate);
/**
* @brief Register modem/SIM with polte.io
*
* @note It takes around 30 seconds for HL7800_EVENT_POLTE_REGISTRATION to
* be generated. If the applications saves the user and password
* information into non-volatile memory, then this command
* only needs to be run once.
*
* @return int32_t negative errno, 0 on success
*/
int32_t mdm_hl7800_polte_register(void);
/**
* @brief Enable PoLTE.
*
* @param user from polte.io or register command callback
* @param password from polte.io register command callback
* @return int32_t negative errno, 0 on success
*/
int32_t mdm_hl7800_polte_enable(char *user, char *password);
/**
* @brief Locate device using PoLTE.
*
* @note The first HL7800_EVENT_POLTE_LOCATE_STATUS event indicates
* the status of issuing the locate command. The second event
* requires 20-120 seconds to be generated and it contains the
* location information (or indicates server failure).
*
* @return int32_t negative errno, 0 on success
*/
int32_t mdm_hl7800_polte_locate(void);
/**
* @brief Perform a site survey. This command may return different values
* each time it is run (depending on what is in range).
*
* HL7800_EVENT_SITE_SURVEY is generated for each response received from modem.
*
* @retval negative error code, 0 on success
*/
int32_t mdm_hl7800_perform_site_survey(void);
/**
* @brief Set desired sleep level. Requires MODEM_HL7800_LOW_POWER_MODE
*
* @param level (sleep, lite hibernate, or hibernate)
* @return int negative errno, 0 on success
*/
int mdm_hl7800_set_desired_sleep_level(enum mdm_hl7800_sleep level);
/**
* @brief Allows mapping of WAKE_UP signal
* to a user accessible test point on the development board.
*
* @param func to be called when application requests modem wake/sleep.
* The state parameter of the callback is 1 when modem should stay awake,
* 0 when modem can sleep
*/
void mdm_hl7800_register_wake_test_point_callback(void (*func)(int state));
/**
* @brief Allows mapping of P1.12_GPIO6 signal
* to a user accessible test point on the development board.
*
* @param func to be called when modem wakes/sleeps is sleep level is
* hibernate or lite hibernate.
* The state parameter of the callback follows gpio_pin_get definitions,
* but will default high if there is an error reading pin
*/
void mdm_hl7800_register_gpio6_callback(void (*func)(int state));
/**
* @brief Allows mapping of UART1_CTS signal
* to a user accessible test point on the development board.
*
* @param func to be called when CTS state changes if sleep level is sleep.
* The state parameter of the callback follows gpio_pin_get definitions,
* but will default low if there is an error reading pin
*/
void mdm_hl7800_register_cts_callback(void (*func)(int state));
/**
* @brief Set the bands available for the LTE connection.
* NOTE: This will cause the modem to reboot. This call returns before the reboot.
*
* @param bands Band bitmap in hexadecimal format without the 0x prefix.
* Leading 0's for the value can be omitted.
*
* @return int32_t negative errno, 0 on success
*/
int32_t mdm_hl7800_set_bands(const char *bands);
/**
* @brief Set the log level for the modem.
*
* @note It cannot be set higher than CONFIG_MODEM_LOG_LEVEL.
* If debug level is desired, then it must be compiled with that level.
*
* @param level 0 (None) - 4 (Debug)
*
* @retval new log level
*/
uint32_t mdm_hl7800_log_filter_set(uint32_t level);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_MODEM_HL7800_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/modem/hl7800.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,423 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for TI's TMP108 temperature sensor
*
* This exposes attributes for the TMP108 which can be used for
* setting the on-chip Temperature Mode and alert parameters.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP108_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP108_H_
#ifdef __cplusplus
extern "C" {
#endif
enum sensor_attribute_tmp_108 {
/** Turn on power saving/one shot mode */
SENSOR_ATTR_TMP108_ONE_SHOT_MODE = SENSOR_ATTR_PRIV_START,
/** Shutdown the sensor */
SENSOR_ATTR_TMP108_SHUTDOWN_MODE,
/** Turn on continuous conversion */
SENSOR_ATTR_TMP108_CONTINUOUS_CONVERSION_MODE,
/** Set the alert pin polarity */
SENSOR_ATTR_TMP108_ALERT_POLARITY
};
/** a tmp108 mask for the over temp alert bit in the status word*/
#define TMP108_OVER_TEMP_MASK 0x1000U
/** a tmp108 mask for the under temp alert bit in the status word*/
#define TMP108_UNDER_TEMP_MASK 0x0800U
/** a as6212 mask for the over temp alert bit in the status word*/
#define A6212_ALERT_TEMP_MASK 0x0020U
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP108_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/tmp108.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 285 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for AMS's TSL2540 ambient light sensor
*
* This exposes attributes for the TSL2540 which can be used for
* setting the on-chip gain and integration time parameters.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TSL2540_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TSL2540_H_
#include <zephyr/drivers/sensor.h>
#ifdef __cplusplus
extern "C" {
#endif
enum sensor_attribute_tsl2540 {
/* Sensor Integration Time (in ms) */
SENSOR_ATTR_INTEGRATION_TIME = SENSOR_ATTR_PRIV_START + 1,
/* Sensor ALS interrupt persistence filters */
SENSOR_ATTR_INT_APERS,
/* Shutdown the sensor */
SENSOR_ATTR_TSL2540_SHUTDOWN_MODE,
/* Turn on continuous conversion */
SENSOR_ATTR_TSL2540_CONTINUOUS_MODE,
/* Turn on continuous conversion without wait */
SENSOR_ATTR_TSL2540_CONTINUOUS_NO_WAIT_MODE,
};
enum sensor_gain_tsl2540 {
TSL2540_SENSOR_GAIN_1_2,
TSL2540_SENSOR_GAIN_1,
TSL2540_SENSOR_GAIN_4,
TSL2540_SENSOR_GAIN_16,
TSL2540_SENSOR_GAIN_64,
TSL2540_SENSOR_GAIN_128,
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TSL2540_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/tsl2540.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 305 |
```objective-c
/*
*
*/
#ifndef _ADC_CMP_NPCX_H_
#define _ADC_CMP_NPCX_H_
enum adc_cmp_npcx_comparison {
ADC_CMP_NPCX_GREATER,
ADC_CMP_NPCX_LESS_OR_EQUAL,
};
/* Supported ADC threshold controllers in NPCX series */
enum npcx_adc_cmp_thrctl {
ADC_CMP_NPCX_THRCTL1,
ADC_CMP_NPCX_THRCTL2,
ADC_CMP_NPCX_THRCTL3,
ADC_CMP_NPCX_THRCTL4,
ADC_CMP_NPCX_THRCTL5,
ADC_CMP_NPCX_THRCTL6,
ADC_CMP_NPCX_THRCTL_COUNT,
};
enum adc_cmp_npcx_sensor_attribute {
SENSOR_ATTR_LOWER_VOLTAGE_THRESH = SENSOR_ATTR_PRIV_START,
SENSOR_ATTR_UPPER_VOLTAGE_THRESH,
};
#endif /* _ADC_CMP_NPCX_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/adc_cmp_npcx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 174 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_QDEC_MCUX_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_QDEC_MCUX_H_
#include <zephyr/drivers/sensor.h>
enum sensor_attribute_qdec_mcux {
/* Number of counts per revolution */
SENSOR_ATTR_QDEC_MOD_VAL = SENSOR_ATTR_PRIV_START,
/* Single phase counting */
SENSOR_ATTR_QDEC_ENABLE_SINGLE_PHASE,
};
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_QDEC_MCUX_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/qdec_mcux.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_EXPLORIR_M_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_EXPLORIR_M_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
enum sensor_attribute_explorir_m {
/* Sensor integrated low-pass filter. Values 16, 32, 64, and 128 is allowed */
SENSOR_ATTR_EXPLORIR_M_FILTER = SENSOR_ATTR_PRIV_START,
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_EXPLORIR_M_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/explorir_m.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_MAX31790_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_MAX31790_H_
#include <zephyr/drivers/sensor.h>
/* MAX31790 specific channels */
enum sensor_channel_max31790 {
SENSOR_CHAN_MAX31790_FAN_FAULT = SENSOR_CHAN_PRIV_START,
};
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_MAX31790_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/max31790.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_VEML7700_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_VEML7700_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Number of enumerators in enum veml7700_als_gain.
*/
#define VEML7700_ALS_GAIN_ELEM_COUNT 4
/**
* @brief Number of enumerators in enum veml7700_als_it.
*/
#define VEML7700_ALS_IT_ELEM_COUNT 6
/**
* @brief Bit mask to check for the low threshold interrupt flag.
*
* See <tt>SENSOR_ATTR_VEML7700_INT_MODE</tt>
* and <tt>SENSOR_CHAN_VEML7700_INTERRUPT</tt>
*/
#define VEML7700_ALS_INT_LOW_MASK BIT(15)
/**
* @brief Bit mask to check for the high threshold interrupt flag.
*
* See <tt>SENSOR_ATTR_VEML7700_INT_MODE</tt>
* and <tt>SENSOR_CHAN_VEML7700_INTERRUPT</tt>
*/
#define VEML7700_ALS_INT_HIGH_MASK BIT(14)
/**
* @brief VEML7700 gain options for ambient light measurements.
*/
enum veml7700_als_gain {
VEML7700_ALS_GAIN_1 = 0x00, /* 0b00 */
VEML7700_ALS_GAIN_2 = 0x01, /* 0b01 */
VEML7700_ALS_GAIN_1_8 = 0x02, /* 0b10 */
VEML7700_ALS_GAIN_1_4 = 0x03, /* 0b11 */
};
/**
* @brief VEML7700 integration time options for ambient light measurements.
*/
enum veml7700_als_it {
VEML7700_ALS_IT_25,
VEML7700_ALS_IT_50,
VEML7700_ALS_IT_100,
VEML7700_ALS_IT_200,
VEML7700_ALS_IT_400,
VEML7700_ALS_IT_800
};
/**
* @brief VEML7700 ALS interrupt persistence protect number options.
*/
enum veml7700_int_mode {
VEML7700_INT_DISABLED = 0xFF,
VEML7700_ALS_PERS_1 = 0x00, /* 0b00 */
VEML7700_ALS_PERS_2 = 0x01, /* 0b01 */
VEML7700_ALS_PERS_4 = 0x02, /* 0b10 */
VEML7700_ALS_PERS_8 = 0x03, /* 0b11 */
};
/**
* @brief VEML7700 specific sensor attributes.
*
* For high and low threshold window settings (ALS_WH and ALS_WL)
* use the generic attributes <tt>SENSOR_ATTR_UPPER_THRESH</tt> and
* <tt>SENSOR_ATTR_LOWER_THRESH</tt> with 16-bit unsigned integer
* values. Both threshold settings are in lux and converted by the
* driver to a value compatible with the sensor. This conversion
* depends on the current gain and integration time settings. So a
* change in gain or integration time usually requires an update of
* threshold window settings. To get the correct threshold values
* into the sensor update the thresholds -after- a change of gain
* or integration time.
*
* All attributes must be set for the <tt>SENSOR_CHAN_LIGHT</tt> channel.
*/
enum sensor_attribute_veml7700 {
/**
* @brief Gain setting for ALS measurements (ALS_GAIN).
*
* Use enum veml7700_als_gain for attribute values.
*/
SENSOR_ATTR_VEML7700_GAIN = SENSOR_ATTR_PRIV_START,
/**
* @brief Integration time setting for ALS measurements (ALS_IT).
*
* Use enum veml7700_als_it for attribute values.
*/
SENSOR_ATTR_VEML7700_ITIME,
/**
* @brief Enable or disable use of ALS interrupt
* (ALS_INT_EN and ALS_PERS).
*
* Please mind that the VEML7700 does not have an interrupt pin.
* That's why this driver does not implement any asynchronous
* notification mechanism. Such notifications would require to
* periodically query the sensor for it's interrupt state and then
* trigger an event based on that state. It's up to the user to
* query the interrupt state manually using
* <tt>sensor_channel_fetch_chan()</tt> on the
* <tt>SENSOR_CHAN_VEML7700_INTERRUPT</tt> channel or using
* <tt>sensor_channel_fetch()</tt>.
*
* Use enum veml7700_int_mode for attribute values.
*/
SENSOR_ATTR_VEML7700_INT_MODE,
};
/**
* @brief VEML7700 specific sensor channels.
*/
enum sensor_channel_veml7700 {
/**
* @brief Channel for raw ALS sensor values.
*
* This channel represents the raw measurement counts provided by the
* sensors ALS register. It is useful for estimating the high/low
* threshold window attributes for the sensors interrupt handling.
*
* You cannot fetch this channel explicitly. Instead, this channel's
* value is fetched implicitly using <tt>SENSOR_CHAN_LIGHT</tt>.
* Trying to call <tt>sensor_channel_fetch_chan()</tt> with this
* enumerator as an argument will result in a <tt>-ENOTSUP</tt>.
*/
SENSOR_CHAN_VEML7700_RAW_COUNTS = SENSOR_CHAN_PRIV_START,
/**
* @brief Channel for white light sensor values.
*
* This channel is the White Channel count output of the sensor.
* The white channel can be used to correct for light sources with
* strong infrared content in the 750-800nm spectrum.
*/
SENSOR_CHAN_VEML7700_WHITE_RAW_COUNTS,
/**
* @brief This channel is used to query the ALS interrupt state (ALS_INT).
*
* In order for this channel to provide any meaningful data you need
* to enable the ALS interrupt mode using the
* <tt>SENSOR_ATTR_VEML7700_INT_MODE</tt> custom sensor attribute.
*
* It's important to note that the sensor resets it's interrupt state
* after retrieving it.
*/
SENSOR_CHAN_VEML7700_INTERRUPT,
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_VEML7700_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/veml7700.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,400 |
```objective-c
/*
*
*/
/**
* @file
* @brief Data structure for the NXP MCUX low-power analog comparator (LPCMP)
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_MCUX_LPCMP_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_MCUX_LPCMP_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
/**
* @brief lpcmp channels.
*/
enum sensor_channel_mcux_lpcmp {
/** LPCMP output. */
SENSOR_CHAN_MCUX_LPCMP_OUTPUT = SENSOR_CHAN_PRIV_START,
};
/**
* @brief lpcmp trigger types.
*/
enum sensor_trigger_type_mcux_lpcmp {
/** LPCMP output rising event trigger. */
SENSOR_TRIG_MCUX_LPCMP_OUTPUT_RISING = SENSOR_TRIG_PRIV_START,
/** LPCMP output falling event trigger. */
SENSOR_TRIG_MCUX_LPCMP_OUTPUT_FALLING,
};
/**
* @brief lpcmp attribute types.
*/
enum sensor_attribute_mcux_lpcmp {
/** LPCMP positive input mux. */
SENSOR_ATTR_MCUX_LPCMP_POSITIVE_MUX_INPUT = SENSOR_ATTR_COMMON_COUNT,
/** LPCMP negative input mux. */
SENSOR_ATTR_MCUX_LPCMP_NEGATIVE_MUX_INPUT,
/**
* LPCMP internal DAC enable.
* 0b: disable
* 1b: enable
*/
SENSOR_ATTR_MCUX_LPCMP_DAC_ENABLE,
/**
* LPCMP internal DAC high power mode disabled.
* 0b: disable
* 1b: enable
*/
SENSOR_ATTR_MCUX_LPCMP_DAC_HIGH_POWER_MODE_ENABLE,
/** LPCMP internal DAC voltage reference source. */
SENSOR_ATTR_MCUX_LPCMP_DAC_REFERENCE_VOLTAGE_SOURCE,
/** LPCMP internal DAC output voltage value. */
SENSOR_ATTR_MCUX_LPCMP_DAC_OUTPUT_VOLTAGE,
/** LPCMP internal filter sample enable. */
SENSOR_ATTR_MCUX_LPCMP_SAMPLE_ENABLE,
/** LPCMP internal filter sample count. */
SENSOR_ATTR_MCUX_LPCMP_FILTER_COUNT,
/** LPCMP internal filter sample period. */
SENSOR_ATTR_MCUX_LPCMP_FILTER_PERIOD,
/** LPCMP window signal invert. */
SENSOR_ATTR_MCUX_LPCMP_COUTA_WINDOW_ENABLE,
/** LPCMP window signal invert. */
SENSOR_ATTR_MCUX_LPCMP_COUTA_WINDOW_SIGNAL_INVERT_ENABLE,
/**
* LPCMP COUTA signal value when a window is closed:
* 00b: latched
* 01b: set to low
* 11b: set to high
*/
SENSOR_ATTR_MCUX_LPCMP_COUTA_SIGNAL,
/**
* LPCMP COUT event to close an active window:
* xx0b: COUT event cannot close an active window
* 001b: COUT rising edge event close an active window
* 011b: COUT falling edge event close an active window
* 1x1b: COUT both edges event close an active window
*/
SENSOR_ATTR_MCUX_LPCMP_COUT_EVENT_TO_CLOSE_WINDOW
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_MCUX_LPCMP_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/mcux_lpcmp.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 708 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_BD8LB600FS_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_BD8LB600FS_H_
#include <zephyr/drivers/sensor.h>
enum sensor_channel_bd8lb600fs {
/**
* Open load detected,
* boolean with one bit per output
*/
SENSOR_CHAN_BD8LB600FS_OPEN_LOAD = SENSOR_ATTR_PRIV_START,
/**
* Over current protection or thermal shutdown,
* boolean with one bit per output
*/
SENSOR_CHAN_BD8LB600FS_OVER_CURRENT_OR_THERMAL_SHUTDOWN,
};
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_BD8LB600FS_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/bd8lb600fs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 152 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_GROW_R502A_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_GROW_R502A_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
/*LED color code*/
enum r502a_led_color_idx {
R502A_LED_COLOR_RED = 0x01,
R502A_LED_COLOR_BLUE,
R502A_LED_COLOR_PURPLE,
};
#define R502A_BAUD_9600 1
#define R502A_BAUD_19200 2
#define R502A_BAUD_38400 4
#define R502A_BAUD_57600 6
#define R502A_BAUD_115200 12
enum r502a_sec_level {
R502A_SEC_LEVEL_1 = 1,
R502A_SEC_LEVEL_2,
R502A_SEC_LEVEL_3,
R502A_SEC_LEVEL_4,
R502A_SEC_LEVEL_5
};
enum r502a_data_len {
R502A_PKG_LEN_32,
R502A_PKG_LEN_64,
R502A_PKG_LEN_128,
R502A_PKG_LEN_256
};
enum r502a_sys_param_set {
R502A_BAUD_RATE = 4,
R502A_SECURITY_LEVEL,
R502A_DATA_PKG_LEN
};
struct r502a_sys_param {
uint16_t status_reg;
uint16_t system_id;
uint16_t lib_size;
uint16_t sec_level;
uint32_t addr;
uint16_t data_pkt_size;
uint32_t baud;
} __packed;
struct r502a_template {
uint8_t *data;
size_t len;
};
enum sensor_channel_grow_r502a {
/** Fingerprint template count, ID number for enrolling and searching*/
SENSOR_CHAN_FINGERPRINT = SENSOR_CHAN_PRIV_START,
};
enum sensor_trigger_type_grow_r502a {
/** Trigger fires when a touch is detected. */
SENSOR_TRIG_TOUCH = SENSOR_TRIG_PRIV_START,
};
enum sensor_attribute_grow_r502a {
/** To capture finger and store as feature file in
* RAM buffers char_buf_1 and char_buf_2.
*/
SENSOR_ATTR_R502A_CAPTURE = SENSOR_ATTR_PRIV_START,
/** create template from feature files at RAM buffers
* char_buf_1 & char_buf_2 and store a template data
* back in both RAM buffers char_buf_1 and char_buf_2.
*/
SENSOR_ATTR_R502A_TEMPLATE_CREATE,
/** Add template to the sensor record storage */
/**
* @param val->val1 record index for template to be
* stored in the sensor device's flash
* library.
*/
SENSOR_ATTR_R502A_RECORD_ADD,
/** To find requested data in record storage */
/**
* @result val->val1 matched record index.
* val->val2 matching score.
*/
SENSOR_ATTR_R502A_RECORD_FIND,
/** To delete mentioned data from record storage */
/**
* @param val->val1 record start index to be deleted.
* @param val->val2 number of records to be deleted.
*/
SENSOR_ATTR_R502A_RECORD_DEL,
/** To get available position to store data on record storage */
SENSOR_ATTR_R502A_RECORD_FREE_IDX,
/** To empty the storage record*/
SENSOR_ATTR_R502A_RECORD_EMPTY,
/** To load template from storage to RAM buffer of sensor*/
/**
* @param val->val1 record start index to be loaded in
* device internal RAM buffer.
*/
SENSOR_ATTR_R502A_RECORD_LOAD,
/** To template data stored in sensor's RAM buffer*/
/**
* @result
* val->val1 match result.
* [R502A_FINGER_MATCH_FOUND or
* R502A_FINGER_MATCH_NOT_FOUND]
* val->val2 matching score.
*/
SENSOR_ATTR_R502A_COMPARE,
/** To read and write device's system parameters */
/** sensor_attr_set
* @param val->val1 parameter number from enum r502a_sys_param_set.
* @param val->val2 content to be written for the respective parameter.
*/
/** sensor_attr_get
* @result val->ex.data buffer holds the system parameter values.
*/
SENSOR_ATTR_R502A_SYS_PARAM,
};
int r502a_read_sys_param(const struct device *dev, struct r502a_sys_param *val);
int fps_upload_char_buf(const struct device *dev, struct r502a_template *temp);
int fps_download_char_buf(const struct device *dev, uint8_t char_buf_id,
const struct r502a_template *temp);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_ZEPHYR_DRIVERS_SENSOR_GROW_R502A_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/grow_r502a.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,032 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for Sensirion's SHT4X T/RH sensors
*
* This exposes an API to the on-chip heater which is specific to
* the application/environment and cannot be expressed within the
* sensor driver abstraction.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_SHT4X_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_SHT4X_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
/* Maximum temperature above which the heater should not be used */
#define SHT4X_HEATER_MAX_TEMP 65
enum sensor_attribute_sht4x {
/* Heater Power: 0, 1, 2 -> high, med, low */
SENSOR_ATTR_SHT4X_HEATER_POWER = SENSOR_ATTR_PRIV_START,
/* Heater Duration: 0, 1 -> long, short */
SENSOR_ATTR_SHT4X_HEATER_DURATION
};
/**
* @brief Fetches data using the on-chip heater.
*
* Measurement is always done with "high" repeatability.
*
* @param dev Pointer to the sensor device
*
* @return 0 if successful, negative errno code if failure.
*/
int sht4x_fetch_with_heater(const struct device *dev);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_SHT4X_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/sht4x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 303 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for the NXP MCUX Analog Comparator (ACMP)
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_MCUX_ACMP_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_MCUX_ACMP_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
#if defined(FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT == 1U)
#define MCUX_ACMP_HAS_INPSEL 1
#else
#define MCUX_ACMP_HAS_INPSEL 0
#endif
#if defined(FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT == 1U)
#define MCUX_ACMP_HAS_INNSEL 1
#else
#define MCUX_ACMP_HAS_INNSEL 0
#endif
#if defined(FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT) && (FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT == 1U)
#define MCUX_ACMP_HAS_OFFSET 1
#else
#define MCUX_ACMP_HAS_OFFSET 0
#endif
#if defined(FSL_FEATURE_ACMP_HAS_C3_REG) && (FSL_FEATURE_ACMP_HAS_C3_REG != 0U)
#define MCUX_ACMP_HAS_DISCRETE_MODE 1
#else
#define MCUX_ACMP_HAS_DISCRETE_MODE 0
#endif
enum sensor_channel_mcux_acmp {
/** Analog Comparator Output. */
SENSOR_CHAN_MCUX_ACMP_OUTPUT = SENSOR_CHAN_PRIV_START,
};
enum sensor_trigger_type_mcux_acmp {
/** Analog Comparator Output rising event trigger. */
SENSOR_TRIG_MCUX_ACMP_OUTPUT_RISING = SENSOR_TRIG_PRIV_START,
/** Analog Comparator Output falling event trigger. */
SENSOR_TRIG_MCUX_ACMP_OUTPUT_FALLING,
};
enum sensor_attribute_mcux_acmp {
/** Analog Comparator hard block offset. */
SENSOR_ATTR_MCUX_ACMP_OFFSET_LEVEL = SENSOR_ATTR_COMMON_COUNT,
/** Analog Comparator hysteresis level. */
SENSOR_ATTR_MCUX_ACMP_HYSTERESIS_LEVEL,
/**
* Analog Comparator Digital-to-Analog Converter voltage
* reference source.
*/
SENSOR_ATTR_MCUX_ACMP_DAC_VOLTAGE_REFERENCE,
/** Analog Comparator Digital-to-Analog Converter value. */
SENSOR_ATTR_MCUX_ACMP_DAC_VALUE,
/** Analog Comparator positive port input. */
SENSOR_ATTR_MCUX_ACMP_POSITIVE_PORT_INPUT,
/** Analog Comparator positive mux input. */
SENSOR_ATTR_MCUX_ACMP_POSITIVE_MUX_INPUT,
/** Analog Comparator negative port input. */
SENSOR_ATTR_MCUX_ACMP_NEGATIVE_PORT_INPUT,
/** Analog Comparator negative mux input. */
SENSOR_ATTR_MCUX_ACMP_NEGATIVE_MUX_INPUT,
#if MCUX_ACMP_HAS_DISCRETE_MODE
/** Analog Comparator Positive Channel Discrete Mode Enable. */
SENSOR_ATTR_MCUX_ACMP_POSITIVE_DISCRETE_MODE,
/** Analog Comparator Negative Channel Discrete Mode Enable. */
SENSOR_ATTR_MCUX_ACMP_NEGATIVE_DISCRETE_MODE,
/** Analog Comparator discrete mode clock selection. */
SENSOR_ATTR_MCUX_ACMP_DISCRETE_CLOCK,
/** Analog Comparator resistor divider enable. */
SENSOR_ATTR_MCUX_ACMP_DISCRETE_ENABLE_RESISTOR_DIVIDER,
/** Analog Comparator discrete sample selection. */
SENSOR_ATTR_MCUX_ACMP_DISCRETE_SAMPLE_TIME,
/** Analog Comparator discrete phase1 sampling time selection. */
SENSOR_ATTR_MCUX_ACMP_DISCRETE_PHASE1_TIME,
/** Analog Comparator discrete phase2 sampling time selection. */
SENSOR_ATTR_MCUX_ACMP_DISCRETE_PHASE2_TIME,
#endif
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_MCUX_ACMP_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/mcux_acmp.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 811 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_NPM1300_CHARGER_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_NPM1300_CHARGER_H_
#include <zephyr/drivers/sensor.h>
/* NPM1300 charger specific channels */
enum sensor_channel_npm1300_charger {
SENSOR_CHAN_NPM1300_CHARGER_STATUS = SENSOR_CHAN_PRIV_START,
SENSOR_CHAN_NPM1300_CHARGER_ERROR,
};
#endif
``` | /content/code_sandbox/include/zephyr/drivers/sensor/npm1300_charger.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for AMS's TSL2591 ambient light sensor
*
* This exposes attributes for the TSL2591 which can be used for
* setting the on-chip gain, integration time, and persist filter parameters.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TSL2591_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TSL2591_H_
#include <zephyr/drivers/sensor.h>
#ifdef __cplusplus
extern "C" {
#endif
enum sensor_attribute_tsl2591 {
/* Sensor ADC Gain Mode
* Rather than set this value directly, can only be set to operate in one of four modes:
*
* TSL2591_SENSOR_GAIN_LOW
* TSL2591_SENSOR_GAIN_MED
* TSL2591_SENSOR_GAIN_HIGH
* TSL2591_SENSOR_GAIN_MAX
*
* See datasheet for actual typical gain scales these modes correspond to.
*/
SENSOR_ATTR_GAIN_MODE = SENSOR_ATTR_PRIV_START + 1,
/* Sensor ADC Integration Time (in ms)
* Can only be set to one of six values:
*
* 100, 200, 300, 400, 500, or 600
*/
SENSOR_ATTR_INTEGRATION_TIME,
/* Sensor ALS Interrupt Persist Filter
* Represents the number of consecutive sensor readings outside of a set threshold
* before triggering an interrupt. Can only be set to one of sixteen values:
*
* 0, 1, 2, 3, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60
*
* Setting this to 0 causes an interrupt to generate every ALS cycle,
* regardless of threshold.
* Setting this to 1 is equivalent to the no-persist interrupt mode.
*/
SENSOR_ATTR_INT_PERSIST
};
enum sensor_gain_tsl2591 {
TSL2591_SENSOR_GAIN_LOW,
TSL2591_SENSOR_GAIN_MED,
TSL2591_SENSOR_GAIN_HIGH,
TSL2591_SENSOR_GAIN_MAX
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TSL2591_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/tsl2591.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 486 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_ENS160_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_ENS160_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
/* Channel for Air Quality Index */
enum sensor_channel_ens160 {
SENSOR_CHAN_ENS160_AQI = SENSOR_CHAN_PRIV_START,
};
enum sensor_attribute_ens160 {
SENSOR_ATTR_ENS160_TEMP = SENSOR_ATTR_PRIV_START,
SENSOR_ATTR_ENS160_RH,
};
#ifdef __cplusplus
}
#endif
#endif
``` | /content/code_sandbox/include/zephyr/drivers/sensor/ens160.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_F75303_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_F75303_H_
#include <zephyr/drivers/sensor.h>
/* F75303 specific channels */
enum sensor_channel_f75303 {
SENSOR_CHAN_F75303_REMOTE1 = SENSOR_CHAN_PRIV_START,
SENSOR_CHAN_F75303_REMOTE2,
};
#endif
``` | /content/code_sandbox/include/zephyr/drivers/sensor/f75303.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for CCS811 Indoor Air Quality Sensor
*
* Some capabilities and operational requirements for this sensor
* cannot be expressed within the sensor driver abstraction.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_CCS811_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_CCS811_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/device.h>
#include <zephyr/drivers/sensor.h>
/* Status register fields */
#define CCS811_STATUS_ERROR BIT(0)
#define CCS811_STATUS_DATA_READY BIT(3)
#define CCS811_STATUS_APP_VALID BIT(4)
#define CCS811_STATUS_FW_MODE BIT(7)
/* Error register fields */
#define CCS811_ERROR_WRITE_REG_INVALID BIT(0)
#define CCS811_ERROR_READ_REG_INVALID BIT(1)
#define CCS811_ERROR_MEASMODE_INVALID BIT(2)
#define CCS811_ERROR_MAX_RESISTANCE BIT(3)
#define CCS811_ERROR_HEATER_FAULT BIT(4)
#define CCS811_ERROR_HEATER_SUPPLY BIT(5)
/* Measurement mode constants */
#define CCS811_MODE_IDLE 0x00
#define CCS811_MODE_IAQ_1SEC 0x10
#define CCS811_MODE_IAQ_10SEC 0x20
#define CCS811_MODE_IAQ_60SEC 0x30
#define CCS811_MODE_IAQ_250MSEC 0x40
#define CCS811_MODE_MSK 0x70
/** @brief Information collected from the sensor on each fetch. */
struct ccs811_result_type {
/** Equivalent carbon dioxide in parts-per-million volume (ppmv). */
uint16_t co2;
/**
* Equivalent total volatile organic compounds in
* parts-per-billion volume.
*/
uint16_t voc;
/** Raw voltage and current measured by sensor. */
uint16_t raw;
/** Sensor status at completion of most recent fetch. */
uint8_t status;
/**
* Sensor error flags at completion of most recent fetch.
*
* Note that errors are cleared when read.
*/
uint8_t error;
};
/**
* @brief Access storage for the most recent data read from the sensor.
*
* This content of the object referenced is updated by
* sensor_fetch_sample(), except for ccs811_result_type::mode which is
* set on driver initialization.
*
* @param dev Pointer to the sensor device
*
* @return a pointer to the result information.
*/
const struct ccs811_result_type *ccs811_result(const struct device *dev);
/**
* @brief Get information about static CCS811 state.
*
* This includes the configured operating mode as well as hardware and
* firmware versions.
*/
struct ccs811_configver_type {
uint16_t fw_boot_version;
uint16_t fw_app_version;
uint8_t hw_version;
uint8_t mode;
};
/**
* @brief Fetch operating mode and version information.
*
* @param dev Pointer to the sensor device
*
* @param ptr Pointer to where the returned information should be stored
*
* @return 0 on success, or a negative errno code on failure.
*/
int ccs811_configver_fetch(const struct device *dev,
struct ccs811_configver_type *ptr);
/**
* @brief Fetch the current value of the BASELINE register.
*
* The BASELINE register encodes data used to correct sensor readings
* based on individual device configuration and variation over time.
*
* For proper management of the BASELINE register see AN000370
* "Baseline Save and Restore on CCS811".
*
* @param dev Pointer to the sensor device
*
* @return a non-negative 16-bit register value, or a negative errno
* code on failure.
*/
int ccs811_baseline_fetch(const struct device *dev);
/**
* @brief Update the BASELINE register.
*
* For proper management of the BASELINE register see AN000370
* "Baseline Save and Restore on CCS811".
*
* @param dev Pointer to the sensor device
*
* @param baseline the value to be stored in the BASELINE register.
*
* @return 0 if successful, negative errno code if failure.
*/
int ccs811_baseline_update(const struct device *dev, uint16_t baseline);
/**
* @brief Update the ENV_DATA register.
*
* Accurate calculation of gas levels requires accurate environment
* data. Measurements are only accurate to 0.5 Cel and 0.5 %RH.
*
* @param dev Pointer to the sensor device
*
* @param temperature the current temperature at the sensor
*
* @param humidity the current humidity at the sensor
*
* @return 0 if successful, negative errno code if failure.
*/
int ccs811_envdata_update(const struct device *dev,
const struct sensor_value *temperature,
const struct sensor_value *humidity);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_CCS811_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/ccs811.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,040 |
```objective-c
/*
*
*
* Driver is developed to be used with Zephyr. And it only supports i2c interface.
*
* Author: Talha Can Havadar <havadartalha@gmail.com>
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_BMP581_USER_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_BMP581_USER_H_
#include <zephyr/drivers/sensor.h>
#define BMP5_SEA_LEVEL_PRESSURE_PA 101325
/* ODR settings */
#define BMP5_ODR_240_HZ 0x00
#define BMP5_ODR_218_5_HZ 0x01
#define BMP5_ODR_199_1_HZ 0x02
#define BMP5_ODR_179_2_HZ 0x03
#define BMP5_ODR_160_HZ 0x04
#define BMP5_ODR_149_3_HZ 0x05
#define BMP5_ODR_140_HZ 0x06
#define BMP5_ODR_129_8_HZ 0x07
#define BMP5_ODR_120_HZ 0x08
#define BMP5_ODR_110_1_HZ 0x09
#define BMP5_ODR_100_2_HZ 0x0A
#define BMP5_ODR_89_6_HZ 0x0B
#define BMP5_ODR_80_HZ 0x0C
#define BMP5_ODR_70_HZ 0x0D
#define BMP5_ODR_60_HZ 0x0E
#define BMP5_ODR_50_HZ 0x0F
#define BMP5_ODR_45_HZ 0x10
#define BMP5_ODR_40_HZ 0x11
#define BMP5_ODR_35_HZ 0x12
#define BMP5_ODR_30_HZ 0x13
#define BMP5_ODR_25_HZ 0x14
#define BMP5_ODR_20_HZ 0x15
#define BMP5_ODR_15_HZ 0x16
#define BMP5_ODR_10_HZ 0x17
#define BMP5_ODR_05_HZ 0x18
#define BMP5_ODR_04_HZ 0x19
#define BMP5_ODR_03_HZ 0x1A
#define BMP5_ODR_02_HZ 0x1B
#define BMP5_ODR_01_HZ 0x1C
#define BMP5_ODR_0_5_HZ 0x1D
#define BMP5_ODR_0_250_HZ 0x1E
#define BMP5_ODR_0_125_HZ 0x1F
/* Oversampling for temperature and pressure */
#define BMP5_OVERSAMPLING_1X 0x00
#define BMP5_OVERSAMPLING_2X 0x01
#define BMP5_OVERSAMPLING_4X 0x02
#define BMP5_OVERSAMPLING_8X 0x03
#define BMP5_OVERSAMPLING_16X 0x04
#define BMP5_OVERSAMPLING_32X 0x05
#define BMP5_OVERSAMPLING_64X 0x06
#define BMP5_OVERSAMPLING_128X 0x07
/* IIR filter for temperature and pressure */
#define BMP5_IIR_FILTER_BYPASS 0x00
#define BMP5_IIR_FILTER_COEFF_1 0x01
#define BMP5_IIR_FILTER_COEFF_3 0x02
#define BMP5_IIR_FILTER_COEFF_7 0x03
#define BMP5_IIR_FILTER_COEFF_15 0x04
#define BMP5_IIR_FILTER_COEFF_31 0x05
#define BMP5_IIR_FILTER_COEFF_63 0x06
#define BMP5_IIR_FILTER_COEFF_127 0x07
/* Custom ATTR values */
/* This is used to enable IIR config,
* keep in mind that disabling IIR back in runtime is not
* supported yet
*/
#define BMP5_ATTR_IIR_CONFIG (SENSOR_ATTR_PRIV_START + 1u)
#define BMP5_ATTR_POWER_MODE (SENSOR_ATTR_PRIV_START + 2u)
enum bmp5_powermode {
/*! Standby powermode */
BMP5_POWERMODE_STANDBY,
/*! Normal powermode */
BMP5_POWERMODE_NORMAL,
/*! Forced powermode */
BMP5_POWERMODE_FORCED,
/*! Continuous powermode */
BMP5_POWERMODE_CONTINUOUS,
/*! Deep standby powermode */
BMP5_POWERMODE_DEEP_STANDBY
};
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_BMP581_USER_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/bmp581_user.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,047 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TLE9104_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TLE9104_H_
#include <zephyr/drivers/sensor.h>
enum sensor_channel_tle9104 {
/** Open load detected, boolean with one bit per output */
SENSOR_CHAN_TLE9104_OPEN_LOAD = SENSOR_ATTR_PRIV_START,
/** Over current detected, boolean with one bit per output */
SENSOR_CHAN_TLE9104_OVER_CURRENT,
};
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TLE9104_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/tle9104.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 120 |
```objective-c
/*
*
*/
/**
* @file
* @brief Extended public API for Sensirion's SGP40 gas sensor
*
* This exposes two attributes for the SGP40 which can be used for
* setting the on-chip Temperature and Humidity compensation parameters.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_SGP40_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_SGP40_H_
#ifdef __cplusplus
extern "C" {
#endif
enum sensor_attribute_sgp40 {
/* Temperature in degC; only the integer part is used */
SENSOR_ATTR_SGP40_TEMPERATURE = SENSOR_ATTR_PRIV_START,
/* Relative Humidity in %; only the integer part is used */
SENSOR_ATTR_SGP40_HUMIDITY
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_SGP40_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/sgp40.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 181 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_VEAA_X_3_H_
#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_VEAA_X_3_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/sensor.h>
enum sensor_attribute_veaa_x_3 {
/* Set pressure setpoint value in kPa. */
SENSOR_ATTR_VEAA_X_3_SETPOINT = SENSOR_ATTR_PRIV_START,
/* Supported pressure range in kPa. val1 is minimum and val2 is maximum */
SENSOR_ATTR_VEAA_X_3_RANGE,
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_VEAA_X_3_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/sensor/veaa_x_3.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 149 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_AXP192_H_
#define ZEPHYR_INCLUDE_DRIVERS_MFD_AXP192_H_
#include <stddef.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO function type. Only one function can be configured per GPIO.
*/
enum axp192_gpio_func {
AXP192_GPIO_FUNC_INPUT = BIT(0),
AXP192_GPIO_FUNC_OUTPUT_OD = BIT(1),
AXP192_GPIO_FUNC_OUTPUT_LOW = BIT(2),
AXP192_GPIO_FUNC_LDO = BIT(3),
AXP192_GPIO_FUNC_ADC = BIT(4),
AXP192_GPIO_FUNC_PWM = BIT(5),
AXP192_GPIO_FUNC_FLOAT = BIT(6),
AXP192_GPIO_FUNC_CHARGE_CTL = BIT(7),
AXP192_GPIO_FUNC_INVALID
};
/**
* @brief Check if a given GPIO function value is valid.
*/
#define AXP192_GPIO_FUNC_VALID(func) (func < AXP192_GPIO_FUNC_INVALID)
/**
* @brief Maximum number of GPIOs supported by AXP192 PMIC.
*/
#define AXP192_GPIO_MAX_NUM 6U
/**
* @defgroup mdf_interface_axp192 MFD AXP192 interface
*
* Pins of AXP192 support several different functions. The mfd interface offers
* an API to configure and control these different functions.
*
* The 6 GPIOS are mapped as follows:
* [0]: GPIO0
* [1]: GPIO1
* [2]: GPIO2
* [3]: GPIO3
* [4]: GPIO4
* [5]: EXTEN
*
* @ingroup mfd_interfaces
* @{
*/
/**
* @brief Request a GPIO pin to be configured to a specific function. GPIO0..5
* of AXP192 feature various functions (see @ref axp192_gpio_func for details).
* A GPIO can only be used by one driver instance. Subsequential calls on the
* same GPIO will overwrite according function.
*
* @param dev axp192 mfd device
* @param client_dev client device the gpio is used in
* @param gpio GPIO to be configured (0..5)
* @param func Function to be configured (see @ref axp192_gpio_func for details)
* @retval 0 on success
* @retval -EINVAL if an invalid GPIO number is passed
* @retval -ENOTSUP if the requested function is not supported by the given
* @retval -errno in case of any bus error
*/
int mfd_axp192_gpio_func_ctrl(const struct device *dev, const struct device *client_dev,
uint8_t gpio, enum axp192_gpio_func func);
/**
* @brief Read out current configuration of a specific GPIO pin.
*
* @param dev axp192 mfd device
* @param gpio GPIO to read configuration from
* @param func Pointer to store current function configuration in.
* @return 0 on success
* @retval -EINVAL if an invalid GPIO number is passed
* @retval -errno in case of any bus error
*/
int mfd_axp192_gpio_func_get(const struct device *dev, uint8_t gpio, enum axp192_gpio_func *func);
/**
* @brief Enable pull-down on specified GPIO pin. AXP192 only supports
* pull-down on GPIO3..5. Pull-ups are not supported.
*
* @param dev axp192 mfd device
* @param gpio GPIO to control pull-downs
* @param enable true to enable, false to disable pull-down
* @retval 0 on success
* @retval -EINVAL if an invalid argument is given (e.g. invalid GPIO number)
* @retval -ENOTSUP if pull-down is not supported by the givenn GPIO
* @retval -errno in case of any bus error
*/
int mfd_axp192_gpio_pd_ctrl(const struct device *dev, uint8_t gpio, bool enable);
/**
* @brief Read out the current pull-down configuration of a specific GPIO.
*
* @param dev axp192 mfd device
* @param gpio GPIO to control pull-downs
* @param enabled Pointer to current pull-down configuration (true: pull-down
* enabled/ false: pull-down disabled)
* @retval -EINVAL if an invalid argument is given (e.g. invalid GPIO number)
* @retval -ENOTSUP if pull-down is not supported by the givenn GPIO
* @retval -errno in case of any bus error
*/
int mfd_axp192_gpio_pd_get(const struct device *dev, uint8_t gpio, bool *enabled);
/**
* @brief Read GPIO port.
*
* @param dev axp192 mfd device
* @param value Pointer to port value
* @retval 0 on success
* @retval -errno in case of any bus error
*/
int mfd_axp192_gpio_read_port(const struct device *dev, uint8_t *value);
/**
* @brief Write GPIO port.
*
* @param dev axp192 mfd device
* @param value port value
* @param mask pin mask within the port
* @retval 0 on success
* @retval -errno in case of any bus error
*/
int mfd_axp192_gpio_write_port(const struct device *dev, uint8_t value, uint8_t mask);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_AXP192_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mfd/axp192.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,185 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_AD559X_H_
#define ZEPHYR_INCLUDE_DRIVERS_MFD_AD559X_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/device.h>
#define AD559X_REG_SEQ_ADC 0x02U
#define AD559X_REG_ADC_CONFIG 0x04U
#define AD559X_REG_LDAC_EN 0x05U
#define AD559X_REG_GPIO_PULLDOWN 0x06U
#define AD559X_REG_READ_AND_LDAC 0x07U
#define AD559X_REG_GPIO_OUTPUT_EN 0x08U
#define AD559X_REG_GPIO_SET 0x09U
#define AD559X_REG_GPIO_INPUT_EN 0x0AU
#define AD559X_REG_PD_REF_CTRL 0x0BU
#define AD559X_EN_REF BIT(9)
#define AD559X_PIN_MAX 8U
/**
* @defgroup mdf_interface_ad559x MFD AD559X interface
* @ingroup mfd_interfaces
* @{
*/
/**
* @brief Check if the chip has a pointer byte map
*
* @param[in] dev Pointer to MFD device
*
* @retval true if chip has a pointer byte map, false if it has normal register map
*/
bool mfd_ad559x_has_pointer_byte_map(const struct device *dev);
/**
* @brief Read raw data from the chip
*
* @param[in] dev Pointer to MFD device
* @param[in] val Pointer to data buffer
* @param[in] len Number of bytes to be read
*
* @retval 0 if success
* @retval negative errno if failure
*/
int mfd_ad559x_read_raw(const struct device *dev, uint8_t *val, size_t len);
/**
* @brief Write raw data to chip
*
* @param[in] dev Pointer to MFD device
* @param[in] val Data to be written
* @param[in] len Number of bytes to be written
*
* @retval 0 if success
* @retval negative errno if failure
*/
int mfd_ad559x_write_raw(const struct device *dev, uint8_t *val, size_t len);
/**
* @brief Read data from provided register
*
* @param[in] dev Pointer to MFD device
* @param[in] reg Register to be read
* @param[in] reg_data Additional data passed to selected register
* @param[in] val Pointer to data buffer
*
* @retval 0 if success
* @retval negative errno if failure
*/
int mfd_ad559x_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data, uint16_t *val);
/**
* @brief Write data to provided register
*
* @param[in] dev Pointer to MFD device
* @param[in] reg Register to be written
* @param[in] val Data to be written
*
* @retval 0 if success
* @retval negative errno if failure
*/
int mfd_ad559x_write_reg(const struct device *dev, uint8_t reg, uint16_t val);
/**
* @brief Read ADC channel data from the chip
*
* @param[in] dev Pointer to MFD device
* @param[in] channel Channel to read
* @param[out] result ADC channel value read
*
* @retval 0 if success
* @retval negative errno if failure
*/
int mfd_ad559x_read_adc_chan(const struct device *dev, uint8_t channel, uint16_t *result);
/**
* @brief Write ADC channel data to the chip
*
* @param[in] dev Pointer to MFD device
* @param[in] channel Channel to write to
* @param[in] value DAC channel value
*
* @retval 0 if success
* @retval negative errno if failure
*/
int mfd_ad559x_write_dac_chan(const struct device *dev, uint8_t channel, uint16_t value);
/**
* @brief Read GPIO port from the chip
*
* @param[in] dev Pointer to MFD device
* @param[in] gpio GPIO to read
* @param[in] value DAC channel value
*
* @retval 0 if success
* @retval negative errno if failure
*/
int mfd_ad559x_gpio_port_get_raw(const struct device *dev, uint8_t gpio, uint16_t *value);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_AD559X_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mfd/ad559x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 968 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_NXP_LP_FLEXCOMM_H_
#define ZEPHYR_DRIVERS_NXP_LP_FLEXCOMM_H_
#include "fsl_lpflexcomm.h"
typedef void (*child_isr_t)(const struct device *dev);
void nxp_lp_flexcomm_setirqhandler(const struct device *dev, const struct device *child_dev,
LP_FLEXCOMM_PERIPH_T periph, child_isr_t handler);
#endif /* ZEPHYR_DRIVERS_NXP_LP_FLEXCOMM_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mfd/nxp_lp_flexcomm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_BD8LB600FS_H_
#define ZEPHYR_INCLUDE_DRIVERS_MFD_BD8LB600FS_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/device.h>
/**
* @defgroup mdf_interface_bd8lb600fs MFD BD8LB600FS interface
* @ingroup mfd_interfaces
* @{
*/
/**
* @brief set outputs
*
* @param[in] dev instance of BD8LB600FS MFD
* @param[in] values values for outputs, one bit per output
*
* @retval 0 if successful
*/
int mfd_bd8lb600fs_set_outputs(const struct device *dev, uint32_t values);
/**
* @brief get output diagnostics
*
* Fetch the current diagnostics from all instances, as multiple
* instances might be daisy chained together. Each bit in old
* and ocp_or_tsd corresponds to one output. A set bit means that the
* function is active, therefore either there is an open load, an over
* current or a too high temperature.
*
* OLD - open load
* OCP - over current protection
* TSD - thermal shutdown
*
* @param[in] dev instance of BD8LB600FS MFD
* @param[out] old open load values
* @param[out] ocp_or_tsd over current protection or thermal shutdown values
*
* @retval 0 if successful
*/
int mfd_bd8lb600fs_get_output_diagnostics(const struct device *dev, uint32_t *old,
uint32_t *ocp_or_tsd);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_BD8LB600FS_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mfd/bd8lb600fs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 381 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_MAX31790_H_
#define ZEPHYR_INCLUDE_DRIVERS_MFD_MAX31790_H_
#include <zephyr/sys/util.h>
#include <zephyr/sys/util_macro.h>
#define MAX31790_OSCILLATOR_FREQUENCY_IN_HZ 32768
#define MAX31790_PWMTARGETDUTYCYCLE_MAXIMUM ((1 << 9) - 1)
#define MAX31790_TACHTARGETCOUNT_MAXIMUM ((1 << 11) - 1)
#define MAX31790_CHANNEL_COUNT 6
#define MAX31790_RESET_TIMEOUT_IN_US 1000
#define MAX37190_REGISTER_GLOBALCONFIGURATION 0x00
#define MAX37190_REGISTER_PWMFREQUENCY 0x01
#define MAX37190_REGISTER_FANCONFIGURATION(channel) (0x02 + channel)
#define MAX31790_REGISTER_FANDYNAMICS(channel) (0x08 + channel)
#define MAX37190_REGISTER_FANFAULTSTATUS1 0x11
#define MAX37190_REGISTER_TACHCOUNTMSB(channel) (0x18 + 2 * channel)
#define MAX31790_REGISTER_PWMOUTTARGETDUTYCYCLEMSB(channel) (0x40 + 2 * channel)
#define MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel) (0x50 + 2 * channel)
#define MAX37190_GLOBALCONFIGURATION_STANDBY_BIT BIT(7)
#define MAX37190_GLOBALCONFIGURATION_RESET_BIT BIT(6)
#define MAX37190_GLOBALCONFIGURATION_BUSTIMEOUT_BIT BIT(5)
#define MAX37190_GLOBALCONFIGURATION_OSCILLATORSELECTION_BIT BIT(3)
#define MAX37190_GLOBALCONFIGURATION_I2CWATCHDOGSTATUS_BIT BIT(0)
#define MAX37190_FANXCONFIGURATION_MONITOR_BIT BIT(4)
#define MAX37190_FANXCONFIGURATION_TACHINPUTENABLED_BIT BIT(3)
#define MAX37190_FANXCONFIGURATION_LOCKEDROTOR_BIT BIT(2)
#define MAX37190_FANXCONFIGURATION_LOCKEDROTORPOLARITY_BIT BIT(1)
#define MAX37190_FANXCONFIGURATION_TACH_BIT BIT(0)
#define MAX37190_FANXCONFIGURATION_MODE_BIT BIT(7)
#define MAX37190_FANXDYNAMICS_ASYMMETRICRATEOFCHANGE_BIT BIT(1)
#define MAX37190_GLOBALCONFIGURATION_I2CWATCHDOG_LENGTH 2
#define MAX37190_GLOBALCONFIGURATION_I2CWATCHDOG_POS 1
#define MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH 3
#define MAX37190_FANXDYNAMICS_SPEEDRANGE_POS 5
#define MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_LENGTH 3
#define MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_POS 2
#define MAX37190_PWMFREQUENCY_PWM_LENGTH 4
#define MAX37190_PWMFREQUENCY_PWM4TO6_POS 4
#define MAX37190_PWMFREQUENCY_PWM1TO3_LENGTH 4
#define MAX37190_PWMFREQUENCY_PWM1TO3_POS 0
#define MAX37190_FANXCONFIGURATION_SPINUP_LENGTH 2
#define MAX37190_FANXCONFIGURATION_SPINUP_POS 5
#define MAX31790_FANXDYNAMCIS_SPEED_RANGE_GET(value) \
FIELD_GET(GENMASK(MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH + \
MAX37190_FANXDYNAMICS_SPEEDRANGE_POS - 1, \
MAX37190_FANXDYNAMICS_SPEEDRANGE_POS), \
value)
#define MAX31790_FLAG_SPEED_RANGE_GET(flags) \
FIELD_GET(GENMASK(MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH + \
PWM_MAX31790_FLAG_SPEED_RANGE_POS - 1, \
PWM_MAX31790_FLAG_SPEED_RANGE_POS), \
flags)
#define MAX31790_FLAG_PWM_RATE_OF_CHANGE_GET(flags) \
FIELD_GET(GENMASK(MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_LENGTH + \
PWM_MAX31790_FLAG_PWM_RATE_OF_CHANGE_POS - 1, \
PWM_MAX31790_FLAG_PWM_RATE_OF_CHANGE_POS), \
flags)
#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_MAX31790_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mfd/max31790.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 937 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_ADP5585_H_
#define ZEPHYR_INCLUDE_DRIVERS_MFD_ADP5585_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/device.h>
#define ADP5585_ID 0x00
#define ADP5585_INT_STATUS 0x01
#define ADP5585_STATUS 0x02
#define ADP5585_FIFO_1 0x03
#define ADP5585_FIFO_2 0x04
#define ADP5585_FIFO_3 0x05
#define ADP5585_FIFO_4 0x06
#define ADP5585_FIFO_5 0x07
#define ADP5585_FIFO_6 0x08
#define ADP5585_FIFO_7 0x09
#define ADP5585_FIFO_8 0x0A
#define ADP5585_FIFO_9 0x0B
#define ADP5585_FIFO_10 0x0C
#define ADP5585_FIFO_11 0x0D
#define ADP5585_FIFO_12 0x0E
#define ADP5585_FIFO_13 0x0F
#define ADP5585_FIFO_14 0x10
#define ADP5585_FIFO_15 0x11
#define ADP5585_FIFO_16 0x12
#define ADP5585_GPI_INT_STAT_A 0x13
#define ADP5585_GPI_INT_STAT_B 0x14
#define ADP5585_GPI_STATUS_A 0x15
#define ADP5585_GPI_STATUS_B 0x16
#define ADP5585_RPULL_CONFIG_A 0x17
#define ADP5585_RPULL_CONFIG_B 0x18
#define ADP5585_RPULL_CONFIG_C 0x19
#define ADP5585_RPULL_CONFIG_D 0x1A
#define ADP5585_GPI_INT_LEVEL_A 0x1B
#define ADP5585_GPI_INT_LEVEL_B 0x1C
#define ADP5585_GPI_EVENT_EN_A 0x1D
#define ADP5585_GPI_EVENT_EN_B 0x1E
#define ADP5585_GPI_INTERRUPT_EN_A 0x1F
#define ADP5585_GPI_INTERRUPT_EN_B 0x20
#define ADP5585_DEBOUNCE_DIS_A 0x21
#define ADP5585_DEBOUNCE_DIS_B 0x22
#define ADP5585_GPO_DATA_OUT_A 0x23
#define ADP5585_GPO_DATA_OUT_B 0x24
#define ADP5585_GPO_OUT_MODE_A 0x25
#define ADP5585_GPO_OUT_MODE_B 0x26
#define ADP5585_GPIO_DIRECTION_A 0x27
#define ADP5585_GPIO_DIRECTION_B 0x28
#define ADP5585_RESET1_EVENT_A 0x29
#define ADP5585_RESET1_EVENT_B 0x2A
#define ADP5585_RESET1_EVENT_C 0x2B
#define ADP5585_RESET2_EVENT_A 0x2C
#define ADP5585_RESET2_EVENT_B 0x2D
#define ADP5585_RESET_CFG 0x2E
#define ADP5585_PWM_OFFT_LOW 0x2F
#define ADP5585_PWM_OFFT_HIGH 0x30
#define ADP5585_PWM_ONT_LOW 0x31
#define ADP5585_PWM_ONT_HIGH 0x32
#define ADP5585_PWM_CFG 0x33
#define ADP5585_LOGIC_CFG 0x34
#define ADP5585_LOGIC_FF_CFG 0x35
#define ADP5585_LOGIC_INT_EVENT_EN 0x36
#define ADP5585_POLL_PTIME_CFG 0x37
#define ADP5585_PIN_CONFIG_A 0x38
#define ADP5585_PIN_CONFIG_B 0x39
#define ADP5585_PIN_CONFIG_C 0x3A
#define ADP5585_GENERAL_CFG 0x3B
#define ADP5585_INT_EN 0x3C
/* ID Register */
#define ADP5585_DEVICE_ID_MASK 0xF
#define ADP5585_MAN_ID_MASK 0xF
#define ADP5585_MAN_ID_SHIFT 4
#define ADP5585_MAN_ID 0x02
#define ADP5585_PWM_CFG_EN 0x1
#define ADP5585_PWM_CFG_MODE 0x2
#define ADP5585_PIN_CONFIG_R3_PWM 0x8
#define ADP5585_PIN_CONFIG_R3_MASK 0xC
#define ADP5585_GENERAL_CFG_OSC_EN 0x80
/* INT_EN and INT_STATUS Register */
#define ADP5585_INT_EVENT (1U << 0)
#define ADP5585_INT_GPI (1U << 1)
#define ADP5585_INT_OVERFLOW (1U << 2)
#define ADP5585_INT_LOGIC (1U << 4)
#define ADP5585_REG_MASK 0xFF
struct mfd_adp5585_config {
struct gpio_dt_spec reset_gpio;
struct gpio_dt_spec nint_gpio;
struct i2c_dt_spec i2c_bus;
};
struct mfd_adp5585_data {
struct k_work work;
struct k_sem lock;
const struct device *dev;
struct {
#ifdef CONFIG_GPIO_ADP5585
const struct device *gpio_dev;
#endif /* CONFIG_GPIO_ADP5585 */
} child;
struct gpio_callback int_gpio_cb;
};
/**
* @brief Forward declaration of child device interrupt
* handler
*/
#ifdef CONFIG_GPIO_ADP5585
void gpio_adp5585_irq_handler(const struct device *dev);
#endif /* CONFIG_GPIO_ADP5585 */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_AD5952_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mfd/adp5585.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,348 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_NPM1300_H_
#define ZEPHYR_INCLUDE_DRIVERS_MFD_NPM1300_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup mdf_interface_npm1300 MFD NPM1300 Interface
* @ingroup mfd_interfaces
* @{
*/
#include <stddef.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
enum mfd_npm1300_event_t {
NPM1300_EVENT_CHG_COMPLETED,
NPM1300_EVENT_CHG_ERROR,
NPM1300_EVENT_BATTERY_DETECTED,
NPM1300_EVENT_BATTERY_REMOVED,
NPM1300_EVENT_SHIPHOLD_PRESS,
NPM1300_EVENT_SHIPHOLD_RELEASE,
NPM1300_EVENT_WATCHDOG_WARN,
NPM1300_EVENT_VBUS_DETECTED,
NPM1300_EVENT_VBUS_REMOVED,
NPM1300_EVENT_GPIO0_EDGE,
NPM1300_EVENT_GPIO1_EDGE,
NPM1300_EVENT_GPIO2_EDGE,
NPM1300_EVENT_GPIO3_EDGE,
NPM1300_EVENT_GPIO4_EDGE,
NPM1300_EVENT_MAX
};
/**
* @brief Read multiple registers from npm1300
*
* @param dev npm1300 mfd device
* @param base Register base address (bits 15..8 of 16-bit address)
* @param offset Register offset address (bits 7..0 of 16-bit address)
* @param data Pointer to buffer for received data
* @param len Number of bytes to read
* @retval 0 If successful
* @retval -errno In case of any bus error (see i2c_write_read_dt())
*/
int mfd_npm1300_reg_read_burst(const struct device *dev, uint8_t base, uint8_t offset, void *data,
size_t len);
/**
* @brief Read single register from npm1300
*
* @param dev npm1300 mfd device
* @param base Register base address (bits 15..8 of 16-bit address)
* @param offset Register offset address (bits 7..0 of 16-bit address)
* @param data Pointer to buffer for received data
* @retval 0 If successful
* @retval -errno In case of any bus error (see i2c_write_read_dt())
*/
int mfd_npm1300_reg_read(const struct device *dev, uint8_t base, uint8_t offset, uint8_t *data);
/**
* @brief Write single register to npm1300
*
* @param dev npm1300 mfd device
* @param base Register base address (bits 15..8 of 16-bit address)
* @param offset Register offset address (bits 7..0 of 16-bit address)
* @param data data to write
* @retval 0 If successful
* @retval -errno In case of any bus error (see i2c_write_dt())
*/
int mfd_npm1300_reg_write(const struct device *dev, uint8_t base, uint8_t offset, uint8_t data);
/**
* @brief Write two registers to npm1300
*
* @param dev npm1300 mfd device
* @param base Register base address (bits 15..8 of 16-bit address)
* @param offset Register offset address (bits 7..0 of 16-bit address)
* @param data1 first byte of data to write
* @param data2 second byte of data to write
* @retval 0 If successful
* @retval -errno In case of any bus error (see i2c_write_dt())
*/
int mfd_npm1300_reg_write2(const struct device *dev, uint8_t base, uint8_t offset, uint8_t data1,
uint8_t data2);
/**
* @brief Update selected bits in npm1300 register
*
* @param dev npm1300 mfd device
* @param base Register base address (bits 15..8 of 16-bit address)
* @param offset Register offset address (bits 7..0 of 16-bit address)
* @param data data to write
* @param mask mask of bits to be modified
* @retval 0 If successful
* @retval -errno In case of any bus error (see i2c_write_read_dt(), i2c_write_dt())
*/
int mfd_npm1300_reg_update(const struct device *dev, uint8_t base, uint8_t offset, uint8_t data,
uint8_t mask);
/**
* @brief Write npm1300 timer register
*
* @param dev npm1300 mfd device
* @param time_ms timer value in ms
* @retval 0 If successful
* @retval -EINVAL if time value is too large
* @retval -errno In case of any bus error (see i2c_write_dt())
*/
int mfd_npm1300_set_timer(const struct device *dev, uint32_t time_ms);
/**
* @brief npm1300 full power reset
*
* @param dev npm1300 mfd device
* @retval 0 If successful
* @retval -errno In case of any bus error (see i2c_write_dt())
*/
int mfd_npm1300_reset(const struct device *dev);
/**
* @brief npm1300 hibernate
*
* Enters low power state, and wakes after specified time
*
* @param dev npm1300 mfd device
* @param time_ms timer value in ms
* @retval 0 If successful
* @retval -EINVAL if time value is too large
* @retval -errno In case of any bus error (see i2c_write_dt())
*/
int mfd_npm1300_hibernate(const struct device *dev, uint32_t time_ms);
/**
* @brief Add npm1300 event callback
*
* @param dev npm1300 mfd device
* @param callback callback
* @return 0 on success, -errno on failure
*/
int mfd_npm1300_add_callback(const struct device *dev, struct gpio_callback *callback);
/**
* @brief Remove npm1300 event callback
*
* @param dev npm1300 mfd device
* @param callback callback
* @return 0 on success, -errno on failure
*/
int mfd_npm1300_remove_callback(const struct device *dev, struct gpio_callback *callback);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_NPM1300_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mfd/npm1300.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,389 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_NCT38XX_H_
#define ZEPHYR_INCLUDE_DRIVERS_MFD_NCT38XX_H_
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Get the semaphore reference for a NCT38xx instance. Callers
* should pass the return value to k_sem_take/k_sem_give
*
* @param[in] dev Pointer to device struct of the driver instance
*
* @return Address of the semaphore
*/
struct k_sem *mfd_nct38xx_get_lock_reference(const struct device *dev);
/**
* @brief Get the I2C DT spec reference for a NCT38xx instance.
*
* @param[in] dev Pointer to device struct of the driver instance
*
* @return Address of the I2C DT spec
*/
const struct i2c_dt_spec *mfd_nct38xx_get_i2c_dt_spec(const struct device *dev);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_NCT38XX_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mfd/nct38xx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 255 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_EEPROM_FAKE_EEPROM_H_
#define ZEPHYR_INCLUDE_DRIVERS_EEPROM_FAKE_EEPROM_H_
#include <zephyr/drivers/eeprom.h>
#include <zephyr/fff.h>
#ifdef __cplusplus
extern "C" {
#endif
DECLARE_FAKE_VALUE_FUNC(int, fake_eeprom_read, const struct device *, off_t, void *, size_t);
DECLARE_FAKE_VALUE_FUNC(int, fake_eeprom_write, const struct device *, off_t, const void *, size_t);
DECLARE_FAKE_VALUE_FUNC(size_t, fake_eeprom_size, const struct device *);
size_t fake_eeprom_size_delegate(const struct device *dev);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_EEPROM_FAKE_EEPROM_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/eeprom/eeprom_fake.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 170 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_TLE9104_H_
#define ZEPHYR_INCLUDE_DRIVERS_MFD_TLE9104_H_
#include <stdbool.h>
#include <zephyr/device.h>
#define TLE9104_GPIO_COUNT 4
enum tle9104_on_state_diagnostics {
/* overtemperature */
TLE9104_ONDIAG_OT = 5,
/* overcurrent timeout */
TLE9104_ONDIAG_OCTIME = 4,
/* overtemperature during overcurrent */
TLE9104_ONDIAG_OCOT = 3,
/* short to battery */
TLE9104_ONDIAG_SCB = 2,
/* no failure */
TLE9104_ONDIAG_NOFAIL = 1,
/* no diagnosis done */
TLE9104_ONDIAG_UNKNOWN = 0,
};
enum tle9104_off_state_diagnostics {
/* short to ground */
TLE9104_OFFDIAG_SCG = 3,
/* open load */
TLE9104_OFFDIAG_OL = 2,
/* no failure */
TLE9104_OFFDIAG_NOFAIL = 1,
/* no diagnosis done */
TLE9104_OFFDIAG_UNKNOWN = 0,
};
struct gpio_tle9104_channel_diagnostics {
enum tle9104_on_state_diagnostics on: 3;
enum tle9104_off_state_diagnostics off: 2;
};
/**
* @brief get the diagnostics of the outputs
*
* @param dev instance of TLE9104
* @param diag destination where the result is written to
*
* @retval 0 If successful.
*/
int tle9104_get_diagnostics(const struct device *dev,
struct gpio_tle9104_channel_diagnostics diag[TLE9104_GPIO_COUNT]);
/**
* @brief clear the diagnostics of the outputs
*
* @param dev instance of TLE9104
*
* @retval 0 If successful.
*/
int tle9104_clear_diagnostics(const struct device *dev);
/*!
* @brief write output state
*
* @param dev instance of TLE9104
* @param state output state, each bit represents on output
*
* @retval 0 If successful.
*/
int tle9104_write_state(const struct device *dev, uint8_t state);
#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_TLE9104_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/mfd/tle9104.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 509 |
```objective-c
/*
*
*/
/**
* @file
* @brief Public APIs for the CDC ACM class driver
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_UART_CDC_ACM_H_
#define ZEPHYR_INCLUDE_DRIVERS_UART_CDC_ACM_H_
#include <errno.h>
#include <zephyr/device.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
* @typedef cdc_dte_rate_callback_t
* @brief A function that is called when the USB host changes the baud
* rate.
*
* @param dev Device struct for the CDC ACM device.
* @param rate New USB baud rate
*/
typedef void (*cdc_dte_rate_callback_t)(const struct device *dev,
uint32_t rate);
/**
* @brief Set the callback for dwDTERate SetLineCoding requests.
*
* The callback is invoked when the USB host changes the baud rate.
*
* @note This function is available only when
* CONFIG_CDC_ACM_DTE_RATE_CALLBACK_SUPPORT is enabled.
*
* @param dev CDC ACM device structure.
* @param callback Event handler.
*
* @return 0 on success.
*/
int cdc_acm_dte_rate_callback_set(const struct device *dev,
cdc_dte_rate_callback_t callback);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* ZEPHYR_INCLUDE_DRIVERS_UART_CDC_ACM_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/uart/cdc_acm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 295 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_IEEE802154_CC1200_H_
#define ZEPHYR_INCLUDE_DRIVERS_IEEE802154_CC1200_H_
#include <zephyr/device.h>
/* RF settings
*
* First 42 entries are for the 42 first registers from
* address 0x04 to 0x2D included.
* Next, the last 58 entries are for the 58 registers from
* extended address 0x00 to 0x39 included
*
* If CONFIG_IEEE802154_CC1200_RF_PRESET is not used, one will need
* to provide 'cc1200_rf_settings' with proper settings. These can
* be generated through TI's SmartRF application.
*
*/
struct cc1200_rf_registers_set {
uint32_t chan_center_freq0;
/* to fit in uint16_t, spacing is a multiple of 100 Hz,
* 12.5KHz for instance will be 125.
*/
uint16_t channel_spacing;
uint8_t registers[100];
};
#ifndef CONFIG_IEEE802154_CC1200_RF_PRESET
extern const struct cc1200_rf_registers_set cc1200_rf_settings;
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_IEEE802154_CC1200_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/ieee802154/cc1200.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 274 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_UART_SERIAL_TEST_H_
#define ZEPHYR_INCLUDE_DRIVERS_UART_SERIAL_TEST_H_
#include <errno.h>
#include <zephyr/device.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
* @brief Queues data to be read by the virtual serial port.
*
* @warning
* Use cases involving multiple writers virtual serial port must prevent
* concurrent write operations, either by preventing all writers from
* being preempted or by using a mutex to govern writes.
*
* @param dev Address of virtual serial port.
* @param data Address of data.
* @param size Data size (in bytes).
*
* @retval Number of bytes written.
*/
int serial_vnd_queue_in_data(const struct device *dev, const unsigned char *data, uint32_t size);
/**
* @brief Returns size of unread written data.
*
* @param dev Address of virtual serial port.
*
* @return Output data size (in bytes).
*/
uint32_t serial_vnd_out_data_size_get(const struct device *dev);
/**
* @brief Read data written to virtual serial port.
*
* Consumes the data, such that future calls to serial_vnd_read_out_data() will
* not include this data. Requires CONFIG_RING_BUFFER.
*
* @warning
* Use cases involving multiple reads of the data must prevent
* concurrent read operations, either by preventing all readers from
* being preempted or by using a mutex to govern reads.
*
*
* @param dev Address of virtual serial port.
* @param data Address of the output buffer. Can be NULL to discard data.
* @param size Data size (in bytes).
*
* @retval Number of bytes written to the output buffer.
*/
uint32_t serial_vnd_read_out_data(const struct device *dev, unsigned char *data, uint32_t size);
/**
* @brief Peek at data written to virtual serial port.
*
* Reads the data without consuming it. Future calls to serial_vnd_peek_out_data() or
* serial_vnd_read_out_data() will return this data again. Requires CONFIG_RING_BUFFER.
*
* @warning
* Use cases involving multiple reads of the data must prevent
* concurrent read operations, either by preventing all readers from
* being preempted or by using a mutex to govern reads.
*
*
* @param dev Address of virtual serial port.
* @param data Address of the output buffer. Cannot be NULL.
* @param size Data size (in bytes).
*
* @retval Number of bytes written to the output buffer.
*/
uint32_t serial_vnd_peek_out_data(const struct device *dev, unsigned char *data, uint32_t size);
/**
* @brief Callback called after bytes written to the virtual serial port.
*
* @param dev Address of virtual serial port.
* @param user_data User data.
*/
typedef void (*serial_vnd_write_cb_t)(const struct device *dev, void *user_data);
/**
* @brief Sets the write callback on a virtual serial port.
*
* @param dev Address of virtual serial port.
* @param callback Function to call after each write to the port.
* @param user_data Opaque data to pass to the callback.
*
*/
void serial_vnd_set_callback(const struct device *dev, serial_vnd_write_cb_t callback,
void *user_data);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* ZEPHYR_INCLUDE_DRIVERS_UART_SERIAL_TEST_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/uart/serial_test.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 727 |
```objective-c
/*
*
*/
#include <zephyr/drivers/flash.h>
enum stm32_ex_ops {
/*
* STM32 sector write protection control.
*
* As an input this operation takes a structure with two sector masks,
* first mask is used to enable protection on sectors, while second mask
* is used to do the opposite. If both masks are 0, then protection will
* remain unchanged. If same sector is set on both masks, protection
* will be enabled.
*
* As an output, sector mask with enabled protection is returned.
* Input can be NULL if we only want to get protected sectors.
* Output can be NULL if not needed.
*/
FLASH_STM32_EX_OP_SECTOR_WP = FLASH_EX_OP_VENDOR_BASE,
/*
* STM32 sector readout protection control.
*
* As an input this operation takes structure with information about
* desired RDP state. As an output the status after applying changes
* is returned.
*/
FLASH_STM32_EX_OP_RDP,
/*
* STM32 block option register.
*
* This operation causes option register to be locked until next boot.
* After calling, it's not possible to change option bytes (WP, RDP,
* user bytes).
*/
FLASH_STM32_EX_OP_BLOCK_OPTION_REG,
/*
* STM32 block control register.
*
* This operation causes control register to be locked until next boot.
* After calling, it's not possible to perform basic operation like
* erasing or writing.
*/
FLASH_STM32_EX_OP_BLOCK_CONTROL_REG,
};
#if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
struct flash_stm32_ex_op_sector_wp_in {
uint32_t enable_mask;
uint32_t disable_mask;
};
struct flash_stm32_ex_op_sector_wp_out {
uint32_t protected_mask;
};
#endif /* CONFIG_FLASH_STM32_WRITE_PROTECT */
#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
struct flash_stm32_ex_op_rdp {
bool enable;
bool permanent;
};
#endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
``` | /content/code_sandbox/include/zephyr/drivers/flash/stm32_flash_api_extensions.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 456 |
```objective-c
/*
*
*/
#ifndef __ZEPHYR_INCLUDE_DRIVERS_NPCX_FLASH_API_EX_H__
#define __ZEPHYR_INCLUDE_DRIVERS_NPCX_FLASH_API_EX_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/drivers/flash.h>
enum flash_npcx_ex_ops {
/*
* NPCX User Mode Access (UMA) mode execution.
*
* Execute a SPI transaction via User Mode Access (UMA) mode. Users can
* perform a customized SPI transaction to gread or write the device's
* configuration such as status registers of nor flash, power on/off,
* and so on.
*/
FLASH_NPCX_EX_OP_EXEC_UMA = FLASH_EX_OP_VENDOR_BASE,
/*
* NPCX Configure specific operation for Quad-SPI nor flash.
*
* It configures specific operation for Quad-SPI nor flash such as lock
* or unlock UMA mode, set write protection pin of internal flash, and
* so on.
*/
FLASH_NPCX_EX_OP_SET_QSPI_OPER,
/*
* NPCX Get specific operation for Quad-SPI nor flash.
*
* It returns current specific operation for Quad-SPI nor flash.
*/
FLASH_NPCX_EX_OP_GET_QSPI_OPER,
};
/* Structures used by FLASH_NPCX_EX_OP_EXEC_UMA */
struct npcx_ex_ops_uma_in {
uint8_t opcode;
uint8_t *tx_buf;
size_t tx_count;
uint32_t addr;
size_t addr_count;
size_t rx_count;
};
struct npcx_ex_ops_uma_out {
uint8_t *rx_buf;
};
/* Structures used by FLASH_NPCX_EX_OP_SET_QSPI_OPER */
struct npcx_ex_ops_qspi_oper_in {
bool enable;
uint32_t mask;
};
/* Structures used by FLASH_NPCX_EX_OP_GET_QSPI_OPER */
struct npcx_ex_ops_qspi_oper_out {
uint32_t oper;
};
/* Specific NPCX QSPI devices control bits */
#define NPCX_EX_OP_LOCK_UMA BIT(0) /* Lock/Unlock UMA mode */
#define NPCX_EX_OP_INT_FLASH_WP BIT(1) /* Issue write protection of internal flash */
#ifdef __cplusplus
}
#endif
#endif /* __ZEPHYR_INCLUDE_DRIVERS_NPCX_FLASH_API_EX_H__ */
``` | /content/code_sandbox/include/zephyr/drivers/flash/npcx_flash_api_ex.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 488 |
```objective-c
/*
*
*/
#ifndef __ZEPHYR_INCLUDE_DRIVERS_FLASH_NRF_QSPI_NOR_H__
#define __ZEPHYR_INCLUDE_DRIVERS_FLASH_NRF_QSPI_NOR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Specifies whether XIP (execute in place) operation should be possible
*
* Normally, the driver deactivates the QSPI peripheral for periods when
* no QSPI operation is performed. This is done to avoid increased current
* consumption when the peripheral is idle. For the same reason, the base
* clock on nRF53 Series SoCs (HFCLK192M) is configured for those periods
* with the default /4 divider that cannot be used otherwise. However, when
* XIP accesses are used, the driver must be prevented from doing both these
* things as that would make XIP to fail. Hence, the application should use
* this function to signal to the driver that XIP accesses are expected to
* occur so that it keeps the QSPI peripheral operable. When XIP operation
* is no longer needed, it should be disabled with this function.
*
* @param dev flash device
* @param enable if true, the driver enables XIP operation and suppresses
* idle actions that would make XIP to fail
*/
__syscall void nrf_qspi_nor_xip_enable(const struct device *dev, bool enable);
#ifdef __cplusplus
}
#endif
#include <zephyr/syscalls/nrf_qspi_nor.h>
#endif /* __ZEPHYR_INCLUDE_DRIVERS_FLASH_NRF_QSPI_NOR_H__ */
``` | /content/code_sandbox/include/zephyr/drivers/flash/nrf_qspi_nor.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 341 |
```objective-c
/*
*
*/
#ifndef __ZEPHYR_INCLUDE_DRIVERS__FLASH_SIMULATOR_H__
#define __ZEPHYR_INCLUDE_DRIVERS__FLASH_SIMULATOR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file
* @brief Flash simulator specific API.
*
* Extension for flash simulator.
*/
/**
* @brief Obtain a pointer to the RAM buffer used but by the simulator
*
* This function allows the caller to get the address and size of the RAM buffer
* in which the flash simulator emulates its flash memory content.
*
* @param[in] dev flash simulator device pointer.
* @param[out] mock_size size of the ram buffer.
*
* @retval pointer to the ram buffer
*/
__syscall void *flash_simulator_get_memory(const struct device *dev,
size_t *mock_size);
#ifdef __cplusplus
}
#endif
#include <zephyr/syscalls/flash_simulator.h>
#endif /* __ZEPHYR_INCLUDE_DRIVERS__FLASH_SIMULATOR_H__ */
``` | /content/code_sandbox/include/zephyr/drivers/flash/flash_simulator.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 210 |
```objective-c
/*
*
*/
/**
* @file
* @brief SCMI SHMEM API
*/
#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_
#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_
#include <zephyr/device.h>
#include <zephyr/arch/cpu.h>
#include <errno.h>
#define SCMI_SHMEM_CHAN_STATUS_BUSY_BIT BIT(0)
#define SCMI_SHMEM_CHAN_FLAG_IRQ_BIT BIT(0)
struct scmi_message;
/**
* @brief Write a message in the SHMEM area
*
* @param shmem pointer to shmem device
* @param msg message to write
*
* @retval 0 if successful
* @retval negative errno if failure
*/
int scmi_shmem_write_message(const struct device *shmem,
struct scmi_message *msg);
/**
* @brief Read a message from a SHMEM area
*
* @param shmem pointer to shmem device
* @param msg message to write the data into
*
* @retval 0 if successful
* @retval negative errno if failure
*/
int scmi_shmem_read_message(const struct device *shmem,
struct scmi_message *msg);
/**
* @brief Update the channel flags
*
* @param shmem pointer to shmem device
* @param mask value to negate and bitwise-and the old
* channel flags value
* @param val value to bitwise and with the mask and
* bitwise-or with the masked old value
*/
void scmi_shmem_update_flags(const struct device *shmem,
uint32_t mask, uint32_t val);
/**
* @brief Read a channel's status
*
* @param shmem pointer to shmem device
*/
uint32_t scmi_shmem_channel_status(const struct device *shmem);
#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/firmware/scmi/shmem.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 400 |
```objective-c
/*
*
*/
/**
* @file
* @brief SCMI protocol generic functions and structures
*/
#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PROTOCOL_H_
#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PROTOCOL_H_
#include <zephyr/device.h>
#include <zephyr/drivers/firmware/scmi/util.h>
#include <stdint.h>
#include <errno.h>
/**
* @brief Build an SCMI message header
*
* Builds an SCMI message header based on the
* fields that make it up.
*
* @param id message ID
* @param type message type
* @param proto protocol ID
* @param token message token
*/
#define SCMI_MESSAGE_HDR_MAKE(id, type, proto, token) \
(SCMI_FIELD_MAKE(id, GENMASK(7, 0), 0) | \
SCMI_FIELD_MAKE(type, GENMASK(1, 0), 8) | \
SCMI_FIELD_MAKE(proto, GENMASK(7, 0), 10) | \
SCMI_FIELD_MAKE(token, GENMASK(9, 0), 18))
struct scmi_channel;
/**
* @brief SCMI message type
*/
enum scmi_message_type {
/** command message */
SCMI_COMMAND = 0x0,
/** delayed reply message */
SCMI_DELAYED_REPLY = 0x2,
/** notification message */
SCMI_NOTIFICATION = 0x3,
};
/**
* @brief SCMI status codes
*/
enum scmi_status_code {
SCMI_SUCCESS = 0,
SCMI_NOT_SUPPORTED = -1,
SCMI_INVALID_PARAMETERS = -2,
SCMI_DENIED = -3,
SCMI_NOT_FOUND = -4,
SCMI_OUT_OF_RANGE = -5,
SCMI_BUSY = -6,
SCMI_COMMS_ERROR = -7,
SCMI_GENERIC_ERROR = -8,
SCMI_HARDWARE_ERROR = -9,
SCMI_PROTOCOL_ERROR = -10,
SCMI_IN_USE = -11,
};
/**
* @struct scmi_protocol
*
* @brief SCMI protocol structure
*/
struct scmi_protocol {
/** protocol ID */
uint32_t id;
/** TX channel */
struct scmi_channel *tx;
/** transport layer device */
const struct device *transport;
/** protocol private data */
void *data;
};
/**
* @struct scmi_message
*
* @brief SCMI message structure
*/
struct scmi_message {
uint32_t hdr;
uint32_t len;
void *content;
};
/**
* @brief Convert an SCMI status code to its Linux equivalent (if possible)
*
* @param scmi_status SCMI status code as shown in `enum scmi_status_code`
*
* @retval Linux equivalent status code
*/
int scmi_status_to_errno(int scmi_status);
/**
* @brief Send an SCMI message and wait for its reply
*
* Blocking function used to send an SCMI message over
* a given channel and wait for its reply
*
* @param proto pointer to SCMI protocol
* @param msg pointer to SCMI message to send
* @param reply pointer to SCMI message in which the reply is to be
* written
*
* @retval 0 if successful
* @retval negative errno if failure
*/
int scmi_send_message(struct scmi_protocol *proto,
struct scmi_message *msg, struct scmi_message *reply);
#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PROTOCOL_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/firmware/scmi/protocol.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 733 |
```objective-c
/*
*
*/
/**
* @file
* @brief ARM SCMI utility header
*
* Contains various utility macros and macros used for protocol and
* transport "registration".
*/
#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_UTIL_H_
#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_UTIL_H_
/**
* @brief Build protocol name from its ID
*
* Given a protocol ID, this macro builds the protocol
* name. This is done by concatenating the scmi_protocol_
* construct with the given protocol ID.
*
* @param proto protocol ID in decimal format
*
* @return protocol name
*/
#define SCMI_PROTOCOL_NAME(proto) CONCAT(scmi_protocol_, proto)
#ifdef CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS
#ifdef CONFIG_ARM_SCMI_MAILBOX_TRANSPORT
/** @brief Check if a protocol node has an associated channel
*
* This macro, when applied to a protocol node, checks if
* the node has a dedicated static channel allocated to it.
* This definition is specific to the mailbox driver and
* each new transport layer driver should define its own
* version of this macro based on the devicetree properties
* that indicate the presence of a dedicated channel.
*
* @param node_id protocol node identifier
* @idx channel index. Should be 0 for TX channels and 1 for
* RX channels
*/
#define DT_SCMI_TRANSPORT_PROTO_HAS_CHAN(node_id, idx)\
DT_PROP_HAS_IDX(node_id, shmem, idx)
#else /* CONFIG_ARM_SCMI_MAILBOX_TRANSPORT */
#error "Transport with static channels needs to define HAS_CHAN macro"
#endif /* CONFIG_ARM_SCMI_MAILBOX_TRANSPORT */
#define SCMI_TRANSPORT_CHAN_NAME(proto, idx) CONCAT(scmi_channel_, proto, _, idx)
/**
* @brief Declare a TX SCMI channel
*
* Given a node_id for a protocol, this macro declares the SCMI
* TX channel statically bound to said protocol via the "extern"
* qualifier. This is useful when the transport layer driver
* supports static channels since all channel structures are
* defined inside the transport layer driver.
*
* @param node_id protocol node identifier
*/
#define DT_SCMI_TRANSPORT_TX_CHAN_DECLARE(node_id) \
COND_CODE_1(DT_SCMI_TRANSPORT_PROTO_HAS_CHAN(node_id, 0), \
(extern struct scmi_channel \
SCMI_TRANSPORT_CHAN_NAME(DT_REG_ADDR(node_id), 0);), \
(extern struct scmi_channel \
SCMI_TRANSPORT_CHAN_NAME(SCMI_PROTOCOL_BASE, 0);)) \
/**
* @brief Declare SCMI TX/RX channels
*
* Given a node_id for a protocol, this macro declares the
* SCMI TX and RX channels statically bound to said protocol via
* the "extern" qualifier. Since RX channels are currently not
* supported, this is equivalent to DT_SCMI_TRANSPORT_TX_CHAN_DECLARE().
* Despite this, users should opt for this macro instead of the TX-specific
* one.
*
* @param node_id protocol node identifier
*/
#define DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) \
DT_SCMI_TRANSPORT_TX_CHAN_DECLARE(node_id) \
/**
* @brief Declare SCMI TX/RX channels using node instance number
*
* Same as DT_SCMI_TRANSPORT_CHANNELS_DECLARE() but uses the
* protocol's node instance number and the DT_DRV_COMPAT macro.
*
* @param protocol node instance number
*/
#define DT_INST_SCMI_TRANSPORT_CHANNELS_DECLARE(inst) \
DT_SCMI_TRANSPORT_CHANNELS_DECLARE(DT_INST(inst, DT_DRV_COMPAT))
/**
* @brief Get a reference to a protocol's SCMI TX channel
*
* Given a node_id for a protocol, this macro returns a
* reference to an SCMI TX channel statically bound to said
* protocol.
*
* @param node_id protocol node identifier
*
* @return reference to the struct scmi_channel of the TX channel
* bound to the protocol identifier by node_id
*/
#define DT_SCMI_TRANSPORT_TX_CHAN(node_id) \
COND_CODE_1(DT_SCMI_TRANSPORT_PROTO_HAS_CHAN(node_id, 0), \
(&SCMI_TRANSPORT_CHAN_NAME(DT_REG_ADDR(node_id), 0)), \
(&SCMI_TRANSPORT_CHAN_NAME(SCMI_PROTOCOL_BASE, 0)))
/**
* @brief Define an SCMI channel for a protocol
*
* This macro defines a struct scmi_channel for a given protocol.
* This should be used by the transport layer driver to statically
* define SCMI channels for the protocols.
*
* @param node_id protocol node identifier
* @param idx channel index. Should be 0 for TX channels and 1
* for RX channels
* @param proto protocol ID in decimal format
*/
#define DT_SCMI_TRANSPORT_CHAN_DEFINE(node_id, idx, proto, pdata) \
struct scmi_channel SCMI_TRANSPORT_CHAN_NAME(proto, idx) = \
{ \
.data = pdata, \
}
/**
* @brief Define an SCMI protocol's data
*
* Each SCMI protocol is identified by a struct scmi_protocol
* placed in a linker section called scmi_protocol. Each protocol
* driver is required to use this macro for "registration". Using
* this macro directly is higly discouraged and users should opt
* for macros such as DT_SCMI_PROTOCOL_DEFINE_NODEV() or
* DT_SCMI_PROTOCOL_DEFINE(), which also takes care of the static
* channel declaration (if applicable).
*
* @param node_id protocol node identifier
* @param proto protocol ID in decimal format
* @param pdata protocol private data
*/
#define DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, proto, pdata) \
STRUCT_SECTION_ITERABLE(scmi_protocol, SCMI_PROTOCOL_NAME(proto)) = \
{ \
.id = proto, \
.tx = DT_SCMI_TRANSPORT_TX_CHAN(node_id), \
.data = pdata, \
}
#else /* CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS */
#define DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id)
#define DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, proto, pdata) \
STRUCT_SECTION_ITERABLE(scmi_protocol, SCMI_PROTOCOL_NAME(proto)) = \
{ \
.id = proto, \
.data = pdata, \
}
#endif /* CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS */
/**
* @brief Define an SCMI transport driver
*
* This is merely a wrapper over DEVICE_DT_INST_DEFINE(), but is
* required since transport layer drivers are not allowed to place
* their own init() function in the init section. Instead, transport
* layer drivers place the scmi_core_transport_init() function in the
* init section, which, in turn, will call the transport layer driver
* init() function. This is required because the SCMI core needs to
* perform channel binding and setup during the transport layer driver's
* initialization.
*/
#define DT_INST_SCMI_TRANSPORT_DEFINE(inst, pm, data, config, level, prio, api) \
DEVICE_DT_INST_DEFINE(inst, &scmi_core_transport_init, \
pm, data, config, level, prio, api)
/**
* @brief Define an SCMI protocol
*
* This macro performs three important functions:
* 1) It defines a `struct scmi_protocol`, which is
* needed by all protocol drivers to work with the SCMI API.
*
* 2) It declares the static channels bound to the protocol.
* This is only applicable if the transport layer driver
* supports static channels.
*
* 3) It creates a `struct device` a sets the `data` field
* to the newly defined `struct scmi_protocol`. This is
* needed because the protocol driver needs to work with the
* SCMI API **and** the subsystem API.
*
* @param node_id protocol node identifier
* @param init_fn pointer to protocol's initialization function
* @param api pointer to protocol's subsystem API
* @param pm pointer to the protocol's power management resources
* @param data pointer to protocol's private data
* @param config pointer to protocol's private constant data
* @param level protocol initialization level
* @param prio protocol's priority within its initialization level
*/
#define DT_SCMI_PROTOCOL_DEFINE(node_id, init_fn, pm, data, config, \
level, prio, api) \
DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) \
DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, DT_REG_ADDR(node_id), data); \
DEVICE_DT_DEFINE(node_id, init_fn, pm, \
&SCMI_PROTOCOL_NAME(DT_REG_ADDR(node_id)), \
config, level, prio, api)
/**
* @brief Just like DT_SCMI_PROTOCOL_DEFINE(), but uses an instance
* of a `DT_DRV_COMPAT` compatible instead of a node identifier
*
* @param inst instance number
* @param ... other parameters as expected by DT_SCMI_PROTOCOL_DEFINE()
*/
#define DT_INST_SCMI_PROTOCOL_DEFINE(inst, init_fn, pm, data, config, \
level, prio, api) \
DT_SCMI_PROTOCOL_DEFINE(DT_INST(inst, DT_DRV_COMPAT), init_fn, pm, \
data, config, level, prio, api)
/**
* @brief Define an SCMI protocol with no device
*
* Variant of DT_SCMI_PROTOCOL_DEFINE(), but no `struct device` is
* created and no initialization function is called during system
* initialization. This is useful for protocols that are not really
* part of a subsystem with an API (e.g: pinctrl).
*
* @param node_id protocol node identifier
* @param data protocol private data
*/
#define DT_SCMI_PROTOCOL_DEFINE_NODEV(node_id, data) \
DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) \
DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, DT_REG_ADDR(node_id), data)
/**
* @brief Create an SCMI message field
*
* Data might not necessarily be encoded in the first
* x bits of an SCMI message parameter/return value.
* This comes in handy when building said parameters/
* return values.
*
* @param x value to encode
* @param mask value to perform bitwise-and with `x`
* @param shift value to left-shift masked `x`
*/
#define SCMI_FIELD_MAKE(x, mask, shift)\
(((uint32_t)(x) & (mask)) << (shift))
/**
* @brief SCMI protocol IDs
*
* Each SCMI protocol is identified by an ID. Each
* of these IDs needs to be in decimal since they
* might be used to build protocol and static channel
* names.
*/
#define SCMI_PROTOCOL_BASE 16
#define SCMI_PROTOCOL_POWER_DOMAIN 17
#define SCMI_PROTOCOL_SYSTEM 18
#define SCMI_PROTOCOL_PERF 19
#define SCMI_PROTOCOL_CLOCK 20
#define SCMI_PROTOCOL_SENSOR 21
#define SCMI_PROTOCOL_RESET_DOMAIN 22
#define SCMI_PROTOCOL_VOLTAGE_DOMAIN 23
#define SCMI_PROTOCOL_PCAP_MONITOR 24
#define SCMI_PROTOCOL_PINCTRL 25
#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_UTIL_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/firmware/scmi/util.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,418 |
```objective-c
/*
*
*/
/**
* @file
* @brief SCMI clock protocol helpers
*/
#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_
#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_
#include <zephyr/drivers/firmware/scmi/protocol.h>
#define SCMI_CLK_CONFIG_DISABLE_ENABLE_MASK GENMASK(1, 0)
#define SCMI_CLK_CONFIG_ENABLE_DISABLE(x)\
((uint32_t)(x) & SCMI_CLK_CONFIG_DISABLE_ENABLE_MASK)
#define SCMI_CLK_ATTRIBUTES_CLK_NUM(x) ((x) & GENMASK(15, 0))
/**
* @struct scmi_clock_config
*
* @brief Describes the parameters for the CLOCK_CONFIG_SET
* command
*/
struct scmi_clock_config {
uint32_t clk_id;
uint32_t attributes;
uint32_t extended_cfg_val;
};
/**
* @brief Clock protocol command message IDs
*/
enum scmi_clock_message {
SCMI_CLK_MSG_PROTOCOL_VERSION = 0x0,
SCMI_CLK_MSG_PROTOCOL_ATTRIBUTES = 0x1,
SCMI_CLK_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
SCMI_CLK_MSG_CLOCK_ATTRIBUTES = 0x3,
SCMI_CLK_MSG_CLOCK_DESCRIBE_RATES = 0x4,
SCMI_CLK_MSG_CLOCK_RATE_SET = 0x5,
SCMI_CLK_MSG_CLOCK_RATE_GET = 0x6,
SCMI_CLK_MSG_CLOCK_CONFIG_SET = 0x7,
SCMI_CLK_MSG_CLOCK_NAME_GET = 0x8,
SCMI_CLK_MSG_CLOCK_RATE_NOTIFY = 0x9,
SCMI_CLK_MSG_CLOCK_RATE_CHANGE_REQUESTED_NOTIFY = 0xa,
SCMI_CLK_MSG_CLOCK_CONFIG_GET = 0xb,
SCMI_CLK_MSG_CLOCK_POSSIBLE_PARENTS_GET = 0xc,
SCMI_CLK_MSG_CLOCK_PARENT_SET = 0xd,
SCMI_CLK_MSG_CLOCK_PARENT_GET = 0xe,
SCMI_CLK_MSG_CLOCK_GET_PERMISSIONS = 0xf,
SCMI_CLK_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10,
};
/**
* @brief Send the PROTOCOL_ATTRIBUTES command and get its reply
*
* @param proto pointer to SCMI clock protocol data
* @param attributes pointer to attributes to be set via
* this command
*
* @retval 0 if successful
* @retval negative errno if failure
*/
int scmi_clock_protocol_attributes(struct scmi_protocol *proto,
uint32_t *attributes);
/**
* @brief Send the CLOCK_CONFIG_SET command and get its reply
*
* @param proto pointer to SCMI clock protocol data
* @param cfg pointer to structure containing configuration
* to be set
*
* @retval 0 if successful
* @retval negative errno if failure
*/
int scmi_clock_config_set(struct scmi_protocol *proto,
struct scmi_clock_config *cfg);
/**
* @brief Query the rate of a clock
*
* @param proto pointer to SCMI clock protocol data
* @param clk_id ID of the clock for which the query is done
* @param rate pointer to rate to be set via this command
*
* @retval 0 if successful
* @retval negative errno if failure
*/
int scmi_clock_rate_get(struct scmi_protocol *proto,
uint32_t clk_id, uint32_t *rate);
#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/firmware/scmi/clk.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 705 |
```objective-c
/*
*
*/
/**
* @file
* @brief Public APIs for the SCMI transport layer drivers
*/
#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_TRANSPORT_H_
#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_TRANSPORT_H_
#include <zephyr/device.h>
#include <zephyr/sys/mutex.h>
struct scmi_message;
struct scmi_channel;
/**
* @typedef scmi_channel_cb
*
* @brief Callback function for message replies
*
* This function should be called by the transport layer
* driver whenever a reply to a previously sent message
* has been received. Its purpose is to notifying the SCMI
* core of the reply's arrival so that proper action can
* be taken.
*
* @param chan pointer to SCMI channel on which the reply
* arrived
*/
typedef void (*scmi_channel_cb)(struct scmi_channel *chan);
/**
* @struct scmi_channel
* @brief SCMI channel structure
*
* An SCMI channel is a medium through which a protocol
* is able to transmit/receive messages. Each of the SCMI
* channels is represented by a `struct scmi_channel`.
*/
struct scmi_channel {
/**
* channel lock. This is meant to be initialized
* and used only by the SCMI core to assure that
* only one protocol can send/receive messages
* through a channel at a given moment.
*/
struct k_mutex lock;
/**
* binary semaphore. This is meant to be initialized
* and used only by the SCMI core. Its purpose is to
* signal that a reply has been received.
*/
struct k_sem sem;
/** channel private data */
void *data;
/**
* callback function. This is meant to be set by
* the SCMI core and should be called by the SCMI
* transport layer driver whenever a reply has
* been received.
*/
scmi_channel_cb cb;
/** is the channel ready to be used by a protocol? */
bool ready;
};
struct scmi_transport_api {
int (*init)(const struct device *transport);
int (*send_message)(const struct device *transport,
struct scmi_channel *chan,
struct scmi_message *msg);
int (*setup_chan)(const struct device *transport,
struct scmi_channel *chan,
bool tx);
int (*read_message)(const struct device *transport,
struct scmi_channel *chan,
struct scmi_message *msg);
bool (*channel_is_free)(const struct device *transport,
struct scmi_channel *chan);
struct scmi_channel *(*request_channel)(const struct device *transport,
uint32_t proto, bool tx);
};
/**
* @brief Request an SCMI channel dynamically
*
* Whenever the SCMI transport layer driver doesn't support
* static channel allocation, the SCMI core will try to bind
* a channel to a protocol dynamically using this function.
* Note that no setup needs to be performed on the channel
* in this function as the core will also call the channel
* setup() function.
*
* @param transport pointer to the device structure for the
* transport layer
* @param proto ID of the protocol for which the core is
* requesting the channel
* @param tx true if the channel is TX, false if RX
*
* @retval pointer to SCMI channel that's to be bound
* to the protocol
* @retval NULL if operation was not successful
*/
static inline struct scmi_channel *
scmi_transport_request_channel(const struct device *transport,
uint32_t proto, bool tx)
{
const struct scmi_transport_api *api =
(const struct scmi_transport_api *)transport->api;
if (api->request_channel) {
return api->request_channel(transport, proto, tx);
}
return NULL;
}
/**
* @brief Perform initialization for the transport layer driver
*
* The transport layer driver can't be initialized directly
* (i.e via a call to its init() function) during system initialization.
* This is because the macro used to define an SCMI transport places
* `scmi_core_transport_init()` in the init section instead of the
* driver's init() function. As such, `scmi_core_transport_init()`
* needs to call this function to perfrom transport layer driver
* initialization if required.
*
* This operation is optional.
*
* @param transport pointer to the device structure for the
* transport layer
*
* @retval 0 if successful
* @retval negative errno code if failure
*/
static inline int scmi_transport_init(const struct device *transport)
{
const struct scmi_transport_api *api =
(const struct scmi_transport_api *)transport->api;
if (api->init) {
return api->init(transport);
}
return 0;
}
/**
* @brief Setup an SCMI channel
*
* Before being able to send/receive messages, an SCMI channel needs
* to be prepared, which is what this function does. If it returns
* successfully, an SCMI protocol will be able to use this channel
* to send/receive messages.
*
* @param transport pointer to the device structure for the
* transport layer
* @param chan pointer to SCMI channel to be prepared
* @param tx true if the channel is TX, false if RX
*
* @retval 0 if successful
* @retval negative errno code if failure
*/
static inline int scmi_transport_setup_chan(const struct device *transport,
struct scmi_channel *chan,
bool tx)
{
const struct scmi_transport_api *api =
(const struct scmi_transport_api *)transport->api;
if (!api || !api->setup_chan) {
return -ENOSYS;
}
return api->setup_chan(transport, chan, tx);
}
/**
* @brief Send an SCMI channel
*
* Send an SCMI message using given SCMI channel. This function is
* not allowed to block.
*
* @param transport pointer to the device structure for the
* transport layer
* @param chan pointer to SCMI channel on which the message
* is to be sent
* @param msg pointer to message the caller wishes to send
*
* @retval 0 if successful
* @retval negative errno code if failure
*/
static inline int scmi_transport_send_message(const struct device *transport,
struct scmi_channel *chan,
struct scmi_message *msg)
{
const struct scmi_transport_api *api =
(const struct scmi_transport_api *)transport->api;
if (!api || !api->send_message) {
return -ENOSYS;
}
return api->send_message(transport, chan, msg);
}
/**
* @brief Read an SCMI message
*
* @param transport pointer to the device structure for the
* transport layer
* @param chan pointer to SCMI channel on which the message
* is to be read
* @param msg pointer to message the caller wishes to read
*
* @retval 0 if successful
* @retval negative errno code if failure
*/
static inline int scmi_transport_read_message(const struct device *transport,
struct scmi_channel *chan,
struct scmi_message *msg)
{
const struct scmi_transport_api *api =
(const struct scmi_transport_api *)transport->api;
if (!api || !api->read_message) {
return -ENOSYS;
}
return api->read_message(transport, chan, msg);
}
/**
* @brief Check if an SCMI channel is free
*
* @param transport pointer to the device structure for
* the transport layer
* @param chan pointer to SCMI channel the query is to be
* performed on
*
* @retval 0 if successful
* @retval negative errno code if failure
*/
static inline bool scmi_transport_channel_is_free(const struct device *transport,
struct scmi_channel *chan)
{
const struct scmi_transport_api *api =
(const struct scmi_transport_api *)transport->api;
if (!api || !api->channel_is_free) {
return -ENOSYS;
}
return api->channel_is_free(transport, chan);
}
/**
* @brief Perfrom SCMI core initialization
*
* @param transport pointer to the device structure for
* the transport layer
*
* @retval 0 if successful
* @retval negative errno code if failure
*/
int scmi_core_transport_init(const struct device *transport);
#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_TRANSPORT_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/firmware/scmi/transport.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,814 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_LED_STRIP_TLC5971_H_
#define ZEPHYR_INCLUDE_DRIVERS_LED_STRIP_TLC5971_H_
/**
* @brief Maximum value for global brightness control, i.e 100% brightness
*/
#define TLC5971_GLOBAL_BRIGHTNESS_CONTROL_MAX 127
/**
* @brief Set the global brightness control levels for the tlc5971 strip.
*
* change will take effect on next update of the led strip
*
* @param dev LED strip device
* @param pixel global brightness values for RGB channels
* @return 0 on success, negative on error
*/
int tlc5971_set_global_brightness(const struct device *dev, struct led_rgb pixel);
#endif /* ZEPHYR_INCLUDE_DRIVERS_LED_STRIP_TLC5971_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/led_strip/tlc5971.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 170 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_POWER_ATMEL_SAM_SUPC_H_
#define ZEPHYR_INCLUDE_DRIVERS_POWER_ATMEL_SAM_SUPC_H_
#define SAM_DT_SUPC_CONTROLLER DEVICE_DT_GET(DT_NODELABEL(supc))
#define SAM_DT_SUPC_WAKEUP_SOURCE_ID(node_id) \
DT_PROP_BY_IDX(node_id, wakeup_source_id wakeup_source_id)
#define SAM_DT_INST_SUPC_WAKEUP_SOURCE_ID(inst) \
SAM_DT_SUPC_WAKEUP_SOURCE_ID(DT_DRV_INST(inst))
#endif /* ZEPHYR_INCLUDE_DRIVERS_POWER_ATMEL_SAM_SUPC_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/power/atmel_sam_supc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 133 |
```objective-c
/*
*
*/
/**
* @file
* @brief SCMI pinctrl protocol helpers
*/
#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PINCTRL_H_
#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PINCTRL_H_
#include <zephyr/drivers/firmware/scmi/protocol.h>
#define ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE (10 * 2)
#define SCMI_PINCTRL_NO_FUNCTION 0xFFFFFFFF
#define SCMI_PINCTRL_CONFIG_ATTRIBUTES(fid_valid, cfg_num, selector) \
(SCMI_FIELD_MAKE(fid_valid, BIT(1), 10) | \
SCMI_FIELD_MAKE(cfg_num, GENMASK(7, 0), 2) | \
SCMI_FIELD_MAKE(selector, GENMASK(1, 0), 0))
#define SCMI_PINCTRL_SELECTOR_PIN 0x0
#define SCMI_PINCTRL_SELECTOR_GROUP 0x1
#define SCMI_PINCTRL_ATTRIBUTES_CONFIG_NUM(attributes)\
(((attributes) & GENMASK(9, 2)) >> 2)
/**
* @brief Pinctrl protocol command message IDs
*/
enum scmi_pinctrl_message {
SCMI_PINCTRL_MSG_PROTOCOL_VERSION = 0x0,
SCMI_PINCTRL_MSG_PROTOCOL_ATTRIBUTES = 0x1,
SCMI_PINCTRL_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
SCMI_PINCTRL_MSG_PINCTRL_ATTRIBUTES = 0x3,
SCMI_PINCTRL_MSG_PINCTRL_LIST_ASSOCIATIONS = 0x4,
SCMI_PINCTRL_MSG_PINCTRL_SETTINGS_GET = 0x5,
SCMI_PINCTRL_MSG_PINCTRL_SETTINGS_CONFIGURE = 0x6,
SCMI_PINCTRL_MSG_PINCTRL_REQUEST = 0x7,
SCMI_PINCTRL_MSG_PINCTRL_RELEASE = 0x8,
SCMI_PINCTRL_MSG_PINCTRL_NAME_GET = 0x9,
SCMI_PINCTRL_MSG_PINCTRL_SET_PERMISSIONS = 0xa,
SCMI_PINCTRL_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10,
};
/**
* @brief Pinctrl configurations
*/
enum scmi_pinctrl_config {
SCMI_PINCTRL_DEFAULT = 0,
SCMI_PINCTRL_BIAS_BUS_HOLD = 1,
SCMI_PINCTRL_BIAS_DISABLE = 2,
SCMI_PINCTRL_BIAS_HIGH_Z = 3,
SCMI_PINCTRL_BIAS_PULL_UP = 4,
SCMI_PINCTRL_BIAS_PULL_DEFAULT = 5,
SCMI_PINCTRL_BIAS_PULL_DOWN = 6,
SCMI_PINCTRL_DRIVE_OPEN_DRAIN = 7,
SCMI_PINCTRL_DRIVE_OPEN_SOURCE = 8,
SCMI_PCINTRL_DRIVE_PUSH_PULL = 9,
SCMI_PCINTRL_DRIVE_STRENGTH = 10,
SCMI_PINCTRL_INPUT_DEBOUNCE = 11,
SCMI_PINCTRL_INPUT_MODE = 12,
SCMI_PINCTRL_PULL_MODE = 13,
SCMI_PINCTRL_INPUT_VALUE = 14,
SCMI_PINCTRL_INPUT_SCHMITT = 15,
SCMI_PINCTRL_LP_MODE = 16,
SCMI_PINCTRL_OUTPUT_MODE = 17,
SCMI_PINCTRL_OUTPUT_VALUE = 18,
SCMI_PINCTRL_POWER_SOURCE = 19,
SCMI_PINCTRL_SLEW_RATE = 20,
SCMI_PINCTRL_RESERVED_START = 21,
SCMI_PINCTRL_RESERVED_END = 191,
SCMI_PINCTRL_VENDOR_START = 192,
};
/**
* @struct scmi_pinctrl_settings
*
* @brief Describes the parameters for the PINCTRL_SETTINGS_CONFIGURE
* command
*/
struct scmi_pinctrl_settings {
uint32_t id;
uint32_t function;
uint32_t attributes;
uint32_t config[ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE];
};
/**
* @brief Send the PINCTRL_SETTINGS_CONFIGURE command and get its reply
*
* @param settings pointer to settings to be applied
*
* @retval 0 if successful
* @retval negative errno if failure
*/
int scmi_pinctrl_settings_configure(struct scmi_pinctrl_settings *settings);
#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PINCTRL_H_ */
``` | /content/code_sandbox/include/zephyr/drivers/firmware/scmi/pinctrl.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 860 |
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