text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32L23X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32L23X_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHB1RST_OFFSET 0x28U
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_APB2RST_OFFSET 0x0CU
/** @} */
/**
* @name Clock enable/disable definitions for peripherals
* @{
*/
/* AHB1 peripherals */
#define GD32_RESET_CRC GD32_RESET_CONFIG(AHB1RST, 6U)
#define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB1RST, 17U)
#define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB1RST, 18U)
#define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 19U)
#define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB1RST, 20U)
#define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB1RST, 22U)
/* AHB2 peripherals */
#define GD32_RESET_CAU GD32_RESET_CONFIG(AHB2RST, 1U)
#define GD32_RESET_TRNG GD32_RESET_CONFIG(AHB2RST, 3U)
/* APB1 peripherals */
#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U)
#define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U)
#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
#define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U)
#define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 8U)
#define GD32_RESET_LPTIMER GD32_RESET_CONFIG(APB1RST, 9U)
#define GD32_RESET_SLCD GD32_RESET_CONFIG(APB1RST, 10U)
#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
#define GD32_RESET_LPUART GD32_RESET_CONFIG(APB1RST, 18U)
#define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U)
#define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U)
#define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
#define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U)
#define GD32_RESET_USBD GD32_RESET_CONFIG(APB1RST, 23U)
#define GD32_RESET_I2C2 GD32_RESET_CONFIG(APB1RST, 24U)
#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
#define GD32_RESET_CTC GD32_RESET_CONFIG(APB1RST, 30U)
/* APB2 peripherals */
#define GD32_RESET_SYSCFG GD32_RESET_CONFIG(APB2RST, 0U)
#define GD32_RESET_CMP GD32_RESET_CONFIG(APB2RST, 1U)
#define GD32_RESET_ADC GD32_RESET_CONFIG(APB2RST, 9U)
#define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 11U)
#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32L23X_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/reset/gd32l23x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 887 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NXP_SYSCON_RESET_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NXP_SYSCON_RESET_COMMON_H_
#define NXP_SYSCON_RESET(offset, bit) ((offset << 16) | bit)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NXP_SYSCON_RESET_COMMON_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/reset/nxp_syscon_reset_common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H
#define NPCX_RESET_SWRST_CTL1_OFFSET 0
#define NPCX_RESET_SWRST_CTL2_OFFSET 32
#define NPCX_RESET_SWRST_CTL3_OFFSET 64
#define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0)
#define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1)
#define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2)
#define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3)
#define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4)
#define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5)
#define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6)
#define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7)
#define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8)
#define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9)
#define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10)
#define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11)
#define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12)
#define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13)
#define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14)
#define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15)
#define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16)
#define NPCX_RESET_ITIM16_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18)
#define NPCX_RESET_ITIM16_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19)
#define NPCX_RESET_ITIM16_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20)
#define NPCX_RESET_ITIM16_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21)
#define NPCX_RESET_ITIM16_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22)
#define NPCX_RESET_ITIM16_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23)
#define NPCX_RESET_ITIM32 (NPCX_RESET_SWRST_CTL1_OFFSET + 24)
#define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25)
#define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26)
#define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27)
#define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28)
#define NPCX_RESET_GDMA (NPCX_RESET_SWRST_CTL1_OFFSET + 29)
#define NPCX_RESET_FIU (NPCX_RESET_SWRST_CTL1_OFFSET + 30)
#define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0)
#define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2)
#define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3)
#define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5)
#define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6)
#define NPCX_RESET_ADC (NPCX_RESET_SWRST_CTL2_OFFSET + 7)
#define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8)
#define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9)
#define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10)
#define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11)
#define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12)
#define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13)
#define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14)
#define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15)
#define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16)
#define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17)
#define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18)
#define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19)
#define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20)
#define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21)
#define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22)
#define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23)
#define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24)
#define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25)
#define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26)
#define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27)
#define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28)
#define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29)
#define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30)
#define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31)
#define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0)
#define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1)
#define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8)
#define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9)
#define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10)
#define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11)
#define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12)
#define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13)
#define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15)
#define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16)
#define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20)
#define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22)
#define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23)
#define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24)
#define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25)
#define NPCX_RESET_ID_START NPCX_RESET_GPIO0
#define NPCX_RESET_ID_END NPCX_RESET_BBRAM
#endif
``` | /content/code_sandbox/include/zephyr/dt-bindings/reset/npcx7_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,721 |
```objective-c
/*
*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_
/* The Reset line value will be used by the reset controller driver to
* derive the register offset and the associated device bit to perform
* device assert and de-assert.
*
* The reset lines should be passed as a parameter to the resets property
* of the driver node in dtsi which will call reset-controller driver to
* assert/de-assert itself.
*
* Example: Deriving Reset Line value
* per0modrst register offset = 0x24;
* NAND RSTLINE pin = 5;
* RSTMGR_NAND_RSTLINE = (0x24 * 8) + 5 = 293
*/
#define RSTMGR_SDMCOLDRST_RSTLINE 0
#define RSTMGR_SDMWARMRST_RSTLINE 1
#define RSTMGR_SDMLASTPORRST_RSTLINE 2
#define RSTMGR_L4WD0RST_RSTLINE 16
#define RSTMGR_L4WD1RST_RSTLINE 17
#define RSTMGR_L4WD2RST_RSTLINE 18
#define RSTMGR_L4WD3RST_RSTLINE 19
#define RSTMGR_L4WD4RST_RSTLINE 20
#define RSTMGR_DEBUGRST_RSTLINE 21
#define RSTMGR_CSDAPRST_RSTLINE 22
#define RSTMGR_EMIFTIMEOUT_RSTLINE 64
#define RSTMGR_FPGAHSTIMEOUT_RSTLINE 66
#define RSTMGR_ETRSTALLTIMEOUT_RSTLINE 67
#define RSTMGR_LWSOC2FPGATIMEOUT_RSTLINE 72
#define RSTMGR_SOC2FPGATIMEOUT_RSTLINE 73
#define RSTMGR_F2SDRAMTIMEOUT_RSTLINE 74
#define RSTMGR_F2STIMEOUT_RSTLINE 75
#define RSTMGR_L3NOCDBGTIMEOUT_RSTLINE 79
#define RSTMGR_DEBUGL3NOCTIMEOUT_RSTLINE 80
#define RSTMGR_EMIF_FLUSH_RSTLINE 128
#define RSTMGR_FPGAHSEN_RSTLINE 130
#define RSTMGR_ETRSTALLEN_RSTLINE 131
#define RSTMGR_LWSOC2FPGA_FLUSH_RSTLINE 137
#define RSTMGR_SOC2FPGA_FLUSH_RSTLINE 138
#define RSTMGR_F2SDRAM_FLUSH_RSTLINE 139
#define RSTMGR_F2SOC_FLUSH_RSTLINE 140
#define RSTMGR_L3NOC_DBG_RSTLINE 144
#define RSTMGR_DEBUG_L3NOC_RSTLINE 145
#define RSTMGR_EMIF_FLUSH_REQ_RSTLINE 160
#define RSTMGR_FPGAHSREQ_RSTLINE 162
#define RSTMGR_ETRSTALLREQ_RSTLINE 163
#define RSTMGR_LWSOC2FPGA_FLUSH_REQ_RSTLINE 169
#define RSTMGR_SOC2FPGA_FLUSH_REQ_RSTLINE 170
#define RSTMGR_F2SDRAM_FLUSH_REQ_RSTLINE 171
#define RSTMGR_F2S_FLUSH_REQ_RSTLINE 172
#define RSTMGR_L3NOC_DBG_REQ_RSTLINE 176
#define RSTMGR_DEBUG_L3NOC_REQ_RSTLINE 177
#define RSTMGR_EMIF_FLUSH_ACK_RSTLINE 192
#define RSTMGR_FPGAHSACK_RSTLINE 194
#define RSTMGR_ETRSTALLACK_RSTLINE 195
#define RSTMGR_LWSOC2FPGA_FLUSH_ACK_RSTLINE 201
#define RSTMGR_SOC2FPGA_FLUSH_ACK_RSTLINE 202
#define RSTMGR_F2SDRAM_FLUSH_ACK_RSTLINE 203
#define RSTMGR_F2S_FLUSH_ACK_RSTLINE 204
#define RSTMGR_L3NOC_DBG_ACK_RSTLINE 208
#define RSTMGR_DEBUG_L3NOC_ACK_RSTLINE 209
#define RSTMGR_ETRSTALLWARMRST_RSTLINE 224
#define RSTMGR_TSN0_RSTLINE 288
#define RSTMGR_TSN1_RSTLINE 289
#define RSTMGR_TSN2_RSTLINE 290
#define RSTMGR_USB0_RSTLINE 291
#define RSTMGR_USB1_RSTLINE 292
#define RSTMGR_NAND_RSTLINE 293
#define RSTMGR_SOFTPHY_RSTLINE 294
#define RSTMGR_SDMMC_RSTLINE 295
#define RSTMGR_TSN0ECC_RSTLINE 296
#define RSTMGR_TSN1ECC_RSTLINE 297
#define RSTMGR_TSN2ECC_RSTLINE 298
#define RSTMGR_USB0ECC_RSTLINE 299
#define RSTMGR_USB1ECC_RSTLINE 300
#define RSTMGR_NANDECC_RSTLINE 301
#define RSTMGR_SDMMCECC_RSTLINE 303
#define RSTMGR_DMA_RSTLINE 304
#define RSTMGR_SPIM0_RSTLINE 305
#define RSTMGR_SPIM1_RSTLINE 306
#define RSTMGR_SPIS0_RSTLINE 307
#define RSTMGR_SPIS1_RSTLINE 308
#define RSTMGR_DMAECC_RSTLINE 309
#define RSTMGR_EMACPTP_RSTLINE 310
#define RSTMGR_DMAIF0_RSTLINE 312
#define RSTMGR_DMAIF1_RSTLINE 313
#define RSTMGR_DMAIF2_RSTLINE 314
#define RSTMGR_DMAIF3_RSTLINE 315
#define RSTMGR_DMAIF4_RSTLINE 316
#define RSTMGR_DMAIF5_RSTLINE 317
#define RSTMGR_DMAIF6_RSTLINE 318
#define RSTMGR_DMAIF7_RSTLINE 319
#define RSTMGR_WATCHDOG0_RSTLINE 320
#define RSTMGR_WATCHDOG1_RSTLINE 321
#define RSTMGR_WATCHDOG2_RSTLINE 322
#define RSTMGR_WATCHDOG3_RSTLINE 323
#define RSTMGR_L4SYSTIMER0_RSTLINE 324
#define RSTMGR_L4SYSTIMER1_RSTLINE 325
#define RSTMGR_SPTIMER0_RSTLINE 326
#define RSTMGR_SPTIMER1_RSTLINE 327
#define RSTMGR_I2C0_RSTLINE 328
#define RSTMGR_I2C1_RSTLINE 329
#define RSTMGR_I2C2_RSTLINE 330
#define RSTMGR_I2C3_RSTLINE 331
#define RSTMGR_I2C4_RSTLINE 332
#define RSTMGR_I3C0_RSTLINE 333
#define RSTMGR_I3C1_RSTLINE 334
#define RSTMGR_UART0_RSTLINE 336
#define RSTMGR_UART1_RSTLINE 337
#define RSTMGR_GPIO0_RSTLINE 344
#define RSTMGR_GPIO1_RSTLINE 345
#define RSTMGR_WATCHDOG4_RSTLINE 346
#define RSTMGR_SOC2FPGA_RSTLINE 352
#define RSTMGR_LWSOC2FPGA_RSTLINE 353
#define RSTMGR_FPGA2SOC_RSTLINE 354
#define RSTMGR_FPGA2SDRAM_RSTLINE 355
#define RSTMGR_MPFE_RSTLINE 358
#define RSTMGR_DBG_RST_RSTLINE 480
#define RSTMGR_SOC2FPGA_WARM_RSTLINE 608
#define RSTMGR_LWSOC2FPGA_WARM_RSTLINE 609
#define RSTMGR_FPGA2SOC_WARM_RSTLINE 610
#define RSTMGR_FPGA2SDRAM_WARM_RSTLINE 611
#define RSTMGR_MPFE_WARM_RSTLINE 614
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/reset/intel_socfpga_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,751 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L1_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L1_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x10
#define STM32_RESET_BUS_APB1 0x18
#define STM32_RESET_BUS_APB2 0x14
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L1_RESET_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32l1_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 110 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SAMPLES_DRIVERS_LED_B1414_H_
#define ZEPHYR_SAMPLES_DRIVERS_LED_B1414_H_
/*
* At 6 MHz: 1 bit in 166.666 ns
* 1200 ns -> 7.2 bits
* 300 ns -> 1.8 bits
* 900 ns -> 5.4 bits
*/
#define SPI_FREQ 6000000
#define ZERO_FRAME 0x60
#define ONE_FRAME 0x7C
#endif
``` | /content/code_sandbox/include/zephyr/dt-bindings/led/seagate_legend_b1414.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M46X_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M46X_RESET_H
/* Beginning of M460 BSP sys_reg.h reset module copy */
#define NUMAKER_SYS_IPRST0_PDMA0RST_Pos (2)
#define NUMAKER_SYS_IPRST0_EBIRST_Pos (3)
#define NUMAKER_SYS_IPRST0_EMAC0RST_Pos (5)
#define NUMAKER_SYS_IPRST0_SDH0RST_Pos (6)
#define NUMAKER_SYS_IPRST0_CRCRST_Pos (7)
#define NUMAKER_SYS_IPRST0_CCAPRST_Pos (8)
#define NUMAKER_SYS_IPRST0_HSUSBDRST_Pos (10)
#define NUMAKER_SYS_IPRST0_HBIRST_Pos (11)
#define NUMAKER_SYS_IPRST0_CRPTRST_Pos (12)
#define NUMAKER_SYS_IPRST0_KSRST_Pos (13)
#define NUMAKER_SYS_IPRST0_SPIMRST_Pos (14)
#define NUMAKER_SYS_IPRST0_HSUSBHRST_Pos (16)
#define NUMAKER_SYS_IPRST0_SDH1RST_Pos (17)
#define NUMAKER_SYS_IPRST0_PDMA1RST_Pos (18)
#define NUMAKER_SYS_IPRST0_CANFD0RST_Pos (20)
#define NUMAKER_SYS_IPRST0_CANFD1RST_Pos (21)
#define NUMAKER_SYS_IPRST0_CANFD2RST_Pos (22)
#define NUMAKER_SYS_IPRST0_CANFD3RST_Pos (23)
#define NUMAKER_SYS_IPRST0_BMCRST_Pos (28)
#define NUMAKER_SYS_IPRST1_GPIORST_Pos (1)
#define NUMAKER_SYS_IPRST1_TMR0RST_Pos (2)
#define NUMAKER_SYS_IPRST1_TMR1RST_Pos (3)
#define NUMAKER_SYS_IPRST1_TMR2RST_Pos (4)
#define NUMAKER_SYS_IPRST1_TMR3RST_Pos (5)
#define NUMAKER_SYS_IPRST1_ACMP01RST_Pos (7)
#define NUMAKER_SYS_IPRST1_I2C0RST_Pos (8)
#define NUMAKER_SYS_IPRST1_I2C1RST_Pos (9)
#define NUMAKER_SYS_IPRST1_I2C2RST_Pos (10)
#define NUMAKER_SYS_IPRST1_I2C3RST_Pos (11)
#define NUMAKER_SYS_IPRST1_QSPI0RST_Pos (12)
#define NUMAKER_SYS_IPRST1_SPI0RST_Pos (13)
#define NUMAKER_SYS_IPRST1_SPI1RST_Pos (14)
#define NUMAKER_SYS_IPRST1_SPI2RST_Pos (15)
#define NUMAKER_SYS_IPRST1_UART0RST_Pos (16)
#define NUMAKER_SYS_IPRST1_UART1RST_Pos (17)
#define NUMAKER_SYS_IPRST1_UART2RST_Pos (18)
#define NUMAKER_SYS_IPRST1_UART3RST_Pos (19)
#define NUMAKER_SYS_IPRST1_UART4RST_Pos (20)
#define NUMAKER_SYS_IPRST1_UART5RST_Pos (21)
#define NUMAKER_SYS_IPRST1_UART6RST_Pos (22)
#define NUMAKER_SYS_IPRST1_UART7RST_Pos (23)
#define NUMAKER_SYS_IPRST1_OTGRST_Pos (26)
#define NUMAKER_SYS_IPRST1_USBDRST_Pos (27)
#define NUMAKER_SYS_IPRST1_EADC0RST_Pos (28)
#define NUMAKER_SYS_IPRST1_I2S0RST_Pos (29)
#define NUMAKER_SYS_IPRST1_HSOTGRST_Pos (30)
#define NUMAKER_SYS_IPRST1_TRNGRST_Pos (31)
#define NUMAKER_SYS_IPRST2_SC0RST_Pos (0)
#define NUMAKER_SYS_IPRST2_SC1RST_Pos (1)
#define NUMAKER_SYS_IPRST2_SC2RST_Pos (2)
#define NUMAKER_SYS_IPRST2_I2C4RST_Pos (3)
#define NUMAKER_SYS_IPRST2_QSPI1RST_Pos (4)
#define NUMAKER_SYS_IPRST2_SPI3RST_Pos (6)
#define NUMAKER_SYS_IPRST2_SPI4RST_Pos (7)
#define NUMAKER_SYS_IPRST2_USCI0RST_Pos (8)
#define NUMAKER_SYS_IPRST2_PSIORST_Pos (10)
#define NUMAKER_SYS_IPRST2_DACRST_Pos (12)
#define NUMAKER_SYS_IPRST2_ECAP2RST_Pos (13)
#define NUMAKER_SYS_IPRST2_ECAP3RST_Pos (14)
#define NUMAKER_SYS_IPRST2_EPWM0RST_Pos (16)
#define NUMAKER_SYS_IPRST2_EPWM1RST_Pos (17)
#define NUMAKER_SYS_IPRST2_BPWM0RST_Pos (18)
#define NUMAKER_SYS_IPRST2_BPWM1RST_Pos (19)
#define NUMAKER_SYS_IPRST2_EQEI2RST_Pos (20)
#define NUMAKER_SYS_IPRST2_EQEI3RST_Pos (21)
#define NUMAKER_SYS_IPRST2_EQEI0RST_Pos (22)
#define NUMAKER_SYS_IPRST2_EQEI1RST_Pos (23)
#define NUMAKER_SYS_IPRST2_ECAP0RST_Pos (26)
#define NUMAKER_SYS_IPRST2_ECAP1RST_Pos (27)
#define NUMAKER_SYS_IPRST2_I2S1RST_Pos (29)
#define NUMAKER_SYS_IPRST2_EADC1RST_Pos (31)
#define NUMAKER_SYS_IPRST3_KPIRST_Pos (0)
#define NUMAKER_SYS_IPRST3_EADC2RST_Pos (6)
#define NUMAKER_SYS_IPRST3_ACMP23RST_Pos (7)
#define NUMAKER_SYS_IPRST3_SPI5RST_Pos (8)
#define NUMAKER_SYS_IPRST3_SPI6RST_Pos (9)
#define NUMAKER_SYS_IPRST3_SPI7RST_Pos (10)
#define NUMAKER_SYS_IPRST3_SPI8RST_Pos (11)
#define NUMAKER_SYS_IPRST3_SPI9RST_Pos (12)
#define NUMAKER_SYS_IPRST3_SPI10RST_Pos (13)
#define NUMAKER_SYS_IPRST3_UART8RST_Pos (16)
#define NUMAKER_SYS_IPRST3_UART9RST_Pos (17)
/* End of M460 BSP sys_reg.h reset module copy */
/* Beginning of M460 BSP sys.h reset module copy */
/*your_sha256_hash-----
* Module Reset Control Resister constant definitions.
*your_sha256_hash-----
*/
#define NUMAKER_PDMA0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_PDMA0RST_Pos)
#define NUMAKER_EBI_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_EBIRST_Pos)
#define NUMAKER_EMAC0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_EMAC0RST_Pos)
#define NUMAKER_SDH0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_SDH0RST_Pos)
#define NUMAKER_CRC_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CRCRST_Pos)
#define NUMAKER_CCAP_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CCAPRST_Pos)
#define NUMAKER_HSUSBD_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_HSUSBDRST_Pos)
#define NUMAKER_HBI_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_HBIRST_Pos)
#define NUMAKER_CRPT_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CRPTRST_Pos)
#define NUMAKER_KS_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_KSRST_Pos)
#define NUMAKER_SPIM_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_SPIMRST_Pos)
#define NUMAKER_HSUSBH_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_HSUSBHRST_Pos)
#define NUMAKER_SDH1_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_SDH1RST_Pos)
#define NUMAKER_PDMA1_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_PDMA1RST_Pos)
#define NUMAKER_CANFD0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CANFD0RST_Pos)
#define NUMAKER_CANFD1_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CANFD1RST_Pos)
#define NUMAKER_CANFD2_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CANFD2RST_Pos)
#define NUMAKER_CANFD3_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CANFD3RST_Pos)
#define NUMAKER_GPIO_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_GPIORST_Pos)
#define NUMAKER_TMR0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TMR0RST_Pos)
#define NUMAKER_TMR1_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TMR1RST_Pos)
#define NUMAKER_TMR2_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TMR2RST_Pos)
#define NUMAKER_TMR3_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TMR3RST_Pos)
#define NUMAKER_ACMP01_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_ACMP01RST_Pos)
#define NUMAKER_I2C0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2C0RST_Pos)
#define NUMAKER_I2C1_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2C1RST_Pos)
#define NUMAKER_I2C2_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2C2RST_Pos)
#define NUMAKER_I2C3_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2C3RST_Pos)
#define NUMAKER_QSPI0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_QSPI0RST_Pos)
#define NUMAKER_SPI0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_SPI0RST_Pos)
#define NUMAKER_SPI1_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_SPI1RST_Pos)
#define NUMAKER_SPI2_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_SPI2RST_Pos)
#define NUMAKER_UART0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART0RST_Pos)
#define NUMAKER_UART1_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART1RST_Pos)
#define NUMAKER_UART2_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART2RST_Pos)
#define NUMAKER_UART3_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART3RST_Pos)
#define NUMAKER_UART4_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART4RST_Pos)
#define NUMAKER_UART5_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART5RST_Pos)
#define NUMAKER_UART6_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART6RST_Pos)
#define NUMAKER_UART7_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART7RST_Pos)
#define NUMAKER_OTG_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_OTGRST_Pos)
#define NUMAKER_USBD_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_USBDRST_Pos)
#define NUMAKER_EADC0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_EADC0RST_Pos)
#define NUMAKER_I2S0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2S0RST_Pos)
#define NUMAKER_HSOTG_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_HSOTGRST_Pos)
#define NUMAKER_TRNG_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TRNGRST_Pos)
#define NUMAKER_SC0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SC0RST_Pos)
#define NUMAKER_SC1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SC1RST_Pos)
#define NUMAKER_SC2_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SC2RST_Pos)
#define NUMAKER_I2C4_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_I2C4RST_Pos)
#define NUMAKER_QSPI1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_QSPI1RST_Pos)
#define NUMAKER_SPI3_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SPI3RST_Pos)
#define NUMAKER_SPI4_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SPI4RST_Pos)
#define NUMAKER_USCI0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_USCI0RST_Pos)
#define NUMAKER_PSIO_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_PSIORST_Pos)
#define NUMAKER_DAC_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_DACRST_Pos)
#define NUMAKER_EPWM0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EPWM0RST_Pos)
#define NUMAKER_EPWM1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EPWM1RST_Pos)
#define NUMAKER_BPWM0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_BPWM0RST_Pos)
#define NUMAKER_BPWM1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_BPWM1RST_Pos)
#define NUMAKER_EQEI0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EQEI0RST_Pos)
#define NUMAKER_EQEI1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EQEI1RST_Pos)
#define NUMAKER_EQEI2_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EQEI2RST_Pos)
#define NUMAKER_EQEI3_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EQEI3RST_Pos)
#define NUMAKER_ECAP0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_ECAP0RST_Pos)
#define NUMAKER_ECAP1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_ECAP1RST_Pos)
#define NUMAKER_ECAP2_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_ECAP2RST_Pos)
#define NUMAKER_ECAP3_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_ECAP3RST_Pos)
#define NUMAKER_I2S1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_I2S1RST_Pos)
#define NUMAKER_EADC1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EADC1RST_Pos)
#define NUMAKER_KPI_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_KPIRST_Pos)
#define NUMAKER_EADC2_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_EADC2RST_Pos)
#define NUMAKER_ACMP23_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_ACMP23RST_Pos)
#define NUMAKER_SPI5_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI5RST_Pos)
#define NUMAKER_SPI6_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI6RST_Pos)
#define NUMAKER_SPI7_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI7RST_Pos)
#define NUMAKER_SPI8_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI8RST_Pos)
#define NUMAKER_SPI9_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI9RST_Pos)
#define NUMAKER_SPI10_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI10RST_Pos)
#define NUMAKER_UART8_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_UART8RST_Pos)
#define NUMAKER_UART9_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_UART9RST_Pos)
/* End of M460 BSP sys.h reset module copy */
#endif
``` | /content/code_sandbox/include/zephyr/dt-bindings/reset/numaker_m46x_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,821 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DT_LED_WS2812C_H_
#define ZEPHYR_DT_LED_WS2812C_H_
/*
* At 7 MHz: 1 bit in 142.86 ns
* 1090 ns -> 7.6 bits
* 300 ns -> 2.1 bits
* 790 ns -> 5.5 bits
*/
#define WS2812C_SPI_FREQ (7000000U)
#define WS2812C_ZERO_FRAME (0xC0U)
#define WS2812C_ONE_FRAME (0xFCU)
#endif
``` | /content/code_sandbox/include/zephyr/dt-bindings/led/worldsemi_ws2812c.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 132 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LED_LED_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_LED_LED_H_
/* Standard LED colors */
#define LED_COLOR_ID_WHITE 0
#define LED_COLOR_ID_RED 1
#define LED_COLOR_ID_GREEN 2
#define LED_COLOR_ID_BLUE 3
#define LED_COLOR_ID_AMBER 4
#define LED_COLOR_ID_VIOLET 5
#define LED_COLOR_ID_YELLOW 6
#define LED_COLOR_ID_IR 7
#define LED_COLOR_ID_MAX 8
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LED_LED_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/led/led.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_NXP_FLEXRAM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_NXP_FLEXRAM_H_
#define FLEXRAM_NONE 0
#define FLEXRAM_OCRAM 1
#define FLEXRAM_DTCM 2
#define FLEXRAM_ITCM 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_NXP_FLEXRAM_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/memory-controller/nxp,flexram.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
/* Number of column address bits */
#define STM32_FMC_SDRAM_NC_8 0x00000000UL
#define STM32_FMC_SDRAM_NC_9 0x00000001UL
#define STM32_FMC_SDRAM_NC_10 0x00000002UL
#define STM32_FMC_SDRAM_NC_11 0x00000003UL
/* Number of row address bits */
#define STM32_FMC_SDRAM_NR_11 0x00000000UL
#define STM32_FMC_SDRAM_NR_12 0x00000004UL
#define STM32_FMC_SDRAM_NR_13 0x00000008UL
/* Memory data bus width. */
#define STM32_FMC_SDRAM_MWID_8 0x00000000UL
#define STM32_FMC_SDRAM_MWID_16 0x00000010UL
#define STM32_FMC_SDRAM_MWID_32 0x00000020UL
/* Number of internal banks */
#define STM32_FMC_SDRAM_NB_2 0x00000000UL
#define STM32_FMC_SDRAM_NB_4 0x00000040UL
/* CAS Latency */
#define STM32_FMC_SDRAM_CAS_1 0x00000080UL
#define STM32_FMC_SDRAM_CAS_2 0x00000100UL
#define STM32_FMC_SDRAM_CAS_3 0x00000180UL
/* SDRAM clock configuration */
#define STM32_FMC_SDRAM_SDCLK_DISABLE 0x00000000UL
#define STM32_FMC_SDRAM_SDCLK_PERIOD_2 0x00000800UL
#define STM32_FMC_SDRAM_SDCLK_PERIOD_3 0x00000C00UL
/* Burst read */
#define STM32_FMC_SDRAM_RBURST_DISABLE 0x00000000UL
#define STM32_FMC_SDRAM_RBURST_ENABLE 0x00001000UL
/* Read pipe */
#define STM32_FMC_SDRAM_RPIPE_0 0x00000000UL
#define STM32_FMC_SDRAM_RPIPE_1 0x00002000UL
#define STM32_FMC_SDRAM_RPIPE_2 0x00004000UL
#endif
``` | /content/code_sandbox/include/zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 525 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
/* Data Address Bus Multiplexing */
#define STM32_FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000UL
#define STM32_FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002UL
/* Memory Type */
#define STM32_FMC_MEMORY_TYPE_SRAM 0x00000000UL
#define STM32_FMC_MEMORY_TYPE_PSRAM 0x00000004UL
#define STM32_FMC_MEMORY_TYPE_NOR 0x00000008UL
/* NORSRAM Data Width */
#define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000UL
#define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010UL
#define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020UL
/* Burst Access Mode */
#define STM32_FMC_BURST_ACCESS_MODE_DISABLE 0x00000000UL
#define STM32_FMC_BURST_ACCESS_MODE_ENABLE 0x00000100UL
/* Wait Signal Polarity */
#define STM32_FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000UL
#define STM32_FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200UL
/* Wait Timing */
#define STM32_FMC_WAIT_TIMING_BEFORE_WS 0x00000000UL
#define STM32_FMC_WAIT_TIMING_DURING_WS 0x00000800UL
/* Write Operation */
#define STM32_FMC_WRITE_OPERATION_DISABLE 0x00000000UL
#define STM32_FMC_WRITE_OPERATION_ENABLE 0x00001000UL
/* Wait Signal */
#define STM32_FMC_WAIT_SIGNAL_DISABLE 0x00000000UL
#define STM32_FMC_WAIT_SIGNAL_ENABLE 0x00002000UL
/* Extended Mode */
#define STM32_FMC_EXTENDED_MODE_DISABLE 0x00000000UL
#define STM32_FMC_EXTENDED_MODE_ENABLE 0x00004000UL
/* Asynchronous Wait */
#define STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000UL
#define STM32_FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000UL
/* Write Burst */
#define STM32_FMC_WRITE_BURST_DISABLE 0x00000000UL
#define STM32_FMC_WRITE_BURST_ENABLE 0x00080000UL
/* Continuous Clock */
#define STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000UL
#define STM32_FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000UL
/* Write FIFO */
/* Not every SoC can disable FIFO, refer to reference manual */
#define STM32_FMC_WRITE_FIFO_DISABLE 0x00200000UL
#define STM32_FMC_WRITE_FIFO_ENABLE 0x00000000UL
/* Page Size */
#define STM32_FMC_PAGE_SIZE_NONE 0x00000000UL
#define STM32_FMC_PAGE_SIZE_128 0x00010000UL
#define STM32_FMC_PAGE_SIZE_256 0x00020000UL
#define STM32_FMC_PAGE_SIZE_512 0x00030000UL
#define STM32_FMC_PAGE_SIZE_1024 0x00040000UL
/* Access Mode */
#define STM32_FMC_ACCESS_MODE_A 0x00000000UL
#define STM32_FMC_ACCESS_MODE_B 0x10000000UL
#define STM32_FMC_ACCESS_MODE_C 0x20000000UL
#define STM32_FMC_ACCESS_MODE_D 0x30000000UL
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 843 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_KEYMAP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_KEYMAP_H_
#define MATRIX_KEY(row, col, code) \
((((row) & 0xff) << 24) | (((col) & 0xff) << 16) | ((code) & 0xffff))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_KEYMAP_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/input/keymap.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_ESP32_TOUCH_SENSOR_INPUT_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_ESP32_TOUCH_SENSOR_INPUT_H_
#include <zephyr/dt-bindings/dt-util.h>
/* Touch sensor IIR filter mode */
#define ESP32_TOUCH_FILTER_MODE_IIR_4 0
#define ESP32_TOUCH_FILTER_MODE_IIR_8 1
#define ESP32_TOUCH_FILTER_MODE_IIR_16 2
#define ESP32_TOUCH_FILTER_MODE_IIR_32 3
#define ESP32_TOUCH_FILTER_MODE_IIR_64 4
#define ESP32_TOUCH_FILTER_MODE_IIR_128 5
#define ESP32_TOUCH_FILTER_MODE_IIR_256 6
#define ESP32_TOUCH_FILTER_MODE_JITTER 7
/* Touch sensor level of filter noise threshold coefficient*/
#define ESP32_TOUCH_FILTER_NOISE_THR_4_8TH 0
#define ESP32_TOUCH_FILTER_NOISE_THR_3_8TH 1
#define ESP32_TOUCH_FILTER_NOISE_THR_2_8TH 2
#define ESP32_TOUCH_FILTER_NOISE_THR_8_8TH 3
/* Touch sensor level of filter applied on the original data */
#define ESP32_TOUCH_FILTER_SMOOTH_MODE_OFF 0
#define ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_2 1
#define ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_4 2
#define ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_8 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_ESP32_TOUCH_SENSOR_INPUT_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/input/esp32-touch-sensor-input.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 339 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_CST816S_GESTURE_CODES_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_CST816S_GESTURE_CODES_H_
#define CST816S_GESTURE_CODE_NONE 0x00
#define CST816S_GESTURE_CODE_SWIPE_UP 0x01
#define CST816S_GESTURE_CODE_SWIPE_DOWN 0x02
#define CST816S_GESTURE_CODE_SWIPE_LEFT 0x03
#define CST816S_GESTURE_CODE_SWIPE_RIGHT 0x04
#define CST816S_GESTURE_CODE_SINGLE_CLICK 0x05
#define CST816S_GESTURE_CODE_DOUBLE_CLICK 0x0B
#define CST816S_GESTURE_CODE_LONG_PRESS 0x0C
#endif
``` | /content/code_sandbox/include/zephyr/dt-bindings/input/cst816s-gesture-codes.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 181 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_
/**
* @brief MIPI-DBI driver APIs
* @defgroup mipi_dbi_interface MIPI-DBI driver APIs
* @ingroup io_interfaces
* @{
*/
/**
* SPI 3 wire (Type C1). Uses 9 write clocks to send a byte of data.
* The bit sent on the 9th clock indicates whether the byte is a
* command or data byte
*
*
* .---. .---. .---. .---. .---. .---. .---. .---.
* SCK -' '---' '---' '---' '---' '---' '---' '---' '---
*
* -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.
* DOUT |D/C| D7| D6| D5| D4| D3| D2| D1| D0|D/C| D7| D6| D5| D4|...|
* -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'
* | Word 1 | Word n
*
* -. .--
* CS '-----------------------------------------------------------'
*/
#define MIPI_DBI_MODE_SPI_3WIRE 0x1
/**
* SPI 4 wire (Type C3). Uses 8 write clocks to send a byte of data.
* an additional C/D pin will be use to indicate whether the byte is a
* command or data byte
*
* .---. .---. .---. .---. .---. .---. .---. .---.
* SCK -' '---' '---' '---' '---' '---' '---' '---' '---
*
* -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.
* DOUT | D7| D6| D5| D4| D3| D2| D1| D0| D7| D6| D5| D4| D3| D2| D1| D0|
* -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'
* | Word 1 | Word n
*
* -. .--
* CS '---------------------------------------------------------------'
*
* -.-------------------------------.-------------------------------.-
* CD | D/C | D/C |
* -'-------------------------------'-------------------------------'-
*/
#define MIPI_DBI_MODE_SPI_4WIRE 0x2
/**
* Parallel Bus protocol for MIPI DBI Type A based on Motorola 6800 bus.
*
* -. .--------. .------------------------
* CS '---' '---'
*
* -------------------------------------------
* RESX
*
* .--------------------------------
* D/CX ----------'
*
*
* R/WX -------------------------------------------
*
* -------------------------------------------
* E
*
* .--------. .--------------------------.
* D[15:0]/ -| COMMAND|---| DATA |
* D[8:0]/ '--------' '--------------------------'
* D[7:0]
*
* Please refer to the MIPI DBI specification for a detailed cycle diagram.
*/
#define MIPI_DBI_MODE_6800_BUS_16_BIT 0x3
#define MIPI_DBI_MODE_6800_BUS_9_BIT 0x4
#define MIPI_DBI_MODE_6800_BUS_8_BIT 0x5
/**
* Parallel Bus protocol for MIPI DBI Type B based on Intel 8080 bus.
*
* -. .-
* CS '---------------------------------------'
*
* -------------------------------------------
* RESX
*
* --. .----------------------------
* D/CX '-----------'
*
* ---. .--------. .----------------------
* WRX '---' '---'
*
* -------------------------------------------
* RDX
*
* .--------. .--------------------------.
* D[15:0]/ ---| COMMAND|---| DATA |
* D[8:0]/ '--------' '--------------------------'
* D[7:0]
*
* Please refer to the MIPI DBI specification for a detailed cycle diagram.
*/
#define MIPI_DBI_MODE_8080_BUS_16_BIT 0x6
#define MIPI_DBI_MODE_8080_BUS_9_BIT 0x7
#define MIPI_DBI_MODE_8080_BUS_8_BIT 0x8
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,146 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_AXP192_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_AXP192_H_
/**
* @defgroup regulator_axp192 AXP192 Devicetree helpers.
* @ingroup regulator_interface
* @{
*/
/**
* @name AXP192 Regulator modes
* @{
*/
/* DCDCs */
#define AXP192_DCDC_MODE_AUTO 0x00U
#define AXP192_DCDC_MODE_PWM 0x01U
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_AXP192_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/regulator/axp192.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM6001_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM6001_H_
/**
* @defgroup regulator_npm6001 NPM6001 Devicetree helpers.
* @ingroup regulator_interface
* @{
*/
/**
* @name NPM6001 Regulator modes
* @{
*/
/** Hysteretic mode */
#define NPM6001_MODE_HYS 0
/** PWM mode */
#define NPM6001_MODE_PWM 1
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM6001_H_*/
``` | /content/code_sandbox/include/zephyr/dt-bindings/regulator/npm6001.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NXP_VREF_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NXP_VREF_H
/**
* @defgroup regulator_nxp_vref Devicetree helpers
* @ingroup regulator_interface
* @{
*/
/**
* @name NXP VREF Regulator API Modes
* @{
*/
#define NXP_VREF_MODE_STANDBY 0
#define NXP_VREF_MODE_LOW_POWER 1
#define NXP_VREF_MODE_HIGH_POWER 2
#define NXP_VREF_MODE_INTERNAL_REGULATOR 3
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NXP_VREF_H */
``` | /content/code_sandbox/include/zephyr/dt-bindings/regulator/nxp_vref.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 149 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NRF5X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NRF_H_
/**
* @defgroup regulator_nrf5x nRF5X regulator devicetree helpers.
* @ingroup regulator_interface
* @{
*/
/**
* @name nRF5X regulator modes
* @{
*/
/** LDO mode */
#define NRF5X_REG_MODE_LDO 0
/** DC/DC mode */
#define NRF5X_REG_MODE_DCDC 1
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NRF5X_H_*/
``` | /content/code_sandbox/include/zephyr/dt-bindings/regulator/nrf5x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 136 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM1100_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM1100_H_
/**
* @defgroup regulator_npm1100 NPM1100 Devicetree helpers.
* @ingroup regulator_interface
* @{
*/
/**
* @name NPM1100 Regulator modes
* @{
*/
/** Automatic mode */
#define NPM1100_MODE_AUTO 0
/** PWM mode */
#define NPM1100_MODE_PWM 1
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM1100_H_*/
``` | /content/code_sandbox/include/zephyr/dt-bindings/regulator/npm1100.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_RPI_PICO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_RPI_PICO_H_
#define REGULATOR_RPI_PICO_MODE_NORMAL 0x0
#define REGULATOR_RPI_PICO_MODE_HI_Z 0x2
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_RPI_PICO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/regulator/rpi_pico.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```objective-c
/*
*
*
* Input event codes, for codes available in Linux, use the same values as in
* path_to_url
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_INPUT_EVENT_CODES_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_INPUT_EVENT_CODES_H_
/**
* @defgroup input_events Input Event Definitions
* @ingroup input_interface
* @{
*/
/**
* @name Input event types.
* @anchor INPUT_EV_CODES
* @{
*/
#define INPUT_EV_KEY 0x01 /**< Key event */
#define INPUT_EV_REL 0x02 /**< Relative coordinate event */
#define INPUT_EV_ABS 0x03 /**< Absolute coordinate event */
#define INPUT_EV_MSC 0x04 /**< Miscellaneous event */
#define INPUT_EV_DEVICE 0xef /**< Device specific input event */
#define INPUT_EV_VENDOR_START 0xf0 /**< Vendor specific event start */
#define INPUT_EV_VENDOR_STOP 0xff /**< Vendor specific event stop */
/** @} */
/**
* @name Input event KEY codes.
* @anchor INPUT_KEY_CODES
* @{
*/
#define INPUT_KEY_RESERVED 0 /**< Reserved, do not use */
#define INPUT_KEY_0 11 /**< 0 Key */
#define INPUT_KEY_1 2 /**< 1 Key */
#define INPUT_KEY_2 3 /**< 2 Key */
#define INPUT_KEY_3 4 /**< 3 Key */
#define INPUT_KEY_4 5 /**< 4 Key */
#define INPUT_KEY_5 6 /**< 5 Key */
#define INPUT_KEY_6 7 /**< 6 Key */
#define INPUT_KEY_7 8 /**< 7 Key */
#define INPUT_KEY_8 9 /**< 8 Key */
#define INPUT_KEY_9 10 /**< 9 Key */
#define INPUT_KEY_A 30 /**< A Key */
#define INPUT_KEY_APOSTROPHE 40 /**< Apostrophe Key */
#define INPUT_KEY_B 48 /**< B Key */
#define INPUT_KEY_BACK 158 /**< Back Key */
#define INPUT_KEY_BACKSLASH 43 /**< Backslash Key */
#define INPUT_KEY_BACKSPACE 14 /**< Backspace Key */
#define INPUT_KEY_BLUETOOTH 237 /**< Bluetooth Key */
#define INPUT_KEY_BRIGHTNESSDOWN 224 /**< Brightness Up Key */
#define INPUT_KEY_BRIGHTNESSUP 225 /**< Brightneess Down Key */
#define INPUT_KEY_C 46 /**< C Key */
#define INPUT_KEY_CAPSLOCK 58 /**< Caps Lock Key */
#define INPUT_KEY_COFFEE 152 /**< Screen Saver Key */
#define INPUT_KEY_COMMA 51 /**< Comma Key */
#define INPUT_KEY_COMPOSE 127 /**< Compose Key */
#define INPUT_KEY_CONNECT 218 /**< Connect Key */
#define INPUT_KEY_D 32 /**< D Key */
#define INPUT_KEY_DELETE 111 /**< Delete Key */
#define INPUT_KEY_DOT 52 /**< Dot Key */
#define INPUT_KEY_DOWN 108 /**< Down Key */
#define INPUT_KEY_E 18 /**< E Key */
#define INPUT_KEY_END 107 /**< End Key */
#define INPUT_KEY_ENTER 28 /**< Enter Key */
#define INPUT_KEY_EQUAL 13 /**< Equal Key */
#define INPUT_KEY_ESC 1 /**< Escape Key */
#define INPUT_KEY_F 33 /**< F Key */
#define INPUT_KEY_F1 59 /**< F1 Key */
#define INPUT_KEY_F10 68 /**< F10 Key */
#define INPUT_KEY_F11 87 /**< F11 Key */
#define INPUT_KEY_F12 88 /**< F12 Key */
#define INPUT_KEY_F13 183 /**< F13 Key */
#define INPUT_KEY_F14 184 /**< F14 Key */
#define INPUT_KEY_F15 185 /**< F15 Key */
#define INPUT_KEY_F16 186 /**< F16 Key */
#define INPUT_KEY_F17 187 /**< F17 Key */
#define INPUT_KEY_F18 188 /**< F18 Key */
#define INPUT_KEY_F19 189 /**< F19 Key */
#define INPUT_KEY_F2 60 /**< F2 Key */
#define INPUT_KEY_F20 190 /**< F20 Key */
#define INPUT_KEY_F21 191 /**< F21 Key */
#define INPUT_KEY_F22 192 /**< F22 Key */
#define INPUT_KEY_F23 193 /**< F23 Key */
#define INPUT_KEY_F24 194 /**< F24 Key */
#define INPUT_KEY_F3 61 /**< F3 Key */
#define INPUT_KEY_F4 62 /**< F4 Key */
#define INPUT_KEY_F5 63 /**< F5 Key */
#define INPUT_KEY_F6 64 /**< F6 Key */
#define INPUT_KEY_F7 65 /**< F7 Key */
#define INPUT_KEY_F8 66 /**< F8 Key */
#define INPUT_KEY_F9 67 /**< F9 Key */
#define INPUT_KEY_FASTFORWARD 208 /**< Fast Forward Key */
#define INPUT_KEY_FORWARD 159 /**< Forward Key */
#define INPUT_KEY_G 34 /**< G Key */
#define INPUT_KEY_GRAVE 41 /**< Grave (backtick) Key */
#define INPUT_KEY_H 35 /**< H Key */
#define INPUT_KEY_HOME 102 /**< Home Key */
#define INPUT_KEY_I 23 /**< I Key */
#define INPUT_KEY_INSERT 110 /**< Insert Key */
#define INPUT_KEY_J 36 /**< J Key */
#define INPUT_KEY_K 37 /**< K Key */
#define INPUT_KEY_KP0 82 /**< Keypad 0 Key */
#define INPUT_KEY_KP1 79 /**< Keypad 1 Key */
#define INPUT_KEY_KP2 80 /**< Keypad 2 Key */
#define INPUT_KEY_KP3 81 /**< Keypad 3 Key */
#define INPUT_KEY_KP4 75 /**< Keypad 4 Key */
#define INPUT_KEY_KP5 76 /**< Keypad 5 Key */
#define INPUT_KEY_KP6 77 /**< Keypad 6 Key */
#define INPUT_KEY_KP7 71 /**< Keypad 7 Key */
#define INPUT_KEY_KP8 72 /**< Keypad 8 Key */
#define INPUT_KEY_KP9 73 /**< Keypad 9 Key */
#define INPUT_KEY_KPASTERISK 55 /**< Keypad Asterisk Key */
#define INPUT_KEY_KPCOMMA 121 /**< Keypad Comma Key */
#define INPUT_KEY_KPDOT 83 /**< Keypad Dot Key */
#define INPUT_KEY_KPENTER 96 /**< Keypad Enter Key */
#define INPUT_KEY_KPEQUAL 117 /**< Keypad Equal Key */
#define INPUT_KEY_KPMINUS 74 /**< Keypad Minus Key */
#define INPUT_KEY_KPPLUS 78 /**< Keypad Plus Key */
#define INPUT_KEY_KPPLUSMINUS 118 /**< Keypad Plus Key */
#define INPUT_KEY_KPSLASH 98 /**< Keypad Slash Key */
#define INPUT_KEY_L 38 /**< L Key */
#define INPUT_KEY_LEFT 105 /**< Left Key */
#define INPUT_KEY_LEFTALT 56 /**< Left Alt Key */
#define INPUT_KEY_LEFTBRACE 26 /**< Left Brace Key */
#define INPUT_KEY_LEFTCTRL 29 /**< Left Ctrl Key */
#define INPUT_KEY_LEFTMETA 125 /**< Left Meta Key */
#define INPUT_KEY_LEFTSHIFT 42 /**< Left Shift Key */
#define INPUT_KEY_M 50 /**< M Key */
#define INPUT_KEY_MENU 139 /**< Menu Key */
#define INPUT_KEY_MINUS 12 /**< Minus Key */
#define INPUT_KEY_MUTE 113 /**< Mute Key */
#define INPUT_KEY_N 49 /**< N Key */
#define INPUT_KEY_NUMLOCK 69 /**< Num Lock Key */
#define INPUT_KEY_O 24 /**< O Key */
#define INPUT_KEY_P 25 /**< P Key */
#define INPUT_KEY_PAGEDOWN 109 /**< Page Down Key */
#define INPUT_KEY_PAGEUP 104 /**< Page UpKey */
#define INPUT_KEY_PAUSE 119 /**< Pause Key */
#define INPUT_KEY_PLAY 207 /**< Play Key */
#define INPUT_KEY_POWER 116 /**< Power Key */
#define INPUT_KEY_PRINT 210 /**< Print Key */
#define INPUT_KEY_Q 16 /**< Q Key */
#define INPUT_KEY_R 19 /**< R Key */
#define INPUT_KEY_RIGHT 106 /**< Right Key */
#define INPUT_KEY_RIGHTALT 100 /**< Right Alt Key */
#define INPUT_KEY_RIGHTBRACE 27 /**< Right Brace Key */
#define INPUT_KEY_RIGHTCTRL 97 /**< Right Ctrl Key */
#define INPUT_KEY_RIGHTMETA 126 /**< Right Meta Key */
#define INPUT_KEY_RIGHTSHIFT 54 /**< Right Shift Key */
#define INPUT_KEY_S 31 /**< S Key */
#define INPUT_KEY_SCALE 120 /**< Scale Key */
#define INPUT_KEY_SCROLLLOCK 70 /**< Scroll Lock Key */
#define INPUT_KEY_SEMICOLON 39 /**< Semicolon Key */
#define INPUT_KEY_SLASH 53 /**< Slash Key */
#define INPUT_KEY_SLEEP 142 /**< System Sleep Key */
#define INPUT_KEY_SPACE 57 /**< Space Key */
#define INPUT_KEY_SYSRQ 99 /**< SysReq Key */
#define INPUT_KEY_T 20 /**< T Key */
#define INPUT_KEY_TAB 15 /**< Tab Key*/
#define INPUT_KEY_U 22 /**< U Key */
#define INPUT_KEY_UP 103 /**< Up Key */
#define INPUT_KEY_UWB 239 /**< Ultra-Wideband Key */
#define INPUT_KEY_V 47 /**< V Key */
#define INPUT_KEY_VOLUMEDOWN 114 /**< Volume Down Key */
#define INPUT_KEY_VOLUMEUP 115 /**< Volume Up Key */
#define INPUT_KEY_W 17 /**< W Key */
#define INPUT_KEY_WAKEUP 143 /**< System Wake Up Key */
#define INPUT_KEY_WLAN 238 /**< Wireless LAN Key */
#define INPUT_KEY_X 45 /**< X Key */
#define INPUT_KEY_Y 21 /**< Y Key */
#define INPUT_KEY_Z 44 /**< Z Key */
/** @} */
/**
* @name Input event BTN codes.
* @anchor INPUT_BTN_CODES
* @{
*/
#define INPUT_BTN_0 0x100 /**< 0 button */
#define INPUT_BTN_1 0x101 /**< 1 button */
#define INPUT_BTN_2 0x102 /**< 2 button */
#define INPUT_BTN_3 0x103 /**< 3 button */
#define INPUT_BTN_4 0x104 /**< 4 button */
#define INPUT_BTN_5 0x105 /**< 5 button */
#define INPUT_BTN_6 0x106 /**< 6 button */
#define INPUT_BTN_7 0x107 /**< 7 button */
#define INPUT_BTN_8 0x108 /**< 8 button */
#define INPUT_BTN_9 0x109 /**< 9 button */
#define INPUT_BTN_A BTN_SOUTH /**< A button */
#define INPUT_BTN_B BTN_EAST /**< B button */
#define INPUT_BTN_BACK 0x116 /**< Back button */
#define INPUT_BTN_C 0x132 /**< C button */
#define INPUT_BTN_DPAD_DOWN 0x221 /**< Directional pad Down */
#define INPUT_BTN_DPAD_LEFT 0x222 /**< Directional pad Left */
#define INPUT_BTN_DPAD_RIGHT 0x223 /**< Directional pad Right */
#define INPUT_BTN_DPAD_UP 0x220 /**< Directional pad Up */
#define INPUT_BTN_EAST 0x131 /**< East button */
#define INPUT_BTN_EXTRA 0x114 /**< Extra button */
#define INPUT_BTN_FORWARD 0x115 /**< Forward button */
#define INPUT_BTN_GEAR_DOWN 0x150 /**< Gear Up button */
#define INPUT_BTN_GEAR_UP 0x151 /**< Gear Down button */
#define INPUT_BTN_LEFT 0x110 /**< Left button */
#define INPUT_BTN_MIDDLE 0x112 /**< Middle button */
#define INPUT_BTN_MODE 0x13c /**< Mode button */
#define INPUT_BTN_NORTH 0x133 /**< North button */
#define INPUT_BTN_RIGHT 0x111 /**< Right button */
#define INPUT_BTN_SELECT 0x13a /**< Select button */
#define INPUT_BTN_SIDE 0x113 /**< Side button */
#define INPUT_BTN_SOUTH 0x130 /**< South button */
#define INPUT_BTN_START 0x13b /**< Start button */
#define INPUT_BTN_TASK 0x117 /**< Task button */
#define INPUT_BTN_THUMBL 0x13d /**< Left thumbstick button */
#define INPUT_BTN_THUMBR 0x13e /**< Right thumbstick button */
#define INPUT_BTN_TL 0x136 /**< Left trigger (L1) */
#define INPUT_BTN_TL2 0x138 /**< Left trigger 2 (L2) */
#define INPUT_BTN_TOUCH 0x14a /**< Touchscreen touch */
#define INPUT_BTN_TR 0x137 /**< Right trigger (R1) */
#define INPUT_BTN_TR2 0x139 /**< Right trigger 2 (R2) */
#define INPUT_BTN_WEST 0x134 /**< West button */
#define INPUT_BTN_X BTN_NORTH /**< X button */
#define INPUT_BTN_Y BTN_WEST /**< Y button */
#define INPUT_BTN_Z 0x135 /**< Z button */
/** @} */
/**
* @name Input event ABS codes.
* @anchor INPUT_ABS_CODES
* @{
*/
#define INPUT_ABS_BRAKE 0x0a /**< Absolute brake position */
#define INPUT_ABS_GAS 0x09 /**< Absolute gas position */
#define INPUT_ABS_MT_SLOT 0x2f /**< Absolute multitouch slot identifier */
#define INPUT_ABS_RUDDER 0x07 /**< Absolute rudder position */
#define INPUT_ABS_RX 0x03 /**< Absolute rotation around X axis */
#define INPUT_ABS_RY 0x04 /**< Absolute rotation around Y axis */
#define INPUT_ABS_RZ 0x05 /**< Absolute rotation around Z axis */
#define INPUT_ABS_THROTTLE 0x06 /**< Absolute throttle position */
#define INPUT_ABS_WHEEL 0x08 /**< Absolute wheel position */
#define INPUT_ABS_X 0x00 /**< Absolute X coordinate */
#define INPUT_ABS_Y 0x01 /**< Absolute Y coordinate */
#define INPUT_ABS_Z 0x02 /**< Absolute Z coordinate */
/** @} */
/**
* @name Input event REL codes.
* @anchor INPUT_REL_CODES
* @{
*/
#define INPUT_REL_DIAL 0x07 /**< Relative dial coordinate */
#define INPUT_REL_HWHEEL 0x06 /**< Relative horizontal wheel coordinate */
#define INPUT_REL_MISC 0x09 /**< Relative misc coordinate */
#define INPUT_REL_RX 0x03 /**< Relative rotation around X axis */
#define INPUT_REL_RY 0x04 /**< Relative rotation around Y axis */
#define INPUT_REL_RZ 0x05 /**< Relative rotation around Z axis */
#define INPUT_REL_WHEEL 0x08 /**< Relative wheel coordinate */
#define INPUT_REL_X 0x00 /**< Relative X coordinate */
#define INPUT_REL_Y 0x01 /**< Relative Y coordinate */
#define INPUT_REL_Z 0x02 /**< Relative Z coordinate */
/** @} */
/**
* @name Input event MSC codes.
* @anchor INPUT_MSC_CODES
* @{
*/
#define INPUT_MSC_SCAN 0x04 /**< Scan code */
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_INPUT_EVENT_CODES_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/input/input-event-codes.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,138 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_ADP5360_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_ADP5360_H_
/**
* @defgroup regulator_adp5360 ADP5360 Devicetree helpers.
* @ingroup regulator_interface
* @{
*/
/**
* @name ADP5360 Regulator modes
* @{
*/
/** Hysteresis mode */
#define ADP5360_MODE_HYS 0
/** PWM mode */
#define ADP5360_MODE_PWM 1
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_ADP5360_H_*/
``` | /content/code_sandbox/include/zephyr/dt-bindings/regulator/adp5360.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 138 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_MAX20335_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_MAX20335_H_
/**
* @defgroup regulator_max20335 MAX20335 Devicetree helpers.
* @ingroup regulator_interface
* @{
*/
/**
* @name MAX20335 Regulator modes
* @{
*/
/** LDO mode */
#define MAX20335_LDO_MODE 0
/** Load switch mode */
#define MAX20335_LOAD_SWITCH_MODE 1
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_MAX20335_H_*/
``` | /content/code_sandbox/include/zephyr/dt-bindings/regulator/max20335.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM1300_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM1300_H_
/**
* @defgroup regulator_npm1300 NPM1300 Devicetree helpers.
* @ingroup regulator_interface
* @{
*/
/**
* @name NPM1300 Regulator modes
* @{
*/
/* Buck modes */
#define NPM1300_BUCK_MODE_AUTO 0x00U
#define NPM1300_BUCK_MODE_PWM 0x01U
#define NPM1300_BUCK_MODE_PFM 0x04U
/* LDSW / LDO modes */
#define NPM1300_LDSW_MODE_LDO 0x02U
#define NPM1300_LDSW_MODE_LDSW 0x03U
/* GPIO control configuration */
#define NPM1300_GPIO_CHAN_NONE 0x00U
#define NPM1300_GPIO_CHAN_0 0x01U
#define NPM1300_GPIO_CHAN_1 0x02U
#define NPM1300_GPIO_CHAN_2 0x03U
#define NPM1300_GPIO_CHAN_3 0x04U
#define NPM1300_GPIO_CHAN_4 0x05U
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM1300_H_*/
``` | /content/code_sandbox/include/zephyr/dt-bindings/regulator/npm1300.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 301 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_I2C_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_I2C_H_
#define I2C_BITRATE_STANDARD 100000 /* 100 Kbit/s */
#define I2C_BITRATE_FAST 400000 /* 400 Kbit/s */
#define I2C_BITRATE_FAST_PLUS 1000000 /* 1 Mbit/s */
#define I2C_BITRATE_HIGH 3400000 /* 3.4 Mbit/s */
#define I2C_BITRATE_ULTRA 5000000 /* 5 Mbit/s */
#define SMB_CHANNEL_A 0
#define SMB_CHANNEL_B 1
#define SMB_CHANNEL_C 2
#define I2C_CHANNEL_D 3
#define I2C_CHANNEL_E 4
#define I2C_CHANNEL_F 5
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_I2C_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/i2c/i2c.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 200 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_H_
#define IT8XXX2_ECPM_CGCTRL4R_OFF 0x09
/*
* The clock gate offsets combine the register offset from ECPM_BASE and the
* mask within that register into one value. These are used for
* clock_enable_peripheral() and clock_disable_peripheral()
*/
#define CGC_OFFSET_SMBF ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x80)
#define CGC_OFFSET_SMBE ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x40)
#define CGC_OFFSET_SMBD ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x20)
#define CGC_OFFSET_SMBC ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x10)
#define CGC_OFFSET_SMBB ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x08)
#define CGC_OFFSET_SMBA ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x04)
/* I2C channel switch selection */
#define I2C_CHA_LOCATE 0
#define I2C_CHB_LOCATE 1
#define I2C_CHC_LOCATE 2
#define I2C_CHD_LOCATE 3
#define I2C_CHE_LOCATE 4
#define I2C_CHF_LOCATE 5
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/i2c/it8xxx2-i2c.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 402 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_
/**
* @brief nRF-specific GPIO Flags
* @defgroup gpio_interface_nrf nRF-specific GPIO Flags
* @ingroup gpio_interface
* @{
*/
/**
* @name nRF GPIO drive flags
* @brief nRF GPIO drive flags
*
* Standard (S) or High (H) drive modes can be applied to both pin levels, 0 or
* 1. High drive mode will increase current capabilities of the pin (refer to
* each SoC reference manual).
*
* When the pin is configured to operate in open-drain mode (wired-and), the
* drive mode can only be selected for the 0 level (1 is disconnected).
* Similarly, when the pin is configured to operate in open-source mode
* (wired-or), the drive mode can only be set for the 1 level
* (0 is disconnected).
*
* The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
* follows:
*
* - Bit 8: Drive mode for '0' (0=Standard, 1=High)
* - Bit 9: Drive mode for '1' (0=Standard, 1=High)
*
* @{
*/
/** @cond INTERNAL_HIDDEN */
/** Drive mode field mask */
#define NRF_GPIO_DRIVE_MSK 0x0300U
/** @endcond */
/** Standard drive for '0' (default, used with GPIO_OPEN_DRAIN) */
#define NRF_GPIO_DRIVE_S0 (0U << 8U)
/** High drive for '0' (used with GPIO_OPEN_DRAIN) */
#define NRF_GPIO_DRIVE_H0 (1U << 8U)
/** Standard drive for '1' (default, used with GPIO_OPEN_SOURCE) */
#define NRF_GPIO_DRIVE_S1 (0U << 9U)
/** High drive for '1' (used with GPIO_OPEN_SOURCE) */
#define NRF_GPIO_DRIVE_H1 (1U << 9U)
/** Standard drive for '0' and '1' (default) */
#define NRF_GPIO_DRIVE_S0S1 (NRF_GPIO_DRIVE_S0 | NRF_GPIO_DRIVE_S1)
/** Standard drive for '0' and high for '1' */
#define NRF_GPIO_DRIVE_S0H1 (NRF_GPIO_DRIVE_S0 | NRF_GPIO_DRIVE_H1)
/** High drive for '0' and standard for '1' */
#define NRF_GPIO_DRIVE_H0S1 (NRF_GPIO_DRIVE_H0 | NRF_GPIO_DRIVE_S1)
/** High drive for '0' and '1' */
#define NRF_GPIO_DRIVE_H0H1 (NRF_GPIO_DRIVE_H0 | NRF_GPIO_DRIVE_H1)
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/nordic-nrf-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 617 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_GPIO_H_
/**
* @brief GPIO Driver APIs
* @defgroup gpio_interface GPIO Driver APIs
* @ingroup io_interfaces
* @{
*/
/** Mask for DT GPIO flags. */
#define GPIO_DT_FLAGS_MASK 0x3F
/**
* @name GPIO pin active level flags
* @{
*/
/** GPIO pin is active (has logical value '1') in low state. */
#define GPIO_ACTIVE_LOW (1 << 0)
/** GPIO pin is active (has logical value '1') in high state. */
#define GPIO_ACTIVE_HIGH (0 << 0)
/** @} */
/**
* @name GPIO pin drive flags
* @{
*/
/** @cond INTERNAL_HIDDEN */
/* Configures GPIO output in single-ended mode (open drain or open source). */
#define GPIO_SINGLE_ENDED (1 << 1)
/* Configures GPIO output in push-pull mode */
#define GPIO_PUSH_PULL (0 << 1)
/* Indicates single ended open drain mode (wired AND). */
#define GPIO_LINE_OPEN_DRAIN (1 << 2)
/* Indicates single ended open source mode (wired OR). */
#define GPIO_LINE_OPEN_SOURCE (0 << 2)
/** @endcond */
/** Configures GPIO output in open drain mode (wired AND).
*
* @note 'Open Drain' mode also known as 'Open Collector' is an output
* configuration which behaves like a switch that is either connected to ground
* or disconnected.
*/
#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
/** Configures GPIO output in open source mode (wired OR).
*
* @note 'Open Source' is a term used by software engineers to describe output
* mode opposite to 'Open Drain'. It behaves like a switch that is either
* connected to power supply or disconnected. There exist no corresponding
* hardware schematic and the term is generally unknown to hardware engineers.
*/
#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
/** @} */
/**
* @name GPIO pin bias flags
* @{
*/
/** Enables GPIO pin pull-up. */
#define GPIO_PULL_UP (1 << 4)
/** Enable GPIO pin pull-down. */
#define GPIO_PULL_DOWN (1 << 5)
/** @} */
/**
* Configures GPIO interrupt to wakeup the system from low power mode.
*/
#define GPIO_INT_WAKEUP (1 << 6)
/* Note: Bits 15 downto 8 are reserved for SoC specific flags. */
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 559 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SEMTECH_SX1509B_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SEMTECH_SX1509B_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding. Only applicable for Semtech SX1509B GPIO
* controllers.
*/
#define SX1509B_GPIO_DEBOUNCE (1U << 8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SEMTECH_SX1509B_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/semtech-sx1509b.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 136 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_TI_CC13XX_CC26XX_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_TI_CC13XX_CC26XX_GPIO_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding. Only applicable for Texas
* Instruments CC1xx/CC26xx SoCs.
*/
#define CC13XX_CC26XX_GPIO_DEBOUNCE (1U << 8)
/**
* @name GPIO drive strength flags
*
* The drive strength flags are a Zephyr specific extension of the standard GPIO
* flags specified by the Linux GPIO binding. Only applicable for Texas
* Instruments CC13xx/CC26xx SoCs.
*
* The interface supports two different drive strengths:
* `DFLT` - The lowest drive strength supported by the HW
* `ALT` - The highest drive strength supported by the HW
*
* @{
*/
/** @cond INTERNAL_HIDDEN */
#define CC13XX_CC26XX_GPIO_DS_POS 9
#define CC13XX_CC26XX_GPIO_DS_MASK (0x3U << CC13XX_CC26XX_GPIO_DS_POS)
/** @endcond */
/** Default drive strength. */
#define CC13XX_CC26XX_GPIO_DS_DFLT (0x0U << CC13XX_CC26XX_GPIO_DS_POS)
/** Alternative drive strength. */
#define CC13XX_CC26XX_GPIO_DS_ALT (0x3U << CC13XX_CC26XX_GPIO_DS_POS)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_TI_CC13XX_CC26XX_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 352 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SNPS_DESIGNWARE_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SNPS_DESIGNWARE_GPIO_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding. Only applicable for SNPS DesignWare GPIO
* controllers.
*/
#define DW_GPIO_DEBOUNCE (1U << 8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SNPS_DESIGNWARE_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/snps-designware-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_STM32_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_STM32_GPIO_H_
/**
* @brief STM32 GPIO specific flags
*
* The driver flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
* follows:
*
* - Bit 8: Configure a GPIO pin to power on the system after Poweroff.
*
* @ingroup gpio_interface
* @{
*/
/**
* Configures a GPIO pin to power on the system after Poweroff.
* This flag is reserved to GPIO pins that are associated with wake-up pins
* in STM32 PWR devicetree node, through the property "wkup-gpios".
*/
#define STM32_GPIO_WKUP (1 << 8)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_STM32_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/stm32-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 191 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM0_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM0_GPIO_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding. Only applicable for Atmel SAM0 SoCs.
*/
#define SAM0_GPIO_DEBOUNCE (1U << 8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM0_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/atmel-sam0-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```objective-c
/*
*/
#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_
#define INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_
/** ST Morpho pin mask (0...143). */
#define ST_MORPHO_PIN_MASK 0xFF
/**
* @name ST Morpho pin identifiers
* @{
*/
#define ST_MORPHO_L_1 0
#define ST_MORPHO_L_2 1
#define ST_MORPHO_L_3 2
#define ST_MORPHO_L_4 3
#define ST_MORPHO_L_5 4
#define ST_MORPHO_L_6 5
#define ST_MORPHO_L_7 6
#define ST_MORPHO_L_8 7
#define ST_MORPHO_L_9 8
#define ST_MORPHO_L_10 9
#define ST_MORPHO_L_11 10
#define ST_MORPHO_L_12 11
#define ST_MORPHO_L_13 12
#define ST_MORPHO_L_14 13
#define ST_MORPHO_L_15 14
#define ST_MORPHO_L_16 15
#define ST_MORPHO_L_17 16
#define ST_MORPHO_L_18 17
#define ST_MORPHO_L_19 18
#define ST_MORPHO_L_20 19
#define ST_MORPHO_L_21 20
#define ST_MORPHO_L_22 21
#define ST_MORPHO_L_23 22
#define ST_MORPHO_L_24 23
#define ST_MORPHO_L_25 24
#define ST_MORPHO_L_26 25
#define ST_MORPHO_L_27 26
#define ST_MORPHO_L_28 27
#define ST_MORPHO_L_29 28
#define ST_MORPHO_L_30 29
#define ST_MORPHO_L_31 30
#define ST_MORPHO_L_32 31
#define ST_MORPHO_L_33 32
#define ST_MORPHO_L_34 33
#define ST_MORPHO_L_35 34
#define ST_MORPHO_L_36 35
#define ST_MORPHO_L_37 36
#define ST_MORPHO_L_38 37
#define ST_MORPHO_L_39 38
#define ST_MORPHO_L_40 39
#define ST_MORPHO_L_41 40
#define ST_MORPHO_L_42 41
#define ST_MORPHO_L_43 42
#define ST_MORPHO_L_44 43
#define ST_MORPHO_L_45 44
#define ST_MORPHO_L_46 45
#define ST_MORPHO_L_47 46
#define ST_MORPHO_L_48 47
#define ST_MORPHO_L_49 48
#define ST_MORPHO_L_50 49
#define ST_MORPHO_L_51 50
#define ST_MORPHO_L_52 51
#define ST_MORPHO_L_53 52
#define ST_MORPHO_L_54 53
#define ST_MORPHO_L_55 54
#define ST_MORPHO_L_56 55
#define ST_MORPHO_L_57 56
#define ST_MORPHO_L_58 57
#define ST_MORPHO_L_59 58
#define ST_MORPHO_L_60 59
#define ST_MORPHO_L_61 60
#define ST_MORPHO_L_62 61
#define ST_MORPHO_L_63 62
#define ST_MORPHO_L_64 63
#define ST_MORPHO_L_65 64
#define ST_MORPHO_L_66 65
#define ST_MORPHO_L_67 66
#define ST_MORPHO_L_68 67
#define ST_MORPHO_L_69 68
#define ST_MORPHO_L_70 69
#define ST_MORPHO_L_71 70
#define ST_MORPHO_L_72 71
#define ST_MORPHO_R_1 72
#define ST_MORPHO_R_2 73
#define ST_MORPHO_R_3 74
#define ST_MORPHO_R_4 75
#define ST_MORPHO_R_5 76
#define ST_MORPHO_R_6 77
#define ST_MORPHO_R_7 78
#define ST_MORPHO_R_8 79
#define ST_MORPHO_R_9 80
#define ST_MORPHO_R_10 81
#define ST_MORPHO_R_11 82
#define ST_MORPHO_R_12 83
#define ST_MORPHO_R_13 84
#define ST_MORPHO_R_14 85
#define ST_MORPHO_R_15 86
#define ST_MORPHO_R_16 87
#define ST_MORPHO_R_17 88
#define ST_MORPHO_R_18 89
#define ST_MORPHO_R_19 90
#define ST_MORPHO_R_20 91
#define ST_MORPHO_R_21 92
#define ST_MORPHO_R_22 93
#define ST_MORPHO_R_23 94
#define ST_MORPHO_R_24 95
#define ST_MORPHO_R_25 96
#define ST_MORPHO_R_26 97
#define ST_MORPHO_R_27 98
#define ST_MORPHO_R_28 99
#define ST_MORPHO_R_29 100
#define ST_MORPHO_R_30 101
#define ST_MORPHO_R_31 102
#define ST_MORPHO_R_32 103
#define ST_MORPHO_R_33 104
#define ST_MORPHO_R_34 105
#define ST_MORPHO_R_35 106
#define ST_MORPHO_R_36 107
#define ST_MORPHO_R_37 108
#define ST_MORPHO_R_38 109
#define ST_MORPHO_R_39 110
#define ST_MORPHO_R_40 111
#define ST_MORPHO_R_41 112
#define ST_MORPHO_R_42 113
#define ST_MORPHO_R_43 114
#define ST_MORPHO_R_44 115
#define ST_MORPHO_R_45 116
#define ST_MORPHO_R_46 117
#define ST_MORPHO_R_47 118
#define ST_MORPHO_R_48 119
#define ST_MORPHO_R_49 120
#define ST_MORPHO_R_50 121
#define ST_MORPHO_R_51 122
#define ST_MORPHO_R_52 123
#define ST_MORPHO_R_53 124
#define ST_MORPHO_R_54 125
#define ST_MORPHO_R_55 126
#define ST_MORPHO_R_56 127
#define ST_MORPHO_R_57 128
#define ST_MORPHO_R_58 129
#define ST_MORPHO_R_59 130
#define ST_MORPHO_R_60 131
#define ST_MORPHO_R_61 132
#define ST_MORPHO_R_62 133
#define ST_MORPHO_R_63 134
#define ST_MORPHO_R_64 135
#define ST_MORPHO_R_65 136
#define ST_MORPHO_R_66 137
#define ST_MORPHO_R_67 138
#define ST_MORPHO_R_68 139
#define ST_MORPHO_R_69 140
#define ST_MORPHO_R_70 141
#define ST_MORPHO_R_71 142
#define ST_MORPHO_R_72 143
/** @} */
#endif /* INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/st-morpho-header.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,827 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ADI_MAX32_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ADI_MAX32_GPIO_H_
/**
* @brief MAX32-specific GPIO Flags
* @defgroup gpio_interface_max32 MAX32-specific GPIO Flags
* @ingroup gpio_interface
* @{
*/
/**
* @name MAX32 GPIO drive flags
* @brief MAX32 GPIO drive flags
*
* The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
* follows:
*
* - Bit 8: GPIO Supply Voltage Select
* Selects the voltage rail used for the pin.
* 0: VDDIO
* 1: VDDIOH
*
* - Bit 9: GPIO Drive Strength Select,
* MAX32_GPIO_DRV_STRENGTH_0 = 1mA
* MAX32_GPIO_DRV_STRENGTH_1 = 2mA
* MAX32_GPIO_DRV_STRENGTH_2 = 4mA
* MAX32_GPIO_DRV_STRENGTH_3 = 8mA
*
* - Bit 10: Weak pull up selection, Weak Pullup to VDDIO (1MOhm)
* 0: Disable
* 1: Enable
*
* - Bit 11: Weak pull down selection, Weak Pulldown to VDDIOH (1MOhm)
* 0: Disable
* 1: Enable
* @{
*/
/** GPIO Voltage Select */
#define MAX32_GPIO_VSEL_POS (8U)
#define MAX32_GPIO_VSEL_MASK (0x01U << MAX32_GPIO_VSEL_POS)
#define MAX32_GPIO_VSEL_VDDIO (0U << MAX32_GPIO_VSEL_POS)
#define MAX32_GPIO_VSEL_VDDIOH (1U << MAX32_GPIO_VSEL_POS)
/** GPIO Drive Strength Select */
#define MAX32_GPIO_DRV_STRENGTH_POS (9U)
#define MAX32_GPIO_DRV_STRENGTH_MASK (0x03U << MAX32_GPIO_DRV_STRENGTH_POS)
#define MAX32_GPIO_DRV_STRENGTH_0 (0U << MAX32_GPIO_DRV_STRENGTH_POS)
#define MAX32_GPIO_DRV_STRENGTH_1 (1U << MAX32_GPIO_DRV_STRENGTH_POS)
#define MAX32_GPIO_DRV_STRENGTH_2 (2U << MAX32_GPIO_DRV_STRENGTH_POS)
#define MAX32_GPIO_DRV_STRENGTH_3 (3U << MAX32_GPIO_DRV_STRENGTH_POS)
/** GPIO bias weak pull up selection, to VDDIO (1MOhm) */
#define MAX32_GPIO_WEAK_PULL_UP_POS (10U)
#define MAX32_GPIO_WEAK_PULL_UP (1U << MAX32_GPIO_WEAK_PULL_UP_POS)
/** GPIO bias weak pull down selection, to VDDIOH (1MOhm) */
#define MAX32_GPIO_WEAK_PULL_DOWN_POS (11U)
#define MAX32_GPIO_WEAK_PULL_DOWN (1U << MAX32_GPIO_WEAK_PULL_DOWN_POS)
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ADI_MAX32_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/adi-max32-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 667 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_S32_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_S32_GPIO_H_
/**
* @brief NXP S32 GPIO specific flags
*
* The driver flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
* follows:
*
* - Bit 8: Interrupt controller to which the respective GPIO interrupt is routed.
*
* @ingroup gpio_interface
* @{
*/
/** @cond INTERNAL_HIDDEN */
#define NXP_S32_GPIO_INT_CONTROLLER_POS 8
#define NXP_S32_GPIO_INT_CONTROLLER_MASK (0x1U << NXP_S32_GPIO_INT_CONTROLLER_POS)
/** @endcond */
/**
* @name NXP S32 GPIO interrupt controller routing flags
* @brief NXP S32 GPIO interrupt controller routing flags
* @{
*/
/** Interrupt routed to the WKPU controller */
#define NXP_S32_GPIO_INT_WKPU (0x1U << NXP_S32_GPIO_INT_CONTROLLER_POS)
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_S32_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/nxp-s32-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 242 |
```objective-c
/*
*/
/**
* @file
* @brief Pmod GPIO nexus signal index definitions
*
* Defines meant to be used in conjunction with the "digilent,pmod"
* GPIO nexus mapping.
*
* Example usage:
*
* @code{.dts}
* &spi1 {
* cs-gpios = <&pmod0 PMOD_SPI_CS GPIO_ACTIVE_LOW>;
*
* example_device: example-dev@0 {
* compatible = "vnd,spi-device";
* reg = <0>;
* };
* };
* @endcode
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_DIGILENT_PMOD_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_DIGILENT_PMOD_H_
/**
* For reference see the Pmod interface specification:
* path_to_url
*/
/* GPIO */
/**
* @brief IO[n] signal on a Pmod GPIO nexus node following
* Pmod Interface Type 1 or 1A (GPIO or expanded GPIO)
*
* The Pmod GPIO nexus maps pin indexes 0..7 to IO1..IO8.
*/
#define PMOD_IO(n) ((n) - 1)
/* SPI */
/**
* @brief SPI CS signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2 (SPI) peripherals.
*/
#define PMOD_SPI_CS PMOD_IO(1)
/**
* @brief SPI MOSI signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2 (SPI) peripherals.
*/
#define PMOD_SPI_MOSI PMOD_IO(2)
/**
* @brief SPI MISO signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2 (SPI) peripherals.
*/
#define PMOD_SPI_MISO PMOD_IO(3)
/**
* @brief SPI SCK signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2 (SPI) peripherals.
*/
#define PMOD_SPI_SCK PMOD_IO(4)
/* Expanded SPI */
/**
* @brief SPI CS signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2A (expanded SPI) peripherals.
*/
#define PMOD_EXP_SPI_CS PMOD_IO(1)
/**
* @brief SPI MOSI signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2A (expanded SPI) peripherals.
*/
#define PMOD_EXP_SPI_MOSI PMOD_IO(2)
/**
* @brief SPI MISO signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2A (expanded SPI) peripherals.
*/
#define PMOD_EXP_SPI_MISO PMOD_IO(3)
/**
* @brief SPI SCK signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2A (expanded SPI) peripherals.
*/
#define PMOD_EXP_SPI_SCK PMOD_IO(4)
/**
* @brief INT alternate signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2A (expanded SPI) peripherals.
*/
#define PMOD_EXP_SPI_INT PMOD_IO(5)
/**
* @brief RESET alternate signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2A (expanded SPI) peripherals.
*/
#define PMOD_EXP_SPI_RESET PMOD_IO(6)
/**
* @brief SPI CS2 alternate signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2A (expanded SPI) peripherals.
*/
#define PMOD_EXP_SPI_CS2 PMOD_IO(7)
/**
* @brief SPI CS3 alternate signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 2A (expanded SPI) peripherals.
*/
#define PMOD_EXP_SPI_CS3 PMOD_IO(8)
/* Expanded UART */
/**
* @brief INT alternate signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 3A (expanded UART) peripherals.
*/
#define PMOD_EXP_UART_INT PMOD_IO(5)
/**
* @brief RESET alternate signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 3A (expanded UART) peripherals.
*/
#define PMOD_EXP_UART_RESET PMOD_IO(6)
/* H-bridge */
/**
* @brief DIR signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 4 (H-bridge) peripherals.
*/
#define PMOD_HBRIDGE_DIR PMOD_IO(1)
/**
* @brief EN signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 4 (H-bridge) peripherals.
*/
#define PMOD_HBRIDGE_EN PMOD_IO(2)
/* Dual H-bridge */
/**
* @brief DIR1 signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 5 (dual H-bridge) peripherals.
*/
#define PMOD_DUAL_HBRIDGE_DIR1 PMOD_IO(1)
/**
* @brief EN1 signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 5 (dual H-bridge) peripherals.
*/
#define PMOD_DUAL_HBRIDGE_EN1 PMOD_IO(2)
/**
* @brief DIR2 signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 5 (dual H-bridge) peripherals.
*/
#define PMOD_DUAL_HBRIDGE_DIR2 PMOD_IO(3)
/**
* @brief EN2 signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 5 (dual H-bridge) peripherals.
*/
#define PMOD_DUAL_HBRIDGE_EN2 PMOD_IO(4)
/* Expanded dual H-bridge */
/**
* @brief DIR1 signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 5A (expanded dual H-bridge) peripherals.
*/
#define PMOD_EXP_DUAL_HBRIDGE_DIR1 PMOD_IO(1)
/**
* @brief EN1 signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 5A (expanded dual H-bridge) peripherals.
*/
#define PMOD_EXP_DUAL_HBRIDGE_EN1 PMOD_IO(2)
/**
* @brief DIR2 signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 5A (expanded dual H-bridge) peripherals.
*/
#define PMOD_EXP_DUAL_HBRIDGE_DIR2 PMOD_IO(5)
/**
* @brief EN2 signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 5A (expanded dual H-bridge) peripherals.
*/
#define PMOD_EXP_DUAL_HBRIDGE_EN2 PMOD_IO(6)
/* I2C */
/**
* @brief INT signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 6 (I2C) peripherals.
*/
#define PMOD_I2C_INT PMOD_IO(1)
/**
* @brief RESET signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 6 (I2C) peripherals.
*/
#define PMOD_I2C_RESET PMOD_IO(2)
/**
* @brief SCL signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 6 (I2C) peripherals.
*/
#define PMOD_I2C_SCL PMOD_IO(3)
/**
* @brief SDA signal index on a Pmod GPIO nexus node.
* Used with Pmod Interface Type 6 (I2C) peripherals.
*/
#define PMOD_I2C_SDA PMOD_IO(4)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_DIGILENT_PMOD_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/digilent-pmod.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,651 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_INFINEON_XMC4XXX_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_INFINEON_XMC4XXX_GPIO_H_
#define XMC4XXX_GPIO_DS_POS 9
#define XMC4XXX_GPIO_DS_MASK 0xf
/* GPIO driver will use XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE if DS is unset */
#define XMC4XXX_GPIO_DS_STRONG_SHARP_EDGE (0x1 << XMC4XXX_GPIO_DS_POS)
#define XMC4XXX_GPIO_DS_STRONG_MEDIUM_EDGE (0x2 << XMC4XXX_GPIO_DS_POS)
#define XMC4XXX_GPIO_DS_STRONG_SOFT_EDGE (0x3 << XMC4XXX_GPIO_DS_POS)
#define XMC4XXX_GPIO_DS_STRONG_SLOW_EDGE (0x4 << XMC4XXX_GPIO_DS_POS)
#define XMC4XXX_GPIO_DS_MEDIUM (0x5 << XMC4XXX_GPIO_DS_POS)
/* values 5, 6 not set in xmc4_gpio.h */
#define XMC4XXX_GPIO_DS_WEAK (0x8 << XMC4XXX_GPIO_DS_POS)
#define XMC4XXX_GPIO_GET_DS(flags) ((flags >> XMC4XXX_GPIO_DS_POS) & XMC4XXX_GPIO_DS_MASK)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_INFINEON_XMC4XXX_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/infineon-xmc4xxx-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 306 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_
#define RENESAS_GPIO_DS_POS (8)
#define RENESAS_GPIO_DS_MSK (0x3U << RENESAS_GPIO_DS_POS)
/* GPIO Drive strength */
#define RENESAS_GPIO_DS_LOW (0x0 << RENESAS_GPIO_DRIVE_POS)
#define RENESAS_GPIO_DS_MIDDLE (0x1 << RENESAS_GPIO_DRIVE_POS)
#define RENESAS_GPIO_DS_HIGH_SPEED_HIGH_DRIVE (0x2 << RENESAS_GPIO_DRIVE_POS)
#define RENESAS_GPIO_DS_HIGH_DRIVE (0x3 << RENESAS_GPIO_DRIVE_POS)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 198 |
```objective-c
/**
*
*
* @file
* @brief SDP-120 GPIO index definitions
*
* Defines meant to be used in conjunction with the "adi,sdp-120"
* ADI SDP-120 mapping.
*
* Example usage:
*
* @code{.dts}
* &spi1 {
* cs-gpios = <&sdp_120 SDP_120_SPI_SS_N GPIO_ACTIVE_LOW>;
*
* example_device: example-dev@0 {
* compatible = "vnd,spi-device";
* reg = <0>;
* };
* };
* @endcode
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ADI_SDP_120_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ADI_SDP_120_H_
/* GPIO */
/**
* @brief IO[n] signal on a SDP-120 GPIO nexus node following
*/
#define SDP_120_IO(n) (n-1)
/* SPI */
#define SDP_120_SPI_D2 SDP_120_IO(33) /* SPI_D2 */
#define SDP_120_SPI_D3 SDP_120_IO(34) /* SPI_D3 */
#define SDP_120_SERIAL_INT SDP_120_IO(35) /* SERIAL_INT */
#define SDP_120_SPI_SEL_B_N SDP_120_IO(37) /* SPI_SEL_B_N */
#define SDP_120_SPI_SEL_C_N SDP_120_IO(38) /* SPI_SEL_C_N */
#define SDP_120_SPI_SS_N SDP_120_IO(39) /* SPI_SS_N */
/* GPIO */
#define SDP_120_GPIO0 SDP_120_IO(43) /* GPIO0 */
#define SDP_120_GPIO2 SDP_120_IO(44) /* GPIO2 */
#define SDP_120_GPIO4 SDP_120_IO(45) /* GPIO4 */
#define SDP_120_GPIO6 SDP_120_IO(47) /* GPIO6 */
/* TMR */
#define SDP_120_TMR_A SDP_120_IO(48) /* TMR_A */
/* USART */
#define SDP_120_UART_RX SDP_120_IO(59) /* UART2_RX */
#define SDP_120_UART_TX SDP_120_IO(62) /* UART2_TX */
/* TMR */
#define SDP_120_TMR_D SDP_120_IO(72) /* TMR_D */
#define SDP_120_TMR_B SDP_120_IO(73) /* TMR_B */
/* GPIO */
#define SDP_120_GPIO7 SDP_120_IO(74) /* GPIO7 */
#define SDP_120_GPIO5 SDP_120_IO(76) /* GPIO5 */
#define SDP_120_GPIO3 SDP_120_IO(77) /* GPIO3 */
#define SDP_120_GPIO1 SDP_120_IO(78) /* GPIO1 */
/* I2C */
#define SDP_120_SCL_0 SDP_120_IO(79) /* SCL_0 */
#define SDP_120_SDA_0 SDP_120_IO(80) /* SDA_0 */
/* SPI */
#define SDP_120_SPI_CLK SDP_120_IO(82) /* SPI_CLK */
#define SDP_120_SPI_MISO SDP_120_IO(83) /* SPI_MISO */
#define SDP_120_SPI_MOSI SDP_120_IO(84) /* SPI_MOSI */
#define SDP_120_SPI_SEL_A_N SDP_120_IO(85) /* SPI_SEL_A_N */
/* SPORT - no driver yet */
#define SDP_120_SPI_SPORT_TSCLK SDP_120_IO(87) /* SPORT_TSCLK */
#define SDP_120_SPI_SPORT_DT0 SDP_120_IO(88) /* SPORT_DT0 */
#define SDP_120_SPI_SPORT_TFS SDP_120_IO(89) /* SPORT_TFS */
#define SDP_120_SPI_SPORT_RFS SDP_120_IO(90) /* SPORT_RFS */
#define SDP_120_SPI_SPORT_DR0 SDP_120_IO(91) /* SPORT_DR0 */
#define SDP_120_SPI_SPORT_RSCLK SDP_120_IO(92) /* SPORT_RSCLK */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ADI_SDP_120_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/adi-sdp-120.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 975 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM_GPIO_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding. Only applicable for Atmel SAM SoCs.
*/
#define SAM_GPIO_DEBOUNCE (1U << 8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/atmel-sam-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NUMICRO_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NUMICRO_GPIO_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding. Only applicable for Nuvoton NuMicro SoCs.
*/
#define NUMICRO_GPIO_INPUT_DEBOUNCE (1U << 8)
/**
* @brief Enable Schmitt trigger on input.
*
* The Schmitt trigger flag is a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding. Only applicable for Nuvoton NuMicro SoCs.
*/
#define NUMICRO_GPIO_INPUT_SCHMITT (1U << 9)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NUMICRO_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/numicro-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 200 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM1300_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM1300_GPIO_H_
/**
* @brief nPM1300-specific GPIO Flags
* @defgroup gpio_interface_npm1300 nPM1300-specific GPIO Flags
*
* The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
* follows:
*
* - Bit 8: Drive strength (0=1mA, 1=6mA)
* - Bit 9: Debounce (0=OFF, 1=ON)
* - Bit 10: Watchdog reset (0=OFF, 1=ON)
* - Bit 11: Power loss warning (0=OFF, 1=ON)
*
* @ingroup gpio_interface
* @{
*/
/**
* @name nPM1300 GPIO drive strength flags
* @brief nPM1300 GPIO drive strength flags
* @{
*/
/** @cond INTERNAL_HIDDEN */
/** Drive mode field mask */
#define NPM1300_GPIO_DRIVE_MSK 0x0100U
/** @endcond */
/** 1mA drive */
#define NPM1300_GPIO_DRIVE_1MA (0U << 8U)
/** 6mA drive */
#define NPM1300_GPIO_DRIVE_6MA (1U << 8U)
/** @} */
/**
* @name nPM1300 GPIO debounce flags
* @brief nPM1300 GPIO debounce flags
* @{
*/
/** @cond INTERNAL_HIDDEN */
/** Debounce field mask */
#define NPM1300_GPIO_DEBOUNCE_MSK 0x0200U
/** @endcond */
/** Normal drive */
#define NPM1300_GPIO_DEBOUNCE_OFF (0U << 9U)
/** High drive */
#define NPM1300_GPIO_DEBOUNCE_ON (1U << 9U)
/** @} */
/**
* @name nPM1300 GPIO watchdog reset flags
* @brief nPM1300 GPIO watchdog reset flags
* @{
*/
/** @cond INTERNAL_HIDDEN */
/** watchdog reset field mask */
#define NPM1300_GPIO_WDT_RESET_MSK 0x0400U
/** @endcond */
/** Off */
#define NPM1300_GPIO_WDT_RESET_OFF (0U << 10U)
/** On */
#define NPM1300_GPIO_WDT_RESET_ON (1U << 10U)
/** @} */
/**
* @name nPM1300 GPIO power loss warning flags
* @brief nPM1300 GPIO power loss warning flags
* @{
*/
/** @cond INTERNAL_HIDDEN */
/** power loss warning field mask */
#define NPM1300_GPIO_PWRLOSSWARN_MSK 0x0800U
/** @endcond */
/** Off */
#define NPM1300_GPIO_PWRLOSSWARN_OFF (0U << 11U)
/** On */
#define NPM1300_GPIO_PWRLOSSWARN_ON (1U << 11U)
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM1300_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/nordic-npm1300-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 650 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NPCX_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NPCX_GPIO_H_
/**
* @name GPIO pin voltage flags
*
* The voltage flags are a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding for use with the Nuvoton NPCX SoCs.
*
* @{
*/
/** @cond INTERNAL_HIDDEN */
#define NPCX_GPIO_VOLTAGE_POS 11
#define NPCX_GPIO_VOLTAGE_MASK (1U << NPCX_GPIO_VOLTAGE_POS)
/** @endcond */
/** Set pin at the default voltage level (3.3V) */
#define NPCX_GPIO_VOLTAGE_DEFAULT (0U << NPCX_GPIO_VOLTAGE_POS)
/** Set pin voltage level at 1.8 V */
#define NPCX_GPIO_VOLTAGE_1P8 (1U << NPCX_GPIO_VOLTAGE_POS)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NPCX_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/nuvoton-npcx-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 225 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM6001_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM6001_GPIO_H_
/**
* @brief nPM6001-specific GPIO Flags
* @defgroup gpio_interface_npm6001 nPM6001-specific GPIO Flags
*
* The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
* follows:
*
* - Bit 8: Drive strength (0=NORMAL, 1=HIGH)
* - Bit 9: Input type (0=SCHMITT, 1=CMOS)
*
* @ingroup gpio_interface
* @{
*/
/**
* @name nPM6001 GPIO drive strength flags
* @brief nPM6001 GPIO drive strength flags
* @{
*/
/** @cond INTERNAL_HIDDEN */
/** Drive mode field mask */
#define NPM6001_GPIO_DRIVE_MSK 0x0100U
/** @endcond */
/** Normal drive */
#define NPM6001_GPIO_DRIVE_NORMAL (0U << 8U)
/** High drive */
#define NPM6001_GPIO_DRIVE_HIGH (1U << 8U)
/** @} */
/**
* @name nPM6001 GPIO drive strength flags
* @brief nPM6001 GPIO drive strength flags
* @{
*/
/** @cond INTERNAL_HIDDEN */
/** Input type field mask */
#define NPM6001_GPIO_SENSE_MSK 0x0200U
/** @endcond */
/** Schmitt trigger input type */
#define NPM6001_GPIO_SENSE_SCHMITT (0U << 9U)
/** CMOS input type */
#define NPM6001_GPIO_SENSE_CMOS (1U << 9U)
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/nordic-npm6001-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 395 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ANDESTECH_ATCGPIO100_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ANDESTECH_ATCGPIO100_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding. Only applicable for Andestech Technology
* Corporation ATCGPIO100 SoCs.
*/
#define ATCGPIO100_GPIO_DEBOUNCE (1U << 8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ANDESTECH_ATCGPIO100_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/andestech-atcgpio100.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 136 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_
/**
* @name GPIO drive strength flags
*
* The drive strength flags are a Zephyr specific extension of the standard GPIO
* flags specified by the Linux GPIO binding. Only applicable for Espressif
* ESP32 SoCs.
*
* The interface supports two different drive strengths:
* `DFLT` - The lowest drive strength supported by the HW
* `ALT` - The highest drive strength supported by the HW
*
* @{
*/
/** @cond INTERNAL_HIDDEN */
#define ESP32_GPIO_DS_POS 9
#define ESP32_GPIO_DS_MASK (0x3U << ESP32_GPIO_DS_POS)
/** @endcond */
/** Default drive strength. */
#define ESP32_GPIO_DS_DFLT (0x0U << ESP32_GPIO_DS_POS)
/** Alternative drive strength. */
#define ESP32_GPIO_DS_ALT (0x3U << ESP32_GPIO_DS_POS)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/espressif-esp32-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 245 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ITE_IT8XXX2_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ITE_IT8XXX2_GPIO_H_
/**
* @name GPIO pin voltage flags
*
* The voltage flags are a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding for use with the ITE IT8xxx2 SoCs.
*
* @{
*/
/** @cond INTERNAL_HIDDEN */
#define IT8XXX2_GPIO_VOLTAGE_POS 11
#define IT8XXX2_GPIO_VOLTAGE_MASK (3U << IT8XXX2_GPIO_VOLTAGE_POS)
/** @endcond */
/** Set pin at the default voltage level */
#define IT8XXX2_GPIO_VOLTAGE_DEFAULT (0U << IT8XXX2_GPIO_VOLTAGE_POS)
/** Set pin voltage level at 1.8 V */
#define IT8XXX2_GPIO_VOLTAGE_1P8 (1U << IT8XXX2_GPIO_VOLTAGE_POS)
/** Set pin voltage level at 3.3 V */
#define IT8XXX2_GPIO_VOLTAGE_3P3 (2U << IT8XXX2_GPIO_VOLTAGE_POS)
/** Set pin voltage level at 5.0 V */
#define IT8XXX2_GPIO_VOLTAGE_5P0 (3U << IT8XXX2_GPIO_VOLTAGE_POS)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ITE_IT8XXX2_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 308 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZT2M_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZT2M_H_
#include <zephyr/sys/util.h>
#define RZT2M_GPIO_DRIVE_OFFSET 8
#define RZT2M_GPIO_DRIVE_MASK GENMASK(RZT2M_GPIO_DRIVE_OFFSET + 2, RZT2M_GPIO_DRIVE_OFFSET)
/**
* @brief Select GPIO pin drive strength
*/
#define RZT2M_GPIO_DRIVE_LOW (0U << RZT2M_GPIO_DRIVE_OFFSET)
#define RZT2M_GPIO_DRIVE_MIDDLE (1U << RZT2M_GPIO_DRIVE_OFFSET)
#define RZT2M_GPIO_DRIVE_HIGH (2U << RZT2M_GPIO_DRIVE_OFFSET)
#define RZT2M_GPIO_DRIVE_ULTRA_HIGH (3U << RZT2M_GPIO_DRIVE_OFFSET)
#define RZT2M_GPIO_SCHMITT_TRIGGER_OFFSET 10
#define RZT2M_GPIO_SCHMITT_TRIGGER_MASK BIT(RZT2M_GPIO_SCHMITT_TRIGGER_OFFSET)
/**
* @brief Enable GPIO pin schmitt trigger
*/
#define RZT2M_GPIO_SCHMITT_TRIGGER BIT(RZT2M_GPIO_SCHMITT_TRIGGER_OFFSET)
#define RZT2M_GPIO_SLEW_RATE_OFFSET 11
#define RZT2M_GPIO_SLEW_RATE_MASK BIT(RZT2M_GPIO_SLEW_RATE_OFFSET)
/**
* @brief Select GPIO pin slew rate
*/
#define RZT2M_GPIO_SLEW_RATE_SLOW 0U
#define RZT2M_GPIO_SLEW_RATE_FAST BIT(RZT2M_GPIO_SLEW_RATE_OFFSET)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZT2M_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/renesas-rzt2m-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 400 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_KINETIS_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_KINETIS_GPIO_H_
/**
* @name GPIO drive strength flags
*
* The drive strength flags are a Zephyr specific extension of the standard GPIO
* flags specified by the Linux GPIO binding. Only applicable for NXP Kinetis
* SoCs.
*
* The interface supports two different drive strengths:
* `DFLT` - The lowest drive strength supported by the HW
* `ALT` - The highest drive strength supported by the HW
*
* @{
*/
/** @cond INTERNAL_HIDDEN */
#define KINETIS_GPIO_DS_POS 9
#define KINETIS_GPIO_DS_MASK (0x3U << KINETIS_GPIO_DS_POS)
/** @endcond */
/** Default drive strength. */
#define KINETIS_GPIO_DS_DFLT (0x0U << KINETIS_GPIO_DS_POS)
/** Alternative drive strength. */
#define KINETIS_GPIO_DS_ALT (0x3U << KINETIS_GPIO_DS_POS)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_KINETIS_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/nxp-kinetis-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 249 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_STM32_TIMER_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_STM32_TIMER_H_
/* Timer countermode values */
#define STM32_TIM_COUNTERMODE_UP 0x00000000U
#define STM32_TIM_COUNTERMODE_DOWN 0x00000010U
#define STM32_TIM_COUNTERMODE_CENTER_DOWN 0x00000020U
#define STM32_TIM_COUNTERMODE_CENTER_UP 0x00000040U
#define STM32_TIM_COUNTERMODE_CENTER_UP_DOWN 0x00000060U
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_STM32_TIMER_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/timer/stm32-timer.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_NUCLEI_SYSTIMER_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_NUCLEI_SYSTIMER_H_
/* Clock divider values */
#define NUCLEI_SYSTIMER_DIVIDER_1 0
#define NUCLEI_SYSTIMER_DIVIDER_2 1
#define NUCLEI_SYSTIMER_DIVIDER_4 2
#define NUCLEI_SYSTIMER_DIVIDER_8 3
#define NUCLEI_SYSTIMER_DIVIDER_16 4
#define NUCLEI_SYSTIMER_DIVIDER_32 5
#define NUCLEI_SYSTIMER_DIVIDER_64 6
#define NUCLEI_SYSTIMER_DIVIDER_128 7
#define NUCLEI_SYSTIMER_DIVIDER_256 8
#define NUCLEI_SYSTIMER_DIVIDER_512 9
#define NUCLEI_SYSTIMER_DIVIDER_1024 10
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_NUCLEI_SYSTIMER_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/timer/nuclei-systimer.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 244 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ESPI_NPCX_ESPI_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ESPI_NPCX_ESPI_H_
/* eSPI VW Master to Slave Register Index */
#define NPCX_VWEVMS0 0
#define NPCX_VWEVMS1 1
#define NPCX_VWEVMS2 2
#define NPCX_VWEVMS3 3
#define NPCX_VWEVMS4 4
#define NPCX_VWEVMS5 5
#define NPCX_VWEVMS6 6
#define NPCX_VWEVMS7 7
#define NPCX_VWEVMS8 8
#define NPCX_VWEVMS9 9
/* eSPI VW Slave to Master Register Index */
#define NPCX_VWEVSM0 0
#define NPCX_VWEVSM1 1
#define NPCX_VWEVSM2 2
#define NPCX_VWEVSM3 3
#define NPCX_VWEVSM4 4
#define NPCX_VWEVSM5 5
#define NPCX_VWEVSM6 6
#define NPCX_VWEVSM7 7
#define NPCX_VWEVSM8 8
#define NPCX_VWEVSM9 9
#define NPCX_VWEVSM10 10
#define NPCX_VWEVSM11 11
/* eSPI VW GPIO Slave to Master Register Index */
#define NPCX_VWGPSM0 0
#define NPCX_VWGPSM1 1
#define NPCX_VWGPSM2 2
#define NPCX_VWGPSM3 3
#define NPCX_VWGPSM4 4
#define NPCX_VWGPSM5 5
#define NPCX_VWGPSM6 6
#define NPCX_VWGPSM7 7
#define NPCX_VWGPSM8 8
#define NPCX_VWGPSM9 9
#define NPCX_VWGPSM10 10
#define NPCX_VWGPSM11 11
#define NPCX_VWGPSM12 12
#define NPCX_VWGPSM13 13
#define NPCX_VWGPSM14 14
#define NPCX_VWGPSM15 15
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ESPI_NPCX_ESPI_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/espi/npcx_espi.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 506 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M10_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M10_H_
#include <zephyr/dt-bindings/dt-util.h>
/* UART Baudrate. */
#define UBX_M10_UART_BAUDRATE_4800 0x00
#define UBX_M10_UART_BAUDRATE_9600 0x01
#define UBX_M10_UART_BAUDRATE_19200 0x02
#define UBX_M10_UART_BAUDRATE_38400 0x03
#define UBX_M10_UART_BAUDRATE_57600 0x04
#define UBX_M10_UART_BAUDRATE_115200 0x05
#define UBX_M10_UART_BAUDRATE_230400 0x06
#define UBX_M10_UART_BAUDRATE_460800 0x07
#define UBX_M10_UART_BAUDRATE_921600 0x08
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M10_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gnss/u_blox_m10.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 231 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PCIE_PCIE_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PCIE_PCIE_H_
/*
* Set the device's IRQ (in devicetree, or whatever) to PCIE_IRQ_DETECT
* if the device doesn't support MSI and we don't/can't know the wired IRQ
* allocated by the firmware ahead of time. Use of this functionality will
* generally also require CONFIG_DYNAMIC_INTERRUPTS.
*/
#define PCIE_IRQ_DETECT 0xFFFFFFFU
/*
* We represent a PCI device ID as [31:16] device ID, [15:0] vendor ID. Not
* coincidentally, this is same representation used in PCI configuration space.
*/
#define PCIE_ID_VEND_SHIFT 0U
#define PCIE_ID_VEND_MASK 0xFFFFU
#define PCIE_ID_DEV_SHIFT 16U
#define PCIE_ID_DEV_MASK 0xFFFFU
#ifdef __DTS__
#define CAST(type, v) (v)
#else
#define CAST(type, v) ((type)(v))
#endif
#define PCIE_ID(vend, dev) \
((((vend) & PCIE_ID_VEND_MASK) << PCIE_ID_VEND_SHIFT) | \
(CAST(uint32_t, (dev) & PCIE_ID_DEV_MASK) << PCIE_ID_DEV_SHIFT))
#define PCIE_ID_TO_VEND(id) (((id) >> PCIE_ID_VEND_SHIFT) & PCIE_ID_VEND_MASK)
#define PCIE_ID_TO_DEV(id) (((id) >> PCIE_ID_DEV_SHIFT) & PCIE_ID_DEV_MASK)
#define PCIE_ID_NONE PCIE_ID(0xFFFF, 0xFFFF)
#define PCIE_BDF_NONE 0xFFFFFFFFU
/*
* Since our internal representation of bus/device/function is arbitrary,
* we choose the same format employed in the x86 Configuration Address Port:
*
* [23:16] bus number, [15:11] device number, [10:8] function number
*
* All other bits must be zero.
*
* The x86 (the only arch, at present, that supports PCI) takes advantage
* of this shared format to avoid unnecessary layers of abstraction.
*/
#define PCIE_BDF_BUS_SHIFT 16U
#define PCIE_BDF_BUS_MASK 0xFFU
#define PCIE_BDF_DEV_SHIFT 11U
#define PCIE_BDF_DEV_MASK 0x1FU
#define PCIE_BDF_FUNC_SHIFT 8U
#define PCIE_BDF_FUNC_MASK 0x7U
#define PCIE_BDF(bus, dev, func) \
((((bus) & PCIE_BDF_BUS_MASK) << PCIE_BDF_BUS_SHIFT) | \
(((dev) & PCIE_BDF_DEV_MASK) << PCIE_BDF_DEV_SHIFT) | \
(((func) & PCIE_BDF_FUNC_MASK) << PCIE_BDF_FUNC_SHIFT))
#define PCIE_BDF_TO_BUS(bdf) (((bdf) >> PCIE_BDF_BUS_SHIFT) & PCIE_BDF_BUS_MASK)
#define PCIE_BDF_TO_DEV(bdf) (((bdf) >> PCIE_BDF_DEV_SHIFT) & PCIE_BDF_DEV_MASK)
#define PCIE_BDF_TO_FUNC(bdf) \
(((bdf) >> PCIE_BDF_FUNC_SHIFT) & PCIE_BDF_FUNC_MASK)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PCIE_PCIE_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/pcie/pcie.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 714 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INPUTMUX_TRIGGER_PORTS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INPUTMUX_TRIGGER_PORTS_H_
#define LPC55S69_DMA0_OTRIG_BASE 0x16000000
#define LPC55S69_DMA0_ITRIG_BASE 0x0E00000F
#define LPC55S69_DMA1_OTRIG_BASE 0x24000002
#define LPC55S69_DMA1_ITRIG_BASE 0x20000008
#define RT595_DMA0_OTRIG_BASE 0x30000000
#define RT595_DMA0_ITRIG_BASE 0x2000000E
#define RT595_DMA1_OTRIG_BASE 0x50000000
#define RT595_DMA1_ITRIG_BASE 0x4000000E
#define LPC55S36_DMA0_OTRIG_BASE 0x16000000
#define LPC55S36_DMA0_ITRIG_BASE 0x0E000011
#define LPC55S36_DMA1_OTRIG_BASE 0x24000002
#define LPC55S36_DMA1_ITRIG_BASE 0x20000008
#endif
``` | /content/code_sandbox/include/zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 249 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_MICROCHIP_XEC_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_MICROCHIP_XEC_GPIO_H_
/**
* @brief Microchip XEC GPIO bank and bit position convenience defines
*
* Microchip XEC documentation uses octal GPIO pin
* numbering. These macros do not require the user to do octal arithmetic
* to derive the pin's bit position.
*
* Example DT usage:
*
* @code{.dts}
* gpios = <MCHP_GPIO_DECODE_176 GPIO_ACTIVE_HIGH>;
* @endcode
*
* @{
*/
#define XEC_GPIO_HELPER(gpio_bank, gpio_bitpos) gpio_bank gpio_bitpos
/* bank A */
#define MCHP_GPIO_DECODE_000 XEC_GPIO_HELPER(&gpio_000_036, 0)
#define MCHP_GPIO_DECODE_001 XEC_GPIO_HELPER(&gpio_000_036, 1)
#define MCHP_GPIO_DECODE_002 XEC_GPIO_HELPER(&gpio_000_036, 2)
#define MCHP_GPIO_DECODE_003 XEC_GPIO_HELPER(&gpio_000_036, 3)
#define MCHP_GPIO_DECODE_004 XEC_GPIO_HELPER(&gpio_000_036, 4)
#define MCHP_GPIO_DECODE_005 XEC_GPIO_HELPER(&gpio_000_036, 5)
#define MCHP_GPIO_DECODE_006 XEC_GPIO_HELPER(&gpio_000_036, 6)
#define MCHP_GPIO_DECODE_007 XEC_GPIO_HELPER(&gpio_000_036, 7)
#define MCHP_GPIO_DECODE_010 XEC_GPIO_HELPER(&gpio_000_036, 8)
#define MCHP_GPIO_DECODE_011 XEC_GPIO_HELPER(&gpio_000_036, 9)
#define MCHP_GPIO_DECODE_012 XEC_GPIO_HELPER(&gpio_000_036, 10)
#define MCHP_GPIO_DECODE_013 XEC_GPIO_HELPER(&gpio_000_036, 11)
#define MCHP_GPIO_DECODE_014 XEC_GPIO_HELPER(&gpio_000_036, 12)
#define MCHP_GPIO_DECODE_015 XEC_GPIO_HELPER(&gpio_000_036, 13)
#define MCHP_GPIO_DECODE_016 XEC_GPIO_HELPER(&gpio_000_036, 14)
#define MCHP_GPIO_DECODE_017 XEC_GPIO_HELPER(&gpio_000_036, 15)
#define MCHP_GPIO_DECODE_020 XEC_GPIO_HELPER(&gpio_000_036, 16)
#define MCHP_GPIO_DECODE_021 XEC_GPIO_HELPER(&gpio_000_036, 17)
#define MCHP_GPIO_DECODE_022 XEC_GPIO_HELPER(&gpio_000_036, 18)
#define MCHP_GPIO_DECODE_023 XEC_GPIO_HELPER(&gpio_000_036, 19)
#define MCHP_GPIO_DECODE_024 XEC_GPIO_HELPER(&gpio_000_036, 20)
#define MCHP_GPIO_DECODE_025 XEC_GPIO_HELPER(&gpio_000_036, 21)
#define MCHP_GPIO_DECODE_026 XEC_GPIO_HELPER(&gpio_000_036, 22)
#define MCHP_GPIO_DECODE_027 XEC_GPIO_HELPER(&gpio_000_036, 23)
#define MCHP_GPIO_DECODE_030 XEC_GPIO_HELPER(&gpio_000_036, 24)
#define MCHP_GPIO_DECODE_031 XEC_GPIO_HELPER(&gpio_000_036, 25)
#define MCHP_GPIO_DECODE_032 XEC_GPIO_HELPER(&gpio_000_036, 26)
#define MCHP_GPIO_DECODE_033 XEC_GPIO_HELPER(&gpio_000_036, 27)
#define MCHP_GPIO_DECODE_034 XEC_GPIO_HELPER(&gpio_000_036, 28)
#define MCHP_GPIO_DECODE_035 XEC_GPIO_HELPER(&gpio_000_036, 29)
#define MCHP_GPIO_DECODE_036 XEC_GPIO_HELPER(&gpio_000_036, 30)
/* bank B */
#define MCHP_GPIO_DECODE_040 XEC_GPIO_HELPER(&gpio_040_076, 0)
#define MCHP_GPIO_DECODE_041 XEC_GPIO_HELPER(&gpio_040_076, 1)
#define MCHP_GPIO_DECODE_042 XEC_GPIO_HELPER(&gpio_040_076, 2)
#define MCHP_GPIO_DECODE_043 XEC_GPIO_HELPER(&gpio_040_076, 3)
#define MCHP_GPIO_DECODE_044 XEC_GPIO_HELPER(&gpio_040_076, 4)
#define MCHP_GPIO_DECODE_045 XEC_GPIO_HELPER(&gpio_040_076, 5)
#define MCHP_GPIO_DECODE_046 XEC_GPIO_HELPER(&gpio_040_076, 6)
#define MCHP_GPIO_DECODE_047 XEC_GPIO_HELPER(&gpio_040_076, 7)
#define MCHP_GPIO_DECODE_050 XEC_GPIO_HELPER(&gpio_040_076, 8)
#define MCHP_GPIO_DECODE_051 XEC_GPIO_HELPER(&gpio_040_076, 9)
#define MCHP_GPIO_DECODE_052 XEC_GPIO_HELPER(&gpio_040_076, 10)
#define MCHP_GPIO_DECODE_053 XEC_GPIO_HELPER(&gpio_040_076, 11)
#define MCHP_GPIO_DECODE_054 XEC_GPIO_HELPER(&gpio_040_076, 12)
#define MCHP_GPIO_DECODE_055 XEC_GPIO_HELPER(&gpio_040_076, 13)
#define MCHP_GPIO_DECODE_056 XEC_GPIO_HELPER(&gpio_040_076, 14)
#define MCHP_GPIO_DECODE_057 XEC_GPIO_HELPER(&gpio_040_076, 15)
#define MCHP_GPIO_DECODE_060 XEC_GPIO_HELPER(&gpio_040_076, 16)
#define MCHP_GPIO_DECODE_061 XEC_GPIO_HELPER(&gpio_040_076, 17)
#define MCHP_GPIO_DECODE_062 XEC_GPIO_HELPER(&gpio_040_076, 18)
#define MCHP_GPIO_DECODE_063 XEC_GPIO_HELPER(&gpio_040_076, 19)
#define MCHP_GPIO_DECODE_064 XEC_GPIO_HELPER(&gpio_040_076, 20)
#define MCHP_GPIO_DECODE_065 XEC_GPIO_HELPER(&gpio_040_076, 21)
#define MCHP_GPIO_DECODE_066 XEC_GPIO_HELPER(&gpio_040_076, 22)
#define MCHP_GPIO_DECODE_067 XEC_GPIO_HELPER(&gpio_040_076, 23)
#define MCHP_GPIO_DECODE_070 XEC_GPIO_HELPER(&gpio_040_076, 24)
#define MCHP_GPIO_DECODE_071 XEC_GPIO_HELPER(&gpio_040_076, 25)
#define MCHP_GPIO_DECODE_072 XEC_GPIO_HELPER(&gpio_040_076, 26)
#define MCHP_GPIO_DECODE_073 XEC_GPIO_HELPER(&gpio_040_076, 27)
#define MCHP_GPIO_DECODE_074 XEC_GPIO_HELPER(&gpio_040_076, 28)
#define MCHP_GPIO_DECODE_075 XEC_GPIO_HELPER(&gpio_040_076, 29)
#define MCHP_GPIO_DECODE_076 XEC_GPIO_HELPER(&gpio_040_076, 30)
/* bank C */
#define MCHP_GPIO_DECODE_100 XEC_GPIO_HELPER(&gpio_100_136, 0)
#define MCHP_GPIO_DECODE_101 XEC_GPIO_HELPER(&gpio_100_136, 1)
#define MCHP_GPIO_DECODE_102 XEC_GPIO_HELPER(&gpio_100_136, 2)
#define MCHP_GPIO_DECODE_103 XEC_GPIO_HELPER(&gpio_100_136, 3)
#define MCHP_GPIO_DECODE_104 XEC_GPIO_HELPER(&gpio_100_136, 4)
#define MCHP_GPIO_DECODE_105 XEC_GPIO_HELPER(&gpio_100_136, 5)
#define MCHP_GPIO_DECODE_106 XEC_GPIO_HELPER(&gpio_100_136, 6)
#define MCHP_GPIO_DECODE_107 XEC_GPIO_HELPER(&gpio_100_136, 7)
#define MCHP_GPIO_DECODE_110 XEC_GPIO_HELPER(&gpio_100_136, 8)
#define MCHP_GPIO_DECODE_111 XEC_GPIO_HELPER(&gpio_100_136, 9)
#define MCHP_GPIO_DECODE_112 XEC_GPIO_HELPER(&gpio_100_136, 10)
#define MCHP_GPIO_DECODE_113 XEC_GPIO_HELPER(&gpio_100_136, 11)
#define MCHP_GPIO_DECODE_114 XEC_GPIO_HELPER(&gpio_100_136, 12)
#define MCHP_GPIO_DECODE_115 XEC_GPIO_HELPER(&gpio_100_136, 13)
#define MCHP_GPIO_DECODE_116 XEC_GPIO_HELPER(&gpio_100_136, 14)
#define MCHP_GPIO_DECODE_117 XEC_GPIO_HELPER(&gpio_100_136, 15)
#define MCHP_GPIO_DECODE_120 XEC_GPIO_HELPER(&gpio_100_136, 16)
#define MCHP_GPIO_DECODE_121 XEC_GPIO_HELPER(&gpio_100_136, 17)
#define MCHP_GPIO_DECODE_122 XEC_GPIO_HELPER(&gpio_100_136, 18)
#define MCHP_GPIO_DECODE_123 XEC_GPIO_HELPER(&gpio_100_136, 19)
#define MCHP_GPIO_DECODE_124 XEC_GPIO_HELPER(&gpio_100_136, 20)
#define MCHP_GPIO_DECODE_125 XEC_GPIO_HELPER(&gpio_100_136, 21)
#define MCHP_GPIO_DECODE_126 XEC_GPIO_HELPER(&gpio_100_136, 22)
#define MCHP_GPIO_DECODE_127 XEC_GPIO_HELPER(&gpio_100_136, 23)
#define MCHP_GPIO_DECODE_130 XEC_GPIO_HELPER(&gpio_100_136, 24)
#define MCHP_GPIO_DECODE_131 XEC_GPIO_HELPER(&gpio_100_136, 25)
#define MCHP_GPIO_DECODE_132 XEC_GPIO_HELPER(&gpio_100_136, 26)
#define MCHP_GPIO_DECODE_133 XEC_GPIO_HELPER(&gpio_100_136, 27)
#define MCHP_GPIO_DECODE_134 XEC_GPIO_HELPER(&gpio_100_136, 28)
#define MCHP_GPIO_DECODE_135 XEC_GPIO_HELPER(&gpio_100_136, 29)
#define MCHP_GPIO_DECODE_136 XEC_GPIO_HELPER(&gpio_100_136, 30)
/* bank D */
#define MCHP_GPIO_DECODE_140 XEC_GPIO_HELPER(&gpio_140_176, 0)
#define MCHP_GPIO_DECODE_141 XEC_GPIO_HELPER(&gpio_140_176, 1)
#define MCHP_GPIO_DECODE_142 XEC_GPIO_HELPER(&gpio_140_176, 2)
#define MCHP_GPIO_DECODE_143 XEC_GPIO_HELPER(&gpio_140_176, 3)
#define MCHP_GPIO_DECODE_144 XEC_GPIO_HELPER(&gpio_140_176, 4)
#define MCHP_GPIO_DECODE_145 XEC_GPIO_HELPER(&gpio_140_176, 5)
#define MCHP_GPIO_DECODE_146 XEC_GPIO_HELPER(&gpio_140_176, 6)
#define MCHP_GPIO_DECODE_147 XEC_GPIO_HELPER(&gpio_140_176, 7)
#define MCHP_GPIO_DECODE_150 XEC_GPIO_HELPER(&gpio_140_176, 8)
#define MCHP_GPIO_DECODE_151 XEC_GPIO_HELPER(&gpio_140_176, 9)
#define MCHP_GPIO_DECODE_152 XEC_GPIO_HELPER(&gpio_140_176, 10)
#define MCHP_GPIO_DECODE_153 XEC_GPIO_HELPER(&gpio_140_176, 11)
#define MCHP_GPIO_DECODE_154 XEC_GPIO_HELPER(&gpio_140_176, 12)
#define MCHP_GPIO_DECODE_155 XEC_GPIO_HELPER(&gpio_140_176, 13)
#define MCHP_GPIO_DECODE_156 XEC_GPIO_HELPER(&gpio_140_176, 14)
#define MCHP_GPIO_DECODE_157 XEC_GPIO_HELPER(&gpio_140_176, 15)
#define MCHP_GPIO_DECODE_160 XEC_GPIO_HELPER(&gpio_140_176, 16)
#define MCHP_GPIO_DECODE_161 XEC_GPIO_HELPER(&gpio_140_176, 17)
#define MCHP_GPIO_DECODE_162 XEC_GPIO_HELPER(&gpio_140_176, 18)
#define MCHP_GPIO_DECODE_163 XEC_GPIO_HELPER(&gpio_140_176, 19)
#define MCHP_GPIO_DECODE_164 XEC_GPIO_HELPER(&gpio_140_176, 20)
#define MCHP_GPIO_DECODE_165 XEC_GPIO_HELPER(&gpio_140_176, 21)
#define MCHP_GPIO_DECODE_166 XEC_GPIO_HELPER(&gpio_140_176, 22)
#define MCHP_GPIO_DECODE_167 XEC_GPIO_HELPER(&gpio_140_176, 23)
#define MCHP_GPIO_DECODE_170 XEC_GPIO_HELPER(&gpio_140_176, 24)
#define MCHP_GPIO_DECODE_171 XEC_GPIO_HELPER(&gpio_140_176, 25)
#define MCHP_GPIO_DECODE_172 XEC_GPIO_HELPER(&gpio_140_176, 26)
#define MCHP_GPIO_DECODE_173 XEC_GPIO_HELPER(&gpio_140_176, 27)
#define MCHP_GPIO_DECODE_174 XEC_GPIO_HELPER(&gpio_140_176, 28)
#define MCHP_GPIO_DECODE_175 XEC_GPIO_HELPER(&gpio_140_176, 29)
#define MCHP_GPIO_DECODE_176 XEC_GPIO_HELPER(&gpio_140_176, 30)
/* bank E */
#define MCHP_GPIO_DECODE_200 XEC_GPIO_HELPER(&gpio_200_236, 0)
#define MCHP_GPIO_DECODE_201 XEC_GPIO_HELPER(&gpio_200_236, 1)
#define MCHP_GPIO_DECODE_202 XEC_GPIO_HELPER(&gpio_200_236, 2)
#define MCHP_GPIO_DECODE_203 XEC_GPIO_HELPER(&gpio_200_236, 3)
#define MCHP_GPIO_DECODE_204 XEC_GPIO_HELPER(&gpio_200_236, 4)
#define MCHP_GPIO_DECODE_205 XEC_GPIO_HELPER(&gpio_200_236, 5)
#define MCHP_GPIO_DECODE_206 XEC_GPIO_HELPER(&gpio_200_236, 6)
#define MCHP_GPIO_DECODE_207 XEC_GPIO_HELPER(&gpio_200_236, 7)
#define MCHP_GPIO_DECODE_210 XEC_GPIO_HELPER(&gpio_200_236, 8)
#define MCHP_GPIO_DECODE_211 XEC_GPIO_HELPER(&gpio_200_236, 9)
#define MCHP_GPIO_DECODE_212 XEC_GPIO_HELPER(&gpio_200_236, 10)
#define MCHP_GPIO_DECODE_213 XEC_GPIO_HELPER(&gpio_200_236, 11)
#define MCHP_GPIO_DECODE_214 XEC_GPIO_HELPER(&gpio_200_236, 12)
#define MCHP_GPIO_DECODE_215 XEC_GPIO_HELPER(&gpio_200_236, 13)
#define MCHP_GPIO_DECODE_216 XEC_GPIO_HELPER(&gpio_200_236, 14)
#define MCHP_GPIO_DECODE_217 XEC_GPIO_HELPER(&gpio_200_236, 15)
#define MCHP_GPIO_DECODE_220 XEC_GPIO_HELPER(&gpio_200_236, 16)
#define MCHP_GPIO_DECODE_221 XEC_GPIO_HELPER(&gpio_200_236, 17)
#define MCHP_GPIO_DECODE_222 XEC_GPIO_HELPER(&gpio_200_236, 18)
#define MCHP_GPIO_DECODE_223 XEC_GPIO_HELPER(&gpio_200_236, 19)
#define MCHP_GPIO_DECODE_224 XEC_GPIO_HELPER(&gpio_200_236, 20)
#define MCHP_GPIO_DECODE_225 XEC_GPIO_HELPER(&gpio_200_236, 21)
#define MCHP_GPIO_DECODE_226 XEC_GPIO_HELPER(&gpio_200_236, 22)
#define MCHP_GPIO_DECODE_227 XEC_GPIO_HELPER(&gpio_200_236, 23)
#define MCHP_GPIO_DECODE_230 XEC_GPIO_HELPER(&gpio_200_236, 24)
#define MCHP_GPIO_DECODE_231 XEC_GPIO_HELPER(&gpio_200_236, 25)
#define MCHP_GPIO_DECODE_232 XEC_GPIO_HELPER(&gpio_200_236, 26)
#define MCHP_GPIO_DECODE_233 XEC_GPIO_HELPER(&gpio_200_236, 27)
#define MCHP_GPIO_DECODE_234 XEC_GPIO_HELPER(&gpio_200_236, 28)
#define MCHP_GPIO_DECODE_235 XEC_GPIO_HELPER(&gpio_200_236, 29)
#define MCHP_GPIO_DECODE_236 XEC_GPIO_HELPER(&gpio_200_236, 30)
/* bank F */
#define MCHP_GPIO_DECODE_240 XEC_GPIO_HELPER(&gpio_240_276, 0)
#define MCHP_GPIO_DECODE_241 XEC_GPIO_HELPER(&gpio_240_276, 1)
#define MCHP_GPIO_DECODE_242 XEC_GPIO_HELPER(&gpio_240_276, 2)
#define MCHP_GPIO_DECODE_243 XEC_GPIO_HELPER(&gpio_240_276, 3)
#define MCHP_GPIO_DECODE_244 XEC_GPIO_HELPER(&gpio_240_276, 4)
#define MCHP_GPIO_DECODE_245 XEC_GPIO_HELPER(&gpio_240_276, 5)
#define MCHP_GPIO_DECODE_246 XEC_GPIO_HELPER(&gpio_240_276, 6)
#define MCHP_GPIO_DECODE_247 XEC_GPIO_HELPER(&gpio_240_276, 7)
#define MCHP_GPIO_DECODE_250 XEC_GPIO_HELPER(&gpio_240_276, 8)
#define MCHP_GPIO_DECODE_251 XEC_GPIO_HELPER(&gpio_240_276, 9)
#define MCHP_GPIO_DECODE_252 XEC_GPIO_HELPER(&gpio_240_276, 10)
#define MCHP_GPIO_DECODE_253 XEC_GPIO_HELPER(&gpio_240_276, 11)
#define MCHP_GPIO_DECODE_254 XEC_GPIO_HELPER(&gpio_240_276, 12)
#define MCHP_GPIO_DECODE_255 XEC_GPIO_HELPER(&gpio_240_276, 13)
#define MCHP_GPIO_DECODE_256 XEC_GPIO_HELPER(&gpio_240_276, 14)
#define MCHP_GPIO_DECODE_257 XEC_GPIO_HELPER(&gpio_240_276, 15)
#define MCHP_GPIO_DECODE_260 XEC_GPIO_HELPER(&gpio_240_276, 16)
#define MCHP_GPIO_DECODE_261 XEC_GPIO_HELPER(&gpio_240_276, 17)
#define MCHP_GPIO_DECODE_262 XEC_GPIO_HELPER(&gpio_240_276, 18)
#define MCHP_GPIO_DECODE_263 XEC_GPIO_HELPER(&gpio_240_276, 19)
#define MCHP_GPIO_DECODE_264 XEC_GPIO_HELPER(&gpio_240_276, 20)
#define MCHP_GPIO_DECODE_265 XEC_GPIO_HELPER(&gpio_240_276, 21)
#define MCHP_GPIO_DECODE_266 XEC_GPIO_HELPER(&gpio_240_276, 22)
#define MCHP_GPIO_DECODE_267 XEC_GPIO_HELPER(&gpio_240_276, 23)
#define MCHP_GPIO_DECODE_270 XEC_GPIO_HELPER(&gpio_240_276, 24)
#define MCHP_GPIO_DECODE_271 XEC_GPIO_HELPER(&gpio_240_276, 25)
#define MCHP_GPIO_DECODE_272 XEC_GPIO_HELPER(&gpio_240_276, 26)
#define MCHP_GPIO_DECODE_273 XEC_GPIO_HELPER(&gpio_240_276, 27)
#define MCHP_GPIO_DECODE_274 XEC_GPIO_HELPER(&gpio_240_276, 28)
#define MCHP_GPIO_DECODE_275 XEC_GPIO_HELPER(&gpio_240_276, 29)
#define MCHP_GPIO_DECODE_276 XEC_GPIO_HELPER(&gpio_240_276, 30)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_MICROCHIP_XEC_GPIO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/gpio/microchip-xec-gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,478 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DU12_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DU12_H_
/* Accel range */
#define LIS2DU12_DT_FS_2G 0
#define LIS2DU12_DT_FS_4G 1
#define LIS2DU12_DT_FS_8G 2
#define LIS2DU12_DT_FS_16G 3
/* Accel rates */
#define LIS2DU12_DT_ODR_OFF 0x00 /* Power-Down */
#define LIS2DU12_DT_ODR_AT_1Hz6_ULP 0x01 /* 1Hz6 (ultra low power) */
#define LIS2DU12_DT_ODR_AT_3Hz_ULP 0x02 /* 3Hz (ultra low power) */
#define LIS2DU12_DT_ODR_AT_6Hz_ULP 0x03 /* 6Hz (ultra low power) */
#define LIS2DU12_DT_ODR_AT_6Hz 0x04 /* 6Hz (normal) */
#define LIS2DU12_DT_ODR_AT_12Hz 0x05 /* 12Hz5 (normal) */
#define LIS2DU12_DT_ODR_AT_25Hz 0x06 /* 25Hz (normal) */
#define LIS2DU12_DT_ODR_AT_50Hz 0x07 /* 50Hz (normal) */
#define LIS2DU12_DT_ODR_AT_100Hz 0x08 /* 100Hz (normal) */
#define LIS2DU12_DT_ODR_AT_200Hz 0x09 /* 200Hz (normal) */
#define LIS2DU12_DT_ODR_AT_400Hz 0x0a /* 400Hz (normal) */
#define LIS2DU12_DT_ODR_AT_800Hz 0x0b /* 800Hz (normal) */
#define LIS2DU12_DT_ODR_TRIG_PIN 0x0e /* Single-shot high latency by INT2 */
#define LIS2DU12_DT_ODR_TRIG_SW 0x0f /* Single-shot high latency by IF */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DU12_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lis2du12.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 492 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM9DS1_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM9DS1_H_
/* Accel range */
#define LSM9DS1_DT_FS_2G 0
#define LSM9DS1_DT_FS_16G 1
#define LSM9DS1_DT_FS_4G 2
#define LSM9DS1_DT_FS_8G 3
#define LSM9DS1_DT_FS_245DPS 0
#define LSM9DS1_DT_FS_500DPS 1
#define LSM9DS1_DT_FS_2000DPS 3
#define LSM9DS1_IMU_OFF 0x00
#define LSM9DS1_GY_OFF_XL_10Hz 0x10
#define LSM9DS1_GY_OFF_XL_50Hz 0x20
#define LSM9DS1_GY_OFF_XL_119Hz 0x30
#define LSM9DS1_GY_OFF_XL_238Hz 0x40
#define LSM9DS1_GY_OFF_XL_476Hz 0x50
#define LSM9DS1_GY_OFF_XL_952Hz 0x60
#define LSM9DS1_XL_OFF_GY_14Hz9 0x01
#define LSM9DS1_XL_OFF_GY_59Hz5 0x02
#define LSM9DS1_XL_OFF_GY_119Hz 0x03
#define LSM9DS1_XL_OFF_GY_238Hz 0x04
#define LSM9DS1_XL_OFF_GY_476Hz 0x05
#define LSM9DS1_XL_OFF_GY_952Hz 0x06
#define LSM9DS1_IMU_14Hz9 0x11
#define LSM9DS1_IMU_59Hz5 0x22
#define LSM9DS1_IMU_119Hz 0x33
#define LSM9DS1_IMU_238Hz 0x44
#define LSM9DS1_IMU_476Hz 0x55
#define LSM9DS1_IMU_952Hz 0x66
#define LSM9DS1_XL_OFF_GY_14Hz9_LP 0x81
#define LSM9DS1_XL_OFF_GY_59Hz5_LP 0x82
#define LSM9DS1_XL_OFF_GY_119Hz_LP 0x83
#define LSM9DS1_IMU_14Hz9_LP 0x91
#define LSM9DS1_IMU_59Hz5_LP 0xA2
#define LSM9DS1_IMU_119Hz_LP 0xB3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM9DS1_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lsm9ds1.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 616 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_IIS2ICLX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_IIS2ICLX_H_
/* Accel range */
#define IIS2ICLX_DT_FS_500mG 0
#define IIS2ICLX_DT_FS_3G 1
#define IIS2ICLX_DT_FS_1G 2
#define IIS2ICLX_DT_FS_2G 3
/* Accel Data rates */
#define IIS2ICLX_DT_ODR_OFF 0x0
#define IIS2ICLX_DT_ODR_12Hz5 0x1
#define IIS2ICLX_DT_ODR_26H 0x2
#define IIS2ICLX_DT_ODR_52Hz 0x3
#define IIS2ICLX_DT_ODR_104Hz 0x4
#define IIS2ICLX_DT_ODR_208Hz 0x5
#define IIS2ICLX_DT_ODR_416Hz 0x6
#define IIS2ICLX_DT_ODR_833Hz 0x7
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_IIS2ICLX_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/iis2iclx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 287 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSO_H_
/* Accel power-modes */
#define LSM6DSO_DT_XL_HP_MODE 0
#define LSM6DSO_DT_XL_LP_NORMAL_MODE 1
#define LSM6DSO_DT_XL_ULP_MODE 2
/* Gyro power-modes */
#define LSM6DSO_DT_GY_HP_MODE 0
#define LSM6DSO_DT_GY_NORMAL_MODE 1
/* Accel range */
#define LSM6DSO_DT_FS_2G 0
#define LSM6DSO_DT_FS_16G 1
#define LSM6DSO_DT_FS_4G 2
#define LSM6DSO_DT_FS_8G 3
/* Gyro range */
#define LSM6DSO_DT_FS_250DPS 0
#define LSM6DSO_DT_FS_125DPS 1
#define LSM6DSO_DT_FS_500DPS 2
#define LSM6DSO_DT_FS_1000DPS 4
#define LSM6DSO_DT_FS_2000DPS 6
/* Accel and Gyro Data rates */
#define LSM6DSO_DT_ODR_OFF 0x0
#define LSM6DSO_DT_ODR_12Hz5 0x1
#define LSM6DSO_DT_ODR_26H 0x2
#define LSM6DSO_DT_ODR_52Hz 0x3
#define LSM6DSO_DT_ODR_104Hz 0x4
#define LSM6DSO_DT_ODR_208Hz 0x5
#define LSM6DSO_DT_ODR_417Hz 0x6
#define LSM6DSO_DT_ODR_833Hz 0x7
#define LSM6DSO_DT_ODR_1667Hz 0x8
#define LSM6DSO_DT_ODR_3333Hz 0x9
#define LSM6DSO_DT_ODR_6667Hz 0xa
#define LSM6DSO_DT_ODR_1Hz6 0xb
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSO_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lsm6dso.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 500 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LPS22HH_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LPS22HH_H_
/* Data rate */
#define LPS22HH_DT_ODR_POWER_DOWN 0
#define LPS22HH_DT_ODR_1HZ 1
#define LPS22HH_DT_ODR_10HZ 2
#define LPS22HH_DT_ODR_25HZ 3
#define LPS22HH_DT_ODR_50HZ 4
#define LPS22HH_DT_ODR_75HZ 5
#define LPS22HH_DT_ODR_100HZ 6
#define LPS22HH_DT_ODR_200HZ 7
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LPS22HH_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lps22hh.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 177 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TMAG5273_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_TMAG5273_H_
#include <zephyr/dt-bindings/dt-util.h>
/* Operating Mode */
#define TMAG5273_DT_OPER_MODE_CONTINUOUS 0
#define TMAG5273_DT_OPER_MODE_STANDBY 1
/* Axis */
#define TMAG5273_DT_AXIS_NONE 0x0
#define TMAG5273_DT_AXIS_X 0x1
#define TMAG5273_DT_AXIS_Y 0x2
#define TMAG5273_DT_AXIS_Z 0x4
#define TMAG5273_DT_AXIS_XY (TMAG5273_DT_AXIS_X | TMAG5273_DT_AXIS_Y)
#define TMAG5273_DT_AXIS_XZ (TMAG5273_DT_AXIS_X | TMAG5273_DT_AXIS_Z)
#define TMAG5273_DT_AXIS_YZ (TMAG5273_DT_AXIS_Y | TMAG5273_DT_AXIS_Z)
#define TMAG5273_DT_AXIS_XYZ (TMAG5273_DT_AXIS_X | TMAG5273_DT_AXIS_Y | TMAG5273_DT_AXIS_Z)
#define TMAG5273_DT_AXIS_XYX 0x8
#define TMAG5273_DT_AXIS_YXY 0x9
#define TMAG5273_DT_AXIS_YZY 0xA
#define TMAG5273_DT_AXIS_XZX 0xB
/* Range */
#define TMAG5273_DT_AXIS_RANGE_LOW 0
#define TMAG5273_DT_AXIS_RANGE_HIGH 1
#define TMAG5273_DT_AXIS_RANGE_RUNTIME 2
/* Interrupt-Mode */
#define TMAG5273_DT_INT_THROUGH_INT 0
#define TMAG5273_DT_INT_THROUGH_INT_EXC_I2C 1
#define TMAG5273_DT_INT_THROUGH_SCL 2
#define TMAG5273_DT_INT_THROUGH_SCL_EXC_I2C 3
/* Threshold crossings */
#define TMAG5273_DT_THRX_COUNT_1 0
#define TMAG5273_DT_THRX_COUNT_4 1
/* Threshold direction */
#define TMAG5273_DT_THRX_ABOVE 0
#define TMAG5273_DT_THRX_BELOW 1
#define TMAG5273_DT_THRX_OUTSIDE 2
#define TMAG5273_DT_THRX_INSIDE 3
/* Temperature coefficient */
#define TMAG5273_DT_TEMP_COEFF_NONE 0
#define TMAG5273_DT_TEMP_COEFF_NDBFE 1
#define TMAG5273_DT_TEMP_COEFF_CERAMIC 2
/* Angle/Magnitude calculation */
#define TMAG5273_DT_ANGLE_MAG_NONE 0
#define TMAG5273_DT_ANGLE_MAG_XY 1
#define TMAG5273_DT_ANGLE_MAG_YZ 2
#define TMAG5273_DT_ANGLE_MAG_XZ 3
#define TMAG5273_DT_ANGLE_MAG_RUNTIME 4
/* Channel Magnitude Gain Correction */
#define TMAG5273_DT_CORRECTION_CH_1 0
#define TMAG5273_DT_CORRECTION_CH_2 1
/* Averaging */
#define TMAG5273_DT_AVERAGING_NONE 0
#define TMAG5273_DT_AVERAGING_2X 1
#define TMAG5273_DT_AVERAGING_4X 2
#define TMAG5273_DT_AVERAGING_8X 3
#define TMAG5273_DT_AVERAGING_16X 4
#define TMAG5273_DT_AVERAGING_32X 5
/* Sleeptime */
#define TMAG5273_DT_SLEEPTIME_1MS 0
#define TMAG5273_DT_SLEEPTIME_5MS 1
#define TMAG5273_DT_SLEEPTIME_10MS 2
#define TMAG5273_DT_SLEEPTIME_15MS 3
#define TMAG5273_DT_SLEEPTIME_20MS 4
#define TMAG5273_DT_SLEEPTIME_30MS 5
#define TMAG5273_DT_SLEEPTIME_50MS 6
#define TMAG5273_DT_SLEEPTIME_100MS 7
#define TMAG5273_DT_SLEEPTIME_500MS 8
#define TMAG5273_DT_SLEEPTIME_1000MS 9
#define TMAG5273_DT_SLEEPTIME_2000MS 10
#define TMAG5273_DT_SLEEPTIME_5000MS 11
#define TMAG5273_DT_SLEEPTIME_20000MS 12
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TMAG5273_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/tmag5273.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,019 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSO16IS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSO16IS_H_
/* Accel range */
#define LSM6DSO16IS_DT_FS_2G 0
#define LSM6DSO16IS_DT_FS_16G 1
#define LSM6DSO16IS_DT_FS_4G 2
#define LSM6DSO16IS_DT_FS_8G 3
/* Gyro range */
#define LSM6DSO16IS_DT_FS_250DPS 0x0
#define LSM6DSO16IS_DT_FS_500DPS 0x1
#define LSM6DSO16IS_DT_FS_1000DPS 0x2
#define LSM6DSO16IS_DT_FS_2000DPS 0x3
#define LSM6DSO16IS_DT_FS_125DPS 0x10
/* Accel and Gyro Data rates */
#define LSM6DSO16IS_DT_ODR_OFF 0x0
#define LSM6DSO16IS_DT_ODR_12Hz5_HP 0x1
#define LSM6DSO16IS_DT_ODR_26H_HP 0x2
#define LSM6DSO16IS_DT_ODR_52Hz_HP 0x3
#define LSM6DSO16IS_DT_ODR_104Hz_HP 0x4
#define LSM6DSO16IS_DT_ODR_208Hz_HP 0x5
#define LSM6DSO16IS_DT_ODR_416Hz_HP 0x6
#define LSM6DSO16IS_DT_ODR_833Hz_HP 0x7
#define LSM6DSO16IS_DT_ODR_1667Hz_HP 0x8
#define LSM6DSO16IS_DT_ODR_3333Hz_HP 0x9
#define LSM6DSO16IS_DT_ODR_6667Hz_HP 0xa
#define LSM6DSO16IS_DT_ODR_12Hz5_LP 0x11
#define LSM6DSO16IS_DT_ODR_26H_LP 0x12
#define LSM6DSO16IS_DT_ODR_52Hz_LP 0x13
#define LSM6DSO16IS_DT_ODR_104Hz_LP 0x14
#define LSM6DSO16IS_DT_ODR_208Hz_LP 0x15
#define LSM6DSO16IS_DT_ODR_416Hz_LP 0x16
#define LSM6DSO16IS_DT_ODR_833Hz_LP 0x17
#define LSM6DSO16IS_DT_ODR_1667Hz_LP 0x18
#define LSM6DSO16IS_DT_ODR_3333Hz_LP 0x19
#define LSM6DSO16IS_DT_ODR_6667Hz_LP 0x1a
#define LSM6DSO16IS_DT_ODR_1Hz6_LP 0x1b
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSO16IS_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lsm6dso16is.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 708 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TDK_ICM42688P_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_TDK_ICM42688P_H_
/**
* @defgroup ICM42688 Invensense (TDK) ICM42688 DT Options
* @ingroup sensor_interface
* @{
*/
/**
* @defgroup ICM42688_ACCEL_POWER_MODES Accelerometer power modes
* @{
*/
#define ICM42688_DT_ACCEL_OFF 0
#define ICM42688_DT_ACCEL_LP 2
#define ICM42688_DT_ACCEL_LN 3
/** @} */
/**
* @defgroup ICM42688_GYRO_POWER_MODES Gyroscope power modes
* @{
*/
#define ICM42688_DT_GYRO_OFF 0
#define ICM42688_DT_GYRO_STANDBY 1
#define ICM42688_DT_GYRO_LN 3
/** @} */
/**
* @defgroup ICM42688_ACCEL_SCALE Accelerometer scale options
* @{
*/
#define ICM42688_DT_ACCEL_FS_16 0
#define ICM42688_DT_ACCEL_FS_8 1
#define ICM42688_DT_ACCEL_FS_4 2
#define ICM42688_DT_ACCEL_FS_2 3
/** @} */
/**
* @defgroup ICM42688_GYRO_SCALE Gyroscope scale options
* @{
*/
#define ICM42688_DT_GYRO_FS_2000 0
#define ICM42688_DT_GYRO_FS_1000 1
#define ICM42688_DT_GYRO_FS_500 2
#define ICM42688_DT_GYRO_FS_250 3
#define ICM42688_DT_GYRO_FS_125 4
#define ICM42688_DT_GYRO_FS_62_5 5
#define ICM42688_DT_GYRO_FS_31_25 6
#define ICM42688_DT_GYRO_FS_15_625 7
/** @} */
/**
* @defgroup ICM42688_ACCEL_DATA_RATE Accelerometer data rate options
* @{
*/
#define ICM42688_DT_ACCEL_ODR_32000 1
#define ICM42688_DT_ACCEL_ODR_16000 2
#define ICM42688_DT_ACCEL_ODR_8000 3
#define ICM42688_DT_ACCEL_ODR_4000 4
#define ICM42688_DT_ACCEL_ODR_2000 5
#define ICM42688_DT_ACCEL_ODR_1000 6
#define ICM42688_DT_ACCEL_ODR_200 7
#define ICM42688_DT_ACCEL_ODR_100 8
#define ICM42688_DT_ACCEL_ODR_50 9
#define ICM42688_DT_ACCEL_ODR_25 10
#define ICM42688_DT_ACCEL_ODR_12_5 11
#define ICM42688_DT_ACCEL_ODR_6_25 12
#define ICM42688_DT_ACCEL_ODR_3_125 13
#define ICM42688_DT_ACCEL_ODR_1_5625 14
#define ICM42688_DT_ACCEL_ODR_500 15
/** @} */
/**
* @defgroup ICM42688_GYRO_DATA_RATE Gyroscope data rate options
* @{
*/
#define ICM42688_DT_GYRO_ODR_32000 1
#define ICM42688_DT_GYRO_ODR_16000 2
#define ICM42688_DT_GYRO_ODR_8000 3
#define ICM42688_DT_GYRO_ODR_4000 4
#define ICM42688_DT_GYRO_ODR_2000 5
#define ICM42688_DT_GYRO_ODR_1000 6
#define ICM42688_DT_GYRO_ODR_200 7
#define ICM42688_DT_GYRO_ODR_100 8
#define ICM42688_DT_GYRO_ODR_50 9
#define ICM42688_DT_GYRO_ODR_25 10
#define ICM42688_DT_GYRO_ODR_12_5 11
#define ICM42688_DT_GYRO_ODR_500 15
/** @} */
/** @} */
#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_TDK_ICM42688P_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/icm42688.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 958 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INA237_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INA237_H_
#include <zephyr/dt-bindings/dt-util.h>
/* Operating Mode */
#define INA237_CFG_HIGH_PRECISION BIT(4)
#define INA237_OPER_MODE_SHUTDOWN 0x00
#define INA237_OPER_MODE_BUS_VOLTAGE_TRIG 0x01
#define INA237_OPER_MODE_SHUNT_VOLTAGE_TRIG 0x02
#define INA237_OPER_MODE_SHUNT_BUS_VOLTAGE_TRIG 0x03
#define INA237_OPER_MODE_TEMP_TRIG 0x04
#define INA237_OPER_MODE_TEMP_BUS_VOLTAGE_TRIG 0x05
#define INA237_OPER_MODE_TEMP_SHUNT_VOLTAGE_TRIG 0x06
#define INA237_OPER_MODE_BUS_SHUNT_VOLTAGE_TEMP_TRIG 0x07
#define INA237_OPER_MODE_BUS_VOLTAGE_CONT 0x09
#define INA237_OPER_MODE_SHUNT_VOLTAGE_CONT 0x0A
#define INA237_OPER_MODE_SHUNT_BUS_VOLTAGE_CONT 0x0B
#define INA237_OPER_MODE_TEMP_CONT 0x0C
#define INA237_OPER_MODE_BUS_VOLTAGE_TEMP_CONT 0x0D
#define INA237_OPER_MODE_TEMP_SHUNT_VOLTAGE_CONT 0x0E
#define INA237_OPER_MODE_BUS_SHUNT_VOLTAGE_TEMP_CONT 0x0F
/* Conversion time for bus, shunt and temp in micro-seconds */
#define INA237_CONV_TIME_50 0x00
#define INA237_CONV_TIME_84 0x01
#define INA237_CONV_TIME_150 0x02
#define INA237_CONV_TIME_280 0x03
#define INA237_CONV_TIME_540 0x04
#define INA237_CONV_TIME_1052 0x05
#define INA237_CONV_TIME_2074 0x06
#define INA237_CONV_TIME_4120 0x07
/* Averaging Mode */
#define INA237_AVG_MODE_1 0x00
#define INA237_AVG_MODE_4 0x01
#define INA237_AVG_MODE_16 0x02
#define INA237_AVG_MODE_64 0x03
#define INA237_AVG_MODE_128 0x04
#define INA237_AVG_MODE_256 0x05
#define INA237_AVG_MODE_512 0x06
#define INA237_AVG_MODE_1024 0x07
/* Reset Mode */
#define INA237_RST_NORMAL_OPERATION 0x00
#define INA237_RST_SYSTEM_RESET 0x01
/* Delay for initial ADC conversion in steps of 2 ms */
#define INA237_INIT_ADC_DELAY_0_S 0x00
#define INA237_INIT_ADC_DELAY_2_MS 0x01
#define INA237_INIT_ADC_DELAY_510_MS 0xFF
/* Shunt full scale range selection across IN+ and IN. */
#define INA237_ADC_RANGE_163_84 0x00
#define INA237_ADC_RANGE_40_96 0x01
/**
* @brief Macro for creating the INA237 configuration value
*
* @param rst_mode Reset mode.
* @param convdly Delay for initial ADC conversion in steps of 2 ms.
* @param adc_range Shunt full scale range selection across IN+ and IN.
*
*/
#define INA237_CONFIG(rst_mode, \
convdly, \
adc_range) \
(((rst_mode) << 15) | ((convdly) << 6) | ((adc_range) << 4))
/**
* @brief Macro for creating the INA237 ADC configuration value
*
* @param mode Operating mode.
* @param vshct Conversion time for shunt voltage.
* @param vbusct Conversion time for bus voltage.
* @param vtct Conversion time for temperature.
* @param avg Averaging mode.
*/
#define INA237_ADC_CONFIG(mode, \
vshct, \
vbusct, \
vtct, \
avg) \
(((mode) << 12) | ((vbusct) << 9) | ((vshct) << 6) | ((vtct) << 3) | (avg))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INA237_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/ina237.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 936 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LPS2xDF_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LPS2xDF_H_
/* Data rate */
#define LPS2xDF_DT_ODR_POWER_DOWN 0
#define LPS2xDF_DT_ODR_1HZ 1
#define LPS2xDF_DT_ODR_4HZ 2
#define LPS2xDF_DT_ODR_10HZ 3
#define LPS2xDF_DT_ODR_25HZ 4
#define LPS2xDF_DT_ODR_50HZ 5
#define LPS2xDF_DT_ODR_75HZ 6
#define LPS2xDF_DT_ODR_100HZ 7
#define LPS2xDF_DT_ODR_200HZ 8
/* Low Pass filter */
#define LPS2xDF_DT_LP_FILTER_OFF 0
#define LPS2xDF_DT_LP_FILTER_ODR_4 1
#define LPS2xDF_DT_LP_FILTER_ODR_9 3
/* Average (number of samples) filter */
#define LPS2xDF_DT_AVG_4_SAMPLES 0
#define LPS2xDF_DT_AVG_8_SAMPLES 1
#define LPS2xDF_DT_AVG_16_SAMPLES 2
#define LPS2xDF_DT_AVG_32_SAMPLES 3
#define LPS2xDF_DT_AVG_64_SAMPLES 4
#define LPS2xDF_DT_AVG_128_SAMPLES 5
#define LPS2xDF_DT_AVG_256_SAMPLES 6
#define LPS2xDF_DT_AVG_512_SAMPLES 7
/* Full Scale Pressure Mode */
#define LPS28DFW_DT_FS_MODE_1_1260 0
#define LPS28DFW_DT_FS_MODE_2_4060 1
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LPS22DF_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lps2xdf.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 413 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_ITE_TACH_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_ITE_TACH_H_
/**
* @name Tachometer channels
* @{
*/
/** Tachometer channel A */
#define IT8XXX2_TACH_CHANNEL_A 0
/** Tachometer channel B */
#define IT8XXX2_TACH_CHANNEL_B 1
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_ITE_TACH_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/it8xxx2_tach.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_IT8XXX2_VCMP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_IT8XXX2_VCMP_H_
/**
* @name it8xxx2 voltage comparator channel references
* @{
*/
#define VCMP_CHANNEL_0 0
#define VCMP_CHANNEL_1 1
#define VCMP_CHANNEL_2 2
#define VCMP_CHANNEL_3 3
#define VCMP_CHANNEL_4 4
#define VCMP_CHANNEL_5 5
#define VCMP_CHANNEL_CNT 6
/** @} */
/**
* @name it8xxx2 voltage comparator scan period for "all comparator channel"
* @{
*/
#define IT8XXX2_VCMP_SCAN_PERIOD_100US 0x10
#define IT8XXX2_VCMP_SCAN_PERIOD_200US 0x20
#define IT8XXX2_VCMP_SCAN_PERIOD_400US 0x30
#define IT8XXX2_VCMP_SCAN_PERIOD_600US 0x40
#define IT8XXX2_VCMP_SCAN_PERIOD_800US 0x50
#define IT8XXX2_VCMP_SCAN_PERIOD_1MS 0x60
#define IT8XXX2_VCMP_SCAN_PERIOD_1_5MS 0x70
#define IT8XXX2_VCMP_SCAN_PERIOD_2MS 0x80
#define IT8XXX2_VCMP_SCAN_PERIOD_2_5MS 0x90
#define IT8XXX2_VCMP_SCAN_PERIOD_3MS 0xa0
#define IT8XXX2_VCMP_SCAN_PERIOD_4MS 0xb0
#define IT8XXX2_VCMP_SCAN_PERIOD_5MS 0xc0
/** @} */
/**
* @name it8xxx2 voltage comparator interrupt trigger mode
* @{
*/
#define IT8XXX2_VCMP_LESS_OR_EQUAL 0
#define IT8XXX2_VCMP_GREATER 1
#define IT8XXX2_VCMP_UNDEFINED 0xffff
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_IT8XXX2_VCMP_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/it8xxx2_vcmp.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 452 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INA226_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INA226_H_
#include <zephyr/dt-bindings/dt-util.h>
/* Reset Mode. */
#define INA226_RST_NORMAL_OPERATION 0x00
#define INA226_RST_SYSTEM_RESET 0x01
/* Averaging Mode. */
#define INA226_AVG_MODE_1 0x00
#define INA226_AVG_MODE_4 0x01
#define INA226_AVG_MODE_16 0x02
#define INA226_AVG_MODE_64 0x03
#define INA226_AVG_MODE_128 0x04
#define INA226_AVG_MODE_256 0x05
#define INA226_AVG_MODE_512 0x06
#define INA226_AVG_MODE_1024 0x07
/* Conversion time for bus and shunt voltage in micro-seconds. */
#define INA226_CONV_TIME_140 0x00
#define INA226_CONV_TIME_204 0x01
#define INA226_CONV_TIME_332 0x02
#define INA226_CONV_TIME_588 0x03
#define INA226_CONV_TIME_1100 0x04
#define INA226_CONV_TIME_2116 0x05
#define INA226_CONV_TIME_4156 0x06
#define INA226_CONV_TIME_8244 0x07
/* Operating Mode. */
#define INA226_OPER_MODE_POWER_DOWN 0x00
#define INA226_OPER_MODE_SHUNT_VOLTAGE_TRIG 0x01
#define INA226_OPER_MODE_BUS_VOLTAGE_TRIG 0x02
#define INA226_OPER_MODE_SHUNT_BUS_VOLTAGE_TRIG 0x03
#define INA226_OPER_MODE_SHUNT_VOLTAGE_CONT 0x05
#define INA226_OPER_MODE_BUS_VOLTAGE_CONT 0x06
#define INA226_OPER_MODE_SHUNT_BUS_VOLTAGE_CONT 0x07
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INA226_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/ina226.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 450 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DS12_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DS12_H_
/* power-modes */
#define LIS2DS12_DT_POWER_DOWN 0
#define LIS2DS12_DT_LOW_POWER 1
#define LIS2DS12_DT_HIGH_RESOLUTION 2
#define LIS2DS12_DT_HIGH_FREQUENCY 3
/* Data rate */
#define LIS2DS12_DT_ODR_OFF 0
#define LIS2DS12_DT_ODR_1Hz_LP 1 /* available in LP mode only */
#define LIS2DS12_DT_ODR_12Hz5 2 /* available in LP and HR mode */
#define LIS2DS12_DT_ODR_25Hz 3 /* available in LP and HR mode */
#define LIS2DS12_DT_ODR_50Hz 4 /* available in LP and HR mode */
#define LIS2DS12_DT_ODR_100Hz 5 /* available in LP and HR mode */
#define LIS2DS12_DT_ODR_200Hz 6 /* available in LP and HR mode */
#define LIS2DS12_DT_ODR_400Hz 7 /* available in LP and HR mode */
#define LIS2DS12_DT_ODR_800Hz 8 /* available in LP and HR mode */
#define LIS2DS12_DT_ODR_1600Hz 9 /* available in HF mode only */
#define LIS2DS12_DT_ODR_3200Hz_HF 10 /* available in HF mode only */
#define LIS2DS12_DT_ODR_6400Hz_HF 11 /* available in HF mode only */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DS12_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lis2ds12.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 383 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DW12_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DW12_H_
/* power-modes */
#define LIS2DW12_DT_LP_M1 0
#define LIS2DW12_DT_LP_M2 1
#define LIS2DW12_DT_LP_M3 2
#define LIS2DW12_DT_LP_M4 3
#define LIS2DW12_DT_HP_MODE 4
/* Filter bandwidth */
#define LIS2DW12_DT_FILTER_BW_ODR_DIV_2 0
#define LIS2DW12_DT_FILTER_BW_ODR_DIV_4 1
#define LIS2DW12_DT_FILTER_BW_ODR_DIV_10 2
#define LIS2DW12_DT_FILTER_BW_ODR_DIV_20 3
/* Tap mode */
#define LIS2DW12_DT_SINGLE_TAP 0
#define LIS2DW12_DT_SINGLE_DOUBLE_TAP 1
/* Free-Fall threshold */
#define LIS2DW12_DT_FF_THRESHOLD_156_mg 0
#define LIS2DW12_DT_FF_THRESHOLD_219_mg 1
#define LIS2DW12_DT_FF_THRESHOLD_250_mg 2
#define LIS2DW12_DT_FF_THRESHOLD_312_mg 3
#define LIS2DW12_DT_FF_THRESHOLD_344_mg 4
#define LIS2DW12_DT_FF_THRESHOLD_406_mg 5
#define LIS2DW12_DT_FF_THRESHOLD_469_mg 6
#define LIS2DW12_DT_FF_THRESHOLD_500_mg 7
/* wakeup duration */
#define LIS2DW12_DT_WAKEUP_1_ODR 0
#define LIS2DW12_DT_WAKEUP_2_ODR 1
#define LIS2DW12_DT_WAKEUP_3_ODR 2
#define LIS2DW12_DT_WAKEUP_4_ODR 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DW12_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lis2dw12.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 433 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_STTS22H_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_STTS22H_H_
/* Output Data Rates */
#define STTS22H_POWER_DOWN 0x00
#define STTS22H_ONE_SHOT 0x01
#define STTS22H_1Hz 0x04
#define STTS22H_25Hz 0x02
#define STTS22H_50Hz 0x12
#define STTS22H_100Hz 0x22
#define STTS22H_200Hz 0x32
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_STTS22H_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/stts22h.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 154 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_ISM330DHCX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_ISM330DHCX_H_
/* Accel and Gyro Data rates */
#define ISM330DHCX_DT_ODR_OFF 0x0
#define ISM330DHCX_DT_ODR_12Hz5 0x1
#define ISM330DHCX_DT_ODR_26H 0x2
#define ISM330DHCX_DT_ODR_52Hz 0x3
#define ISM330DHCX_DT_ODR_104Hz 0x4
#define ISM330DHCX_DT_ODR_208Hz 0x5
#define ISM330DHCX_DT_ODR_416Hz 0x6
#define ISM330DHCX_DT_ODR_833Hz 0x7
#define ISM330DHCX_DT_ODR_1666Hz 0x8
#define ISM330DHCX_DT_ODR_3332Hz 0x9
#define ISM330DHCX_DT_ODR_6667Hz 0xa
#define ISM330DHCX_DT_ODR_1Hz6 0xb
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_ISM330DHCX_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/ism330dhcx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 298 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_NPCX_TACH_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_NPCX_TACH_H_
/* NPCX tachometer port type */
#define NPCX_TACH_PORT_A 0
#define NPCX_TACH_PORT_B 1
/* NPCX tachometer specific operate frequency */
#define NPCX_TACH_FREQ_LFCLK 32768
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_NPCX_TACH_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/npcx_tach.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 108 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LIS2DUX12_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_LIS2DUX12_H_
#include <zephyr/dt-bindings/dt-util.h>
/* Operating Mode */
#define LIS2DUX12_OPER_MODE_POWER_DOWN 0
#define LIS2DUX12_OPER_MODE_LOW_POWER 1
#define LIS2DUX12_OPER_MODE_HIGH_RESOLUTION 2
#define LIS2DUX12_OPER_MODE_HIGH_FREQUENCY 3
/* Data rate */
#define LIS2DUX12_DT_ODR_OFF 0
#define LIS2DUX12_DT_ODR_1Hz_ULP 1 /* available in ultra-low power mode */
#define LIS2DUX12_DT_ODR_3Hz_ULP 2 /* available in ultra-low power mode */
#define LIS2DUX12_DT_ODR_25Hz_ULP 3 /* available in ultra-low power mode */
#define LIS2DUX12_DT_ODR_6Hz 4 /* available in LP and HP mode */
#define LIS2DUX12_DT_ODR_12Hz5 5 /* available in LP and HP mode */
#define LIS2DUX12_DT_ODR_25Hz 6 /* available in LP and HP mode */
#define LIS2DUX12_DT_ODR_50Hz 7 /* available in LP and HP mode */
#define LIS2DUX12_DT_ODR_100Hz 8 /* available in LP and HP mode */
#define LIS2DUX12_DT_ODR_200Hz 9 /* available in LP and HP mode */
#define LIS2DUX12_DT_ODR_400Hz 10 /* available in LP and HP mode */
#define LIS2DUX12_DT_ODR_800Hz 11 /* available in LP and HP mode */
#define LIS2DUX12_DT_ODR_END 12
/* Accelerometer Full-scale */
#define LIS2DUX12_DT_FS_2G 0 /* 2g (0.061 mg/LSB) */
#define LIS2DUX12_DT_FS_4G 1 /* 4g (0.122 mg/LSB) */
#define LIS2DUX12_DT_FS_8G 2 /* 8g (0.244 mg/LSB) */
#define LIS2DUX12_DT_FS_16G 3 /* 16g (0.488 mg/LSB) */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LIS2DUX12_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lis2dux12.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 550 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSV16X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSV16X_H_
/* Accel range */
#define LSM6DSV16X_DT_FS_2G 0
#define LSM6DSV16X_DT_FS_4G 1
#define LSM6DSV16X_DT_FS_8G 2
#define LSM6DSV16X_DT_FS_16G 3
/* Gyro range */
#define LSM6DSV16X_DT_FS_125DPS 0x0
#define LSM6DSV16X_DT_FS_250DPS 0x1
#define LSM6DSV16X_DT_FS_500DPS 0x2
#define LSM6DSV16X_DT_FS_1000DPS 0x3
#define LSM6DSV16X_DT_FS_2000DPS 0x4
#define LSM6DSV16X_DT_FS_4000DPS 0xc
/* Accel and Gyro Data rates */
#define LSM6DSV16X_DT_ODR_OFF 0x0
#define LSM6DSV16X_DT_ODR_AT_1Hz875 0x1
#define LSM6DSV16X_DT_ODR_AT_7Hz5 0x2
#define LSM6DSV16X_DT_ODR_AT_15Hz 0x3
#define LSM6DSV16X_DT_ODR_AT_30Hz 0x4
#define LSM6DSV16X_DT_ODR_AT_60Hz 0x5
#define LSM6DSV16X_DT_ODR_AT_120Hz 0x6
#define LSM6DSV16X_DT_ODR_AT_240Hz 0x7
#define LSM6DSV16X_DT_ODR_AT_480Hz 0x8
#define LSM6DSV16X_DT_ODR_AT_960Hz 0x9
#define LSM6DSV16X_DT_ODR_AT_1920Hz 0xA
#define LSM6DSV16X_DT_ODR_AT_3840Hz 0xB
#define LSM6DSV16X_DT_ODR_AT_7680Hz 0xC
#define LSM6DSV16X_DT_ODR_HA01_AT_15Hz625 0x13
#define LSM6DSV16X_DT_ODR_HA01_AT_31Hz25 0x14
#define LSM6DSV16X_DT_ODR_HA01_AT_62Hz5 0x15
#define LSM6DSV16X_DT_ODR_HA01_AT_125Hz 0x16
#define LSM6DSV16X_DT_ODR_HA01_AT_250Hz 0x17
#define LSM6DSV16X_DT_ODR_HA01_AT_500Hz 0x18
#define LSM6DSV16X_DT_ODR_HA01_AT_1000Hz 0x19
#define LSM6DSV16X_DT_ODR_HA01_AT_2000Hz 0x1A
#define LSM6DSV16X_DT_ODR_HA01_AT_4000Hz 0x1B
#define LSM6DSV16X_DT_ODR_HA01_AT_8000Hz 0x1C
#define LSM6DSV16X_DT_ODR_HA02_AT_12Hz5 0x23
#define LSM6DSV16X_DT_ODR_HA02_AT_25Hz 0x24
#define LSM6DSV16X_DT_ODR_HA02_AT_50Hz 0x25
#define LSM6DSV16X_DT_ODR_HA02_AT_100Hz 0x26
#define LSM6DSV16X_DT_ODR_HA02_AT_200Hz 0x27
#define LSM6DSV16X_DT_ODR_HA02_AT_400Hz 0x28
#define LSM6DSV16X_DT_ODR_HA02_AT_800Hz 0x29
#define LSM6DSV16X_DT_ODR_HA02_AT_1600Hz 0x2A
#define LSM6DSV16X_DT_ODR_HA02_AT_3200Hz 0x2B
#define LSM6DSV16X_DT_ODR_HA02_AT_6400Hz 0x2C
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSV16X_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lsm6dsv16x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,009 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DH_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DH_H_
/* GPIO interrupt configuration */
#define LIS2DH_DT_GPIO_INT_EDGE_BOTH 0
#define LIS2DH_DT_GPIO_INT_EDGE_RISING 1
#define LIS2DH_DT_GPIO_INT_EDGE_FALLING 2
#define LIS2DH_DT_GPIO_INT_LEVEL_HIGH 3
#define LIS2DH_DT_GPIO_INT_LEVEL_LOW 4
/* Any Motion mode */
#define LIS2DH_DT_ANYM_OR_COMBINATION 0
#define LIS2DH_DT_ANYM_6D_MOVEMENT 1
#define LIS2DH_DT_ANYM_AND_COMBINATION 2
#define LIS2DH_DT_ANYM_6D_POSITION 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DH_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lis2dh.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 192 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INA230_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INA230_H_
#include <zephyr/dt-bindings/dt-util.h>
/* Mask/Enable bits that asserts the ALERT pin */
#define INA230_SHUNT_VOLTAGE_OVER BIT(15)
#define INA230_SHUNT_VOLTAGE_UNDER BIT(14)
#define INA230_BUS_VOLTAGE_OVER BIT(13)
#define INA230_BUS_VOLTAGE_UNDER BIT(12)
#define INA230_OVER_LIMIT_POWER BIT(11)
#define INA230_CONVERSION_READY BIT(10)
#define INA230_ALERT_FUNCTION_FLAG BIT(4)
#define INA230_CONVERSION_READY_FLAG BIT(3)
#define INA230_MATH_OVERFLOW_FLAG BIT(2)
#define INA230_ALERT_POLARITY BIT(1)
#define INA230_ALERT_LATCH_ENABLE BIT(0)
/* Operating Mode */
#define INA230_OPER_MODE_POWER_DOWN 0x00
#define INA230_OPER_MODE_SHUNT_VOLTAGE_TRIG 0x01
#define INA230_OPER_MODE_BUS_VOLTAGE_TRIG 0x02
#define INA230_OPER_MODE_SHUNT_BUS_VOLTAGE_TRIG 0x03
#define INA230_OPER_MODE_SHUNT_VOLTAGE_CONT 0x05
#define INA230_OPER_MODE_BUS_VOLTAGE_CONT 0x06
#define INA230_OPER_MODE_SHUNT_BUS_VOLTAGE_CONT 0x07
/* Conversion time for bus and shunt in micro-seconds */
#define INA230_CONV_TIME_140 0x00
#define INA230_CONV_TIME_204 0x01
#define INA230_CONV_TIME_332 0x02
#define INA230_CONV_TIME_588 0x03
#define INA230_CONV_TIME_1100 0x04
#define INA230_CONV_TIME_2116 0x05
#define INA230_CONV_TIME_4156 0x06
#define INA230_CONV_TIME_8244 0x07
/* Averaging Mode */
#define INA230_AVG_MODE_1 0x00
#define INA230_AVG_MODE_4 0x01
#define INA230_AVG_MODE_16 0x02
#define INA230_AVG_MODE_64 0x03
#define INA230_AVG_MODE_128 0x04
#define INA230_AVG_MODE_256 0x05
#define INA230_AVG_MODE_512 0x06
#define INA230_AVG_MODE_1024 0x07
/**
* @brief Macro for creating the INA230 configuration value
*
* @param mode Operating mode.
* @param svct Conversion time for shunt voltage.
* @param bvct Conversion time for bus voltage.
* @param avg Averaging mode.
*/
#define INA230_CONFIG(mode, \
svct, \
bvct, \
avg) \
(((avg) << 9) | ((bvct) << 6) | ((svct) << 3) | (mode))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INA230_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/ina230.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 661 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DE12_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DE12_H_
/* Accel range */
#define LIS2DE12_DT_FS_2G 0
#define LIS2DE12_DT_FS_4G 1
#define LIS2DE12_DT_FS_8G 2
#define LIS2DE12_DT_FS_16G 3
/* Accel rates */
#define LIS2DE12_DT_ODR_OFF 0x00 /* Power-Down */
#define LIS2DE12_DT_ODR_AT_1Hz 0x01 /* 1Hz (normal) */
#define LIS2DE12_DT_ODR_AT_10Hz 0x02 /* 10Hz (normal) */
#define LIS2DE12_DT_ODR_AT_25Hz 0x03 /* 25Hz (normal) */
#define LIS2DE12_DT_ODR_AT_50Hz 0x04 /* 50Hz (normal) */
#define LIS2DE12_DT_ODR_AT_100Hz 0x05 /* 100Hz (normal) */
#define LIS2DE12_DT_ODR_AT_200Hz 0x06 /* 200Hz (normal) */
#define LIS2DE12_DT_ODR_AT_400Hz 0x07 /* 400Hz (normal) */
#define LIS2DE12_DT_ODR_AT_1kHz620 0x08 /* 1KHz620 (normal) */
#define LIS2DE12_DT_ODR_AT_5kHz376 0x09 /* 5KHz376 (normal) */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DE12_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/lis2de12.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 377 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_QDEC_STM32_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_QDEC_STM32_H_
#define NO_FILTER 0
#define FDIV1_N2 1
#define FDIV1_N4 2
#define FDIV1_N8 3
#define FDIV2_N6 4
#define FDIV2_N8 5
#define FDIV4_N6 6
#define FDIV4_N8 7
#define FDIV8_N6 8
#define FDIV8_N8 9
#define FDIV16_N5 10
#define FDIV16_N6 11
#define FDIV16_N8 12
#define FDIV32_N5 13
#define FDIV32_N6 14
#define FDIV32_N8 15
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_QDEC_STM32_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/qdec_stm32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 195 |
```objective-c
/*
*
*
* Relevant documents:
* - BQ27421
* Datasheet: path_to_url
* Technical reference manual: path_to_url
* - BQ27427
* Datasheet: path_to_url
* Technical reference manual: path_to_url
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_BQ274XX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_BQ274XX_H_
/* Chemistry IDs for BQ27427 */
#define BQ27427_CHEM_ID_A 0x3230
#define BQ27427_CHEM_ID_B 0x1202
#define BQ27427_CHEM_ID_C 0x3142
/* Chemistry IDs for BQ27421 variants */
#define BQ27421_G1A_CHEM_ID 0x0128
#define BQ27421_G1B_CHEM_ID 0x0312
#define BQ27421_G1D_CHEM_ID 0x3142
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_BQ274XX_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/bq274xx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 234 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_IIS2DLPC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_IIS2DLPC_H_
/* power-modes */
#define IIS2DLPC_DT_LP_M1 0
#define IIS2DLPC_DT_LP_M2 1
#define IIS2DLPC_DT_LP_M3 2
#define IIS2DLPC_DT_LP_M4 3
#define IIS2DLPC_DT_HP_MODE 4
/* Filter bandwidth */
#define IIS2DLPC_DT_FILTER_BW_ODR_DIV_2 0
#define IIS2DLPC_DT_FILTER_BW_ODR_DIV_4 1
#define IIS2DLPC_DT_FILTER_BW_ODR_DIV_10 2
#define IIS2DLPC_DT_FILTER_BW_ODR_DIV_20 3
/* Tap mode */
#define IIS2DLPC_DT_SINGLE_TAP 0
#define IIS2DLPC_DT_SINGLE_DOUBLE_TAP 1
/* Free-Fall threshold */
#define IIS2DLPC_DT_FF_THRESHOLD_156_mg 0
#define IIS2DLPC_DT_FF_THRESHOLD_219_mg 1
#define IIS2DLPC_DT_FF_THRESHOLD_250_mg 2
#define IIS2DLPC_DT_FF_THRESHOLD_312_mg 3
#define IIS2DLPC_DT_FF_THRESHOLD_344_mg 4
#define IIS2DLPC_DT_FF_THRESHOLD_406_mg 5
#define IIS2DLPC_DT_FF_THRESHOLD_469_mg 6
#define IIS2DLPC_DT_FF_THRESHOLD_500_mg 7
/* wakeup duration */
#define IIS2DLPC_DT_WAKEUP_1_ODR 0
#define IIS2DLPC_DT_WAKEUP_2_ODR 1
#define IIS2DLPC_DT_WAKEUP_3_ODR 2
#define IIS2DLPC_DT_WAKEUP_4_ODR 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_IIS2DLPC_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/iis2dlpc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 456 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LVGL_LVGL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_LVGL_LVGL_H_
/* Predefined keys to control the focused object.
* Values taken from enum _lv_key_t in lv_group.h
*/
#define LV_KEY_UP 17
#define LV_KEY_DOWN 18
#define LV_KEY_RIGHT 19
#define LV_KEY_LEFT 20
#define LV_KEY_ESC 27
#define LV_KEY_DEL 127
#define LV_KEY_BACKSPACE 8
#define LV_KEY_ENTER 10
#define LV_KEY_NEXT 9
#define LV_KEY_PREV 11
#define LV_KEY_HOME 2
#define LV_KEY_END 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LVGL_LVGL_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/lvgl/lvgl.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 180 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DISPLAY_ILI9XXX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DISPLAY_ILI9XXX_H_
/* Pixel formats */
#define ILI9XXX_PIXEL_FORMAT_RGB565 0U
#define ILI9XXX_PIXEL_FORMAT_RGB888 1U
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DISPLAY_ILI9XXX_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/display/ili9xxx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```objective-c
/*
*
*/
/* Logic Trigger Numbers. See Trgmux_Ip_Init_PBcfg.h */
#define TRGMUX_LOGIC_GROUP_0_TRIGGER_0 (0) /* Logic Trigger 0 */
#define TRGMUX_LOGIC_GROUP_0_TRIGGER_1 (1) /* Logic Trigger 1 */
#define TRGMUX_LOGIC_GROUP_1_TRIGGER_0 (2) /* Logic Trigger 2 */
#define TRGMUX_LOGIC_GROUP_1_TRIGGER_1 (3) /* Logic Trigger 3 */
/*-----------------------------------------------
* TRGMUX HARDWARE TRIGGER INPUT
* See Trgmux_Ip_Cfg_Defines.h
*-----------------------------------------------
*/
#define TRGMUX_IP_INPUT_SIUL2_IN0 (60)
#define TRGMUX_IP_INPUT_SIUL2_IN1 (61)
#define TRGMUX_IP_INPUT_SIUL2_IN2 (62)
#define TRGMUX_IP_INPUT_SIUL2_IN3 (63)
#define TRGMUX_IP_INPUT_SIUL2_IN4 (64)
#define TRGMUX_IP_INPUT_SIUL2_IN5 (65)
#define TRGMUX_IP_INPUT_SIUL2_IN6 (66)
#define TRGMUX_IP_INPUT_SIUL2_IN7 (67)
#define TRGMUX_IP_INPUT_SIUL2_IN8 (68)
#define TRGMUX_IP_INPUT_SIUL2_IN9 (69)
#define TRGMUX_IP_INPUT_SIUL2_IN10 (70)
#define TRGMUX_IP_INPUT_SIUL2_IN11 (71)
#define TRGMUX_IP_INPUT_SIUL2_IN12 (72)
#define TRGMUX_IP_INPUT_SIUL2_IN13 (73)
#define TRGMUX_IP_INPUT_SIUL2_IN14 (74)
#define TRGMUX_IP_INPUT_SIUL2_IN15 (75)
#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I0 (105)
#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I1 (106)
#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I2 (107)
#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I3 (108)
/*-----------------------------------------------
* TRGMUX HARDWARE TRIGGER OUTPUT
* See Trgmux_Ip_Cfg_Defines.h
*-----------------------------------------------
*/
#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I0 (144)
#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I1 (145)
#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I2 (146)
#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I3 (147)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH1 (32)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH2 (33)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH3 (34)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH4 (35)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH5 (36)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH6 (37)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH7 (38)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH9 (39)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH10 (40)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH11 (41)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH12 (42)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH13 (43)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH14_15_IPP_IND_CH14 (44)
#define TRGMUX_IP_OUTPUT_EMIOS0_CH14_15_IPP_IND_CH15 (45)
/*-----------------------------------------------
* LCU SOURCE MUX SELECT
* See Lcu_Ip_Cfg_Defines.h
*-----------------------------------------------
*/
#define LCU_IP_MUX_SEL_LOGIC_0 (0)
#define LCU_IP_MUX_SEL_LU_IN_0 (1)
#define LCU_IP_MUX_SEL_LU_IN_1 (2)
#define LCU_IP_MUX_SEL_LU_IN_2 (3)
#define LCU_IP_MUX_SEL_LU_IN_3 (4)
#define LCU_IP_MUX_SEL_LU_IN_4 (5)
#define LCU_IP_MUX_SEL_LU_IN_5 (6)
#define LCU_IP_MUX_SEL_LU_IN_6 (7)
#define LCU_IP_MUX_SEL_LU_IN_7 (8)
#define LCU_IP_MUX_SEL_LU_IN_8 (9)
#define LCU_IP_MUX_SEL_LU_IN_9 (10)
#define LCU_IP_MUX_SEL_LU_IN_10 (11)
#define LCU_IP_MUX_SEL_LU_IN_11 (12)
#define LCU_IP_MUX_SEL_LU_OUT_0 (13)
#define LCU_IP_MUX_SEL_LU_OUT_1 (14)
#define LCU_IP_MUX_SEL_LU_OUT_2 (15)
#define LCU_IP_MUX_SEL_LU_OUT_3 (16)
#define LCU_IP_MUX_SEL_LU_OUT_4 (17)
#define LCU_IP_MUX_SEL_LU_OUT_5 (18)
#define LCU_IP_MUX_SEL_LU_OUT_6 (19)
#define LCU_IP_MUX_SEL_LU_OUT_7 (20)
#define LCU_IP_MUX_SEL_LU_OUT_8 (21)
#define LCU_IP_MUX_SEL_LU_OUT_9 (22)
#define LCU_IP_MUX_SEL_LU_OUT_10 (23)
#define LCU_IP_MUX_SEL_LU_OUT_11 (24)
#define LCU_IP_IN_0 (0)
#define LCU_IP_IN_1 (1)
#define LCU_IP_IN_2 (2)
#define LCU_IP_IN_3 (3)
#define LCU_IP_IN_4 (4)
#define LCU_IP_IN_5 (5)
#define LCU_IP_IN_6 (6)
#define LCU_IP_IN_7 (7)
#define LCU_IP_IN_8 (8)
#define LCU_IP_IN_9 (9)
#define LCU_IP_IN_10 (10)
#define LCU_IP_IN_11 (11)
``` | /content/code_sandbox/include/zephyr/dt-bindings/sensor/qdec_nxp_s32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,395 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DISPLAY_PANEL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DISPLAY_PANEL_H_
/**
* @brief LCD Interface
* @defgroup lcd_interface LCD Interface
* @ingroup display_interface
* @{
*/
/**
* @brief Display pixel formats
*
* Display pixel format enumeration.
*
* These defines must match those present in the display_pixel_format enum.
* They are required because the enum cannot be reused within devicetree,
* since enum definitions are not supported by devicetree tooling.
*/
#define PANEL_PIXEL_FORMAT_RGB_888 (0x1 << 0)
#define PANEL_PIXEL_FORMAT_MONO01 (0x1 << 1) /* 0=Black 1=White */
#define PANEL_PIXEL_FORMAT_MONO10 (0x1 << 2) /* 1=Black 0=White */
#define PANEL_PIXEL_FORMAT_ARGB_8888 (0x1 << 3)
#define PANEL_PIXEL_FORMAT_RGB_565 (0x1 << 4)
#define PANEL_PIXEL_FORMAT_BGR_565 (0x1 << 5)
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DISPLAY_PANEL_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/display/panel.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 260 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_STM32_PWR_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_STM32_PWR_H_
/**
* @brief STM32 power controller
* @{
*/
/**
* @name flags for wake-up pins sources
* @{
*/
#define STM32_PWR_WKUP_PIN_SRC_0 0
#define STM32_PWR_WKUP_PIN_SRC_1 1
#define STM32_PWR_WKUP_PIN_SRC_2 (1 << 2)
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_STM32_PWR_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/power/stm32_pwr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 132 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_ATMEL_SAM_SUPC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_ATMEL_SAM_SUPC_H_
#define SUPC_WAKEUP_SOURCE_FWUP 0
#define SUPC_WAKEUP_SOURCE_SM 1
#define SUPC_WAKEUP_SOURCE_RTT 2
#define SUPC_WAKEUP_SOURCE_RTC 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_ATMEL_SAM_SUPC_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/power/atmel_sam_supc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 108 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_
#define PMU_RESET_CM33_SOFT_RESET 0x1
#define PMU_RESET_CM33_LOCKUP 0x2
#define PMU_RESET_WATCHDOG 0x4
#define PMU_RESET_AP_RESET 0x8
#define PMU_RESET_CODE_WATCHDOG 0x10
#define PMU_RESET_ITRC 0x20
#define PMU_RESET_RESETB 0x40
#define PMU_RESET_ALL 0x7F
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/power/nxp_rw_pmu.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```objective-c
/*
*
*/
/*
* Setpoint definitions for IMX Set point controller. The SPC uses a series
* of set points to determine the clock speeds and states of cores, as well
* as which peripherals to gate clocks to. Higher values correspond to more
* power saving. See your SOC's datasheet for specifics of what peripherals
* have their clocks gated at each set point.
*
* Set point control is implemented at the soc level (see pm_state_set())
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_
#define IMX_GPC_RUN 0x0
#define IMX_GPC_WAIT 0x1
#define IMX_GPC_STOP 0x2
#define IMX_GPC_SUSPEND 0x3
#define IMX_SPC_MASK 0xF0
#define IMX_SPC_SHIFT 4
#define IMX_GPC_MODE_MASK 0xF
#define IMX_SPC(x) ((x & IMX_SPC_MASK) >> IMX_SPC_SHIFT)
#define IMX_GPC_MODE(x) (x & IMX_GPC_MODE_MASK)
#define IMX_SPC_0 0x00
#define IMX_SPC_1 0x10
#define IMX_SPC_2 0x20
#define IMX_SPC_3 0x30
#define IMX_SPC_4 0x40
#define IMX_SPC_5 0x50
#define IMX_SPC_6 0x60
#define IMX_SPC_7 0x70
#define IMX_SPC_8 0x80
#define IMX_SPC_9 0x90
#define IMX_SPC_10 0xA0
#define IMX_SPC_11 0xB0
#define IMX_SPC_12 0xC0
#define IMX_SPC_13 0xD0
#define IMX_SPC_14 0xE0
#define IMX_SPC_15 0xF0
#define IMX_SPC_SET_POINT_0_RUN (IMX_SPC_0 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_0_WAIT (IMX_SPC_0 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_0_STOP (IMX_SPC_0 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_0_SUSPEND (IMX_SPC_0 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_1_RUN (IMX_SPC_1 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_1_WAIT (IMX_SPC_1 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_1_STOP (IMX_SPC_1 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_1_SUSPEND (IMX_SPC_1 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_2_RUN (IMX_SPC_2 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_2_WAIT (IMX_SPC_2 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_2_STOP (IMX_SPC_2 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_2_SUSPEND (IMX_SPC_2 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_3_RUN (IMX_SPC_3 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_3_WAIT (IMX_SPC_3 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_3_STOP (IMX_SPC_3 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_3_SUSPEND (IMX_SPC_3 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_4_RUN (IMX_SPC_4 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_4_WAIT (IMX_SPC_4 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_4_STOP (IMX_SPC_4 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_4_SUSPEND (IMX_SPC_4 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_5_RUN (IMX_SPC_5 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_5_WAIT (IMX_SPC_5 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_5_STOP (IMX_SPC_5 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_5_SUSPEND (IMX_SPC_5 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_6_RUN (IMX_SPC_6 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_6_WAIT (IMX_SPC_6 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_6_STOP (IMX_SPC_6 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_6_SUSPEND (IMX_SPC_6 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_7_RUN (IMX_SPC_7 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_7_WAIT (IMX_SPC_7 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_7_STOP (IMX_SPC_7 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_7_SUSPEND (IMX_SPC_7 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_8_RUN (IMX_SPC_8 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_8_WAIT (IMX_SPC_8 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_8_STOP (IMX_SPC_8 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_8_SUSPEND (IMX_SPC_8 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_9_RUN (IMX_SPC_9 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_9_WAIT (IMX_SPC_9 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_9_STOP (IMX_SPC_9 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_9_SUSPEND (IMX_SPC_9 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_10_RUN (IMX_SPC_10 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_10_WAIT (IMX_SPC_10 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_10_STOP (IMX_SPC_10 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_10_SUSPEND (IMX_SPC_10 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_11_RUN (IMX_SPC_11 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_11_WAIT (IMX_SPC_11 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_11_STOP (IMX_SPC_11 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_11_SUSPEND (IMX_SPC_11 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_12_RUN (IMX_SPC_12 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_12_WAIT (IMX_SPC_12 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_12_STOP (IMX_SPC_12 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_12_SUSPEND (IMX_SPC_12 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_13_RUN (IMX_SPC_13 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_13_WAIT (IMX_SPC_13 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_13_STOP (IMX_SPC_13 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_13_SUSPEND (IMX_SPC_13 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_14_RUN (IMX_SPC_14 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_14_WAIT (IMX_SPC_14 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_14_STOP (IMX_SPC_14 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_14_SUSPEND (IMX_SPC_14 | IMX_GPC_SUSPEND)
#define IMX_SPC_SET_POINT_15_RUN (IMX_SPC_15 | IMX_GPC_RUN)
#define IMX_SPC_SET_POINT_15_WAIT (IMX_SPC_15 | IMX_GPC_WAIT)
#define IMX_SPC_SET_POINT_15_STOP (IMX_SPC_15 | IMX_GPC_STOP)
#define IMX_SPC_SET_POINT_15_SUSPEND (IMX_SPC_15 | IMX_GPC_SUSPEND)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/power/imx_spc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,085 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_USB_AUDIO_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_USB_AUDIO_H
/* USB Device Class Definition for Audio Devices Release 2.0 May 31, 2006
* A.7 Audio Function Category Codes
*/
#define AUDIO_FUNCTION_SUBCLASS_UNDEFINED 0x00
#define AUDIO_FUNCTION_DESKTOP_SPEAKER 0x01
#define AUDIO_FUNCTION_HOME_THEATER 0x02
#define AUDIO_FUNCTION_MICROPHONE 0x03
#define AUDIO_FUNCTION_HEADSET 0x04
#define AUDIO_FUNCTION_TELEPHONE 0x05
#define AUDIO_FUNCTION_CONVERTER 0x06
#define AUDIO_FUNCTION_VOICE_SOUND_RECORDER 0x07
#define AUDIO_FUNCTION_IO_BOX 0x08
#define AUDIO_FUNCTION_MUSICAL_INSTRUMENT 0x09
#define AUDIO_FUNCTION_PRO_AUDIO 0x0A
#define AUDIO_FUNCTION_AUDIO_VIDEO 0x0B
#define AUDIO_FUNCTION_CONTROL_PANEL 0x0C
#define AUDIO_FUNCTION_OTHER 0xFF
/* USB Device Class Definition for Terminal Types
* Both "Universal Serial Bus Device Class Definition for Terminal Types"
* Release 2.0 May 31, 2006 and Release 3.0 September 22, 2016 contain exactly
* the same terminal types and values.
*/
/* 2.1 USB Terminal Types */
#define USB_TERMINAL_UNDEFINED 0x0100
#define USB_TERMINAL_STREAMING 0x0101
#define USB_TERMINAL_VENDOR_SPECIFIC 0x01FF
/* 2.2 Input Terminal Types */
#define INPUT_TERMINAL_UNDEFINED 0x0200
#define INPUT_TERMINAL_MICROPHONE 0x0201
#define INPUT_TERMINAL_DESKTOP_MICROPHONE 0x0202
#define INPUT_TERMINAL_PERSONAL_MICROPHONE 0x0203
#define INPUT_TERMINAL_OMNI_DIRECTIONAL_MICROPHONE 0x0204
#define INPUT_TERMINAL_MICROPHONE_ARRAY 0x0205
#define INPUT_TERMINAL_PROCESSING_MICROPHONE_ARRAY 0x0206
/* 2.3 Output Terminal Types */
#define OUTPUT_TERMINAL_UNDEFINED 0x0300
#define OUTPUT_TERMINAL_SPEAKER 0x0301
#define OUTPUT_TERMINAL_HEADPHONES 0x0302
#define OUTPUT_TERMINAL_HEAD_MOUNTED_DISPLAY_AUDIO 0x0303
#define OUTPUT_TERMINAL_DESKTOP_SPEAKER 0x0304
#define OUTPUT_TERMINAL_ROOM_SPEAKER 0x0305
#define OUTPUT_TERMINAL_COMMUNICATION_SPEAKER 0x0306
#define OUTPUT_TERMINAL_LOW_FREQUENCY_EFFECTS_SPEAKER 0x0307
/* 2.4 Bi-directional Terminal Types */
#define BIDIRECTIONAL_TERMINAL_UNDEFINED 0x0400
#define BIDIRECTIONAL_TERMINAL_HANDSET 0x0401
#define BIDIRECTIONAL_TERMINAL_HEADSET 0x0402
#define BIDIRECTIONAL_TERMINAL_SPEAKERPHONE_NO_ECHO_REDUCTION 0x0403
#define BIDIRECTIONAL_TERMINAL_ECHO_SUPPRESSING_SPEAKERPHONE 0x0404
#define BIDIRECTIONAL_TERMINAL_ECHO_CANCELLING_SPEAKERPHONE 0x0405
/* 2.5 Telephony Terminal Types */
#define TELEPHONY_TERMINAL_UNDEFINED 0x0500
#define TELEPHONY_TERMINAL_PHONE_LINE 0x0501
#define TELEPHONY_TERMINAL_TELEPHONE 0x0502
#define TELEPHONY_TERMINAL_DOWN_LINE_PHONE 0x0503
/* 2.6 External Terminal Types */
#define EXTERNAL_TERMINAL_UNDEFINED 0x0600
#define EXTERNAL_TERMINAL_ANALOG_CONNECTOR 0x0601
#define EXTERNAL_TERMINAL_DIGITAL_AUDIO_INTERFACE 0x0602
#define EXTERNAL_TERMINAL_LINE_CONNECTOR 0x0603
#define EXTERNAL_TERMINAL_LEGACY_AUDIO_CONNECTOR 0x0604
#define EXTERNAL_TERMINAL_SPDIF_INTERFACE 0x0605
#define EXTERNAL_TERMINAL_1394_DA_STREAM 0x0606
#define EXTERNAL_TERMINAL_1394_DV_STREAM_SOUNDTRACK 0x0607
#define EXTERNAL_TERMINAL_ADAT_LIGHTPIPE 0x0608
#define EXTERNAL_TERMINAL_TDIF 0x0609
#define EXTERNAL_TERMINAL_MADI 0x060A
/* 2.7 Embedded Function Terminal Types */
#define EMBEDDED_TERMINAL_UNDEFINED 0x0700
#define EMBEDDED_TERMINAL_LEVEL_CALIBRATION_NOISE_SOURCE 0x0701
#define EMBEDDED_TERMINAL_EQUALIZATION_NOISE 0x0702
#define EMBEDDED_TERMINAL_CD_PLAYER 0x0703
#define EMBEDDED_TERMINAL_DAT 0x0704
#define EMBEDDED_TERMINAL_DCC 0x0705
#define EMBEDDED_TERMINAL_COMPRESSED_AUDIO_PLAYER 0x0706
#define EMBEDDED_TERMINAL_ANALOG_TAPE 0x0707
#define EMBEDDED_TERMINAL_PHONOGRAPH 0x0708
#define EMBEDDED_TERMINAL_VCR_AUDIO 0x0709
#define EMBEDDED_TERMINAL_VIDEO_DISC_AUDIO 0x070A
#define EMBEDDED_TERMINAL_DVD_AUDIO 0x070B
#define EMBEDDED_TERMINAL_TV_TUNER_AUDIO 0x070C
#define EMBEDDED_TERMINAL_SATELLITE_RECEIVER_AUDIO 0x070D
#define EMBEDDED_TERMINAL_CABLE_TUNER_AUDIO 0x070E
#define EMBEDDED_TERMINAL_DSS_AUDIO 0x070F
#define EMBEDDED_TERMINAL_RADIO_RECEIVER 0x0710
#define EMBEDDED_TERMINAL_RADIO_TRANSMITTER 0x0711
#define EMBEDDED_TERMINAL_MULTI_TRACK_RECORDER 0x0712
#define EMBEDDED_TERMINAL_SYNTHESIZER 0x0713
#define EMBEDDED_TERMINAL_PIANO 0x0714
#define EMBEDDED_TERMINAL_GUITAR 0x0715
#define EMBEDDED_TERMINAL_DRUMS_RHYTHM 0x0716
#define EMBEDDED_TERMINAL_OTHER_MUSICAL_INSTRUMENT 0x0717
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_USB_AUDIO_H */
``` | /content/code_sandbox/include/zephyr/dt-bindings/usb/audio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,377 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DAC_DACX0508_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DAC_DACX0508_H_
#define DACX0508_REF_INTERNAL_1 0x00
#define DACX0508_REF_INTERNAL_1_2 0x01
#define DACX0508_REF_EXTERNAL_1 0x02
#define DACX0508_REF_EXTERNAL_1_2 0x03
#define DACX0508_CHANNEL_GAIN_1 0x00
#define DACX0508_CHANNEL_GAIN_2 0x01
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DAC_DACX0508_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/dac/dacx0508.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 146 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_USB_USB_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_USB_USB_H_
/* Ideally we'd generate this enum to match what's coming out of the YAML,
* however, we dont have a good way to know how to name such an enum from
* the generation point of view, so for now we just hand code the enum. This
* enum is expected to match the order in the yaml (dts/bindings/usb/usb.yaml)
*/
enum dt_usb_maximum_speed {
DT_USB_MAXIMUM_SPEED_LOW_SPEED,
DT_USB_MAXIMUM_SPEED_FULL_SPEED,
DT_USB_MAXIMUM_SPEED_HIGH_SPEED,
DT_USB_MAXIMUM_SPEED_SUPER_SPEED,
};
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_USB_USB_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/usb/usb.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 163 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_
#include <zephyr/dt-bindings/dt-util.h>
/* PWM prescaler references */
#define PWM_PRESCALER_C4 1
#define PWM_PRESCALER_C6 2
#define PWM_PRESCALER_C7 3
/* PWM channel references */
#define PWM_CHANNEL_0 0
#define PWM_CHANNEL_1 1
#define PWM_CHANNEL_2 2
#define PWM_CHANNEL_3 3
#define PWM_CHANNEL_4 4
#define PWM_CHANNEL_5 5
#define PWM_CHANNEL_6 6
#define PWM_CHANNEL_7 7
/*
* Provides a type to hold PWM configuration flags.
*
* The upper 8 bits are reserved for SoC specific flags.
* Output onpe-drain flag [ 8 ]
*/
#define PWM_IT8XXX2_OPEN_DRAIN BIT(8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 234 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_H_
/**
* @brief PWM Interface
* @defgroup pwm_interface PWM Interface
* @ingroup io_interfaces
* @{
*/
/**
* @name PWM period set helpers
* The period cell in the PWM specifier needs to be provided in nanoseconds.
* However, in some applications it is more convenient to use another scale.
* @{
*/
/** Specify PWM period in nanoseconds */
#define PWM_NSEC(x) (x)
/** Specify PWM period in microseconds */
#define PWM_USEC(x) (PWM_NSEC(x) * 1000UL)
/** Specify PWM period in milliseconds */
#define PWM_MSEC(x) (PWM_USEC(x) * 1000UL)
/** Specify PWM period in seconds */
#define PWM_SEC(x) (PWM_MSEC(x) * 1000UL)
/** Specify PWM frequency in hertz */
#define PWM_HZ(x) (PWM_SEC(1UL) / (x))
/** Specify PWM frequency in kilohertz */
#define PWM_KHZ(x) (PWM_HZ((x) * 1000UL))
/** @} */
/**
* @name PWM polarity flags
* The `PWM_POLARITY_*` flags are used with pwm_set_cycles(), pwm_set()
* or pwm_configure_capture() to specify the polarity of a PWM channel.
*
* The flags are on the lower 8bits of the pwm_flags_t
* @{
*/
/** PWM pin normal polarity (active-high pulse). */
#define PWM_POLARITY_NORMAL (0 << 0)
/** PWM pin inverted polarity (active-low pulse). */
#define PWM_POLARITY_INVERTED (1 << 0)
/** @cond INTERNAL_HIDDEN */
#define PWM_POLARITY_MASK 0x1
/** @endcond */
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/pwm/pwm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 405 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32_PWM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32_PWM_H_
/**
* @name custom PWM complementary flags for output pins
* This flag can be used with any of the `pwm_pin_set_*` API calls to indicate
* that the PWM signal has to be routed to the complementary output channel.
* This feature is only available on certain SoC families, refer to the
* binding's documentation for more details.
* The custom flags are on the upper 8bits of the pwm_flags_t
* @{
*/
/** PWM complementary output pin is enabled */
#define STM32_PWM_COMPLEMENTARY (1U << 8)
/**
* @deprecated Use the PWM complementary `STM32_PWM_COMPLEMENTARY` flag instead.
*/
#define PWM_STM32_COMPLEMENTARY (1U << 8)
/** @cond INTERNAL_HIDDEN */
#define STM32_PWM_COMPLEMENTARY_MASK 0x100
/** @endcond */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_STM32_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/pwm/stm32_pwm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 230 |
```objective-c
/*
*
*/
#ifndef DMA_SMARTBOND_H_
#define DMA_SMARTBOND_H_
/**
* @brief Vendror-specific DMA peripheral triggering sources.
*
* A valid triggering source should be provided when DMA
* is configured for peripheral to peripheral or memory to peripheral
* transactions.
*/
#define DMA_SMARTBOND_TRIG_MUX_SPI 0x0
#define DMA_SMARTBOND_TRIG_MUX_SPI2 0x1
#define DMA_SMARTBOND_TRIG_MUX_UART 0x2
#define DMA_SMARTBOND_TRIG_MUX_UART2 0x3
#define DMA_SMARTBOND_TRIG_MUX_I2C 0x4
#define DMA_SMARTBOND_TRIG_MUX_I2C2 0x5
#define DMA_SMARTBOND_TRIG_MUX_USB 0x6
#define DMA_SMARTBOND_TRIG_MUX_UART3 0x7
#define DMA_SMARTBOND_TRIG_MUX_PCM 0x8
#define DMA_SMARTBOND_TRIG_MUX_SRC 0x9
#define DMA_SMARTBOND_TRIG_MUX_GPADC 0xC
#define DMA_SMARTBOND_TRIG_MUX_SDADC 0xD
#define DMA_SMARTBOND_TRIG_MUX_NONE 0xF
#endif /* DMA_SMARTBOND_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/dma/dma_smartbond.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 285 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.