text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_RISCV_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_RISCV_H_
#include <zephyr/sys/util_macro.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
/*
* Architecture specific RISCV related attributes.
*/
#define DT_MEM_RISCV_MASK DT_MEM_ARC... | /content/code_sandbox/include/zephyr/dt-bindings/memory-attr/memory-attr-riscv.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 496 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_XTENSA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_XTENSA_H_
#include <zephyr/sys/util_macro.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
/*
* Architecture specific Xtensa related attributes.
*/
#define DT_MEM_XTENSA_MASK DT_MEM_... | /content/code_sandbox/include/zephyr/dt-bindings/memory-attr/memory-attr-xtensa.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 380 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_SW_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_SW_H_
#include <zephyr/sys/util_macro.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
/*
* Software specific memory attributes.
*/
#define DT_MEM_SW_MASK DT_MEM_SW_ATTR_MASK
#define DT... | /content/code_sandbox/include/zephyr/dt-bindings/memory-attr/memory-attr-sw.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 218 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_H_
#include <zephyr/sys/util_macro.h>
/*
* Generic memory attributes.
*
* Generic memory attributes that should be common to all architectures.
*/
#define DT_MEM_ATTR_MASK GENMASK(15, 0)
#define DT... | /content/code_sandbox/include/zephyr/dt-bindings/memory-attr/memory-attr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 397 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RDC_IMX_RDC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RDC_IMX_RDC_H_
#define A7_DOMAIN_ID 0
#define A9_DOMAIN_ID 0
#define A53_DOMAIN_ID 0
#define M4_DOMAIN_ID 1
#define M7_DOMAIN_ID 1
#define RDC_DOMAIN_PERM_NONE (0x0)
#define RDC_DOMAIN_PERM_W (0x1)
#def... | /content/code_sandbox/include/zephyr/dt-bindings/rdc/imx_rdc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```objective-c
/*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_
/* PHY auto-detection alias */
#define XLNX_GEM_PHY_AUTO_DETECT 0
/*
* MDC divider values
*
* According to the ZynqMP's gem.network_config register documentation (UG1087),
* divid... | /content/code_sandbox/include/zephyr/dt-bindings/ethernet/xlnx_gem.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 810 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_NXP_ENET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_NXP_ENET_H_
#define NXP_ENET_MII_MODE 0
#define NXP_ENET_RMII_MODE 1
#define NXP_ENET_RGMII_MODE 2
#define NXP_ENET_INVALID_MII_MODE 100
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_NXP_ENET_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/ethernet/nxp_enet.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DSI_MIPI_DSI_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DSI_MIPI_DSI_H_
/**
* @brief MIPI-DSI driver APIs
* @defgroup mipi_dsi_interface MIPI-DSI driver APIs
* @ingroup io_interfaces
* @{
*/
/**
* @name MIPI-DSI Pixel formats.
* @{
*/
/** RGB8... | /content/code_sandbox/include/zephyr/dt-bindings/mipi_dsi/mipi_dsi.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 218 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32L23X_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32L23X_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHB1EN_OFFSET 0x14U
#define GD32_APB1EN_OFFSET 0x1CU
#define GD32_APB2EN_O... | /content/code_sandbox/include/zephyr/dt-bindings/clock/gd32l23x-clocks.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 980 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_
#include "pinctrl-rcar-common.h"
/* Pins declaration */
#define PIN_NONE -1
#define PIN_D0 RCAR_GP_PIN(0, 0)
#def... | /content/code_sandbox/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16,872 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU_CLK_SRC_PLL 1U
#define ESP32_CLK_SRC_RC_FAST 2U
/* Supported CPU frequencies */
#define ESP32_CLK_CP... | /content/code_sandbox/include/zephyr/dt-bindings/clock/esp32c2_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 712 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_
/* NXP Kinetis Peripheral Clock Controller IP sources */
#define KINETIS_PCC_SRC_NONE_OR_EXT 0 /* Clock off or external clock is used */
#define KINETIS_PCC_SRC_SOSC_ASYNC 1 /* Sys... | /content/code_sandbox/include/zephyr/dt-bindings/clock/kinetis_pcc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 167 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H_
#define CPG_CORE 0 /* Core Clock */
#define CPG_MOD 1 /* Module Clock */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_C... | /content/code_sandbox/include/zephyr/dt-bindings/clock/renesas_cpg_mssr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
#define RA_PLL_SOURCE_HOCO 0
#define RA_PLL_SOURCE_MOCO 1
#define RA_PLL_SOURCE_LOCO 2
#define RA_PLL_SOURCE_MAIN_OSC 3
#define RA_PLL_SOURCE_SUBCLOCK 4
#define RA_PLL_SOURCE_DISABLE 0xf... | /content/code_sandbox/include/zephyr/dt-bindings/clock/ra_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,314 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_
/* Peripheral:
* range: 0 - 0xFF, starting from 0
*
* Instance:
* range: 0 - 0xFF, starting from 0
*/
#define IMX_CCM_PERIPHERAL_MASK 0xFF00UL
#define IMX_CCM_INST... | /content/code_sandbox/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,575 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU_CLK_SRC_PLL 1U
#define ESP32_CLK_SRC_RC_FAST 2U
/* Supported PLL CPU frequencies */
#define ESP32_CL... | /content/code_sandbox/include/zephyr/dt-bindings/clock/esp32s3_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 847 |
```objective-c
/*
*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_INTEL_SOCFPGA_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_INTEL_SOCFPGA_CLOCK_H_
#define INTEL_SOCFPGA_CLOCK_MPU 0
#define INTEL_SOCFPGA_CLOCK_WDT 1
#define INTEL_SOCFPGA_CLOCK_UART 2
#define INTEL_SOCFPGA_CLOCK_MMC ... | /content/code_sandbox/include/zephyr/dt-bindings/clock/intel_socfpga_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_
/* SCG system oscillator mode */
#define KINETIS_SCG_SOSC_MODE_EXT 0U
#define KINETIS_SCG_SOSC_MODE_LOW_POWER 4U
#define KINETIS_SCG_SOSC_MODE_HIGH_GAIN 12U
/* SCG clock co... | /content/code_sandbox/include/zephyr/dt-bindings/clock/kinetis_scg.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 359 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x030
#define STM32_CLOCK_BUS_AHB2 0x034
#define STM32_CLOCK_BUS_AHB3... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f7_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,333 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x048
#define STM32_CLOCK_BUS_AHB2 0x04c
#define STM32_CLOCK_BUS_AHB3 0x050
#define STM3... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32wl_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,102 |
```objective-c
/*
*
*/
#ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_
#define _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_
/* IMPORTANT: the indexes used by these macros need to
* match the indexes in the PCC driver LUT at which the
* corresponding clock ID encoding can be found.
*/
/* clocks ... | /content/code_sandbox/include/zephyr/dt-bindings/clock/imx8ulp_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ATMEL_SAM_PMC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ATMEL_SAM_PMC_H_
#define PMC_TYPE_CORE 0
#define PMC_TYPE_SYSTEM 1
#define PMC_TYPE_PERIPHERAL 2
#define PMC_TYPE_GCK 3
#define PMC_TYPE_PROGRAMMABLE 4
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_C... | /content/code_sandbox/include/zephyr/dt-bindings/clock/atmel_sam_pmc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_
#define KINETIS_MCG_FIXED_FREQ_CLK 0
#define KINETIS_MCG_OUT_CLK 1
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/clock/kinetis_mcg.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_LPC11U6X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_LPC11U6X_CLOCK_H_
#define LPC11U6X_CLOCK_I2C0 0
#define LPC11U6X_CLOCK_I2C1 1
#define LPC11U6X_CLOCK_GPIO 2
#define LPC11U6X_CLOCK_USART0 3
#define LPC11U6X_CLOCK_USART1 4
#defin... | /content/code_sandbox/include/zephyr/dt-bindings/clock/lpc11u6x_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 170 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AST10X0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AST10X0_H_
#define ASPEED_CLK_GRP_0_OFFSET (0)
#define ASPEED_CLK_GRP_1_OFFSET (32)
#define ASPEED_CLK_GRP_2_OFFSET (64)
#define ASPEED_CLK_MCLK (ASPEED_CLK_GRP_0_OFFSET + 0)
#define ASPEED_CLK_... | /content/code_sandbox/include/zephyr/dt-bindings/clock/ast10x0_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 662 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/* RM0477 */
/** System clock */
/* defined in stm32_common_clocks.h */
/** Fixed clocks */
/* Low speed clocks de... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,756 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHBEN_OFFSET 0x14U
#define GD32_APB1EN_OFFSET 0x1CU
#define GD32_APB2EN_O... | /content/code_sandbox/include/zephyr/dt-bindings/clock/gd32e50x-clocks.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,389 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_
#define ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_
#include <zephyr/dt-bindings/clock/renesas-ra-cgc.h>
#endif /* ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ */
``` | /content/code_sandbox/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_
#define NXP_S32_FIRC_CLK 1U
#define NXP_S32_FXOSC_CLK 2U
#define NXP_S32_SIRC_CLK 3U
#define NXP... | /content/code_sandbox/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,568 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_
/* clock bus references */
#define STM32_CLOCK_BUS_AHB1 0
#define STM32_CLOCK_BUS_AHB2 1
#define STM32_CLOCK_BUS_APB1 2
#define STM32_CLOCK_BUS_APB2 3
#define STM32_CLOCK... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 227 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32VF103_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32VF103_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHBEN_OFFSET 0x14U
#define GD32_APB1EN_OFFSET 0x1CU
#define GD32_APB2EN... | /content/code_sandbox/include/zephyr/dt-bindings/clock/gd32vf103-clocks.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 920 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K344_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K344_CLOCK_H_
#define NXP_S32_FIRC_CLK 1U
#define NXP_S32_FIRC_STANDBY_CLK 2U
#define NXP_S32_SIRC_CLK 3U
#define... | /content/code_sandbox/include/zephyr/dt-bindings/clock/nxp_s32k344_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,166 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus gatting clocks */
#define STM32_CLOCK_BUS_IOP 0x02c
#define STM32_CLOCK_BUS_AHB1 0x030
#define STM32_CLOCK_BUS_APB2 0x034
#def... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32l0_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 885 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU_CLK_SRC_PLL 1U
#define ESP32_CLK_SRC_RC_FAST 2U
#define ESP32_CLK_SRC_APLL_CLK 3U
/* Supported PLL CPU f... | /content/code_sandbox/include/zephyr/dt-bindings/clock/esp32_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 823 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus clocks */
#define STM32_CLOCK_BUS_IOP 0x034
#define STM32_CLOCK_BUS_AHB1 0x038
#define STM32_CLOCK_BUS_APB1 0x03c
#define STM3... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32g0_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,268 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHBEN_OFFSET 0x14U
#define GD32_APB1EN_OFFSET 0x1CU
#define GD32_APB2EN_O... | /content/code_sandbox/include/zephyr/dt-bindings/clock/gd32f403-clocks.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,144 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x048
#define STM32_CLOCK_BUS_AHB2 0x04c
#define STM32_CLOCK_BUS_AHB3 0x050
#define STM3... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32l4_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,469 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCX_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCX_CLOCK_H_
/* clock bus references */
#define NPCX_CLOCK_BUS_FREERUN 0
#define NPCX_CLOCK_BUS_LFCLK 1
#define NPCX_CLOCK_BUS_OSC 2
#define NPCX_CLOCK_BUS_FIU 3
#define N... | /content/code_sandbox/include/zephyr/dt-bindings/clock/npcx_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 344 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_
#define KINETIS_SIM_CORESYS_CLK 0
#define KINETIS_SIM_PLATFORM_CLK 1
#define KINETIS_SIM_BUS_CLK 2
#define KINETIS_SIM_FAST_PERIPHERAL_CLK 5
#define KINETIS_SIM_LPO_CLK 19
#defin... | /content/code_sandbox/include/zephyr/dt-bindings/clock/kinetis_sim.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 283 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_
#define RPI_PICO_PLL_SYS 0
#define RPI_PICO_PLL_USB 1
#define RPI_PICO_PLL_COUNT 2
#define RPI_PICO_GPIN_0 0
#define RPI_PICO_GPIN_1 1
#define RPI_PICO_GPIN_COUNT ... | /content/code_sandbox/include/zephyr/dt-bindings/clock/rpi_pico_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 442 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_
#include "renesas_cpg_mssr.h"
/* r8a7795 CPG Core Clocks */
#define R8A7795_CLK_Z 0
#define R8A7795_CLK_Z2 1
#define R8A7795_CLK_ZR 2
#define R8A7795_CLK_... | /content/code_sandbox/include/zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 833 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_
#define ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_
#define RA_CLOCK(grp, func, ch) ((grp << 28) | (func << 20) | ch)
#define RA_CLOCK_GROUP(mod) (((mod >> 28) & 0xF) * 4)
#define RA_CLOCK_BIT(mod) BIT(((mod >> 20) & 0xFF) - ((mod >> 0) & 0... | /content/code_sandbox/include/zephyr/dt-bindings/clock/renesas-ra-cgc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,045 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus gatting clocks */
#define STM32_CLOCK_BUS_AHB1 0x01c
#define STM32_CLOCK_BUS_APB2 0x020
#define STM32_CLOCK_BUS_APB1 0x024
#de... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32l1_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 594 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus gatting clocks */
#define STM32_CLOCK_BUS_AHB1 0x014
#define STM32_CLOCK_BUS_APB2 0x018
#define STM32_CLOCK_BUS_APB1 0x01c
#de... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f0_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 849 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_
#define NXP_S32_LPO_128K_CLK 1U
#define NXP_S32_SIRC_CLK 2U
#define NXP_S32_SIRC_VLP_CLK 3U
#define... | /content/code_sandbox/include/zephyr/dt-bindings/clock/nxp_s32k146_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,327 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU_CLK_SRC_PLL 1U
#define ESP32_CLK_SRC_RC_FAST 2U
#define ESP32_CLK_SRC_APLL_CLK 3U
/* Supported PLL C... | /content/code_sandbox/include/zephyr/dt-bindings/clock/esp32s2_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 755 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x048
#define STM32_CLOCK_BUS_AHB2 0x04c
#define STM32_CLOCK_BUS_AHB3 0x050
#define STM3... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32wb_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,111 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_
/*
* Define 16 bits clock ID: 0xXXXX
* The highest 8 bits is Peripheral ID
* The lowest 8 bits is Instance ID
*/
#define IMX_CCM_PERIPHERAL_MASK 0xFF00UL
#define IMX_CCM_INSTANCE_MASK ... | /content/code_sandbox/include/zephyr/dt-bindings/clock/imx_ccm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 795 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU_CLK_SRC_PLL 1U
#define ESP32_CLK_SRC_RC_FAST 2U
/* Supported CPU frequencies */
#define ESP32_CLK_CP... | /content/code_sandbox/include/zephyr/dt-bindings/clock/esp32c3_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 695 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E10X_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E10X_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHBEN_OFFSET 0x14U
#define GD32_APB1EN_OFFSET 0x1CU
#define GD32_APB2EN_O... | /content/code_sandbox/include/zephyr/dt-bindings/clock/gd32e10x-clocks.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,068 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_
/** System clock */
#define STM32_SRC_SYSCLK 0x001
/** Fixed clocks */
#define STM32_SRC_LSE 0x002
#define STM32_SRC_LSI 0x003
/** Dummy: Add a specifier when no ... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32_common_clocks.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_COMMON_H_
/**
* Encode RCU register offset and configuration bit.
*
* - 0..5: bit number
* - 6..14: offset
* - 15: reserved
*
* @param reg RCU register name (expands to GD32_{reg}_OFFS... | /content/code_sandbox/include/zephyr/dt-bindings/clock/gd32-clocks-common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 149 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHBEN_OFFSET 0x14U
#define GD32_APB1EN_OFFSET 0x1CU
#define GD32_APB2EN_O... | /content/code_sandbox/include/zephyr/dt-bindings/clock/gd32a50x-clocks.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 919 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x030
#define STM32_CLOCK_BUS_AHB2 0x034
#define STM32_CLOCK_BUS_AHB3... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f4_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 806 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M2L31_CLOCK_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M2L31_CLOCK_H
#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT 0x00000000
#define NUMAKER_CLK_CLKSEL0_HCLKSEL_LXT 0x00000001
#define NUMAKER_CLK_CLKSEL0_HCLKSEL_PLL 0x00000002
#define NUMAKE... | /content/code_sandbox/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,093 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHB1EN_OFFSET 0x30U
#define GD32_AHB2EN_OFFSET 0x34U
#define GD32_AHB3EN_O... | /content/code_sandbox/include/zephyr/dt-bindings/clock/gd32f4xx-clocks.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,646 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/* RM0481/0492, Table 47 Kernel clock distribution summary */
/** System clock */
/* defined in stm32_common_clocks.h */
... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32h5_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,160 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
/** @brief RCC_DCKCFGR register offset */
#define DCKCFGR_REG 0x8C
/** @brief Device domain clocks selection helpers */
/** DCKCFGR devices */
#define CKDFSDM2A_SEL(val) ST... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f427_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 286 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_
/* PLL 32KHz clock source VTR rail ON. */
#define MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC 0U
#define MCHP_XEC_PLL_CLK32K_SRC_XTAL 1U
#define MCHP_XEC_PLL_CLK32K_SRC_PIN 2U
/* Peripheral 32KHz... | /content/code_sandbox/include/zephyr/dt-bindings/clock/mchp_xec_pcr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 322 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/* RM0468, Table 56 Kernel clock distribution summary */
/** System clock */
/* defined in stm32_common_clocks.h */
/** F... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32u5_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,957 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
/** @brief RCC_DCKCFGR register offset */
#define DCKCFGR_REG 0x8C
#define DCKCFGR2_REG 0x94
/** @brief Device domain clocks selection helpers */
/** DCKCFGR devices */
#d... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f410_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 450 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x014
#define STM32_CLOCK_BUS_APB2 0x018
#define STM32_CLOCK_BUS_APB1... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f1_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 689 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_
#include "stm32_common_clocks.h"
/** Peripheral clock sources */
/* RM0493, Figure 30, clock tree */
/** System clock */
/* defined in stm32_common_clocks.h */
/** Fixed clo... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32wba_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,205 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus gatting clocks */
#define STM32_CLOCK_BUS_AHB1 0x014
#define STM32_CLOCK_BUS_APB2 0x018
#define STM32_CLOCK_BUS_APB1 0x01c
#de... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f3_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,130 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/* RM0468, Table 56 Kernel clock dictribution summary */
/** System clock */
/* defined in stm32_common_clocks.h */
/** ... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32h7_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,019 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus clocks */
#define STM32_CLOCK_BUS_IOP 0x034
#define STM32_CLOCK_BUS_AHB1 0x038
#define STM32_CLOCK_BUS_APB1 0x03c
#define STM3... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32c0_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 801 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU_CLK_SRC_PLL 1U
#define ESP32_CLK_SRC_RC_FAST 2U
/* Supported CPU frequencies */
#define ESP32_CLK_CP... | /content/code_sandbox/include/zephyr/dt-bindings/clock/esp32c6_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 819 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ADI_MAX32_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ADI_MAX32_CLOCK_H_
/** Peripheral clock register */
#define ADI_MAX32_CLOCK_BUS0 0
#define ADI_MAX32_CLOCK_BUS1 1
#define ADI_MAX32_CLOCK_BUS2 2
/** Clock source for peripheral interfaces lik... | /content/code_sandbox/include/zephyr/dt-bindings/clock/adi_max32_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 268 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHBEN_OFFSET 0x14U
#define GD32_APB1EN_OFFSET 0x1CU
#define GD32_APB2EN_O... | /content/code_sandbox/include/zephyr/dt-bindings/clock/gd32f3x0-clocks.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 824 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_
#include "renesas_cpg_mssr.h"
/* r8a779f0 CPG Core Clocks */
#define R8A779F0_CLK_Z0 0
#define R8A779F0_CLK_Z1 1
#define R8A779F0_CLK_ZR 2
#define R8A77... | /content/code_sandbox/include/zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 936 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x048
#define STM32_CLOCK_BUS_AHB2 0x04c
#define STM32_CLOCK_BUS_AHB3 0x050
#define STM3... | /content/code_sandbox/include/zephyr/dt-bindings/clock/stm32g4_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,291 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_
/* Note- clock identifiers in this file must be unique,
* as the driver uses them in a switch case
*/
#define MCUX_LPC_CLK_ID(high, low) ((high << 8) | (low))
/* These I... | /content/code_sandbox/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,418 |
```objective-c
/*
*
*/
#define ACPI_IRQ_DETECT 0xFFFFFFFU
#define ACPI_IRQ_FLAG_DETECT 0xFFFFFFFU
``` | /content/code_sandbox/include/zephyr/dt-bindings/acpi/acpi.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28U
... | /content/code_sandbox/include/zephyr/dt-bindings/reset/gd32f403.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,048 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_
/**
* Pack RCC register offset and bit in one 32-bit value.
*
* 5 LSBs are used to keep bit number in 32-bit RCC register.
* Next 12 bits are used to keep RCC regi... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32-common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 163 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H
/* Beginning of M2L31 BSP sys_reg.h reset module copy */
#define LPSCC_IPRST0_LPPDMA0RST_Pos 0
#define LPSCC_IPRST0_LPGPIORST_Pos 1
#define LPSCC_IPRST0_... | /content/code_sandbox/include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,850 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28U
... | /content/code_sandbox/include/zephyr/dt-bindings/reset/gd32e10x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,030 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_
#define ASPEED_RESET_GRP_0_OFFSET (0)
#define ASPEED_RESET_GRP_1_OFFSET (32)
#define ASPEED_RESET_HACE (ASPEED_RESET_GRP_0_OFFSET + 4)
#define ASPEED_RESET_USB (ASPEED_RESET_GRP_0_OFFSET... | /content/code_sandbox/include/zephyr/dt-bindings/reset/ast10x0_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 531 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX9_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX9_RESET_H
#define NPCX_RESET_SWRST_CTL1_OFFSET 0
#define NPCX_RESET_SWRST_CTL2_OFFSET 32
#define NPCX_RESET_SWRST_CTL3_OFFSET 64
#define NPCX_RESET_SWRST_CTL4_OFFSET 96
#define NPCX_RESET_GPIO... | /content/code_sandbox/include/zephyr/dt-bindings/reset/npcx9_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,901 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G4_L4_5_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G4_L4_5_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x28
#define STM32_RESET_BUS_AHB2 0x2C
#define STM32_RESET_BUS_AHB3 0x30... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 166 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB_L_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB_L_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x28
#define STM32_RESET_BUS_AHB2 0x2C
#define STM32_RESET_BUS_AHB3 0x30
#defi... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32wb_l_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 167 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28U
... | /content/code_sandbox/include/zephyr/dt-bindings/reset/gd32f3x0.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 726 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F0_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F0_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x28
#define STM32_RESET_BUS_APB1 0x10
#define STM32_RESET_BUS_APB2 0x0C
#endif /* Z... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32f0_1_3_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHBRST_OFFSET 0x28U
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_APB2RST_OFFSET 0x0CU
... | /content/code_sandbox/include/zephyr/dt-bindings/reset/gd32a50x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 953 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G0_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G0_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_IOP 0x24
#define STM32_RESET_BUS_AHB1 0x28
#define STM32_RESET_BUS_APB1L 0x2C
#define S... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32g0_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 127 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H5_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H5_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x60
#define STM32_RESET_BUS_AHB2 0x64
#define STM32_RESET_BUS_AHB4 0x6C
#define S... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32h5_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 167 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHB1RST_OFFSET 0x10U
#define GD32_AHB2RST_OFFSET 0x14U
#define GD32_AHB3RST_OFFSET 0x18U
... | /content/code_sandbox/include/zephyr/dt-bindings/reset/gd32f4xx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,713 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L0_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L0_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_IOP 0x1C
#define STM32_RESET_BUS_AHB1 0x20
#define STM32_RESET_BUS_APB1 0x28
#define STM3... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32l0_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7RS_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7RS_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x80
#define STM32_RESET_BUS_AHB2 0x84
#define STM32_RESET_BUS_AHB3 0xA4
#defi... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32h7rs_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 210 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M46X_CLOCK_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M46X_CLOCK_H
/* Beginning of M460 BSP clk_reg.h copy */
#define NUMAKER_CLK_AHBCLK0_PDMA0CKEN_Pos (1)
#define NUMAKER_CLK_AHBCLK0_ISPCKEN_Pos (2)
#define NUMAKER_CLK_AHBCLK0_EBI... | /content/code_sandbox/include/zephyr/dt-bindings/clock/numaker_m46x_clock.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24,766 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28U
... | /content/code_sandbox/include/zephyr/dt-bindings/reset/gd32e50x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,263 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U5_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U5_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x60
#define STM32_RESET_BUS_AHB2L 0x64
#define STM32_RESET_BUS_AHB2H 0x68
#define S... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32u5_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 180 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28... | /content/code_sandbox/include/zephyr/dt-bindings/reset/gd32vf103.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 854 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F2_4_7_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F2_4_7_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x10
#define STM32_RESET_BUS_AHB2 0x14
#define STM32_RESET_BUS_AHB3 0x18
#def... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32f2_4_7_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 146 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x80
#define STM32_RESET_BUS_AHB2 0x84
#define STM32_RESET_BUS_AHB3 0x7C
#define S... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32h7_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 194 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32C0_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32C0_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_IOP 0x24
#define STM32_RESET_BUS_AHB1 0x28
#define STM32_RESET_BUS_APB1L 0x2C
#define S... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32c0_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 127 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H
#define NPCX_RESET_SWRST_CTL1_OFFSET 0
#define NPCX_RESET_SWRST_CTL2_OFFSET 32
#define NPCX_RESET_SWRST_CTL3_OFFSET 64
#define NPCX_RESET_SWRST_CTL4_OFFSET 96
#define NPCX_RESET_GPIO... | /content/code_sandbox/include/zephyr/dt-bindings/reset/npcx4_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,131 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_
/**
* Pack RCC register offset and bit in one 32-bit value.
*
* 5 LSBs are used to keep bit number in 32-bit RCC register.
* Next 12 bits are used to keep reset set regist... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32mp1_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 520 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_
/**
* Encode RCU register offset and configuration bit.
*
* - 0..5: bit number
* - 6..14: offset
* - 15: reserved
*
* @param reg RCU register name (expands to GD3... | /content/code_sandbox/include/zephyr/dt-bindings/reset/gd32-common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WBA_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WBA_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x60
#define STM32_RESET_BUS_AHB2 0x64
#define STM32_RESET_BUS_AHB4 0x6C
#define... | /content/code_sandbox/include/zephyr/dt-bindings/reset/stm32wba_reset.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 180 |
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