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```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_RISCV_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_RISCV_H_ #include <zephyr/sys/util_macro.h> #include <zephyr/dt-bindings/memory-attr/memory-attr.h> /* * Architecture specific RISCV related attributes. */ #define DT_MEM_RISCV_MASK DT_MEM_ARCH_ATTR_MASK #define DT_MEM_RISCV_GET(x) ((x) & DT_MEM_RISCV_MASK) #define DT_MEM_RISCV(x) ((x) << DT_MEM_ARCH_ATTR_SHIFT) #define ATTR_RISCV_TYPE_MAIN BIT(0) #define ATTR_RISCV_TYPE_IO BIT(1) #define ATTR_RISCV_TYPE_EMPTY BIT(2) #define ATTR_RISCV_AMO_SWAP BIT(3) #define ATTR_RISCV_AMO_LOGICAL BIT(4) #define ATTR_RISCV_AMO_ARITHMETIC BIT(5) #define ATTR_RISCV_IO_IDEMPOTENT_READ BIT(6) #define ATTR_RISCV_IO_IDEMPOTENT_WRITE BIT(7) #define DT_MEM_RISCV_TYPE_MAIN DT_MEM_RISCV(ATTR_RISCV_TYPE_MAIN) #define DT_MEM_RISCV_TYPE_IO DT_MEM_RISCV(ATTR_RISCV_TYPE_IO) #define DT_MEM_RISCV_TYPE_EMPTY DT_MEM_RISCV(ATTR_RISCV_TYPE_EMPTY) #define DT_MEM_RISCV_AMO_SWAP DT_MEM_RISCV(ATTR_RISCV_AMO_SWAP) #define DT_MEM_RISCV_AMO_LOGICAL DT_MEM_RISCV(ATTR_RISCV_AMO_LOGICAL) #define DT_MEM_RISCV_AMO_ARITHMETIC DT_MEM_RISCV(ATTR_RISCV_AMO_ARITHMETIC) #define DT_MEM_RISCV_IO_IDEMPOTENT_READ DT_MEM_RISCV(ATTR_RISCV_IO_IDEMPOTENT_READ) #define DT_MEM_RISCV_IO_IDEMPOTENT_WRITE DT_MEM_RISCV(ATTR_RISCV_IO_IDEMPOTENT_WRITE) #define DT_MEM_RISCV_UNKNOWN DT_MEM_ARCH_ATTR_UNKNOWN #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_RISCV_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/memory-attr/memory-attr-riscv.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
496
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_XTENSA_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_XTENSA_H_ #include <zephyr/sys/util_macro.h> #include <zephyr/dt-bindings/memory-attr/memory-attr.h> /* * Architecture specific Xtensa related attributes. */ #define DT_MEM_XTENSA_MASK DT_MEM_ARCH_ATTR_MASK #define DT_MEM_XTENSA_GET(x) ((x) & DT_MEM_XTENSA_MASK) #define DT_MEM_XTENSA(x) ((x) << DT_MEM_ARCH_ATTR_SHIFT) #define ATTR_XTENSA_INSTR_ROM BIT(0) #define ATTR_XTENSA_INSTR_RAM BIT(1) #define ATTR_XTENSA_DATA_ROM BIT(2) #define ATTR_XTENSA_DATA_RAM BIT(3) #define ATTR_XTENSA_XLMI BIT(4) #define DT_MEM_XTENSA_INSTR_ROM DT_MEM_XTENSA(ATTR_XTENSA_INSTR_ROM) #define DT_MEM_XTENSA_INSTR_RAM DT_MEM_XTENSA(ATTR_XTENSA_INSTR_RAM) #define DT_MEM_XTENSA_DATA_ROM DT_MEM_XTENSA(ATTR_XTENSA_DATA_ROM) #define DT_MEM_XTENSA_DATA_RAM DT_MEM_XTENSA(ATTR_XTENSA_DATA_RAM) #define DT_MEM_XTENSA_XLMI DT_MEM_XTENSA(ATTR_XTENSA_XLMI) #define DT_MEM_XTENSA_UNKNOWN DT_MEM_ARCH_ATTR_UNKNOWN #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_XTENSA_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/memory-attr/memory-attr-xtensa.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
380
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_SW_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_SW_H_ #include <zephyr/sys/util_macro.h> #include <zephyr/dt-bindings/memory-attr/memory-attr.h> /* * Software specific memory attributes. */ #define DT_MEM_SW_MASK DT_MEM_SW_ATTR_MASK #define DT_MEM_SW_GET(x) ((x) & DT_MEM_SW_ATTR_MASK) #define DT_MEM_SW(x) ((x) << DT_MEM_SW_ATTR_SHIFT) #define ATTR_SW_ALLOC_CACHE BIT(0) #define ATTR_SW_ALLOC_NON_CACHE BIT(1) #define ATTR_SW_ALLOC_DMA BIT(2) #define DT_MEM_SW_ALLOC_CACHE DT_MEM_SW(ATTR_SW_ALLOC_CACHE) #define DT_MEM_SW_ALLOC_NON_CACHE DT_MEM_SW(ATTR_SW_ALLOC_NON_CACHE) #define DT_MEM_SW_ALLOC_DMA DT_MEM_SW(ATTR_SW_ALLOC_DMA) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_SW_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/memory-attr/memory-attr-sw.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
218
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_H_ #include <zephyr/sys/util_macro.h> /* * Generic memory attributes. * * Generic memory attributes that should be common to all architectures. */ #define DT_MEM_ATTR_MASK GENMASK(15, 0) #define DT_MEM_ATTR_GET(x) ((x) & DT_MEM_ATTR_MASK) #define DT_MEM_ATTR_SHIFT (0) #define DT_MEM_CACHEABLE BIT(0) /* cacheable */ #define DT_MEM_NON_VOLATILE BIT(1) /* non-volatile */ #define DT_MEM_OOO BIT(2) /* out-of-order */ #define DT_MEM_DMA BIT(3) /* DMA-able */ #define DT_MEM_UNKNOWN BIT(15) /* must be last */ /* to be continued */ /* * Software specific memory attributes. * * Software can define their own memory attributes if needed using the * provided mask. */ #define DT_MEM_SW_ATTR_MASK GENMASK(19, 16) #define DT_MEM_SW_ATTR_GET(x) ((x) & DT_MEM_SW_ATTR_MASK) #define DT_MEM_SW_ATTR_SHIFT (16) #define DT_MEM_SW_ATTR_UNKNOWN BIT(19) /* * Architecture specific memory attributes. * * Architectures can define their own memory attributes if needed using the * provided mask. * * See for example `include/zephyr/dt-bindings/memory-attr/memory-attr-arm.h` */ #define DT_MEM_ARCH_ATTR_MASK GENMASK(31, 20) #define DT_MEM_ARCH_ATTR_GET(x) ((x) & DT_MEM_ARCH_ATTR_MASK) #define DT_MEM_ARCH_ATTR_SHIFT (20) #define DT_MEM_ARCH_ATTR_UNKNOWN BIT(31) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/memory-attr/memory-attr.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
397
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RDC_IMX_RDC_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RDC_IMX_RDC_H_ #define A7_DOMAIN_ID 0 #define A9_DOMAIN_ID 0 #define A53_DOMAIN_ID 0 #define M4_DOMAIN_ID 1 #define M7_DOMAIN_ID 1 #define RDC_DOMAIN_PERM_NONE (0x0) #define RDC_DOMAIN_PERM_W (0x1) #define RDC_DOMAIN_PERM_R (0x2) #define RDC_DOMAIN_PERM_RW (RDC_DOMAIN_PERM_W|RDC_DOMAIN_PERM_R) #define RDC_DOMAIN_PERM(domain, perm) (perm << (domain * 2)) #define RDC_DT_VAL(nodelabel) DT_PROP(DT_NODELABEL(nodelabel), rdc) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RDC_IMX_RDC_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/rdc/imx_rdc.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
199
```objective-c /* */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_ /* PHY auto-detection alias */ #define XLNX_GEM_PHY_AUTO_DETECT 0 /* * MDC divider values * * According to the ZynqMP's gem.network_config register documentation (UG1087), * divider /32 is the reset value. The network_config[mdc_clock_division] * documentation in UG1087 is likely wrong (copied directly from the Zynq-7000), * as it claims that the MDC clock division is applied to the cpu_1x clock * which the UltraScale doesn't have. Contradicting information is provided in * the UltraScale TRM (UG1085), which mentions in chapter 34, section "Configure * the PHY", p. 1074, that the MDC clock division is applied to the IOU_SWITCH_CLK. * Xilinx's emacps driver doesn't (or no longer does) limit the range of dividers * on the UltraScale compared to the Zynq-7000. * -> Contrary to earlier revisions of this driver, all dividers are available * to both the UltraScale and the Zynq-7000. */ #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */ #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */ #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */ #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */ #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */ #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */ #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */ #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */ /* Link speed values */ #define XLNX_GEM_LINK_SPEED_10MBIT 1 #define XLNX_GEM_LINK_SPEED_100MBIT 2 #define XLNX_GEM_LINK_SPEED_1GBIT 3 /* AMBA AHB data bus width */ #define XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT 0 #define XLNX_GEM_AMBA_AHB_DBUS_WIDTH_64BIT 1 #define XLNX_GEM_AMBA_AHB_DBUS_WIDTH_128BIT 2 /* AMBA AHB burst length */ #define XLNX_GEM_AMBA_AHB_BURST_SINGLE 1 #define XLNX_GEM_AMBA_AHB_BURST_INCR4 4 #define XLNX_GEM_AMBA_AHB_BURST_INCR8 8 #define XLNX_GEM_AMBA_AHB_BURST_INCR16 16 /* Hardware RX buffer size */ #define XLNX_GEM_HW_RX_BUFFER_SIZE_1KB 0 #define XLNX_GEM_HW_RX_BUFFER_SIZE_2KB 1 #define XLNX_GEM_HW_RX_BUFFER_SIZE_4KB 2 #define XLNX_GEM_HW_RX_BUFFER_SIZE_8KB 3 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/ethernet/xlnx_gem.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
810
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_NXP_ENET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_NXP_ENET_H_ #define NXP_ENET_MII_MODE 0 #define NXP_ENET_RMII_MODE 1 #define NXP_ENET_RGMII_MODE 2 #define NXP_ENET_INVALID_MII_MODE 100 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_NXP_ENET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/ethernet/nxp_enet.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
97
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DSI_MIPI_DSI_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DSI_MIPI_DSI_H_ /** * @brief MIPI-DSI driver APIs * @defgroup mipi_dsi_interface MIPI-DSI driver APIs * @ingroup io_interfaces * @{ */ /** * @name MIPI-DSI Pixel formats. * @{ */ /** RGB888 (24bpp). */ #define MIPI_DSI_PIXFMT_RGB888 0U /** RGB666 (24bpp). */ #define MIPI_DSI_PIXFMT_RGB666 1U /** Packed RGB666 (18bpp). */ #define MIPI_DSI_PIXFMT_RGB666_PACKED 2U /** RGB565 (16bpp). */ #define MIPI_DSI_PIXFMT_RGB565 3U /** @} */ /** * @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DSI_MIPI_DSI_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/mipi_dsi/mipi_dsi.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
218
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32L23X_CLOCKS_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32L23X_CLOCKS_H_ #include "gd32-clocks-common.h" /** * @name Register offsets * @{ */ #define GD32_AHB1EN_OFFSET 0x14U #define GD32_APB1EN_OFFSET 0x1CU #define GD32_APB2EN_OFFSET 0x18U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB1 peripherals */ #define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHB1EN, 0U) #define GD32_CLOCK_SRAM0 GD32_CLOCK_CONFIG(AHB1EN, 2U) #define GD32_CLOCK_FMC GD32_CLOCK_CONFIG(AHB1EN, 4U) #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHB1EN, 6U) #define GD32_CLOCK_SRAM1 GD32_CLOCK_CONFIG(AHB1EN, 7U) #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 17U) #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 18U) #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 19U) #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHB1EN, 20U) #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB1EN, 22U) /* AHB2 peripherals */ #define GD32_CLOCK_CAU GD32_CLOCK_CONFIG(AHB2EN, 1U) #define GD32_CLOCK_TRNG GD32_CLOCK_CONFIG(AHB2EN, 3U) /* APB1 peripherals */ #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U) #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U) #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) #define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U) #define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 8U) #define GD32_CLOCK_LPTIMER GD32_CLOCK_CONFIG(APB1EN, 9U) #define GD32_CLOCK_SLCD GD32_CLOCK_CONFIG(APB1EN, 10U) #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) #define GD32_CLOCK_LPUART GD32_CLOCK_CONFIG(APB1EN, 18U) #define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U) #define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U) #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) #define GD32_CLOCK_USBD GD32_CLOCK_CONFIG(APB1EN, 23U) #define GD32_CLOCK_I2C2 GD32_CLOCK_CONFIG(APB1EN, 24U) #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) #define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(APB1EN, 30U) #define GD32_CLOCK_BKP GD32_CLOCK_CONFIG(APB1EN, 31U) /* APB2 peripherals */ #define GD32_CLOCK_SYSCFG GD32_CLOCK_CONFIG(APB2EN, 0U) #define GD32_CLOCK_CMP GD32_CLOCK_CONFIG(APB2EN, 1U) #define GD32_CLOCK_ADC GD32_CLOCK_CONFIG(APB2EN, 9U) #define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 11U) #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) #define GD32_CLOCK_DBGMCU GD32_CLOCK_CONFIG(APB2EN, 22U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/gd32l23x-clocks.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
980
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_ #include "pinctrl-rcar-common.h" /* Pins declaration */ #define PIN_NONE -1 #define PIN_D0 RCAR_GP_PIN(0, 0) #define PIN_D1 RCAR_GP_PIN(0, 1) #define PIN_D2 RCAR_GP_PIN(0, 2) #define PIN_D3 RCAR_GP_PIN(0, 3) #define PIN_D4 RCAR_GP_PIN(0, 4) #define PIN_D5 RCAR_GP_PIN(0, 5) #define PIN_D6 RCAR_GP_PIN(0, 6) #define PIN_D7 RCAR_GP_PIN(0, 7) #define PIN_D8 RCAR_GP_PIN(0, 8) #define PIN_D9 RCAR_GP_PIN(0, 9) #define PIN_D10 RCAR_GP_PIN(0, 10) #define PIN_D11 RCAR_GP_PIN(0, 11) #define PIN_D12 RCAR_GP_PIN(0, 12) #define PIN_D13 RCAR_GP_PIN(0, 13) #define PIN_D14 RCAR_GP_PIN(0, 14) #define PIN_D15 RCAR_GP_PIN(0, 15) #define PIN_A0 RCAR_GP_PIN(1, 0) #define PIN_A1 RCAR_GP_PIN(1, 1) #define PIN_A2 RCAR_GP_PIN(1, 2) #define PIN_A3 RCAR_GP_PIN(1, 3) #define PIN_A4 RCAR_GP_PIN(1, 4) #define PIN_A5 RCAR_GP_PIN(1, 5) #define PIN_A6 RCAR_GP_PIN(1, 6) #define PIN_A7 RCAR_GP_PIN(1, 7) #define PIN_A8 RCAR_GP_PIN(1, 8) #define PIN_A9 RCAR_GP_PIN(1, 9) #define PIN_A10 RCAR_GP_PIN(1, 10) #define PIN_A11 RCAR_GP_PIN(1, 11) #define PIN_A12 RCAR_GP_PIN(1, 12) #define PIN_A13 RCAR_GP_PIN(1, 13) #define PIN_A14 RCAR_GP_PIN(1, 14) #define PIN_A15 RCAR_GP_PIN(1, 15) #define PIN_A16 RCAR_GP_PIN(1, 16) #define PIN_A17 RCAR_GP_PIN(1, 17) #define PIN_A18 RCAR_GP_PIN(1, 18) #define PIN_A19 RCAR_GP_PIN(1, 19) #define PIN_CS0 RCAR_GP_PIN(1, 20) #define PIN_CS1 RCAR_GP_PIN(1, 21) #define PIN_BS RCAR_GP_PIN(1, 22) #define PIN_RD RCAR_GP_PIN(1, 23) #define PIN_RD_WR RCAR_GP_PIN(1, 24) #define PIN_WE0 RCAR_GP_PIN(1, 25) #define PIN_WE1 RCAR_GP_PIN(1, 26) #define PIN_EX_WAIT0 RCAR_GP_PIN(1, 27) #define PIN_CLKOUT RCAR_GP_PIN(1, 28) #define PIN_IRQ0 RCAR_GP_PIN(2, 0) #define PIN_IRQ1 RCAR_GP_PIN(2, 1) #define PIN_IRQ2 RCAR_GP_PIN(2, 2) #define PIN_IRQ3 RCAR_GP_PIN(2, 3) #define PIN_IRQ4 RCAR_GP_PIN(2, 4) #define PIN_IRQ5 RCAR_GP_PIN(2, 5) #define PIN_PWM0 RCAR_GP_PIN(2, 6) #define PIN_PWM1_A RCAR_GP_PIN(2, 7) #define PIN_PWM2_A RCAR_GP_PIN(2, 8) #define PIN_AVB_MDC RCAR_GP_PIN(2, 9) #define PIN_AVB_MAGIC RCAR_GP_PIN(2, 10) #define PIN_AVB_PHY_INT RCAR_GP_PIN(2, 11) #define PIN_AVB_LINK RCAR_GP_PIN(2, 12) #define PIN_AVB_AVTP_MATCH_A RCAR_GP_PIN(2, 13) #define PIN_AVB_AVTP_CAPTURE_A RCAR_GP_PIN(2, 14) #define PIN_SD0_CLK RCAR_GP_PIN(3, 0) #define PIN_SD0_CMD RCAR_GP_PIN(3, 1) #define PIN_SD0_DATA0 RCAR_GP_PIN(3, 2) #define PIN_SD0_DATA1 RCAR_GP_PIN(3, 3) #define PIN_SD0_DATA2 RCAR_GP_PIN(3, 4) #define PIN_SD0_DATA3 RCAR_GP_PIN(3, 5) #define PIN_SD1_CLK RCAR_GP_PIN(3, 6) #define PIN_SD1_CMD RCAR_GP_PIN(3, 7) #define PIN_SD1_DATA0 RCAR_GP_PIN(3, 8) #define PIN_SD1_DATA1 RCAR_GP_PIN(3, 9) #define PIN_SD1_DATA2 RCAR_GP_PIN(3, 10) #define PIN_SD1_DATA3 RCAR_GP_PIN(3, 11) #define PIN_SD0_CD RCAR_GP_PIN(3, 12) #define PIN_SD0_WP RCAR_GP_PIN(3, 13) #define PIN_SD1_CD RCAR_GP_PIN(3, 14) #define PIN_SD1_WP RCAR_GP_PIN(3, 15) #define PIN_SD2_CLK RCAR_GP_PIN(4, 0) #define PIN_SD2_CMD RCAR_GP_PIN(4, 1) #define PIN_SD2_DATA0 RCAR_GP_PIN(4, 2) #define PIN_SD2_DATA1 RCAR_GP_PIN(4, 3) #define PIN_SD2_DATA2 RCAR_GP_PIN(4, 4) #define PIN_SD2_DATA3 RCAR_GP_PIN(4, 5) #define PIN_SD2_DS RCAR_GP_PIN(4, 6) #define PIN_SD3_CLK RCAR_GP_PIN(4, 7) #define PIN_SD3_CMD RCAR_GP_PIN(4, 8) #define PIN_SD3_DATA0 RCAR_GP_PIN(4, 9) #define PIN_SD3_DATA1 RCAR_GP_PIN(4, 10) #define PIN_SD3_DATA2 RCAR_GP_PIN(4, 11) #define PIN_SD3_DATA3 RCAR_GP_PIN(4, 12) #define PIN_SD3_DATA4 RCAR_GP_PIN(4, 13) #define PIN_SD3_DATA5 RCAR_GP_PIN(4, 14) #define PIN_SD3_DATA6 RCAR_GP_PIN(4, 15) #define PIN_SD3_DATA7 RCAR_GP_PIN(4, 16) #define PIN_SD3_DS RCAR_GP_PIN(4, 17) #define PIN_SCK0 RCAR_GP_PIN(5, 0) #define PIN_RX0 RCAR_GP_PIN(5, 1) #define PIN_TX0 RCAR_GP_PIN(5, 2) #define PIN_CTS0 RCAR_GP_PIN(5, 3) #define PIN_RTS0 RCAR_GP_PIN(5, 4) #define PIN_RX1_A RCAR_GP_PIN(5, 5) #define PIN_TX1_A RCAR_GP_PIN(5, 6) #define PIN_CTS1 RCAR_GP_PIN(5, 7) #define PIN_RTS1 RCAR_GP_PIN(5, 8) #define PIN_SCK2 RCAR_GP_PIN(5, 9) #define PIN_TX2_A RCAR_GP_PIN(5, 10) #define PIN_RX2_A RCAR_GP_PIN(5, 11) #define PIN_HSCK0 RCAR_GP_PIN(5, 12) #define PIN_HRX0 RCAR_GP_PIN(5, 13) #define PIN_HTX0 RCAR_GP_PIN(5, 14) #define PIN_HCTS0 RCAR_GP_PIN(5, 15) #define PIN_HRTS0 RCAR_GP_PIN(5, 16) #define PIN_MSIOF0_SCK RCAR_GP_PIN(5, 17) #define PIN_MSIOF0_SYNC RCAR_GP_PIN(5, 18) #define PIN_MSIOF0_SS1 RCAR_GP_PIN(5, 19) #define PIN_MSIOF0_TXD RCAR_GP_PIN(5, 20) #define PIN_MSIOF0_SS2 RCAR_GP_PIN(5, 21) #define PIN_MSIOF0_RXD RCAR_GP_PIN(5, 22) #define PIN_MLB_CLK RCAR_GP_PIN(5, 23) #define PIN_MLB_SIG RCAR_GP_PIN(5, 24) #define PIN_MLB_DAT RCAR_GP_PIN(5, 25) #define PIN_SSI_SCK01239 RCAR_GP_PIN(6, 0) #define PIN_SSI_WS01239 RCAR_GP_PIN(6, 1) #define PIN_SSI_SDATA0 RCAR_GP_PIN(6, 2) #define PIN_SSI_SDATA1_A RCAR_GP_PIN(6, 3) #define PIN_SSI_SDATA2_A RCAR_GP_PIN(6, 4) #define PIN_SSI_SCK349 RCAR_GP_PIN(6, 5) #define PIN_SSI_WS349 RCAR_GP_PIN(6, 6) #define PIN_SSI_SDATA3 RCAR_GP_PIN(6, 7) #define PIN_SSI_SCK4 RCAR_GP_PIN(6, 8) #define PIN_SSI_WS4 RCAR_GP_PIN(6, 9) #define PIN_SSI_SDAT_A4 RCAR_GP_PIN(6, 10) #define PIN_SSI_SCK5 RCAR_GP_PIN(6, 11) #define PIN_SSI_WS5 RCAR_GP_PIN(6, 12) #define PIN_SSI_SDAT_A5 RCAR_GP_PIN(6, 13) #define PIN_SSI_SCK6 RCAR_GP_PIN(6, 14) #define PIN_SSI_WS6 RCAR_GP_PIN(6, 15) #define PIN_SSI_SDATA6 RCAR_GP_PIN(6, 16) #define PIN_SSI_SCK78 RCAR_GP_PIN(6, 17) #define PIN_WS78 RCAR_GP_PIN(6, 18) #define PIN_SSI_SDATA7 RCAR_GP_PIN(6, 19) #define PIN_SSI_SDATA8 RCAR_GP_PIN(6, 20) #define PIN_SSI_SDATA9_A RCAR_GP_PIN(6, 21) #define PIN_AUDIO_CLKA_A RCAR_GP_PIN(6, 22) #define PIN_AUDIO_CLKB_B RCAR_GP_PIN(6, 23) #define PIN_USB0_PWEN RCAR_GP_PIN(6, 24) #define PIN_USB0_OVC RCAR_GP_PIN(6, 25) #define PIN_USB1_PWEN RCAR_GP_PIN(6, 26) #define PIN_USB1_OVC RCAR_GP_PIN(6, 27) #define PIN_USB30_PWEN RCAR_GP_PIN(6, 28) #define PIN_USB30_OVC RCAR_GP_PIN(6, 29) #define PIN_USB2_CH3_PWEN RCAR_GP_PIN(6, 30) #define PIN_USB2_CH3_OVC RCAR_GP_PIN(6, 31) #define PIN_AVS1 RCAR_GP_PIN(7, 0) #define PIN_AVS2 RCAR_GP_PIN(7, 1) #define PIN_GP7_02 RCAR_GP_PIN(7, 2) #define PIN_GP7_03 RCAR_GP_PIN(7, 3) #define PIN_ASEBRK RCAR_NOGP_PIN(1) #define PIN_AVB_MDIO RCAR_NOGP_PIN(2) #define PIN_AVB_RD0 RCAR_NOGP_PIN(3) #define PIN_AVB_RD1 RCAR_NOGP_PIN(4) #define PIN_AVB_RD2 RCAR_NOGP_PIN(5) #define PIN_AVB_RD3 RCAR_NOGP_PIN(6) #define PIN_AVB_RXC RCAR_NOGP_PIN(7) #define PIN_AVB_RX_CTL RCAR_NOGP_PIN(8) #define PIN_AVB_TD0 RCAR_NOGP_PIN(9) #define PIN_AVB_TD1 RCAR_NOGP_PIN(10) #define PIN_AVB_TD2 RCAR_NOGP_PIN(11) #define PIN_AVB_TD3 RCAR_NOGP_PIN(12) #define PIN_AVB_TXC RCAR_NOGP_PIN(13) #define PIN_AVB_TXCREFCLK RCAR_NOGP_PIN(14) #define PIN_AVB_TX_CTL RCAR_NOGP_PIN(15) #define PIN_DU_DOTCLKIN0 RCAR_NOGP_PIN(16) #define PIN_DU_DOTCLKIN1 RCAR_NOGP_PIN(17) #define PIN_DU_DOTCLKIN2 RCAR_NOGP_PIN(18) #define PIN_DU_DOTCLKIN3 RCAR_NOGP_PIN(19) #define PIN_EXTALR RCAR_NOGP_PIN(20) #define PIN_FSCLKST_N RCAR_NOGP_PIN(21) #define PIN_MLB_REF RCAR_NOGP_PIN(22) #define PIN_PRESETOUT_N RCAR_NOGP_PIN(23) #define PIN_QSPI0_IO2 RCAR_NOGP_PIN(24) #define PIN_QSPI0_IO3 RCAR_NOGP_PIN(25) #define PIN_QSPI0_MISO_IO1 RCAR_NOGP_PIN(26) #define PIN_QSPI0_MOSI_IO0 RCAR_NOGP_PIN(27) #define PIN_QSPI0_SPCLK RCAR_NOGP_PIN(28) #define PIN_QSPI0_SSL RCAR_NOGP_PIN(29) #define PIN_QSPI1_IO2 RCAR_NOGP_PIN(30) #define PIN_QSPI1_IO3 RCAR_NOGP_PIN(31) #define PIN_QSPI1_MISO_IO1 RCAR_NOGP_PIN(32) #define PIN_QSPI1_MOSI_IO0 RCAR_NOGP_PIN(33) #define PIN_QSPI1_SPCLK RCAR_NOGP_PIN(34) #define PIN_QSPI1_SSL RCAR_NOGP_PIN(35) #define PIN_RPC_INT_N RCAR_NOGP_PIN(36) #define PIN_RPC_RESET_N RCAR_NOGP_PIN(37) #define PIN_RPC_WP_N RCAR_NOGP_PIN(38) #define PIN_TCK RCAR_NOGP_PIN(39) #define PIN_TDI RCAR_NOGP_PIN(40) #define PIN_TDO RCAR_NOGP_PIN(41) #define PIN_TMS RCAR_NOGP_PIN(42) #define PIN_TRST_N RCAR_NOGP_PIN(43) /* Pinmux function declarations */ #define FUNC_AVB_MDC IPSR(0, 0, 0) #define FUNC_MSIOD2_SS2_C IPSR(0, 0, 2) #define FUNC_AVB_MAGIC IPSR(0, 4, 0) #define FUNC_MSIOF2_SS1_C IPSR(0, 4, 2) #define FUNC_SCK4_A IPSR(0, 4, 3) #define FUNC_AVB_PHY_INT IPSR(0, 8, 0) #define FUNC_MSIOF2_SYNC_C IPSR(0, 8, 2) #define FUNC_RX4_A IPSR(0, 8, 3) #define FUNC_AVB_LINK IPSR(0, 12, 0) #define FUNC_MSIOF2_SCK_C IPSR(0, 12, 2) #define FUNC_TX4_A IPSR(0, 12, 3) #define FUNC_AVB_AVTP_MATCH_A IPSR(0, 16, 0) #define FUNC_MSIOF2_RXD_C IPSR(0, 16, 2) #define FUNC_CTS4_N_A IPSR(0, 16, 3) #define FUNC_AVB_AVTP_CAPTURE_A IPSR(0, 20, 0) #define FUNC_MSIOF2_TXD_C IPSR(0, 20, 2) #define FUNC_RTS4_N_A IPSR(0, 20, 3) #define FUNC_IRQ0 IPSR(0, 24, 0) #define FUNC_QPOLB IPSR(0, 24, 1) #define FUNC_DU_CDE IPSR(0, 24, 3) #define FUNC_VI4_DATA0_B IPSR(0, 24, 4) #define FUNC_CAN0_TX_B IPSR(0, 24, 5) #define FUNC_CANFD0_TX_B IPSR(0, 24, 6) #define FUNC_MSIOF3_SS2_E IPSR(0, 24, 7) #define FUNC_IRQ1 IPSR(0, 28, 0) #define FUNC_QPOLA IPSR(0, 28, 1) #define FUNC_DU_DISP IPSR(0, 28, 3) #define FUNC_VI4_DATA1_B IPSR(0, 28, 4) #define FUNC_CAN0_RX_B IPSR(0, 28, 5) #define FUNC_CANFD0_RX_B IPSR(0, 28, 6) #define FUNC_MSIOF3_SS1_E IPSR(0, 28, 7) #define FUNC_IRQ2 IPSR(1, 0, 0) #define FUNC_QCPV_QDE IPSR(1, 0, 1) #define FUNC_DU_EXODDF_DU_ODDF_DISP_CDE IPSR(1, 0, 3) #define FUNC_VI4_DATA2_B IPSR(1, 0, 4) #define FUNC_MSIOF3_SYNC_E IPSR(1, 0, 7) #define FUNC_PWM3_B IPSR(1, 0, 9) #define FUNC_IRQ3 IPSR(1, 4, 0) #define FUNC_QSTVB_QVE IPSR(1, 4, 1) #define FUNC_DU_DOTCLKOUT1 IPSR(1, 4, 3) #define FUNC_VI4_DATA3_B IPSR(1, 4, 4) #define FUNC_MSIOF3_SCK_E IPSR(1, 4, 7) #define FUNC_PWM4_B IPSR(1, 4, 9) #define FUNC_IRQ4 IPSR(1, 8, 0) #define FUNC_QSTH_QHS IPSR(1, 8, 1) #define FUNC_DU_EXHSYNC_DU_HSYNC IPSR(1, 8, 3) #define FUNC_VI4_DATA4_B IPSR(1, 8, 4) #define FUNC_MSIOF3_RXD_E IPSR(1, 8, 7) #define FUNC_PWM5_B IPSR(1, 8, 9) #define FUNC_IRQ5 IPSR(1, 12, 0) #define FUNC_QSTB_QHE IPSR(1, 12, 1) #define FUNC_DU_EXVSYNC_DU_VSYNC IPSR(1, 12, 3) #define FUNC_VI4_DATA5_B IPSR(1, 12, 4) #define FUNC_MSIOF3_TXD_E IPSR(1, 12, 7) #define FUNC_PWM6_B IPSR(1, 12, 9) #define FUNC_PWM0 IPSR(1, 16, 0) #define FUNC_AVB_AVTP_PPS IPSR(1, 16, 1) #define FUNC_VI4_DATA6_B IPSR(1, 16, 4) #define FUNC_IECLK_B IPSR(1, 16, 9) #define FUNC_PWM1_A IPSR(1, 20, 0) #define FUNC_HRX3_D IPSR(1, 20, 3) #define FUNC_VI4_DATA7_B IPSR(1, 20, 4) #define FUNC_IERX_B IPSR(1, 20, 9) #define FUNC_PWM2_A IPSR(1, 24, 0) #define FUNC_HTX3_D IPSR(1, 24, 3) #define FUNC_IETX_B IPSR(1, 24, 9) #define FUNC_A0 IPSR(1, 28, 0) #define FUNC_LCDOUT16 IPSR(1, 28, 1) #define FUNC_MSIOF3_SYNC_B IPSR(1, 28, 2) #define FUNC_VI4_DATA8 IPSR(1, 28, 4) #define FUNC_DU_DB0 IPSR(1, 28, 6) #define FUNC_PWM3_A IPSR(1, 28, 9) #define FUNC_A1 IPSR(2, 0, 0) #define FUNC_LCDOUT17 IPSR(2, 0, 1) #define FUNC_MSIOF3_TXD_B IPSR(2, 0, 2) #define FUNC_VI4_DATA9 IPSR(2, 0, 4) #define FUNC_DU_DB1 IPSR(2, 0, 6) #define FUNC_PWM4_A IPSR(2, 0, 9) #define FUNC_A2 IPSR(2, 4, 0) #define FUNC_LCDOUT18 IPSR(2, 4, 1) #define FUNC_MSIOF3_SCK_B IPSR(2, 4, 2) #define FUNC_VI4_DATA10 IPSR(2, 4, 4) #define FUNC_DU_DB2 IPSR(2, 4, 6) #define FUNC_PWM5_A IPSR(2, 4, 9) #define FUNC_A3 IPSR(2, 8, 0) #define FUNC_LCDOUT19 IPSR(2, 8, 1) #define FUNC_MSIOF3_RXD_B IPSR(2, 8, 2) #define FUNC_VI4_DATA11 IPSR(2, 8, 4) #define FUNC_DU_DB3 IPSR(2, 8, 6) #define FUNC_PWM6_A IPSR(2, 8, 9) #define FUNC_A4 IPSR(2, 12, 0) #define FUNC_LCDOUT20 IPSR(2, 12, 1) #define FUNC_MSIOF3_SS1_B IPSR(2, 12, 2) #define FUNC_VI4_DATA12 IPSR(2, 12, 4) #define FUNC_VI5_DATA12 IPSR(2, 12, 5) #define FUNC_DU_DB4 IPSR(2, 12, 6) #define FUNC_A5 IPSR(2, 16, 0) #define FUNC_LCDOUT21 IPSR(2, 16, 1) #define FUNC_MSIOF3_SS2_B IPSR(2, 16, 2) #define FUNC_SCK4_B IPSR(2, 16, 3) #define FUNC_VI4_DATA13 IPSR(2, 16, 4) #define FUNC_VI5_DATA13 IPSR(2, 16, 5) #define FUNC_DU_DB5 IPSR(2, 16, 6) #define FUNC_A6 IPSR(2, 20, 0) #define FUNC_LCDOUT22 IPSR(2, 20, 1) #define FUNC_MSIOF2_SS1_A IPSR(2, 20, 2) #define FUNC_RX4_B IPSR(2, 20, 3) #define FUNC_VI4_DATA14 IPSR(2, 20, 4) #define FUNC_VI5_DATA14 IPSR(2, 20, 5) #define FUNC_DU_DB6 IPSR(2, 20, 6) #define FUNC_A7 IPSR(2, 24, 0) #define FUNC_LCDOUT23 IPSR(2, 24, 1) #define FUNC_MSIOF2_SS2_A IPSR(2, 24, 2) #define FUNC_TX4_B IPSR(2, 24, 3) #define FUNC_VI4_DATA15 IPSR(2, 24, 4) #define FUNC_VI5_DATA15 IPSR(2, 24, 5) #define FUNC_DU_DB7 IPSR(2, 24, 6) #define FUNC_A8 IPSR(2, 28, 0) #define FUNC_RX3_B IPSR(2, 28, 1) #define FUNC_MSIOF2_SYNC_A IPSR(2, 28, 2) #define FUNC_HRX4_B IPSR(2, 28, 3) #define FUNC_SDA6_A IPSR(2, 28, 7) #define FUNC_AVB_AVTP_MATCH_B IPSR(2, 28, 8) #define FUNC_PWM1_B IPSR(2, 28, 9) #define FUNC_A9 IPSR(3, 0, 0) #define FUNC_MSIOF2_SCK_A IPSR(3, 0, 2) #define FUNC_CTS4_N_B IPSR(3, 0, 3) #define FUNC_VI5_VSYNC_N IPSR(3, 0, 5) #define FUNC_A10 IPSR(3, 4, 0) #define FUNC_MSIOF2_RXD_A IPSR(3, 4, 2) #define FUNC_RTS4_N_B IPSR(3, 4, 3) #define FUNC_VI5_HSYNC_N IPSR(3, 4, 5) #define FUNC_A11 IPSR(3, 8, 0) #define FUNC_TX3_B IPSR(3, 8, 1) #define FUNC_MSIOF2_TXD_A IPSR(3, 8, 2) #define FUNC_HTX4_B IPSR(3, 8, 3) #define FUNC_HSCK4 IPSR(3, 8, 4) #define FUNC_VI5_FIELD IPSR(3, 8, 5) #define FUNC_SCL6_A IPSR(3, 8, 7) #define FUNC_AVB_AVTP_CAPTURE_B IPSR(3, 8, 8) #define FUNC_PWM2_B IPSR(3, 8, 9) #define FUNC_A12 IPSR(3, 12, 0) #define FUNC_LCDOUT12 IPSR(3, 12, 1) #define FUNC_MSIOF3_SCK_C IPSR(3, 12, 2) #define FUNC_HRX4_A IPSR(3, 12, 4) #define FUNC_VI5_DATA8 IPSR(3, 12, 5) #define FUNC_DU_DG4 IPSR(3, 12, 6) #define FUNC_A13 IPSR(3, 16, 0) #define FUNC_LCDOUT13 IPSR(3, 16, 1) #define FUNC_MSIOF3_SYNC_C IPSR(3, 16, 2) #define FUNC_HTX4_A IPSR(3, 16, 4) #define FUNC_VI5_DATA9 IPSR(3, 16, 5) #define FUNC_DU_DG5 IPSR(3, 16, 6) #define FUNC_A14 IPSR(3, 20, 0) #define FUNC_LCDOUT14 IPSR(3, 20, 1) #define FUNC_MSIOF3_RXD_C IPSR(3, 20, 2) #define FUNC_HCTS4_N IPSR(3, 20, 4) #define FUNC_VI5_DATA10 IPSR(3, 20, 5) #define FUNC_DU_DG6 IPSR(3, 20, 6) #define FUNC_A15 IPSR(3, 24, 0) #define FUNC_LCDOUT15 IPSR(3, 24, 1) #define FUNC_MSIOF3_TXD_C IPSR(3, 24, 2) #define FUNC_HRTS4_N IPSR(3, 24, 4) #define FUNC_VI5_DATA11 IPSR(3, 24, 5) #define FUNC_DU_DG7 IPSR(3, 24, 6) #define FUNC_A16 IPSR(3, 28, 0) #define FUNC_LCDOUT8 IPSR(3, 28, 1) #define FUNC_VI4_FIELD IPSR(3, 28, 4) #define FUNC_DU_DG0 IPSR(3, 28, 6) #define FUNC_A17 IPSR(4, 0, 0) #define FUNC_LCDOUT9 IPSR(4, 0, 1) #define FUNC_VI4_VSYNC_N IPSR(4, 0, 4) #define FUNC_DU_DG1 IPSR(4, 0, 6) #define FUNC_A18 IPSR(4, 4, 0) #define FUNC_LCDOUT10 IPSR(4, 4, 1) #define FUNC_VI4_HSYNC_N IPSR(4, 4, 4) #define FUNC_DU_DG2 IPSR(4, 4, 6) #define FUNC_A19 IPSR(4, 8, 0) #define FUNC_LCDOUT11 IPSR(4, 8, 1) #define FUNC_VI4_CLKENB IPSR(4, 8, 4) #define FUNC_DU_DG3 IPSR(4, 8, 6) #define FUNC_CS0_N IPSR(4, 12, 0) #define FUNC_VI5_CLKENB IPSR(4, 12, 5) #define FUNC_CS1_N IPSR(4, 16, 0) #define FUNC_VI5_CLK IPSR(4, 16, 5) #define FUNC_EX_WAIT0_B IPSR(4, 16, 7) #define FUNC_BS_N IPSR(4, 20, 0) #define FUNC_QSTVA_QVS IPSR(4, 20, 1) #define FUNC_MSIOF3_SCK_D IPSR(4, 20, 2) #define FUNC_SCK3 IPSR(4, 20, 3) #define FUNC_HSCK3 IPSR(4, 20, 4) #define FUNC_CAN1_TX IPSR(4, 20, 8) #define FUNC_CANFD1_TX IPSR(4, 20, 9) #define FUNC_IETX_A IPSR(4, 20, 0xA) #define FUNC_RD_N IPSR(4, 24, 0) #define FUNC_MSIOF3_SYNC_D IPSR(4, 24, 2) #define FUNC_RX3_A IPSR(4, 24, 3) #define FUNC_HRX3_A IPSR(4, 24, 4) #define FUNC_CAN0_TX_A IPSR(4, 24, 8) #define FUNC_CANFD0_TX_A IPSR(4, 24, 9) #define FUNC_RD_WR_N IPSR(4, 28, 0) #define FUNC_MSIOF3_RXD_D IPSR(4, 28, 2) #define FUNC_TX3_A IPSR(4, 28, 3) #define FUNC_HTX3_A IPSR(4, 28, 4) #define FUNC_CAN0_RX_A IPSR(4, 28, 8) #define FUNC_CANFD0_RX_A IPSR(4, 28, 9) #define FUNC_WE0_N IPSR(5, 0, 0) #define FUNC_MSIOF3_TXD_D IPSR(5, 0, 2) #define FUNC_CTS3_N IPSR(5, 0, 3) #define FUNC_HCTS3_N IPSR(5, 0, 4) #define FUNC_SCL6_B IPSR(5, 0, 7) #define FUNC_CAN_CLK IPSR(5, 0, 8) #define FUNC_IECLK_A IPSR(5, 0, 0xA) #define FUNC_WE1_N IPSR(5, 4, 0) #define FUNC_MSIOF3_SS1_D IPSR(5, 4, 2) #define FUNC_RTS3_N IPSR(5, 4, 3) #define FUNC_HRTS3_N IPSR(5, 4, 4) #define FUNC_SDA6_B IPSR(5, 4, 7) #define FUNC_CAN1_RX IPSR(5, 4, 8) #define FUNC_CANFD1_RX IPSR(5, 4, 9) #define FUNC_IERX_A IPSR(5, 4, 0xA) #define FUNC_EX_WAIT0_A IPSR(5, 8, 0) #define FUNC_QCLK IPSR(5, 8, 1) #define FUNC_VI4_CLK IPSR(5, 8, 4) #define FUNC_DU_DOTCLKOUT0 IPSR(5, 8, 6) #define FUNC_D0 IPSR(5, 12, 0) #define FUNC_MSIOF2_SS1_B IPSR(5, 12, 1) #define FUNC_MSIOF3_SCK_A IPSR(5, 12, 2) #define FUNC_VI4_DATA16 IPSR(5, 12, 4) #define FUNC_VI5_DATA0 IPSR(5, 12, 5) #define FUNC_D1 IPSR(5, 16, 0) #define FUNC_MSIOF2_SS2_B IPSR(5, 16, 1) #define FUNC_MSIOF3_SYNC_A IPSR(5, 16, 2) #define FUNC_VI4_DATA17 IPSR(5, 16, 4) #define FUNC_VI5_DATA1 IPSR(5, 16, 5) #define FUNC_D2 IPSR(5, 20, 0) #define FUNC_MSIOF3_RXD_A IPSR(5, 20, 2) #define FUNC_VI4_DATA18 IPSR(5, 20, 4) #define FUNC_VI5_DATA2 IPSR(5, 20, 5) #define FUNC_D3 IPSR(5, 24, 0) #define FUNC_MSIOF3_TXD_A IPSR(5, 24, 2) #define FUNC_VI4_DATA19 IPSR(5, 24, 4) #define FUNC_VI5_DATA3 IPSR(5, 24, 5) #define FUNC_D4 IPSR(5, 28, 0) #define FUNC_MSIOF2_SCK_B IPSR(5, 28, 1) #define FUNC_VI4_DATA20 IPSR(5, 28, 4) #define FUNC_VI5_DATA4 IPSR(5, 28, 5) #define FUNC_D5 IPSR(6, 0, 0) #define FUNC_MSIOF2_SYNC_B IPSR(6, 0, 1) #define FUNC_VI4_DATA21 IPSR(6, 0, 4) #define FUNC_VI5_DATA5 IPSR(6, 0, 5) #define FUNC_D6 IPSR(6, 4, 0) #define FUNC_MSIOF2_RXD_B IPSR(6, 4, 1) #define FUNC_VI4_DATA22 IPSR(6, 4, 4) #define FUNC_VI5_DATA6 IPSR(6, 4, 5) #define FUNC_D7 IPSR(6, 8, 0) #define FUNC_MSIOF2_TXD_B IPSR(6, 8, 1) #define FUNC_VI4_DATA23 IPSR(6, 8, 4) #define FUNC_VI5_DATA7 IPSR(6, 8, 5) #define FUNC_D8 IPSR(6, 12, 0) #define FUNC_LCDOUT0 IPSR(6, 12, 1) #define FUNC_MSIOF2_SCK_D IPSR(6, 12, 2) #define FUNC_SCK4_C IPSR(6, 12, 3) #define FUNC_VI4_DATA0_A IPSR(6, 12, 4) #define FUNC_DU_DR0 IPSR(6, 12, 6) #define FUNC_D9 IPSR(6, 16, 0) #define FUNC_LCDOUT1 IPSR(6, 16, 1) #define FUNC_MSIOF2_SYNC_D IPSR(6, 16, 2) #define FUNC_VI4_DATA1_A IPSR(6, 16, 4) #define FUNC_DU_DR1 IPSR(6, 16, 6) #define FUNC_D10 IPSR(6, 20, 0) #define FUNC_LCDOUT2 IPSR(6, 20, 1) #define FUNC_MSIOF2_RXD_D IPSR(6, 20, 2) #define FUNC_HRX3_B IPSR(6, 20, 3) #define FUNC_VI4_DATA2_A IPSR(6, 20, 4) #define FUNC_CTS4_N_C IPSR(6, 20, 5) #define FUNC_DU_DR2 IPSR(6, 20, 6) #define FUNC_D11 IPSR(6, 24, 0) #define FUNC_LCDOUT3 IPSR(6, 24, 1) #define FUNC_MSIOF2_TXD_D IPSR(6, 24, 2) #define FUNC_HTX3_B IPSR(6, 24, 3) #define FUNC_VI4_DATA3_A IPSR(6, 24, 4) #define FUNC_RTS4_N_C IPSR(6, 24, 5) #define FUNC_DU_DR3 IPSR(6, 24, 6) #define FUNC_D12 IPSR(6, 28, 0) #define FUNC_LCDOUT4 IPSR(6, 28, 1) #define FUNC_MSIOF2_SS1_D IPSR(6, 28, 2) #define FUNC_RX4_C IPSR(6, 28, 3) #define FUNC_VI4_DATA4_A IPSR(6, 28, 4) #define FUNC_DU_DR4 IPSR(6, 28, 6) #define FUNC_D13 IPSR(7, 0, 0) #define FUNC_LCDOUT5 IPSR(7, 0, 1) #define FUNC_MSIOF2_SS2_D IPSR(7, 0, 2) #define FUNC_TX4_C IPSR(7, 0, 3) #define FUNC_VI4_DATA5_A IPSR(7, 0, 4) #define FUNC_DU_DR5 IPSR(7, 0, 6) #define FUNC_D14 IPSR(7, 4, 0) #define FUNC_LCDOUT6 IPSR(7, 4, 1) #define FUNC_MSIOF3_SS1_A IPSR(7, 4, 2) #define FUNC_HRX3_C IPSR(7, 4, 3) #define FUNC_VI4_DATA6_A IPSR(7, 4, 4) #define FUNC_DU_DR6 IPSR(7, 4, 6) #define FUNC_SCL6_C IPSR(7, 4, 7) #define FUNC_D15 IPSR(7, 8, 0) #define FUNC_LCDOUT7 IPSR(7, 8, 1) #define FUNC_MSIOF3_SS2_A IPSR(7, 8, 2) #define FUNC_HTX3_C IPSR(7, 8, 3) #define FUNC_VI4_DATA7_A IPSR(7, 8, 4) #define FUNC_DU_DR7 IPSR(7, 8, 6) #define FUNC_SDA6_C IPSR(7, 8, 7) #define FUNC_SD0_CLK IPSR(7, 16, 0) #define FUNC_MSIOF1_SCK_E IPSR(7, 16, 2) #define FUNC_STP_OPWM_0_B IPSR(7, 16, 6) #define FUNC_SD0_CMD IPSR(7, 20, 0) #define FUNC_MSIOF1_SYNC_E IPSR(7, 20, 2) #define FUNC_STP_IVCXO27_0_B IPSR(7, 20, 6) #define FUNC_SD0_DAT0 IPSR(7, 24, 0) #define FUNC_MSIOF1_RXD_E IPSR(7, 24, 2) #define FUNC_TS_SCK0_B IPSR(7, 24, 5) #define FUNC_STP_ISCLK_0_B IPSR(7, 24, 6) #define FUNC_SD0_DAT1 IPSR(7, 28, 0) #define FUNC_MSIOF1_TXD_E IPSR(7, 28, 2) #define FUNC_TS_SPSYNC0_B IPSR(7, 28, 5) #define FUNC_STP_ISSYNC_0_B IPSR(7, 28, 6) #define FUNC_SD0_DAT2 IPSR(8, 0, 0) #define FUNC_MSIOF1_SS1_E IPSR(8, 0, 2) #define FUNC_TS_SDAT0_B IPSR(8, 0, 5) #define FUNC_STP_ISD_0_B IPSR(8, 0, 6) #define FUNC_SD0_DAT3 IPSR(8, 4, 0) #define FUNC_MSIOF1_SS2_E IPSR(8, 4, 2) #define FUNC_TS_SDEN0_B IPSR(8, 4, 5) #define FUNC_STP_ISEN_0_B IPSR(8, 4, 6) #define FUNC_SD1_CLK IPSR(8, 8, 0) #define FUNC_MSIOF1_SCK_G IPSR(8, 8, 2) #define FUNC_SIM0_CLK_A IPSR(8, 8, 5) #define FUNC_SD1_CMD IPSR(8, 12, 0) #define FUNC_MSIOF1_SYNC_G IPSR(8, 12, 2) #define FUNC_NFCE_N_B IPSR(8, 12, 3) #define FUNC_SIM0_D_A IPSR(8, 12, 5) #define FUNC_STP_IVCXO27_1_B IPSR(8, 12, 6) #define FUNC_SD1_DAT0 IPSR(8, 16, 0) #define FUNC_SD2_DAT4 IPSR(8, 16, 1) #define FUNC_MSIOF1_RXD_G IPSR(8, 16, 2) #define FUNC_NFWP_N_B IPSR(8, 16, 3) #define FUNC_TS_SCK1_B IPSR(8, 16, 5) #define FUNC_STP_ISCLK_1_B IPSR(8, 16, 6) #define FUNC_SD1_DAT1 IPSR(8, 20, 0) #define FUNC_SD2_DAT5 IPSR(8, 20, 1) #define FUNC_MSIOF1_TXD_G IPSR(8, 20, 2) #define FUNC_NFDATA14_B IPSR(8, 20, 3) #define FUNC_TS_SPSYNC1_B IPSR(8, 20, 5) #define FUNC_STP_ISSYNC_1_B IPSR(8, 20, 6) #define FUNC_SD1_DAT2 IPSR(8, 24, 0) #define FUNC_SD2_DAT6 IPSR(8, 24, 1) #define FUNC_MSIOF1_SS1_G IPSR(8, 24, 2) #define FUNC_NFDATA15_B IPSR(8, 24, 3) #define FUNC_TS_SDAT1_B IPSR(8, 24, 5) #define FUNC_STP_ISD_1_B IPSR(8, 24, 6) #define FUNC_SD1_DAT3 IPSR(8, 28, 0) #define FUNC_SD2_DAT7 IPSR(8, 28, 1) #define FUNC_MSIOF1_SS2_G IPSR(8, 28, 2) #define FUNC_NFRB_N_B IPSR(8, 28, 3) #define FUNC_TS_SDEN1_B IPSR(8, 28, 5) #define FUNC_STP_ISEN_1_B IPSR(8, 28, 6) #define FUNC_SD2_CLK IPSR(9, 0, 0) #define FUNC_NFDATA8 IPSR(9, 0, 2) #define FUNC_SD2_CMD IPSR(9, 4, 0) #define FUNC_NFDATA9 IPSR(9, 4, 2) #define FUNC_SD2_DAT0 IPSR(9, 8, 0) #define FUNC_NFDATA10 IPSR(9, 8, 2) #define FUNC_SD2_DAT1 IPSR(9, 12, 0) #define FUNC_NFDATA11 IPSR(9, 12, 2) #define FUNC_SD2_DAT2 IPSR(9, 16, 0) #define FUNC_NFDATA12 IPSR(9, 16, 2) #define FUNC_SD2_DAT3 IPSR(9, 20, 0) #define FUNC_NFDATA13 IPSR(9, 20, 2) #define FUNC_SD2_DS IPSR(9, 24, 0) #define FUNC_NFALE IPSR(9, 24, 2) #define FUNC_SD3_CLK IPSR(9, 28, 0) #define FUNC_NFWE_N IPSR(9, 28, 2) #define FUNC_SD3_CMD IPSR(10, 0, 0) #define FUNC_NFRE_N IPSR(10, 0, 2) #define FUNC_SD3_DAT0 IPSR(10, 4, 0) #define FUNC_NFDATA0 IPSR(10, 4, 2) #define FUNC_SD3_DAT1 IPSR(10, 8, 0) #define FUNC_NFDATA1 IPSR(10, 8, 2) #define FUNC_SD3_DAT2 IPSR(10, 12, 0) #define FUNC_NFDATA2 IPSR(10, 12, 2) #define FUNC_SD3_DAT3 IPSR(10, 16, 0) #define FUNC_NFDATA3 IPSR(10, 16, 2) #define FUNC_SD3_DAT4 IPSR(10, 20, 0) #define FUNC_SD2_CD_A IPSR(10, 20, 1) #define FUNC_NFDATA4 IPSR(10, 20, 2) #define FUNC_SD3_DAT5 IPSR(10, 24, 0) #define FUNC_SD2_WP_A IPSR(10, 24, 1) #define FUNC_NFDATA5 IPSR(10, 24, 2) #define FUNC_SD3_DAT6 IPSR(10, 28, 0) #define FUNC_SD3_CD IPSR(10, 28, 1) #define FUNC_NFDATA6 IPSR(10, 28, 2) #define FUNC_SD3_DAT7 IPSR(11, 0, 0) #define FUNC_SD3_WP IPSR(11, 0, 1) #define FUNC_NFDATA7 IPSR(11, 0, 2) #define FUNC_SD3_DS IPSR(11, 4, 0) #define FUNC_NFCLE IPSR(11, 4, 2) #define FUNC_SD0_CD IPSR(11, 8, 0) #define FUNC_NFDATA14_A IPSR(11, 8, 2) #define FUNC_SCL2_B IPSR(11, 8, 4) #define FUNC_SIM0_RST_A IPSR(11, 8, 5) #define FUNC_SD0_WP IPSR(11, 12, 0) #define FUNC_NFDATA15_A IPSR(11, 12, 2) #define FUNC_SDA2_B IPSR(11, 12, 4) #define FUNC_SD1_CD IPSR(11, 16, 0) #define FUNC_NFRB_N_A IPSR(11, 16, 2) #define FUNC_SIM0_CLK_B IPSR(11, 16, 5) #define FUNC_SD1_WP IPSR(11, 20, 0) #define FUNC_NFCE_N_A IPSR(11, 20, 2) #define FUNC_SIM0_D_B IPSR(11, 20, 5) #define FUNC_SCK0 IPSR(11, 24, 0) #define FUNC_HSCK1_B IPSR(11, 24, 1) #define FUNC_MSIOF1_SS2_B IPSR(11, 24, 2) #define FUNC_AUDIO_CLKC_B IPSR(11, 24, 3) #define FUNC_SDA2_A IPSR(11, 24, 4) #define FUNC_SIM0_RST_B IPSR(11, 24, 5) #define FUNC_STP_OPWM_0_C IPSR(11, 24, 6) #define FUNC_RIF0_CLK_B IPSR(11, 24, 7) #define FUNC_ADICHS2 IPSR(11, 24, 9) #define FUNC_SCK5_B IPSR(11, 24, 0xA) #define FUNC_RX0 IPSR(11, 28, 0) #define FUNC_HRX1_B IPSR(11, 28, 1) #define FUNC_TS_SCK0_C IPSR(11, 28, 5) #define FUNC_STP_ISCLK_0_C IPSR(11, 28, 6) #define FUNC_RIF0_D0_B IPSR(11, 28, 7) #define FUNC_TX0 IPSR(12, 0, 0) #define FUNC_HTX1_B IPSR(12, 0, 1) #define FUNC_TS_SPSYNC0_C IPSR(12, 0, 5) #define FUNC_STP_ISSYNC_0_C IPSR(12, 0, 6) #define FUNC_RIF0_D1_B IPSR(12, 0, 7) #define FUNC_CTS0_N IPSR(12, 4, 0) #define FUNC_HCTS1_N_B IPSR(12, 4, 1) #define FUNC_MSIOF1_SYNC_B IPSR(12, 4, 2) #define FUNC_TS_SPSYNC1_C IPSR(12, 4, 5) #define FUNC_STP_ISSYNC_1_C IPSR(12, 4, 6) #define FUNC_RIF1_SYNC_B IPSR(12, 4, 7) #define FUNC_AUDIO_CLKOUT_C IPSR(12, 4, 8) #define FUNC_ADICS_SAMP IPSR(12, 4, 9) #define FUNC_RTS0_N IPSR(12, 8, 0) #define FUNC_HRTS1_N_B IPSR(12, 8, 1) #define FUNC_MSIOF1_SS1_B IPSR(12, 8, 2) #define FUNC_AUDIO_CLKA_B IPSR(12, 8, 3) #define FUNC_SCL2_A IPSR(12, 8, 4) #define FUNC_STP_IVCXO27_1_C IPSR(12, 8, 6) #define FUNC_RIF0_SYNC_B IPSR(12, 8, 7) #define FUNC_ADICHS1 IPSR(12, 8, 9) #define FUNC_RX1_A IPSR(12, 12, 0) #define FUNC_HRX1_A IPSR(12, 12, 1) #define FUNC_TS_SDAT0_C IPSR(12, 12, 5) #define FUNC_STP_ISD_0_C IPSR(12, 12, 6) #define FUNC_RIF1_CLK_C IPSR(12, 12, 7) #define FUNC_TX1_A IPSR(12, 16, 0) #define FUNC_HTX1_A IPSR(12, 16, 1) #define FUNC_TS_SDEN0_C IPSR(12, 16, 5) #define FUNC_STP_ISEN_0_C IPSR(12, 16, 6) #define FUNC_RIF1_D0_C IPSR(12, 16, 7) #define FUNC_CTS1_N IPSR(12, 20, 0) #define FUNC_HCTS1_N_A IPSR(12, 20, 1) #define FUNC_MSIOF1_RXD_B IPSR(12, 20, 2) #define FUNC_TS_SDEN1_C IPSR(12, 20, 5) #define FUNC_STP_ISEN_1_C IPSR(12, 20, 6) #define FUNC_RIF1_D0_B IPSR(12, 20, 7) #define FUNC_ADIDATA IPSR(12, 20, 9) #define FUNC_RTS1_N IPSR(12, 24, 0) #define FUNC_HRTS1_N_A IPSR(12, 24, 1) #define FUNC_MSIOF1_TXD_B IPSR(12, 24, 2) #define FUNC_TS_SDAT1_C IPSR(12, 24, 5) #define FUNC_STP_ISD_1_C IPSR(12, 24, 6) #define FUNC_RIF1_D1_B IPSR(12, 24, 7) #define FUNC_ADICHS0 IPSR(12, 24, 9) #define FUNC_SCK2 IPSR(12, 28, 0) #define FUNC_SCIF_CLK_B IPSR(12, 28, 1) #define FUNC_MSIOF1_SCK_B IPSR(12, 28, 2) #define FUNC_TS_SCK1_C IPSR(12, 28, 5) #define FUNC_STP_ISCLK_1_C IPSR(12, 28, 6) #define FUNC_RIF1_CLK_B IPSR(12, 28, 7) #define FUNC_ADICLK IPSR(12, 28, 9) #define FUNC_TX2_A IPSR(13, 0, 0) #define FUNC_SD2_CD_B IPSR(13, 0, 3) #define FUNC_SCL1_A IPSR(13, 0, 4) #define FUNC_FMCLK_A IPSR(13, 0, 6) #define FUNC_RIF1_D1_C IPSR(13, 0, 7) #define FUNC_FSO_CFE_0_N IPSR(13, 0, 9) #define FUNC_RX2_A IPSR(13, 4, 0) #define FUNC_SD2_WP_B IPSR(13, 4, 3) #define FUNC_SDA1_A IPSR(13, 4, 4) #define FUNC_FMIN_A IPSR(13, 4, 6) #define FUNC_RIF1_SYNC_C IPSR(13, 4, 7) #define FUNC_FSO_CFE_1_N IPSR(13, 4, 9) #define FUNC_HSCK0 IPSR(13, 8, 0) #define FUNC_MSIOF1_SCK_D IPSR(13, 8, 2) #define FUNC_AUDIO_CLKB_A IPSR(13, 8, 3) #define FUNC_SSI_SDATA1_B IPSR(13, 8, 4) #define FUNC_TS_SCK0_D IPSR(13, 8, 5) #define FUNC_STP_ISCLK_0_D IPSR(13, 8, 6) #define FUNC_RIF0_CLK_C IPSR(13, 8, 7) #define FUNC_RX5_B IPSR(13, 8, 0xA) #define FUNC_HRX0 IPSR(13, 12, 0) #define FUNC_MSIOF1_RXD_D IPSR(13, 12, 2) #define FUNC_SSI_SDATA2_B IPSR(13, 12, 4) #define FUNC_TS_SDEN0_D IPSR(13, 12, 5) #define FUNC_STP_ISEN_0_D IPSR(13, 12, 6) #define FUNC_RIF0_D0_C IPSR(13, 12, 7) #define FUNC_HTX0 IPSR(13, 16, 0) #define FUNC_MSIOF1_TXD_D IPSR(13, 16, 2) #define FUNC_SSI_SDATA9_B IPSR(13, 16, 4) #define FUNC_TS_SDAT0_D IPSR(13, 16, 5) #define FUNC_STP_ISD_0_D IPSR(13, 16, 6) #define FUNC_RIF0_D1_C IPSR(13, 16, 7) #define FUNC_HCTS0_N IPSR(13, 20, 0) #define FUNC_RX2_B IPSR(13, 20, 1) #define FUNC_MSIOF1_SYNC_D IPSR(13, 20, 2) #define FUNC_SSI_SCK9_A IPSR(13, 20, 4) #define FUNC_TS_SPSYNC0_D IPSR(13, 20, 5) #define FUNC_STP_ISSYNC_0_D IPSR(13, 20, 6) #define FUNC_RIF0_SYNC_C IPSR(13, 20, 7) #define FUNC_AUDIO_CLKOUT1_A IPSR(13, 20, 8) #define FUNC_HRTS0_N IPSR(13, 24, 0) #define FUNC_TX2_B IPSR(13, 24, 1) #define FUNC_MSIOF1_SS1_D IPSR(13, 24, 2) #define FUNC_SSI_WS9_A IPSR(13, 24, 4) #define FUNC_STP_IVCXO27_0_D IPSR(13, 24, 6) #define FUNC_BPFCLK_A IPSR(13, 24, 7) #define FUNC_AUDIO_CLKOUT2_A IPSR(13, 24, 8) #define FUNC_MSIOF0_SYNC IPSR(13, 28, 0) #define FUNC_AUDIO_CLKOUT_A IPSR(13, 28, 8) #define FUNC_TX5_B IPSR(13, 28, 0xA) #define FUNC_BPFCLK_D IPSR(13, 28, 0xD) #define FUNC_MSIOF0_SS1 IPSR(14, 0, 0) #define FUNC_RX5_A IPSR(14, 0, 1) #define FUNC_NFWP_N_A IPSR(14, 0, 2) #define FUNC_AUDIO_CLKA_C IPSR(14, 0, 3) #define FUNC_SSI_SCK2_A IPSR(14, 0, 4) #define FUNC_STP_IVCXO27_0_C IPSR(14, 0, 6) #define FUNC_AUDIO_CLKOUT3_A IPSR(14, 0, 8) #define FUNC_TCLK1_B IPSR(14, 0, 0xA) #define FUNC_MSIOF0_SS2 IPSR(14, 4, 0) #define FUNC_TX5_A IPSR(14, 4, 1) #define FUNC_MSIOF1_SS2_D IPSR(14, 4, 2) #define FUNC_AUDIO_CLKC_A IPSR(14, 4, 3) #define FUNC_SSI_WS2_A IPSR(14, 4, 4) #define FUNC_STP_OPWM_0_D IPSR(14, 4, 6) #define FUNC_AUDIO_CLKOUT_D IPSR(14, 4, 8) #define FUNC_SPEEDIN_B IPSR(14, 4, 0xA) #define FUNC_MLB_CLK IPSR(14, 8, 0) #define FUNC_MSIOF1_SCK_F IPSR(14, 8, 2) #define FUNC_SCL1_B IPSR(14, 8, 4) #define FUNC_MLB_SIG IPSR(14, 12, 0) #define FUNC_RX1_B IPSR(14, 12, 1) #define FUNC_MSIOF1_SYNC_F IPSR(14, 12, 2) #define FUNC_SDA1_B IPSR(14, 12, 4) #define FUNC_MLB_DAT IPSR(14, 16, 0) #define FUNC_TX1_B IPSR(14, 16, 1) #define FUNC_MSIOF1_RXD_F IPSR(14, 16, 2) #define FUNC_SSI_SCK01239 IPSR(14, 20, 0) #define FUNC_MSIOF1_TXD_F IPSR(14, 20, 2) #define FUNC_SSI_WS01239 IPSR(14, 24, 0) #define FUNC_MSIOF1_SS1_F IPSR(14, 24, 2) #define FUNC_SSI_SDATA0 IPSR(14, 28, 0) #define FUNC_MSIOF1_SS2_F IPSR(14, 28, 2) #define FUNC_SSI_SDATA1_A IPSR(15, 0, 0) #define FUNC_SSI_SDATA2_A IPSR(15, 4, 0) #define FUNC_SSI_SCK1_B IPSR(15, 4, 4) #define FUNC_SSI_SCK349 IPSR(15, 8, 0) #define FUNC_MSIOF1_SS1_A IPSR(15, 8, 2) #define FUNC_STP_OPWM_0_A IPSR(15, 8, 6) #define FUNC_SSI_WS349 IPSR(15, 12, 0) #define FUNC_HCTS2_N_A IPSR(15, 12, 1) #define FUNC_MSIOF1_SS2_A IPSR(15, 12, 2) #define FUNC_STP_IVCXO27_0_A IPSR(15, 12, 6) #define FUNC_SSI_SDATA3 IPSR(15, 16, 0) #define FUNC_HRTS2_N_A IPSR(15, 16, 1) #define FUNC_MSIOF1_TXD_A IPSR(15, 16, 2) #define FUNC_TS_SCK0_A IPSR(15, 16, 5) #define FUNC_STP_ISCLK_0_A IPSR(15, 16, 6) #define FUNC_RIF0_D1_A IPSR(15, 16, 7) #define FUNC_RIF2_D0_A IPSR(15, 16, 8) #define FUNC_SSI_SCK4 IPSR(15, 20, 0) #define FUNC_HRX2_A IPSR(15, 20, 1) #define FUNC_MSIOF1_SCK_A IPSR(15, 20, 2) #define FUNC_TS_SDAT0_A IPSR(15, 20, 5) #define FUNC_STP_ISD_0_A IPSR(15, 20, 6) #define FUNC_RIF0_CLK_A IPSR(15, 20, 7) #define FUNC_RIF2_CLK_A IPSR(15, 20, 8) #define FUNC_SSI_WS4 IPSR(15, 24, 0) #define FUNC_HTX2_A IPSR(15, 24, 1) #define FUNC_MSIOF1_SYNC_A IPSR(15, 24, 2) #define FUNC_TS_SDEN0_A IPSR(15, 24, 5) #define FUNC_STP_ISEN_0_A IPSR(15, 24, 6) #define FUNC_RIF0_SYNC_A IPSR(15, 24, 7) #define FUNC_RIF2_SYNC_A IPSR(15, 24, 8) #define FUNC_SSI_SDATA4 IPSR(15, 28, 0) #define FUNC_HSCK2_A IPSR(15, 28, 1) #define FUNC_MSIOF1_RXD_A IPSR(15, 28, 2) #define FUNC_TS_SPSYNC0_A IPSR(15, 28, 5) #define FUNC_STP_ISSYNC_0_A IPSR(15, 28, 6) #define FUNC_RIF0_D0_A IPSR(15, 28, 7) #define FUNC_RIF2_D1_A IPSR(15, 28, 8) #define FUNC_SSI_SCK6 IPSR(16, 0, 0) #define FUNC_SIM0_RST_D IPSR(16, 0, 3) #define FUNC_SSI_WS6 IPSR(16, 4, 0) #define FUNC_SIM0_D_D IPSR(16, 4, 3) #define FUNC_SSI_SDATA6 IPSR(16, 8, 0) #define FUNC_SIM0_CLK_D IPSR(16, 8, 3) #define FUNC_SSI_SCK78 IPSR(16, 12, 0) #define FUNC_HRX2_B IPSR(16, 12, 1) #define FUNC_MSIOF1_SCK_C IPSR(16, 12, 2) #define FUNC_TS_SCK1_A IPSR(16, 12, 5) #define FUNC_STP_ISCLK_1_A IPSR(16, 12, 6) #define FUNC_RIF1_CLK_A IPSR(16, 12, 7) #define FUNC_RIF3_CLK_A IPSR(16, 12, 8) #define FUNC_SSI_WS78 IPSR(16, 16, 0) #define FUNC_HTX2_B IPSR(16, 16, 1) #define FUNC_MSIOF1_SYNC_C IPSR(16, 16, 2) #define FUNC_TS_SDAT1_A IPSR(16, 16, 5) #define FUNC_STP_ISD_1_A IPSR(16, 16, 6) #define FUNC_RIF1_SYNC_A IPSR(16, 16, 7) #define FUNC_RIF3_SYNC_A IPSR(16, 16, 8) #define FUNC_SSI_SDATA7 IPSR(16, 20, 0) #define FUNC_HCTS2_N_B IPSR(16, 20, 1) #define FUNC_MSIOF1_RXD_C IPSR(16, 20, 2) #define FUNC_TS_SDEN1_A IPSR(16, 20, 5) #define FUNC_STP_ISEN_1_A IPSR(16, 20, 6) #define FUNC_RIF1_D0_A IPSR(16, 20, 7) #define FUNC_RIF3_D0_A IPSR(16, 20, 8) #define FUNC_TCLK2_A IPSR(16, 20, 0xA) #define FUNC_SSI_SDATA8 IPSR(16, 24, 0) #define FUNC_HRTS2_N_B IPSR(16, 24, 1) #define FUNC_MSIOF1_TXD_C IPSR(16, 24, 2) #define FUNC_TS_SPSYNC1_A IPSR(16, 24, 5) #define FUNC_STP_ISSYNC_1_A IPSR(16, 24, 6) #define FUNC_RIF1_D1_A IPSR(16, 24, 7) #define FUNC_RIF3_D1_A IPSR(16, 24, 8) #define FUNC_SSI_SDATA9_A IPSR(16, 28, 0) #define FUNC_HSCK2_B IPSR(16, 28, 1) #define FUNC_MSIOF1_SS1_C IPSR(16, 28, 2) #define FUNC_HSCK1_A IPSR(16, 28, 3) #define FUNC_SSI_WS1_B IPSR(16, 28, 4) #define FUNC_SCK1 IPSR(16, 28, 5) #define FUNC_STP_IVCXO27_1_A IPSR(16, 28, 6) #define FUNC_SCK5_A IPSR(16, 28, 7) #define FUNC_AUDIO_CLKA_A IPSR(17, 0, 0) #define FUNC_AUDIO_CLKB_B IPSR(17, 4, 0) #define FUNC_SCIF_CLK_A IPSR(17, 4, 1) #define FUNC_STP_IVCXO27_1_D IPSR(17, 4, 6) #define FUNC_REMOCON_A IPSR(17, 4, 7) #define FUNC_TCLK1_A IPSR(17, 4, 0xA) #define FUNC_USB0_PWEN IPSR(17, 8, 0) #define FUNC_SIM0_RST_C IPSR(17, 8, 3) #define FUNC_TS_SCK1_D IPSR(17, 8, 5) #define FUNC_STP_ISCLK_1_D IPSR(17, 8, 6) #define FUNC_BPFCLK_B IPSR(17, 8, 7) #define FUNC_RIF3_CLK_B IPSR(17, 8, 8) #define FUNC_HSCK2_C IPSR(17, 8, 0xD) #define FUNC_USB0_OVC IPSR(17, 12, 0) #define FUNC_SIM0_D_C IPSR(17, 12, 3) #define FUNC_TS_SDAT1_D IPSR(17, 12, 5) #define FUNC_STP_ISD_1_D IPSR(17, 12, 6) #define FUNC_RIF3_SYNC_B IPSR(17, 12, 8) #define FUNC_HRX2_C IPSR(17, 12, 0xD) #define FUNC_USB1_PWEN IPSR(17, 16, 0) #define FUNC_SIM0_CLK_C IPSR(17, 16, 3) #define FUNC_SSI_SCK1_A IPSR(17, 16, 4) #define FUNC_TS_SCK0_E IPSR(17, 16, 5) #define FUNC_STP_ISCLK_0_E IPSR(17, 16, 6) #define FUNC_FMCLK_B IPSR(17, 16, 7) #define FUNC_RIF2_CLK_B IPSR(17, 16, 8) #define FUNC_SPEEDIN_A IPSR(17, 16, 0xA) #define FUNC_HTX2_C IPSR(17, 16, 0xD) #define FUNC_USB1_OVC IPSR(17, 20, 0) #define FUNC_MSIOF1_SS2_C IPSR(17, 20, 2) #define FUNC_SSI_WS1_A IPSR(17, 20, 4) #define FUNC_TS_SDAT0_E IPSR(17, 20, 5) #define FUNC_STP_ISD_0_E IPSR(17, 20, 6) #define FUNC_FMIN_B IPSR(17, 20, 7) #define FUNC_RIF2_SYNC_B IPSR(17, 20, 8) #define FUNC_REMOCON_B IPSR(17, 20, 0xA) #define FUNC_HCTS2_N_C IPSR(17, 20, 0xD) #define FUNC_USB30_PWEN IPSR(17, 24, 0) #define FUNC_AUDIO_CLKOUT_B IPSR(17, 24, 3) #define FUNC_SSI_SCK2_B IPSR(17, 24, 4) #define FUNC_TS_SDEN1_D IPSR(17, 24, 5) #define FUNC_STP_ISEN_1_D IPSR(17, 24, 6) #define FUNC_STP_OPWM_0_E IPSR(17, 24, 7) #define FUNC_RIF3_D0_B IPSR(17, 24, 8) #define FUNC_TCLK2_B IPSR(17, 24, 0xA) #define FUNC_TPU0TO0 IPSR(17, 24, 0xB) #define FUNC_BPFCLK_C IPSR(17, 24, 0xC) #define FUNC_HRTS2_N_C IPSR(17, 24, 0xD) #define FUNC_USB30_OVC IPSR(17, 28, 0) #define FUNC_AUDIO_CLKOUT1_B IPSR(17, 28, 3) #define FUNC_SSI_WS2_B IPSR(17, 28, 4) #define FUNC_TS_SPSYNC1_D IPSR(17, 28, 5) #define FUNC_STP_ISSYNC_1_D IPSR(17, 28, 6) #define FUNC_STP_IVCXO27_0_E IPSR(17, 28, 7) #define FUNC_RIF3_D1_B IPSR(17, 28, 8) #define FUNC_FSO_TOE_N IPSR(17, 28, 0xA) #define FUNC_TPU0TO1 IPSR(17, 28, 0xB) #define FUNC_GP6_30 IPSR(18, 0, 0) #define FUNC_AUDIO_CLKOUT2_B IPSR(18, 0, 3) #define FUNC_SSI_SCK9_B IPSR(18, 0, 4) #define FUNC_TS_SDEN0_E IPSR(18, 0, 5) #define FUNC_STP_ISEN_0_E IPSR(18, 0, 6) #define FUNC_RIF2_D0_B IPSR(18, 0, 8) #define FUNC_TPU0TO2 IPSR(18, 0, 0xB) #define FUNC_FMCLK_C IPSR(18, 0, 0xC) #define FUNC_FMCLK_D IPSR(18, 0, 0xD) #define FUNC_GP6_31 IPSR(18, 4, 0) #define FUNC_AUDIO_CLKOUT3_B IPSR(18, 4, 3) #define FUNC_SSI_WS9_B IPSR(18, 4, 4) #define FUNC_TS_SPSYNC0_E IPSR(18, 4, 5) #define FUNC_STP_ISSYNC_0_E IPSR(18, 4, 6) #define FUNC_RIF2_D1_B IPSR(18, 4, 8) #define FUNC_TPU0TO3 IPSR(18, 4, 0xB) #define FUNC_FMIN_C IPSR(18, 4, 0xC) #define FUNC_FMIN_D IPSR(18, 4, 0xD) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
16,872
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ /* Supported CPU clock Sources */ #define ESP32_CPU_CLK_SRC_XTAL 0U #define ESP32_CPU_CLK_SRC_PLL 1U #define ESP32_CLK_SRC_RC_FAST 2U /* Supported CPU frequencies */ #define ESP32_CLK_CPU_PLL_40M 40000000 #define ESP32_CLK_CPU_PLL_60M 60000000 #define ESP32_CLK_CPU_PLL_80M 80000000 #define ESP32_CLK_CPU_PLL_120M 120000000 #define ESP32_CLK_CPU_RC_FAST_FREQ 8750000 /* Supported XTAL frequencies */ #define ESP32_CLK_XTAL_26M 26000000 #define ESP32_CLK_XTAL_32M 32000000 #define ESP32_CLK_XTAL_40M 40000000 /* Supported RTC fast clock sources */ #define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 0 #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 /* Supported RTC slow clock sources */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 #define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW 1 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 /* RTC slow clock frequencies */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000 #define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW_FREQ 32768 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 68359 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. * These IDs shouldn't be changed unless there is a Hardware change * from Espressif. * * Basic Modules * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG */ #define ESP32_LEDC_MODULE 0 #define ESP32_UART0_MODULE 1 #define ESP32_UART1_MODULE 2 #define ESP32_I2C0_MODULE 3 #define ESP32_TIMG0_MODULE 4 #define ESP32_TIMG1_MODULE 5 /* No timg1 on esp32c2, TODO: IDF-3825 */ #define ESP32_UHCI0_MODULE 6 #define ESP32_SPI_MODULE 7 /* SPI1 */ #define ESP32_SPI2_MODULE 8 /* SPI2 */ #define ESP32_RNG_MODULE 9 #define ESP32_WIFI_MODULE 10 #define ESP32_BT_MODULE 11 #define ESP32_WIFI_BT_COMMON_MODULE 12 #define ESP32_BT_BASEBAND_MODULE 13 #define ESP32_BT_LC_MODULE 14 #define ESP32_AES_MODULE 15 #define ESP32_SHA_MODULE 16 #define ESP32_ECC_MODULE 17 #define ESP32_GDMA_MODULE 18 #define ESP32_SYSTIMER_MODULE 19 #define ESP32_SARADC_MODULE 20 #define ESP32_TEMPSENSOR_MODULE 21 #define ESP32_MODEM_RPA_MODULE 22 #define ESP32_MODULE_MAX 23 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/esp32c2_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
712
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_ /* NXP Kinetis Peripheral Clock Controller IP sources */ #define KINETIS_PCC_SRC_NONE_OR_EXT 0 /* Clock off or external clock is used */ #define KINETIS_PCC_SRC_SOSC_ASYNC 1 /* System Oscillator async clock */ #define KINETIS_PCC_SRC_SIRC_ASYNC 2 /* Slow IRC async clock */ #define KINETIS_PCC_SRC_FIRC_ASYNC 3 /* Fast IRC async clock */ #define KINETIS_PCC_SRC_SPLL_ASYNC 6 /* System PLL async clock */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/kinetis_pcc.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
167
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H_ #define CPG_CORE 0 /* Core Clock */ #define CPG_MOD 1 /* Module Clock */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/renesas_cpg_mssr.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
90
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ #define RA_PLL_SOURCE_HOCO 0 #define RA_PLL_SOURCE_MOCO 1 #define RA_PLL_SOURCE_LOCO 2 #define RA_PLL_SOURCE_MAIN_OSC 3 #define RA_PLL_SOURCE_SUBCLOCK 4 #define RA_PLL_SOURCE_DISABLE 0xff #define RA_CLOCK_SOURCE_HOCO 0 #define RA_CLOCK_SOURCE_MOCO 1 #define RA_CLOCK_SOURCE_LOCO 2 #define RA_CLOCK_SOURCE_MAIN_OSC 3 #define RA_CLOCK_SOURCE_SUBCLOCK 4 #define RA_CLOCK_SOURCE_PLL 5 #define RA_CLOCK_SOURCE_PLL1P RA_CLOCK_SOURCE_PLL #define RA_CLOCK_SOURCE_PLL2 6 #define RA_CLOCK_SOURCE_PLL2P RA_CLOCK_SOURCE_PLL2 #define RA_CLOCK_SOURCE_PLL1Q 7 #define RA_CLOCK_SOURCE_PLL1R 8 #define RA_CLOCK_SOURCE_PLL2Q 9 #define RA_CLOCK_SOURCE_PLL2R 10 #define RA_CLOCK_SOURCE_DISABLE 0xff #define RA_SYS_CLOCK_DIV_1 0 #define RA_SYS_CLOCK_DIV_2 1 #define RA_SYS_CLOCK_DIV_4 2 #define RA_SYS_CLOCK_DIV_8 3 #define RA_SYS_CLOCK_DIV_16 4 #define RA_SYS_CLOCK_DIV_32 5 #define RA_SYS_CLOCK_DIV_64 6 #define RA_SYS_CLOCK_DIV_128 7 /* available for CLKOUT only */ #define RA_SYS_CLOCK_DIV_3 8 #define RA_SYS_CLOCK_DIV_6 9 #define RA_SYS_CLOCK_DIV_12 10 /* PLL divider options. */ #define RA_PLL_DIV_1 0 #define RA_PLL_DIV_2 1 #define RA_PLL_DIV_3 2 #define RA_PLL_DIV_4 3 #define RA_PLL_DIV_5 4 #define RA_PLL_DIV_6 5 #define RA_PLL_DIV_8 7 #define RA_PLL_DIV_9 8 #define RA_PLL_DIV_16 15 /* USB clock divider options. */ #define RA_USB_CLOCK_DIV_1 0 #define RA_USB_CLOCK_DIV_2 1 #define RA_USB_CLOCK_DIV_3 2 #define RA_USB_CLOCK_DIV_4 3 #define RA_USB_CLOCK_DIV_5 4 #define RA_USB_CLOCK_DIV_6 5 #define RA_USB_CLOCK_DIV_8 7 /* USB60 clock divider options. */ #define RA_USB60_CLOCK_DIV_1 0 #define RA_USB60_CLOCK_DIV_2 1 #define RA_USB60_CLOCK_DIV_3 5 #define RA_USB60_CLOCK_DIV_4 2 #define RA_USB60_CLOCK_DIV_5 6 #define RA_USB60_CLOCK_DIV_6 3 #define RA_USB60_CLOCK_DIV_8 4 /* OCTA clock divider options. */ #define RA_OCTA_CLOCK_DIV_1 0 #define RA_OCTA_CLOCK_DIV_2 1 #define RA_OCTA_CLOCK_DIV_4 2 #define RA_OCTA_CLOCK_DIV_6 3 #define RA_OCTA_CLOCK_DIV_8 4 /* CANFD clock divider options. */ #define RA_CANFD_CLOCK_DIV_1 0 #define RA_CANFD_CLOCK_DIV_2 1 #define RA_CANFD_CLOCK_DIV_3 5 #define RA_CANFD_CLOCK_DIV_4 2 #define RA_CANFD_CLOCK_DIV_5 6 #define RA_CANFD_CLOCK_DIV_6 3 #define RA_CANFD_CLOCK_DIV_8 4 /* SCI clock divider options. */ #define RA_SCI_CLOCK_DIV_1 0 #define RA_SCI_CLOCK_DIV_2 1 #define RA_SCI_CLOCK_DIV_3 5 #define RA_SCI_CLOCK_DIV_4 2 #define RA_SCI_CLOCK_DIV_5 6 #define RA_SCI_CLOCK_DIV_6 3 #define RA_SCI_CLOCK_DIV_8 4 /* SPI clock divider options. */ #define RA_SPI_CLOCK_DIV_1 0 #define RA_SPI_CLOCK_DIV_2 1 #define RA_SPI_CLOCK_DIV_3 5 #define RA_SPI_CLOCK_DIV_4 2 #define RA_SPI_CLOCK_DIV_5 6 #define RA_SPI_CLOCK_DIV_6 3 #define RA_SPI_CLOCK_DIV_8 4 /* CEC clock divider options. */ #define RA_CEC_CLOCK_DIV_1 0 #define RA_CEC_CLOCK_DIV_2 1 /* I3C clock divider options. */ #define RA_I3C_CLOCK_DIV_1 0 #define RA_I3C_CLOCK_DIV_2 1 #define RA_I3C_CLOCK_DIV_3 5 #define RA_I3C_CLOCK_DIV_4 2 #define RA_I3C_CLOCK_DIV_5 6 #define RA_I3C_CLOCK_DIV_6 3 #define RA_I3C_CLOCK_DIV_8 4 /* LCD clock divider options. */ #define RA_LCD_CLOCK_DIV_1 0 #define RA_LCD_CLOCK_DIV_2 1 #define RA_LCD_CLOCK_DIV_3 5 #define RA_LCD_CLOCK_DIV_4 2 #define RA_LCD_CLOCK_DIV_5 6 #define RA_LCD_CLOCK_DIV_6 3 #define RA_LCD_CLOCK_DIV_8 4 /* SDADC clock divider options. */ #define RA_SDADC_CLOCK_DIV_1 0 #define RA_SDADC_CLOCK_DIV_2 1 #define RA_SDADC_CLOCK_DIV_3 2 #define RA_SDADC_CLOCK_DIV_4 3 #define RA_SDADC_CLOCK_DIV_5 4 #define RA_SDADC_CLOCK_DIV_6 5 #define RA_SDADC_CLOCK_DIV_8 6 #define RA_SDADC_CLOCK_DIV_12 7 #define RA_SDADC_CLOCK_DIV_16 8 #define MSTPA 0x40203000 #define MSTPB 0x40203004 #define MSTPC 0x40203008 #define MSTPD 0x4020300C #define MSTPE 0x40203010 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/ra_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,314
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ /* Peripheral: * range: 0 - 0xFF, starting from 0 * * Instance: * range: 0 - 0xFF, starting from 0 */ #define IMX_CCM_PERIPHERAL_MASK 0xFF00UL #define IMX_CCM_INSTANCE_MASK 0xFFUL #define IMX_CCM_CORESYS_CLK 0 #define IMX_CCM_PLATFORM_CLK 0x1UL #define IMX_CCM_BUS_CLK 0x2UL /* LPUART */ #define IMX_CCM_LPUART_CLK 0x300UL #define IMX_CCM_LPUART1_CLK 0x300UL #define IMX_CCM_LPUART0102_CLK 0x300UL #define IMX_CCM_LPUART2_CLK 0x301UL #define IMX_CCM_LPUART0304_CLK 0x301UL #define IMX_CCM_LPUART3_CLK 0x302UL #define IMX_CCM_LPUART0506_CLK 0x302UL #define IMX_CCM_LPUART4_CLK 0x303UL #define IMX_CCM_LPUART0708_CLK 0x303UL #define IMX_CCM_LPUART5_CLK 0x304UL #define IMX_CCM_LPUART0910_CLK 0x304UL #define IMX_CCM_LPUART6_CLK 0x305UL #define IMX_CCM_LPUART1112_CLK 0x305UL #define IMX_CCM_LPUART7_CLK 0x306UL #define IMX_CCM_LPUART8_CLK 0x307UL #define IMX_CCM_LPUART9_CLK 0x308UL #define IMX_CCM_LPUART10_CLK 0x309UL #define IMX_CCM_LPUART11_CLK 0x30aUL #define IMX_CCM_LPUART12_CLK 0x30bUL /* LPI2C */ #define IMX_CCM_LPI2C_CLK 0x400UL #define IMX_CCM_LPI2C1_CLK 0x400UL #define IMX_CCM_LPI2C2_CLK 0x401UL #define IMX_CCM_LPI2C3_CLK 0x402UL #define IMX_CCM_LPI2C4_CLK 0x403UL #define IMX_CCM_LPI2C5_CLK 0x404UL #define IMX_CCM_LPI2C6_CLK 0x405UL #define IMX_CCM_LPI2C7_CLK 0x406UL #define IMX_CCM_LPI2C8_CLK 0x407UL /* LPSPI */ #define IMX_CCM_LPSPI_CLK 0x500UL #define IMX_CCM_LPSPI1_CLK 0x500UL #define IMX_CCM_LPSPI2_CLK 0x501UL #define IMX_CCM_LPSPI3_CLK 0x502UL #define IMX_CCM_LPSPI4_CLK 0x503UL #define IMX_CCM_LPSPI5_CLK 0x504UL #define IMX_CCM_LPSPI6_CLK 0x505UL #define IMX_CCM_LPSPI7_CLK 0x506UL #define IMX_CCM_LPSPI8_CLK 0x507UL /* USDHC */ #define IMX_CCM_USDHC1_CLK 0x600UL #define IMX_CCM_USDHC2_CLK 0x601UL /* DMA */ #define IMX_CCM_EDMA_CLK 0x700UL #define IMX_CCM_EDMA_LPSR_CLK 0x701UL /* PWM */ #define IMX_CCM_PWM_CLK 0x800UL /* CAN */ #define IMX_CCM_CAN_CLK 0x900UL #define IMX_CCM_CAN1_CLK 0x900UL #define IMX_CCM_CAN2_CLK 0x901UL #define IMX_CCM_CAN3_CLK 0x902UL /* GPT */ #define IMX_CCM_GPT_CLK 0x1000UL #define IMX_CCM_GPT1_CLK 0x1000UL #define IMX_CCM_GPT2_CLK 0x1001UL #define IMX_CCM_GPT3_CLK 0x1002UL #define IMX_CCM_GPT4_CLK 0x1003UL #define IMX_CCM_GPT5_CLK 0x1004UL #define IMX_CCM_GPT6_CLK 0x1005UL /* SAI */ #define IMX_CCM_SAI1_CLK 0x1100UL #define IMX_CCM_SAI2_CLK 0x1101UL #define IMX_CCM_SAI3_CLK 0x1102UL #define IMX_CCM_SAI4_CLK 0x1103UL /* ENET */ #define IMX_CCM_ENET_CLK 0x1200UL #define IMX_CCM_ENET_PLL 0x1201UL #define IMX_CCM_ENET1G_CLK 0x1202UL #define IMX_CCM_ENET1G_PLL 0x1203UL /* FLEXSPI */ #define IMX_CCM_FLEXSPI_CLK 0x1300UL #define IMX_CCM_FLEXSPI2_CLK 0x1301UL /* PIT */ #define IMX_CCM_PIT_CLK 0x1400UL #define IMX_CCM_PIT1_CLK 0x1401UL /* ADC */ #define IMX_CCM_LPADC1_CLK 0x1500UL #define IMX_CCM_LPADC2_CLK 0x1501UL /* TPM */ #define IMX_CCM_TPM_CLK 0x1600UL #define IMX_CCM_TPM1_CLK 0x1600UL #define IMX_CCM_TPM2_CLK 0x1601UL #define IMX_CCM_TPM3_CLK 0x1602UL #define IMX_CCM_TPM4_CLK 0x1603UL #define IMX_CCM_TPM5_CLK 0x1604UL #define IMX_CCM_TPM6_CLK 0x1605UL /* QTMR */ #define IMX_CCM_QTMR_CLK 0x6000UL #define IMX_CCM_QTMR1_CLK 0x6000UL #define IMX_CCM_QTMR2_CLK 0x6001UL #define IMX_CCM_QTMR3_CLK 0x6002UL #define IMX_CCM_QTMR4_CLK 0x6003UL #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,575
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_ /* Supported CPU clock Sources */ #define ESP32_CPU_CLK_SRC_XTAL 0U #define ESP32_CPU_CLK_SRC_PLL 1U #define ESP32_CLK_SRC_RC_FAST 2U /* Supported PLL CPU frequencies */ #define ESP32_CLK_CPU_PLL_80M 80000000 #define ESP32_CLK_CPU_PLL_160M 160000000 #define ESP32_CLK_CPU_PLL_240M 240000000 #define ESP32_CLK_CPU_RC_FAST_FREQ 17500000 /* Supported XTAL frequencies */ #define ESP32_CLK_XTAL_32M 32000000 #define ESP32_CLK_XTAL_40M 40000000 /* Supported RTC fast clock sources */ #define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 0 #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 /* Supported RTC slow clock sources */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 #define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 /* RTC slow clock frequencies */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 68359 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. * These IDs shouldn't be changed unless there is a Hardware change * from Espressif. * * Basic Modules * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG */ #define ESP32_LEDC_MODULE 0 #define ESP32_UART0_MODULE 1 #define ESP32_UART1_MODULE 2 #define ESP32_UART2_MODULE 3 #define ESP32_USB_MODULE 4 #define ESP32_I2C0_MODULE 5 #define ESP32_I2C1_MODULE 6 #define ESP32_I2S0_MODULE 7 #define ESP32_I2S1_MODULE 8 #define ESP32_LCD_CAM_MODULE 9 #define ESP32_TIMG0_MODULE 10 #define ESP32_TIMG1_MODULE 11 #define ESP32_PWM0_MODULE 12 #define ESP32_PWM1_MODULE 13 #define ESP32_PWM2_MODULE 14 #define ESP32_PWM3_MODULE 15 #define ESP32_UHCI0_MODULE 16 #define ESP32_UHCI1_MODULE 17 #define ESP32_RMT_MODULE 18 #define ESP32_PCNT_MODULE 19 #define ESP32_SPI_MODULE 20 #define ESP32_SPI2_MODULE 21 #define ESP32_SPI3_MODULE 22 #define ESP32_SDMMC_MODULE 23 #define ESP32_TWAI_MODULE 24 #define ESP32_RNG_MODULE 25 #define ESP32_WIFI_MODULE 26 #define ESP32_BT_MODULE 27 #define ESP32_WIFI_BT_COMMON_MODULE 28 #define ESP32_BT_BASEBAND_MODULE 29 #define ESP32_BT_LC_MODULE 30 #define ESP32_AES_MODULE 31 #define ESP32_SHA_MODULE 32 #define ESP32_HMAC_MODULE 33 #define ESP32_DS_MODULE 34 #define ESP32_RSA_MODULE 35 #define ESP32_SYSTIMER_MODULE 36 #define ESP32_GDMA_MODULE 37 #define ESP32_DEDIC_GPIO_MODULE 38 #define ESP32_SARADC_MODULE 39 #define ESP32_MODULE_MAX 40 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/esp32s3_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
847
```objective-c /* * * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_INTEL_SOCFPGA_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_INTEL_SOCFPGA_CLOCK_H_ #define INTEL_SOCFPGA_CLOCK_MPU 0 #define INTEL_SOCFPGA_CLOCK_WDT 1 #define INTEL_SOCFPGA_CLOCK_UART 2 #define INTEL_SOCFPGA_CLOCK_MMC 3 #define INTEL_SOCFPGA_CLOCK_TIMER 4 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_INTEL_SOCFPGA_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/intel_socfpga_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
124
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_ /* SCG system oscillator mode */ #define KINETIS_SCG_SOSC_MODE_EXT 0U #define KINETIS_SCG_SOSC_MODE_LOW_POWER 4U #define KINETIS_SCG_SOSC_MODE_HIGH_GAIN 12U /* SCG clock controller clock names */ #define KINETIS_SCG_CORESYS_CLK 0U #define KINETIS_SCG_BUS_CLK 1U #define KINETIS_SCG_FLEXBUS_CLK 2U #define KINETIS_SCG_FLASH_CLK 3U #define KINETIS_SCG_SOSC_CLK 4U #define KINETIS_SCG_SIRC_CLK 5U #define KINETIS_SCG_FIRC_CLK 6U #define KINETIS_SCG_SPLL_CLK 7U #define KINETIS_SCG_SOSC_ASYNC_DIV1_CLK 8U #define KINETIS_SCG_SOSC_ASYNC_DIV2_CLK 9U #define KINETIS_SCG_SIRC_ASYNC_DIV1_CLK 10U #define KINETIS_SCG_SIRC_ASYNC_DIV2_CLK 11U #define KINETIS_SCG_FIRC_ASYNC_DIV1_CLK 12U #define KINETIS_SCG_FIRC_ASYNC_DIV2_CLK 13U #define KINETIS_SCG_SPLL_ASYNC_DIV1_CLK 14U #define KINETIS_SCG_SPLL_ASYNC_DIV2_CLK 15U #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/kinetis_scg.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
359
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ #include "stm32_common_clocks.h" /** Domain clocks */ /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x030 #define STM32_CLOCK_BUS_AHB2 0x034 #define STM32_CLOCK_BUS_AHB3 0x038 #define STM32_CLOCK_BUS_APB1 0x040 #define STM32_CLOCK_BUS_APB2 0x044 #define STM32_CLOCK_BUS_APB3 0x0A8 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 /** Domain clocks */ /* RM0386, 0390, 0402, 0430 Dedicated Clock configuration register (RCC_DCKCFGRx) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) /** PLL clock outputs */ #define STM32_SRC_PLL_P (STM32_SRC_HSI + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) /** Peripheral bus clock */ #define STM32_SRC_PCLK (STM32_SRC_PLL_R + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CFGRx register offset * @param shift Position within RCC_CFGRx. * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CFGRx register offset */ #define CFGR_REG 0x08 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x70 /** @brief Device domain clocks selection helpers */ /** CFGR devices */ #define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) /** @brief RCC_DKCFGR register offset */ #define DCKCFGR1_REG 0x8C #define DCKCFGR2_REG 0x90 /** @brief Dedicated clocks configuration register selection helpers */ /** DKCFGR2 devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, DCKCFGR2_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, DCKCFGR2_REG) #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, DCKCFGR2_REG) #define USART4_SEL(val) STM32_CLOCK(val, 3, 6, DCKCFGR2_REG) #define USART5_SEL(val) STM32_CLOCK(val, 3, 8, DCKCFGR2_REG) #define USART6_SEL(val) STM32_CLOCK(val, 3, 10, DCKCFGR2_REG) #define USART7_SEL(val) STM32_CLOCK(val, 3, 12, DCKCFGR2_REG) #define USART8_SEL(val) STM32_CLOCK(val, 3, 14, DCKCFGR2_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 16, DCKCFGR2_REG) #define I2C2_SEL(val) STM32_CLOCK(val, 3, 18, DCKCFGR2_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR2_REG) #define I2C4_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 24, DCKCFGR2_REG) #define CEC_SEL(val) STM32_CLOCK(val, 1, 26, DCKCFGR2_REG) #define CK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR2_REG) #define SDMMC1_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR2_REG) #define SDMMC2_SEL(val) STM32_CLOCK(val, 1, 29, DCKCFGR2_REG) #define DSI_SEL(val) STM32_CLOCK(val, 1, 30, DCKCFGR2_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f7_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,333
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x048 #define STM32_CLOCK_BUS_AHB2 0x04c #define STM32_CLOCK_BUS_AHB3 0x050 #define STM32_CLOCK_BUS_APB1 0x058 #define STM32_CLOCK_BUS_APB1_2 0x05c #define STM32_CLOCK_BUS_APB2 0x060 #define STM32_CLOCK_BUS_APB3 0x064 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 /** Domain clocks */ /* RM0461, 6.4.29 Clock configuration register (RCC_CFGR3) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) #define STM32_SRC_MSI (STM32_SRC_HSI + 1) /* #define STM32_SRC_HSI48 TBD */ /** Bus clock */ #define STM32_SRC_PCLK (STM32_SRC_MSI + 1) /** PLL clock outputs */ #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPR register offset */ #define CCIPR_REG 0x88 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x90 /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) #define SPI2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) #define LPTIM3_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG) #define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG) #define RNG_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32wl_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,102
```objective-c /* * */ #ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_ #define _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_ /* IMPORTANT: the indexes used by these macros need to * match the indexes in the PCC driver LUT at which the * corresponding clock ID encoding can be found. */ /* clocks managed by PCC4 */ #define IMX8ULP_CLOCK_LPUART7 0 #endif /* _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/imx8ulp_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
122
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ATMEL_SAM_PMC_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ATMEL_SAM_PMC_H_ #define PMC_TYPE_CORE 0 #define PMC_TYPE_SYSTEM 1 #define PMC_TYPE_PERIPHERAL 2 #define PMC_TYPE_GCK 3 #define PMC_TYPE_PROGRAMMABLE 4 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ATMEL_SAM_PMC_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/atmel_sam_pmc.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
106
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_ #define KINETIS_MCG_FIXED_FREQ_CLK 0 #define KINETIS_MCG_OUT_CLK 1 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/kinetis_mcg.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
81
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_LPC11U6X_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_LPC11U6X_CLOCK_H_ #define LPC11U6X_CLOCK_I2C0 0 #define LPC11U6X_CLOCK_I2C1 1 #define LPC11U6X_CLOCK_GPIO 2 #define LPC11U6X_CLOCK_USART0 3 #define LPC11U6X_CLOCK_USART1 4 #define LPC11U6X_CLOCK_USART2 5 #define LPC11U6X_CLOCK_USART3 6 #define LPC11U6X_CLOCK_USART4 7 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_LPC11U6X_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/lpc11u6x_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
170
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AST10X0_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AST10X0_H_ #define ASPEED_CLK_GRP_0_OFFSET (0) #define ASPEED_CLK_GRP_1_OFFSET (32) #define ASPEED_CLK_GRP_2_OFFSET (64) #define ASPEED_CLK_MCLK (ASPEED_CLK_GRP_0_OFFSET + 0) #define ASPEED_CLK_USB_DEVICE (ASPEED_CLK_GRP_0_OFFSET + 7) #define ASPEED_CLK_YCLK (ASPEED_CLK_GRP_0_OFFSET + 13) #define ASPEED_CLK_LCLK (ASPEED_CLK_GRP_1_OFFSET + 0) #define ASPEED_CLK_ESPI (ASPEED_CLK_GRP_1_OFFSET + 1) #define ASPEED_CLK_REFCLK (ASPEED_CLK_GRP_1_OFFSET + 2) #define ASPEED_CLK_LHCCLK (ASPEED_CLK_GRP_1_OFFSET + 5) #define ASPEED_CLK_RSACLK (ASPEED_CLK_GRP_1_OFFSET + 6) #define ASPEED_CLK_I3C0 (ASPEED_CLK_GRP_1_OFFSET + 8) #define ASPEED_CLK_I3C1 (ASPEED_CLK_GRP_1_OFFSET + 9) #define ASPEED_CLK_I3C2 (ASPEED_CLK_GRP_1_OFFSET + 10) #define ASPEED_CLK_I3C3 (ASPEED_CLK_GRP_1_OFFSET + 11) #define ASPEED_CLK_UART1 (ASPEED_CLK_GRP_1_OFFSET + 16) #define ASPEED_CLK_UART2 (ASPEED_CLK_GRP_1_OFFSET + 17) #define ASPEED_CLK_UART3 (ASPEED_CLK_GRP_1_OFFSET + 18) #define ASPEED_CLK_UART4 (ASPEED_CLK_GRP_1_OFFSET + 19) #define ASPEED_CLK_MAC (ASPEED_CLK_GRP_1_OFFSET + 20) #define ASPEED_CLK_UART6 (ASPEED_CLK_GRP_1_OFFSET + 22) #define ASPEED_CLK_UART7 (ASPEED_CLK_GRP_1_OFFSET + 23) #define ASPEED_CLK_UART8 (ASPEED_CLK_GRP_1_OFFSET + 24) #define ASPEED_CLK_UART9 (ASPEED_CLK_GRP_1_OFFSET + 25) #define ASPEED_CLK_UART10 (ASPEED_CLK_GRP_1_OFFSET + 26) #define ASPEED_CLK_UART11 (ASPEED_CLK_GRP_1_OFFSET + 27) #define ASPEED_CLK_UART12 (ASPEED_CLK_GRP_1_OFFSET + 28) #define ASPEED_CLK_UART13 (ASPEED_CLK_GRP_1_OFFSET + 29) #define ASPEED_CLK_PCLK (ASPEED_CLK_GRP_2_OFFSET + 0) #define ASPEED_CLK_HCLK (ASPEED_CLK_GRP_2_OFFSET + 1) #define ASPEED_CLK_UART5 (ASPEED_CLK_GRP_2_OFFSET + 2) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AST10X0_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/ast10x0_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
662
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ #include "stm32_common_clocks.h" /** Domain clocks */ /* RM0477 */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSE (STM32_SRC_LSI + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSE + 1) #define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */ #define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1) /* CSI + CSIKERON */ /** PLL outputs */ #define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1) #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) #define STM32_SRC_PLL1_S (STM32_SRC_PLL1_R + 1) #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_S + 1) #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) #define STM32_SRC_PLL2_S (STM32_SRC_PLL2_R + 1) #define STM32_SRC_PLL2_T (STM32_SRC_PLL2_S + 1) #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_T + 1) #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) #define STM32_SRC_PLL3_S (STM32_SRC_PLL3_R + 1) /** Clock muxes */ #define STM32_SRC_CKPER (STM32_SRC_PLL3_S + 1) /** Others: Not yet supported */ /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x138 #define STM32_CLOCK_BUS_AHB2 0x13C #define STM32_CLOCK_BUS_AHB3 0x158 #define STM32_CLOCK_BUS_AHB4 0x140 #define STM32_CLOCK_BUS_AHB5 0x134 #define STM32_CLOCK_BUS_APB1 0x148 #define STM32_CLOCK_BUS_APB1_2 0x14C #define STM32_CLOCK_BUS_APB2 0x150 #define STM32_CLOCK_BUS_APB4 0x154 #define STM32_CLOCK_BUS_APB5 0x144 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB5 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_AHB3 #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32H7RS clock configuration bit field. * * - reg (0/1) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..3) [ 16 : 18 ] * * @param reg RCC_DxCCIP register offset * @param shift Position within RCC_DxCCIP. * @param mask Mask for the RCC_DxCCIP field. * @param val Clock value (0, 1, 2 or 3). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_DxCCIP register offset (RM0477.pdf) */ #define D1CCIPR_REG 0x4C #define D2CCIPR_REG 0x50 #define D3CCIPR_REG 0x54 #define D4CCIPR_REG 0x58 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x70 /** @brief Device domain clocks selection helpers (RM0477.pdf) */ /* TODO to be completed */ /** D1CCIPR devices */ #define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG) #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 2, D1CCIPR_REG) #define XSPI1_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG) #define XSPI2_SEL(val) STM32_CLOCK(val, 3, 6, D1CCIPR_REG) #define ADC_SEL(val) STM32_CLOCK(val, 3, 24, D1CCIPR_REG) #define CKPER_SEL(val) STM32_CLOCK(val, 3, 28, D1CCIPR_REG) /** D2CCIPR devices */ #define USART234578_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIPR_REG) #define SPI23_SEL(val) STM32_CLOCK(val, 7, 4, D2CCIPR_REG) #define I2C23_SEL(val) STM32_CLOCK(val, 3, 8, D2CCIPR_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, D2CCIPR_REG) #define I3C1_SEL(val) STM32_CLOCK(val, 3, 12, D2CCIPR_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 7, 16, D2CCIPR_REG) #define FDCAN_SEL(val) STM32_CLOCK(val, 3, 22, D2CCIPR_REG) /** D3CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 7, 0, D3CCIPR_REG) #define SPI45_SEL(val) STM32_CLOCK(val, 7, 4, D3CCIPR_REG) #define SPI1_SEL(val) STM32_CLOCK(val, 7, 8, D3CCIPR_REG) #define SAI1_SEL(val) STM32_CLOCK(val, 7, 16, D3CCIPR_REG) #define SAI2_SEL(val) STM32_CLOCK(val, 7, 20, D3CCIPR_REG) /** D4CCIPR devices */ #define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, D4CCIPR_REG) #define SPI6_SEL(val) STM32_CLOCK(val, 7, 4, D4CCIPR_REG) #define LPTIM23_SEL(val) STM32_CLOCK(val, 7, 8, D4CCIPR_REG) #define LPTIM45_SEL(val) STM32_CLOCK(val, 7, 12, D4CCIPR_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,756
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_ #include "gd32-clocks-common.h" /** * @name Register offsets * @{ */ #define GD32_AHBEN_OFFSET 0x14U #define GD32_APB1EN_OFFSET 0x1CU #define GD32_APB2EN_OFFSET 0x18U #define GD32_ADDAPB1EN_OFFSET 0xE4U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB peripherals */ #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U) #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U) #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U) #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U) #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U) #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U) #define GD32_CLOCK_USBHS GD32_CLOCK_CONFIG(AHBEN, 12U) #define GD32_CLOCK_ULPI GD32_CLOCK_CONFIG(AHBEN, 13U) #define GD32_CLOCK_ENET GD32_CLOCK_CONFIG(AHBEN, 14U) #define GD32_CLOCK_ENETTX GD32_CLOCK_CONFIG(AHBEN, 15U) #define GD32_CLOCK_ENETRX GD32_CLOCK_CONFIG(AHBEN, 16U) #define GD32_CLOCK_TMU GD32_CLOCK_CONFIG(AHBEN, 30U) #define GD32_CLOCK_SQPI GD32_CLOCK_CONFIG(AHBEN, 31U) /* APB1 peripherals */ #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U) #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U) #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U) #define GD32_CLOCK_TIMER4 GD32_CLOCK_CONFIG(APB1EN, 3U) #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) #define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U) #define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U) #define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U) #define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U) #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) #define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U) #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) #define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U) #define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U) #define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U) #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) #define GD32_CLOCK_I2C2 GD32_CLOCK_CONFIG(APB1EN, 24U) #define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U) #define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U) #define GD32_CLOCK_BKPI GD32_CLOCK_CONFIG(APB1EN, 27U) #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) /* APB2 peripherals */ #define GD32_CLOCK_AFIO GD32_CLOCK_CONFIG(APB2EN, 0U) #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(APB2EN, 2U) #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(APB2EN, 3U) #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(APB2EN, 4U) #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(APB2EN, 5U) #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(APB2EN, 6U) #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(APB2EN, 7U) #define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(APB2EN, 8U) #define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U) #define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U) #define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U) #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) #define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 13U) #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) #define GD32_CLOCK_ADC2 GD32_CLOCK_CONFIG(APB2EN, 15U) #define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 19U) #define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 20U) #define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 21U) #define GD32_CLOCK_USART5 GD32_CLOCK_CONFIG(APB2EN, 28U) #define GD32_CLOCK_SHRTIMER GD32_CLOCK_CONFIG(APB2EN, 29U) #define GD32_CLOCK_CMP GD32_CLOCK_CONFIG(APB2EN, 31U) /* APB1 additional peripherals */ #define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U) #define GD32_CLOCK_CAN2 GD32_CLOCK_CONFIG(ADDAPB1EN, 31U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/gd32e50x-clocks.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,389
```objective-c /* * */ #ifndef ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ #define ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ #include <zephyr/dt-bindings/clock/renesas-ra-cgc.h> #endif /* ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
86
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_ #define NXP_S32_FIRC_CLK 1U #define NXP_S32_FXOSC_CLK 2U #define NXP_S32_SIRC_CLK 3U #define NXP_S32_COREPLL_CLK 4U #define NXP_S32_PERIPHPLL_CLK 5U #define NXP_S32_DDRPLL_CLK 6U #define NXP_S32_LFAST0_PLL_CLK 7U #define NXP_S32_LFAST1_PLL_CLK 8U #define NXP_S32_COREPLL_PHI0_CLK 9U #define NXP_S32_COREPLL_DFS0_CLK 10U #define NXP_S32_COREPLL_DFS1_CLK 11U #define NXP_S32_COREPLL_DFS2_CLK 12U #define NXP_S32_COREPLL_DFS3_CLK 13U #define NXP_S32_COREPLL_DFS4_CLK 14U #define NXP_S32_COREPLL_DFS5_CLK 15U #define NXP_S32_PERIPHPLL_PHI0_CLK 16U #define NXP_S32_PERIPHPLL_PHI1_CLK 17U #define NXP_S32_PERIPHPLL_PHI2_CLK 18U #define NXP_S32_PERIPHPLL_PHI3_CLK 19U #define NXP_S32_PERIPHPLL_PHI4_CLK 20U #define NXP_S32_PERIPHPLL_PHI5_CLK 21U #define NXP_S32_PERIPHPLL_PHI6_CLK 22U #define NXP_S32_PERIPHPLL_DFS0_CLK 23U #define NXP_S32_PERIPHPLL_DFS1_CLK 24U #define NXP_S32_PERIPHPLL_DFS2_CLK 25U #define NXP_S32_PERIPHPLL_DFS3_CLK 26U #define NXP_S32_PERIPHPLL_DFS4_CLK 27U #define NXP_S32_PERIPHPLL_DFS5_CLK 28U #define NXP_S32_DDRPLL_PHI0_CLK 29U #define NXP_S32_LFAST0_PLL_PH0_CLK 30U #define NXP_S32_LFAST1_PLL_PH0_CLK 31U #define NXP_S32_ETH_RGMII_REF_CLK 32U #define NXP_S32_TMR_1588_CLK 33U #define NXP_S32_ETH0_EXT_RX_CLK 34U #define NXP_S32_ETH0_EXT_TX_CLK 35U #define NXP_S32_ETH1_EXT_RX_CLK 36U #define NXP_S32_ETH1_EXT_TX_CLK 37U #define NXP_S32_LFAST0_EXT_REF_CLK 38U #define NXP_S32_LFAST1_EXT_REF_CLK 39U #define NXP_S32_DDR_CLK 40U #define NXP_S32_P0_SYS_CLK 41U #define NXP_S32_P1_SYS_CLK 42U #define NXP_S32_P1_SYS_DIV2_CLK 43U #define NXP_S32_P1_SYS_DIV4_CLK 44U #define NXP_S32_P2_SYS_CLK 45U #define NXP_S32_CORE_M33_CLK 46U #define NXP_S32_P2_SYS_DIV2_CLK 47U #define NXP_S32_P2_SYS_DIV4_CLK 48U #define NXP_S32_P3_SYS_CLK 49U #define NXP_S32_CE_SYS_DIV2_CLK 50U #define NXP_S32_CE_SYS_DIV4_CLK 51U #define NXP_S32_P3_SYS_DIV2_NOC_CLK 52U #define NXP_S32_P3_SYS_DIV4_CLK 53U #define NXP_S32_P4_SYS_CLK 54U #define NXP_S32_P4_SYS_DIV2_CLK 55U #define NXP_S32_HSE_SYS_DIV2_CLK 56U #define NXP_S32_P5_SYS_CLK 57U #define NXP_S32_P5_SYS_DIV2_CLK 58U #define NXP_S32_P5_SYS_DIV4_CLK 59U #define NXP_S32_P2_MATH_CLK 60U #define NXP_S32_P2_MATH_DIV3_CLK 61U #define NXP_S32_GLB_LBIST_CLK 62U #define NXP_S32_RTU0_CORE_CLK 63U #define NXP_S32_RTU0_CORE_DIV2_CLK 64U #define NXP_S32_RTU1_CORE_CLK 65U #define NXP_S32_RTU1_CORE_DIV2_CLK 66U #define NXP_S32_P0_PSI5_S_UTIL_CLK 67U #define NXP_S32_P4_PSI5_S_UTIL_CLK 68U #define NXP_S32_ADC0_CLK 70U #define NXP_S32_ADC1_CLK 71U #define NXP_S32_CE_EDMA_CLK 72U #define NXP_S32_CE_PIT0_CLK 73U #define NXP_S32_CE_PIT1_CLK 74U #define NXP_S32_CE_PIT2_CLK 75U #define NXP_S32_CE_PIT3_CLK 76U #define NXP_S32_CE_PIT4_CLK 77U #define NXP_S32_CE_PIT5_CLK 78U #define NXP_S32_CLKOUT0_CLK 79U #define NXP_S32_CLKOUT1_CLK 80U #define NXP_S32_CLKOUT2_CLK 81U #define NXP_S32_CLKOUT3_CLK 82U #define NXP_S32_CLKOUT4_CLK 83U #define NXP_S32_CTU_CLK 84U #define NXP_S32_DMACRC0_CLK 85U #define NXP_S32_DMACRC1_CLK 86U #define NXP_S32_DMACRC4_CLK 87U #define NXP_S32_DMACRC5_CLK 88U #define NXP_S32_DMAMUX0_CLK 89U #define NXP_S32_DMAMUX1_CLK 90U #define NXP_S32_DMAMUX4_CLK 91U #define NXP_S32_DMAMUX5_CLK 92U #define NXP_S32_EDMA0_CLK 93U #define NXP_S32_EDMA1_CLK 94U #define NXP_S32_EDMA3_CLK 95U #define NXP_S32_EDMA4_CLK 96U #define NXP_S32_EDMA5_CLK 97U #define NXP_S32_ETH0_TX_MII_CLK 98U #define NXP_S32_ENET0_CLK 99U #define NXP_S32_P3_CAN_PE_CLK 100U #define NXP_S32_FLEXCAN0_CLK 101U #define NXP_S32_FLEXCAN1_CLK 102U #define NXP_S32_FLEXCAN2_CLK 103U #define NXP_S32_FLEXCAN3_CLK 104U #define NXP_S32_FLEXCAN4_CLK 105U #define NXP_S32_FLEXCAN5_CLK 106U #define NXP_S32_FLEXCAN6_CLK 107U #define NXP_S32_FLEXCAN7_CLK 108U #define NXP_S32_FLEXCAN8_CLK 109U #define NXP_S32_FLEXCAN9_CLK 110U #define NXP_S32_FLEXCAN10_CLK 111U #define NXP_S32_FLEXCAN11_CLK 112U #define NXP_S32_FLEXCAN12_CLK 113U #define NXP_S32_FLEXCAN13_CLK 114U #define NXP_S32_FLEXCAN14_CLK 115U #define NXP_S32_FLEXCAN15_CLK 116U #define NXP_S32_FLEXCAN16_CLK 117U #define NXP_S32_FLEXCAN17_CLK 118U #define NXP_S32_FLEXCAN18_CLK 119U #define NXP_S32_FLEXCAN19_CLK 120U #define NXP_S32_FLEXCAN20_CLK 121U #define NXP_S32_FLEXCAN21_CLK 122U #define NXP_S32_FLEXCAN22_CLK 123U #define NXP_S32_FLEXCAN23_CLK 124U #define NXP_S32_P0_FR_PE_CLK 125U #define NXP_S32_FRAY0_CLK 126U #define NXP_S32_FRAY1_CLK 127U #define NXP_S32_GTM_CLK 128U #define NXP_S32_IIIC0_CLK 129U #define NXP_S32_IIIC1_CLK 130U #define NXP_S32_IIIC2_CLK 131U #define NXP_S32_P0_LIN_BAUD_CLK 132U #define NXP_S32_LIN0_CLK 133U #define NXP_S32_LIN1_CLK 134U #define NXP_S32_LIN2_CLK 135U #define NXP_S32_P1_LIN_BAUD_CLK 136U #define NXP_S32_LIN3_CLK 137U #define NXP_S32_LIN4_CLK 138U #define NXP_S32_LIN5_CLK 139U #define NXP_S32_P4_LIN_BAUD_CLK 140U #define NXP_S32_LIN6_CLK 141U #define NXP_S32_LIN7_CLK 142U #define NXP_S32_LIN8_CLK 143U #define NXP_S32_P5_LIN_BAUD_CLK 144U #define NXP_S32_LIN9_CLK 145U #define NXP_S32_LIN10_CLK 146U #define NXP_S32_LIN11_CLK 147U #define NXP_S32_MSCDSPI_CLK 148U #define NXP_S32_MSCLIN_CLK 149U #define NXP_S32_NANO_CLK 150U #define NXP_S32_P0_CLKOUT_SRC_CLK 151U #define NXP_S32_P0_CTU_PER_CLK 152U #define NXP_S32_P0_DSPI_MSC_CLK 153U #define NXP_S32_P0_EMIOS_LCU_CLK 154U #define NXP_S32_P0_GTM_CLK 155U #define NXP_S32_P0_GTM_NOC_CLK 156U #define NXP_S32_P0_GTM_TS_CLK 157U #define NXP_S32_P0_LIN_CLK 158U #define NXP_S32_P0_NANO_CLK 159U #define NXP_S32_P0_PSI5_125K_CLK 160U #define NXP_S32_P0_PSI5_189K_CLK 161U #define NXP_S32_P0_PSI5_S_BAUD_CLK 162U #define NXP_S32_P0_PSI5_S_CORE_CLK 163U #define NXP_S32_P0_PSI5_S_TRIG0_CLK 164U #define NXP_S32_P0_PSI5_S_TRIG1_CLK 165U #define NXP_S32_P0_PSI5_S_TRIG2_CLK 166U #define NXP_S32_P0_PSI5_S_TRIG3_CLK 167U #define NXP_S32_P0_PSI5_S_UART_CLK 168U #define NXP_S32_P0_PSI5_S_WDOG0_CLK 169U #define NXP_S32_P0_PSI5_S_WDOG1_CLK 170U #define NXP_S32_P0_PSI5_S_WDOG2_CLK 171U #define NXP_S32_P0_PSI5_S_WDOG3_CLK 172U #define NXP_S32_P0_REG_INTF_2X_CLK 173U #define NXP_S32_P0_REG_INTF_CLK 174U #define NXP_S32_P1_CLKOUT_SRC_CLK 175U #define NXP_S32_P1_DSPI60_CLK 176U #define NXP_S32_ETH_TS_CLK 177U #define NXP_S32_ETH_TS_DIV4_CLK 178U #define NXP_S32_ETH0_REF_RMII_CLK 179U #define NXP_S32_ETH0_RX_MII_CLK 180U #define NXP_S32_ETH0_RX_RGMII_CLK 181U #define NXP_S32_ETH0_TX_RGMII_CLK 182U #define NXP_S32_ETH0_PS_TX_CLK 183U #define NXP_S32_ETH1_REF_RMII_CLK 184U #define NXP_S32_ETH1_RX_MII_CLK 185U #define NXP_S32_ETH1_RX_RGMII_CLK 186U #define NXP_S32_ETH1_TX_MII_CLK 187U #define NXP_S32_ETH1_TX_RGMII_CLK 188U #define NXP_S32_ETH1_PS_TX_CLK 189U #define NXP_S32_P1_LFAST0_REF_CLK 190U #define NXP_S32_P1_LFAST1_REF_CLK 191U #define NXP_S32_P1_NETC_AXI_CLK 192U #define NXP_S32_P1_LIN_CLK 193U #define NXP_S32_P1_REG_INTF_CLK 194U #define NXP_S32_P2_DBG_ATB_CLK 195U #define NXP_S32_P2_REG_INTF_CLK 196U #define NXP_S32_P3_AES_CLK 197U #define NXP_S32_P3_CLKOUT_SRC_CLK 198U #define NXP_S32_P3_DBG_TS_CLK 199U #define NXP_S32_P3_REG_INTF_CLK 200U #define NXP_S32_P3_SYS_MON1_CLK 201U #define NXP_S32_P3_SYS_MON2_CLK 202U #define NXP_S32_P3_SYS_MON3_CLK 203U #define NXP_S32_P4_CLKOUT_SRC_CLK 204U #define NXP_S32_P4_DSPI60_CLK 205U #define NXP_S32_P4_EMIOS_LCU_CLK 206U #define NXP_S32_P4_LIN_CLK 207U #define NXP_S32_P4_PSI5_125K_CLK 208U #define NXP_S32_P4_PSI5_189K_CLK 209U #define NXP_S32_P4_PSI5_S_BAUD_CLK 210U #define NXP_S32_P4_PSI5_S_CORE_CLK 211U #define NXP_S32_P4_PSI5_S_TRIG0_CLK 212U #define NXP_S32_P4_PSI5_S_TRIG1_CLK 213U #define NXP_S32_P4_PSI5_S_TRIG2_CLK 214U #define NXP_S32_P4_PSI5_S_TRIG3_CLK 215U #define NXP_S32_P4_PSI5_S_UART_CLK 216U #define NXP_S32_P4_PSI5_S_WDOG0_CLK 217U #define NXP_S32_P4_PSI5_S_WDOG1_CLK 218U #define NXP_S32_P4_PSI5_S_WDOG2_CLK 219U #define NXP_S32_P4_PSI5_S_WDOG3_CLK 220U #define NXP_S32_P4_QSPI0_2X_CLK 221U #define NXP_S32_P4_QSPI0_1X_CLK 222U #define NXP_S32_P4_QSPI1_2X_CLK 223U #define NXP_S32_P4_QSPI1_1X_CLK 224U #define NXP_S32_P4_REG_INTF_2X_CLK 225U #define NXP_S32_P4_REG_INTF_CLK 226U #define NXP_S32_P4_SDHC_IP_CLK 227U #define NXP_S32_P4_SDHC_IP_DIV2_CLK 228U #define NXP_S32_P5_DIPORT_CLK 229U #define NXP_S32_P5_AE_CLK 230U #define NXP_S32_P5_CANXL_PE_CLK 231U #define NXP_S32_P5_CANXL_CHI_CLK 232U #define NXP_S32_P5_CLKOUT_SRC_CLK 233U #define NXP_S32_P5_LIN_CLK 234U #define NXP_S32_P5_REG_INTF_CLK 235U #define NXP_S32_P6_REG_INTF_CLK 236U #define NXP_S32_PIT0_CLK 237U #define NXP_S32_PIT1_CLK 238U #define NXP_S32_PIT4_CLK 239U #define NXP_S32_PIT5_CLK 240U #define NXP_S32_P0_PSI5_1US_CLK 241U #define NXP_S32_PSI5_0_CLK 242U #define NXP_S32_P4_PSI5_1US_CLK 243U #define NXP_S32_PSI5_1_CLK 244U #define NXP_S32_PSI5S_0_CLK 245U #define NXP_S32_PSI5S_1_CLK 246U #define NXP_S32_QSPI0_CLK 247U #define NXP_S32_QSPI1_CLK 248U #define NXP_S32_RTU0_CORE_MON1_CLK 249U #define NXP_S32_RTU0_CORE_MON2_CLK 250U #define NXP_S32_RTU0_CORE_DIV2_MON1_CLK 251U #define NXP_S32_RTU0_CORE_DIV2_MON2_CLK 252U #define NXP_S32_RTU0_CORE_DIV2_MON3_CLK 253U #define NXP_S32_RTU0_REG_INTF_CLK 254U #define NXP_S32_RTU1_CORE_MON1_CLK 255U #define NXP_S32_RTU1_CORE_MON2_CLK 256U #define NXP_S32_RTU1_CORE_DIV2_MON1_CLK 257U #define NXP_S32_RTU1_CORE_DIV2_MON2_CLK 258U #define NXP_S32_RTU1_CORE_DIV2_MON3_CLK 259U #define NXP_S32_RTU1_REG_INTF_CLK 260U #define NXP_S32_P4_SDHC_CLK 261U #define NXP_S32_RXLUT_CLK 262U #define NXP_S32_SDHC0_CLK 263U #define NXP_S32_SINC_CLK 264U #define NXP_S32_SIPI0_CLK 265U #define NXP_S32_SIPI1_CLK 266U #define NXP_S32_SIUL2_0_CLK 267U #define NXP_S32_SIUL2_1_CLK 268U #define NXP_S32_SIUL2_4_CLK 269U #define NXP_S32_SIUL2_5_CLK 270U #define NXP_S32_P0_DSPI_CLK 271U #define NXP_S32_SPI0_CLK 272U #define NXP_S32_SPI1_CLK 273U #define NXP_S32_P1_DSPI_CLK 274U #define NXP_S32_SPI2_CLK 275U #define NXP_S32_SPI3_CLK 276U #define NXP_S32_SPI4_CLK 277U #define NXP_S32_P4_DSPI_CLK 278U #define NXP_S32_SPI5_CLK 279U #define NXP_S32_SPI6_CLK 280U #define NXP_S32_SPI7_CLK 281U #define NXP_S32_P5_DSPI_CLK 282U #define NXP_S32_SPI8_CLK 283U #define NXP_S32_SPI9_CLK 284U #define NXP_S32_SRX0_CLK 285U #define NXP_S32_SRX1_CLK 286U #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
4,568
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_ /* clock bus references */ #define STM32_CLOCK_BUS_AHB1 0 #define STM32_CLOCK_BUS_AHB2 1 #define STM32_CLOCK_BUS_APB1 2 #define STM32_CLOCK_BUS_APB2 3 #define STM32_CLOCK_BUS_APB1_2 4 #define STM32_CLOCK_BUS_IOP 5 #define STM32_CLOCK_BUS_AHB3 6 #define STM32_CLOCK_BUS_AHB4 7 #define STM32_CLOCK_BUS_AHB5 8 #define STM32_CLOCK_BUS_AHB6 9 #define STM32_CLOCK_BUS_APB3 10 #define STM32_CLOCK_BUS_APB4 11 #define STM32_CLOCK_BUS_APB5 12 #define STM32_CLOCK_BUS_AXI 13 #define STM32_CLOCK_BUS_MLAHB 14 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
227
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32VF103_CLOCKS_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32VF103_CLOCKS_H_ #include "gd32-clocks-common.h" /** * @name Register offsets * @{ */ #define GD32_AHBEN_OFFSET 0x14U #define GD32_APB1EN_OFFSET 0x1CU #define GD32_APB2EN_OFFSET 0x18U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB peripherals */ #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U) #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U) #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U) #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U) #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U) #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U) #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U) /* APB1 peripherals */ #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U) #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U) #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U) #define GD32_CLOCK_TIMER4 GD32_CLOCK_CONFIG(APB1EN, 3U) #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) #define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U) #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) #define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U) #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) #define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U) #define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U) #define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U) #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) #define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U) #define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U) #define GD32_CLOCK_BKPI GD32_CLOCK_CONFIG(APB1EN, 27U) #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) /* APB2 peripherals */ #define GD32_CLOCK_AFIO GD32_CLOCK_CONFIG(APB2EN, 0U) #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(APB2EN, 2U) #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(APB2EN, 3U) #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(APB2EN, 4U) #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(APB2EN, 5U) #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(APB2EN, 6U) #define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U) #define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U) #define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U) #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32VF103_CLOCKS_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/gd32vf103-clocks.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
920
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K344_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K344_CLOCK_H_ #define NXP_S32_FIRC_CLK 1U #define NXP_S32_FIRC_STANDBY_CLK 2U #define NXP_S32_SIRC_CLK 3U #define NXP_S32_SIRC_STANDBY_CLK 4U #define NXP_S32_FXOSC_CLK 5U #define NXP_S32_SXOSC_CLK 6U #define NXP_S32_PLL_CLK 7U #define NXP_S32_PLL_POSTDIV_CLK 8U #define NXP_S32_PLL_PHI0_CLK 9U #define NXP_S32_PLL_PHI1_CLK 10U #define NXP_S32_EMAC_MII_RX_CLK 11U #define NXP_S32_EMAC_MII_RMII_TX_CLK 12U #define NXP_S32_SCS_CLK 13U #define NXP_S32_CORE_CLK 14U #define NXP_S32_AIPS_PLAT_CLK 15U #define NXP_S32_AIPS_SLOW_CLK 16U #define NXP_S32_HSE_CLK 17U #define NXP_S32_DCM_CLK 18U #define NXP_S32_LBIST_CLK 19U #define NXP_S32_QSPI_MEM_CLK 20U #define NXP_S32_CLKOUT_RUN_CLK 21U #define NXP_S32_ADC0_CLK 23U #define NXP_S32_ADC1_CLK 24U #define NXP_S32_ADC2_CLK 25U #define NXP_S32_BCTU0_CLK 26U #define NXP_S32_CLKOUT_STANDBY_CLK 27U #define NXP_S32_CMP0_CLK 28U #define NXP_S32_CMP1_CLK 29U #define NXP_S32_CMP2_CLK 30U #define NXP_S32_CRC0_CLK 31U #define NXP_S32_DCM0_CLK 32U #define NXP_S32_DMAMUX0_CLK 33U #define NXP_S32_DMAMUX1_CLK 34U #define NXP_S32_EDMA0_CLK 35U #define NXP_S32_EDMA0_TCD0_CLK 36U #define NXP_S32_EDMA0_TCD1_CLK 37U #define NXP_S32_EDMA0_TCD2_CLK 38U #define NXP_S32_EDMA0_TCD3_CLK 39U #define NXP_S32_EDMA0_TCD4_CLK 40U #define NXP_S32_EDMA0_TCD5_CLK 41U #define NXP_S32_EDMA0_TCD6_CLK 42U #define NXP_S32_EDMA0_TCD7_CLK 43U #define NXP_S32_EDMA0_TCD8_CLK 44U #define NXP_S32_EDMA0_TCD9_CLK 45U #define NXP_S32_EDMA0_TCD10_CLK 46U #define NXP_S32_EDMA0_TCD11_CLK 47U #define NXP_S32_EDMA0_TCD12_CLK 48U #define NXP_S32_EDMA0_TCD13_CLK 49U #define NXP_S32_EDMA0_TCD14_CLK 50U #define NXP_S32_EDMA0_TCD15_CLK 51U #define NXP_S32_EDMA0_TCD16_CLK 52U #define NXP_S32_EDMA0_TCD17_CLK 53U #define NXP_S32_EDMA0_TCD18_CLK 54U #define NXP_S32_EDMA0_TCD19_CLK 55U #define NXP_S32_EDMA0_TCD20_CLK 56U #define NXP_S32_EDMA0_TCD21_CLK 57U #define NXP_S32_EDMA0_TCD22_CLK 58U #define NXP_S32_EDMA0_TCD23_CLK 59U #define NXP_S32_EDMA0_TCD24_CLK 60U #define NXP_S32_EDMA0_TCD25_CLK 61U #define NXP_S32_EDMA0_TCD26_CLK 62U #define NXP_S32_EDMA0_TCD27_CLK 63U #define NXP_S32_EDMA0_TCD28_CLK 64U #define NXP_S32_EDMA0_TCD29_CLK 65U #define NXP_S32_EDMA0_TCD30_CLK 66U #define NXP_S32_EDMA0_TCD31_CLK 67U #define NXP_S32_EIM_CLK 68U #define NXP_S32_EMAC_RX_CLK 69U #define NXP_S32_EMAC0_RX_CLK 70U #define NXP_S32_EMAC_TS_CLK 71U #define NXP_S32_EMAC0_TS_CLK 72U #define NXP_S32_EMAC_TX_CLK 73U #define NXP_S32_EMAC0_TX_CLK 74U #define NXP_S32_EMIOS0_CLK 75U #define NXP_S32_EMIOS1_CLK 76U #define NXP_S32_EMIOS2_CLK 77U #define NXP_S32_ERM0_CLK 78U #define NXP_S32_FLEXCANA_CLK 79U #define NXP_S32_FLEXCAN0_CLK 80U #define NXP_S32_FLEXCAN1_CLK 81U #define NXP_S32_FLEXCAN2_CLK 82U #define NXP_S32_FLEXCANB_CLK 83U #define NXP_S32_FLEXCAN3_CLK 84U #define NXP_S32_FLEXCAN4_CLK 85U #define NXP_S32_FLEXCAN5_CLK 86U #define NXP_S32_FLEXIO0_CLK 87U #define NXP_S32_INTM_CLK 88U #define NXP_S32_LCU0_CLK 89U #define NXP_S32_LCU1_CLK 90U #define NXP_S32_LPI2C0_CLK 91U #define NXP_S32_LPI2C1_CLK 92U #define NXP_S32_LPSPI0_CLK 93U #define NXP_S32_LPSPI1_CLK 94U #define NXP_S32_LPSPI2_CLK 95U #define NXP_S32_LPSPI3_CLK 96U #define NXP_S32_LPSPI4_CLK 97U #define NXP_S32_LPSPI5_CLK 98U #define NXP_S32_LPUART0_CLK 99U #define NXP_S32_LPUART1_CLK 100U #define NXP_S32_LPUART2_CLK 101U #define NXP_S32_LPUART3_CLK 102U #define NXP_S32_LPUART4_CLK 103U #define NXP_S32_LPUART5_CLK 104U #define NXP_S32_LPUART6_CLK 105U #define NXP_S32_LPUART7_CLK 106U #define NXP_S32_LPUART8_CLK 107U #define NXP_S32_LPUART9_CLK 108U #define NXP_S32_LPUART10_CLK 109U #define NXP_S32_LPUART11_CLK 110U #define NXP_S32_LPUART12_CLK 111U #define NXP_S32_LPUART13_CLK 112U #define NXP_S32_LPUART14_CLK 113U #define NXP_S32_LPUART15_CLK 114U #define NXP_S32_MSCM_CLK 115U #define NXP_S32_MU2A_CLK 116U #define NXP_S32_MU2B_CLK 117U #define NXP_S32_PIT0_CLK 118U #define NXP_S32_PIT1_CLK 119U #define NXP_S32_PIT2_CLK 120U #define NXP_S32_QSPI0_CLK 121U #define NXP_S32_QSPI0_RAM_CLK 122U #define NXP_S32_QSPI0_TX_MEM_CLK 123U #define NXP_S32_QSPI_SFCK_CLK 124U #define NXP_S32_RTC_CLK 125U #define NXP_S32_RTC0_CLK 126U #define NXP_S32_SAI0_CLK 127U #define NXP_S32_SAI1_CLK 128U #define NXP_S32_SEMA42_CLK 129U #define NXP_S32_SIUL2_CLK 130U #define NXP_S32_STCU0_CLK 131U #define NXP_S32_STMA_CLK 132U #define NXP_S32_STM0_CLK 133U #define NXP_S32_STMB_CLK 134U #define NXP_S32_STM1_CLK 135U #define NXP_S32_SWT0_CLK 136U #define NXP_S32_TEMPSENSE_CLK 137U #define NXP_S32_TRACE_CLK 138U #define NXP_S32_TRGMUX0_CLK 139U #define NXP_S32_TSENSE0_CLK 140U #define NXP_S32_WKPU0_CLK 141U #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K344_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/nxp_s32k344_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
2,166
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus gatting clocks */ #define STM32_CLOCK_BUS_IOP 0x02c #define STM32_CLOCK_BUS_AHB1 0x030 #define STM32_CLOCK_BUS_APB2 0x034 #define STM32_CLOCK_BUS_APB1 0x038 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 /** Domain clocks */ /* RM0367, 7.3.20 Clock configuration register (RCC_CCIPR) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSE (STM32_SRC_LSI + 1) #define STM32_SRC_HSI (STM32_SRC_HSE + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) /** Bus clock */ #define STM32_SRC_PCLK (STM32_SRC_HSI48 + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPR register offset */ #define CCIPR_REG 0x4C /** @brief RCC_CSR register offset */ #define CSR_REG 0x50 /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) #define HSI48_SEL(val) STM32_CLOCK(val, 1, 26, CCIPR_REG) /** CSR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 16, CSR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32l0_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
885
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ /* Supported CPU clock Sources */ #define ESP32_CPU_CLK_SRC_XTAL 0U #define ESP32_CPU_CLK_SRC_PLL 1U #define ESP32_CLK_SRC_RC_FAST 2U #define ESP32_CLK_SRC_APLL_CLK 3U /* Supported PLL CPU frequencies */ #define ESP32_CLK_CPU_PLL_80M 80000000 #define ESP32_CLK_CPU_PLL_160M 160000000 #define ESP32_CLK_CPU_PLL_240M 240000000 #define ESP32_CLK_CPU_RC_FAST_FREQ 1062500 /* Supported XTAL frequencies */ #define ESP32_CLK_XTAL_24M 24000000 #define ESP32_CLK_XTAL_26M 26000000 #define ESP32_CLK_XTAL_40M 40000000 /* Supported RTC fast clock sources */ #define ESP32_RTC_FAST_CLK_SRC_XTAL_D4 0 #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 /* Supported RTC slow clock sources */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 #define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 /* RTC slow clock frequencies */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 150000 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 33203 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. * These IDs shouldn't be changed unless there is a Hardware change * from Espressif. * * Basic Modules * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG */ #define ESP32_LEDC_MODULE 0 #define ESP32_UART0_MODULE 1 #define ESP32_UART1_MODULE 2 #define ESP32_UART2_MODULE 3 #define ESP32_I2C0_MODULE 4 #define ESP32_I2C1_MODULE 5 #define ESP32_I2S0_MODULE 6 #define ESP32_I2S1_MODULE 7 #define ESP32_TIMG0_MODULE 8 #define ESP32_TIMG1_MODULE 9 #define ESP32_PWM0_MODULE 10 #define ESP32_PWM1_MODULE 11 #define ESP32_UHCI0_MODULE 12 #define ESP32_UHCI1_MODULE 13 #define ESP32_RMT_MODULE 14 #define ESP32_PCNT_MODULE 15 #define ESP32_SPI_MODULE 16 #define ESP32_HSPI_MODULE 17 #define ESP32_VSPI_MODULE 18 #define ESP32_SPI_DMA_MODULE 19 #define ESP32_SDMMC_MODULE 20 #define ESP32_SDIO_SLAVE_MODULE 21 #define ESP32_TWAI_MODULE 22 #define ESP32_CAN_MODULE ESP32_TWAI_MODULE #define ESP32_EMAC_MODULE 23 #define ESP32_RNG_MODULE 24 #define ESP32_WIFI_MODULE 25 #define ESP32_BT_MODULE 26 #define ESP32_WIFI_BT_COMMON_MODULE 27 #define ESP32_BT_BASEBAND_MODULE 28 #define ESP32_BT_LC_MODULE 29 #define ESP32_AES_MODULE 30 #define ESP32_SHA_MODULE 31 #define ESP32_RSA_MODULE 32 #define ESP32_SARADC_MODULE 33 #define ESP32_MODULE_MAX 34 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/esp32_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
823
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus clocks */ #define STM32_CLOCK_BUS_IOP 0x034 #define STM32_CLOCK_BUS_AHB1 0x038 #define STM32_CLOCK_BUS_APB1 0x03c #define STM32_CLOCK_BUS_APB1_2 0x040 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2 /** Domain clocks */ /* RM0444, 5.4.21/22 Clock configuration register (RCC_CCIPRx) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1) #define STM32_SRC_HSE (STM32_SRC_MSI + 1) /** Peripheral bus clock */ #define STM32_SRC_PCLK (STM32_SRC_HSE + 1) /** PLL clock outputs */ #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPR register offset */ #define CCIPR_REG 0x54 #define CCIPR2_REG 0x58 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x5C /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG) #define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR_REG) #define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) #define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) #define TIM1_SEL(val) STM32_CLOCK(val, 1, 22, CCIPR_REG) #define TIM15_SEL(val) STM32_CLOCK(val, 1, 24, CCIPR_REG) #define RNG_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG) #define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) /** CCIPR2 devices */ #define I2S1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG) #define I2S2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR2_REG) #define FDCAN_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR2_REG) #define USB_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32g0_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,268
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_ #include "gd32-clocks-common.h" /** * @name Register offsets * @{ */ #define GD32_AHBEN_OFFSET 0x14U #define GD32_APB1EN_OFFSET 0x1CU #define GD32_APB2EN_OFFSET 0x18U #define GD32_ADDAPB1EN_OFFSET 0xE4U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB peripherals */ #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U) #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U) #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U) #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U) #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U) #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U) #define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(AHBEN, 10U) #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U) /* APB1 peripherals */ #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U) #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U) #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) #define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U) #define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U) #define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U) #define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U) #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) #define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U) #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) #define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U) #define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U) #define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U) #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) #define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U) #define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U) #define GD32_CLOCK_BKPI GD32_CLOCK_CONFIG(APB1EN, 27U) #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) /* APB2 peripherals */ #define GD32_CLOCK_AFIO GD32_CLOCK_CONFIG(APB2EN, 0U) #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(APB2EN, 2U) #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(APB2EN, 3U) #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(APB2EN, 4U) #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(APB2EN, 5U) #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(APB2EN, 6U) #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(APB2EN, 7U) #define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(APB2EN, 8U) #define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U) #define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U) #define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U) #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) #define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 13U) #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) #define GD32_CLOCK_ADC2 GD32_CLOCK_CONFIG(APB2EN, 15U) #define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 19U) #define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 20U) #define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 21U) /* APB1 additional peripherals */ #define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/gd32f403-clocks.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,144
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x048 #define STM32_CLOCK_BUS_AHB2 0x04c #define STM32_CLOCK_BUS_AHB3 0x050 #define STM32_CLOCK_BUS_APB1 0x058 #define STM32_CLOCK_BUS_APB1_2 0x05c #define STM32_CLOCK_BUS_APB2 0x060 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2 /** Domain clocks */ /* RM0351/RM0432/RM0438, Clock configuration register (RCC_CCIPRx) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1) /** Bus clock */ #define STM32_SRC_PCLK (STM32_SRC_MSI + 1) /** PLL clock outputs */ #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) /* TODO: PLLSAI clocks */ #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPR register offset */ #define CCIPR_REG 0x88 #define CCIPR2_REG 0x9C /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x90 /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG) #define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG) #define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) #define SAI1_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG) #define SAI2_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR_REG) #define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG) #define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG) #define SWPMI1_SEL(val) STM32_CLOCK(val, 1, 30, CCIPR_REG) #define DFSDM1_SEL(val) STM32_CLOCK(val, 1, 31, CCIPR_REG) /** CCIPR2 devices */ #define I2C4_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG) #define DFSDM_SEL(val) STM32_CLOCK(val, 1, 2, CCIPR2_REG) #define ADFSDM_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR2_REG) /* #define SAI1_SEL(val) STM32_CLOCK(val, 7, 5, CCIPR2_REG) */ /* #define SAI2_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG) */ #define DSI_SEL(val) STM32_CLOCK(val, 1, 12, CCIPR2_REG) #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG) #define OSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32l4_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,469
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCX_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCX_CLOCK_H_ /* clock bus references */ #define NPCX_CLOCK_BUS_FREERUN 0 #define NPCX_CLOCK_BUS_LFCLK 1 #define NPCX_CLOCK_BUS_OSC 2 #define NPCX_CLOCK_BUS_FIU 3 #define NPCX_CLOCK_BUS_CORE 4 #define NPCX_CLOCK_BUS_APB1 5 #define NPCX_CLOCK_BUS_APB2 6 #define NPCX_CLOCK_BUS_APB3 7 #define NPCX_CLOCK_BUS_APB4 8 #define NPCX_CLOCK_BUS_AHB6 9 #define NPCX_CLOCK_BUS_FMCLK 10 #define NPCX_CLOCK_BUS_FIU0 NPCX_CLOCK_BUS_FIU #define NPCX_CLOCK_BUS_FIU1 11 #define NPCX_CLOCK_BUS_MCLKD 12 /* clock enable/disable references */ #define NPCX_PWDWN_CTL1 0 #define NPCX_PWDWN_CTL2 1 #define NPCX_PWDWN_CTL3 2 #define NPCX_PWDWN_CTL4 3 #define NPCX_PWDWN_CTL5 4 #define NPCX_PWDWN_CTL6 5 #define NPCX_PWDWN_CTL7 6 #define NPCX_PWDWN_CTL8 7 #define NPCX_PWDWN_CTL9 8 #define NPCX_PWDWN_CTL_COUNT 9 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCX_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/npcx_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
344
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_ #define KINETIS_SIM_CORESYS_CLK 0 #define KINETIS_SIM_PLATFORM_CLK 1 #define KINETIS_SIM_BUS_CLK 2 #define KINETIS_SIM_FAST_PERIPHERAL_CLK 5 #define KINETIS_SIM_LPO_CLK 19 #define KINETIS_SIM_DMAMUX_CLK KINETIS_SIM_BUS_CLK #define KINETIS_SIM_DMA_CLK KINETIS_SIM_CORESYS_CLK #define KINETIS_SIM_SIM_SOPT7 7 #define KINETIS_SIM_PLLFLLSEL_MCGFLLCLK 0 #define KINETIS_SIM_PLLFLLSEL_MCGPLLCLK 1 #define KINETIS_SIM_PLLFLLSEL_IRC48MHZ 3 #define KINETIS_SIM_ER32KSEL_OSC32KCLK 0 #define KINETIS_SIM_ER32KSEL_RTC 2 #define KINETIS_SIM_ER32KSEL_LPO1KHZ 3 #define KINETIS_SIM_ENET_CLK 4321 #define KINETIS_SIM_ENET_1588_CLK 4322 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/kinetis_sim.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
283
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_ #define RPI_PICO_PLL_SYS 0 #define RPI_PICO_PLL_USB 1 #define RPI_PICO_PLL_COUNT 2 #define RPI_PICO_GPIN_0 0 #define RPI_PICO_GPIN_1 1 #define RPI_PICO_GPIN_COUNT 2 #define RPI_PICO_CLKID_CLK_GPOUT0 0 #define RPI_PICO_CLKID_CLK_GPOUT1 1 #define RPI_PICO_CLKID_CLK_GPOUT2 2 #define RPI_PICO_CLKID_CLK_GPOUT3 3 #define RPI_PICO_CLKID_CLK_REF 4 #define RPI_PICO_CLKID_CLK_SYS 5 #define RPI_PICO_CLKID_CLK_PERI 6 #define RPI_PICO_CLKID_CLK_USB 7 #define RPI_PICO_CLKID_CLK_ADC 8 #define RPI_PICO_CLKID_CLK_RTC 9 #define RPI_PICO_CLKID_PLL_SYS 10 #define RPI_PICO_CLKID_PLL_USB 11 #define RPI_PICO_CLKID_XOSC 12 #define RPI_PICO_CLKID_ROSC 13 #define RPI_PICO_CLKID_ROSC_PH 14 #define RPI_PICO_CLKID_GPIN0 15 #define RPI_PICO_CLKID_GPIN1 16 #define RPI_PICO_ROSC_RANGE_RESET 0xAA0 #define RPI_PICO_ROSC_RANGE_LOW 0xFA4 #define RPI_PICO_ROSC_RANGE_MEDIUM 0xFA5 #define RPI_PICO_ROSC_RANGE_HIGH 0xFA7 #define RPI_PICO_ROSC_RANGE_TOOHIGH 0xFA6 #define RPI_PICO_CLOCK_COUNT 10 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/rpi_pico_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
442
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_ #include "renesas_cpg_mssr.h" /* r8a7795 CPG Core Clocks */ #define R8A7795_CLK_Z 0 #define R8A7795_CLK_Z2 1 #define R8A7795_CLK_ZR 2 #define R8A7795_CLK_ZG 3 #define R8A7795_CLK_ZTR 4 #define R8A7795_CLK_ZTRD2 5 #define R8A7795_CLK_ZT 6 #define R8A7795_CLK_ZX 7 #define R8A7795_CLK_S0D1 8 #define R8A7795_CLK_S0D4 9 #define R8A7795_CLK_S1D1 10 #define R8A7795_CLK_S1D2 11 #define R8A7795_CLK_S1D4 12 #define R8A7795_CLK_S2D1 13 #define R8A7795_CLK_S2D2 14 #define R8A7795_CLK_S2D4 15 #define R8A7795_CLK_S3D1 16 #define R8A7795_CLK_S3D2 17 #define R8A7795_CLK_S3D4 18 /* SCIF clock */ #define R8A7795_CLK_LB 19 #define R8A7795_CLK_CL 20 #define R8A7795_CLK_ZB3 21 #define R8A7795_CLK_ZB3D2 22 #define R8A7795_CLK_CR 23 #define R8A7795_CLK_CRD2 24 #define R8A7795_CLK_SD0H 25 #define R8A7795_CLK_SD0 26 #define R8A7795_CLK_SD1H 27 #define R8A7795_CLK_SD1 28 #define R8A7795_CLK_SD2H 29 #define R8A7795_CLK_SD2 30 #define R8A7795_CLK_SD3H 31 #define R8A7795_CLK_SD3 32 #define R8A7795_CLK_SSP2 33 #define R8A7795_CLK_SSP1 34 #define R8A7795_CLK_SSPRS 35 #define R8A7795_CLK_RPC 36 #define R8A7795_CLK_RPCD2 37 #define R8A7795_CLK_MSO 38 #define R8A7795_CLK_CANFD 39 /* CANFD clock */ #define R8A7795_CLK_HDMI 40 #define R8A7795_CLK_CSI0 41 /* CLK_CSIREF was removed */ #define R8A7795_CLK_CP 43 #define R8A7795_CLK_CPEX 44 #define R8A7795_CLK_R 45 #define R8A7795_CLK_OSC 46 /* r8a7795 ES2.0 CPG Core Clocks */ #define R8A7795_CLK_S0D2 47 #define R8A7795_CLK_S0D3 48 #define R8A7795_CLK_S0D6 49 #define R8A7795_CLK_S0D8 50 #define R8A7795_CLK_S0D12 51 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
833
```objective-c /* * */ #ifndef ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_ #define ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_ #define RA_CLOCK(grp, func, ch) ((grp << 28) | (func << 20) | ch) #define RA_CLOCK_GROUP(mod) (((mod >> 28) & 0xF) * 4) #define RA_CLOCK_BIT(mod) BIT(((mod >> 20) & 0xFF) - ((mod >> 0) & 0xF)) #define RA_CLOCK_DMAC(channel) RA_CLOCK(0, 22, channel) #define RA_CLOCK_DTC(channel) RA_CLOCK(0, 22, channel) #define RA_CLOCK_CAN(channel) RA_CLOCK(1, 2, channel) #define RA_CLOCK_CEC(channel) RA_CLOCK(1, 3U, channel) #define RA_CLOCK_I3C(channel) RA_CLOCK(1, 4U, channel) #define RA_CLOCK_IRDA(channel) RA_CLOCK(1, 5U, channel) #define RA_CLOCK_QSPI(channel) RA_CLOCK(1, 6U, channel) #define RA_CLOCK_IIC(channel) RA_CLOCK(1, 9U, channel) #define RA_CLOCK_USBFS(channel) RA_CLOCK(1, 11U, channel) #define RA_CLOCK_USBHS(channel) RA_CLOCK(1, 12U, channel) #define RA_CLOCK_EPTPC(channel) RA_CLOCK(1, 13U, channel) #define RA_CLOCK_ETHER(channel) RA_CLOCK(1, 15U, channel) #define RA_CLOCK_OSPI(channel) RA_CLOCK(1, 16U, channel) #define RA_CLOCK_SPI(channel) RA_CLOCK(1, 19U, channel) #define RA_CLOCK_SCI(channel) RA_CLOCK(1, 31U, channel) #define RA_CLOCK_CAC(channel) RA_CLOCK(2, 0U, channel) #define RA_CLOCK_CRC(channel) RA_CLOCK(2, 1U, channel) #define RA_CLOCK_PDC(channel) RA_CLOCK(2, 2U, channel) #define RA_CLOCK_CTSU(channel) RA_CLOCK(2, 3U, channel) #define RA_CLOCK_SLCDC(channel) RA_CLOCK(2, 4U, channel) #define RA_CLOCK_GLCDC(channel) RA_CLOCK(2, 4U, channel) #define RA_CLOCK_JPEG(channel) RA_CLOCK(2, 5U, channel) #define RA_CLOCK_DRW(channel) RA_CLOCK(2, 6U, channel) #define RA_CLOCK_SSI(channel) RA_CLOCK(2, 8U, channel) #define RA_CLOCK_SRC(channel) RA_CLOCK(2, 9U, channel) #define RA_CLOCK_SDHIMMC(channel) RA_CLOCK(2, 12U, channel) #define RA_CLOCK_DOC(channel) RA_CLOCK(2, 13U, channel) #define RA_CLOCK_ELC(channel) RA_CLOCK(2, 14U, channel) #define RA_CLOCK_CEU(channel) RA_CLOCK(2, 16U, channel) #define RA_CLOCK_TFU(channel) RA_CLOCK(2, 20U, channel) #define RA_CLOCK_IIRFA(channel) RA_CLOCK(2, 21U, channel) #define RA_CLOCK_CANFD(channel) RA_CLOCK(2, 27U, channel) #define RA_CLOCK_TRNG(channel) RA_CLOCK(2, 28U, channel) #define RA_CLOCK_SCE(channel) RA_CLOCK(2, 31U, channel) #define RA_CLOCK_AES(channel) RA_CLOCK(2, 31U, channel) #define RA_CLOCK_POEG(channel) RA_CLOCK(3, 14U, channel) #define RA_CLOCK_ADC(channel) RA_CLOCK(3, 16U, channel) #define RA_CLOCK_SDADC(channel) RA_CLOCK(3, 17U, channel) #define RA_CLOCK_DAC8(channel) RA_CLOCK(3, 19U, channel) #define RA_CLOCK_DAC(channel) RA_CLOCK(3, 20U, channel) #define RA_CLOCK_TSN(channel) RA_CLOCK(3, 22U, channel) #define RA_CLOCK_ACMPHS(channel) RA_CLOCK(3, 28U, channel) #define RA_CLOCK_ACMPLP(channel) RA_CLOCK(3, 29U, channel) #define RA_CLOCK_OPAMP(channel) RA_CLOCK(3, 31U, channel) #define RA_CLOCK_AGT(channel) RA_CLOCK(4, 3U, channel) #define RA_CLOCK_KEY(channel) RA_CLOCK(4, 4U, channel) #define RA_CLOCK_ULPT(channel) RA_CLOCK(4, 9U, channel) #define RA_CLOCK_GPT(channel) RA_CLOCK(5, 31U, channel) #endif /* ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/renesas-ra-cgc.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,045
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus gatting clocks */ #define STM32_CLOCK_BUS_AHB1 0x01c #define STM32_CLOCK_BUS_APB2 0x020 #define STM32_CLOCK_BUS_APB1 0x024 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 /** Domain clocks */ /* RM0038.pdf, 6.3.14 Control/status register (RCC_CSR) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSE (STM32_SRC_LSI + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CSR register offset */ #define CSR_REG 0x34 #define RTC_SEL(val) STM32_CLOCK(val, 3, 16, CSR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32l1_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
594
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus gatting clocks */ #define STM32_CLOCK_BUS_AHB1 0x014 #define STM32_CLOCK_BUS_APB2 0x018 #define STM32_CLOCK_BUS_APB1 0x01c #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 /** Domain clocks */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) #define STM32_SRC_HSI14 (STM32_SRC_HSI + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSI14 + 1) /** Bus clock */ #define STM32_SRC_PCLK (STM32_SRC_HSI48 + 1) /** PLL clock */ #define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CFGRx register offset * @param shift Position within RCC_CFGRx. * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CFGRx register offset */ #define CFGR3_REG 0x30 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x20 /** @brief Device domain clocks selection helpers */ /** CFGR3 devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG) #define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG) #define USB_SEL(val) STM32_CLOCK(val, 1, 7, CFGR3_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG) #define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f0_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
849
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_ #define NXP_S32_LPO_128K_CLK 1U #define NXP_S32_SIRC_CLK 2U #define NXP_S32_SIRC_VLP_CLK 3U #define NXP_S32_SIRC_STOP_CLK 4U #define NXP_S32_FIRC_CLK 5U #define NXP_S32_FIRC_VLP_CLK 6U #define NXP_S32_FIRC_STOP_CLK 7U #define NXP_S32_SOSC_CLK 8U #define NXP_S32_SPLL_CLK 9U #define NXP_S32_SIRCDIV1_CLK 10U #define NXP_S32_SIRCDIV2_CLK 11U #define NXP_S32_FIRCDIV1_CLK 12U #define NXP_S32_FIRCDIV2_CLK 13U #define NXP_S32_SOSCDIV1_CLK 14U #define NXP_S32_SOSCDIV2_CLK 15U #define NXP_S32_SPLLDIV1_CLK 16U #define NXP_S32_SPLLDIV2_CLK 17U #define NXP_S32_LPO_32K_CLK 18U #define NXP_S32_LPO_1K_CLK 19U #define NXP_S32_TCLK0_REF_CLK 20U #define NXP_S32_TCLK1_REF_CLK 21U #define NXP_S32_TCLK2_REF_CLK 22U #define NXP_S32_SCS_CLK 24U #define NXP_S32_SCS_RUN_CLK 25U #define NXP_S32_SCS_VLPR_CLK 26U #define NXP_S32_SCS_HSRUN_CLK 27U #define NXP_S32_CORE_CLK 28U #define NXP_S32_CORE_RUN_CLK 29U #define NXP_S32_CORE_VLPR_CLK 30U #define NXP_S32_CORE_HSRUN_CLK 31U #define NXP_S32_BUS_CLK 32U #define NXP_S32_BUS_RUN_CLK 33U #define NXP_S32_BUS_VLPR_CLK 34U #define NXP_S32_BUS_HSRUN_CLK 35U #define NXP_S32_SLOW_CLK 36U #define NXP_S32_SLOW_RUN_CLK 37U #define NXP_S32_SLOW_VLPR_CLK 38U #define NXP_S32_SLOW_HSRUN_CLK 39U #define NXP_S32_RTC_CLK 40U #define NXP_S32_LPO_CLK 41U #define NXP_S32_SCG_CLKOUT_CLK 42U #define NXP_S32_FTM0_EXT_CLK 43U #define NXP_S32_FTM1_EXT_CLK 44U #define NXP_S32_FTM2_EXT_CLK 45U #define NXP_S32_FTM3_EXT_CLK 46U #define NXP_S32_FTM4_EXT_CLK 47U #define NXP_S32_FTM5_EXT_CLK 48U #define NXP_S32_ADC0_CLK 50U #define NXP_S32_ADC1_CLK 51U #define NXP_S32_CLKOUT0_CLK 52U #define NXP_S32_CMP0_CLK 53U #define NXP_S32_CRC0_CLK 54U #define NXP_S32_DMA0_CLK 55U #define NXP_S32_DMAMUX0_CLK 56U #define NXP_S32_EIM0_CLK 57U #define NXP_S32_ERM0_CLK 58U #define NXP_S32_EWM0_CLK 59U #define NXP_S32_FLEXCAN0_CLK 60U #define NXP_S32_FLEXCAN1_CLK 61U #define NXP_S32_FLEXCAN2_CLK 62U #define NXP_S32_FLEXIO_CLK 63U #define NXP_S32_FTFC_CLK 64U #define NXP_S32_FTM0_CLK 65U #define NXP_S32_FTM1_CLK 66U #define NXP_S32_FTM2_CLK 67U #define NXP_S32_FTM3_CLK 68U #define NXP_S32_FTM4_CLK 69U #define NXP_S32_FTM5_CLK 70U #define NXP_S32_LPI2C0_CLK 71U #define NXP_S32_LPIT0_CLK 72U #define NXP_S32_LPSPI0_CLK 73U #define NXP_S32_LPSPI1_CLK 74U #define NXP_S32_LPSPI2_CLK 75U #define NXP_S32_LPTMR0_CLK 76U #define NXP_S32_LPUART0_CLK 77U #define NXP_S32_LPUART1_CLK 78U #define NXP_S32_LPUART2_CLK 79U #define NXP_S32_MPU0_CLK 80U #define NXP_S32_MSCM0_CLK 81U #define NXP_S32_PDB0_CLK 82U #define NXP_S32_PDB1_CLK 83U #define NXP_S32_PORTA_CLK 84U #define NXP_S32_PORTB_CLK 85U #define NXP_S32_PORTC_CLK 86U #define NXP_S32_PORTD_CLK 87U #define NXP_S32_PORTE_CLK 88U #define NXP_S32_RTC0_CLK 89U #define NXP_S32_TRACE_CLK 90U #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/nxp_s32k146_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,327
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_ /* Supported CPU clock Sources */ #define ESP32_CPU_CLK_SRC_XTAL 0U #define ESP32_CPU_CLK_SRC_PLL 1U #define ESP32_CLK_SRC_RC_FAST 2U #define ESP32_CLK_SRC_APLL_CLK 3U /* Supported PLL CPU frequencies */ #define ESP32_CLK_CPU_PLL_80M 80000000 #define ESP32_CLK_CPU_PLL_160M 160000000 #define ESP32_CLK_CPU_PLL_240M 240000000 #define ESP32_CLK_CPU_RC_FAST_FREQ 8500000 /* Supported XTAL frequencies */ #define ESP32_CLK_XTAL_40M 40000000 /* Supported RTC fast clock sources */ #define ESP32_RTC_FAST_CLK_SRC_XTAL_D4 0 #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 /* Supported RTC slow clock sources */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 #define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 /* RTC slow clock frequencies */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 90000 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 33203 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. * These IDs shouldn't be changed unless there is a Hardware change * from Espressif. * * Basic Modules * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG */ #define ESP32_LEDC_MODULE 0 #define ESP32_UART0_MODULE 1 #define ESP32_UART1_MODULE 2 #define ESP32_USB_MODULE 3 #define ESP32_I2C0_MODULE 4 #define ESP32_I2C1_MODULE 5 #define ESP32_I2S0_MODULE 6 #define ESP32_TIMG0_MODULE 7 #define ESP32_TIMG1_MODULE 8 #define ESP32_UHCI0_MODULE 9 #define ESP32_UHCI1_MODULE 10 #define ESP32_RMT_MODULE 11 #define ESP32_PCNT_MODULE 12 #define ESP32_SPI_MODULE 13 #define ESP32_FSPI_MODULE 14 #define ESP32_HSPI_MODULE 15 #define ESP32_SPI2_DMA_MODULE 16 #define ESP32_SPI3_DMA_MODULE 17 #define ESP32_TWAI_MODULE 18 #define ESP32_RNG_MODULE 19 #define ESP32_WIFI_MODULE 20 #define ESP32_WIFI_BT_COMMON_MODULE 21 #define ESP32_SYSTIMER_MODULE 22 #define ESP32_AES_MODULE 23 #define ESP32_SHA_MODULE 24 #define ESP32_RSA_MODULE 25 #define ESP32_CRYPTO_DMA_MODULE 26 #define ESP32_AES_DMA_MODULE 27 #define ESP32_SHA_DMA_MODULE 28 #define ESP32_DEDIC_GPIO_MODULE 29 #define ESP32_PERIPH_SARADC_MODULE 30 #define ESP32_MODULE_MAX 31 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/esp32s2_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
755
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x048 #define STM32_CLOCK_BUS_AHB2 0x04c #define STM32_CLOCK_BUS_AHB3 0x050 #define STM32_CLOCK_BUS_APB1 0x058 #define STM32_CLOCK_BUS_APB1_2 0x05c #define STM32_CLOCK_BUS_APB2 0x060 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2 /** Domain clocks */ /* RM0434, Clock configuration register (RCC_CCIPRx) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1) #define STM32_SRC_HSE (STM32_SRC_MSI + 1) /** Bus clock */ #define STM32_SRC_PCLK (STM32_SRC_HSE + 1) /** PLL clock outputs */ #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) /* TODO: PLLSAI clocks */ #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPR register offset */ #define CCIPR_REG 0x88 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x90 /** @brief RCC_CSR register offset */ #define CSR_REG 0x94 /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) #define SAI1_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG) #define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG) #define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG) #define RNG_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) /** CSR devices */ #define RFWKP_SEL(val) STM32_CLOCK(val, 3, 14, CSR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32wb_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,111
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ /* * Define 16 bits clock ID: 0xXXXX * The highest 8 bits is Peripheral ID * The lowest 8 bits is Instance ID */ #define IMX_CCM_PERIPHERAL_MASK 0xFF00UL #define IMX_CCM_INSTANCE_MASK 0x00FFUL #define IMX_CCM_CORESYS_CLK 0x0000UL #define IMX_CCM_PLATFORM_CLK 0x0100UL #define IMX_CCM_BUS_CLK 0x0200UL #define IMX_CCM_LPUART_CLK 0x0300UL #define IMX_CCM_LPUART1_CLK 0x0300UL #define IMX_CCM_LPUART2_CLK 0x0301UL #define IMX_CCM_LPUART3_CLK 0x0302UL #define IMX_CCM_LPUART4_CLK 0x0303UL #define IMX_CCM_LPUART5_CLK 0x0304UL #define IMX_CCM_LPUART6_CLK 0x0305UL #define IMX_CCM_LPUART7_CLK 0x0306UL #define IMX_CCM_LPUART8_CLK 0x0307UL #define IMX_CCM_LPI2C_CLK 0x0400UL #define IMX_CCM_LPSPI_CLK 0x0500UL #define IMX_CCM_USDHC1_CLK 0x0600UL #define IMX_CCM_USDHC2_CLK 0x0601UL #define IMX_CCM_EDMA_CLK 0x0700UL #define IMX_CCM_UART1_CLK 0x0800UL #define IMX_CCM_UART2_CLK 0x0801UL #define IMX_CCM_UART3_CLK 0x0802UL #define IMX_CCM_UART4_CLK 0x0803UL #define IMX_CCM_CAN_CLK 0x0900UL #define IMX_CCM_GPT_CLK 0x0A00UL #define IMX_CCM_SAI1_CLK 0x0B00UL #define IMX_CCM_SAI2_CLK 0x0B01UL #define IMX_CCM_SAI3_CLK 0x0B02UL #define IMX_CCM_PWM_CLK 0x0C00UL #define IMX_CCM_QTMR_CLK 0x0D00UL #define IMX_CCM_ENET_CLK 0x0E00UL #define IMX_CCM_ENET_PLL 0x0E01UL #define IMX_CCM_FLEXSPI_CLK 0x0F00UL #define IMX_CCM_FLEXSPI2_CLK 0x0F01UL #define IMX_CCM_PIT_CLK 0x1000UL #define IMX_CCM_FLEXIO1_CLK 0x1100UL #define IMX_CCM_FLEXIO2_3_CLK 0x1101UL #define IMX_CCM_ECSPI1_CLK 0x1200UL #define IMX_CCM_ECSPI2_CLK 0x1201UL #define IMX_CCM_ECSPI3_CLK 0x1202UL #define IMX_CCM_GPT_IPG_CLK 0x1300UL #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/imx_ccm.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
795
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_ /* Supported CPU clock Sources */ #define ESP32_CPU_CLK_SRC_XTAL 0U #define ESP32_CPU_CLK_SRC_PLL 1U #define ESP32_CLK_SRC_RC_FAST 2U /* Supported CPU frequencies */ #define ESP32_CLK_CPU_PLL_80M 80000000 #define ESP32_CLK_CPU_PLL_160M 160000000 #define ESP32_CLK_CPU_RC_FAST_FREQ 17500000 /* Supported XTAL frequencies */ #define ESP32_CLK_XTAL_32M 32000000 #define ESP32_CLK_XTAL_40M 40000000 /* Supported RTC fast clock sources */ #define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 0 #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 /* Supported RTC slow clock sources */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 #define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 /* RTC slow clock frequencies */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 68359 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. * These IDs shouldn't be changed unless there is a Hardware change * from Espressif. * * Basic Modules * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG */ #define ESP32_LEDC_MODULE 0 #define ESP32_UART0_MODULE 1 #define ESP32_UART1_MODULE 2 #define ESP32_USB_MODULE 3 #define ESP32_I2C0_MODULE 4 #define ESP32_I2S1_MODULE 5 #define ESP32_TIMG0_MODULE 6 #define ESP32_TIMG1_MODULE 7 #define ESP32_UHCI0_MODULE 8 #define ESP32_RMT_MODULE 9 #define ESP32_SPI_MODULE 10 #define ESP32_SPI2_MODULE 11 #define ESP32_TWAI_MODULE 12 #define ESP32_RNG_MODULE 13 #define ESP32_WIFI_MODULE 14 #define ESP32_BT_MODULE 15 #define ESP32_WIFI_BT_COMMON_MODULE 16 #define ESP32_BT_BASEBAND_MODULE 17 #define ESP32_BT_LC_MODULE 18 #define ESP32_RSA_MODULE 19 #define ESP32_AES_MODULE 20 #define ESP32_SHA_MODULE 21 #define ESP32_HMAC_MODULE 22 #define ESP32_DS_MODULE 23 #define ESP32_GDMA_MODULE 24 #define ESP32_SYSTIMER_MODULE 25 #define ESP32_SARADC_MODULE 26 #define ESP32_MODULE_MAX 27 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/esp32c3_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
695
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E10X_CLOCKS_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E10X_CLOCKS_H_ #include "gd32-clocks-common.h" /** * @name Register offsets * @{ */ #define GD32_AHBEN_OFFSET 0x14U #define GD32_APB1EN_OFFSET 0x1CU #define GD32_APB2EN_OFFSET 0x18U #define GD32_ADDAPB1EN_OFFSET 0xE4U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB peripherals */ #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U) #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U) #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U) #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U) #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U) #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U) #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U) /* APB1 peripherals */ #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U) #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U) #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U) #define GD32_CLOCK_TIMER4 GD32_CLOCK_CONFIG(APB1EN, 3U) #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) #define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U) #define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U) #define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U) #define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U) #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) #define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U) #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) #define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U) #define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U) #define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U) #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) #define GD32_CLOCK_BKPI GD32_CLOCK_CONFIG(APB1EN, 27U) #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) /* APB2 peripherals */ #define GD32_CLOCK_AFIO GD32_CLOCK_CONFIG(APB2EN, 0U) #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(APB2EN, 2U) #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(APB2EN, 3U) #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(APB2EN, 4U) #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(APB2EN, 5U) #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(APB2EN, 6U) #define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U) #define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U) #define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U) #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) #define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 13U) #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) #define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 19U) #define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 20U) #define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 21U) /* APB1 additional peripherals */ #define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E10X_CLOCKS_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/gd32e10x-clocks.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,068
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_ /** System clock */ #define STM32_SRC_SYSCLK 0x001 /** Fixed clocks */ #define STM32_SRC_LSE 0x002 #define STM32_SRC_LSI 0x003 /** Dummy: Add a specifier when no selection is possible */ #define NO_SEL 0xFF #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32_common_clocks.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
124
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_COMMON_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_COMMON_H_ /** * Encode RCU register offset and configuration bit. * * - 0..5: bit number * - 6..14: offset * - 15: reserved * * @param reg RCU register name (expands to GD32_{reg}_OFFSET) * @param bit Configuration bit */ #define GD32_CLOCK_CONFIG(reg, bit) \ (((GD32_ ## reg ## _OFFSET) << 6U) | (bit)) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/gd32-clocks-common.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
149
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_ #include "gd32-clocks-common.h" /** * @name Register offsets * @{ */ #define GD32_AHBEN_OFFSET 0x14U #define GD32_APB1EN_OFFSET 0x1CU #define GD32_APB2EN_OFFSET 0x18U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB peripherals */ #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U) #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U) #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U) #define GD32_CLOCK_DMAMUX GD32_CLOCK_CONFIG(AHBEN, 3U) #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U) #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U) #define GD32_CLOCK_MFCOM GD32_CLOCK_CONFIG(AHBEN, 14U) #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U) #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHBEN, 18U) #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHBEN, 19U) #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHBEN, 20U) #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHBEN, 21U) #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHBEN, 22U) /* APB1 peripherals */ #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U) #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) #define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U) #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) #define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U) #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) #define GD32_CLOCK_BKP GD32_CLOCK_CONFIG(APB1EN, 26U) #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) /* APB2 peripherals */ #define GD32_CLOCK_SYSCFG GD32_CLOCK_CONFIG(APB2EN, 0U) #define GD32_CLOCK_CMP GD32_CLOCK_CONFIG(APB2EN, 1U) #define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U) #define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U) #define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U) #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) #define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 13U) #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) #define GD32_CLOCK_TIMER19 GD32_CLOCK_CONFIG(APB2EN, 20U) #define GD32_CLOCK_TIMER20 GD32_CLOCK_CONFIG(APB2EN, 21U) #define GD32_CLOCK_TRIGSEL GD32_CLOCK_CONFIG(APB2EN, 29U) #define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB2EN, 30U) #define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB2EN, 31U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/gd32a50x-clocks.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
919
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ #include "stm32_common_clocks.h" /** Domain clocks */ /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x030 #define STM32_CLOCK_BUS_AHB2 0x034 #define STM32_CLOCK_BUS_AHB3 0x038 #define STM32_CLOCK_BUS_APB1 0x040 #define STM32_CLOCK_BUS_APB2 0x044 #define STM32_CLOCK_BUS_APB3 0x0A8 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 /** Domain clocks */ /* RM0386, 0390, 0402, 0430 Dedicated Clock configuration register (RCC_DCKCFGRx) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ /** PLL clock outputs */ #define STM32_SRC_PLL_P (STM32_SRC_LSI + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) /** I2S sources */ #define STM32_SRC_PLLI2S_R (STM32_SRC_PLL_R + 1) /* I2S_CKIN not supported yet */ /* #define STM32_SRC_I2S_CKIN TBD */ #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CFGRx register offset * @param shift Position within RCC_CFGRx. * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CFGR register offset */ #define CFGR_REG 0x08 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x70 /** @brief Device domain clocks selection helpers */ /** CFGR devices */ #define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f4_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
806
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M2L31_CLOCK_H #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M2L31_CLOCK_H #define NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_LXT 0x00000001 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_PLL 0x00000002 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_LIRC 0x00000003 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_MIRC 0x00000005 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC48M 0x00000006 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC 0x00000007 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_LXT 0x00000001 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_PLL 0x00000002 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_LIRC 0x00000003 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_MIRC 0x00000005 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HIRC48M 0x00000006 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HIRC 0x00000007 #define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL0_STCLKSEL_LXT 0x00000008 #define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT_DIV2 0x00000010 #define NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x00000018 #define NUMAKER_CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x00000038 #define NUMAKER_CLK_CLKSEL0_HCLK1SEL_HIRC 0x00000000 #define NUMAKER_CLK_CLKSEL0_HCLK1SEL_MIRC 0x00001000 #define NUMAKER_CLK_CLKSEL0_HCLK1SEL_LXT 0x00002000 #define NUMAKER_CLK_CLKSEL0_HCLK1SEL_LIRC 0x00003000 #define NUMAKER_CLK_CLKSEL0_HCLK1SEL_HIRC48M_DIV2 0x00004000 #define NUMAKER_CLK_CLKSEL0_USBSEL_HIRC48M 0x00000000 #define NUMAKER_CLK_CLKSEL0_USBSEL_PLL 0x00000100 #define NUMAKER_CLK_CLKSEL0_EADC0SEL_PLL 0x00000400 #define NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK 0x00000800 #define NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK0 0x00000800 #define NUMAKER_CLK_CLKSEL0_EADC0SEL_HIRC 0x00000C00 #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HIRC48M 0x01000000 #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK 0x02000000 #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK0 0x02000000 #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HIRC 0x03000000 #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HIRC48M 0x04000000 #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK 0x08000000 #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK0 0x08000000 #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HIRC 0x0C000000 #define NUMAKER_CLK_CLKSEL1_CLKOSEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL1_CLKOSEL_LXT 0x00000010 #define NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK 0x00000020 #define NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK0 0x00000020 #define NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC 0x00000030 #define NUMAKER_CLK_CLKSEL1_CLKOSEL_LIRC 0x00000040 #define NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC48M 0x00000050 #define NUMAKER_CLK_CLKSEL1_CLKOSEL_PLL 0x00000060 #define NUMAKER_CLK_CLKSEL1_CLKOSEL_MIRC 0x00000070 #define NUMAKER_CLK_CLKSEL1_TMR0SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL1_TMR0SEL_LXT 0x00000100 #define NUMAKER_CLK_CLKSEL1_TMR0SEL_PCLK0 0x00000200 #define NUMAKER_CLK_CLKSEL1_TMR0SEL_EXT 0x00000300 #define NUMAKER_CLK_CLKSEL1_TMR0SEL_LIRC 0x00000500 #define NUMAKER_CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700 #define NUMAKER_CLK_CLKSEL1_TMR1SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL1_TMR1SEL_LXT 0x00001000 #define NUMAKER_CLK_CLKSEL1_TMR1SEL_PCLK0 0x00002000 #define NUMAKER_CLK_CLKSEL1_TMR1SEL_EXT 0x00003000 #define NUMAKER_CLK_CLKSEL1_TMR1SEL_LIRC 0x00005000 #define NUMAKER_CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000 #define NUMAKER_CLK_CLKSEL1_TMR2SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL1_TMR2SEL_LXT 0x00010000 #define NUMAKER_CLK_CLKSEL1_TMR2SEL_PCLK1 0x00020000 #define NUMAKER_CLK_CLKSEL1_TMR2SEL_EXT 0x00030000 #define NUMAKER_CLK_CLKSEL1_TMR2SEL_LIRC 0x00050000 #define NUMAKER_CLK_CLKSEL1_TMR2SEL_HIRC 0x00070000 #define NUMAKER_CLK_CLKSEL1_TMR3SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL1_TMR3SEL_LXT 0x00100000 #define NUMAKER_CLK_CLKSEL1_TMR3SEL_PCLK1 0x00200000 #define NUMAKER_CLK_CLKSEL1_TMR3SEL_EXT 0x00300000 #define NUMAKER_CLK_CLKSEL1_TMR3SEL_LIRC 0x00500000 #define NUMAKER_CLK_CLKSEL1_TMR3SEL_HIRC 0x00700000 #define NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 0x80000000 #define NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK0_DIV2048 0x80000000 #define NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC 0xC0000000 #define NUMAKER_CLK_CLKSEL2_EPWM0SEL_HCLK 0x00000000 #define NUMAKER_CLK_CLKSEL2_EPWM0SEL_HCLK0 0x00000000 #define NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 0x00000001 #define NUMAKER_CLK_CLKSEL2_EPWM1SEL_HCLK 0x00000000 #define NUMAKER_CLK_CLKSEL2_EPWM1SEL_HCLK0 0x00000000 #define NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 0x00000002 #define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PLL 0x00000004 #define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PCLK0 0x00000008 #define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HIRC 0x0000000C #define NUMAKER_CLK_CLKSEL2_SPI0SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL2_SPI0SEL_PLL 0x00000010 #define NUMAKER_CLK_CLKSEL2_SPI0SEL_PCLK1 0x00000020 #define NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0x00000030 #define NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC48M 0x00000040 #define NUMAKER_CLK_CLKSEL2_TKSEL_HIRC 0x00000000 #define NUMAKER_CLK_CLKSEL2_TKSEL_MIRC 0x00000080 #define NUMAKER_CLK_CLKSEL2_SPI1SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL2_SPI1SEL_PLL 0x00001000 #define NUMAKER_CLK_CLKSEL2_SPI1SEL_PCLK0 0x00002000 #define NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0x00003000 #define NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC48M 0x00004000 #define NUMAKER_CLK_CLKSEL3_PWM0SEL_HCLK 0x00000000 #define NUMAKER_CLK_CLKSEL3_PWM0SEL_HCLK0 0x00000000 #define NUMAKER_CLK_CLKSEL3_PWM0SEL_PCLK0 0x00000040 #define NUMAKER_CLK_CLKSEL3_PWM1SEL_HCLK 0x00000000 #define NUMAKER_CLK_CLKSEL3_PWM1SEL_HCLK0 0x00000000 #define NUMAKER_CLK_CLKSEL3_PWM1SEL_PCLK1 0x00000080 #define NUMAKER_CLK_CLKSEL3_SPI2SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL3_SPI2SEL_PLL 0x00000100 #define NUMAKER_CLK_CLKSEL3_SPI2SEL_PCLK1 0x00000200 #define NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0x00000300 #define NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC48M 0x00000400 #define NUMAKER_CLK_CLKSEL3_SPI3SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL3_SPI3SEL_PLL 0x00001000 #define NUMAKER_CLK_CLKSEL3_SPI3SEL_PCLK0 0x00002000 #define NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0x00003000 #define NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC48M 0x00004000 #define NUMAKER_CLK_CLKSEL4_UART0SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL4_UART0SEL_PLL 0x00000001 #define NUMAKER_CLK_CLKSEL4_UART0SEL_LXT 0x00000002 #define NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC 0x00000003 #define NUMAKER_CLK_CLKSEL4_UART0SEL_MIRC 0x00000004 #define NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC48M 0x00000005 #define NUMAKER_CLK_CLKSEL4_UART1SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL4_UART1SEL_PLL 0x00000010 #define NUMAKER_CLK_CLKSEL4_UART1SEL_LXT 0x00000020 #define NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC 0x00000030 #define NUMAKER_CLK_CLKSEL4_UART1SEL_MIRC 0x00000040 #define NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC48M 0x00000050 #define NUMAKER_CLK_CLKSEL4_UART2SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL4_UART2SEL_PLL 0x00000100 #define NUMAKER_CLK_CLKSEL4_UART2SEL_LXT 0x00000200 #define NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC 0x00000300 #define NUMAKER_CLK_CLKSEL4_UART2SEL_MIRC 0x00000400 #define NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC48M 0x00000500 #define NUMAKER_CLK_CLKSEL4_UART3SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL4_UART3SEL_PLL 0x00001000 #define NUMAKER_CLK_CLKSEL4_UART3SEL_LXT 0x00002000 #define NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC 0x00003000 #define NUMAKER_CLK_CLKSEL4_UART3SEL_MIRC 0x00004000 #define NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC48M 0x00005000 #define NUMAKER_CLK_CLKSEL4_UART4SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL4_UART4SEL_PLL 0x00010000 #define NUMAKER_CLK_CLKSEL4_UART4SEL_LXT 0x00020000 #define NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC 0x00030000 #define NUMAKER_CLK_CLKSEL4_UART4SEL_MIRC 0x00040000 #define NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC48M 0x00050000 #define NUMAKER_CLK_CLKSEL4_UART5SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL4_UART5SEL_PLL 0x00100000 #define NUMAKER_CLK_CLKSEL4_UART5SEL_LXT 0x00200000 #define NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC 0x00300000 #define NUMAKER_CLK_CLKSEL4_UART5SEL_MIRC 0x00400000 #define NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC48M 0x00500000 #define NUMAKER_CLK_CLKSEL4_UART6SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL4_UART6SEL_PLL 0x01000000 #define NUMAKER_CLK_CLKSEL4_UART6SEL_LXT 0x02000000 #define NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC 0x03000000 #define NUMAKER_CLK_CLKSEL4_UART6SEL_MIRC 0x04000000 #define NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC48M 0x05000000 #define NUMAKER_CLK_CLKSEL4_UART7SEL_HXT 0x00000000 #define NUMAKER_CLK_CLKSEL4_UART7SEL_PLL 0x10000000 #define NUMAKER_CLK_CLKSEL4_UART7SEL_LXT 0x20000000 #define NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC 0x30000000 #define NUMAKER_CLK_CLKSEL4_UART7SEL_MIRC 0x40000000 #define NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC48M 0x50000000 #define NUMAKER_CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << (0)) #define NUMAKER_CLK_CLKDIV0_HCLK0(x) (((x) - 1UL) << (0)) #define NUMAKER_CLK_CLKDIV0_USB(x) (((x) - 1UL) << (4)) #define NUMAKER_CLK_CLKDIV0_UART0(x) (((x) - 1UL) << (8)) #define NUMAKER_CLK_CLKDIV0_UART1(x) (((x) - 1UL) << (12)) #define NUMAKER_CLK_CLKDIV0_EADC0(x) (((x) - 1UL) << (16)) #define NUMAKER_CLK_CLKDIV4_UART2(x) (((x) - 1UL) << (0)) #define NUMAKER_CLK_CLKDIV4_UART3(x) (((x) - 1UL) << (4)) #define NUMAKER_CLK_CLKDIV4_UART4(x) (((x) - 1UL) << (8)) #define NUMAKER_CLK_CLKDIV4_UART5(x) (((x) - 1UL) << (12)) #define NUMAKER_CLK_CLKDIV4_UART6(x) (((x) - 1UL) << (16)) #define NUMAKER_CLK_CLKDIV4_UART7(x) (((x) - 1UL) << (20)) #define NUMAKER_CLK_CLKDIV5_CANFD0(x) (((x) - 1UL) << (0)) #define NUMAKER_CLK_CLKDIV5_CANFD1(x) (((x) - 1UL) << (4)) #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV1 0x00000000 #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 0x00000001 #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV4 0x00000002 #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV8 0x00000003 #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV16 0x00000004 #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV1 0x00000000 #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2 0x00000010 #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV4 0x00000020 #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV8 0x00000030 #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV16 0x00000040 #define NUMAKER_PDMA0_MODULE 0x00000001 #define NUMAKER_ISP_MODULE 0x00000002 #define NUMAKER_EBI_MODULE 0x00000003 #define NUMAKER_ST_MODULE 0x018C0004 #define NUMAKER_CRC_MODULE 0x00000007 #define NUMAKER_CRPT_MODULE 0x0000000C #define NUMAKER_KS_MODULE 0x0000000D #define NUMAKER_USBH_MODULE 0x00A01090 #define NUMAKER_GPA_MODULE 0x00000018 #define NUMAKER_GPB_MODULE 0x00000019 #define NUMAKER_GPC_MODULE 0x0000001A #define NUMAKER_GPD_MODULE 0x0000001B #define NUMAKER_GPE_MODULE 0x0000001C #define NUMAKER_GPF_MODULE 0x0000001D #define NUMAKER_GPG_MODULE 0x0000001E #define NUMAKER_GPH_MODULE 0x0000001F #define NUMAKER_RTC_MODULE 0x20000001 #define NUMAKER_TMR0_MODULE 0x25A00002 #define NUMAKER_TMR1_MODULE 0x25B00003 #define NUMAKER_TMR2_MODULE 0x25C00004 #define NUMAKER_TMR3_MODULE 0x25D00005 #define NUMAKER_CLKO_MODULE 0x26100006 #define NUMAKER_ACMP01_MODULE 0x20000007 #define NUMAKER_I2C0_MODULE 0x20000008 #define NUMAKER_I2C1_MODULE 0x20000009 #define NUMAKER_I2C2_MODULE 0x2000000A #define NUMAKER_I2C3_MODULE 0x2000000B #define NUMAKER_QSPI0_MODULE 0x2908000C #define NUMAKER_SPI0_MODULE 0x2990000D #define NUMAKER_SPI1_MODULE 0x29B0000E #define NUMAKER_SPI2_MODULE 0x2DA0000F #define NUMAKER_UART0_MODULE 0x31801110 #define NUMAKER_UART1_MODULE 0x31901191 #define NUMAKER_UART2_MODULE 0x31A11012 #define NUMAKER_UART3_MODULE 0x31B11093 #define NUMAKER_UART4_MODULE 0x31C11114 #define NUMAKER_UART5_MODULE 0x31D11195 #define NUMAKER_UART6_MODULE 0x31E11216 #define NUMAKER_UART7_MODULE 0x31F11297 #define NUMAKER_OTG_MODULE 0x2000001A #define NUMAKER_USBD_MODULE 0x20A0109B #define NUMAKER_EADC0_MODULE 0x2128221C #define NUMAKER_TRNG_MODULE 0x2000001F #define NUMAKER_SPI3_MODULE 0x4DB00006 #define NUMAKER_USCI0_MODULE 0x40000008 #define NUMAKER_USCI1_MODULE 0x40000009 #define NUMAKER_WWDT_MODULE 0x4578000B #define NUMAKER_DAC_MODULE 0x4000000C #define NUMAKER_EPWM0_MODULE 0x48800010 #define NUMAKER_EPWM1_MODULE 0x48840011 #define NUMAKER_EQEI0_MODULE 0x40000016 #define NUMAKER_EQEI1_MODULE 0x40000017 #define NUMAKER_TK_MODULE 0x489C0019 #define NUMAKER_ECAP0_MODULE 0x4000001A #define NUMAKER_ECAP1_MODULE 0x4000001B #define NUMAKER_ACMP2_MODULE 0x60000007 #define NUMAKER_PWM0_MODULE 0x6C980008 #define NUMAKER_PWM1_MODULE 0x6C9C0009 #define NUMAKER_UTCPD0_MODULE 0x6000000F #define NUMAKER_CANRAM0_MODULE 0x80000010 #define NUMAKER_CANRAM1_MODULE 0x80000011 #define NUMAKER_CANFD0_MODULE 0x81621014 #define NUMAKER_CANFD1_MODULE 0x816A1095 #define NUMAKER_HCLK1_MODULE 0x81B3101C #define NUMAKER_LPPDMA0_MODULE 0xA0000000 #define NUMAKER_LPGPIO_MODULE 0xA0000001 #define NUMAKER_LPSRAM_MODULE 0xA0000002 #define NUMAKER_WDT_MODULE 0xB5600010 #define NUMAKER_LPSPI0_MODULE 0xB5080011 #define NUMAKER_LPI2C0_MODULE 0xA0000012 #define NUMAKER_LPUART0_MODULE 0xB5031113 #define NUMAKER_LPTMR0_MODULE 0xB5A00014 #define NUMAKER_LPTMR1_MODULE 0xB5B00015 #define NUMAKER_TTMR0_MODULE 0xB5100016 #define NUMAKER_TTMR1_MODULE 0xB5180017 #define NUMAKER_LPADC0_MODULE 0xB5431218 #define NUMAKER_OPA_MODULE 0xA000001B #define NUMAKER_CLK_PMUCTL_PDMSEL_PD 0x00000000 #define NUMAKER_CLK_PMUCTL_PDMSEL_NPD0 0x00000000 #define NUMAKER_CLK_PMUCTL_PDMSEL_NPD1 0x00000001 #define NUMAKER_CLK_PMUCTL_PDMSEL_NPD2 0x00000002 #define NUMAKER_CLK_PMUCTL_PDMSEL_NPD3 0x00000003 #define NUMAKER_CLK_PMUCTL_PDMSEL_NPD4 0x00000004 #define NUMAKER_CLK_PMUCTL_PDMSEL_NPD5 0x00000005 #define NUMAKER_CLK_PMUCTL_PDMSEL_SPD0 0x00000008 #define NUMAKER_CLK_PMUCTL_PDMSEL_SPD1 0x00000009 #define NUMAKER_CLK_PMUCTL_PDMSEL_SPD2 0x0000000A #define NUMAKER_CLK_PMUCTL_PDMSEL_DPD0 0x0000000C #define NUMAKER_CLK_PMUCTL_PDMSEL_DPD1 0x0000000D #endif ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
5,093
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_ #include "gd32-clocks-common.h" /** * @name Register offsets * @{ */ #define GD32_AHB1EN_OFFSET 0x30U #define GD32_AHB2EN_OFFSET 0x34U #define GD32_AHB3EN_OFFSET 0x38U #define GD32_APB1EN_OFFSET 0x40U #define GD32_APB2EN_OFFSET 0x44U #define GD32_ADDAPB1EN_OFFSET 0xE4U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB1 peripherals */ #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 0U) #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 1U) #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 2U) #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHB1EN, 3U) #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHB1EN, 4U) #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB1EN, 5U) #define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(AHB1EN, 6U) #define GD32_CLOCK_GPIOH GD32_CLOCK_CONFIG(AHB1EN, 7U) #define GD32_CLOCK_GPIOI GD32_CLOCK_CONFIG(AHB1EN, 8U) #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHB1EN, 12U) #define GD32_CLOCK_BKPSRAM GD32_CLOCK_CONFIG(AHB1EN, 18U) #define GD32_CLOCK_TCMSRAM GD32_CLOCK_CONFIG(AHB1EN, 20U) #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHB1EN, 21U) #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHB1EN, 22U) #define GD32_CLOCK_IPA GD32_CLOCK_CONFIG(AHB1EN, 23U) #define GD32_CLOCK_ENET GD32_CLOCK_CONFIG(AHB1EN, 25U) #define GD32_CLOCK_ENETTX GD32_CLOCK_CONFIG(AHB1EN, 26U) #define GD32_CLOCK_ENETRX GD32_CLOCK_CONFIG(AHB1EN, 27U) #define GD32_CLOCK_ENETPTP GD32_CLOCK_CONFIG(AHB1EN, 28U) #define GD32_CLOCK_USBHS GD32_CLOCK_CONFIG(AHB1EN, 29U) #define GD32_CLOCK_USBHSULPI GD32_CLOCK_CONFIG(AHB1EN, 30U) /* AHB2 peripherals */ #define GD32_CLOCK_DCI GD32_CLOCK_CONFIG(AHB2EN, 0U) #define GD32_CLOCK_TRNG GD32_CLOCK_CONFIG(AHB2EN, 6U) #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHB2EN, 7U) /* AHB3 peripherals */ #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHB3EN, 0U) /* APB1 peripherals */ #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U) #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U) #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U) #define GD32_CLOCK_TIMER4 GD32_CLOCK_CONFIG(APB1EN, 3U) #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) #define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U) #define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U) #define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U) #define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U) #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) #define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U) #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) #define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U) #define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U) #define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U) #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) #define GD32_CLOCK_I2C2 GD32_CLOCK_CONFIG(APB1EN, 23U) #define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U) #define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U) #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) #define GD32_CLOCK_UART6 GD32_CLOCK_CONFIG(APB1EN, 30U) #define GD32_CLOCK_UART7 GD32_CLOCK_CONFIG(APB1EN, 31U) #define GD32_CLOCK_RTC GD32_CLOCK_CONFIG(BDCTL, 15U) /* APB2 peripherals */ #define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 0U) #define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 1U) #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 4U) #define GD32_CLOCK_USART5 GD32_CLOCK_CONFIG(APB2EN, 5U) #define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 8U) #define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 9U) #define GD32_CLOCK_ADC2 GD32_CLOCK_CONFIG(APB2EN, 10U) #define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(APB2EN, 11U) #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) #define GD32_CLOCK_SPI3 GD32_CLOCK_CONFIG(APB2EN, 13U) #define GD32_CLOCK_SYSCFG GD32_CLOCK_CONFIG(APB2EN, 14U) #define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 16U) #define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 17U) #define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 18U) #define GD32_CLOCK_SPI4 GD32_CLOCK_CONFIG(APB2EN, 20U) #define GD32_CLOCK_SPI5 GD32_CLOCK_CONFIG(APB2EN, 21U) #define GD32_CLOCK_TLI GD32_CLOCK_CONFIG(APB2EN, 26U) /* APB1 additional peripherals */ #define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U) #define GD32_CLOCK_IREF GD32_CLOCK_CONFIG(ADDAPB1EN, 31U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/gd32f4xx-clocks.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,646
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ #include "stm32_common_clocks.h" /** Domain clocks */ /* RM0481/0492, Table 47 Kernel clock distribution summary */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSE (STM32_SRC_LSI + 1) #define STM32_SRC_CSI (STM32_SRC_HSE + 1) #define STM32_SRC_HSI (STM32_SRC_CSI + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) /** PLL outputs */ #define STM32_SRC_PLL1_P (STM32_SRC_HSI48 + 1) #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1) #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1) #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) /** Clock muxes */ #define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1) /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x088 #define STM32_CLOCK_BUS_AHB2 0x08C #define STM32_CLOCK_BUS_AHB4 0x094 #define STM32_CLOCK_BUS_APB1 0x09c #define STM32_CLOCK_BUS_APB1_2 0x0A0 #define STM32_CLOCK_BUS_APB2 0x0A4 #define STM32_CLOCK_BUS_APB3 0x0A8 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32H5 clock configuration bit field. * * - reg (1/2/3/4/5) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPRx register offset (RM0456.pdf) */ #define CCIPR1_REG 0xD8 #define CCIPR2_REG 0xDC #define CCIPR3_REG 0xE0 #define CCIPR4_REG 0xE4 #define CCIPR5_REG 0xE8 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0xF0 /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ #define USART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR1_REG) #define USART2_SEL(val) STM32_CLOCK(val, 7, 3, CCIPR1_REG) #define USART3_SEL(val) STM32_CLOCK(val, 7, 6, CCIPR1_REG) #define USART4_SEL(val) STM32_CLOCK(val, 7, 9, CCIPR1_REG) #define USART5_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR1_REG) #define USART6_SEL(val) STM32_CLOCK(val, 7, 15, CCIPR1_REG) #define USART7_SEL(val) STM32_CLOCK(val, 7, 18, CCIPR1_REG) #define USART8_SEL(val) STM32_CLOCK(val, 7, 21, CCIPR1_REG) #define USART9_SEL(val) STM32_CLOCK(val, 7, 24, CCIPR1_REG) #define USART10_SEL(val) STM32_CLOCK(val, 7, 27, CCIPR1_REG) #define TIMIC_SEL(val) STM32_CLOCK(val, 1, 31, CCIPR1_REG) /** CCIPR2 devices */ #define USART11_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR2_REG) #define USART12_SEL(val) STM32_CLOCK(val, 7, 4, CCIPR2_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR2_REG) #define LPTIM3_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR2_REG) #define LPTIM4_SEL(val) STM32_CLOCK(val, 7, 20, CCIPR2_REG) #define LPTIM5_SEL(val) STM32_CLOCK(val, 7, 24, CCIPR2_REG) #define LPTIM6_SEL(val) STM32_CLOCK(val, 7, 28, CCIPR2_REG) /** CCIPR3 devices */ #define SPI1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR3_REG) #define SPI2_SEL(val) STM32_CLOCK(val, 7, 3, CCIPR3_REG) #define SPI3_SEL(val) STM32_CLOCK(val, 7, 6, CCIPR3_REG) #define SPI4_SEL(val) STM32_CLOCK(val, 7, 9, CCIPR3_REG) #define SPI5_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG) #define SPI6_SEL(val) STM32_CLOCK(val, 7, 15, CCIPR2_REG) #define LPUART1_SEL(val) STM32_CLOCK(val, 7, 24, CCIPR3_REG) /** CCIPR4 devices */ #define OCTOSPI1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR4_REG) #define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR4_REG) #define USB_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR4_REG) #define SDMMC1_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR4_REG) #define SDMMC2_SEL(val) STM32_CLOCK(val, 1, 7, CCIPR4_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR4_REG) #define I2C2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR4_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR4_REG) #define I2C4_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR4_REG) #define I3C1_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR4_REG) /** CCIPR5 devices */ #define ADCDAC_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR5_REG) #define DAC_SEL(val) STM32_CLOCK(val, 1, 3, CCIPR5_REG) #define RNG_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR5_REG) #define CEC_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR5_REG) #define FDCAN_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR5_REG) #define SAI1_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR5_REG) #define SAI2_SEL(val) STM32_CLOCK(val, 7, 19, CCIPR5_REG) #define CKPER_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR5_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32h5_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
2,160
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_ /** @brief RCC_DCKCFGR register offset */ #define DCKCFGR_REG 0x8C /** @brief Device domain clocks selection helpers */ /** DCKCFGR devices */ #define CKDFSDM2A_SEL(val) STM32_CLOCK(val, 1, 14, DCKCFGR_REG) #define CKDFSDM1A_SEL(val) STM32_CLOCK(val, 1, 15, DCKCFGR_REG) #define SAI1A_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR_REG) #define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG) #define CLK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR_REG) #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR_REG) #define DSI_SEL(val) STM32_CLOCK(val, 1, 29, DCKCFGR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f427_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
286
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_ /* PLL 32KHz clock source VTR rail ON. */ #define MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC 0U #define MCHP_XEC_PLL_CLK32K_SRC_XTAL 1U #define MCHP_XEC_PLL_CLK32K_SRC_PIN 2U /* Peripheral 32KHz clock source for VTR rail ON and off(VBAT operation) */ #define MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO 0U #define MCHP_XEC_PERIPH_CLK32K_SRC_XTAL_XTAL 1U #define MCHP_XEC_PERIPH_CLK32K_SRC_PIN_SO 2U #define MCHP_XEC_PERIPH_CLK32K_SRC_PIN_XTAL 3U /* clocks supported by the driver */ #define MCHP_XEC_PCR_CLK_CORE 0 #define MCHP_XEC_PCR_CLK_CPU 1 #define MCHP_XEC_PCR_CLK_BUS 2 #define MCHP_XEC_PCR_CLK_PERIPH 3 #define MCHP_XEC_PCR_CLK_PERIPH_FAST 4 #define MCHP_XEC_PCR_CLK_PERIPH_SLOW 5 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/mchp_xec_pcr.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
322
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ #include "stm32_common_clocks.h" /** Domain clocks */ /* RM0468, Table 56 Kernel clock distribution summary */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ #define STM32_SRC_HSE (STM32_SRC_LSI + 1) #define STM32_SRC_HSI16 (STM32_SRC_HSE + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1) #define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1) #define STM32_SRC_MSIK (STM32_SRC_MSIS + 1) /** PLL outputs */ #define STM32_SRC_PLL1_P (STM32_SRC_MSIK + 1) #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1) #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1) #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) /** Clock muxes */ /* #define STM32_SRC_ICLK TBD */ /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x088 #define STM32_CLOCK_BUS_AHB2 0x08C #define STM32_CLOCK_BUS_AHB2_2 0x090 #define STM32_CLOCK_BUS_AHB3 0x094 #define STM32_CLOCK_BUS_APB1 0x09C #define STM32_CLOCK_BUS_APB1_2 0x0A0 #define STM32_CLOCK_BUS_APB2 0x0A4 #define STM32_CLOCK_BUS_APB3 0x0A8 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32U5 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPRx register offset (RM0456.pdf) */ #define CCIPR1_REG 0xE0 #define CCIPR2_REG 0xE4 #define CCIPR3_REG 0xE8 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0xF0 /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG) #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR1_REG) #define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR1_REG) #define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR1_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG) #define I2C2_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR1_REG) #define I2C4_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR1_REG) #define SPI2_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR1_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR1_REG) #define SPI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR1_REG) #define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR1_REG) #define FDCAN1_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR1_REG) #define ICKLK_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR1_REG) #define TIMIC_SEL(val) STM32_CLOCK(val, 7, 29, CCIPR1_REG) /** CCIPR2 devices */ #define MDF1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR2_REG) #define SAI1_SEL(val) STM32_CLOCK(val, 7, 5, CCIPR2_REG) #define SAI2_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG) #define SAE_SEL(val) STM32_CLOCK(val, 1, 11, CCIPR2_REG) #define RNG_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG) #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG) #define DSIHOST_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR2_REG) #define USART6_SEL(val) STM32_CLOCK(val, 1, 16, CCIPR2_REG) #define LTDC_SEL(val) STM32_CLOCK(val, 1, 18, CCIPR2_REG) #define OCTOSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG) #define HSPI_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR2_REG) #define I2C5_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR2_REG) #define I2C6_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR2_REG) #define USBPHYC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR2_REG) /** CCIPR3 devices */ #define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR3_REG) #define SPI3_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR3_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR3_REG) #define LPTIM34_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR3_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR3_REG) #define ADCDAC_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG) #define DAC1_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR3_REG) #define ADF1_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR3_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32u5_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,957
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ /** @brief RCC_DCKCFGR register offset */ #define DCKCFGR_REG 0x8C #define DCKCFGR2_REG 0x94 /** @brief Device domain clocks selection helpers */ /** DCKCFGR devices */ #define CKDFSDM2A_SEL(val) STM32_CLOCK(val, 1, 14, DCKCFGR_REG) #define CKDFSDM1A_SEL(val) STM32_CLOCK(val, 1, 15, DCKCFGR_REG) #define SAI1A_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR_REG) #define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG) #define I2S1_SEL(val) STM32_CLOCK(val, 3, 25, DCKCFGR_REG) #define I2S2_SEL(val) STM32_CLOCK(val, 3, 27, DCKCFGR_REG) #define CKDFSDM_SEL(val) STM32_CLOCK(val, 1, 31, DCKCFGR_REG) /** DCKCFGR2 devices */ #define I2CFMP1_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG) #define CK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR2_REG) #define SDIO_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR2_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 30, DCKCFGR2_REG) /* F4 generic I2S_SEL is not compatible with F410 devices */ #ifdef I2S_SEL #undef I2S_SEL #endif #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f410_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
450
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ #include "stm32_common_clocks.h" /** Domain clocks */ /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x014 #define STM32_CLOCK_BUS_APB2 0x018 #define STM32_CLOCK_BUS_APB1 0x01c #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) #define STM32_SRC_HSE (STM32_SRC_HSI + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CFGRx register offset * @param shift Position within RCC_CFGRx. * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CFGR2 register offset */ #define CFGR2_REG 0x2C /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x20 /** @brief Device domain clocks selection helpers */ /** CFGR2 devices */ #define I2S2_SEL(val) STM32_CLOCK(val, 1, 17, CFGR2_REG) #define I2S3_SEL(val) STM32_CLOCK(val, 1, 18, CFGR2_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f1_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
689
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ #include "stm32_common_clocks.h" /** Peripheral clock sources */ /* RM0493, Figure 30, clock tree */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSE (STM32_SRC_LSI + 1) #define STM32_SRC_HSI16 (STM32_SRC_HSE + 1) /** PLL outputs */ #define STM32_SRC_PLL1_P (STM32_SRC_HSI16 + 1) #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) #define STM32_SRC_CLOCK_MIN STM32_SRC_PLL1_P #define STM32_SRC_CLOCK_MAX STM32_SRC_SYSCLK /** Bus clocks (Register address offsets) */ #define STM32_CLOCK_BUS_AHB1 0x088 #define STM32_CLOCK_BUS_AHB2 0x08C #define STM32_CLOCK_BUS_AHB4 0x094 #define STM32_CLOCK_BUS_AHB5 0x098 #define STM32_CLOCK_BUS_APB1 0x09C #define STM32_CLOCK_BUS_APB1_2 0x0A0 #define STM32_CLOCK_BUS_APB2 0x0A4 #define STM32_CLOCK_BUS_APB7 0x0A8 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB7 /** * @brief STM32WBA clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPRx register offset (RM0493.pdf) */ #define CCIPR1_REG 0xE0 #define CCIPR2_REG 0xE4 #define CCIPR3_REG 0xE8 /** @brief RCC_BCDR1 register offset (RM0493.pdf) */ #define BCDR1_REG 0xF0 /** @brief Device clk sources selection helpers */ /** CCIPR1 devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR1_REG) #define SPI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR1_REG) #define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR1_REG) #define TIMIC_SEL(val) STM32_CLOCK(val, 1, 31, CCIPR1_REG) /** CCIPR2 devices */ #define RNG_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG) /** CCIPR3 devices */ #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR3_REG) #define SPI3_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR3_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR3_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR3_REG) #define ADC_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG) /** BCDR1 devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BCDR1_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32wba_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,205
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus gatting clocks */ #define STM32_CLOCK_BUS_AHB1 0x014 #define STM32_CLOCK_BUS_APB2 0x018 #define STM32_CLOCK_BUS_APB1 0x01c #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 /** Domain clocks */ /* RM0316, 9.4.13 Clock configuration register (RCC_CFGR3) */ /** System clock */ /* Defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) /* #define STM32_SRC_HSI48 TDB */ /** Bus clock */ #define STM32_SRC_PCLK (STM32_SRC_HSI + 1) /** PLL clock */ #define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CFGRx register offset * @param shift Position within RCC_CFGRx. * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CFGRx register offset */ #define CFGR_REG 0x04 #define CFGR3_REG 0x30 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x20 /** @brief Device domain clocks selection helpers) */ /** CFGR devices */ #define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) /** CFGR3 devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG) #define I2C2_SEL(val) STM32_CLOCK(val, 1, 5, CFGR3_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG) #define TIM1_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG) #define TIM8_SEL(val) STM32_CLOCK(val, 1, 9, CFGR3_REG) #define TIM15_SEL(val) STM32_CLOCK(val, 1, 10, CFGR3_REG) #define TIM16_SEL(val) STM32_CLOCK(val, 1, 11, CFGR3_REG) #define TIM17_SEL(val) STM32_CLOCK(val, 1, 13, CFGR3_REG) #define TIM20_SEL(val) STM32_CLOCK(val, 1, 15, CFGR3_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG) #define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG) #define USART4_SEL(val) STM32_CLOCK(val, 3, 20, CFGR3_REG) #define USART5_SEL(val) STM32_CLOCK(val, 3, 22, CFGR3_REG) #define TIM2_SEL(val) STM32_CLOCK(val, 1, 24, CFGR3_REG) #define TIM3_4_SEL(val) STM32_CLOCK(val, 1, 25, CFGR3_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32f3_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,130
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ #include "stm32_common_clocks.h" /** Domain clocks */ /* RM0468, Table 56 Kernel clock dictribution summary */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSE (STM32_SRC_LSI + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSE + 1) #define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */ #define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1) /* CSI + CSIKERON */ /** PLL outputs */ #define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1) #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1) #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1) #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) /** Clock muxes */ #define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1) /** Others: Not yet supported */ /* #define STM32_SRC_I2SCKIN TBD */ /* #define STM32_SRC_SPDIFRX TBD */ /** Bus clocks */ #define STM32_CLOCK_BUS_AHB3 0x0D4 #define STM32_CLOCK_BUS_AHB1 0x0D8 #define STM32_CLOCK_BUS_AHB2 0x0DC #define STM32_CLOCK_BUS_AHB4 0x0E0 #define STM32_CLOCK_BUS_APB3 0x0E4 #define STM32_CLOCK_BUS_APB1 0x0E8 #define STM32_CLOCK_BUS_APB1_2 0x0EC #define STM32_CLOCK_BUS_APB2 0x0F0 #define STM32_CLOCK_BUS_APB4 0x0F4 /** Alias D1/2/3 domains clocks */ /* TBD: To remove ? */ #define STM32_SRC_PCLK1 STM32_CLOCK_BUS_APB1 #define STM32_SRC_PCLK2 STM32_CLOCK_BUS_APB2 #define STM32_SRC_HCLK3 STM32_CLOCK_BUS_AHB3 #define STM32_SRC_PCLK3 STM32_CLOCK_BUS_APB3 #define STM32_SRC_PCLK4 STM32_CLOCK_BUS_APB4 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4 #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32H7 clock configuration bit field. * * - reg (0/1) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..3) [ 16 : 18 ] * * @param reg RCC_DxCCIP register offset * @param shift Position within RCC_DxCCIP. * @param mask Mask for the RCC_DxCCIP field. * @param val Clock value (0, 1, 2 or 3). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_DxCCIP register offset (RM0399.pdf) */ #define D1CCIPR_REG 0x4C #define D2CCIP1R_REG 0x50 #define D2CCIP2R_REG 0x54 #define D3CCIPR_REG 0x58 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x70 /** @brief Device domain clocks selection helpers (RM0399.pdf) */ /** D1CCIPR devices */ #define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG) #define QSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG) #define DSI_SEL(val) STM32_CLOCK(val, 1, 8, D1CCIPR_REG) #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 16, D1CCIPR_REG) #define CKPER_SEL(val) STM32_CLOCK(val, 3, 28, D1CCIPR_REG) /* Device domain clocks selection helpers (RM0468.pdf) */ #define OSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG) /** D2CCIP1R devices */ #define SAI1_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP1R_REG) #define SAI23_SEL(val) STM32_CLOCK(val, 7, 6, D2CCIP1R_REG) #define SPI123_SEL(val) STM32_CLOCK(val, 7, 12, D2CCIP1R_REG) #define SPI45_SEL(val) STM32_CLOCK(val, 7, 16, D2CCIP1R_REG) #define SPDIF_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP1R_REG) #define DFSDM1_SEL(val) STM32_CLOCK(val, 1, 24, D2CCIP1R_REG) #define FDCAN_SEL(val) STM32_CLOCK(val, 3, 28, D2CCIP1R_REG) #define SWP_SEL(val) STM32_CLOCK(val, 1, 31, D2CCIP1R_REG) /** D2CCIP2R devices */ #define USART2345678_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP2R_REG) #define USART16_SEL(val) STM32_CLOCK(val, 7, 3, D2CCIP2R_REG) #define RNG_SEL(val) STM32_CLOCK(val, 3, 8, D2CCIP2R_REG) #define I2C123_SEL(val) STM32_CLOCK(val, 3, 12, D2CCIP2R_REG) #define USB_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP2R_REG) #define CEC_SEL(val) STM32_CLOCK(val, 3, 22, D2CCIP2R_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 7, 28, D2CCIP2R_REG) /** D3CCIPR devices */ #define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, D3CCIPR_REG) #define I2C4_SEL(val) STM32_CLOCK(val, 3, 8, D3CCIPR_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 7, 10, D3CCIPR_REG) #define LPTIM345_SEL(val) STM32_CLOCK(val, 7, 13, D3CCIPR_REG) #define ADC_SEL(val) STM32_CLOCK(val, 3, 16, D3CCIPR_REG) #define SAI4A_SEL(val) STM32_CLOCK(val, 7, 21, D3CCIPR_REG) #define SAI4B_SEL(val) STM32_CLOCK(val, 7, 24, D3CCIPR_REG) #define SPI6_SEL(val) STM32_CLOCK(val, 7, 28, D3CCIPR_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32h7_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
2,019
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus clocks */ #define STM32_CLOCK_BUS_IOP 0x034 #define STM32_CLOCK_BUS_AHB1 0x038 #define STM32_CLOCK_BUS_APB1 0x03c #define STM32_CLOCK_BUS_APB1_2 0x040 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2 /** Domain clocks */ /* RM0490, 5.4.21/22 Clock configuration register (RCC_CCIPRx) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI48 (STM32_SRC_LSI + 1) #define STM32_SRC_HSE (STM32_SRC_HSI48 + 1) /** Peripheral bus clock */ #define STM32_SRC_PCLK (STM32_SRC_HSE + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPR register offset */ #define CCIPR_REG 0x54 /** @brief RCC_CSR1 register offset */ #define CSR1_REG 0x5C /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) #define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) #define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) /** CSR1 devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, CSR1_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32c0_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
801
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_ /* Supported CPU clock Sources */ #define ESP32_CPU_CLK_SRC_XTAL 0U #define ESP32_CPU_CLK_SRC_PLL 1U #define ESP32_CLK_SRC_RC_FAST 2U /* Supported CPU frequencies */ #define ESP32_CLK_CPU_PLL_80M 80000000 #define ESP32_CLK_CPU_PLL_160M 160000000 #define ESP32_CLK_CPU_RC_FAST_FREQ 17500000 /* Supported XTAL Frequencies */ #define ESP32_CLK_XTAL_32M 32000000 #define ESP32_CLK_XTAL_40M 40000000 /* Supported RTC fast clock sources */ #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 0 #define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 1 /* Supported RTC slow clock frequencies */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 #define ESP32_RTC_SLOW_CLK_SRC_RC32K 2 #define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 /* RTC slow clock frequencies */ #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000 #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 #define ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ 32768 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. * These IDs shouldn't be changed unless there is a Hardware change * from Espressif. * * Basic Modules * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG */ #define ESP32_LEDC_MODULE 0 #define ESP32_UART0_MODULE 1 #define ESP32_UART1_MODULE 2 #define ESP32_USB_MODULE 3 #define ESP32_I2C0_MODULE 4 #define ESP32_I2S1_MODULE 5 #define ESP32_TIMG0_MODULE 6 #define ESP32_TIMG1_MODULE 7 #define ESP32_UHCI0_MODULE 8 #define ESP32_RMT_MODULE 9 #define ESP32_PCNT_MODULE 10 #define ESP32_SPI_MODULE 11 #define ESP32_SPI2_MODULE 12 #define ESP32_TWAI0_MODULE 13 #define ESP32_TWAI1_MODULE 14 #define ESP32_RNG_MODULE 15 #define ESP32_RSA_MODULE 16 #define ESP32_AES_MODULE 17 #define ESP32_SHA_MODULE 18 #define ESP32_ECC_MODULE 19 #define ESP32_HMAC_MODULE 20 #define ESP32_DS_MODULE 21 #define ESP32_SDIO_SLAVE_MODULE 22 #define ESP32_GDMA_MODULE 23 #define ESP32_MCPWM0_MODULE 24 #define ESP32_ETM_MODULE 25 #define ESP32_PARLIO_MODULE 26 #define ESP32_SYSTIMER_MODULE 27 #define ESP32_SARADC_MODULE 28 #define ESP32_TEMPSENSOR_MODULE 29 #define ESP32_REGDMA_MODULE 30 #define ESP32_LP_I2C0_MODULE 31 /* Peripherals clock managed by the modem_clock driver must be listed last */ #define ESP32_WIFI_MODULE 32 #define ESP32_BT_MODULE 33 #define ESP32_IEEE802154_MODULE 34 #define ESP32_COEX_MODULE 35 #define ESP32_PHY_MODULE 36 #define ESP32_MODULE_MAX 37 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/esp32c6_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
819
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ADI_MAX32_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ADI_MAX32_CLOCK_H_ /** Peripheral clock register */ #define ADI_MAX32_CLOCK_BUS0 0 #define ADI_MAX32_CLOCK_BUS1 1 #define ADI_MAX32_CLOCK_BUS2 2 /** Clock source for peripheral interfaces like UART, WDT... */ #define ADI_MAX32_PRPH_CLK_SRC_PCLK 0 /* Peripheral clock */ #define ADI_MAX32_PRPH_CLK_SRC_EXTCLK 1 /* External clock */ #define ADI_MAX32_PRPH_CLK_SRC_IBRO 2 /* Internal Baud Rate Oscillator*/ #define ADI_MAX32_PRPH_CLK_SRC_ERFO 3 /* External RF Oscillator */ #define ADI_MAX32_PRPH_CLK_SRC_ERTCO 4 /* External RTC Oscillator */ #define ADI_MAX32_PRPH_CLK_SRC_INRO 5 /* Internal Nano Ring Oscillator */ #define ADI_MAX32_PRPH_CLK_SRC_ISO 6 /* Internal Secondary Oscillator */ #define ADI_MAX32_PRPH_CLK_SRC_IBRO_DIV8 7 /* IBRO/8 */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ADI_MAX32_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/adi_max32_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
268
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_ #include "gd32-clocks-common.h" /** * @name Register offsets * @{ */ #define GD32_AHBEN_OFFSET 0x14U #define GD32_APB1EN_OFFSET 0x1CU #define GD32_APB2EN_OFFSET 0x18U #define GD32_ADDAPB1EN_OFFSET 0xF8U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB peripherals */ #define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHBEN, 0U) #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U) #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U) #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U) #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U) #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U) #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHBEN, 18U) #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHBEN, 19U) #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHBEN, 20U) #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHBEN, 22U) #define GD32_CLOCK_TSI GD32_CLOCK_CONFIG(AHBEN, 24U) /* APB1 peripherals */ #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U) #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U) #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) #define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U) #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) #define GD32_CLOCK_CEC GD32_CLOCK_CONFIG(APB1EN, 30U) /* APB2 peripherals */ #define GD32_CLOCK_CFGCMP GD32_CLOCK_CONFIG(APB2EN, 0U) #define GD32_CLOCK_ADC GD32_CLOCK_CONFIG(APB2EN, 9U) #define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U) #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) #define GD32_CLOCK_TIMER14 GD32_CLOCK_CONFIG(APB2EN, 16U) #define GD32_CLOCK_TIMER15 GD32_CLOCK_CONFIG(APB2EN, 17U) #define GD32_CLOCK_TIMER16 GD32_CLOCK_CONFIG(APB2EN, 18U) /* APB1 additional peripherals */ #define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/gd32f3x0-clocks.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
824
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_ #include "renesas_cpg_mssr.h" /* r8a779f0 CPG Core Clocks */ #define R8A779F0_CLK_Z0 0 #define R8A779F0_CLK_Z1 1 #define R8A779F0_CLK_ZR 2 #define R8A779F0_CLK_ZX 3 #define R8A779F0_CLK_ZS 4 #define R8A779F0_CLK_ZT 5 #define R8A779F0_CLK_ZTR 6 #define R8A779F0_CLK_S0D2 7 #define R8A779F0_CLK_S0D3 8 #define R8A779F0_CLK_S0D4 9 #define R8A779F0_CLK_S0D2_MM 10 #define R8A779F0_CLK_S0D3_MM 11 #define R8A779F0_CLK_S0D4_MM 12 #define R8A779F0_CLK_S0D2_RT 13 #define R8A779F0_CLK_S0D3_RT 14 #define R8A779F0_CLK_S0D4_RT 15 #define R8A779F0_CLK_S0D6_RT 16 #define R8A779F0_CLK_S0D3_PER 17 #define R8A779F0_CLK_S0D6_PER 18 #define R8A779F0_CLK_S0D12_PER 19 #define R8A779F0_CLK_S0D24_PER 20 #define R8A779F0_CLK_S0D2_HSC 21 #define R8A779F0_CLK_S0D3_HSC 22 #define R8A779F0_CLK_S0D4_HSC 23 #define R8A779F0_CLK_S0D6_HSC 24 #define R8A779F0_CLK_S0D12_HSC 25 #define R8A779F0_CLK_S0D2_CC 26 #define R8A779F0_CLK_CL 27 #define R8A779F0_CLK_CL16M 28 #define R8A779F0_CLK_CL16M_MM 29 #define R8A779F0_CLK_CL16M_RT 30 #define R8A779F0_CLK_CL16M_PER 31 #define R8A779F0_CLK_CL16M_HSC 32 #define R8A779F0_CLK_ZB3 33 #define R8A779F0_CLK_ZB3D2 34 #define R8A779F0_CLK_ZB3D4 35 #define R8A779F0_CLK_SD0H 36 #define R8A779F0_CLK_SD0 37 #define R8A779F0_CLK_RPC 38 #define R8A779F0_CLK_RPCD2 39 #define R8A779F0_CLK_MSO 40 #define R8A779F0_CLK_POST 41 #define R8A779F0_CLK_POST2 42 #define R8A779F0_CLK_SASYNCRT 43 #define R8A779F0_CLK_SASYNCPERD1 44 #define R8A779F0_CLK_SASYNCPERD2 45 #define R8A779F0_CLK_SASYNCPERD4 46 #define R8A779F0_CLK_DBGSOC_HSC 47 #define R8A779F0_CLK_RSW2 48 #define R8A779F0_CLK_CPEX 49 #define R8A779F0_CLK_CBFUSA 50 #define R8A779F0_CLK_R 51 #define R8A779F0_CLK_OSC 52 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
936
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ #include "stm32_common_clocks.h" /** Bus clocks */ #define STM32_CLOCK_BUS_AHB1 0x048 #define STM32_CLOCK_BUS_AHB2 0x04c #define STM32_CLOCK_BUS_AHB3 0x050 #define STM32_CLOCK_BUS_APB1 0x058 #define STM32_CLOCK_BUS_APB1_2 0x05c #define STM32_CLOCK_BUS_APB2 0x060 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2 /** Domain clocks */ /* RM0440, Clock configuration register (RCC_CCIPRx) */ /** System clock */ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) #define STM32_SRC_HSE (STM32_SRC_HSI48 + 1) #define STM32_SRC_MSI (STM32_SRC_HSE + 1) /** Bus clock */ #define STM32_SRC_PCLK (STM32_SRC_MSI + 1) /** PLL clock outputs */ #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) /* TODO: PLLSAI clocks */ #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U /** * @brief STM32 clock configuration bit field. * * - reg (1/2/3) [ 0 : 7 ] * - shift (0..31) [ 8 : 12 ] * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] * - val (0..7) [ 16 : 18 ] * * @param reg RCC_CCIPRx register offset * @param shift Position within RCC_CCIPRx. * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ #define STM32_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CCIPR register offset */ #define CCIPR_REG 0x88 #define CCIPR2_REG 0x9C /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x90 /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG) #define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG) #define USART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) #define SAI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) #define I2S23_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG) #define FDCAN_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR_REG) #define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG) #define ADC12_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG) #define ADC34_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) /** CCIPR2 devices */ #define I2C4_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG) #define QSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/stm32g4_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,291
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ /* Note- clock identifiers in this file must be unique, * as the driver uses them in a switch case */ #define MCUX_LPC_CLK_ID(high, low) ((high << 8) | (low)) /* These IDs are used within SOC macros, and thus cannot be defined * using the standard MCUX_LPC_CLK_ID form */ #define MCUX_CTIMER0_CLK 0 #define MCUX_CTIMER1_CLK 1 #define MCUX_CTIMER2_CLK 2 #define MCUX_CTIMER3_CLK 3 #define MCUX_CTIMER4_CLK 4 #define MCUX_FLEXCOMM0_CLK MCUX_LPC_CLK_ID(0x01, 0x00) #define MCUX_FLEXCOMM1_CLK MCUX_LPC_CLK_ID(0x01, 0x01) #define MCUX_FLEXCOMM2_CLK MCUX_LPC_CLK_ID(0x01, 0x02) #define MCUX_FLEXCOMM3_CLK MCUX_LPC_CLK_ID(0x01, 0x03) #define MCUX_FLEXCOMM4_CLK MCUX_LPC_CLK_ID(0x01, 0x04) #define MCUX_FLEXCOMM5_CLK MCUX_LPC_CLK_ID(0x01, 0x05) #define MCUX_FLEXCOMM6_CLK MCUX_LPC_CLK_ID(0x01, 0x06) #define MCUX_FLEXCOMM7_CLK MCUX_LPC_CLK_ID(0x01, 0x07) #define MCUX_FLEXCOMM8_CLK MCUX_LPC_CLK_ID(0x01, 0x08) #define MCUX_FLEXCOMM9_CLK MCUX_LPC_CLK_ID(0x01, 0x09) #define MCUX_FLEXCOMM10_CLK MCUX_LPC_CLK_ID(0x01, 0x0A) #define MCUX_FLEXCOMM11_CLK MCUX_LPC_CLK_ID(0x01, 0x0B) #define MCUX_FLEXCOMM12_CLK MCUX_LPC_CLK_ID(0x01, 0x0C) #define MCUX_FLEXCOMM13_CLK MCUX_LPC_CLK_ID(0x01, 0x0D) #define MCUX_HS_SPI_CLK MCUX_LPC_CLK_ID(0x01, 0x0E) #define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK #define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F) #define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10) #define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00) #define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01) #define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00) #define MCUX_BUS_CLK MCUX_LPC_CLK_ID(0x04, 0x00) #define MCUX_SDIF_CLK MCUX_LPC_CLK_ID(0x05, 0x00) #define MCUX_I3C_CLK MCUX_LPC_CLK_ID(0x06, 0x00) #define MCUX_MIPI_DSI_DPHY_CLK MCUX_LPC_CLK_ID(0x07, 0x00) #define MCUX_MIPI_DSI_ESC_CLK MCUX_LPC_CLK_ID(0x07, 0x01) #define MCUX_LCDIF_PIXEL_CLK MCUX_LPC_CLK_ID(0x08, 0x00) #define MCUX_SCTIMER_CLK MCUX_LPC_CLK_ID(0x09, 0x00) #define MCUX_DMIC_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) #define MCUX_FLEXSPI_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) #define MCUX_FLEXSPI2_CLK MCUX_LPC_CLK_ID(0x0A, 0x01) #define MCUX_MRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x00) #define MCUX_FREEMRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x01) #define MCUX_PORT0_CLK MCUX_LPC_CLK_ID(0x0C, 0x00) #define MCUX_PORT1_CLK MCUX_LPC_CLK_ID(0x0C, 0x01) #define MCUX_PORT2_CLK MCUX_LPC_CLK_ID(0x0C, 0x02) #define MCUX_PORT3_CLK MCUX_LPC_CLK_ID(0x0C, 0x03) #define MCUX_PORT4_CLK MCUX_LPC_CLK_ID(0x0C, 0x04) #define MCUX_PORT5_CLK MCUX_LPC_CLK_ID(0x0C, 0x05) #define MCUX_ENET_QOS_CLK MCUX_LPC_CLK_ID(0x0D, 0x00) #define MCUX_ENET_CLK MCUX_LPC_CLK_ID(0x0D, 0x80) #define MCUX_ENET_PLL MCUX_LPC_CLK_ID(0x0D, 0x81) #define MCUX_LCDIC_CLK MCUX_LPC_CLK_ID(0x0E, 0x00) #define MCUX_LPADC1_CLK MCUX_LPC_CLK_ID(0x0F, 0x00) #define MCUX_LPADC2_CLK MCUX_LPC_CLK_ID(0x0F, 0x01) #define MCUX_FLEXCAN0_CLK MCUX_LPC_CLK_ID(0x10, 0x00) #define MCUX_FLEXCAN1_CLK MCUX_LPC_CLK_ID(0x10, 0x01) #define MCUX_FLEXIO0_CLK MCUX_LPC_CLK_ID(0x11, 0x00) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,418
```objective-c /* * */ #define ACPI_IRQ_DETECT 0xFFFFFFFU #define ACPI_IRQ_FLAG_DETECT 0xFFFFFFFU ```
/content/code_sandbox/include/zephyr/dt-bindings/acpi/acpi.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
25
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_ #include "gd32-common.h" /** * @name Register offsets * @{ */ #define GD32_APB2RST_OFFSET 0x0CU #define GD32_APB1RST_OFFSET 0x10U #define GD32_AHBRST_OFFSET 0x28U #define GD32_ADDAPB1RST_OFFSET 0xE0U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* APB2 peripherals */ #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U) #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U) #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U) #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U) #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U) #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U) #define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U) #define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U) #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U) #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) #define GD32_RESET_ADC2 GD32_RESET_CONFIG(APB2RST, 15U) #define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 19U) #define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 20U) #define GD32_RESET_TIMER10 GD32_RESET_CONFIG(APB2RST, 21U) /* APB1 peripherals */ #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) #define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 6U) #define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U) #define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U) #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) #define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U) #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) #define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U) #define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U) #define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U) #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) #define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U) #define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U) #define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U) #define GD32_RESET_BKPI GD32_RESET_CONFIG(APB1RST, 27U) #define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U) #define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U) /* AHB peripherals */ #define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U) /* APB1 additional peripherals */ #define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/gd32f403.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,048
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_ /** * Pack RCC register offset and bit in one 32-bit value. * * 5 LSBs are used to keep bit number in 32-bit RCC register. * Next 12 bits are used to keep RCC register offset. * Remaining bits are unused. * * @param bus STM32 bus name (expands to STM32_RESET_BUS_{bus}) * @param bit Reset bit */ #define STM32_RESET(bus, bit) (((STM32_RESET_BUS_##bus) << 5U) | (bit)) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32-common.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
163
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H /* Beginning of M2L31 BSP sys_reg.h reset module copy */ #define LPSCC_IPRST0_LPPDMA0RST_Pos 0 #define LPSCC_IPRST0_LPGPIORST_Pos 1 #define LPSCC_IPRST0_LPSRAMRST_Pos 2 #define LPSCC_IPRST0_WDTRST_Pos 16 #define LPSCC_IPRST0_LPSPI0RST_Pos 17 #define LPSCC_IPRST0_LPI2C0RST_Pos 18 #define LPSCC_IPRST0_LPUART0RST_Pos 19 #define LPSCC_IPRST0_LPTMR0RST_Pos 20 #define LPSCC_IPRST0_LPTMR1RST_Pos 21 #define LPSCC_IPRST0_TTMR0RST_Pos 22 #define LPSCC_IPRST0_TTMR1RST_Pos 23 #define LPSCC_IPRST0_LPADC0RST_Pos 24 #define LPSCC_IPRST0_OPARST_Pos 27 #define SYS_IPRST0_CHIPRST_Pos 0 #define SYS_IPRST0_CPURST_Pos 1 #define SYS_IPRST0_PDMA0RST_Pos 2 #define SYS_IPRST0_EBIRST_Pos 3 #define SYS_IPRST0_USBHRST_Pos 4 #define SYS_IPRST0_CRCRST_Pos 7 #define SYS_IPRST0_CRPTRST_Pos 12 #define SYS_IPRST0_CANFD0RST_Pos 20 #define SYS_IPRST0_CANFD1RST_Pos 21 #define SYS_IPRST1_GPIORST_Pos 1 #define SYS_IPRST1_TMR0RST_Pos 2 #define SYS_IPRST1_TMR1RST_Pos 3 #define SYS_IPRST1_TMR2RST_Pos 4 #define SYS_IPRST1_TMR3RST_Pos 5 #define SYS_IPRST1_ACMP01RST_Pos 7 #define SYS_IPRST1_I2C0RST_Pos 8 #define SYS_IPRST1_I2C1RST_Pos 9 #define SYS_IPRST1_I2C2RST_Pos 10 #define SYS_IPRST1_I2C3RST_Pos 11 #define SYS_IPRST1_QSPI0RST_Pos 12 #define SYS_IPRST1_SPI0RST_Pos 13 #define SYS_IPRST1_SPI1RST_Pos 14 #define SYS_IPRST1_SPI2RST_Pos 15 #define SYS_IPRST1_UART0RST_Pos 16 #define SYS_IPRST1_UART1RST_Pos 17 #define SYS_IPRST1_UART2RST_Pos 18 #define SYS_IPRST1_UART3RST_Pos 19 #define SYS_IPRST1_UART4RST_Pos 20 #define SYS_IPRST1_UART5RST_Pos 21 #define SYS_IPRST1_UART6RST_Pos 22 #define SYS_IPRST1_UART7RST_Pos 23 #define SYS_IPRST1_OTGRST_Pos 26 #define SYS_IPRST1_USBDRST_Pos 27 #define SYS_IPRST1_EADC0RST_Pos 28 #define SYS_IPRST1_TRNGRST_Pos 31 #define SYS_IPRST2_SPI3RST_Pos 6 #define SYS_IPRST2_USCI0RST_Pos 8 #define SYS_IPRST2_USCI1RST_Pos 9 #define SYS_IPRST2_WWDTRST_Pos 11 #define SYS_IPRST2_DACRST_Pos 12 #define SYS_IPRST2_EPWM0RST_Pos 16 #define SYS_IPRST2_EPWM1RST_Pos 17 #define SYS_IPRST2_EQEI0RST_Pos 22 #define SYS_IPRST2_EQEI1RST_Pos 23 #define SYS_IPRST2_TKRST_Pos 25 #define SYS_IPRST2_ECAP0RST_Pos 26 #define SYS_IPRST2_ECAP1RST_Pos 27 #define SYS_IPRST3_ACMP2RST_Pos 7 #define SYS_IPRST3_PWM0RST_Pos 8 #define SYS_IPRST3_PWM1RST_Pos 9 #define SYS_IPRST3_UTCPD0RST_Pos 15 /* End of M2L31 BSP sys_reg.h reset module copy */ /* Beginning of M2L31 BSP sys.h reset module copy */ /*your_sha256_hash----- * Module Reset Control Resister constant definitions. *your_sha256_hash----- */ #define NUMAKER_PDMA0_RST ((0UL<<24) | SYS_IPRST0_PDMA0RST_Pos) #define NUMAKER_EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) #define NUMAKER_USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) #define NUMAKER_CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) #define NUMAKER_CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) #define NUMAKER_CANFD0_RST ((0UL<<24) | SYS_IPRST0_CANFD0RST_Pos) #define NUMAKER_CANFD1_RST ((0UL<<24) | SYS_IPRST0_CANFD1RST_Pos) #define NUMAKER_GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) #define NUMAKER_TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) #define NUMAKER_TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) #define NUMAKER_TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) #define NUMAKER_TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) #define NUMAKER_ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) #define NUMAKER_I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) #define NUMAKER_I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) #define NUMAKER_I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) #define NUMAKER_I2C3_RST ((4UL<<24) | SYS_IPRST1_I2C3RST_Pos) #define NUMAKER_QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) #define NUMAKER_SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) #define NUMAKER_SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) #define NUMAKER_SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) #define NUMAKER_UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) #define NUMAKER_UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) #define NUMAKER_UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) #define NUMAKER_UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) #define NUMAKER_UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) #define NUMAKER_UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) #define NUMAKER_UART6_RST ((4UL<<24) | SYS_IPRST1_UART6RST_Pos) #define NUMAKER_UART7_RST ((4UL<<24) | SYS_IPRST1_UART7RST_Pos) #define NUMAKER_OTG_RST ((4UL<<24) | SYS_IPRST1_OTGRST_Pos) #define NUMAKER_USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) #define NUMAKER_EADC0_RST ((4UL<<24) | SYS_IPRST1_EADC0RST_Pos) #define NUMAKER_TRNG_RST ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos) #define NUMAKER_SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) #define NUMAKER_USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) #define NUMAKER_USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) #define NUMAKER_WWDT_RST ((8UL<<24) | SYS_IPRST2_WWDTRST_Pos) #define NUMAKER_DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) #define NUMAKER_EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) #define NUMAKER_EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) #define NUMAKER_EQEI0_RST ((8UL<<24) | SYS_IPRST2_EQEI0RST_Pos) #define NUMAKER_EQEI1_RST ((8UL<<24) | SYS_IPRST2_EQEI1RST_Pos) #define NUMAKER_TK_RST ((8UL<<24) | SYS_IPRST2_TKRST_Pos) #define NUMAKER_ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) #define NUMAKER_ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) #define NUMAKER_ACMP2_RST ((0x18UL<<24) | SYS_IPRST3_ACMP2RST_Pos) #define NUMAKER_PWM0_RST ((0x18UL<<24) | SYS_IPRST3_PWM0RST_Pos) #define NUMAKER_PWM1_RST ((0x18UL<<24) | SYS_IPRST3_PWM1RST_Pos) #define NUMAKER_UTCPD0_RST ((0x18UL<<24) | SYS_IPRST3_UTCPD0RST_Pos) #define NUMAKER_LPPDMA0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPPDMA0RST_Pos) #define NUMAKER_LPGPIO_RST ((0x80UL<<24) | LPSCC_IPRST0_LPGPIORST_Pos) #define NUMAKER_LPSRAM_RST ((0x80UL<<24) | LPSCC_IPRST0_LPSRAMRST_Pos) #define NUMAKER_WDT_RST ((0x80UL<<24) | LPSCC_IPRST0_WDTRST_Pos) #define NUMAKER_LPSPI0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPSPI0RST_Pos) #define NUMAKER_LPI2C0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPI2C0RST_Pos) #define NUMAKER_LPUART0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPUART0RST_Pos) #define NUMAKER_LPTMR0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPTMR0RST_Pos) #define NUMAKER_LPTMR1_RST ((0x80UL<<24) | LPSCC_IPRST0_LPTMR1RST_Pos) #define NUMAKER_TTMR0_RST ((0x80UL<<24) | LPSCC_IPRST0_TTMR0RST_Pos) #define NUMAKER_TTMR1_RST ((0x80UL<<24) | LPSCC_IPRST0_TTMR1RST_Pos) #define NUMAKER_LPADC0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPADC0RST_Pos) #define NUMAKER_OPA_RST ((0x80UL<<24) | LPSCC_IPRST0_OPARST_Pos) /* End of M2L31 BSP sys.h reset module copy */ #endif ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
2,850
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_ #include "gd32-common.h" /** * @name Register offsets * @{ */ #define GD32_APB2RST_OFFSET 0x0CU #define GD32_APB1RST_OFFSET 0x10U #define GD32_AHBRST_OFFSET 0x28U #define GD32_ADDAPB1RST_OFFSET 0xE0U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* APB2 peripherals */ #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U) #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U) #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U) #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U) #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U) #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U) #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U) #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) #define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 19U) #define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 20U) #define GD32_RESET_TIMER10 GD32_RESET_CONFIG(APB2RST, 21U) /* APB1 peripherals */ #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) #define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U) #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) #define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 6U) #define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U) #define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U) #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) #define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U) #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) #define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U) #define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U) #define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U) #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) #define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U) #define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U) #define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U) #define GD32_RESET_BKPI GD32_RESET_CONFIG(APB1RST, 27U) #define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U) #define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U) /* AHB peripherals */ #define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U) /* APB1 additional peripherals */ #define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/gd32e10x.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,030
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_ #define ASPEED_RESET_GRP_0_OFFSET (0) #define ASPEED_RESET_GRP_1_OFFSET (32) #define ASPEED_RESET_HACE (ASPEED_RESET_GRP_0_OFFSET + 4) #define ASPEED_RESET_USB (ASPEED_RESET_GRP_0_OFFSET + 3) #define ASPEED_RESET_SRAM (ASPEED_RESET_GRP_0_OFFSET + 0) #define ASPEED_RESET_UART4 (ASPEED_RESET_GRP_1_OFFSET + 31) #define ASPEED_RESET_UART3 (ASPEED_RESET_GRP_1_OFFSET + 30) #define ASPEED_RESET_UART2 (ASPEED_RESET_GRP_1_OFFSET + 29) #define ASPEED_RESET_UART1 (ASPEED_RESET_GRP_1_OFFSET + 28) #define ASPEED_RESET_JTAG_M0 (ASPEED_RESET_GRP_1_OFFSET + 26) #define ASPEED_RESET_ESPI (ASPEED_RESET_GRP_1_OFFSET + 25) #define ASPEED_RESET_ADC (ASPEED_RESET_GRP_1_OFFSET + 23) #define ASPEED_RESET_JTAG_M1 (ASPEED_RESET_GRP_1_OFFSET + 22) #define ASPEED_RESET_MAC (ASPEED_RESET_GRP_1_OFFSET + 20) #define ASPEED_RESET_I3C3 (ASPEED_RESET_GRP_1_OFFSET + 11) #define ASPEED_RESET_I3C2 (ASPEED_RESET_GRP_1_OFFSET + 10) #define ASPEED_RESET_I3C1 (ASPEED_RESET_GRP_1_OFFSET + 9) #define ASPEED_RESET_I3C0 (ASPEED_RESET_GRP_1_OFFSET + 8) #define ASPEED_RESET_I3C (ASPEED_RESET_GRP_1_OFFSET + 7) #define ASPEED_RESET_PWM_TACH (ASPEED_RESET_GRP_1_OFFSET + 5) #define ASPEED_RESET_PECI (ASPEED_RESET_GRP_1_OFFSET + 4) #define ASPEED_RESET_MII (ASPEED_RESET_GRP_1_OFFSET + 3) #define ASPEED_RESET_I2C (ASPEED_RESET_GRP_1_OFFSET + 2) #define ASPEED_RESET_LPC (ASPEED_RESET_GRP_1_OFFSET + 0) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/ast10x0_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
531
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX9_RESET_H #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX9_RESET_H #define NPCX_RESET_SWRST_CTL1_OFFSET 0 #define NPCX_RESET_SWRST_CTL2_OFFSET 32 #define NPCX_RESET_SWRST_CTL3_OFFSET 64 #define NPCX_RESET_SWRST_CTL4_OFFSET 96 #define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0) #define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1) #define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2) #define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3) #define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4) #define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5) #define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6) #define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7) #define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8) #define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9) #define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10) #define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11) #define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12) #define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13) #define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14) #define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15) #define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16) #define NPCX_RESET_ITIM32_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18) #define NPCX_RESET_ITIM32_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19) #define NPCX_RESET_ITIM32_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20) #define NPCX_RESET_ITIM32_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21) #define NPCX_RESET_ITIM32_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22) #define NPCX_RESET_ITIM32_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23) #define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25) #define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26) #define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27) #define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28) #define NPCX_RESET_GDMA (NPCX_RESET_SWRST_CTL1_OFFSET + 29) #define NPCX_RESET_FIU (NPCX_RESET_SWRST_CTL1_OFFSET + 30) #define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0) #define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2) #define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3) #define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5) #define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6) #define NPCX_RESET_ADC (NPCX_RESET_SWRST_CTL2_OFFSET + 7) #define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8) #define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9) #define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10) #define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11) #define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12) #define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13) #define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14) #define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15) #define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16) #define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17) #define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18) #define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19) #define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20) #define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21) #define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22) #define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23) #define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24) #define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25) #define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26) #define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27) #define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28) #define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29) #define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30) #define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31) #define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0) #define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1) #define NPCX_RESET_I3C (NPCX_RESET_SWRST_CTL3_OFFSET + 5) #define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8) #define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9) #define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10) #define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11) #define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12) #define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13) #define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15) #define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16) #define NPCX_RESET_CRUART3 (NPCX_RESET_SWRST_CTL3_OFFSET + 18) #define NPCX_RESET_CRUART4 (NPCX_RESET_SWRST_CTL3_OFFSET + 19) #define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20) #define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22) #define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23) #define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24) #define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25) #define NPCX_RESET_SHA (NPCX_RESET_SWRST_CTL3_OFFSET + 29) #define NPCX_RESET_MDMA1 (NPCX_RESET_SWRST_CTL4_OFFSET + 24) #define NPCX_RESET_MDMA2 (NPCX_RESET_SWRST_CTL4_OFFSET + 25) #define NPCX_RESET_MDMA3 (NPCX_RESET_SWRST_CTL4_OFFSET + 26) #define NPCX_RESET_MDMA4 (NPCX_RESET_SWRST_CTL4_OFFSET + 27) #define NPCX_RESET_MDMA5 (NPCX_RESET_SWRST_CTL4_OFFSET + 28) #define NPCX_RESET_ID_START NPCX_RESET_GPIO0 #define NPCX_RESET_ID_END NPCX_RESET_MDMA5 #endif ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/npcx9_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,901
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G4_L4_5_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G4_L4_5_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB1 0x28 #define STM32_RESET_BUS_AHB2 0x2C #define STM32_RESET_BUS_AHB3 0x30 #define STM32_RESET_BUS_APB1L 0x38 #define STM32_RESET_BUS_APB1H 0x3C #define STM32_RESET_BUS_APB2 0x40 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G4_L4_5_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
166
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB_L_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB_L_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB1 0x28 #define STM32_RESET_BUS_AHB2 0x2C #define STM32_RESET_BUS_AHB3 0x30 #define STM32_RESET_BUS_APB1L 0x38 #define STM32_RESET_BUS_APB1H 0x3C #define STM32_RESET_BUS_APB2 0x40 #define STM32_RESET_BUS_APB3 0x44 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB_L_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32wb_l_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
167
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_ #include "gd32-common.h" /** * @name Register offsets * @{ */ #define GD32_APB2RST_OFFSET 0x0CU #define GD32_APB1RST_OFFSET 0x10U #define GD32_AHBRST_OFFSET 0x28U #define GD32_ADDAPB1RST_OFFSET 0xFCU /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* APB2 peripherals */ #define GD32_RESET_CFGCMP GD32_RESET_CONFIG(APB2RST, 0U) #define GD32_RESET_ADC GD32_RESET_CONFIG(APB2RST, 9U) #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) #define GD32_RESET_TIMER14 GD32_RESET_CONFIG(APB2RST, 16U) #define GD32_RESET_TIMER15 GD32_RESET_CONFIG(APB2RST, 17U) #define GD32_RESET_TIMER16 GD32_RESET_CONFIG(APB2RST, 18U) /* APB1 peripherals */ #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) #define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U) #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) #define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U) #define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U) #define GD32_RESET_CEC GD32_RESET_CONFIG(APB1RST, 30U) /* AHB peripherals */ #define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U) #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U) #define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHBRST, 18U) #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHBRST, 19U) #define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHBRST, 20U) #define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHBRST, 22U) #define GD32_RESET_TSI GD32_RESET_CONFIG(AHBRST, 24U) /* APB1 additional peripherals */ #define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/gd32f3x0.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
726
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F0_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F0_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB1 0x28 #define STM32_RESET_BUS_APB1 0x10 #define STM32_RESET_BUS_APB2 0x0C #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F0_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32f0_1_3_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
111
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_ #include "gd32-common.h" /** * @name Register offsets * @{ */ #define GD32_AHBRST_OFFSET 0x28U #define GD32_APB1RST_OFFSET 0x10U #define GD32_APB2RST_OFFSET 0x0CU /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB peripherals */ #define GD32_RESET_DMA0 GD32_RESET_CONFIG(AHBRST, 0U) #define GD32_RESET_DMA1 GD32_RESET_CONFIG(AHBRST, 1U) #define GD32_RESET_SRAMSP GD32_RESET_CONFIG(AHBRST, 2U) #define GD32_RESET_DMAMUX GD32_RESET_CONFIG(AHBRST, 3U) #define GD32_RESET_FMCSP GD32_RESET_CONFIG(AHBRST, 4U) #define GD32_RESET_CRC GD32_RESET_CONFIG(AHBRST, 6U) #define GD32_RESET_MFCOM GD32_RESET_CONFIG(AHBRST, 14U) #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U) #define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHBRST, 18U) #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHBRST, 19U) #define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHBRST, 20U) #define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHBRST, 21U) #define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHBRST, 22U) /* APB1 peripherals */ #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) #define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U) #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) #define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U) #define GD32_RESET_BKP GD32_RESET_CONFIG(APB1RST, 26U) #define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U) #define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U) /* APB2 peripherals */ #define GD32_RESET_SYSCFG GD32_RESET_CONFIG(APB2RST, 0U) #define GD32_RESET_CMP GD32_RESET_CONFIG(APB2RST, 1U) #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U) #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) #define GD32_RESET_TIMER19 GD32_RESET_CONFIG(APB2RST, 20U) #define GD32_RESET_TIMER20 GD32_RESET_CONFIG(APB2RST, 21U) #define GD32_RESET_TRIGSEL GD32_RESET_CONFIG(APB2RST, 29U) #define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB2RST, 30U) #define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB2RST, 31U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/gd32a50x.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
953
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G0_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G0_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_IOP 0x24 #define STM32_RESET_BUS_AHB1 0x28 #define STM32_RESET_BUS_APB1L 0x2C #define STM32_RESET_BUS_APB1H 0x30 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G0_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32g0_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
127
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H5_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H5_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB1 0x60 #define STM32_RESET_BUS_AHB2 0x64 #define STM32_RESET_BUS_AHB4 0x6C #define STM32_RESET_BUS_APB1L 0x74 #define STM32_RESET_BUS_APB1H 0x78 #define STM32_RESET_BUS_APB2 0x7C #define STM32_RESET_BUS_APB3 0x80 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H5_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32h5_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
167
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_ #include "gd32-common.h" /** * @name Register offsets * @{ */ #define GD32_AHB1RST_OFFSET 0x10U #define GD32_AHB2RST_OFFSET 0x14U #define GD32_AHB3RST_OFFSET 0x18U #define GD32_APB1RST_OFFSET 0x20U #define GD32_APB2RST_OFFSET 0x24U #define GD32_ADDAPB1RST_OFFSET 0xE0U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* AHB1 peripherals */ #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB1RST, 0U) #define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB1RST, 1U) #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 2U) #define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB1RST, 3U) #define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHB1RST, 4U) #define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB1RST, 5U) #define GD32_RESET_GPIOG GD32_RESET_CONFIG(AHB1RST, 6U) #define GD32_RESET_GPIOH GD32_RESET_CONFIG(AHB1RST, 7U) #define GD32_RESET_GPIOI GD32_RESET_CONFIG(AHB1RST, 8U) #define GD32_RESET_CRC GD32_RESET_CONFIG(AHB1RST, 12U) #define GD32_RESET_BKPSRAM GD32_RESET_CONFIG(AHB1RST, 18U) #define GD32_RESET_TCMSRAM GD32_RESET_CONFIG(AHB1RST, 20U) #define GD32_RESET_DMA0 GD32_RESET_CONFIG(AHB1RST, 21U) #define GD32_RESET_DMA1 GD32_RESET_CONFIG(AHB1RST, 22U) #define GD32_RESET_IPA GD32_RESET_CONFIG(AHB1RST, 23U) #define GD32_RESET_ENET GD32_RESET_CONFIG(AHB1RST, 25U) #define GD32_RESET_ENETTX GD32_RESET_CONFIG(AHB1RST, 26U) #define GD32_RESET_ENETRX GD32_RESET_CONFIG(AHB1RST, 27U) #define GD32_RESET_ENETPTP GD32_RESET_CONFIG(AHB1RST, 28U) #define GD32_RESET_USBHS GD32_RESET_CONFIG(AHB1RST, 29U) #define GD32_RESET_USBHSULPI GD32_RESET_CONFIG(AHB1RST, 30U) /* AHB2 peripherals */ #define GD32_RESET_DCI GD32_RESET_CONFIG(AHB2RST, 0U) #define GD32_RESET_TRNG GD32_RESET_CONFIG(AHB2RST, 6U) #define GD32_RESET_USBFS GD32_RESET_CONFIG(AHB2RST, 7U) /* AHB3 peripherals */ #define GD32_RESET_EXMC GD32_RESET_CONFIG(AHB3RST, 0U) /* APB1 peripherals */ #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) #define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U) #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) #define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 6U) #define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U) #define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U) #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) #define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U) #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) #define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U) #define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U) #define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U) #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) #define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U) #define GD32_RESET_I2C2 GD32_RESET_CONFIG(APB1RST, 23U) #define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U) #define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U) #define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U) #define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U) #define GD32_RESET_UART6 GD32_RESET_CONFIG(APB1RST, 30U) #define GD32_RESET_UART7 GD32_RESET_CONFIG(APB1RST, 31U) #define GD32_RESET_RTC GD32_RESET_CONFIG(BDCTL, 15U) /* APB2 peripherals */ #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 0U) #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 1U) #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 4U) #define GD32_RESET_USART5 GD32_RESET_CONFIG(APB2RST, 5U) #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 8U) #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 9U) #define GD32_RESET_ADC2 GD32_RESET_CONFIG(APB2RST, 10U) #define GD32_RESET_SDIO GD32_RESET_CONFIG(APB2RST, 11U) #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) #define GD32_RESET_SPI3 GD32_RESET_CONFIG(APB2RST, 13U) #define GD32_RESET_SYSCFG GD32_RESET_CONFIG(APB2RST, 14U) #define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 16U) #define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 17U) #define GD32_RESET_TIMER10 GD32_RESET_CONFIG(APB2RST, 18U) #define GD32_RESET_SPI4 GD32_RESET_CONFIG(APB2RST, 20U) #define GD32_RESET_SPI5 GD32_RESET_CONFIG(APB2RST, 21U) #define GD32_RESET_TLI GD32_RESET_CONFIG(APB2RST, 26U) /* APB1 additional peripherals */ #define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U) #define GD32_RESET_IREF GD32_RESET_CONFIG(ADDAPB1RST, 31U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/gd32f4xx.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,713
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L0_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L0_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_IOP 0x1C #define STM32_RESET_BUS_AHB1 0x20 #define STM32_RESET_BUS_APB1 0x28 #define STM32_RESET_BUS_APB2 0x24 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L0_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32l0_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
124
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7RS_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7RS_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB1 0x80 #define STM32_RESET_BUS_AHB2 0x84 #define STM32_RESET_BUS_AHB3 0xA4 #define STM32_RESET_BUS_AHB5 0x7C #define STM32_RESET_BUS_APB5 0x8C #define STM32_RESET_BUS_AHB4 0x88 #define STM32_RESET_BUS_APB1L 0x90 #define STM32_RESET_BUS_APB1H 0x94 #define STM32_RESET_BUS_APB2 0x98 #define STM32_RESET_BUS_APB4 0x9C #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7RS_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32h7rs_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
210
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M46X_CLOCK_H #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M46X_CLOCK_H /* Beginning of M460 BSP clk_reg.h copy */ #define NUMAKER_CLK_AHBCLK0_PDMA0CKEN_Pos (1) #define NUMAKER_CLK_AHBCLK0_ISPCKEN_Pos (2) #define NUMAKER_CLK_AHBCLK0_EBICKEN_Pos (3) #define NUMAKER_CLK_AHBCLK0_STCKEN_Pos (4) #define NUMAKER_CLK_AHBCLK0_EMAC0CKEN_Pos (5) #define NUMAKER_CLK_AHBCLK0_SDH0CKEN_Pos (6) #define NUMAKER_CLK_AHBCLK0_CRCCKEN_Pos (7) #define NUMAKER_CLK_AHBCLK0_CCAPCKEN_Pos (8) #define NUMAKER_CLK_AHBCLK0_SENCKEN_Pos (9) #define NUMAKER_CLK_AHBCLK0_HSUSBDCKEN_Pos (10) #define NUMAKER_CLK_AHBCLK0_HBICKEN_Pos (11) #define NUMAKER_CLK_AHBCLK0_CRPTCKEN_Pos (12) #define NUMAKER_CLK_AHBCLK0_KSCKEN_Pos (13) #define NUMAKER_CLK_AHBCLK0_SPIMCKEN_Pos (14) #define NUMAKER_CLK_AHBCLK0_FMCIDLE_Pos (15) #define NUMAKER_CLK_AHBCLK0_USBHCKEN_Pos (16) #define NUMAKER_CLK_AHBCLK0_SDH1CKEN_Pos (17) #define NUMAKER_CLK_AHBCLK0_PDMA1CKEN_Pos (18) #define NUMAKER_CLK_AHBCLK0_TRACECKEN_Pos (19) #define NUMAKER_CLK_AHBCLK0_GPACKEN_Pos (24) #define NUMAKER_CLK_AHBCLK0_GPBCKEN_Pos (25) #define NUMAKER_CLK_AHBCLK0_GPCCKEN_Pos (26) #define NUMAKER_CLK_AHBCLK0_GPDCKEN_Pos (27) #define NUMAKER_CLK_AHBCLK0_GPECKEN_Pos (28) #define NUMAKER_CLK_AHBCLK0_GPFCKEN_Pos (29) #define NUMAKER_CLK_AHBCLK0_GPGCKEN_Pos (30) #define NUMAKER_CLK_AHBCLK0_GPHCKEN_Pos (31) #define NUMAKER_CLK_APBCLK0_WDTCKEN_Pos (0) #define NUMAKER_CLK_APBCLK0_RTCCKEN_Pos (1) #define NUMAKER_CLK_APBCLK0_TMR0CKEN_Pos (2) #define NUMAKER_CLK_APBCLK0_TMR1CKEN_Pos (3) #define NUMAKER_CLK_APBCLK0_TMR2CKEN_Pos (4) #define NUMAKER_CLK_APBCLK0_TMR3CKEN_Pos (5) #define NUMAKER_CLK_APBCLK0_CLKOCKEN_Pos (6) #define NUMAKER_CLK_APBCLK0_ACMP01CKEN_Pos (7) #define NUMAKER_CLK_APBCLK0_I2C0CKEN_Pos (8) #define NUMAKER_CLK_APBCLK0_I2C1CKEN_Pos (9) #define NUMAKER_CLK_APBCLK0_I2C2CKEN_Pos (10) #define NUMAKER_CLK_APBCLK0_I2C3CKEN_Pos (11) #define NUMAKER_CLK_APBCLK0_QSPI0CKEN_Pos (12) #define NUMAKER_CLK_APBCLK0_SPI0CKEN_Pos (13) #define NUMAKER_CLK_APBCLK0_SPI1CKEN_Pos (14) #define NUMAKER_CLK_APBCLK0_SPI2CKEN_Pos (15) #define NUMAKER_CLK_APBCLK0_UART0CKEN_Pos (16) #define NUMAKER_CLK_APBCLK0_UART1CKEN_Pos (17) #define NUMAKER_CLK_APBCLK0_UART2CKEN_Pos (18) #define NUMAKER_CLK_APBCLK0_UART3CKEN_Pos (19) #define NUMAKER_CLK_APBCLK0_UART4CKEN_Pos (20) #define NUMAKER_CLK_APBCLK0_UART5CKEN_Pos (21) #define NUMAKER_CLK_APBCLK0_UART6CKEN_Pos (22) #define NUMAKER_CLK_APBCLK0_UART7CKEN_Pos (23) #define NUMAKER_CLK_APBCLK0_OTGCKEN_Pos (26) #define NUMAKER_CLK_APBCLK0_USBDCKEN_Pos (27) #define NUMAKER_CLK_APBCLK0_EADC0CKEN_Pos (28) #define NUMAKER_CLK_APBCLK0_I2S0CKEN_Pos (29) #define NUMAKER_CLK_APBCLK0_HSOTGCKEN_Pos (30) #define NUMAKER_CLK_APBCLK1_SC0CKEN_Pos (0) #define NUMAKER_CLK_APBCLK1_SC1CKEN_Pos (1) #define NUMAKER_CLK_APBCLK1_SC2CKEN_Pos (2) #define NUMAKER_CLK_APBCLK1_I2C4CKEN_Pos (3) #define NUMAKER_CLK_APBCLK1_QSPI1CKEN_Pos (4) #define NUMAKER_CLK_APBCLK1_SPI3CKEN_Pos (6) #define NUMAKER_CLK_APBCLK1_SPI4CKEN_Pos (7) #define NUMAKER_CLK_APBCLK1_USCI0CKEN_Pos (8) #define NUMAKER_CLK_APBCLK1_PSIOCKEN_Pos (10) #define NUMAKER_CLK_APBCLK1_DACCKEN_Pos (12) #define NUMAKER_CLK_APBCLK1_ECAP2CKEN_Pos (13) #define NUMAKER_CLK_APBCLK1_ECAP3CKEN_Pos (14) #define NUMAKER_CLK_APBCLK1_EPWM0CKEN_Pos (16) #define NUMAKER_CLK_APBCLK1_EPWM1CKEN_Pos (17) #define NUMAKER_CLK_APBCLK1_BPWM0CKEN_Pos (18) #define NUMAKER_CLK_APBCLK1_BPWM1CKEN_Pos (19) #define NUMAKER_CLK_APBCLK1_EQEI2CKEN_Pos (20) #define NUMAKER_CLK_APBCLK1_EQEI3CKEN_Pos (21) #define NUMAKER_CLK_APBCLK1_EQEI0CKEN_Pos (22) #define NUMAKER_CLK_APBCLK1_EQEI1CKEN_Pos (23) #define NUMAKER_CLK_APBCLK1_TRNGCKEN_Pos (25) #define NUMAKER_CLK_APBCLK1_ECAP0CKEN_Pos (26) #define NUMAKER_CLK_APBCLK1_ECAP1CKEN_Pos (27) #define NUMAKER_CLK_APBCLK1_I2S1CKEN_Pos (29) #define NUMAKER_CLK_APBCLK1_EADC1CKEN_Pos (31) #define NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos (0) #define NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos (3) #define NUMAKER_CLK_CLKSEL0_USBSEL_Pos (8) #define NUMAKER_CLK_CLKSEL0_EADC0SEL_Pos (10) #define NUMAKER_CLK_CLKSEL0_EADC1SEL_Pos (12) #define NUMAKER_CLK_CLKSEL0_EADC2SEL_Pos (14) #define NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos (16) #define NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos (20) #define NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos (22) #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_Pos (24) #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_Pos (26) #define NUMAKER_CLK_CLKSEL0_CANFD2SEL_Pos (28) #define NUMAKER_CLK_CLKSEL0_CANFD3SEL_Pos (30) #define NUMAKER_CLK_CLKSEL1_WDTSEL_Pos (0) #define NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos (4) #define NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos (8) #define NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos (12) #define NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos (16) #define NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos (20) #define NUMAKER_CLK_CLKSEL1_UART0SEL_Pos (24) #define NUMAKER_CLK_CLKSEL1_UART1SEL_Pos (26) #define NUMAKER_CLK_CLKSEL1_WWDTSEL_Pos (30) #define NUMAKER_CLK_CLKSEL2_EPWM0SEL_Pos (0) #define NUMAKER_CLK_CLKSEL2_EPWM1SEL_Pos (1) #define NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos (2) #define NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos (4) #define NUMAKER_CLK_CLKSEL2_BPWM0SEL_Pos (8) #define NUMAKER_CLK_CLKSEL2_BPWM1SEL_Pos (9) #define NUMAKER_CLK_CLKSEL2_QSPI1SEL_Pos (10) #define NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos (12) #define NUMAKER_CLK_CLKSEL2_I2S1SEL_Pos (16) #define NUMAKER_CLK_CLKSEL2_UART8SEL_Pos (20) #define NUMAKER_CLK_CLKSEL2_UART9SEL_Pos (22) #define NUMAKER_CLK_CLKSEL2_TRNGSEL_Pos (27) #define NUMAKER_CLK_CLKSEL2_PSIOSEL_Pos (28) #define NUMAKER_CLK_CLKSEL3_SC0SEL_Pos (0) #define NUMAKER_CLK_CLKSEL3_SC1SEL_Pos (2) #define NUMAKER_CLK_CLKSEL3_SC2SEL_Pos (4) #define NUMAKER_CLK_CLKSEL3_KPISEL_Pos (6) #define NUMAKER_CLK_CLKSEL3_SPI2SEL_Pos (9) #define NUMAKER_CLK_CLKSEL3_SPI3SEL_Pos (12) #define NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos (16) #define NUMAKER_CLK_CLKSEL3_UART6SEL_Pos (20) #define NUMAKER_CLK_CLKSEL3_UART7SEL_Pos (22) #define NUMAKER_CLK_CLKSEL3_UART2SEL_Pos (24) #define NUMAKER_CLK_CLKSEL3_UART3SEL_Pos (26) #define NUMAKER_CLK_CLKSEL3_UART4SEL_Pos (28) #define NUMAKER_CLK_CLKSEL3_UART5SEL_Pos (30) #define NUMAKER_CLK_CLKDIV0_HCLKDIV_Pos (0) #define NUMAKER_CLK_CLKDIV0_USBDIV_Pos (4) #define NUMAKER_CLK_CLKDIV0_UART0DIV_Pos (8) #define NUMAKER_CLK_CLKDIV0_UART1DIV_Pos (12) #define NUMAKER_CLK_CLKDIV0_EADC0DIV_Pos (16) #define NUMAKER_CLK_CLKDIV0_SDH0DIV_Pos (24) #define NUMAKER_CLK_CLKDIV1_SC0DIV_Pos (0) #define NUMAKER_CLK_CLKDIV1_SC1DIV_Pos (8) #define NUMAKER_CLK_CLKDIV1_SC2DIV_Pos (16) #define NUMAKER_CLK_CLKDIV1_PSIODIV_Pos (24) #define NUMAKER_CLK_CLKDIV2_I2S0DIV_Pos (0) #define NUMAKER_CLK_CLKDIV2_I2S1DIV_Pos (4) #define NUMAKER_CLK_CLKDIV2_KPIDIV_Pos (8) #define NUMAKER_CLK_CLKDIV2_EADC1DIV_Pos (24) #define NUMAKER_CLK_CLKDIV3_VSENSEDIV_Pos (8) #define NUMAKER_CLK_CLKDIV3_EMAC0DIV_Pos (16) #define NUMAKER_CLK_CLKDIV3_SDH1DIV_Pos (24) #define NUMAKER_CLK_CLKDIV4_UART2DIV_Pos (0) #define NUMAKER_CLK_CLKDIV4_UART3DIV_Pos (4) #define NUMAKER_CLK_CLKDIV4_UART4DIV_Pos (8) #define NUMAKER_CLK_CLKDIV4_UART5DIV_Pos (12) #define NUMAKER_CLK_CLKDIV4_UART6DIV_Pos (16) #define NUMAKER_CLK_CLKDIV4_UART7DIV_Pos (20) #define NUMAKER_CLK_PCLKDIV_APB0DIV_Pos (0) #define NUMAKER_CLK_PCLKDIV_APB1DIV_Pos (4) #define NUMAKER_CLK_APBCLK2_KPICKEN_Pos (0) #define NUMAKER_CLK_APBCLK2_EADC2CKEN_Pos (6) #define NUMAKER_CLK_APBCLK2_ACMP23CKEN_Pos (7) #define NUMAKER_CLK_APBCLK2_SPI5CKEN_Pos (8) #define NUMAKER_CLK_APBCLK2_SPI6CKEN_Pos (9) #define NUMAKER_CLK_APBCLK2_SPI7CKEN_Pos (10) #define NUMAKER_CLK_APBCLK2_SPI8CKEN_Pos (11) #define NUMAKER_CLK_APBCLK2_SPI9CKEN_Pos (12) #define NUMAKER_CLK_APBCLK2_SPI10CKEN_Pos (13) #define NUMAKER_CLK_APBCLK2_UART8CKEN_Pos (16) #define NUMAKER_CLK_APBCLK2_UART9CKEN_Pos (17) #define NUMAKER_CLK_CLKDIV5_CANFD0DIV_Pos (0) #define NUMAKER_CLK_CLKDIV5_CANFD1DIV_Pos (4) #define NUMAKER_CLK_CLKDIV5_CANFD2DIV_Pos (8) #define NUMAKER_CLK_CLKDIV5_CANFD3DIV_Pos (12) #define NUMAKER_CLK_CLKDIV5_UART8DIV_Pos (16) #define NUMAKER_CLK_CLKDIV5_UART9DIV_Pos (20) #define NUMAKER_CLK_CLKDIV5_EADC2DIV_Pos (24) #define NUMAKER_CLK_AHBCLK1_CANFD0CKEN_Pos (20) #define NUMAKER_CLK_AHBCLK1_CANFD1CKEN_Pos (21) #define NUMAKER_CLK_AHBCLK1_CANFD2CKEN_Pos (22) #define NUMAKER_CLK_AHBCLK1_CANFD3CKEN_Pos (23) #define NUMAKER_CLK_AHBCLK1_GPICKEN_Pos (24) #define NUMAKER_CLK_AHBCLK1_GPJCKEN_Pos (25) #define NUMAKER_CLK_AHBCLK1_BMCCKEN_Pos (28) #define NUMAKER_CLK_CLKSEL4_SPI4SEL_Pos (0) #define NUMAKER_CLK_CLKSEL4_SPI5SEL_Pos (4) #define NUMAKER_CLK_CLKSEL4_SPI6SEL_Pos (8) #define NUMAKER_CLK_CLKSEL4_SPI7SEL_Pos (12) #define NUMAKER_CLK_CLKSEL4_SPI8SEL_Pos (16) #define NUMAKER_CLK_CLKSEL4_SPI9SEL_Pos (20) #define NUMAKER_CLK_CLKSEL4_SPI10SEL_Pos (24) /* End of M460 BSP clk_reg.h copy */ /* Beginning of M460 BSP clk.h copy */ /* CLKSEL0 constant definitions. (Write-protection) */ #define NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos) #define NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK (0x1UL << SysTick_CTRL_CLKSOURCE_Pos) #define NUMAKER_CLK_CLKSEL0_USBSEL_HIRC48M (0x0UL << NUMAKER_CLK_CLKSEL0_USBSEL_Pos) #define NUMAKER_CLK_CLKSEL0_USBSEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_USBSEL_Pos) #define NUMAKER_CLK_CLKSEL0_EADC0SEL_PLLFN_DIV2 (0x0UL << NUMAKER_CLK_CLKSEL0_EADC0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_EADC0SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_EADC0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_EADC0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_EADC1SEL_PLLFN_DIV2 (0x0UL << NUMAKER_CLK_CLKSEL0_EADC1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_EADC1SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_EADC1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_EADC1SEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_EADC1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_EADC2SEL_PLLFN_DIV2 (0x0UL << NUMAKER_CLK_CLKSEL0_EADC2SEL_Pos) #define NUMAKER_CLK_CLKSEL0_EADC2SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_EADC2SEL_Pos) #define NUMAKER_CLK_CLKSEL0_EADC2SEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_EADC2SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos) #define NUMAKER_CLK_CLKSEL0_CCAPSEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos) #define NUMAKER_CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos) #define NUMAKER_CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos) #define NUMAKER_CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_SDH0SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_SDH1SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL0_CANFD0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_CANFD0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_CANFD0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL0_CANFD0SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL0_CANFD1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_CANFD1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_CANFD1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL0_CANFD1SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD2SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL0_CANFD2SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD2SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_CANFD2SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD2SEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_CANFD2SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD2SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL0_CANFD2SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD3SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL0_CANFD3SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD3SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL0_CANFD3SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD3SEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL0_CANFD3SEL_Pos) #define NUMAKER_CLK_CLKSEL0_CANFD3SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL0_CANFD3SEL_Pos) /* CLKSEL1 constant definitions. */ #define NUMAKER_CLK_CLKSEL1_WDTSEL_LXT (0x1UL << NUMAKER_CLK_CLKSEL1_WDTSEL_Pos) #define NUMAKER_CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << NUMAKER_CLK_CLKSEL1_WDTSEL_Pos) #define NUMAKER_CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << NUMAKER_CLK_CLKSEL1_WDTSEL_Pos) #define NUMAKER_CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos) #define NUMAKER_CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos) #define NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos) #define NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos) #define NUMAKER_CLK_CLKSEL1_CLKOSEL_LIRC (0x4UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos) #define NUMAKER_CLK_CLKSEL1_CLKOSEL_PLLFN_DIV2 (0x5UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos) #define NUMAKER_CLK_CLKSEL1_CLKOSEL_PLL_DIV2 (0x6UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos) #define NUMAKER_CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos) #define NUMAKER_CLK_CLKSEL1_UART0SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_UART0SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_UART0SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos) #define NUMAKER_CLK_CLKSEL1_UART1SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_UART1SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_UART1SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos) #define NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << NUMAKER_CLK_CLKSEL1_WWDTSEL_Pos) #define NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << NUMAKER_CLK_CLKSEL1_WWDTSEL_Pos) /* CLKSEL2 constant definitions. */ #define NUMAKER_CLK_CLKSEL2_EPWM0SEL_HCLK (0x0UL << NUMAKER_CLK_CLKSEL2_EPWM0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << NUMAKER_CLK_CLKSEL2_EPWM0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_EPWM1SEL_HCLK (0x0UL << NUMAKER_CLK_CLKSEL2_EPWM1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << NUMAKER_CLK_CLKSEL2_EPWM1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI0SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC48M (0x4UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI0SEL_PLLFN_DIV2 (0x5UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_BPWM0SEL_HCLK (0x0UL << NUMAKER_CLK_CLKSEL2_BPWM0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << NUMAKER_CLK_CLKSEL2_BPWM0SEL_Pos) #define NUMAKER_CLK_CLKSEL2_BPWM1SEL_HCLK (0x0UL << NUMAKER_CLK_CLKSEL2_BPWM1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << NUMAKER_CLK_CLKSEL2_BPWM1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_QSPI1SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL2_QSPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_QSPI1SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL2_QSPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_QSPI1SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL2_QSPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_QSPI1SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL2_QSPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI1SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC48M (0x4UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_SPI1SEL_PLLFN_DIV2 (0x5UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_I2S1SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL2_I2S1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_I2S1SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL2_I2S1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_I2S1SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL2_I2S1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_I2S1SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL2_I2S1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_I2S1SEL_HIRC48M (0x4UL << NUMAKER_CLK_CLKSEL2_I2S1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_I2S1SEL_PLLFN_DIV2 (0x5UL << NUMAKER_CLK_CLKSEL2_I2S1SEL_Pos) #define NUMAKER_CLK_CLKSEL2_UART8SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL2_UART8SEL_Pos) #define NUMAKER_CLK_CLKSEL2_UART8SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL2_UART8SEL_Pos) #define NUMAKER_CLK_CLKSEL2_UART8SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL2_UART8SEL_Pos) #define NUMAKER_CLK_CLKSEL2_UART8SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL2_UART8SEL_Pos) #define NUMAKER_CLK_CLKSEL2_UART9SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL2_UART9SEL_Pos) #define NUMAKER_CLK_CLKSEL2_UART9SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL2_UART9SEL_Pos) #define NUMAKER_CLK_CLKSEL2_UART9SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL2_UART9SEL_Pos) #define NUMAKER_CLK_CLKSEL2_UART9SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL2_UART9SEL_Pos) #define NUMAKER_CLK_CLKSEL2_TRNGSEL_LXT (0x0UL << NUMAKER_CLK_CLKSEL2_TRNGSEL_Pos) #define NUMAKER_CLK_CLKSEL2_TRNGSEL_LIRC (0x1UL << NUMAKER_CLK_CLKSEL2_TRNGSEL_Pos) #define NUMAKER_CLK_CLKSEL2_PSIOSEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL2_PSIOSEL_Pos) #define NUMAKER_CLK_CLKSEL2_PSIOSEL_LXT (0x1UL << NUMAKER_CLK_CLKSEL2_PSIOSEL_Pos) #define NUMAKER_CLK_CLKSEL2_PSIOSEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL2_PSIOSEL_Pos) #define NUMAKER_CLK_CLKSEL2_PSIOSEL_PLL_DIV2 (0x3UL << NUMAKER_CLK_CLKSEL2_PSIOSEL_Pos) #define NUMAKER_CLK_CLKSEL2_PSIOSEL_LIRC (0x4UL << NUMAKER_CLK_CLKSEL2_PSIOSEL_Pos) #define NUMAKER_CLK_CLKSEL2_PSIOSEL_HIRC (0x5UL << NUMAKER_CLK_CLKSEL2_PSIOSEL_Pos) /* CLKSEL3 constant definitions. */ #define NUMAKER_CLK_CLKSEL3_SC0SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC0SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC1SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC1SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC2SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC2SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_KPISEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_KPISEL_Pos) #define NUMAKER_CLK_CLKSEL3_KPISEL_LIRC (0x1UL << NUMAKER_CLK_CLKSEL3_KPISEL_Pos) #define NUMAKER_CLK_CLKSEL3_KPISEL_HIRC (0x2UL << NUMAKER_CLK_CLKSEL3_KPISEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI2SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_SPI2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI2SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_SPI2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI2SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL3_SPI2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_SPI2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC48M (0x4UL << NUMAKER_CLK_CLKSEL3_SPI2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI2SEL_PLLFN_DIV2 (0x5UL << NUMAKER_CLK_CLKSEL3_SPI2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI3SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_SPI3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI3SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_SPI3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI3SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL3_SPI3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_SPI3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC48M (0x4UL << NUMAKER_CLK_CLKSEL3_SPI3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_SPI3SEL_PLLFN_DIV2 (0x5UL << NUMAKER_CLK_CLKSEL3_SPI3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_I2S0SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_I2S0SEL_HIRC48M (0x4UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_I2S0SEL_PLLFN_DIV2 (0x5UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART6SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART6SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART6SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART7SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART7SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART7SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART2SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART2SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART2SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART3SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART3SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART3SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART4SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART4SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART4SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART5SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART5SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART5SEL_LXT (0x2UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos) #define NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos) /* CLKSEL4 constant definitions. */ #define NUMAKER_CLK_CLKSEL4_SPI4SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL4_SPI4SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI4SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL4_SPI4SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI4SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL4_SPI4SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI4SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL4_SPI4SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI5SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL4_SPI5SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI5SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL4_SPI5SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI5SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL4_SPI5SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI5SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL4_SPI5SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI6SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL4_SPI6SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI6SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL4_SPI6SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI6SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL4_SPI6SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI6SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL4_SPI6SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI7SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL4_SPI7SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI7SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL4_SPI7SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI7SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL4_SPI7SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI7SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL4_SPI7SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI8SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL4_SPI8SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI8SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL4_SPI8SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI8SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL4_SPI8SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI8SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL4_SPI8SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI9SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL4_SPI9SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI9SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL4_SPI9SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI9SEL_PCLK0 (0x2UL << NUMAKER_CLK_CLKSEL4_SPI9SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI9SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL4_SPI9SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI10SEL_HXT (0x0UL << NUMAKER_CLK_CLKSEL4_SPI10SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI10SEL_PLL_DIV2 (0x1UL << NUMAKER_CLK_CLKSEL4_SPI10SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI10SEL_PCLK1 (0x2UL << NUMAKER_CLK_CLKSEL4_SPI10SEL_Pos) #define NUMAKER_CLK_CLKSEL4_SPI10SEL_HIRC (0x3UL << NUMAKER_CLK_CLKSEL4_SPI10SEL_Pos) /* CLKDIV0 constant definitions. */ #define NUMAKER_CLK_CLKDIV0_HCLK(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV0_HCLKDIV_Pos) #define NUMAKER_CLK_CLKDIV0_USB(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV0_USBDIV_Pos) #define NUMAKER_CLK_CLKDIV0_SDH0(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV0_SDH0DIV_Pos) #define NUMAKER_CLK_CLKDIV0_UART0(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV0_UART0DIV_Pos) #define NUMAKER_CLK_CLKDIV0_UART1(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV0_UART1DIV_Pos) #define NUMAKER_CLK_CLKDIV0_EADC0(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV0_EADC0DIV_Pos) /* CLKDIV1 constant definitions. */ #define NUMAKER_CLK_CLKDIV1_SC0(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV1_SC0DIV_Pos) #define NUMAKER_CLK_CLKDIV1_SC1(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV1_SC1DIV_Pos) #define NUMAKER_CLK_CLKDIV1_SC2(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV1_SC2DIV_Pos) #define NUMAKER_CLK_CLKDIV1_PSIO(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV1_PSIODIV_Pos) /* CLKDIV2 constant definitions. */ #define NUMAKER_CLK_CLKDIV2_I2S0(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV2_I2S0DIV_Pos) #define NUMAKER_CLK_CLKDIV2_I2S1(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV2_I2S1DIV_Pos) #define NUMAKER_CLK_CLKDIV2_KPI(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV2_KPIDIV_Pos) #define NUMAKER_CLK_CLKDIV2_EADC1(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV2_EADC1DIV_Pos) /* CLKDIV3 constant definitions. */ #define NUMAKER_CLK_CLKDIV3_VSENSE(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV3_VSENSEDIV_Pos) #define NUMAKER_CLK_CLKDIV3_EMAC0(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV3_EMAC0DIV_Pos) #define NUMAKER_CLK_CLKDIV3_SDH1(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV3_SDH1DIV_Pos) /* CLKDIV4 constant definitions. */ #define NUMAKER_CLK_CLKDIV4_UART2(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV4_UART2DIV_Pos) #define NUMAKER_CLK_CLKDIV4_UART3(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV4_UART3DIV_Pos) #define NUMAKER_CLK_CLKDIV4_UART4(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV4_UART4DIV_Pos) #define NUMAKER_CLK_CLKDIV4_UART5(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV4_UART5DIV_Pos) #define NUMAKER_CLK_CLKDIV4_UART6(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV4_UART6DIV_Pos) #define NUMAKER_CLK_CLKDIV4_UART7(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV4_UART7DIV_Pos) /* CLKDIV5 constant definitions. */ #define NUMAKER_CLK_CLKDIV5_CANFD0(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV5_CANFD0DIV_Pos) #define NUMAKER_CLK_CLKDIV5_CANFD1(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV5_CANFD1DIV_Pos) #define NUMAKER_CLK_CLKDIV5_CANFD2(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV5_CANFD2DIV_Pos) #define NUMAKER_CLK_CLKDIV5_CANFD3(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV5_CANFD3DIV_Pos) #define NUMAKER_CLK_CLKDIV5_UART8(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV5_UART8DIV_Pos) #define NUMAKER_CLK_CLKDIV5_UART9(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV5_UART9DIV_Pos) #define NUMAKER_CLK_CLKDIV5_EADC2(x) (((x)-1UL) << NUMAKER_CLK_CLKDIV5_EADC2DIV_Pos) /* PCLKDIV constant definitions. */ #define NUMAKER_CLK_PCLKDIV_PCLK0DIV1 (0x0UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_PCLK0DIV2 (0x1UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_PCLK0DIV4 (0x2UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_PCLK0DIV8 (0x3UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_PCLK0DIV16 (0x4UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_PCLK1DIV1 (0x0UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) #define NUMAKER_CLK_PCLKDIV_PCLK1DIV2 (0x1UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) #define NUMAKER_CLK_PCLKDIV_PCLK1DIV4 (0x2UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) #define NUMAKER_CLK_PCLKDIV_PCLK1DIV8 (0x3UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) #define NUMAKER_CLK_PCLKDIV_PCLK1DIV16 (0x4UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) #define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos) /* MODULE constant definitions. */ /* * APBCLK(31:29)|CLKSEL(28:26)|CLKSEL_Msk(25:22)|CLKSEL_Pos(21:17)|CLKDIV(16:14)| * CLKDIV_Msk(13:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */ #define NUMAKER_MODULE_NoMsk 0x0UL #define NUMAKER_NA NUMAKER_MODULE_NoMsk #define NUMAKER_MODULE_APBCLK_ENC(x) (((x)&0x07UL) << 29) #define NUMAKER_MODULE_CLKSEL_ENC(x) (((x)&0x07UL) << 26) #define NUMAKER_MODULE_CLKSEL_Msk_ENC(x) (((x)&0x0fUL) << 22) #define NUMAKER_MODULE_CLKSEL_Pos_ENC(x) (((x)&0x1fUL) << 17) #define NUMAKER_MODULE_CLKDIV_ENC(x) (((x)&0x07UL) << 14) #define NUMAKER_MODULE_CLKDIV_Msk_ENC(x) (((x)&0x0fUL) << 10) #define NUMAKER_MODULE_CLKDIV_Pos_ENC(x) (((x)&0x1fUL) << 5) #define NUMAKER_MODULE_IP_EN_Pos_ENC(x) (((x)&0x1fUL) << 0) /* AHBCLK0 */ #define NUMAKER_PDMA0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_PDMA0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_ISP_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_ISPCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_EBI_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_EBICKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_ST_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_STCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_EMAC0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_EMAC0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(3UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(16UL)) #define NUMAKER_SDH0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_SDH0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(20UL) | NUMAKER_MODULE_CLKDIV_ENC(0UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(24UL)) #define NUMAKER_CRC_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_CRCCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_CCAP_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_CCAPCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SEN_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_SENCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(16UL) | NUMAKER_MODULE_CLKDIV_ENC(3UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(8UL)) #define NUMAKER_HSUSBD_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_HSUSBDCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_HBI_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_HBICKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_CRPT_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_CRPTCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_KS_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_KSCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPIM_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_SPIMCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_FMCIDLE_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_FMCIDLE_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_USBH_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_USBHCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(1UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(8UL) | NUMAKER_MODULE_CLKDIV_ENC(0UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0xFUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(4UL)) #define NUMAKER_SDH1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_SDH1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(22UL) | NUMAKER_MODULE_CLKDIV_ENC(3UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(24UL)) #define NUMAKER_PDMA1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_PDMA1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_TRACE_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_TRACECKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_GPA_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_GPACKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_GPB_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_GPBCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_GPC_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_GPCCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_GPD_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_GPDCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_GPE_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_GPECKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_GPF_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_GPFCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_GPG_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_GPGCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_GPH_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(0UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK0_GPHCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) /* AHBCLK1 */ #define NUMAKER_CANFD0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(4UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK1_CANFD0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(24UL) | NUMAKER_MODULE_CLKDIV_ENC(5UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(0UL)) #define NUMAKER_CANFD1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(4UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK1_CANFD1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(26UL) | NUMAKER_MODULE_CLKDIV_ENC(5UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(4UL)) #define NUMAKER_CANFD2_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(4UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK1_CANFD2CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(28UL) | NUMAKER_MODULE_CLKDIV_ENC(5UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(8UL)) #define NUMAKER_CANFD3_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(4UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK1_CANFD3CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(30UL) | NUMAKER_MODULE_CLKDIV_ENC(5UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(12UL)) #define NUMAKER_GPI_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(4UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK1_GPICKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_GPJ_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(4UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK1_GPJCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_BMC_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(4UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_AHBCLK1_BMCCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) /* APBCLK0 */ #define NUMAKER_WDT_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_WDTCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(1UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(0UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_WWDT_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_WDTCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(1UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(30UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_RTC_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_RTCCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_TMR0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_TMR0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(1UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(8UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_TMR1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_TMR1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(1UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(12UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_TMR2_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_TMR2CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(1UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(16UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_TMR3_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_TMR3CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(1UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(20UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_CLKO_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_CLKOCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(1UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(4UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_ACMP01_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_ACMP01CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_I2C0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_I2C0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_I2C1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_I2C1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_I2C2_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_I2C2CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_I2C3_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_I2C3CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_QSPI0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_QSPI0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(2UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_SPI0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(4UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_SPI1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(12UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI2_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_SPI2CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(9UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_UART0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_UART0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(1UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(24UL) | NUMAKER_MODULE_CLKDIV_ENC(0UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(8UL)) #define NUMAKER_UART1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_UART1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(1UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(26UL) | NUMAKER_MODULE_CLKDIV_ENC(0UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(12UL)) #define NUMAKER_UART2_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_UART2CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(24UL) | NUMAKER_MODULE_CLKDIV_ENC(4UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(0UL)) #define NUMAKER_UART3_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_UART3CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(26UL) | NUMAKER_MODULE_CLKDIV_ENC(4UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(4UL)) #define NUMAKER_UART4_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_UART4CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(28UL) | NUMAKER_MODULE_CLKDIV_ENC(4UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(8UL)) #define NUMAKER_UART5_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_UART5CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(30UL) | NUMAKER_MODULE_CLKDIV_ENC(4UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(12UL)) #define NUMAKER_UART6_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_UART6CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(20UL) | NUMAKER_MODULE_CLKDIV_ENC(4UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(16UL)) #define NUMAKER_UART7_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_UART7CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(22UL) | NUMAKER_MODULE_CLKDIV_ENC(4UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(20UL)) #define NUMAKER_OTG_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_OTGCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(1UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(8UL) | NUMAKER_MODULE_CLKDIV_ENC(0UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0xFUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(4UL)) #define NUMAKER_USBD_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_USBDCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(1UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(8UL) | NUMAKER_MODULE_CLKDIV_ENC(0UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0xFUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(4UL)) #define NUMAKER_EADC0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_EADC0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(10UL) | NUMAKER_MODULE_CLKDIV_ENC(0UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(16UL)) #define NUMAKER_I2S0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_I2S0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(16UL) | NUMAKER_MODULE_CLKDIV_ENC(2UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(0UL)) #define NUMAKER_HSOTG_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(1UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK0_HSOTGCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) /* APBCLK1 */ #define NUMAKER_SC0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_SC0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(0UL) | NUMAKER_MODULE_CLKDIV_ENC(1UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(0UL)) #define NUMAKER_SC1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_SC1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(2UL) | NUMAKER_MODULE_CLKDIV_ENC(1UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(8UL)) #define NUMAKER_SC2_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_SC2CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(4UL) | NUMAKER_MODULE_CLKDIV_ENC(1UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(16UL)) #define NUMAKER_I2C4_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_I2C4CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_QSPI1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_QSPI1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(10UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI3_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_SPI3CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(12UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI4_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_SPI4CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(4UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(0UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_USCI0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_USCI0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_PSIO_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_PSIOCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(28UL) | NUMAKER_MODULE_CLKDIV_ENC(1UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(24UL)) #define NUMAKER_DAC_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_DACCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_ECAP2_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_ECAP2CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_ECAP3_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_ECAP3CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_EPWM0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_EPWM0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(1UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(0UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_EPWM1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_EPWM1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(1UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(1UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_BPWM0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_BPWM0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(1UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(8UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_BPWM1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_BPWM1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(1UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(9UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_EQEI0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_EQEI0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_EQEI1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_EQEI1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_EQEI2_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_EQEI2CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_EQEI3_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_EQEI3CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_TRNG_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_TRNGCKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(1UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(27UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_ECAP0_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_ECAP0CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_ECAP1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_ECAP1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_I2S1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_I2S1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(16UL) | NUMAKER_MODULE_CLKDIV_ENC(2UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(4UL)) #define NUMAKER_EADC1_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(2UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK1_EADC1CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(12UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) /* APBCLK2 */ #define NUMAKER_KPI_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_KPICKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(3UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(6UL) | NUMAKER_MODULE_CLKDIV_ENC(2UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(8UL)) #define NUMAKER_EADC2_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_EADC2CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(0UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(14UL) | NUMAKER_MODULE_CLKDIV_ENC(2UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(24UL)) #define NUMAKER_ACMP23_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_ACMP23CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKSEL_Msk_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI5_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_SPI5CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(4UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(4UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI6_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_SPI6CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(4UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(8UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI7_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_SPI7CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(4UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(12UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI8_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_SPI8CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(4UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(16UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI9_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_SPI9CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(4UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(20UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_SPI10_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_SPI10CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(4UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(7UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(24UL) | NUMAKER_MODULE_CLKDIV_ENC(NUMAKER_NA) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(NUMAKER_NA) | NUMAKER_MODULE_CLKDIV_Pos_ENC(NUMAKER_NA)) #define NUMAKER_UART8_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_UART8CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(20UL) | NUMAKER_MODULE_CLKDIV_ENC(5UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(16UL)) #define NUMAKER_UART9_MODULE \ (NUMAKER_MODULE_APBCLK_ENC(3UL) | \ NUMAKER_MODULE_IP_EN_Pos_ENC(NUMAKER_CLK_APBCLK2_UART9CKEN_Pos) | \ NUMAKER_MODULE_CLKSEL_ENC(2UL) | NUMAKER_MODULE_CLKSEL_Msk_ENC(3UL) | \ NUMAKER_MODULE_CLKSEL_Pos_ENC(22UL) | NUMAKER_MODULE_CLKDIV_ENC(5UL) | \ NUMAKER_MODULE_CLKDIV_Msk_ENC(0x0FUL) | NUMAKER_MODULE_CLKDIV_Pos_ENC(20UL)) /* End of M460 BSP clk.h copy */ #define NUMAKER_CLK_PMUCTL_PDMSEL_PD 0x00000000 #define NUMAKER_CLK_PMUCTL_PDMSEL_LLPD 0x00000001 #define NUMAKER_CLK_PMUCTL_PDMSEL_FWPD 0x00000002 #define NUMAKER_CLK_PMUCTL_PDMSEL_SPD 0x00000004 #define NUMAKER_CLK_PMUCTL_PDMSEL_DPD 0x00000006 #endif ```
/content/code_sandbox/include/zephyr/dt-bindings/clock/numaker_m46x_clock.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
24,766
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_ #include "gd32-common.h" /** * @name Register offsets * @{ */ #define GD32_APB2RST_OFFSET 0x0CU #define GD32_APB1RST_OFFSET 0x10U #define GD32_AHBRST_OFFSET 0x28U #define GD32_ADDAPB1RST_OFFSET 0xE0U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* APB2 peripherals */ #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U) #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U) #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U) #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U) #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U) #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U) #define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U) #define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U) #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U) #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) #define GD32_RESET_ADC2 GD32_RESET_CONFIG(APB2RST, 15U) #define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 19U) #define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 20U) #define GD32_RESET_TIMER10 GD32_RESET_CONFIG(APB2RST, 21U) #define GD32_RESET_USART5 GD32_RESET_CONFIG(APB2RST, 28U) #define GD32_RESET_SHRTIMER GD32_RESET_CONFIG(APB2RST, 29U) #define GD32_RESET_CMP GD32_RESET_CONFIG(APB2RST, 31U) /* APB1 peripherals */ #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) #define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 2U) #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) #define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 6U) #define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U) #define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U) #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) #define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U) #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) #define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U) #define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U) #define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U) #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) #define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U) #define GD32_RESET_I2C2 GD32_RESET_CONFIG(APB1RST, 24U) #define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U) #define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U) #define GD32_RESET_BKPI GD32_RESET_CONFIG(APB1RST, 27U) #define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U) #define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U) /* AHB peripherals */ #define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U) #define GD32_RESET_ENET GD32_RESET_CONFIG(AHBRST, 14U) #define GD32_RESET_TMU GD32_RESET_CONFIG(AHBRST, 30U) #define GD32_RESET_SQPI GD32_RESET_CONFIG(AHBRST, 31U) /* APB1 additional peripherals */ #define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U) #define GD32_RESET_CAN2 GD32_RESET_CONFIG(ADDAPB1RST, 31U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/gd32e50x.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
1,263
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U5_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U5_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB1 0x60 #define STM32_RESET_BUS_AHB2L 0x64 #define STM32_RESET_BUS_AHB2H 0x68 #define STM32_RESET_BUS_AHB3 0x6C #define STM32_RESET_BUS_APB1L 0x74 #define STM32_RESET_BUS_APB1H 0x78 #define STM32_RESET_BUS_APB2 0x7C #define STM32_RESET_BUS_APB3 0x80 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U5_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32u5_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
180
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_ #include "gd32-common.h" /** * @name Register offsets * @{ */ #define GD32_APB2RST_OFFSET 0x0CU #define GD32_APB1RST_OFFSET 0x10U #define GD32_AHBRST_OFFSET 0x28U /** @} */ /** * @name Clock enable/disable definitions for peripherals * @{ */ /* APB2 peripherals */ #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U) #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U) #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U) #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U) #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U) #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U) #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U) #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) /* APB1 peripherals */ #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) #define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U) #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) #define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U) #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) #define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U) #define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U) #define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U) #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) #define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U) #define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U) #define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U) #define GD32_RESET_BKPI GD32_RESET_CONFIG(APB1RST, 27U) #define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U) #define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U) /* AHB peripherals */ #define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U) /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/gd32vf103.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
854
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F2_4_7_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F2_4_7_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB1 0x10 #define STM32_RESET_BUS_AHB2 0x14 #define STM32_RESET_BUS_AHB3 0x18 #define STM32_RESET_BUS_APB1 0x20 #define STM32_RESET_BUS_APB2 0x24 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F2_4_7_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32f2_4_7_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
146
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB1 0x80 #define STM32_RESET_BUS_AHB2 0x84 #define STM32_RESET_BUS_AHB3 0x7C #define STM32_RESET_BUS_AHB4 0x88 #define STM32_RESET_BUS_APB1L 0x90 #define STM32_RESET_BUS_APB1H 0x94 #define STM32_RESET_BUS_APB2 0x98 #define STM32_RESET_BUS_APB3 0x8C #define STM32_RESET_BUS_APB4 0x9C #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32h7_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
194
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32C0_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32C0_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_IOP 0x24 #define STM32_RESET_BUS_AHB1 0x28 #define STM32_RESET_BUS_APB1L 0x2C #define STM32_RESET_BUS_APB1H 0x30 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32C0_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32c0_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
127
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H #define NPCX_RESET_SWRST_CTL1_OFFSET 0 #define NPCX_RESET_SWRST_CTL2_OFFSET 32 #define NPCX_RESET_SWRST_CTL3_OFFSET 64 #define NPCX_RESET_SWRST_CTL4_OFFSET 96 #define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0) #define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1) #define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2) #define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3) #define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4) #define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5) #define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6) #define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7) #define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8) #define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9) #define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10) #define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11) #define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12) #define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13) #define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14) #define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15) #define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16) #define NPCX_RESET_ITIM32_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18) #define NPCX_RESET_ITIM32_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19) #define NPCX_RESET_ITIM32_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20) #define NPCX_RESET_ITIM32_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21) #define NPCX_RESET_ITIM32_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22) #define NPCX_RESET_ITIM32_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23) #define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25) #define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26) #define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27) #define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28) #define NPCX_RESET_GDMA1 (NPCX_RESET_SWRST_CTL1_OFFSET + 29) #define NPCX_RESET_GDMA2 (NPCX_RESET_SWRST_CTL1_OFFSET + 30) #define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0) #define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2) #define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3) #define NPCX_RESET_ADCE (NPCX_RESET_SWRST_CTL2_OFFSET + 4) #define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5) #define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6) #define NPCX_RESET_ADCI (NPCX_RESET_SWRST_CTL2_OFFSET + 7) #define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8) #define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9) #define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10) #define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11) #define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12) #define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13) #define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14) #define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15) #define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16) #define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17) #define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18) #define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19) #define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20) #define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21) #define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22) #define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23) #define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24) #define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25) #define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26) #define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27) #define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28) #define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29) #define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30) #define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31) #define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0) #define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1) #define NPCX_RESET_I3C_1 (NPCX_RESET_SWRST_CTL3_OFFSET + 4) #define NPCX_RESET_I3C_2 (NPCX_RESET_SWRST_CTL3_OFFSET + 5) #define NPCX_RESET_I3C_3 (NPCX_RESET_SWRST_CTL3_OFFSET + 6) #define NPCX_RESET_I3C_RD (NPCX_RESET_SWRST_CTL3_OFFSET + 7) #define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8) #define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9) #define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10) #define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11) #define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12) #define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13) #define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15) #define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16) #define NPCX_RESET_CRUART3 (NPCX_RESET_SWRST_CTL3_OFFSET + 18) #define NPCX_RESET_CRUART4 (NPCX_RESET_SWRST_CTL3_OFFSET + 19) #define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20) #define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22) #define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23) #define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24) #define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25) #define NPCX_RESET_SHA_2B (NPCX_RESET_SWRST_CTL3_OFFSET + 26) #define NPCX_RESET_SHA_2A (NPCX_RESET_SWRST_CTL3_OFFSET + 29) #define NPCX_RESET_MDC (NPCX_RESET_SWRST_CTL4_OFFSET + 15) #define NPCX_RESET_FIU0 (NPCX_RESET_SWRST_CTL4_OFFSET + 16) #define NPCX_RESET_FIU1 (NPCX_RESET_SWRST_CTL4_OFFSET + 17) #define NPCX_RESET_MDMA1 (NPCX_RESET_SWRST_CTL4_OFFSET + 24) #define NPCX_RESET_MDMA2 (NPCX_RESET_SWRST_CTL4_OFFSET + 25) #define NPCX_RESET_MDMA3 (NPCX_RESET_SWRST_CTL4_OFFSET + 26) #define NPCX_RESET_MDMA4 (NPCX_RESET_SWRST_CTL4_OFFSET + 27) #define NPCX_RESET_MDMA5 (NPCX_RESET_SWRST_CTL4_OFFSET + 28) #define NPCX_RESET_MDMA6 (NPCX_RESET_SWRST_CTL4_OFFSET + 29) #define NPCX_RESET_MDMA7 (NPCX_RESET_SWRST_CTL4_OFFSET + 30) #define NPCX_RESET_ID_START NPCX_RESET_GPIO0 #define NPCX_RESET_ID_END NPCX_RESET_MDMA7 #endif ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/npcx4_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
2,131
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_ /** * Pack RCC register offset and bit in one 32-bit value. * * 5 LSBs are used to keep bit number in 32-bit RCC register. * Next 12 bits are used to keep reset set register offset. * Next 12 bits are used to keep reset clear register offset. * * @param bus STM32 bus name * @param bit Reset bit */ #define STM32_RESET(bus, bit) \ (((STM32_RESET_BUS_##bus##_CLR) << 17U) | ((STM32_RESET_BUS_##bus##_SET) << 5U) | (bit)) /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB2_SET 0x998 #define STM32_RESET_BUS_AHB2_CLR 0x99C #define STM32_RESET_BUS_AHB3_SET 0x9A0 #define STM32_RESET_BUS_AHB3_CLR 0x9A4 #define STM32_RESET_BUS_AHB4_SET 0x9A8 #define STM32_RESET_BUS_AHB4_CLR 0x9AC #define STM32_RESET_BUS_AHB5_SET 0x190 #define STM32_RESET_BUS_AHB5_CLR 0x194 #define STM32_RESET_BUS_AHB6_SET 0x198 #define STM32_RESET_BUS_AHB6_CLR 0x19C #define STM32_RESET_BUS_TZAHB6_SET 0x1A0 #define STM32_RESET_BUS_TZAHB6_CLR 0x1A4 #define STM32_RESET_BUS_APB1_SET 0x980 #define STM32_RESET_BUS_APB1_CLR 0x984 #define STM32_RESET_BUS_APB2_SET 0x988 #define STM32_RESET_BUS_APB2_CLR 0x98C #define STM32_RESET_BUS_APB3_SET 0x990 #define STM32_RESET_BUS_APB3_CLR 0x994 #define STM32_RESET_BUS_APB4_SET 0x180 #define STM32_RESET_BUS_APB4_CLR 0x184 #define STM32_RESET_BUS_APB5_SET 0x188 #define STM32_RESET_BUS_APB5_CLR 0x18C #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32mp1_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
520
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_ /** * Encode RCU register offset and configuration bit. * * - 0..5: bit number * - 6..14: offset * - 15: reserved * * @param reg RCU register name (expands to GD32_{reg}_OFFSET) * @param bit Configuration bit */ #define GD32_RESET_CONFIG(reg, bit) \ (((GD32_ ## reg ## _OFFSET) << 6U) | (bit)) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/gd32-common.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
153
```objective-c /* * */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WBA_RESET_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WBA_RESET_H_ #include "stm32-common.h" /* RCC bus reset register offset */ #define STM32_RESET_BUS_AHB1 0x60 #define STM32_RESET_BUS_AHB2 0x64 #define STM32_RESET_BUS_AHB4 0x6C #define STM32_RESET_BUS_AHB5 0x70 #define STM32_RESET_BUS_APB1L 0x74 #define STM32_RESET_BUS_APB1H 0x78 #define STM32_RESET_BUS_APB2 0x7C #define STM32_RESET_BUS_APB7 0x80 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WBA_RESET_H_ */ ```
/content/code_sandbox/include/zephyr/dt-bindings/reset/stm32wba_reset.h
objective-c
2016-05-26T17:54:19
2024-08-16T18:09:06
zephyr
zephyrproject-rtos/zephyr
10,307
180