code
string |
|---|
// DESCRIPTION: Verilator: Verilog Test for generate IF constants
//
// The given generate loop should have a constant expression as argument. This
// test checks it really does evaluate as constant.
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2012 by Jeremy Bennett.
`define MAX_SIZE 4
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Set the parameters, so that we use a size less than MAX_SIZE
test_gen
#(.SIZE (2),
.MASK (4'b1111))
i_test_gen (.clk (clk));
// This is only a compilation test, but for good measure we do one clock
// cycle.
integer count;
initial begin
count = 0;
end
always @(posedge clk) begin
if (count == 1) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
count = count + 1;
end
end
endmodule // t
module test_gen
#( parameter
SIZE = `MAX_SIZE,
MASK = `MAX_SIZE'b0)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// Generate blocks that rely on short-circuiting of the logic to avoid
// errors.
generate
if ((SIZE < 8'h04) && MASK[0]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Generate IF MASK[0] = %d\n", MASK[0]);
`endif
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test of the export parameter used with modport
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett.
interface test_if;
// Pre-declare function
extern function myfunc (input logic val);
// Interface variable
logic data;
// Modport
modport mp_e(
export myfunc,
output data
);
// Modport
modport mp_i(
import myfunc,
output data
);
endinterface // test_if
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
test_if i ();
testmod_callee testmod_callee_i (.ie (i.mp_e));
testmod_caller testmod_caller_i (.clk (clk),
.ii (i.mp_i));
endmodule
module testmod_callee
(
test_if.mp_e ie
);
function automatic logic ie.myfunc (input logic val);
begin
myfunc = (val == 1'b0);
end
endfunction
endmodule // testmod_caller
module testmod_caller
(
input clk,
test_if.mp_i ii
);
always @(posedge clk) begin
ii.data = 1'b0;
if (ii.myfunc (1'b0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
wire GSR;
task setGSR;
/* verilator public */
input value;
GSR = value;
endtask
`else
wire GSR /*verilator public*/;
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
module pipeline_bridge_PERIPHERALS_downstream_adapter (
// inputs:
m1_clk,
m1_endofpacket,
m1_readdata,
m1_readdatavalid,
m1_reset_n,
m1_waitrequest,
s1_address,
s1_arbiterlock,
s1_arbiterlock2,
s1_burstcount,
s1_byteenable,
s1_chipselect,
s1_debugaccess,
s1_nativeaddress,
s1_read,
s1_write,
s1_writedata,
// outputs:
m1_address,
m1_arbiterlock,
m1_arbiterlock2,
m1_burstcount,
m1_byteenable,
m1_chipselect,
m1_debugaccess,
m1_nativeaddress,
m1_read,
m1_write,
m1_writedata,
s1_endofpacket,
s1_readdata,
s1_readdatavalid,
s1_waitrequest
)
;output [ 11: 0] m1_address;
output m1_arbiterlock;
output m1_arbiterlock2;
output m1_burstcount;
output [ 3: 0] m1_byteenable;
output m1_chipselect;
output m1_debugaccess;
output [ 9: 0] m1_nativeaddress;
output m1_read;
output m1_write;
output [ 31: 0] m1_writedata;
output s1_endofpacket;
output [ 31: 0] s1_readdata;
output s1_readdatavalid;
output s1_waitrequest;
input m1_clk;
input m1_endofpacket;
input [ 31: 0] m1_readdata;
input m1_readdatavalid;
input m1_reset_n;
input m1_waitrequest;
input [ 11: 0] s1_address;
input s1_arbiterlock;
input s1_arbiterlock2;
input s1_burstcount;
input [ 3: 0] s1_byteenable;
input s1_chipselect;
input s1_debugaccess;
input [ 9: 0] s1_nativeaddress;
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'hf0afc2bfa78277c5) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
// Test empty cases
casez (in[0])
endcase
casez (in)
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
// Same pattern, but reversed to test we work OK.
24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
function integer get_baz(input integer bar);
get_baz = bar;
$fatal(2, "boom");
endfunction
module foo #(parameter BAR = 0);
localparam integer BAZ = get_baz(BAR);
endmodule
module foo2 #(parameter QUX = 0);
genvar x;
generate
for (x = 0; x < 2; x++) begin: foo2_loop
foo #(.BAR (QUX + x)) foo_in_foo2_inst();
end
endgenerate
endmodule
module t;
genvar i, j;
generate
for (i = 0; i < 2; i++) begin: genloop
foo #(.BAR (i)) foo_inst();
end
for (i = 2; i < 4; i++) begin: gen_l1
for (j = 0; j < 2; j++) begin: gen_l2
foo #(.BAR (i + j*2)) foo_inst2();
end
end
if (1 == 1) begin: cond_true
foo #(.BAR (6)) foo_inst3();
end
if (1 == 1) begin // unnamed
foo #(.BAR (7)) foo_inst4();
end
for (i = 8; i < 12; i = i + 2) begin: nested_loop
foo2 #(.QUX (i)) foo2_inst();
end
endgenerate
endmodule
|
// This module generates M pairs of N-1 bits unsigned numbers A, B
// and also serialises them starting from LSB bits between
// activation of active-high reset signal
module stimulus #(parameter N = 4, M = 10) (input clk,
output reg reset,
output reg sa, sb,
output reg unsigned [N-1:0] A, B );
parameter D = 5;
int unsigned i;
reg unsigned [N-1:0] r1, r2;
initial begin
repeat(M) begin
r1 = {$random} % N;
r2 = {$random} % N;
do_items(r1, r2);
end
end
task do_items (input unsigned [N-1:0] v1, v2);
begin
A = 0; B = 0; reset = 0;
do_reset();
A = v1; B = v2;
for (i=0; i<N; i=i+1) begin
#2 sa = A[i];
sb = B[i];
@(posedge clk);
end
#2 sa = 1'b0;
sb = 1'b0;
@(posedge clk);
end
endtask
task do_reset;
begin
@(posedge clk);
@(negedge clk) reset = 1'b1;
repeat(D) @(negedge clk);
reset = 1'b0;
end
endtask
endmodule
// This module takes M pairs of N-1 bits unsigned numbers A, B and a serial stream ss
// then it checks that following a negedge of a reset, after N positive clock cycles
// the reconstuction of N ss bits is equal to A+B.
module check #(parameter N = 4, M = 10)(input clk, reset, input unsigned [N-1:0] A, B, input ss);
reg unsigned [N:0] psum;
reg unsigned [N:0] ssum;
int unsigned i;
initial begin
repeat(M)
check_item();
end
task check_item;
begin
@(posedge reset);
@(negedge reset);
#2;
psum = A + B;
for (i=0; i<=N; i=i+1) begin
@(posedge clk);
#1;
ssum[i] = ss;
end
if (psum != ssum) begin
$display("ERROR");
$finish;
end
end
endtask
endmodule
module test;
parameter N = 8, M = 25;
parameter T = 10;
parameter S = (N+1+6)*M*T + 100; // 6 is duration of a reset
reg reset, clk;
wire sa, sb, ss;
wire [N-1:0] A, B;
initial begin
clk = 0;
forever #(T/2) clk = ~clk;
end
stimulus #(N, M) stim (.clk(clk), .reset(reset), .sa(sa), .sb(sb), .A(A), .B(B));
sa1 duv (.clk(clk), .reset(reset), .a_i(sa), .b_i(sb), .s_o(ss) );
check #(N, M) check (.clk(clk), .reset(reset), .A(A), .B(B), .ss(ss));
initial begin
#S;
$display("PASSED");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
reg [15:0] onebit;
sub #(1)
sub0 (allbits, onebit[1:0], bitout[10]),
sub1 (allbits, onebit[3:2], bitout[11]),
sub2 (allbits, onebit[5:4], bitout[12]),
sub3 (allbits, onebit[7:6], bitout[13]),
sub4 (allbits, onebit[9:8], bitout[14]),
sub5 (allbits, onebit[11:10], bitout[15]),
sub6 (allbits, onebit[13:12], bitout[16]),
sub7 (allbits, onebit[15:14], bitout[17]);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
allbits <= 8'hac;
onebit <= 16'hc01a;
end
if (cyc==2) begin
if (bitout !== 8'h07) $stop;
allbits <= 8'hca;
onebit <= 16'h1f01;
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
if (sub0.bitout !== 1'b1) $stop;
if (sub1.bitout !== 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
`INLINE_MODULE
parameter integer P = 0;
initial if (P != 1) $stop;
wire bitout = (^ onebit) ^ (^ allbits);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [2:0] sum;
wire [2:0] in = crc[2:0];
wire [2:0] out;
MxN_pipeline pipe (in, out, clk);
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 3'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[1:0],sum[2]} ^ out;
end
else if (cyc==99) begin
if (crc !== 8'b01110000) $stop;
if (sum !== 3'h3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module dffn (q,d,clk);
parameter BITS = 1;
input [BITS-1:0] d;
output reg [BITS-1:0] q;
input clk;
always @ (posedge clk) begin
q <= d;
end
endmodule
module MxN_pipeline (in, out, clk);
parameter M=3, N=4;
input [M-1:0] in;
output [M-1:0] out;
input clk;
// Unsupported: Per-bit array instantiations with output connections to non-wires.
//wire [M*(N-1):1] t;
//dffn #(M) p[N:1] ({out,t},{t,in},clk);
wire [M*(N-1):1] w;
wire [M*N:1] q;
dffn #(M) p[N:1] (q,{w,in},clk);
assign {out,w} = q;
endmodule
|
module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
ign, ign2, ign3,
// Inputs
clk
);
input clk;
output [31:0] ign;
output [3:0] ign2;
output [11:0] ign3;
parameter [95:0] P6 = 6;
localparam P64 = (1 << P6);
// verilator lint_off WIDTH
localparam [4:0] PBIG23 = 1'b1 << ~73'b0;
localparam [3:0] PBIG29 = 4'b1 << 33'h100000000;
// verilator lint_on WIDTH
reg [31:0] right;
reg [31:0] left;
reg [P64-1:0] qright;
reg [P64-1:0] qleft;
reg [31:0] amt;
assign ign = {31'h0, clk} >>> 4'bx; // bug760
assign ign2 = {amt[1:0] >> {22{amt[5:2]}}, amt[1:0] << (0 <<< amt[5:2])}; // bug1174
assign ign3 = {amt[1:0] >> {22{amt[5:2]}},
amt[1:0] >> {11{amt[5:2]}},
$signed(amt[1:0]) >>> {22{amt[5:2]}},
$signed(amt[1:0]) >>> {11{amt[5:2]}},
amt[1:0] << {22{amt[5:2]}},
amt[1:0] << {11{amt[5:2]}}};
always @* begin
right = 32'h819b018a >> amt;
left = 32'h819b018a << amt;
qright = 64'hf784bf8f_12734089 >> amt;
qleft = 64'hf784bf8f_12734089 >> amt;
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x\\n", cyc, left, right, qleft, qright);
`endif
if (cyc==1) begin
amt <= 32'd0;
if (P64 != 64) $stop;
if (5'b10110>>2 != 5'b00101) $stop;
if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
if (5'b10110<<2 != 5'b11000) $stop;
if (5'b10110<<<2 != 5'b11000) $stop;
if (5'sb10110>>2 != 5'sb00101) $stop;
if (5'sb10110>>>2 != 5'sb11101) $stop;
if (5'sb10110<<2 != 5'sb11000) $stop;
if (5'sb10110<<<2 != 5'sb11000) $stop;
// Allow >64 bit shifts if the shift amount is a constant
if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop;
end
if (cyc==2) begin
amt <= 32'd28;
if (left != 32'h819b018a) $stop;
if (right != 32'h819b018a) $stop;
if (qleft != 64'hf784bf8f_12734089) $stop;
if (qright != 64'hf784bf8f_12734089) $stop;
end
if (cyc==3) begin
amt <= 32'd31;
if (left != 32'ha0000000) $stop;
if (right != 32'h8) $stop;
if (qleft != 64'h0000000f784bf8f1) $stop;
if (qright != 64'h0000000f784bf8f1) $stop;
end
if (cyc==4) begin
amt <= 32'd32;
if (left != 32'h0) $stop;
if (right != 32'h1) $stop;
if (qleft != 64'h00000001ef097f1e) $stop;
if (qright != 64'h00000001ef097f1e) $stop;
end
if (cyc==5) begin
amt <= 32'd33;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h00000000f784bf8f) $stop;
if (qright != 64'h00000000f784bf8f) $stop;
end
if (cyc==6) begin
amt <= 32'd64;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h000000007bc25fc7) $stop;
if (qright != 64'h000000007bc25fc7) $stop;
end
if (cyc==7) begin
amt <= 32'd128;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==8) begin
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\\n");
$finish;
end
end
end
endmodule
|
module pipeline_bridge_PERIPHERAL_waitrequest_adapter (
// inputs:
m1_endofpacket,
m1_readdata,
m1_readdatavalid,
m1_waitrequest,
s1_address,
s1_arbiterlock,
s1_arbiterlock2,
s1_burstcount,
s1_byteenable,
s1_chipselect,
s1_debugaccess,
s1_nativeaddress,
s1_read,
s1_write,
s1_writedata,
// outputs:
m1_address,
m1_arbiterlock,
m1_arbiterlock2,
m1_burstcount,
m1_byteenable,
m1_chipselect,
m1_debugaccess,
m1_nativeaddress,
m1_read,
m1_write,
m1_writedata,
s1_endofpacket,
s1_readdata,
s1_readdatavalid,
s1_waitrequest
)
;output [ 14: 0] m1_address;
output m1_arbiterlock;
output m1_arbiterlock2;
output m1_burstcount;
output [ 3: 0] m1_byteenable;
output m1_chipselect;
output m1_debugaccess;
output [ 12: 0] m1_nativeaddress;
output m1_read;
output m1_write;
output [ 31: 0] m1_writedata;
output s1_endofpacket;
output [ 31: 0] s1_readdata;
output s1_readdatavalid;
output s1_waitrequest;
input m1_endofpacket;
input [ 31: 0] m1_readdata;
input m1_readdatavalid;
input m1_waitrequest;
input [ 14: 0] s1_address;
input s1_arbiterlock;
input s1_arbiterlock2;
input s1_burstcount;
input [ 3: 0] s1_byteenable;
input s1_chipselect;
input s1_debugaccess;
input [ 12: 0] s1_nativeaddress;
input s1_read;
input s1_write;
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
// bug823
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [6:0] in = crc[6:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] mask; // From test of Test.v
wire [3:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
.mask (mask[3:0]),
// Inputs
.clk (clk),
.in (in[6:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out & mask};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e9d3a74e9d3f656
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, mask,
// Inputs
clk, in
);
input clk;
input [6:0] in; // Note much wider than any index
output reg [3:0] out;
output reg [3:0] mask;
localparam [15:5] p = 11'h1ac;
always @(posedge clk) begin
// verilator lint_off WIDTH
out <= p[15 + in -: 5];
// verilator lint_on WIDTH
mask[3] <= ((15 + in - 5) < 12);
mask[2] <= ((15 + in - 5) < 13);
mask[1] <= ((15 + in - 5) < 14);
mask[0] <= ((15 + in - 5) < 15);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire b;
reg reset;
integer cyc=0;
Testit testit (/*AUTOINST*/
// Outputs
.b (b),
// Inputs
.clk (clk),
.reset (reset));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
reset <= 1'b0;
end
else if (cyc<10) begin
reset <= 1'b1;
end
else if (cyc<90) begin
reset <= 1'b0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Testit (clk, reset, b);
input clk;
input reset;
output b;
wire [0:0] c;
wire my_sig;
wire [0:0] d;
genvar i;
generate
for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
fnxtclk fnxtclk1
(.u(c[i]),
.reset(reset),
.clk(clk),
.w(d[i]) );
end
endgenerate
assign b = d[0];
assign c[0] = my_sig;
assign my_sig = 1'b1;
endmodule
module fnxtclk (u, reset, clk, w );
input u;
input reset;
input clk;
output reg w;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
w <= 1'b0;
end
else begin
w <= u;
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////
//
// copyright (c) 2020 akilesh kannan <akileshkannan@gmail.com>
//
// file: boothmultiplier4bit.v
// modified: 2020-07-15
// description: 4 bit booth multiplier
// signed multiplication
//
// license: mit
//
////////////////////////////////////////////////////////////////////////
`default_nettype none
`timescale 1ns/1ps
module boothmultiplier4bit(output reg[7:0] prod, output reg busy, input[3:0] mc, input[3:0] mp, input clk, input start);
reg [3:0] a, q, m;
reg q_1;
reg [2:0] count;
wire [3:0] sum, difference;
always @(posedge clk) begin
if (start) begin
a <= 0;
m <= mc;
q <= mp;
q_1 <= 1'b0;
count <= 0;
end
else begin
busy <= 1'b1;
case ({q[0], q_1})
2'b0_1 : {a, q, q_1} <= {sum[3], sum, q};
2'b1_0 : {a, q, q_1} <= {difference[3], difference, q};
default: {a, q, q_1} <= {a[3], a, q};
endcase
count <= count + 1'b1;
if(count == 4) begin
busy <= 1'b0;
prod <= {a, q};
count <= 0;
end
end
end
assign sum = a + m;
assign difference = a + ~m + 1'b1;
endmodule
|
// DESCRIPTION:tor:ilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [31:0] o;
wire [31:0] oe;
Test test (/*AUTOINST*/
// Outputs
.o (o[31:0]),
.oe (oe[31:0]));
// Test loop
always @ (posedge clk) begin
if (o !== 32'h00000001) $stop;
if (oe !== 32'h00000001) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module subimp(o,oe);
output [31:0] o;
assign o = 32'h12345679;
output [31:0] oe;
assign oe = 32'hab345679;
endmodule
module Test(o,oe);
output [31:0] o;
output [31:0] oe;
wire [31:0] xe;
assign xe[31:1] = 0;
// verilator lint_off IMPLICIT
// verilator lint_off WIDTH
subimp subimp(x, // x is implicit and one bit
xe[0]); // xe explicit one bit
assign o = x;
assign oe = xe;
// verilator lint_on WIDTH
// verilator lint_on IMPLICIT
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t;
// verilator lint_off PINMISSING
`ifdef T_GEN_MISSING_BAD
foobar #(.FOO_TYPE(1)) foobar; // This means we should instatiate missing module
`elsif T_GEN_MISSING
foobar #(.FOO_TYPE(0)) foobar; // This means we should instatiate foo0
`else
`error "Bad Test"
`endif
endmodule
module foobar
#( parameter
FOO_START = 0,
FOO_NUM = 2,
FOO_TYPE = 1
)
(
input wire[FOO_NUM-1:0] foo,
output wire[FOO_NUM-1:0] bar);
generate
begin: g
genvar j;
for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1)
begin: foo_inst;
if (FOO_TYPE == 0)
begin: foo_0
// instatiate foo0
foo0 i_foo(.x(foo[j]), .y(bar[j]));
end
if (FOO_TYPE == 1)
begin: foo_1
// instatiate foo1
foo_not_needed i_foo(.x(foo[j]), .y(bar[j]));
end
end
end
endgenerate
endmodule
module foo0(input wire x, output wire y);
assign y = ~x;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [71:0] muxed; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {muxed[63:0]};
wire [5:0] width_check = cyc[5:0] + 1;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
muxed,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [71:0] muxed;
wire [71:0] a = {in[7:0],~in[31:0],in[31:0]};
wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]};
/*AUTOWIRE*/
Muxer muxer (
.sa (0),
.sb (in[0]),
/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.a (a[71:0]),
.b (b[71:0]));
endmodule
module Muxer (/*AUTOARG*/
// Outputs
muxed,
// Inputs
sa, sb, a, b
);
input sa;
input sb;
output wire [71:0] muxed;
input [71:0] a;
input [71:0] b;
// Constification wasn't sizing with inlining and gave
// unsized error on below
// v
assign muxed = (({72{sa}} & a)
| ({72{sb}} & b));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [63:0] rf;
reg [63:0] rf2;
reg [63:0] biu;
reg b;
always @* begin
rf[63:32] = biu[63:32] & {32{b}};
rf[31:0] = {32{b}};
rf2 = rf;
rf2[31:0] = ~{32{b}};
end
reg [31:0] src1, src0, sr, mask;
wire [31:0] dualasr
= ((| src1[31:4])
? {{16{src0[31]}}, {16{src0[15]}}}
: ( ( sr & {2{mask[31:16]}})
| ( {{16{src0[31]}}, {16{src0[15]}}}
& {2{~mask[31:16]}})));
wire [31:0] sl_mask
= (32'hffffffff << src1[4:0]);
wire [31:0] sr_mask
= {sl_mask[0], sl_mask[1],
sl_mask[2], sl_mask[3], sl_mask[4],
sl_mask[5], sl_mask[6], sl_mask[7],
sl_mask[8], sl_mask[9],
sl_mask[10], sl_mask[11],
sl_mask[12], sl_mask[13], sl_mask[14],
sl_mask[15], sl_mask[16],
sl_mask[17], sl_mask[18], sl_mask[19],
sl_mask[20], sl_mask[21],
sl_mask[22], sl_mask[23], sl_mask[24],
sl_mask[25], sl_mask[26],
sl_mask[27], sl_mask[28], sl_mask[29],
sl_mask[30], sl_mask[31]};
wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}};
wire [1:0] w = {2{b}};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep);
`endif
if (cyc==1) begin
biu <= 64'h12451282_abadee00;
b <= 1'b0;
src1 <= 32'h00000001;
src0 <= 32'h9a4f1235;
sr <= 32'h0f19f567;
mask <= 32'h7af07ab4;
end
if (cyc==2) begin
biu <= 64'h12453382_abad8801;
b <= 1'b1;
if (rf != 64'h0) $stop;
if (rf2 != 64'h00000000ffffffff) $stop;
src1 <= 32'h0010000f;
src0 <= 32'h028aa336;
sr <= 32'h42ad0377;
mask <= 32'h1ab3b906;
if (dualasr != 32'h8f1f7060) $stop;
if (sl_mask != 32'hfffffffe) $stop;
if (sr_mask != 32'h7fffffff) $stop;
if (widerep != '0) $stop;
end
if (cyc==3) begin
biu <= 64'h12422382_77ad8802;
b <= 1'b1;
if (rf != 64'h12453382ffffffff) $stop;
if (rf2 != 64'h1245338200000000) $stop;
src1 <= 32'h0000000f;
src0 <= 32'h5c158f71;
sr <= 32'h7076c40a;
mask <= 32'h33eb3d44;
if (dualasr != 32'h0000ffff) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
if (widerep != '1) $stop;
end
if (cyc==4) begin
if (rf != 64'h12422382ffffffff) $stop;
if (rf2 != 64'h1242238200000000) $stop;
if (dualasr != 32'h3062cc1e) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
$write("*-* All Finished *-*\n");
if (widerep != '1) $stop;
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
`ifndef verilator // Unsupported
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}
// option.goal = {number}; // Default 90%
// option.name = {string}
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Check empty blocks
task EmptyFor;
/* verilator public */
integer i;
begin
for (i = 0; i < 2; i = i+1)
begin
end
end
endtask
// Check look unroller
reg signed signed_tests_only = 1'sb1;
integer total;
integer i;
reg [31:0] iu;
reg [31:0] dly_to_ensure_was_unrolled [1:0];
reg [2:0] i3;
integer cyc; initial cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
case (cyc)
1: begin
// >= signed
total = 0;
for (i=5; i>=0; i=i-1) begin
total = total - i -1;
dly_to_ensure_was_unrolled[i] <= i;
end
if (total != -21) $stop;
end
2: begin
// > signed
total = 0;
for (i=5; i>0; i=i-1) begin
total = total - i -1;
dly_to_ensure_was_unrolled[i] <= i;
end
if (total != -20) $stop;
end
3: begin
// < signed
total = 0;
for (i=1; i<5; i=i+1) begin
total = total - i -1;
dly_to_ensure_was_unrolled[i] <= i;
end
if (total != -14) $stop;
end
4: begin
// <= signed
total = 0;
for (i=1; i<=5; i=i+1) begin
total = total - i -1;
dly_to_ensure_was_unrolled[i] <= i;
end
if (total != -20) $stop;
end
// UNSIGNED
5: begin
// >= unsigned
total = 0;
for (iu=5; iu>=1; iu=iu-1) begin
total = total - iu -1;
dly_to_ensure_was_unrolled[iu] <= iu;
end
if (total != -20) $stop;
end
6: begin
// > unsigned
total = 0;
for (iu=5; iu>1; iu=iu-1) begin
total = total - iu -1;
dly_to_ensure_was_unrolled[iu] <= iu;
end
if (total != -18) $stop;
end
7: begin
// < unsigned
total = 0;
for (iu=1; iu<5; iu=iu+1) begin
total = total - iu -1;
dly_to_ensure_was_unrolled[iu] <= iu;
end
if (total != -14) $stop;
end
8: begin
// <= unsigned
total = 0;
for (iu=1; iu<=5; iu=iu+1) begin
total = total - iu -1;
dly_to_ensure_was_unrolled[iu] <= iu;
end
if (total != -20) $stop;
end
//===
9: begin
// mostly cover a small index
total = 0;
for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin
total = total - {29'd0,i3} -1;
dly_to_ensure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
10: begin
// mostly cover a small index
total = 0;
for (i3=0; i3<3'd7; i3=i3+3'd1) begin
total = total - {29'd0,i3} -1;
dly_to_ensure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
11: begin
// width violation on <, causes extend
total = 0;
for (i3=3'd0; i3<7; i3=i3+1) begin
total = total - {29'd0,i3} -1;
dly_to_ensure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
// width violation on <, causes extend signed
// Unsupported as yet
//===
19: begin
$write("*-* All Finished *-*\\n");
$finish;
end
default: ;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// bug789 generates
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(1) itopa();
ifc #(2) itopb();
sub #(1) ca (.isub(itopa),
.i_value(4));
sub #(2) cb (.isub(itopb),
.i_value(5));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (itopa.MODE != 1) $stop;
if (itopb.MODE != 2) $stop;
end
if (cyc==20) begin
if (itopa.i != 4) $stop;
if (itopb.i != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub
#(parameter MODE = 0)
(
ifc isub,
input integer i_value
);
// Commercial unsupported Xmrs into scopes within interfaces
generate
always_comb isub.i = i_value;
endgenerate
endmodule
interface ifc;
parameter MODE = 0;
// Commercial unsupported Xmrs into scopes within interfaces
generate
integer i;
endgenerate
endinterface
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
wire GSR;
task setGSR;
/* verilator public */
input value;
GSR = value;
endtask
`else
wire GSR /*verilator public*/;
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg posedge_wr_clocks;
reg prev_wr_clocks;
reg [31:0] m_din;
reg [31:0] m_dout;
always @(negedge clk) begin
prev_wr_clocks = 0;
end
reg comb_pos_1;
reg comb_prev_1;
always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin
comb_pos_1 = (clk &~ prev_wr_clocks);
comb_prev_1 = comb_pos_1 | posedge_wr_clocks;
comb_pos_1 = 1'b1;
end
always @ (posedge clk) begin
posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS
prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS
if (posedge_wr_clocks) begin
//$write("[%0t] Wrclk\n", $time);
m_dout <= m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'hfeed;
end
if (cyc==2) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'he11e;
end
if (cyc==3) begin
m_din <= 32'he22e;
$write(" %x\n",comb_pos_1);
if (m_dout!=32'hfeed) $stop;
end
if (cyc==4) begin
if (m_dout!=32'he11e) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [83:4] from;
reg [83:4] to;
reg [6:0] bitn;
reg [3:0] nibblep;
reg [3:0] nibblem;
reg [7:0] cyc; initial cyc=0;
always @* begin
nibblep = from[bitn +: 4];
nibblem = from[bitn -: 4];
to = from;
to[bitn +: 4] = cyc[3:0];
to[bitn -: 4] = cyc[3:0];
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n",$time, cyc, nibblep, nibblem, from^to);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end
8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end
8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -:
8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end
8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +:
8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc
8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc
8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end
8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate
8'd09: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
case (cyc)
8'd00: ;
8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end
8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end
8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end
8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end
8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end
8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end
8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end
8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end
8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end
default: $stop;
endcase
case (cyc)
8'd00: ;
8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end
8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end
8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end
8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end
8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0
8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0
8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end
8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end
8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end
default: $stop;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [255:0] a;
reg [60:0] divisor;
reg [60:0] qq;
reg [60:0] rq;
reg [60:0] qq4;
reg [60:0] rq4;
reg [60:0] qq5;
reg [60:0] rq5;
reg signed [60:0] qqs;
reg signed [60:0] rqs;
always @* begin
qq = a[60:0] / divisor;
rq = a[60:0] % divisor;
qq4 = a[60:0] / 4; // Check power-of-two constification
rq4 = a[60:0] % 4;
qq5 = a[60:0] / 5; // Non power-of-two
rq5 = a[60:0] % 5;
qqs = $signed(a[60:0]) / $signed(divisor);
rqs = $signed(a[60:0]) % $signed(divisor);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs);
if (cyc==1) begin
a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
divisor <= 61'h12371;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
end
if (cyc > 1) begin
if (qq4 != {2'b0, a[60:2]}) $stop;
if (rq4 != {59'h0, a[1:0]}) $stop;
end
if (cyc==2) begin
a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
divisor <= 61'h1238123771;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
if (qq!==61'h00000403ad81c0da) $stop;
if (rq!==61'h00000000000090ec) $stop;
if (qqs!==61'h00000403ad81c0da) $stop;
if (rqs!==61'h00000000000090ec) $stop;
if (qq4 != 61'h01247cf6851f9fc9) $stop;
if (rq4 != 61'h0000000000000002) $stop;
end
if (cyc==3) begin
a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8;
divisor <= 61'hf1b;
a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed
if (qq!==61'h000000000090832e) $stop;
if (rq!==61'h0000000334becc6a) $stop;
if (qqs!==61'h000000000090832e) $stop;
if (rqs!==61'h0000000334becc6a) $stop;
if (qq4 != 61'h0292380e727ce56e) $stop;
if (rq4 != 61'h0000000000000000) $stop;
end
if (cyc==4) begin
a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0001eda37cca1be8) $stop;
if (rq!==61'h0000000000000c40) $stop;
if (qqs!==61'h1fffcf5187c76510) $stop;
if (rqs!==61'h1ffffffffffffd08) $stop;
if (qq4 != 61'h07482923803ce56e) $stop;
if (rq4 != 61'h0000000000000000) $stop;
end
if (cyc==5) begin
a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0000000000000000) $stop;
if (rq!==61'h0d20a48e00f395b8) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h0d20a48e00f395b8) $stop;
end
if (cyc==6) begin
if (qq!==61'h0000000000000001) $stop;
if (rq!==61'h0d20a48e00f3869d) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h1d20a48e00f395b8) $stop;
end
// Div by zero
if (cyc==9) begin
divisor <= 61'd0;
end
if (cyc==10) begin
`ifdef verilator
if (qq !== {61{1'b0}}) $stop;
if (rq !== {61{1'b0}}) $stop;
`else
if (qq !== {61{1'bx}}) $stop;
if (rq !== {61{1'bx}}) $stop;
`endif
if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors
if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors
end
if (cyc==19) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire b;
reg reset;
integer cyc=0;
Testit testit (/*AUTOINST*/
// Outputs
.b (b),
// Inputs
.clk (clk),
.reset (reset));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
reset <= 1'b0;
end
else if (cyc<10) begin
reset <= 1'b1;
end
else if (cyc<90) begin
reset <= 1'b0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Testit (clk, reset, b);
input clk;
input reset;
output b;
wire [0:0] c;
wire my_sig;
wire [0:0] d;
genvar i;
generate
for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
fnxtclk fnxtclk1
(.u(c[i]),
.reset(reset),
.clk(clk),
.w(d[i]) );
end
endgenerate
assign b = d[0];
assign c[0] = my_sig;
assign my_sig = 1'b1;
endmodule
module fnxtclk (u, reset, clk, w );
input u;
input reset;
input clk;
output reg w;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
w <= 1'b0;
end
else begin
w <= u;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [1:0] clkvec = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef T_TEST1
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
`endif
`ifdef T_TEST2
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
`endif
`ifdef T_TEST3
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
`endif
|
// Model of FIFO in Altera
module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 2048;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output wrempty;
output [10:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [10:0] rdusedw;
reg [10:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo_1c_2k
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
reg enable;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.enable (enable),
.in (in[31:0]));
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset, enable, in
);
input clk;
input reset;
input enable;
input [31:0] in;
output [31:0] out;
// No gating
reg [31:0] d10;
always @(posedge clk) begin
d10 <= in;
end
reg displayit;
`ifdef VERILATOR // Harder test
initial displayit = $c1("0"); // Something that won't optimize away
`else
initial displayit = '0;
`endif
// Obvious gating + PLI
reg [31:0] d20;
always @(posedge clk) begin
if (enable) begin
d20 <= d10; // Obvious gating
if (displayit) begin
$display("hello!"); // Must glob with other PLI statements
end
end
end
// Reset means second-level gating
reg [31:0] d30, d31a, d31b, d32;
always @(posedge clk) begin
d32 <= d31b;
if (reset) begin
d30 <= 32'h0;
d31a <= 32'h0;
d31b <= 32'h0;
d32 <= 32'h0; // Overlaps above, just to make things interesting
end
else begin
// Mix two outputs
d30 <= d20;
if (enable) begin
d31a <= d30;
d31b <= d31a;
end
end
end
// Multiple ORs for gater
reg [31:0] d40a,d40b;
always @(posedge clk) begin
if (reset) begin
d40a <= 32'h0;
d40b <= 32'h0;
end
if (enable) begin
d40a <= d32;
d40b <= d40a;
end
end
// Non-optimizable
reg [31:0] d91, d92;
reg [31:0] inverted;
always @(posedge clk) begin
inverted = ~d40b;
if (reset) begin
d91 <= 32'h0;
end
else begin
if (enable) begin
d91 <= inverted;
end
else begin
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
end
end
end
wire [31:0] out = d91 ^ d92;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverybkb_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./contact_discoverybkb_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverybkb(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
contact_discoverybkb_ram contact_discoverybkb_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
// Model of FIFO in Altera
module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 2048;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output wrempty;
output [10:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [10:0] rdusedw;
reg [10:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo_1c_2k
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Chris Randall.
// SPDX-License-Identifier: CC0-1.0
interface ifc;
integer value;
modport out_modport (output value);
endinterface
module m
(
input clk_ip, // verilator tag clk_ip
input rst_ip,
output foo_op); // verilator tag foo_op
// This is a comment
typedef struct packed {
logic clk; /* verilator tag this is clk */
logic k; /* verilator lint_off UNUSED */
logic enable; // verilator tag enable
logic data; // verilator tag data
} my_struct; // verilator tag my_struct
// This is a comment
ifc itop();
my_struct this_struct [2]; // verilator tag this_struct
wire [31:0] dotted = itop.value;
function f(input string m);
$display("%s", m);
endfunction
initial begin
// Contains all 256 characters except 0 (null character)
f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff");
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_clk (/*AUTOARG*/
// Outputs
passed,
// Inputs
fastclk, clk, reset_l
);
input fastclk;
input clk;
input reset_l;
output passed; reg passed; initial passed = 0;
// surefire lint_off STMINI
// surefire lint_off CWECSB
// surefire lint_off NBAJAM
reg _ranit; initial _ranit=0;
// surefire lint_off UDDSMX
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
wire [7:0] clk_clocks_d1r;
wire [7:0] clk_clocks_d1sr;
wire [7:0] clk_clocks_cp2_d1r;
wire [7:0] clk_clocks_cp2_d1sr;
// verilator lint_off MULTIDRIVEN
reg [7:0] int_clocks; initial int_clocks = 0;
// verilator lint_on MULTIDRIVEN
reg [7:0] int_clocks_copy;
// verilator lint_off GENCLK
reg internal_clk; initial internal_clk = 0;
reg reset_int_;
// verilator lint_on GENCLK
always @ (posedge clk) begin
//$write("CLK1 %x\n", reset_l);
if (!reset_l) begin
clk_clocks <= 0;
int_clocks <= 0;
internal_clk <= 1'b1;
reset_int_ <= 0;
end
else begin
internal_clk <= ~internal_clk;
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_clk: Running\n",$time);
reset_int_ <= 1;
end
end
end
reg [7:0] sig_rst;
always @ (posedge clk or negedge reset_l) begin
//$write("CLK2 %x sr=%x\n", reset_l, sig_rst);
if (!reset_l) begin
sig_rst <= 0;
end
else begin
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
end
end
always @ (posedge clk) begin
//$write("CLK3 %x cc=%x sr=%x\n", reset_l, clk_clocks, sig_rst);
if (!reset_l) begin
clk_clocks <= 0;
end
else begin
clk_clocks <= clk_clocks + 8'd1;
if (clk_clocks == 4) begin
if (sig_rst !== 4) $stop;
if (clk_clocks_d1r !== 3) $stop;
if (int_clocks !== 2) $stop;
if (int_clocks_copy !== 2) $stop;
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
passed <= 1'b1;
$write("[%0t] t_clk: Passed\n",$time);
end
end
end
reg [7:0] resetted;
always @ (posedge clk or negedge reset_int_) begin
//$write("CLK4 %x\n", reset_l);
if (!reset_int_) begin
resetted <= 0;
end
else begin
resetted <= resetted + 8'd1;
end
end
always @ (int_clocks) begin
int_clocks_copy = int_clocks;
end
always @ (negedge internal_clk) begin
int_clocks <= int_clocks + 8'd1;
end
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
t_clk_two two (/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
`ifndef VERILATOR
module t;
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg c0; // To t2 of t2.v
reg c1; // To t2 of t2.v
reg check; // To t2 of t2.v
reg [1:0] clks; // To t2 of t2.v
// End of automatics
t2 t2 (/*AUTOINST*/
// Inputs
.clks (clks[1:0]),
.c0 (c0),
.c1 (c1),
.check (check));
task clockit (input v1, v0);
c1 = v1;
c0 = v0;
clks[1] = v1;
clks[0] = v0;
`ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif
#1;
endtask
initial begin
check = '0;
c0 = '0;
c1 = '0;
clks = '0;
#1
t2.clear();
#10;
for (int i=0; i<2; i++) begin
clockit(0, 0);
clockit(0, 0);
clockit(0, 1);
clockit(1, 1);
clockit(0, 0);
clockit(1, 1);
clockit(1, 0);
clockit(0, 0);
clockit(1, 0);
clockit(0, 1);
clockit(0, 0);
end
check = 1;
clockit(0, 0);
end
endmodule
`endif
`ifdef VERILATOR
`define t2 t
`else
`define t2 t2
`endif
module `t2 (
input [1:0] clks,
input c0,
input c1,
input check
);
`ifdef T_CLK_2IN_VEC
wire clk0 = clks[0];
wire clk1 = clks[1];
`else
wire clk0 = c0;
wire clk1 = c1;
`endif
integer p0 = 0;
integer p1 = 0;
integer p01 = 0;
integer n0 = 0;
integer n1 = 0;
integer n01 = 0;
integer vp = 0;
integer vn = 0;
integer vpn = 0;
task clear;
`ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif
p0 = 0;
p1 = 0;
p01 = 0;
n0 = 0;
n1 = 0;
n01 = 0;
vp = 0;
vn = 0;
vpn = 0;
endtask
`define display_counts(text) begin \
$write("[%0t] ",$time); \
`ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \
$write(text); \
$write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \
end
always @ (posedge clk0) begin
p0 = p0 + 1; // Want blocking, so don't miss clock counts
`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif
end
always @ (posedge clk1) begin
p1 = p1 + 1;
`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif
end
always @ (posedge clk0 or posedge clk1) begin
p01 = p01 + 1;
`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif
end
always @ (negedge clk0) begin
n0 = n0 + 1;
`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif
end
always @ (negedge clk1) begin
n1 = n1 + 1;
`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif
end
always @ (negedge clk0 or negedge clk1) begin
n01 = n01 + 1;
`ifdef TEST_VERBOSE `display_counts("negedge *"); `endif
end
`ifndef VERILATOR
always @ (posedge clks) begin
vp = vp + 1;
`ifdef TEST_VERBOSE `display_counts("pos vec"); `endif
end
always @ (negedge clks) begin
vn = vn + 1;
`ifdef TEST_VERBOSE `display_counts("neg vec"); `endif
end
always @ (posedge clks or negedge clks) begin
vpn = vpn + 1;
`ifdef TEST_VERBOSE `display_counts("or vec"); `endif
end
`endif
always @ (posedge check) begin
if (p0!=6) $stop;
if (p1!=6) $stop;
if (p01!=10) $stop;
if (n0!=6) $stop;
if (n1!=6) $stop;
if (n01!=10) $stop;
`ifndef VERILATOR
if (vp!=6) $stop;
if (vn!=6) $stop;
if (vpn!=12) $stop;
`endif
$write("*-* All Finished *-*\n");
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/);
initial begin
int q[int];
int qe[int]; // Empty
int qv[$]; // Value returns
int qi[$]; // Index returns
int i;
string v;
q = '{10:1, 11:2, 12:2, 13:4, 14:3};
v = $sformatf("%p", q); `checks(v, "'{'ha:'h1, 'hb:'h2, 'hc:'h2, 'hd:'h4, 'he:'h3} ");
// NOT tested: with ... selectors
//q.sort; // Not legal on assoc - see t_assoc_meth_bad
//q.rsort; // Not legal on assoc - see t_assoc_meth_bad
//q.reverse; // Not legal on assoc - see t_assoc_meth_bad
//q.shuffle; // Not legal on assoc - see t_assoc_meth_bad
v = $sformatf("%p", qe); `checks(v, "'{}");
qv = q.unique;
v = $sformatf("%p", qv); `checks(v, "'{'h1, 'h2, 'h4, 'h3} ");
qv = qe.unique;
v = $sformatf("%p", qv); `checks(v, "'{}");
qi = q.unique_index; qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{'ha, 'hb, 'hd, 'he} ");
qi = qe.unique_index;
v = $sformatf("%p", qi); `checks(v, "'{}");
// These require an with clause or are illegal
// TODO add a lint check that with clause is provided
qv = q.find with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2, 'h2} ");
qv = q.find_first with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = q.find_last with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = q.find with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_first with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_last with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qi = q.find_index with (item == 2); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{'hb, 'hc} ");
qi = q.find_first_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'hb} ");
qi = q.find_last_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'hc} ");
qi = q.find_index with (item == 20); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_first_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_last_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_index with (item.index == 12);
v = $sformatf("%p", qi); `checks(v, "'{'hc} ");
qi = q.find with (item.index == 12);
v = $sformatf("%p", qi); `checks(v, "'{'h2} ");
qv = q.min;
v = $sformatf("%p", qv); `checks(v, "'{'h1} ");
qv = q.max;
v = $sformatf("%p", qv); `checks(v, "'{'h4} ");
qv = qe.min;
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = qe.max;
v = $sformatf("%p", qv); `checks(v, "'{}");
// Reduction methods
i = q.sum;
`checkh(i, 32'hc);
i = q.sum with (item + 1);
`checkh(i, 32'h11);
i = q.product;
`checkh(i, 32'h30);
i = q.product with (item + 1);
`checkh(i, 32'h168);
i = qe.sum;
`checkh(i, 32'h0);
i = qe.product;
`checkh(i, 32'h0);
q = '{10:32'b1100, 11:32'b1010};
i = q.and;
`checkh(i, 32'b1000);
i = q.and with (item + 1);
`checkh(i, 32'b1001);
i = q.or;
`checkh(i, 32'b1110);
i = q.or with (item + 1);
`checkh(i, 32'b1111);
i = q.xor;
`checkh(i, 32'b0110);
i = q.xor with (item + 1);
`checkh(i, 32'b0110);
i = qe.and;
`checkh(i, 32'b0);
i = qe.or;
`checkh(i, 32'b0);
i = qe.xor;
`checkh(i, 32'b0);
i = q.and();
`checkh(i, 32'b1000);
i = q.and() with (item + 1);
`checkh(i, 32'b1001);
i = q.or();
`checkh(i, 32'b1110);
i = q.or() with (item + 1);
`checkh(i, 32'b1111);
i = q.xor();
`checkh(i, 32'b0110);
i = q.xor() with (item + 1);
`checkh(i, 32'b0110);
i = qe.and();
`checkh(i, 32'b0);
i = qe.or();
`checkh(i, 32'b0);
i = qe.xor();
`checkh(i, 32'b0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This files is used to generated the BLKLOOPINIT error which
// is actually caused by not being able to unroll the for loop.
//
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jie Xu.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [3:0] tmp [3:0];
initial begin
tmp[0] = 4'b0000;
tmp[2] = 4'b0010;
tmp[3] = 4'b0011;
end
// Test loop
always @ (posedge clk) begin
int i;
int j;
for (i = 0;(i < 4) && (i > 1); i++) begin
tmp[i] <= tmp[i-i];
end
if (tmp[0] != 4'b0000) $stop;
if (tmp[3] != 4'b0011) $stop;
j = 0; for (i=$c32("1"); i<3; ++i) j++;
if (j!=2) $stop;
j = 0; for (i=1; i<$c32("3"); ++i) j++;
if (j!=2) $stop;
j = 0; for (i=1; i<3; i=i+$c32("1")) j++;
if (j!=2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
module for an adder */
`timescale 10ns/10ps
module tb_adder;parameter PAYLOAD = 20; //how many flits per packet
parameter N = 31;
parameter STEP = 1.0;
integer i;
// Inputs
reg [N-1:0] input1; //time is unsigned 64 bit integer
reg [N-1:0] input2;
// Outputs
wire [N-1:0] sum;
integer count, seed;
reg clk;
always #( STEP / 2 ) begin
clk <= ~clk;
end
always #( STEP ) begin
count = count + 1;
seed = seed + 1;
end
// Instantiate the Unit Under Test (UUT)
adder adder (
.input1(input1),
.input2(input2),
.sum(sum)
);
initial begin
// Initialize Inputs
$dumpfile("dump_adder.vcd");
$dumpvars(0,tb_adder.adder);
$dumpoff;
/* Initialization */
#0
clk <= {1'b0};
count = 0;
input1 <= 0;
input2 <= 0;
#(STEP)
#(STEP / 2)
$write("Start clock %d \n", count);
$dumpon;
for (i = 0; i < 10; i = i + 1) begin //10 packets are sent. each packet has 20 data flits (payload, len=20)
send_data( PAYLOAD );
#(STEP*7) // Link utilization 4/13=0.30 (flit_rate injection)
$write("------------------------\n");
end
#(STEP)
$write("Stop clock %d \n", count);
$dumpoff;
$finish;
end
task send_data;
input [31:0] len; //payload
integer j;
//reg [31:0] ran0;
//reg [31:0] ran1;
time inj_data; //"time" is unsigned 64 bit datatype
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0], out1,out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`define EXPECTED_SUM 64'h10204fa5567c8a4b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
case (in[3:0]) inside
default: {out1,out2} = {1'b0,5'h0F}; // Note not last item
4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01};
4'h4: {out1,out2} = {1'b1,5'h04};
[4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match
4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08};
[4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C};
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// [16] is SV syntax for [15:0]
reg [7:0] memory8_16 [16];
reg m_we;
reg [3:1] m_addr;
reg [15:0] m_data;
always @ (posedge clk) begin
// Load instructions from cache
memory8_16[{m_addr,1'd0}] <= 8'hfe;
if (m_we) begin
{memory8_16[{m_addr,1'd1}],
memory8_16[{m_addr,1'd0}]} <= m_data;
end
end
reg [7:0] memory8_16_4;
reg [7:0] memory8_16_5;
// Test complicated sensitivity lists
always @ (memory8_16[4][7:1] or memory8_16[5]) begin
memory8_16_4 = memory8_16[4];
memory8_16_5 = memory8_16[5];
end
always @ (posedge clk) begin
m_we <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
m_we <= 1'b1;
m_addr <= 3'd2;
m_data <= 16'h55_44;
end
if (cyc==2) begin
m_we <= 1'b1;
m_addr <= 3'd3;
m_data <= 16'h77_66;
end
if (cyc==3) begin
m_we <= 0; // Check we really don't write this
m_addr <= 3'd3;
m_data <= 16'h0bad;
end
if (cyc==5) begin
if (memory8_16_4 != 8'h44) $stop;
if (memory8_16_5 != 8'h55) $stop;
if (memory8_16[6] != 8'hfe) $stop;
if (memory8_16[7] != 8'h77) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// simplistic example, should choose 1st conditional generate and assign straight through
// the tool also compiles the special case and determines an error (replication value is 0)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
`timescale 1ns / 1ps
module t(data_i, data_o, single);
parameter op_bits = 32;
input [op_bits -1:0] data_i;
output [31:0] data_o;
input single;
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate
if (op_bits == 32) begin : general_case
assign data_o = data_i;
// Test implicit signals
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
else begin : special_case
assign data_o = {{(32 -op_bits){1'b0}},data_i};
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
// bug420
typedef logic [7-1:0] wb_ind_t;
typedef logic [7-1:0] id_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
wire [6:0] out = line_wb_ind( in[6:0] );
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc918fa0aa882a206
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function wb_ind_t line_wb_ind( id_t id );
if( id[$bits(id_t)-1] == 0 )
return {2'b00, id[$bits(wb_ind_t)-3:0]};
else
return {2'b01, id[$bits(wb_ind_t)-3:0]};
endfunction // line_wb_ind
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
integer i;
reg [63:0] mem [7:0];
always @ (posedge clk) begin
if (cyc==1) begin
for (i=0; i<8; i=i+1) begin
mem[i] <= 64'h0;
end
end
else begin
mem[0] <= crc;
for (i=1; i<8; i=i+1) begin
mem[i] <= mem[i-1];
end
end
end
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData != 64'h1265e3bddcd9bc27) $stop;
end
else if (cyc==91) begin
if (outData != 64'h24cbc77bb9b3784e) $stop;
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module SwitchAllocator( // @[SwitchAllocator.scala:64:7]
input clock, // @[SwitchAllocator.scala:64:7]
input reset, // @[SwitchAllocator.scala:64:7]
output io_req_3_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_1_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_2_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_3_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_4_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_5_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_6_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_7_alloc, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_1_0 // @[SwitchAllocator.scala:74:14]
);
wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37]
wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37]
wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_0 | io_req_1_0_bits_vc_sel_0_1 | io_req_1_0_bits_vc_sel_0_2 | io_req_1_0_bits_vc_sel_0_3 | io_req_1_0_bits_vc_sel_0_4 | io_req_1_0_bits_vc_sel_0_5 | io_req_1_0_bits_vc_sel_0_6 | io_req_1_0_bits_vc_sel_0_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37]
wire arbs_2_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37]
wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_0 | io_req_2_0_bits_vc_sel_0_1 | io_req_2_0_bits_vc_sel_0_2 | io_req_2_0_bits_vc_sel_0_3 | io_req_2_0_bits_vc_sel_0_4 | io_req_2_0_bits_vc_sel_0_5 | io_req_2_0_bits_vc_sel_0_6 | io_req_2_0_bits_vc_sel_0_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37]
wire arbs_2_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37]
wire arbs_0_io_in_3_valid = io_req_3_0_valid & (io_req_3_0_bits_vc_sel_0_0 | io_req_3_0_bits_vc_sel_0_1 | io_req_3_0_bits_vc_sel_0_2 | io_req_3_0_bits_vc_sel_0_3 | io_req_3_0_bits_vc_sel_0_4 | io_req_3_0_bits_vc_sel_0_5 | io_req_3_0_bits_vc_sel_0_6 | io_req_3_0_bits_vc_sel_0_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_3_valid = io_req_3_0_valid & io_req_3_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37]
wire arbs_2_io_in_3_valid = io_req_3_0_valid & io_req_3_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37]
wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33]
wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33]
SwitchArbiter_1 arbs_0 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (/* unused */),
.io_in_0_valid (1'h0),
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_0_io_in_1_ready),
.io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1),
.io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2),
.io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3),
.io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4),
.io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5),
.io_in_1_bits_vc_sel_0_6 (io_req_1_0_bits_vc_sel_0_6),
.io_in_1_bits_vc_sel_0_7 (io_req_1_0_bits_vc_sel_0_7),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_0_io_in_2_ready),
.io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1),
.io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2),
.io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3),
.io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4),
.io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5),
.io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6),
.io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_0_io_in_3_ready),
.io_in_3_valid (arbs_0_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1),
.io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2),
.io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3),
.io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4),
.io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5),
.io_in_3_bits_vc_sel_0_6 (io_req_3_0_bits_vc_sel_0_6),
.io_in_3_bits_vc_sel_0_7 (io_req_3_0_bits_vc_sel_0_7),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_0_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_1_0 (/* unused */),
.io_out_0_bits_vc_sel_0_0 (_arbs_0_io_out_0_bits_vc_sel_0_0),
.io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1),
.io_out_0_bits_vc_sel_0_2 (_arbs_0_io_out_0_bits_vc_sel_0_2),
.io_out_0_bits_vc_sel_0_3 (_arbs_0_io_out_0_bits_vc_sel_0_3),
.io_out_0_bits_vc_sel_0_4 (_arbs_0_io_out_0_bits_vc_sel_0_4),
.io_out_0_bits_vc_sel_0_5 (_arbs_0_io_out_0_bits_vc_sel_0_5),
.io_out_0_bits_vc_sel_0_6 (_arbs_0_io_out_0_bits_vc_sel_0_6),
.io_out_0_bits_vc_sel_0_7 (_arbs_0_io_out_0_bits_vc_sel_0_7),
.io_out_0_bits_tail (/* unused */),
.io_chosen_oh_0 (_arbs_0_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_1 arbs_1 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_1_io_in_0_ready),
.io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_1_io_in_1_ready),
.io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1),
.io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2),
.io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3),
.io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4),
.io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5),
.io_in_1_bits_vc_sel_0_6 (io_req_1_0_bits_vc_sel_0_6),
.io_in_1_bits_vc_sel_0_7 (io_req_1_0_bits_vc_sel_0_7),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_1_io_in_2_ready),
.io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1),
.io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2),
.io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3),
.io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4),
.io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5),
.io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6),
.io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_1_io_in_3_ready),
.io_in_3_valid (arbs_1_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1),
.io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2),
.io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3),
.io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4),
.io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5),
.io_in_3_bits_vc_sel_0_6 (io_req_3_0_bits_vc_sel_0_6),
.io_in_3_bits_vc_sel_0_7 (io_req_3_0_bits_vc_sel_0_7),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_1_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0),
.io_out_0_bits_vc_sel_0_0 (/* unused */),
.io_out_0_bits_vc_sel_0_1 (/* unused */),
.io_out_0_bits_vc_sel_0_2 (/* unused */),
.io_out_0_bits_vc_sel_0_3 (/* unused */),
.io_out_0_bits_vc_sel_0_4 (/* unused */),
.io_out_0_bits_vc_sel_0_5 (/* unused */),
.io_out_0_bits_vc_sel_0_6 (/* unused */),
.io_out_0_bits_vc_sel_0_7 (/* unused */),
.io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail),
.io_chosen_oh_0 (_arbs_1_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_1 arbs_2 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_2_io_in_0_ready),
.io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_2_io_in_1_ready),
.io_in_1_valid (arbs_2_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1),
.io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2),
.io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3),
.io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4),
.io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5),
.io_in_1_bits_vc_sel_0_6 (io_req_1_0_bits_vc_sel_0_6),
.io_in_1_bits_vc_sel_0_7 (io_req_1_0_bits_vc_sel_0_7),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_2_io_in_2_ready),
.io_in_2_valid (arbs_2_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1),
.io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2),
.io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3),
.io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4),
.io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5),
.io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6),
.io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_2_io_in_3_ready),
.io_in_3_valid (arbs_2_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1),
.io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2),
.io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3),
.io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4),
.io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5),
.io_in_3_bits_vc_sel_0_6 (io_req_3_0_bits_vc_sel_0_6),
.io_in_3_bits_vc_sel_0_7 (io_req_3_0_bits_vc_sel_0_7),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_2_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0),
.io_out_0_bits_vc_sel_1_0 (/* unused */),
.io_out_0_bits_vc_sel_0_0 (/* unused */),
.io_out_0_bits_vc_sel_0_1 (/* unused */),
.io_out_0_bits_vc_sel_0_2 (/* unused */),
.io_out_0_bits_vc_sel_0_3 (/* unused */),
.io_out_0_bits_vc_sel_0_4 (/* unused */),
.io_out_0_bits_vc_sel_0_5 (/* unused */),
.io_out_0_bits_vc_sel_0_6 (/* unused */),
.io_out_0_bits_vc_sel_0_7 (/* unused */),
.io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail),
.io_chosen_oh_0 (_arbs_2_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
assign io_req_3_0_ready = _arbs_0_io_in_3_ready & arbs_0_io_in_3_valid | _arbs_1_io_in_3_ready & arbs_1_io_in_3_valid | _arbs_2_io_in_3_ready & arbs_2_io_in_3_valid; // @[Decoupled.scala:51:35]
assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid | _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid | _arbs_2_io_in_2_ready & arbs_2_io_in_2_valid; // @[Decoupled.scala:51:35]
assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid | _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid | _arbs_2_io_in_1_ready & arbs_2_io_in_1_valid; // @[Decoupled.scala:51:35]
assign io_req_0_0_ready = _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid; // @[Decoupled.scala:51:35]
assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33]
assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21]
assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33]
assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21]
assign io_credit_alloc_0_0_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_2_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_3_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_4_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_5_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_6_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_7_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_switch_sel_2_0_3_0 = arbs_2_io_in_3_valid & _arbs_2_io_chosen_oh_0[3] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_2_0 = arbs_2_io_in_2_valid & _arbs_2_io_chosen_oh_0[2] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_1_0 = arbs_2_io_in_1_valid & _arbs_2_io_chosen_oh_0[1] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_3_0 = arbs_1_io_in_3_valid & _arbs_1_io_chosen_oh_0[3] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_3_0 = arbs_0_io_in_3_valid & _arbs_0_io_chosen_oh_0[3] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Check empty blocks
task EmptyFor;
/* verilator public */
integer i;
begin
for (i = 0; i < 2; i = i+1)
begin
end
end
endtask
// Check look unroller
reg signed signed_tests_only = 1'sb1;
integer total;
integer i;
reg [31:0] iu;
reg [31:0] dly_to_insure_was_unrolled [1:0];
reg [2:0] i3;
integer cyc; initial cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
case (cyc)
1: begin
// >= signed
total = 0;
for (i=5; i>=0; i=i-1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -21) $stop;
end
2: begin
// > signed
total = 0;
for (i=5; i>0; i=i-1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -20) $stop;
end
3: begin
// < signed
total = 0;
for (i=1; i<5; i=i+1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -14) $stop;
end
4: begin
// <= signed
total = 0;
for (i=1; i<=5; i=i+1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -20) $stop;
end
// UNSIGNED
5: begin
// >= unsigned
total = 0;
for (iu=5; iu>=1; iu=iu-1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -20) $stop;
end
6: begin
// > unsigned
total = 0;
for (iu=5; iu>1; iu=iu-1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -18) $stop;
end
7: begin
// < unsigned
total = 0;
for (iu=1; iu<5; iu=iu+1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -14) $stop;
end
8: begin
// <= unsigned
total = 0;
for (iu=1; iu<=5; iu=iu+1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -20) $stop;
end
//===
9: begin
// mostly cover a small index
total = 0;
for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin
total = total - {29'd0,i3} -1;
dly_to_insure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
10: begin
// mostly cover a small index
total = 0;
for (i3=0; i3<3'd7; i3=i3+3'd1) begin
total = total - {29'd0,i3} -1;
dly_to_insure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
11: begin
// width violation on <, causes extend
total = 0;
for (i3=3'd0; i3<7; i3=i3+1) begin
total = total - {29'd0,i3} -1;
dly_to_insure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
// width violation on <, causes extend signed
// Unsupported as yet
//===
19: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define DDIFF_BITS 9
`define AOA_BITS 8
`define HALF_DDIFF `DDIFF_BITS'd256
`define MAX_AOA `AOA_BITS'd255
`define BURP_DIVIDER 9'd16
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0];
wire reset = (cyc<7);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.AOA_B (AOA_B[`AOA_BITS-1:0]),
// Inputs
.DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]),
.reset (reset),
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {56'h0, AOA_B};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3a74e9d34771ad93
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
AOA_B,
// Inputs
DDIFF_B, reset, clk
);
input [`DDIFF_BITS-1:0] DDIFF_B;
input reset;
input clk;
output reg [`AOA_BITS-1:0] AOA_B;
reg [`AOA_BITS-1:0] AOA_NEXT_B;
reg [`AOA_BITS-1:0] tmp;
always @(posedge clk) begin
if (reset) begin
AOA_B <= 8'h80;
end
else begin
AOA_B <= AOA_NEXT_B;
end
end
always @* begin
// verilator lint_off WIDTH
tmp = ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER);
t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER));
// verilator lint_on WIDTH
end
task t_aoa_update;
output [`AOA_BITS-1:0] aoa_reg_next;
input [`AOA_BITS-1:0] aoa_reg;
input [`AOA_BITS-1:0] aoa_delta_update;
begin
if ((`MAX_AOA-aoa_reg)<aoa_delta_update) //Overflow protection
aoa_reg_next=`MAX_AOA;
else
aoa_reg_next=aoa_reg+aoa_delta_update;
end
endtask
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg [31:0] runner; initial runner = 5;
reg [31:0] runnerm1;
reg [59:0] runnerq;
reg [89:0] runnerw;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
if (runner != 0) $stop; // Initial settlement failed
`endif
end
if (cyc==2) begin
runner = 20;
runnerq = 60'h0;
runnerw = 90'h0;
end
if (cyc==3) begin
if (runner != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
// This forms a "loop" where we keep going through the always till runner=0
// This isn't "regular" beh code, but insures our change detection is working properly
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
runner = runnerm1;
runnerq = runnerq - 60'd1;
runnerw = runnerw - 90'd1;
$write ("[%0t] runner=%d\n", $time, runner);
end
end
endmodule
|
module t();//intf #(.PARAM(1)) my_intf [1:0] ();
intf #(.PARAM(1)) my_intf ();
generate
genvar the_genvar;
for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf
//assign my_intf[the_genvar].val = '1;
//t1 t (.mod_intf(my_intf[the_genvar]));
t1 t (.mod_intf(my_intf));
end
endgenerate
// t1 t (.mod_intf(my_intf[1]));
// generate
// begin : TestIf
// assign my_intf[1].val = '1;
// t1 t (.mod_intf(my_intf[1]));
// end
// endgenerate
// generate
// begin
// assign my_intf[0].val = '1;
// t1 t (.mod_intf(my_intf[0]));
// end
// endgenerate
initial begin
$write("*-* All Finished *-*\n");
|
module RotatingSingleVCAllocator( // @[ISLIP.scala:43:7]
input clock, // @[ISLIP.scala:43:7]
input reset, // @[ISLIP.scala:43:7]
output io_req_3_ready, // @[VCAllocator.scala:49:14]
input io_req_3_valid, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_req_2_ready, // @[VCAllocator.scala:49:14]
input io_req_2_valid, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_req_1_ready, // @[VCAllocator.scala:49:14]
input io_req_1_valid, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_req_0_ready, // @[VCAllocator.scala:49:14]
input io_req_0_valid, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_6, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_7, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_8, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_6, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_7, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_8, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_6, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_7, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_8, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_6, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_7, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_8, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_9, // @[VCAllocator.scala:49:14]
input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_3_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_4_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_5_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_6_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_7_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_8_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_9_occupied, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_2_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_3_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_4_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_5_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_6_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_7_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_8_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_9_alloc // @[VCAllocator.scala:49:14]
);
wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39]
reg [3:0] mask; // @[SingleVCAllocator.scala:16:21]
wire [3:0] _in_arb_filter_T_3 = {in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39]
wire [7:0] in_arb_filter = _in_arb_filter_T_3[0] ? 8'h1 : _in_arb_filter_T_3[1] ? 8'h2 : _in_arb_filter_T_3[2] ? 8'h4 : _in_arb_filter_T_3[3] ? 8'h8 : in_arb_vals_0 ? 8'h10 : in_arb_vals_1 ? 8'h20 : in_arb_vals_2 ? 8'h40 : {in_arb_vals_3, 7'h0}; // @[OneHot.scala:85:71]
wire [3:0] in_arb_sel = in_arb_filter[3:0] | in_arb_filter[7:4]; // @[Mux.scala:50:70]
wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2 | in_arb_vals_3; // @[package.scala:81:59]
wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_2 = io_req_0_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_3 = io_req_0_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_4 = io_req_0_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_5 = io_req_0_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_6 = io_req_0_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_7 = io_req_0_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_8 = io_req_0_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_9 = io_req_0_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 | in_arb_reqs_0_0_1 | in_arb_reqs_0_0_2 | in_arb_reqs_0_0_3 | in_arb_reqs_0_0_4 | in_arb_reqs_0_0_5 | in_arb_reqs_0_0_6 | in_arb_reqs_0_0_7 | in_arb_reqs_0_0_8 | in_arb_reqs_0_0_9 | in_arb_reqs_0_1_0 | in_arb_reqs_0_2_0); // @[package.scala:81:59]
wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_3 = io_req_1_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_4 = io_req_1_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_5 = io_req_1_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_6 = io_req_1_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_7 = io_req_1_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_8 = io_req_1_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_9 = io_req_1_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 | in_arb_reqs_1_0_1 | in_arb_reqs_1_0_2 | in_arb_reqs_1_0_3 | in_arb_reqs_1_0_4 | in_arb_reqs_1_0_5 | in_arb_reqs_1_0_6 | in_arb_reqs_1_0_7 | in_arb_reqs_1_0_8 | in_arb_reqs_1_0_9 | in_arb_reqs_1_1_0 | in_arb_reqs_1_2_0); // @[package.scala:81:59]
wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_2 = io_req_2_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_3 = io_req_2_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_4 = io_req_2_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_5 = io_req_2_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_6 = io_req_2_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_7 = io_req_2_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_8 = io_req_2_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_9 = io_req_2_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 | in_arb_reqs_2_0_1 | in_arb_reqs_2_0_2 | in_arb_reqs_2_0_3 | in_arb_reqs_2_0_4 | in_arb_reqs_2_0_5 | in_arb_reqs_2_0_6 | in_arb_reqs_2_0_7 | in_arb_reqs_2_0_8 | in_arb_reqs_2_0_9 | in_arb_reqs_2_1_0 | in_arb_reqs_2_2_0); // @[package.scala:81:59]
wire in_arb_reqs_3_0_0 = io_req_3_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_1 = io_req_3_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_2 = io_req_3_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_3 = io_req_3_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_4 = io_req_3_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_5 = io_req_3_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_6 = io_req_3_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_7 = io_req_3_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_8 = io_req_3_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_9 = io_req_3_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_3 = io_req_3_valid & (in_arb_reqs_3_0_0 | in_arb_reqs_3_0_1 | in_arb_reqs_3_0_2 | in_arb_reqs_3_0_3 | in_arb_reqs_3_0_4 | in_arb_reqs_3_0_5 | in_arb_reqs_3_0_6 | in_arb_reqs_3_0_7 | in_arb_reqs_3_0_8 | in_arb_reqs_3_0_9 | in_arb_reqs_3_1_0 | in_arb_reqs_3_2_0); // @[package.scala:81:59]
wire _in_vc_sel_T_10 = in_arb_sel[0] & in_arb_reqs_0_0_0 | in_arb_sel[1] & in_arb_reqs_1_0_0 | in_arb_sel[2] & in_arb_reqs_2_0_0 | in_arb_sel[3] & in_arb_reqs_3_0_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_17 = in_arb_sel[0] & in_arb_reqs_0_0_1 | in_arb_sel[1] & in_arb_reqs_1_0_1 | in_arb_sel[2] & in_arb_reqs_2_0_1 | in_arb_sel[3] & in_arb_reqs_3_0_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_24 = in_arb_sel[0] & in_arb_reqs_0_0_2 | in_arb_sel[1] & in_arb_reqs_1_0_2 | in_arb_sel[2] & in_arb_reqs_2_0_2 | in_arb_sel[3] & in_arb_reqs_3_0_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_31 = in_arb_sel[0] & in_arb_reqs_0_0_3 | in_arb_sel[1] & in_arb_reqs_1_0_3 | in_arb_sel[2] & in_arb_reqs_2_0_3 | in_arb_sel[3] & in_arb_reqs_3_0_3; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_38 = in_arb_sel[0] & in_arb_reqs_0_0_4 | in_arb_sel[1] & in_arb_reqs_1_0_4 | in_arb_sel[2] & in_arb_reqs_2_0_4 | in_arb_sel[3] & in_arb_reqs_3_0_4; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_45 = in_arb_sel[0] & in_arb_reqs_0_0_5 | in_arb_sel[1] & in_arb_reqs_1_0_5 | in_arb_sel[2] & in_arb_reqs_2_0_5 | in_arb_sel[3] & in_arb_reqs_3_0_5; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_52 = in_arb_sel[0] & in_arb_reqs_0_0_6 | in_arb_sel[1] & in_arb_reqs_1_0_6 | in_arb_sel[2] & in_arb_reqs_2_0_6 | in_arb_sel[3] & in_arb_reqs_3_0_6; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_59 = in_arb_sel[0] & in_arb_reqs_0_0_7 | in_arb_sel[1] & in_arb_reqs_1_0_7 | in_arb_sel[2] & in_arb_reqs_2_0_7 | in_arb_sel[3] & in_arb_reqs_3_0_7; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_66 = in_arb_sel[0] & in_arb_reqs_0_0_8 | in_arb_sel[1] & in_arb_reqs_1_0_8 | in_arb_sel[2] & in_arb_reqs_2_0_8 | in_arb_sel[3] & in_arb_reqs_3_0_8; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_73 = in_arb_sel[0] & in_arb_reqs_0_0_9 | in_arb_sel[1] & in_arb_reqs_1_0_9 | in_arb_sel[2] & in_arb_reqs_2_0_9 | in_arb_sel[3] & in_arb_reqs_3_0_9; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_80 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0 | in_arb_sel[2] & in_arb_reqs_2_1_0 | in_arb_sel[3] & in_arb_reqs_3_1_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_87 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0 | in_arb_sel[3] & in_arb_reqs_3_2_0; // @[Mux.scala:30:73, :32:36]
reg [11:0] mask_1; // @[ISLIP.scala:17:25]
wire [11:0] _full_T_1 = {_in_vc_sel_T_87, _in_vc_sel_T_80, _in_vc_sel_T_73, _in_vc_sel_T_66, _in_vc_sel_T_59, _in_vc_sel_T_52, _in_vc_sel_T_45, _in_vc_sel_T_38, _in_vc_sel_T_31, _in_vc_sel_T_24, _in_vc_sel_T_17, _in_vc_sel_T_10} & ~mask_1; // @[Mux.scala:30:73]
wire [23:0] oh = _full_T_1[0] ? 24'h1 : _full_T_1[1] ? 24'h2 : _full_T_1[2] ? 24'h4 : _full_T_1[3] ? 24'h8 : _full_T_1[4] ? 24'h10 : _full_T_1[5] ? 24'h20 : _full_T_1[6] ? 24'h40 : _full_T_1[7] ? 24'h80 : _full_T_1[8] ? 24'h100 : _full_T_1[9] ? 24'h200 : _full_T_1[10] ? 24'h400 : _full_T_1[11] ? 24'h800 : _in_vc_sel_T_10 ? 24'h1000 : _in_vc_sel_T_17 ? 24'h2000 : _in_vc_sel_T_24 ? 24'h4000 : _in_vc_sel_T_31 ? 24'h8000 : _in_vc_sel_T_38 ? 24'h10000 : _in_vc_sel_T_45 ? 24'h20000 : _in_vc_sel_T_52 ? 24'h40000 : _in_vc_sel_T_59 ? 24'h80000 : _in_vc_sel_T_66 ? 24'h100000 : _in_vc_sel_T_73 ? 24'h200000 : _in_vc_sel_T_80 ? 24'h400000 : {_in_vc_sel_T_87, 23'h0}; // @[OneHot.scala:85:71]
wire [11:0] sel = oh[11:0] | oh[23:12]; // @[Mux.scala:50:70]
wire in_alloc_2_0 = _GEN & sel[11]; // @[package.scala:81:59]
wire in_alloc_1_0 = _GEN & sel[10]; // @[package.scala:81:59]
wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59]
wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]
wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59]
wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59]
wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59]
wire in_alloc_0_6 = _GEN & sel[6]; // @[package.scala:81:59]
wire in_alloc_0_7 = _GEN & sel[7]; // @[package.scala:81:59]
wire in_alloc_0_8 = _GEN & sel[8]; // @[package.scala:81:59]
wire in_alloc_0_9 = _GEN & sel[9]; // @[package.scala:81:59]
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] a = crc[7:0];
wire [7:0] b = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[63:0]),
// Inputs
.clk (clk),
.a (a[7:0]),
.b (b[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0908a1f2194d24ee
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, a, b
);
input clk;
input [7:0] a;
input [7:0] b;
output reg [63:0] out;
and u0[7:0] (out[7:0], a[7:0], b[7:0]);
and u1[7:0] (out[15:8], a[0], b[7:0]);
and u2[7:0] (out[23:16], a[0], b[0]);
nand u3[7:0] (out[31:24], a[0], b[7:0]);
or u4[7:0] (out[39:32], a[0], b[7:0]);
nor u5[7:0] (out[47:40], a[0], b[7:0]);
xor u6[7:0] (out[55:48], a[0], b[7:0]);
xnor u7[7:0] (out[63:56], a[0], b[7:0]);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off LITENDIAN
wire [10:41] sel2 = crc[31:0];
wire [10:100] sel3 = {crc[26:0],crc};
wire out20 = sel2[{1'b0,crc[3:0]} + 11];
wire [3:0] out21 = sel2[13 : 16];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
wire out30 = sel3[{2'b0,crc[3:0]} + 11];
wire [3:0] out31 = sel3[13 : 16];
wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
reg [19:50] sel1;
initial begin
// Path clearing
// 122333445
// 826048260
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[47 : 50] != 4'h8) $stop;
if (sel1[31 : 34] != 4'h4) $stop;
if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h28bf65439eb12c00
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Aggregate outputs into a single result vector
//wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows
wire [3:0] pow4b = crc[7:4]**crc[3:0];
wire [63:0] result = {60'h0, pow4b};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h1fec4b2b71cf8024
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverycud_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 19;
parameter MEM_SIZE = 480000;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./contact_discoverycud_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverycud(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd480000;
parameter AddressWidth = 32'd19;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
contact_discoverycud_ram contact_discoverycud_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
module fifo_packer_64 (
input CLK,
input RST,
input [63:0] DATA_IN, // Incoming data
input [1:0] DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [63:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg [1:0] rPackedCount=0, _rPackedCount=0;
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [95:0] rPackedData=96'd0, _rPackedData=96'd0;
reg [63:0] rDataIn=64'd0, _rDataIn=64'd0;
reg [1:0] rDataInEn=0, _rDataInEn=0;
reg [63:0] rDataMasked=64'd0, _rDataMasked=64'd0;
reg [1:0] rDataMaskedEn=0, _rDataMaskedEn=0;
assign PACKED_DATA = rPackedData[63:0];
assign PACKED_WEN = rPackedCount[1];
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data until 2 words are available, then writes 2 words out.
wire [63:0] wMask = {64{1'b1}}<<(32*rDataInEn);
wire [63:0] wDataMasked = ~wMask & rDataIn;
always @ (posedge CLK) begin
rPackedCount <= #1 (RST ? 2'd0 : _rPackedCount);
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rPackedData <= #1 (RST ? 96'd0 : _rPackedData);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 2'd0 : _rDataInEn);
rDataMasked <= #1 _rDataMasked;
rDataMaskedEn <= #1 (RST ? 2'd0 : _rDataMaskedEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
_rDataMasked = wDataMasked;
_rDataMaskedEn = rDataInEn;
// Count what's in our buffer. When we reach 2 words, 2 words will be written
// out. If flush is requested, write out whatever remains.
if (rPackedFlush && rPackedCount[0])
_rPackedCount = 2;
else
_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[1], 1'd0};
// Shift data into and out of our buffer as we receive and write out data.
if (rDataMaskedEn != 2'd0)
_rPackedData = ((rPackedData>>(32*{rPackedCount[1], 1'd0})) | (rDataMasked<<(32*rPackedCount[0])));
else
_rPackedData = (rPackedData>>(32*{rPackedCount[1], 1'd0}));
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning("Warning....");
InErrorBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1,"Fatal....");
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module for an adder */
`timescale 10ns/10ps
module tb_adder;parameter PAYLOAD = 20; //how many flits per packet
parameter N = 4;
parameter STEP = 1.0;
integer i;
// Inputs
reg [N-1:0] input1; //time is unsigned 64 bit integer
reg [N-1:0] input2;
// Outputs
wire [N-1:0] sum;
integer count, seed;
reg clk;
always #( STEP / 2 ) begin
clk <= ~clk;
end
always #( STEP ) begin
count = count + 1;
seed = seed + 1;
end
// Instantiate the Unit Under Test (UUT)
adder adder (
.input1(input1),
.input2(input2),
.sum(sum)
);
initial begin
// Initialize Inputs
$dumpfile("dump_adder.vcd");
$dumpvars(0,tb_adder.adder);
$dumpoff;
/* Initialization */
#0
clk <= {1'b0};
count = 0;
input1 <= 0;
input2 <= 0;
#(STEP)
#(STEP / 2)
$write("Start clock %d \n", count);
$dumpon;
for (i = 0; i < 10; i = i + 1) begin //10 packets are sent. each packet has 20 data flits (payload, len=20)
send_data( PAYLOAD );
#(STEP*7) // Link utilization 4/13=0.30 (flit_rate injection)
$write("------------------------\n");
end
#(STEP)
$write("Stop clock %d \n", count);
$dumpoff;
$finish;
end
task send_data;
input [31:0] len; //payload
integer j;
//reg [31:0] ran0;
//reg [31:0] ran1;
time inj_data; //"time" is unsigned 64 bit datatype
begin
/* data transfer */
inj_data = {8{1'b0}};
for (j = 0; j < len; j = j + 1) begin
#(STEP)
case(inj_data)
{8'b00000000} : inj_data = {8'b11110000};
{8'b11110000} : inj_data = {8'b11111111};
{8'b11111111} : inj_data = {8'b00001111};
{8'b00001111} : inj_data = {8'b00000000};
default : inj_data = {8{1'b0}};
endcase
|
module rom
( wb_adr_i, wb_stb_i, wb_cyc_i, wb_cti_i, wb_bte_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);parameter addr_width = 5;
input [(addr_width+2)-1:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
input [2:0] wb_cti_i;
input [1:0] wb_bte_i;
output reg [31:0] wb_dat_o;
output reg wb_ack_o;
input wb_clk;
input wb_rst;
`ifdef B3_BURST
reg [addr_width-1:0] adr;
reg wb_stb_i_r;
wire new_access;
reg new_access_r;
wire burst;
reg burst_r;
wire new_burst;
`endif
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o `NONBLOCK_ASSIGN 32'h15000000;
else
`ifdef B3_BURST
case (adr)
`else
case (wb_adr_i)
`endif
`include "bootrom.v"
/*
// Zero r0 and jump to 0x00000100
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
*/
default:
wb_dat_o `NONBLOCK_ASSIGN 32'h00000000;
endcase // case (wb_adr_i)
`ifdef B3_BURST
always @(posedge wb_clk)
wb_stb_i_r `NONBLOCK_ASSIGN wb_stb_i;
assign new_access = (wb_stb_i & !wb_stb_i_r);
always @(posedge wb_clk)
new_access_r <= new_access;
always @(posedge wb_clk)
burst_r `NONBLOCK_ASSIGN burst;
assign new_burst = (burst & !burst_r);
always @(posedge wb_clk)
if (wb_rst)
adr `NONBLOCK_ASSIGN 0;
else if (new_access)
// New access, register address, ack a cycle later
adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
else if (burst)
begin
if (wb_cti_i == 3'b010)
case (wb_bte_i)
2'b00: adr `NONBLOCK_ASSIGN adr + 1;
2'b01: adr[1:0] `NONBLOCK_ASSIGN adr[1:0] + 1;
2'b10: adr[2:0] `NONBLOCK_ASSIGN adr[2:0] + 1;
2'b11: adr[3:0] `NONBLOCK_ASSIGN adr[3:0] + 1;
endcase // case (wb_bte_i)
else
adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
end // if (burst)
always @(posedge wb_clk)
|
module RotatingSingleVCAllocator_30( // @[ISLIP.scala:43:7]
input clock, // @[ISLIP.scala:43:7]
input reset, // @[ISLIP.scala:43:7]
output io_req_2_ready, // @[VCAllocator.scala:49:14]
input io_req_2_valid, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_req_0_ready, // @[VCAllocator.scala:49:14]
input io_req_0_valid, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14]
output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_1_alloc // @[VCAllocator.scala:49:14]
);
wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39]
reg [2:0] mask; // @[SingleVCAllocator.scala:16:21]
wire [2:0] _in_arb_filter_T_3 = {in_arb_vals_2, 1'h0, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39]
wire [5:0] in_arb_filter = _in_arb_filter_T_3[0] ? 6'h1 : _in_arb_filter_T_3[1] ? 6'h2 : _in_arb_filter_T_3[2] ? 6'h4 : in_arb_vals_0 ? 6'h8 : {in_arb_vals_2, 5'h0}; // @[OneHot.scala:85:71]
wire [2:0] in_arb_sel = in_arb_filter[2:0] | in_arb_filter[5:3]; // @[Mux.scala:50:70]
wire _GEN = in_arb_vals_0 | in_arb_vals_2; // @[package.scala:81:59]
wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_1_0 | in_arb_reqs_0_2_0 | in_arb_reqs_0_3_0); // @[package.scala:81:59]
wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_3_0 = io_req_2_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_2 = io_req_2_valid & (io_req_2_bits_vc_sel_0_0 | in_arb_reqs_2_0_1 | io_req_2_bits_vc_sel_0_2 | io_req_2_bits_vc_sel_0_3 | io_req_2_bits_vc_sel_0_4 | in_arb_reqs_2_1_0 | in_arb_reqs_2_2_0 | in_arb_reqs_2_3_0); // @[package.scala:81:59]
wire _in_vc_sel_T_5 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_10 = in_arb_sel[2] & in_arb_reqs_2_0_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_15 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_20 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_3; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_25 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_4; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_32 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[2] & in_arb_reqs_2_1_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_37 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_42 = in_arb_sel[0] & in_arb_reqs_0_3_0 | in_arb_sel[2] & in_arb_reqs_2_3_0; // @[Mux.scala:30:73, :32:36]
reg [7:0] mask_1; // @[ISLIP.scala:17:25]
wire [7:0] _full_T_1 = {_in_vc_sel_T_42, _in_vc_sel_T_37, _in_vc_sel_T_32, _in_vc_sel_T_25, _in_vc_sel_T_20, _in_vc_sel_T_15, _in_vc_sel_T_10, _in_vc_sel_T_5} & ~mask_1; // @[Mux.scala:30:73]
wire [15:0] oh = _full_T_1[0] ? 16'h1 : _full_T_1[1] ? 16'h2 : _full_T_1[2] ? 16'h4 : _full_T_1[3] ? 16'h8 : _full_T_1[4] ? 16'h10 : _full_T_1[5] ? 16'h20 : _full_T_1[6] ? 16'h40 : _full_T_1[7] ? 16'h80 : _in_vc_sel_T_5 ? 16'h100 : _in_vc_sel_T_10 ? 16'h200 : _in_vc_sel_T_15 ? 16'h400 : _in_vc_sel_T_20 ? 16'h800 : _in_vc_sel_T_25 ? 16'h1000 : _in_vc_sel_T_32 ? 16'h2000 : _in_vc_sel_T_37 ? 16'h4000 : {_in_vc_sel_T_42, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] sel = oh[7:0] | oh[15:8]; // @[Mux.scala:50:70]
wire in_alloc_3_0 = _GEN & sel[7]; // @[package.scala:81:59]
wire in_alloc_2_0 = _GEN & sel[6]; // @[package.scala:81:59]
wire in_alloc_1_0 = _GEN & sel[5]; // @[package.scala:81:59]
wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59]
wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]
wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59]
wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59]
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
integer i;
reg [63:0] mem [7:0];
always @ (posedge clk) begin
if (cyc==1) begin
for (i=0; i<8; i=i+1) begin
mem[i] <= 64'h0;
end
end
else begin
mem[0] <= crc;
for (i=1; i<8; i=i+1) begin
mem[i] <= mem[i-1];
end
end
end
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData != 64'h1265e3bddcd9bc27) $stop;
end
else if (cyc==91) begin
if (outData != 64'h24cbc77bb9b3784e) $stop;
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module for an adder */
`timescale 10ns/10ps
module tb_adder;parameter PAYLOAD = 20; //how many flits per packet
parameter N = 18;
parameter STEP = 1.0;
integer i;
// Inputs
reg [N-1:0] input1; //time is unsigned 64 bit integer
reg [N-1:0] input2;
// Outputs
wire [N-1:0] sum;
integer count, seed;
reg clk;
always #( STEP / 2 ) begin
clk <= ~clk;
end
always #( STEP ) begin
count = count + 1;
seed = seed + 1;
end
// Instantiate the Unit Under Test (UUT)
adder adder (
.input1(input1),
.input2(input2),
.sum(sum)
);
initial begin
// Initialize Inputs
$dumpfile("dump_adder.vcd");
$dumpvars(0,tb_adder.adder);
$dumpoff;
/* Initialization */
#0
clk <= {1'b0};
count = 0;
input1 <= 0;
input2 <= 0;
#(STEP)
#(STEP / 2)
$write("Start clock %d \n", count);
$dumpon;
for (i = 0; i < 10; i = i + 1) begin //10 packets are sent. each packet has 20 data flits (payload, len=20)
send_data( PAYLOAD );
#(STEP*7) // Link utilization 4/13=0.30 (flit_rate injection)
$write("------------------------\n");
end
#(STEP)
$write("Stop clock %d \n", count);
$dumpoff;
$finish;
end
task send_data;
input [31:0] len; //payload
integer j;
//reg [31:0] ran0;
//reg [31:0] ran1;
time inj_data; //"time" is unsigned 64 bit datatype
begin
/* data transfer */
inj_data = {36{1'b0}};
for (j = 0; j < len; j = j + 1) begin
#(STEP)
case(inj_data)
{36'b000000000000000000000000000000000000} : inj_data = {36'b110000000000000000000000000000000000};
{36'b110000000000000000000000000000000000} : inj_data = {36'b111100000000000000000000000000000000};
{36'b111100000000000000000000000000000000} : inj_data = {36'b111111000000000000000000000000000000};
{36'b111111000000000000000000000000000000} : inj_data = {36'b111111110000000000000000000000000000};
{36'b111111110000000000000000000000000000} : inj_data = {36'b111111111100000000000000000000000000};
{36'b111111111100000000000000000000000000} : inj_data = {36'b111111111111000000000000000000000000};
{36'b111111111111000000000000000000000000} : inj_data = {36'b111111111111110000000000000000000000};
{36'b111111111111110000000000000000000000} : inj_data = {36'b111111111111111100000000000000000000};
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [89:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [89:0] out; // From test of Test.v
wire [44:0] line0;
wire [44:0] line1;
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[89:0]),
.line0 (line0[44:0]),
.line1 (line1[44:0]),
// Inputs
.clk (clk),
.in (in[89:0]));
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x out=%x\n", $time, cyc, in, out);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
end
else if (cyc==10) begin
if (in==out) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$write("*-* Failed!! *-*\n");
$finish;
end
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
line0, line1, out,
// Inputs
clk, in
);
input clk;
input [89:0] in;
output reg [44:0] line0;
output reg [44:0] line1;
output reg [89:0] out;
assign {line0,line1} = in;
always @(posedge clk) begin
out <= {line0,line1};
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef enum [3:0] {
E01 = 1,
E03 = 3,
E04 = 4
} my_t;
integer cyc=0;
my_t e;
int arrayfits [e.num]; // Check can use as constant
string all;
// Check constification
initial begin
e = E03;
`checkh(e.first, E01);
`checkh(e.last, E04);
`checkh(e.last(), E04);
`checkh(e.next, E04);
`checkh(e.next(), E04);
`checkh(e.next(1), E04);
//Unsup: `checkh(e.next(2), E01);
`checkh(e.prev, E01);
`checkh(e.prev(1), E01);
//Unsup: `checkh(e.prev(2), E04);
`checkh(e.num, 3);
`checks(e.name, "E03");
//
all = "";
for (my_t e = e.first; e != e.last; e = e.next) begin
all = {all, e.name};
end
e = e.last;
all = {all, e.name};
`checks(all, "E01E03E04");
end
// Check runtime
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
e <= E01;
end
else if (cyc==1) begin
`checks(e.name, "E01");
`checkh(e.next, E03);
`checkh(e.next(1), E03);
//Unsup: `checkh(e.next(2), E04);
`checkh(e.prev, E04);
`checkh(e.prev(1), E04);
//Unsup: `checkh(e.prev(2), E03);
e <= E03;
end
else if (cyc==2) begin
`checks(e.name, "E03");
`checkh(e.next, E04);
`checkh(e.next(1), E04);
//Unsup: `checkh(e.next(2), E01);
`checkh(e.prev, E01);
`checkh(e.prev(1), E01);
//Unsup: `checkh(e.prev(2), E04);
e <= E04;
end
else if (cyc==3) begin
`checks(e.name, "E04");
`checkh(e.next, E01);
`checkh(e.next(1), E01);
//Unsup: `checkh(e.next(2), E03);
`checkh(e.prev, E03);
`checkh(e.prev(1), E03);
//Unsup: `checkh(e.prev(2), E01);
e <= E01;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003-2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
wire out;
reg in;
Genit g (.clk(clk), .value(in), .result(out));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 1'b1;
end
else if (cyc==1) begin
in <= 1'b0;
end
else if (cyc==2) begin
if (out != 1'b1) $stop;
end
else if (cyc==3) begin
if (out != 1'b0) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
$dumpvars(12, t);
end
`endif
endmodule
module Generate (clk, value, result);
input clk;
input value;
output result;
reg Internal;
assign result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 value;
endmodule
module Checker (clk, value);
input clk, value;
always @(posedge clk) begin
$write ("[%0t] value=%h\n", $time, value);
end
endmodule
module Test (clk, value, result);
input clk;
input value;
output result;
Generate gen (clk, value, result);
Checker chk (clk, gen.Internal);
endmodule
module Genit (clk, value, result);
input clk;
input value;
output result;
`ifndef ATSIM // else unsupported
`ifndef NC // else unsupported
`define WITH_FOR_GENVAR
`endif
`endif
`define WITH_GENERATE
`ifdef WITH_GENERATE
`ifndef WITH_FOR_GENVAR
genvar i;
`endif
generate
for (
`ifdef WITH_FOR_GENVAR
genvar
`endif
i = 0; i < 1; i = i + 1)
begin : foo
Test tt (clk, value, result);
end
endgenerate
`else
Test tt (clk, value, result);
`endif
wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
always @ (posedge clk) begin
$write("[%0t] Result2 = %x\n", $time, Result2);
end
endmodule
|
module main;
localparam WID = 4;
reg [WID:0] X;
wire q_and, q_or, q_xor, q_nand, q_nor, q_xnor;
test_logic DUT(.\A[3] (X[3]), .\A[2] (X[2]), .\A[1] (X[1]), .\A[0] (X[0]),
.q_and(q_and), .q_or(q_or), .q_xor(q_xor),
.q_nand(q_nand), .q_nor(q_nor), .q_xnor(q_xnor));
initial begin
for (X = 0 ; X < 16 ; X = X+1) begin
#1 /* Let gates settle. */;
if (q_and !== & X[WID-1:0]) begin
$display("FAILED -- q_and=%b, X=%b", q_and, X[WID-1:0]);
$finish;
end
if (q_or !== | X[WID-1:0]) begin
$display("FAILED -- q_or=%b, X=%b", q_or, X[WID-1:0]);
$finish;
end
if (q_xor !== ^ X[WID-1:0]) begin
$display("FAILED -- q_xor=%b, X=%b", q_xor, X[WID-1:0]);
$finish;
end
if (q_nand !== ~& X[WID-1:0]) begin
$display("FAILED -- q_nand=%b, X=%b", q_nand, X[WID-1:0]);
$finish;
end
if (q_nor !== ~| X[WID-1:0]) begin
$display("FAILED -- q_nor=%b, X=%b", q_nor, X[WID-1:0]);
$finish;
end
if (q_xnor !== ~^ X[WID-1:0]) begin
$display("FAILED -- q_xnor=%b, X=%b", q_xnor, X[WID-1:0]);
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
module fifo_packer_128 (
input CLK,
input RST,
input [127:0] DATA_IN, // Incoming data
input [2:0] DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [127:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);reg [2:0] rPackedCount=0, _rPackedCount=0;
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [223:0] rPackedData=224'd0, _rPackedData=224'd0;
reg [127:0] rDataIn=128'd0, _rDataIn=128'd0;
reg [2:0] rDataInEn=0, _rDataInEn=0;
reg [127:0] rDataMasked=128'd0, _rDataMasked=128'd0;
reg [2:0] rDataMaskedEn=0, _rDataMaskedEn=0;
assign PACKED_DATA = rPackedData[127:0];
assign PACKED_WEN = rPackedCount[2];
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data until 4 words are available, then writes 4 words out.
wire [127:0] wMask = {128{1'b1}}<<(32*rDataInEn);
wire [127:0] wDataMasked = ~wMask & rDataIn;
always @ (posedge CLK) begin
rPackedCount <= #1 (RST ? 3'd0 : _rPackedCount);
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rPackedData <= #1 (RST ? 224'd0 : _rPackedData);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 3'd0 : _rDataInEn);
rDataMasked <= #1 _rDataMasked;
rDataMaskedEn <= #1 (RST ? 3'd0 : _rDataMaskedEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
_rDataMasked = wDataMasked;
_rDataMaskedEn = rDataInEn;
// Count what's in our buffer. When we reach 4 words, 4 words will be written
// out. If flush is requested, write out whatever remains.
if (rPackedFlush && (rPackedCount[1] | rPackedCount[0]))
_rPackedCount = 4;
else
_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[2], 2'd0};
// Shift data into and out of our buffer as we receive and write out data.
if (rDataMaskedEn != 3'd0)
_rPackedData = ((rPackedData>>(32*{rPackedCount[2], 2'd0})) | (rDataMasked<<(32*rPackedCount[1:0])));
else
_rPackedData = (rPackedData>>(32*{rPackedCount[2], 2'd0}));
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// simplistic example, should choose 1st conditional generate and assign straight through
// the tool also compiles the special case and determines an error (replication value is 0)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns / 1ps
module t(data_i, data_o, single);
parameter op_bits = 32;
input [op_bits -1:0] data_i;
output [31:0] data_o;
input single;
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate
if (op_bits == 32) begin : general_case
assign data_o = data_i;
// Test implicit signals
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
else begin : special_case
assign data_o = {{(32 -op_bits){1'b0}},data_i};
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
sub sub (.in(crc[23:0]), .out1(out1));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'h2e5cb972eb02b8a0) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1,
// Inputs
in
);
input [23:0] in;
output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal
parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101;
always @* begin
casez (in[17:16])
2'b00: casez (in[2:0])
3'h0: out1[0] = in[0]^RANDOM[0];
3'h1: out1[0] = in[0]^RANDOM[1];
3'h2: out1[0] = in[0]^RANDOM[2];
3'h3: out1[0] = in[0]^RANDOM[3];
3'h4: out1[0] = in[0]^RANDOM[4];
3'h5: out1[0] = in[0]^RANDOM[5];
3'h6: out1[0] = in[0]^RANDOM[6];
3'h7: out1[0] = in[0]^RANDOM[7];
endcase
2'b01: casez (in[2:0])
3'h0: out1[0] = RANDOM[10];
3'h1: out1[0] = RANDOM[11];
3'h2: out1[0] = RANDOM[12];
3'h3: out1[0] = RANDOM[13];
3'h4: out1[0] = RANDOM[14];
3'h5: out1[0] = RANDOM[15];
3'h6: out1[0] = RANDOM[16];
3'h7: out1[0] = RANDOM[17];
endcase
2'b1?: casez (in[4])
1'b1: casez (in[2:0])
3'h0: out1[0] = RANDOM[20];
3'h1: out1[0] = RANDOM[21];
3'h2: out1[0] = RANDOM[22];
3'h3: out1[0] = RANDOM[23];
3'h4: out1[0] = RANDOM[24];
3'h5: out1[0] = RANDOM[25];
3'h6: out1[0] = RANDOM[26];
3'h7: out1[0] = RANDOM[27];
endcase
1'b0: casez (in[2:0])
3'h0: out1[0] = RANDOM[30];
3'h1: out1[0] = RANDOM[31];
3'h2: out1[0] = RANDOM[32];
3'h3: out1[0] = RANDOM[33];
3'h4: out1[0] = RANDOM[34];
3'h5: out1[0] = RANDOM[35];
3'h6: out1[0] = RANDOM[36];
3'h7: out1[0] = RANDOM[37];
endcase
endcase
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2016 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
u u ();
tx x ();
parameter PARAM = 0;
parameter HIER = 0;
initial begin
$display("%m PARAM=%0d HIER=%0d", PARAM, HIER);
`ifdef IVERILOG
`check(PARAM, 0);
`elsif NC
`check(PARAM, 0);
`elsif VCS
`check(PARAM, 10);
`else
`check(PARAM, 10);
`endif
`check(HIER, 0);
end
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module u;
ux x();
endmodule
module ux;
parameter PARAM = 0;
parameter HIER = 0;
initial begin
$display("%m PARAM=%0d HIER=%0d", PARAM, HIER);
`ifdef IVERILOG
`check(PARAM, 0);
`elsif NC
`check(PARAM, 0);
`elsif VCS
`check(PARAM, 10);
`else
`check(PARAM, 0);
`endif
`check(HIER, 0);
end
endmodule
module tx;
parameter PARAM = 0;
parameter HIER = 0;
initial begin
$display("%m PARAM=%0d HIER=%0d", PARAM, HIER);
`ifdef IVERILOG
`check(PARAM, 0);
`elsif NC
`check(PARAM, 10);
`elsif VCS
`check(PARAM, 10);
`else
`check(PARAM, 0);
`endif
`ifdef NC
`check(HIER, 20);
`else
`check(HIER, 0);
`endif
end
endmodule
|
// Block FIFO Verilog Module
// Author: Matthew Knight
// Date: 2017-03-21
// The Block FIFO has an output signal to signal when full. When full the module
// does not accept writes to memory, but allows for reads. The FIFO only becomes
// empty when it is reset.
module blockfifo #(
parameter len = 320,
parameter wid = 8,
parameter addrWid = 9
)
(
input clk, reset, write,
output reg ready,
input [(wid-1):0] data_i,
input [(addrWid-1):0] readPtr,
output reg [(wid-1):0] data_o
);
reg [(addrWid-1):0] writePtr;
reg [(wid-1):0] ram [0:(len-1)];
// Combinational
always @(*) begin
// Determine if buffer is full
if (writePtr == len)
ready = 'b0;
else
ready = 1'b1;
if (readPtr < len)
data_o = ram[readPtr];
else
data_o = 'b0;
end
// Sequential logic
always @(posedge clk) begin
if (reset)
writePtr <= 'b0;
else begin
if (write & ready) begin
ram[writePtr] <= data_i;
writePtr <= writePtr + 1'b1;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h966e272fd829e672
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] out;
// End of automatics
`ifdef verilator
`define dontOptimize $c1("1")
`else
`define dontOptimize 1'b1
`endif
always @(posedge clk) begin
out <= in;
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (in[0])
out <= ~in;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off BLKANDNBLK
// verilator lint_off COMBDLY
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
reg [31:0] runnerm1, runner; initial runner = 0;
reg [31:0] runcount; initial runcount = 0;
reg [31:0] clkrun; initial clkrun = 0;
reg [31:0] clkcount; initial clkcount = 0;
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
reg run0;
always @ (/*AS*/runnerm1) begin
if ((runner & 32'hf)!=0) begin
runcount = runcount + 1;
runner = runnerm1;
$write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1);
end
run0 = (runner[8:4]!=0 && runner[3:0]==0);
end
always @ (posedge run0) begin
// Do something that forces another combo run
clkcount <= clkcount + 1;
runner[8:4] <= runner[8:4] - 1;
runner[3:0] <= 3;
$write ("[%0t] posedge runner=%0x\n", $time, runner);
end
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
$write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
runner <= 0;
end
8'd01: begin
runner <= 32'h35;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (runcount!=32'he) $stop;
if (clkcount!=32'h3) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [6:0] mem1d;
reg [6:0] mem2d [5:0];
reg [6:0] mem3d [4:0][5:0];
integer i,j,k;
// Four different test cases for out of bounds
// =
// <=
// Continuous assigns
// Output pin interconnect (also covers cont assigns)
// Each with both bit selects and array selects
initial begin
mem1d[0] = 1'b0;
i=7;
mem1d[i] = 1'b1;
if (mem1d[0] !== 1'b0) $stop;
//
for (i=0; i<8; i=i+1) begin
for (j=0; j<8; j=j+1) begin
for (k=0; k<8; k=k+1) begin
mem1d[k] = k[0];
mem2d[j][k] = j[0]+k[0];
mem3d[i][j][k] = i[0]+j[0]+k[0];
end
end
end
for (i=0; i<5; i=i+1) begin
for (j=0; j<6; j=j+1) begin
for (k=0; k<7; k=k+1) begin
if (mem1d[k] !== k[0]) $stop;
if (mem2d[j][k] !== j[0]+k[0]) $stop;
if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop;
end
end
end
end
integer wi;
wire [31:0] wd = cyc;
reg [31:0] reg2d[6:0];
always @ (posedge clk) reg2d[wi[2:0]] <= wd;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
`endif
cyc <= cyc + 1;
if (cyc<10) begin
wi <= 0;
end
else if (cyc==10) begin
wi <= 1;
end
else if (cyc==11) begin
if (reg2d[0] !== 10) $stop;
wi <= 6;
end
else if (cyc==12) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
wi <= 7; // Will be ignored
end
else if (cyc==13) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==14) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg [31:0] runner; initial runner = 5;
reg [31:0] runnerm1;
reg [59:0] runnerq;
reg [89:0] runnerw;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
if (runner != 0) $stop; // Initial settlement failed
`endif
end
if (cyc==2) begin
runner = 20;
runnerq = 60'h0;
runnerw = 90'h0;
end
if (cyc==3) begin
if (runner != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
// This forms a "loop" where we keep going through the always till runner=0
// This isn't "regular" beh code, but insures our change detection is working properly
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
runner = runnerm1;
runnerq = runnerq - 60'd1;
runnerw = runnerw - 90'd1;
$write ("[%0t] runner=%d\n", $time, runner);
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer j;
integer hit_count;
reg [63:0] cam_lookup_hit_vector;
strings strings ();
task show;
input [8*8-1:0] str;
reg [7:0] char;
integer loc;
begin
$write("[%0t] ",$time);
strings.stringStart(8*8-1);
for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin
$write("%c",char);
end
$write("\n");
end
endtask
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
show("hello\000xx");
end
if (cyc==2) begin
show("world\000xx");
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module strings;
// **NOT** reentrant, just a test!
integer index;
task stringStart;
input [31:0] bits;
begin
index = (bits-1)/8;
end
endtask
function isNull;
input [7:0] chr;
isNull = (chr == 8'h0);
endfunction
function [7:0] stringByte;
input [8*8-1:0] str;
begin
if (index<=0) stringByte=8'h0;
else stringByte = str[index*8 +: 8];
index = index - 1;
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk /*verilator sc_clock*/;
input fastclk /*verilator sc_clock*/;
reg reset_l;
int cyc;
initial reset_l = 0;
always @ (posedge clk) begin
if (cyc==0) reset_l <= 1'b1;
else if (cyc==1) reset_l <= 1'b0;
else if (cyc==10) reset_l <= 1'b1;
end
t_clk t (/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
module t_clk (/*AUTOARG*/
// Inputs
clk, fastclk, reset_l
);
input clk /*verilator sc_clock*/;
input fastclk /*verilator sc_clock*/;
input reset_l;
// surefire lint_off STMINI
// surefire lint_off CWECSB
// surefire lint_off NBAJAM
reg _ranit; initial _ranit=0;
// surefire lint_off UDDSMX
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
wire [7:0] clk_clocks_d1r;
wire [7:0] clk_clocks_d1sr;
wire [7:0] clk_clocks_cp2_d1r;
wire [7:0] clk_clocks_cp2_d1sr;
// verilator lint_off MULTIDRIVEN
reg [7:0] int_clocks; initial int_clocks = 0;
// verilator lint_on MULTIDRIVEN
reg [7:0] int_clocks_copy;
// verilator lint_off GENCLK
reg internal_clk; initial internal_clk = 0;
reg reset_int_;
// verilator lint_on GENCLK
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK1 %x\n", $time, reset_l);
`endif
if (!reset_l) begin
clk_clocks <= 0;
int_clocks <= 0;
internal_clk <= 1'b1;
reset_int_ <= 0;
end
else begin
internal_clk <= ~internal_clk;
if (!_ranit) begin
_ranit <= 1;
`ifdef TEST_VERBOSE
$write("[%0t] t_clk: Running\n",$time);
`endif
reset_int_ <= 1;
end
end
end
reg [7:0] sig_rst;
always @ (posedge clk or negedge reset_l) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst);
`endif
if (!reset_l) begin
sig_rst <= 0;
end
else begin
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
end
end
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst);
`endif
if (!reset_l) begin
clk_clocks <= 0;
end
else begin
clk_clocks <= clk_clocks + 8'd1;
if (clk_clocks == 4) begin
if (sig_rst !== 4) $stop;
if (clk_clocks_d1r !== 3) $stop;
if (int_clocks !== 2) $stop;
if (int_clocks_copy !== 2) $stop;
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
reg [7:0] resetted;
always @ (posedge clk or negedge reset_int_) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK4 %x\n", $time, reset_l);
`endif
if (!reset_int_) begin
resetted <= 0;
end
else begin
resetted <= resetted + 8'd1;
end
end
always @ (int_clocks) begin
int_clocks_copy = int_clocks;
end
always @ (negedge internal_clk) begin
int_clocks <= int_clocks + 8'd1;
end
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
t_clk_two two (/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
module t_clk_flop (/*AUTOARG*/
// Outputs
q, q2,
// Inputs
clk, clk2, a
);
parameter WIDTH=8;
input clk;
input clk2;
input [(WIDTH-1):0] a;
output [(WIDTH-1):0] q;
output [(WIDTH-1):0] q2;
reg [(WIDTH-1):0] q;
reg [(WIDTH-1):0] q2;
always @ (posedge clk) q<=a;
always @ (posedge clk2) q2<=a;
endmodule
module t_clk_two (/*AUTOARG*/
// Inputs
fastclk, reset_l
);
input fastclk;
input reset_l;
// verilator lint_off GENCLK
reg clk2;
// verilator lint_on GENCLK
reg [31:0] count;
t_clk_twob tb (.*);
wire reset_h = ~reset_l;
always @ (posedge fastclk) begin
if (reset_h) clk2 <= 0;
else clk2 <= ~clk2;
end
always @ (posedge clk2) begin
if (reset_h) count <= 0;
else count <= count + 1;
end
endmodule
module t_clk_twob (/*AUTOARG*/
// Inputs
fastclk, reset_l
);
input fastclk;
input reset_l;
always @ (posedge fastclk) begin
// Extra line coverage point, just to make sure coverage
// hierarchy under inlining lands properly
if (reset_l) ;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
// bug420
typedef logic [7-1:0] wb_ind_t;
typedef logic [7-1:0] id_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
wire [6:0] out = line_wb_ind( in[6:0] );
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc918fa0aa882a206
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function wb_ind_t line_wb_ind( id_t id );
if( id[$bits(id_t)-1] == 0 )
return {2'b00, id[$bits(wb_ind_t)-3:0]};
else
return {2'b01, id[$bits(wb_ind_t)-3:0]};
endfunction // line_wb_ind
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer j;
integer hit_count;
reg [63:0] cam_lookup_hit_vector;
strings strings ();
task show;
input [8*8-1:0] str;
reg [7:0] char;
integer loc;
begin
$write("[%0t] ",$time);
strings.stringStart(8*8-1);
for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin
$write("%c",char);
end
$write("\n");
end
endtask
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
show("hello\000xx");
end
if (cyc==2) begin
show("world\000xx");
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module strings;
// **NOT** reentrant, just a test!
integer index;
task stringStart;
input [31:0] bits;
begin
index = (bits-1)/8;
end
endtask
function isNull;
input [7:0] chr;
isNull = (chr == 8'h0);
endfunction
function [7:0] stringByte;
input [8*8-1:0] str;
begin
if (index<=0) stringByte=8'h0;
else stringByte = str[index*8 +: 8];
index = index - 1;
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
interface counter_if;
logic [3:0] value;
logic reset;
modport counter_mp (input reset, output value);
modport core_mp (output reset, input value);
endinterface
// Check can have inst module before top module
module counter_ansi
(
input clkm,
counter_if c_data,
input logic [3:0] i_value
);
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
counter_if c1_data();
counter_if c2_data();
counter_if c3_data();
counter_if c4_data();
counter_ansi c1 (.clkm(clk),
.c_data(c1_data.counter_mp),
.i_value(4'h1));
`ifdef VERILATOR counter_ansi `else counter_nansi `endif
/**/ c2 (.clkm(clk),
.c_data(c2_data.counter_mp),
.i_value(4'h2));
counter_ansi_m c3 (.clkm(clk),
.c_data(c3_data),
.i_value(4'h3));
`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif
/**/ c4 (.clkm(clk),
.c_data(c4_data),
.i_value(4'h4));
initial begin
c1_data.value = 4'h4;
c2_data.value = 4'h5;
c3_data.value = 4'h6;
c4_data.value = 4'h7;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc<2) begin
c1_data.reset <= 1;
c2_data.reset <= 1;
c3_data.reset <= 1;
c4_data.reset <= 1;
end
if (cyc==2) begin
c1_data.reset <= 0;
c2_data.reset <= 0;
c3_data.reset <= 0;
c4_data.reset <= 0;
end
if (cyc==20) begin
$write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc,
c1_data.value, c1_data.reset,
c2_data.value, c2_data.reset,
c3_data.value, c3_data.reset,
c4_data.value, c4_data.reset);
if (c1_data.value != 2) $stop;
if (c2_data.value != 3) $stop;
if (c3_data.value != 4) $stop;
if (c4_data.value != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi
(clkm, c_data, i_value);
input clkm;
counter_if c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi
`endif
module counter_ansi_m
(
input clkm,
counter_if.counter_mp c_data,
input logic [3:0] i_value
);
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi_m
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi_m
(clkm, c_data, i_value);
input clkm;
counter_if.counter_mp c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi_m
`endif
|
// Model of FIFO in Altera
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule // fifo_1c_4k
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t;
`ifdef T_GEN_MISSING_BAD
foobar #(.FOO_TYPE(1)) foobar; // This means we should instatiate missing module
`elsif T_GEN_MISSING
foobar #(.FOO_TYPE(0)) foobar; // This means we should instatiate foo0
`else
`error "Bad Test"
`endif
endmodule
module foobar
#( parameter
FOO_START = 0,
FOO_NUM = 2,
FOO_TYPE = 1
)
(
input wire[FOO_NUM-1:0] foo,
output wire[FOO_NUM-1:0] bar);
generate
begin: g
genvar j;
for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1)
begin: foo_inst;
if (FOO_TYPE == 0)
begin: foo_0
// instatiate foo0
foo0 i_foo(.x(foo[j]), .y(bar[j]));
end
if (FOO_TYPE == 1)
begin: foo_1
// instatiate foo1
foo_not_needed i_foo(.x(foo[j]), .y(bar[j]));
end
end
end
endgenerate
endmodule
module foo0(input wire x, output wire y);
assign y = ~x;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
//
// bug354
typedef logic [5:0] data_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire rst;
data_t iii_in = crc[5:0];
data_t jjj_in = crc[11:6];
data_t iii_out;
data_t jjj_out;
logic [1:0] ctl0 = crc[63:62];
aaa aaa (.*);
// Aggregate outputs into a single result vector
wire [63:0] result = {64'h0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
rst <= 1'b0;
end
else if (cyc<10) begin
sum <= 64'h0;
rst <= 1'b1;
end
else if (cyc<90) begin
rst <= 1'b0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module bbb
(
output data_t ggg_out[1:0],
input data_t ggg_in [1:0],
input [1:0] [1:0] ctl,
input logic clk,
input logic rst
);
genvar i;
generate
for (i=0; i<2; i++) begin: PPP
always_ff @(posedge clk) begin
if (rst) begin
ggg_out[i] <= 6'b0;
end
else begin
if (ctl[i][0]) begin
if (ctl[i][1]) begin
ggg_out[i] <= ~ggg_in[i];
end else begin
ggg_out[i] <= ggg_in[i];
end
end
end
end
end
endgenerate
endmodule
module aaa
(
input data_t iii_in,
input data_t jjj_in,
input [1:0] ctl0,
output data_t iii_out,
output data_t jjj_out,
input logic clk,
input logic rst
);
// Below is a bug; {} concat isn't used to make arrays
bbb bbb (
.ggg_in ({jjj_in, iii_in}),
.ggg_out ({jjj_out, iii_out}),
.ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}),
.*);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
typedef enum { EN_ZERO,
EN_ONE
} En_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Insure that we can declare a type with a function declaration
function enum integer {
EF_TRUE = 1,
EF_FALSE = 0 }
f_enum_inv ( input a);
f_enum_inv = a ? EF_FALSE : EF_TRUE;
endfunction
initial begin
if (f_enum_inv(1) != 0) $stop;
if (f_enum_inv(0) != 1) $stop;
end
En_t a, z;
sub sub (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.a (a));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= EN_ZERO;
end
if (cyc==2) begin
a <= EN_ONE;
if (z != EN_ONE) $stop;
end
if (cyc==3) begin
if (z != EN_ZERO) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input En_t a, output En_t z);
always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
["module ac (\\\\n input valid_i,\\\\n input [PHY_REG_ADDR_WIDTH - 1 : 0] rd_addr_i,\\\\n input opcode_i,\\\\n input [1:0] size_i,\\\\n input [VIRTUAL_ADDR_LEN - 1 : 0] addr_i,\\\\n\\\\n output [EXCEPTION_CODE_WIDTH - 1 : 0] ecause_o,\\\\n output exception_valid_o\\\\n);\\\\n wire misalign_fault;\\\\n wire access_fault;\\\\n \\\\n assign misalign_fault = \\\\n (size_i == 2'b01 && addr_i[0] != 0) || // hw\\\\n (size_i == 2'b10 && addr_i[1:0] != 0) || // w\\\\n (size_i == 2'b11 && addr_i[2:0] != 0); // dw\\\\n assign access_fault = (rd_addr_i == '0);\\\\n\\\\n assign ecause_o = \\\\n access_fault ? (opcode_i ? EXCEPTION_STORE_ACCESS_FAULT : EXCEPTION_LOAD_ACCESS_FAULT) :\\\\n misalign_fault ? (opcode_i ? EXCEPTION_STORE_ADDR_MISALIGNED : EXCEPTION_LOAD_ADDR_MISALIGNED) :\\\\n 0; \\\\n assign exception_valid_o = valid_i & \\\\n (misalign_fault);\\\\nendmodule"]
|
["module reduction #(\\\\n parameter DATA_WIDTH = 4\\\\n) (\\\\n input [$clog2(DATA_WIDTH):0] polyn_grade, // Orden del polinomio a reducir\\\\n input [DATA_WIDTH:0] polyn_red_in, // Polinomio primitivo\\\\n input [2*DATA_WIDTH-1:0] reduc_in, // Polinomio a reducir\\\\n output [DATA_WIDTH-1:0] out // Salida normal\\\\n);\\\\n //////////////////////////////////////////////////////////\\\\n // Generacion de los operandos\\\\n //////////////////////////////////////////////////////////\\\\n\\\\n wire [DATA_WIDTH:0] polyn_red_op [0:DATA_WIDTH];\\\\n wire [DATA_WIDTH:0] polyn_red_op_out;\\\\n wire [2*DATA_WIDTH-1:0] reduc_op [0:DATA_WIDTH];\\\\n wire [2*DATA_WIDTH-1:0] reduc_op_out;\\\\n\\\\n /* Creo N conexiones, customizando para operar con cualquier grado de polinomio primitivo */\\\\n genvar i;\\\\n generate\\\\n for (i = 0; i <= DATA_WIDTH; i = i + 1) begin\\\\n assign polyn_red_op[i] = (i > 1) ? {polyn_red_in[i:0],{DATA_WIDTH-i{1'b0}}} : 'b0;\\\\n assign reduc_op[i] = (i > 1) ? {reduc_in[(2*i)-1:0],{(2*(DATA_WIDTH-i)){1'b0}}} : 'b0;\\\\n end\\\\n endgenerate\\\\n\\\\n assign polyn_red_op_out = polyn_red_op[polyn_grade];\\\\n assign reduc_op_out = reduc_op[polyn_grade];\\\\n\\\\n //////////////////////////////////////////////////////////\\\\n // Inversion de las entradas - Para reducir el polinomio\\\\n //////////////////////////////////////////////////////////\\\\n\\\\n wire [2*DATA_WIDTH-1:0] reduc_in_n; // Polinomio a reducir invertido\\\\n wire [DATA_WIDTH:0] polyn_red_in_n; // Polinomio primitivo invertido\\\\n\\\\n wire [2*DATA_WIDTH-1:0] reduc; // Salidas para la siguiente etapa\\\\n wire [DATA_WIDTH:0] polyn_red;\\\\n\\\\n bit_order_inversion #(2*DATA_WIDTH) bit_inv_reduc(\\\\n .a(reduc_op_out),\\\\n .a_n(reduc_in_n)\\\\n );\\\\n bit_order_inversion #(DATA_WIDTH+1) bit_inv_polym(\\\\n .a(polyn_red_op_out),\\\\n .a_n(polyn_red_in_n)\\\\n );\\\\n\\\\n // Invierto o no las entradas dependiendo si es polinomio de reduccion o no\\\\n assign reduc = reduc_in_n;\\\\n assign polyn_red = polyn_red_in_n;\\\\n\\\\n //////////////////////////////////////////////////////////\\\\n // Sumas parciales\\\\n //////////////////////////////////////////////////////////\\\\n\\\\n wire [DATA_WIDTH:0] partial_sum [0:DATA_WIDTH-1];\\\\n\\\\n wire [DATA_WIDTH:0] a_sum [0:DATA_WIDTH-2];\\\\n wire [DATA_WIDTH:0] b_sum [0:DATA_WIDTH-2];\\\\n\\\\n // La primera suma parcial del modulo de reduccion es el la primera parte del polinomio a reducir\\\\n assign partial_sum[0] = reduc[0 +: (DATA_WIDTH+1)];\\\\n \\\\n\\\\n /* Creo los N adders de N bits de ancho */\\\\n generate\\\\n for (i = 0; i < DATA_WIDTH-1; i = i + 1) begin // 0 a 3\\\\n cl_add #(DATA_WIDTH+1) adder0(\\\\n .a(a_sum[i]),\\\\n .b(b_sum[i]),\\\\n .sum(partial_sum[i+1]) // 0 a 4\\\\n );\\\\n\\\\n // Asigno las entradas de las sumas parciales\\\\n assign a_sum[i] = {reduc[DATA_WIDTH+1+i],partial_sum[i][1 +: DATA_WIDTH]}; \\\\n assign b_sum[i] = a_sum[i][0] ? polyn_red : 0; \\\\n \\\\n end\\\\n endgenerate\\\\n\\\\n //////////////////////////////////////////////////////////\\\\n // Selecciono la salida correcta\\\\n //////////////////////////////////////////////////////////\\\\n\\\\n wire [DATA_WIDTH-1:0] poly_mux_out;\\\\n wire [DATA_WIDTH-1:0] poly_out [0:DATA_WIDTH];\\\\n\\\\n generate\\\\n for (i = 0; i <= DATA_WIDTH; i = i + 1) begin // 0 a 5\\\\n assign poly_out[i] = (i > 1) ? {partial_sum[i-1][i:1],{DATA_WIDTH-i{1'b0}}} : 'b0;\\\\n end\\\\n endgenerate\\\\n\\\\n assign poly_mux_out = poly_out[polyn_grade];\\\\n\\\\n //////////////////////////////////////////////////////////\\\\n // Inversion de las salidas - Para reducir el polinomio\\\\n //////////////////////////////////////////////////////////\\\\n\\\\n wire [DATA_WIDTH-1:0] out_poly; // Salida del polinomio de reduccion\\\\n\\\\n bit_order_inversion #(DATA_WIDTH) bit_inv_poly_out(\\\\n .a(poly_mux_out),\\\\n .a_n(out_poly)\\\\n );\\\\n\\\\n //////////////////////////////////////////////////////////\\\\n // Salidas\\\\n //////////////////////////////////////////////////////////\\\\n\\\\n assign out = out_poly;\\\\n\\\\nendmodule"]
|
["module sequency_order(i_clk, i_ce, i_reset, o_index);\\\\n parameter L_WIDTH = 3;\\\\n\\\\n input wire i_clk;\\\\n input wire i_ce;\\\\n input wire i_reset;\\\\n output wire [L_WIDTH-1:0] o_index;\\\\n\\\\n reg [L_WIDTH-1:0] binary_value = {{L_WIDTH-1{1'b0}},1'b1};\\\\n reg [L_WIDTH-1:0] gray_value = {L_WIDTH{1'b0}};\\\\n\\\\n always @(posedge i_clk)\\\\n if (i_reset) begin\\\\n binary_value <= {{L_WIDTH-1{1'b0}},1'b1};\\\\n gray_value <= {L_WIDTH{1'b0}};\\\\n end\\\\n else if (i_ce) begin\\\\n binary_value <= binary_value + 1;\\\\n gray_value <= (binary_value >> 1) ^ binary_value;\\\\n end\\\\n\\\\n /*bit_reversal*/\\\\n /*genvar i;\\\\n generate\\\\n for ( i = 0; i < L_WIDTH; i = i + 1)\\\\n begin\\\\n assign o_index[L_WIDTH-i] = gray_value[i];\\\\n end\\\\n endgenerate\\\\n */\\\\n assign o_index[11] = gray_value[0];\\\\n assign o_index[10] = gray_value[1];\\\\n assign o_index[9] = gray_value[2];\\\\n assign o_index[8] = gray_value[3];\\\\n assign o_index[7] = gray_value[4];\\\\n assign o_index[6] = gray_value[5];\\\\n assign o_index[5] = gray_value[6];\\\\n assign o_index[4] = gray_value[7];\\\\n assign o_index[3] = gray_value[8];\\\\n assign o_index[2] = gray_value[9];\\\\n assign o_index[1] = gray_value[10];\\\\n assign o_index[0] = gray_value[11];\\\\n\\\\n\\\\n\\\\nendmodule"]
|
['module TeamBeeper(input clock, [4:0] timing, command, output state);\\\\n reg [26:0] COUNT = 0;\\\\n reg C0 = 0;\\\\n wire [26:0] limit;\\\\n wire tick;\\\\n \\\\n assign limit = timing == 0 ? 4999999 :\\\\n timing == 1 ? 9999999 :\\\\n timing == 2 ? 29999999 :\\\\n timing == 3 ? 39999999 :\\\\n timing == 4 ? 49999999 :\\\\n timing == 5 ? 59999999 :\\\\n timing == 6 ? 69999999 :\\\\n timing == 7 ? 79999999 :\\\\n timing == 8 ? 89999999 :\\\\n timing == 9 ? 99999999 : 0;\\\\n \\\\n \\\\n always @ (posedge clock) begin\\\\n if (command == 0) begin\\\\n C0 <= COUNT == 0 ? 0 : 1;\\\\n COUNT <= COUNT == 0 ? 0 : (COUNT == limit) ? 0 : COUNT + 1;\\\\n end else begin\\\\n C0 <= 1;\\\\n COUNT <= 1;\\\\n end\\\\n end\\\\n \\\\n assign state = C0;\\\\n \\\\nendmodule']
|
["module syncs the digit with the clock\\\\n// Dependencies: \\\\n// \\\\n// Revision:\\\\n// Revision 0.01 - File Created\\\\n// Additional Comments:\\\\n// \\\\n//////////////////////////////////////////////////////////////////////////////////\\\\n\\\\n\\\\nmodule multidigit(\\\\n input clk, rst,\\\\n input [3:0] dig7, dig6, dig5, dig4, dig3, dig2, dig1, dig0,\\\\n output a, b, c, d, e, f, g,\\\\n output reg [7:0] an\\\\n );\\\\n \\\\n wire led_clk;\\\\n reg [3:0] dig_sel;\\\\n reg [2:0] led_index = 3'd0;\\\\n reg [28:0] clk_count = 11'd0;\\\\n \\\\n always @(posedge clk)\\\\n clk_count <= clk_count + 1'b1;\\\\n \\\\n assign led_clk = clk_count[16];\\\\n assign div_clk = clk_count[25];\\\\n \\\\n always@(posedge led_clk)\\\\n if(rst)\\\\n led_index <= 3'd0;\\\\n else\\\\n led_index <= led_index + 1'b1;\\\\n\\\\n always@*\\\\n begin \\\\n an = 8'b11111111;\\\\n an[led_index] = 1'b0;\\\\n case (led_index)\\\\n 3'd0: dig_sel = dig0;\\\\n 3'd1: dig_sel = dig1;\\\\n 3'd2: dig_sel = dig2;\\\\n 3'd3: dig_sel = dig3;\\\\n 3'd4: dig_sel = dig4;\\\\n 3'd5: dig_sel = dig5;\\\\n 3'd6: dig_sel = dig6;\\\\n 3'd7: dig_sel = dig7;\\\\n endcase \\\\n end\\\\n\\\\n led M1 (.num(dig_sel), .a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g));\\\\n \\\\nendmodule"]
|
['module m8VG_pipelined(\\\\n min1,\\\\n min2,\\\\n q2q1q0,\\\\n \\\\n x,\\\\n clk,\\\\n rst\\\\n );\\\\n \\\\n parameter W=6;\\\\n parameter Wc=8;\\\\n \\\\n output reg [W-2:0]min1;\\\\n output reg [W-2:0]min2;\\\\n output reg [2:0]q2q1q0;\\\\n \\\\n input [Wc*(W-1)-1:0]x;\\\\n input clk;\\\\n input rst;\\\\n \\\\n wire [1:0]m1_q1q0;\\\\n wire [1:0]m2_q1q0;\\\\n wire [W-2:0]m1A,m1B,m2A,m2B;\\\\n\\\\n \\\\n wire [W-2:0]min1_wire;\\\\n wire [W-2:0]min2_wire;\\\\n wire [2:0]q2q1q0_wire;\\\\n \\\\n always@(posedge clk)begin\\\\n if(rst)begin\\\\n min1 <= 0;\\\\n min2 <= 0;\\\\n q2q1q0 <= 0;\\\\n end\\\\n else begin\\\\n min1 <= min1_wire;\\\\n min2 <= min2_wire;\\\\n q2q1q0 <= q2q1q0_wire; \\\\n end\\\\n end \\\\n \\\\n m4VG_pipelined m1(m1A,m1B,m1_q1q0,x[4*(W-1)-1:0],clk,rst);\\\\n m4VG_pipelined m2(m2A,m2B,m2_q1q0,x[8*(W-1)-1:4*(W-1)],clk,rst);\\\\n \\\\n assign min1_wire = m1A > m2A ? m2A :m1A ;\\\\n assign q2q1q0_wire[2] = m1A > m2A ? 1:0;\\\\n //assign min2 = q2q1q0[2] ? m1A < m2B ? m1A : m2B : m1B < m2A ? m1B : m2A;\\\\n assign min2_wire = m1A > m2A ? m1A < m2B ? m1A : m2B : m1B < m2A ? m1B : m2A;\\\\n // assign q2q1q0[1:0] = q2q1q0[2] ? m2_q1q0 : m1_q1q0;\\\\n assign q2q1q0_wire[1:0] = m1A > m2A ? m2_q1q0 : m1_q1q0;\\\\nendmodule']
|
["module tx(\\\\n input clk_bit,\\\\n input rst,\\\\n input [7:0] d_in,\\\\n input d_in_valid,\\\\n input prbs_on,\\\\n output reg out,\\\\n output reg read_enable,\\\\n output reg idle\\\\n );\\\\n\\\\nreg [15:0] lfsr;\\\\nreg [3:0] bitcount;\\\\nreg encode_enable;\\\\nwire [9:0] d_out;\\\\n\\\\nencode_8b10b encoder(\\\\n .clk(clk_bit),\\\\n .nextword_enable(encode_enable),\\\\n .rst(rst),\\\\n .d_in(d_in),\\\\n .idle(idle),\\\\n .d_out(d_out)\\\\n );\\\\n\\\\nalways @ (posedge clk_bit or posedge rst) begin\\\\n if (rst) begin\\\\n read_enable <= 0;\\\\n encode_enable <= 0;\\\\n lfsr <= 16'h5678;\\\\n out <= 0;\\\\n bitcount <= 0;\\\\n idle <= 0;\\\\n end else begin\\\\n if (prbs_on) begin\\\\n lfsr <= {lfsr[14:0], lfsr[15] ^ lfsr[13] ^ lfsr[12] ^ lfsr[10]};\\\\n out <= lfsr[0];\\\\n end else begin\\\\n read_enable <= 0;\\\\n encode_enable <= 0;\\\\n if (bitcount == 9) begin\\\\n bitcount <= 0;\\\\n end else begin\\\\n if (bitcount == 8) begin\\\\n encode_enable <= 1;\\\\n if (d_in_valid) begin\\\\n read_enable <= 1;\\\\n idle <= 0;\\\\n end else begin\\\\n idle <= 1;\\\\n end\\\\n end\\\\n bitcount <= bitcount + 1'b1;\\\\n end\\\\n out <= d_out[bitcount];\\\\n end\\\\n end \\\\nend\\\\nendmodule"]
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['module imply_tb();\\\\n parameter LUT_SIZE = 8;\\\\n parameter TRUTH_TABLE_BITS = 1 << LUT_SIZE;\\\\n parameter [1:0] ZERO = 2\\'b00;\\\\n parameter [1:0] ONE = 2\\'b01;\\\\n parameter [1:0] UNKNOWN = 2\\'b11;\\\\n\\\\n reg [2*LUT_SIZE + 1:0] pins;\\\\n reg [TRUTH_TABLE_BITS - 1:0] tt;\\\\n wire [2*LUT_SIZE + 1:0] implied_pins;\\\\n wire conflict;\\\\n\\\\n imply #(.LUT_SIZE(LUT_SIZE)) uut(.pins(pins), .tt(tt), .implied_pins(implied_pins), .conflict(conflict));\\\\n\\\\n localparam period = 20;\\\\n\\\\n function [TRUTH_TABLE_BITS-1 : 0] projection(input integer i);\\\\n integer address;\\\\n begin\\\\n for(address = 0; address < TRUTH_TABLE_BITS; address = address + 1) begin\\\\n if(address[i] == 1\\'b1) begin\\\\n projection[address] = 1;\\\\n end else begin\\\\n projection[address] = 0;\\\\n end\\\\n end\\\\n end\\\\n endfunction\\\\n\\\\n initial\\\\n begin\\\\n // CONST\\\\n tt = 0;\\\\n pins = -1;\\\\n #period;\\\\n if(implied_pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] != ZERO)\\\\n $display(\\\\"Test failed for const 0 output\\\\");\\\\n\\\\n // SINGLE VAR PROJECTION\\\\n tt = projection(0);\\\\n pins = -1;\\\\n #period;\\\\n if(implied_pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] != UNKNOWN)\\\\n $display(\\\\"Test failed for var_0 projection output (U)\\\\");\\\\n\\\\n pins[1:0] = ZERO;\\\\n #period;\\\\n if(implied_pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] != ZERO)\\\\n $display(\\\\"Test failed for var_0 projection output (0)\\\\");\\\\n\\\\n pins[1:0] = ONE;\\\\n #period;\\\\n if(implied_pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] != ONE)\\\\n $display(\\\\"Test failed for var_0 projection output (1)\\\\");\\\\n\\\\n // AND\\\\n tt = projection(0) & projection(1);\\\\n pins = -1;\\\\n pins[1:0] = ZERO;\\\\n #period;\\\\n if(implied_pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] != ZERO)\\\\n $display(\\\\"Test failed for AND output (0)\\\\");\\\\n\\\\n pins[1:0] = ONE;\\\\n pins[3:2] = ONE;\\\\n #period;\\\\n if(implied_pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] != ONE)\\\\n $display(\\\\"Test failed for AND output (1)\\\\");\\\\n\\\\n pins[1:0] = UNKNOWN;\\\\n pins[3:2] = UNKNOWN;\\\\n pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] = ONE;\\\\n #period;\\\\n if(implied_pins[1:0] != ONE || implied_pins[3:2] != ONE)\\\\n $display(\\\\"Test failed for AND input (1, 1)\\\\");\\\\n\\\\n pins[1:0] = ONE;\\\\n pins[3:2] = UNKNOWN;\\\\n pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] = ZERO;\\\\n #period;\\\\n if(implied_pins[3:2] != ZERO)\\\\n $display(\\\\"Test failed for AND input (0)\\\\");\\\\n\\\\n // Conflict Detection (AND)\\\\n pins[1:0] = ZERO;\\\\n pins[3:2] = ZERO;\\\\n pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] = ONE;\\\\n #period;\\\\n if(conflict != 1\\'b1)\\\\n $display(\\\\"Test failed for conflicting AND\\\\");\\\\n\\\\n pins[2*LUT_SIZE + 1 : 2*LUT_SIZE] = ZERO;\\\\n #period;\\\\n if(conflict != 1\\'b0)\\\\n $display(\\\\"Test failed for non-conflicting AND\\\\");\\\\n \\\\n $display(\\\\"Test Finished!\\\\");\\\\n $finish;\\\\n end\\\\nendmodule']
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["module mul_fsm(clk, rst_n, cs_start, phase);\\\\n\\\\n input clk; // Clock\\\\n input rst_n; // nReset\\\\n input\\\\t\\\\tcs_start;\\\\t// Start\\\\n output \\\\tphase; // Current state \\\\n \\\\n // BINARY ENCODED state machine:\\\\n // State codes definitions:\\\\n parameter ST_P1 = 1'b0;\\\\n parameter ST_P2 = 1'b1;\\\\n \\\\n reg \\\\tcurr_state, next_state;\\\\n \\\\n //=============================================================\\\\n // main code\\\\n //============================================================= \\\\n // Current State Logic (sequential)\\\\n always @ (negedge clk or negedge rst_n)\\\\n begin\\\\n if(~rst_n) // an asynchronous rst\\\\n curr_state = ST_P1;\\\\n else\\\\n curr_state = next_state;\\\\n end\\\\n \\\\n \\\\n // NextState logic (combinatorial)\\\\n always @ (curr_state or cs_start)\\\\n begin\\\\n case (curr_state)\\\\n ST_P1: next_state = (cs_start)?ST_P2:ST_P1;\\\\n ST_P2: next_state = ST_P1;\\\\n endcase\\\\n end\\\\n \\\\n assign phase = curr_state;\\\\n \\\\nendmodule"]
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["module BranchDecisionMaking(\\\\n input wire [2: 0] BranchTypeE,\\\\n input wire [31: 0] Operand1, Operand2,\\\\n output reg BranchE\\\\n );\\\\nwire signed [31: 0] Operand1_S = $signed(Operand1);\\\\nwire signed [31: 0] Operand2_S = $signed(Operand2);\\\\nalways @( * ) begin\\\\n case (BranchTypeE)\\\\n `BEQ:\\\\n BranchE <= (Operand1 == Operand2) ? 1'b1 : 1'b0;\\\\n `BNE:\\\\n BranchE <= (Operand1 == Operand2) ? 1'b0 : 1'b1;\\\\n `BLT:\\\\n BranchE <= (Operand1_S < Operand2_S ) ? 1'b1 : 1'b0;\\\\n `BLTU:\\\\n BranchE <= (Operand1 < Operand2) ? 1'b1 : 1'b0;\\\\n `BGE:\\\\n BranchE <= (Operand1_S >= Operand2_S ) ? 1'b1 : 1'b0;\\\\n `BGEU:\\\\n BranchE <= (Operand1 >= Operand2) ? 1'b1 : 1'b0;\\\\n default:\\\\n BranchE <= 1'b0; //NOBRANCH\\\\n endcase\\\\nend\\\\n\\\\n\\\\nendmodule"]
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['module D_CMP(\\\\n input [31:0] i_cmpA,\\\\n input [31:0] i_cmpB,\\\\n input [3 :0] i_branchOp,\\\\n output o_jumpEn_of_B\\\\n); \\\\n wire cmp_signed_less = $signed(i_cmpA) < $signed(i_cmpB);\\\\n wire cmp_signed_less_or_equal = $signed(i_cmpA) <= $signed(i_cmpB);\\\\n wire cmp_signed_greater = $signed(i_cmpA) > $signed(i_cmpB);\\\\n wire cmp_signed_greater_or_equal = $signed(i_cmpA) >= $signed(i_cmpB);\\\\n assign o_jumpEn_of_B = (i_branchOp == `CMP_EQUAL ) ? (i_cmpA == i_cmpB ) :\\\\n (i_branchOp == `CMP_NOT_EQUAL ) ? (i_cmpA != i_cmpB ) :\\\\n (i_branchOp == `CMP_SIGNED_LESS ) ? (cmp_signed_less ) :\\\\n (i_branchOp == `CMP_SIGNED_LESS_OR_EQUAL ) ? (cmp_signed_less_or_equal ) :\\\\n (i_branchOp == `CMP_UNSIGNED_LESS ) ? (i_cmpA < i_cmpB ) :\\\\n (i_branchOp == `CMP_UNSIGNED_LESS_OR_EQUAL ) ? (i_cmpA <= i_cmpB ) :\\\\n (i_branchOp == `CMP_SIGNED_GREATER ) ? (cmp_signed_greater ) :\\\\n (i_branchOp == `CMP_SIGNED_GREATWER_OR_EQUAL ) ? (cmp_signed_greater_or_equal ) :\\\\n (i_branchOp == `CMP_UNSIGNED_GREATER ) ? (i_cmpA > i_cmpB ) :\\\\n (i_branchOp == `CMP_UNSIGNED_GREATWE_OR_EQUAL) ? (i_cmpA >= i_cmpB ) :\\\\n 0;\\\\nendmodule']
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["module CPU(\\\\n input reset, clk,\\\\n output [7: 0] bcds, leds,\\\\n output [3: 0] ano,\\\\n // output [31: 0] RegisterData [31: 0],\\\\n output [15: 0] DataMemoryData\\\\n // input [1: 0] choose_RF_data_out,\\\\n // output reg [7: 0] RF_data_out_reg\\\\n );\\\\n\\\\nwire [31: 0] RegisterData [31: 0];\\\\n\\\\nwire Stall;\\\\nwire [1: 0] Interrupt_out;\\\\n// reg IRQ_IF = 0;\\\\nreg [31 : 0] PC = 0;\\\\nwire [31 : 0] PC_next;\\\\nwire [31: 0] PC_next_next;\\\\nalways @(posedge clk)\\\\n if (reset)\\\\n begin\\\\n PC <= 32'h80000000;\\\\n // IRQ_IF <= 0;\\\\n end\\\\n else\\\\n if(Stall)\\\\n begin\\\\n PC <= PC;\\\\n // IRQ_IF <= IRQ_IF;\\\\n end\\\\n else\\\\n begin\\\\n PC <= PC_next_next;\\\\n // IRQ_IF <= Interrupt_out;\\\\n end\\\\n\\\\n\\\\nwire Interrupt;\\\\nreg Exception = 0;\\\\nassign Interrupt_out = PC[31] ? 0 :\\\\n Interrupt ? 2'b10 : Exception ? 2'b11 : 2'b00;\\\\nassign PC_next_next = Interrupt_out == 2'b11 ? 32'h80000008 : Interrupt_out == 2'b10 ? 32'h80000004 : PC_next;\\\\n\\\\nwire [31 : 0] PC_plus_4_IF = PC + 32'd4;\\\\n\\\\n\\\\nwire [31 : 0] Instruction_IF;\\\\nInstructionMemory2 instruction_memory1(.Address(PC), .Instruction(Instruction_IF));\\\\n\\\\n\\\\n// IF / ID Register below\\\\nwire [31: 0] Instruction_ID;\\\\nwire [31: 0] PC_plus_4_ID;\\\\nwire JumpFlush;\\\\nwire BranchFlush;\\\\n// wire IRQ_ID;\\\\nIF_ID_reg IF_ID(.reset(reset), .clk(clk), .stall(Stall),\\\\n .InstructionInput(Instruction_IF),\\\\n .InstructionOutput(Instruction_ID),\\\\n .PC_plus4_IF(PC_plus_4_IF),\\\\n .PC_plus4_ID(PC_plus_4_ID),\\\\n .PC_FlushIn(PC_next + 4),\\\\n .Flush(JumpFlush || BranchFlush || Interrupt_out[1])\\\\n // .IRQ_ID(IRQ_ID)\\\\n );\\\\n// IF / ID Register above\\\\n\\\\n\\\\nwire RegWrite_ID;\\\\nwire [1: 0] MemtoReg_ID;\\\\nwire MemRead_ID;\\\\nwire MemWrite_ID;\\\\nwire ALUSrc1_ID;\\\\nwire ALUSrc2_ID;\\\\nwire LuOp_ID;\\\\nwire [3 : 0]ALUOp_ID;\\\\nwire [1: 0] RegDst_ID;\\\\nwire ExtOp;\\\\n\\\\n\\\\nwire [1: 0] PCSrc;\\\\nwire Branch;\\\\n\\\\nwire ClearControl;\\\\nControl control1(\\\\n .OpCode(Instruction_ID[31: 26]), .Funct(Instruction_ID[5: 0]),\\\\n .Clear(ClearControl),\\\\n .PCSrc(PCSrc), .Branch(Branch),\\\\n .RegWrite(RegWrite_ID), .MemtoReg(MemtoReg_ID),\\\\n .MemRead(MemRead_ID), .MemWrite(MemWrite_ID),\\\\n .ALUSrc1(ALUSrc1_ID), .ALUSrc2(ALUSrc2_ID), .LuOp(LuOp_ID), .ALUOp(ALUOp_ID), .RegDst(RegDst_ID),\\\\n .ExtOp(ExtOp),\\\\n .Flush_IF_ID(JumpFlush)\\\\n );\\\\n// wire [127: 0] RF_data_out;\\\\n// always @( * )\\\\n// case (choose_RF_data_out)\\\\n// 0:\\\\n// RF_data_out_reg = RF_data_out[7: 0];\\\\n// 1:\\\\n// RF_data_out_reg = RF_data_out[39: 32];\\\\n// 2:\\\\n// RF_data_out_reg = RF_data_out[71: 64];\\\\n// 3:\\\\n// RF_data_out_reg = RF_data_out[103: 96];\\\\n// endcase\\\\n\\\\n\\\\nwire [31: 0] RegReadData1_init, RegReadData2_init, WriteBackResult;\\\\nreg [4: 0] Write_register_ME = 0;\\\\nreg [31: 0] PC_plus_4 [3: 2] = '{4, 4};\\\\n\\\\nRegisterFile register_file1(\\\\n .reset(reset), .clk(clk),\\\\n .RegWrite(RegWrite[3]),\\\\n .Read_register1(Instruction_ID[25: 21]), .Read_register2(Instruction_ID[20: 16]),\\\\n .Write_register(Write_register_ME), .Write_data(WriteBackResult),\\\\n .WriteData_26(PC_plus_4[2] - 4), .isWrite_26(Interrupt_out[1]),\\\\n .Read_data1(RegReadData1_init), .Read_data2(RegReadData2_init),\\\\n .RF_data_out(RegisterData)\\\\n // .RF_data_out(RF_data_out)\\\\n );\\\\n\\\\nwire [1: 0] ForwardA, ForwardB;\\\\nwire [31: 0] ALU_out_EX;\\\\nwire [31: 0] RegReadData1_ID =\\\\n (ForwardA == 0) ? RegReadData1_init :\\\\n (ForwardA == 1) ? WriteBackResult : ALU_out_EX;\\\\nwire [31: 0] RegReadData2_ID =\\\\n (ForwardB == 0) ? RegReadData2_init:\\\\n (ForwardB == 1) ? WriteBackResult : ALU_out_EX;\\\\n\\\\n\\\\nwire [31: 0] ExtResult_ID = {ExtOp ? {16{Instruction_ID[15]}} : 16'h0000, Instruction_ID[15 : 0]};\\\\nwire [31: 0] LeftShift16Result_ID = {Instruction_ID[15 : 0], 16'h0000};\\\\n\\\\nwire [4: 0] Write_register_EX;\\\\nHazardUnit hazardUnit1(\\\\n .ID_EX_MenRead(MemRead[2]),\\\\n .ID_EX_WriteRegister(Write_register_EX), .IF_ID_ReadRegister1(Instruction_ID[25: 21]), .IF_ID_ReadRegister2(Instruction_ID[20: 16]),\\\\n .Stall(Stall), .ClearControl(ClearControl)\\\\n );\\\\n\\\\n\\\\n// ID / EX Register below\\\\nreg RegWrite [3: 2] = '{0,0};\\\\nreg [1: 0] MemtoReg [3: 2] = '{0,0};\\\\nreg MemRead [3: 2] = '{0,0};\\\\nreg MemWrite [3: 2] = '{0,0};\\\\nreg ALUSrc1_EX = 0;\\\\nreg ALUSrc2_EX = 0;\\\\nreg LuOp_EX = 0;\\\\nreg [3 : 0] ALUOp_EX = 0;\\\\nreg [1: 0] RegDst_EX = 0;\\\\nreg [31: 0] RegReadData1_EX = 0, RegReadData2_EX = 0;\\\\nreg [31: 0] ExtResult_EX = 0, LeftShift16Result_EX = 0;\\\\nreg [31: 0] Instruction_EX = 0;\\\\nalways @(posedge clk)\\\\nbegin\\\\n PC_plus_4[2] <= reset ? 4 : (BranchFlush || Interrupt_out[1]) ? PC_next + 4 : PC_plus_4_ID;\\\\n if(reset || BranchFlush || Interrupt_out[1])\\\\n begin\\\\n RegWrite[2] <= 0;\\\\n MemtoReg[2] <= 0;\\\\n MemRead[2] <= 0;\\\\n MemWrite[2] <= 0;\\\\n ALUSrc1_EX <= 0;\\\\n ALUSrc2_EX <= 0;\\\\n LuOp_EX <= 0;\\\\n ALUOp_EX <= 0;\\\\n RegDst_EX <= 0;\\\\n RegReadData1_EX <= 0;\\\\n RegReadData2_EX <= 0;\\\\n ExtResult_EX <= 0;\\\\n LeftShift16Result_EX <= 0;\\\\n Instruction_EX <= 0;\\\\n end\\\\n else\\\\n begin\\\\n RegWrite[2] <= RegWrite_ID;\\\\n MemtoReg[2] <= MemtoReg_ID;\\\\n MemRead[2] <= MemRead_ID;\\\\n MemWrite[2] <= MemWrite_ID;\\\\n ALUSrc1_EX <= ALUSrc1_ID;\\\\n ALUSrc2_EX <= ALUSrc2_ID;\\\\n LuOp_EX <= LuOp_ID;\\\\n ALUOp_EX <= ALUOp_ID;\\\\n RegDst_EX <= RegDst_ID;\\\\n RegReadData1_EX <= RegReadData1_ID;\\\\n RegReadData2_EX <= RegReadData2_ID;\\\\n ExtResult_EX <= ExtResult_ID;\\\\n LeftShift16Result_EX <= LeftShift16Result_ID;\\\\n Instruction_EX <= Instruction_ID[31: 0];\\\\n end\\\\nend\\\\n// ID / EX Register above\\\\n\\\\nwire [31: 0] LU_out = LuOp_EX ? LeftShift16Result_EX : ExtResult_EX;\\\\n\\\\nwire [4: 0] ALUCtrl;\\\\nwire Sign;\\\\nALUControl alu_control1(\\\\n .ALUOp(ALUOp_EX), .Funct(Instruction_EX[5: 0]),\\\\n .ALUCtl(ALUCtrl), .Sign(Sign)\\\\n );\\\\n\\\\nreg [31: 0] ALU_out_ME = 0;\\\\nwire [31: 0] ALU_in1 =\\\\n ALUSrc1_EX ? {17'h00000, Instruction_EX[10 : 6]} : RegReadData1_EX;\\\\n\\\\nwire [31: 0] ALU_in2 =\\\\n ALUSrc2_EX ? LU_out : RegReadData2_EX;\\\\n\\\\nwire Zero;\\\\nALU alu1(\\\\n .in1(ALU_in1),\\\\n .in2(ALU_in2),\\\\n .ALUCtl(ALUCtrl),\\\\n .Sign(Sign),\\\\n .out(ALU_out_EX),\\\\n .zero(Zero)\\\\n );\\\\n\\\\nassign Write_register_EX =\\\\n (RegDst_EX == 0) ? Instruction_EX[20: 16] :\\\\n (RegDst_EX == 1) ? Instruction_EX[15: 11] : 31;\\\\n\\\\nwire isPCFromBranch;\\\\nBranchHazardUnit branchHazardUnit1(\\\\n .OpCode(Instruction_EX[31: 26]),\\\\n .ALU_in_1(ALU_in1), .ALU_in_2(ALU_in2),\\\\n .isPCFromBranch(isPCFromBranch),\\\\n .BranchFlush(BranchFlush)\\\\n );\\\\n\\\\nassign PC_next =\\\\n (isPCFromBranch) ? PC_plus_4[2] + {LU_out[29: 0], 2'b00} :\\\\n (PCSrc == 0) ? PC_plus_4_IF :\\\\n (PCSrc == 1) ? {PC_plus_4_IF[31: 28], Instruction_ID[25: 0], 2'b00}:\\\\n RegReadData1_ID;\\\\n\\\\n\\\\n// EX / ME Register below\\\\nreg [31: 0] WriteData_ME = 0;\\\\nalways @(posedge clk)\\\\n if(reset || Interrupt_out[1])\\\\n begin\\\\n RegWrite[3] <= 0;\\\\n MemtoReg[3] <= 0;\\\\n MemRead[3] <= 0;\\\\n MemWrite[3] <= 0;\\\\n ALU_out_ME <= 0;\\\\n WriteData_ME <= 0;\\\\n Write_register_ME <= 0;\\\\n PC_plus_4[3] <= 4;\\\\n end\\\\n else\\\\n begin\\\\n RegWrite[3] <= RegWrite[2];\\\\n MemtoReg[3] <= MemtoReg[2];\\\\n MemRead[3] <= MemRead[2];\\\\n MemWrite[3] <= MemWrite[2];\\\\n ALU_out_ME <= ALU_out_EX;\\\\n WriteData_ME <= RegReadData2_EX;\\\\n Write_register_ME <= Write_register_EX;\\\\n PC_plus_4[3] <= PC_plus_4[2];\\\\n end\\\\n// EX / ME Register above\\\\n\\\\n\\\\nwire [31: 0] Read_data_ME;\\\\nDataMemory data_memory1(\\\\n .reset(reset),\\\\n .clk(clk),\\\\n .Address(ALU_out_ME),\\\\n .Write_data(WriteData_ME),\\\\n .Read_data(Read_data_ME),\\\\n .MemRead(MemRead[3]),\\\\n .MemWrite(MemWrite[3]),\\\\n .Interrupt(Interrupt),\\\\n .LEDs(leds),\\\\n .bcds(bcds),\\\\n .ano(ano),\\\\n .DataMemory_out(DataMemoryData)\\\\n );\\\\n\\\\n\\\\nForwardingUnit forwardingUnit1(\\\\n .EX_ME_RegWrite(RegWrite[2]), .ME_WB_RegWrite(RegWrite[3]),\\\\n .EX_ME_WriteRegister(Write_register_EX), .ME_WB_WriteRegister(Write_register_ME),\\\\n .ID_EX_ReadRegister1(Instruction_ID[25: 21]), .ID_EX_ReadRegister2(Instruction_ID[20: 16]),\\\\n .ForwardA(ForwardA), .ForwardB(ForwardB));\\\\n\\\\n// ME / WB Register\\\\n// reg [31: 0] Read_data_WB = 0;\\\\n// reg [31: 0] ALU_out_WB = 0;\\\\n// always @(posedge clk)\\\\n// if(reset)\\\\n// begin\\\\n// // Read_data_WB <= 0;\\\\n// // ALU_out_WB <= 0;\\\\n// // RegWrite[4] <= 0;\\\\n// // MemtoReg[4] <= 0;\\\\n// // Write_register[4] <= 0;\\\\n// // PC_plus_4[4] <= 0;\\\\n// end\\\\n// else\\\\n// begin\\\\n// // Read_data_WB <= Read_data_ME;\\\\n// // ALU_out_WB <= ALU_out_ME;\\\\n// // RegWrite[4] <= RegWrite[3];\\\\n// // MemtoReg[4] <= MemtoReg[3];\\\\n// // Write_register[4] <= Write_register[3];\\\\n// // PC_plus_4[4] <= PC_plus_4[3];\\\\n// end\\\\n// ME / WB Register\\\\n\\\\n\\\\nassign WriteBackResult = (MemtoReg[3] == 2'b00) ? ALU_out_ME : (MemtoReg[3] == 2'b01) ? Read_data_ME : PC_plus_4[3];\\\\n\\\\n\\\\nendmodule"]
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["module pmod_als_spi_receiver\\\\n(\\\\n input clock,\\\\n input reset,\\\\n output cs,\\\\n output sck,\\\\n input sdo,\\\\n output reg [15:0] value\\\\n);\\\\n\\\\n reg [21:0] cnt;\\\\n reg [15:0] shift;\\\\n\\\\n always @ (posedge clock or posedge reset)\\\\n begin \\\\n if (reset)\\\\n cnt <= 22'b100;\\\\n else\\\\n cnt <= cnt + 22'b1;\\\\n end\\\\n\\\\n assign sck = ~ cnt [3];\\\\n assign cs = cnt [8];\\\\n\\\\n wire sample_bit = ( cs == 1'b0 && cnt [3:0] == 4'b1111 );\\\\n wire value_done = ( cnt [21:0] == 22'b0 );\\\\n\\\\n always @ (posedge clock or posedge reset)\\\\n begin \\\\n if (reset)\\\\n begin \\\\n shift <= 16'h0000;\\\\n value <= 16'h0000;\\\\n end\\\\n else if (sample_bit)\\\\n begin \\\\n shift <= (shift << 1) | sdo;\\\\n end\\\\n else if (value_done)\\\\n begin \\\\n value <= shift;\\\\n end\\\\n end\\\\n\\\\nendmodule"]
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["module BE(\\\\n input [31:0] data_w_in,\\\\n input [1:0] addr_low,\\\\n input [2:0] write_type,\\\\n output [31:0] data_w_out,\\\\n output [3:0] data_w_byteen,\\\\n input req\\\\n );\\\\n \\\\n reg [31:0] r_data_w_out;\\\\n reg [3 :0] r_data_w_byteen;\\\\n\\\\n always @(*) begin\\\\n if (write_type == `Word) begin\\\\n r_data_w_byteen <= 4'b1111;\\\\n r_data_w_out <= data_w_in;\\\\n end\\\\n else if (write_type == `Half) begin\\\\n if (addr_low[1] == 1'b1) begin\\\\n r_data_w_byteen <= 4'b1100;\\\\n r_data_w_out <= {data_w_in[15:0], 16'b0};\\\\n end\\\\n else begin\\\\n r_data_w_byteen <= 4'b0011;\\\\n r_data_w_out <= {16'b0, data_w_in[15:0]};\\\\n end\\\\n end\\\\n else if (write_type == `Byte) begin\\\\n if (addr_low == 2'b00) begin\\\\n r_data_w_byteen <= 4'b0001;\\\\n r_data_w_out <= {24'b0, data_w_in[7:0]};\\\\n end\\\\n else if (addr_low == 2'b01) begin\\\\n r_data_w_byteen <= 4'b0010;\\\\n r_data_w_out <= {16'b0, data_w_in[7:0], 8'b0};\\\\n end\\\\n else if (addr_low == 2'b10) begin\\\\n r_data_w_byteen <= 4'b0100;\\\\n r_data_w_out <= {8'b0, data_w_in[7:0], 16'b0};\\\\n end\\\\n else if (addr_low == 2'b11) begin\\\\n r_data_w_byteen <= 4'b1000;\\\\n r_data_w_out <= {data_w_in[7:0], 24'b0};\\\\n end\\\\n end\\\\n else begin\\\\n r_data_w_byteen <= 4'b0000;\\\\n r_data_w_out <= data_w_in;\\\\n end\\\\n end\\\\n \\\\n assign data_w_byteen = r_data_w_byteen & {4{~req}};\\\\n assign data_w_out = r_data_w_out;\\\\n\\\\nendmodule"]
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["module LATCH_MUL #(\\\\n parameter\\\\n DWIDTH = 32\\\\n) (\\\\n input wire START,\\\\n input wire [DWIDTH - 1: 0] INA,\\\\n input wire [DWIDTH - 1: 0] INB,\\\\n output wire [DWIDTH - 1: 0] OUT\\\\n);\\\\n\\\\n reg [DWIDTH - 1: 0] REGA, REGB;\\\\n wire [DWIDTH - 1: 0] WIRE_OUT;\\\\n assign OUT = WIRE_OUT;\\\\n\\\\n FLOATING_32BIT_MUL mul (.INA(REGA), .INB(REGB), .OUT(WIRE_OUT));\\\\n always @(INA or INB) begin\\\\n if (!START) begin\\\\n {REGA, REGB} <= {DWIDTH{1'b0}};\\\\n end else begin\\\\n {REGA, REGB} <= {INA, INB};\\\\n end\\\\n end\\\\n \\\\nendmodule", "module SWITCH_ADD #(\\\\n parameter\\\\n DWIDTH = 32\\\\n) (\\\\n input wire CLOCK,\\\\n input wire START,\\\\n input wire [DWIDTH - 1: 0] IN,\\\\n output wire [DWIDTH - 1: 0] OUT\\\\n);\\\\n\\\\n reg [DWIDTH - 1: 0] REGA = 0, REGB = 0;\\\\n wire [DWIDTH - 1: 0] WSUM;\\\\n assign OUT = WSUM;\\\\n FLOATING_32BIT_ADD add (\\\\n .INA(REGA), \\\\n .INB(REGB),\\\\n .OUT(WSUM)\\\\n );\\\\n\\\\n reg flag = 0;\\\\n always @(negedge CLOCK) begin\\\\n if (!START) begin\\\\n flag <= 0;\\\\n end else begin\\\\n if (!flag) begin\\\\n flag <= 1;\\\\n {REGA, REGB} <= {{DWIDTH{1'b0}}, IN}; \\\\n end else begin\\\\n {REGA, REGB} <= {WSUM, IN};\\\\n end\\\\n end\\\\n end\\\\n\\\\nendmodule", 'module MatrixMulSingleCore #(\\\\n parameter\\\\n DWIDTH = 32,\\\\n SIZE = DWIDTH\\\\n\\\\n) (\\\\n input wire CLOCK , \\\\n input wire START ,\\\\n input wire [SIZE - 1: 0] STREAM_A,\\\\n input wire [SIZE - 1: 0] STREAM_B,\\\\n output wire [DWIDTH - 1: 0] STREAM_O\\\\n);\\\\n \\\\n wire [DWIDTH - 1: 0] WIRE_AB, WIRE_SUM;\\\\n assign STREAM_O = WIRE_SUM;\\\\n\\\\n LATCH_MUL #(\\\\n .DWIDTH(DWIDTH)\\\\n ) latch (\\\\n .START (START ),\\\\n .INA (STREAM_A ), \\\\n .INB (STREAM_B ), \\\\n .OUT (WIRE_AB )\\\\n );\\\\n SWITCH_ADD #(\\\\n .DWIDTH(DWIDTH)\\\\n ) switch (\\\\n .CLOCK (CLOCK ),\\\\n .START (START ), \\\\n .IN (WIRE_AB ),\\\\n .OUT (WIRE_SUM )\\\\n );\\\\n\\\\nendmodule', 'module MatrixMul2Cores #(\\\\n parameter\\\\n DWIDTH = 32,\\\\n CORES = 2,\\\\n SIZE = DWIDTH * CORES\\\\n\\\\n) (\\\\n input wire CLOCK ,\\\\n input wire START ,\\\\n input wire [SIZE - 1: 0] STREAM_A,\\\\n input wire [SIZE - 1: 0] STREAM_B,\\\\n output wire [DWIDTH - 1: 0] STREAM_O\\\\n);\\\\n\\\\n generate\\\\n genvar i, j, k;\\\\n wire [DWIDTH - 1: 0] WIRE_SUM;\\\\n assign STREAM_O = WIRE_SUM;\\\\n\\\\n wire [DWIDTH - 1: 0] OUTPUT [0: CORES - 1];\\\\n for (i = 0; i < CORES; i = i + 1) begin: gen_cores\\\\n MatrixMulSingleCore core (\\\\n .CLOCK (CLOCK ), \\\\n .START (START ), \\\\n .STREAM_A (STREAM_A[(DWIDTH * (i + 1)) - 1: DWIDTH * i]), \\\\n .STREAM_B (STREAM_B[(DWIDTH * (i + 1)) - 1: DWIDTH * i]), \\\\n .STREAM_O (OUTPUT[i] )\\\\n );\\\\n end\\\\n FLOATING_32BIT_ADD add (\\\\n .INA (OUTPUT[0]), \\\\n .INB (OUTPUT[1]),\\\\n .OUT (WIRE_SUM )\\\\n );\\\\n endgenerate\\\\n\\\\nendmodule', 'module MatrixMul4Cores #(\\\\n parameter\\\\n DWIDTH = 32,\\\\n CORES = 4,\\\\n SIZE = DWIDTH * CORES\\\\n\\\\n) (\\\\n input wire CLOCK ,\\\\n input wire START ,\\\\n input wire [SIZE - 1: 0] STREAM_A,\\\\n input wire [SIZE - 1: 0] STREAM_B,\\\\n output wire [DWIDTH - 1: 0] STREAM_O\\\\n);\\\\n\\\\n generate\\\\n genvar i, j, k;\\\\n wire [DWIDTH - 1: 0] OUTPUT [0: CORES * 2 - 2];\\\\n assign STREAM_O = OUTPUT[CORES * 2 - 2];\\\\n for (i = 0; i < CORES; i = i + 1) begin: gen_cores_mull\\\\n MatrixMulSingleCore core (\\\\n .CLOCK (CLOCK ), \\\\n .START (START ), \\\\n .STREAM_A (STREAM_A[(DWIDTH * (i + 1)) - 1: DWIDTH * i]), \\\\n .STREAM_B (STREAM_B[(DWIDTH * (i + 1)) - 1: DWIDTH * i]), \\\\n .STREAM_O (OUTPUT[i] )\\\\n );\\\\n end\\\\n\\\\n for (i = 0; i < CORES - 1; i = i + 1) begin: gen_cores_add\\\\n FLOATING_32BIT_ADD add (\\\\n .INA(OUTPUT[i * 2] ), \\\\n .INB(OUTPUT[i * 2 + 1]), \\\\n .OUT(OUTPUT[i + CORES])\\\\n ); \\\\n end\\\\n endgenerate\\\\n\\\\nendmodule', 'module MatrixMul8Cores #(\\\\n parameter\\\\n DWIDTH = 32,\\\\n CORES = 8,\\\\n SIZE = DWIDTH * CORES\\\\n\\\\n) (\\\\n input wire CLOCK ,\\\\n input wire START ,\\\\n input wire [SIZE - 1: 0] STREAM_A,\\\\n input wire [SIZE - 1: 0] STREAM_B,\\\\n output wire [DWIDTH - 1: 0] STREAM_O\\\\n);\\\\n\\\\n MatrixMul4Cores #(\\\\n .DWIDTH(DWIDTH), \\\\n .CORES (CORES )\\\\n ) cores (\\\\n .CLOCK (CLOCK ),\\\\n .START (START ),\\\\n .STREAM_A (STREAM_A),\\\\n .STREAM_B (STREAM_B),\\\\n .STREAM_O (STREAM_O)\\\\n );\\\\n\\\\nendmodule', 'module MatrixMul16Cores #(\\\\n parameter\\\\n DWIDTH = 32,\\\\n CORES = 16,\\\\n SIZE = DWIDTH * CORES\\\\n\\\\n) (\\\\n input wire CLOCK ,\\\\n input wire START ,\\\\n input wire [SIZE - 1: 0] STREAM_A,\\\\n input wire [SIZE - 1: 0] STREAM_B,\\\\n output wire [DWIDTH - 1: 0] STREAM_O\\\\n);\\\\n\\\\n MatrixMul4Cores #(\\\\n .DWIDTH(DWIDTH), \\\\n .CORES (CORES )\\\\n ) cores (\\\\n .CLOCK (CLOCK ),\\\\n .START (START ),\\\\n .STREAM_A(STREAM_A),\\\\n .STREAM_B(STREAM_B),\\\\n .STREAM_O(STREAM_O)\\\\n );\\\\n\\\\nendmodule', 'module MatrixMul32Cores #(\\\\n parameter\\\\n DWIDTH = 32,\\\\n CORES = 32,\\\\n SIZE = DWIDTH * CORES\\\\n\\\\n) (\\\\n input wire CLOCK ,\\\\n input wire START ,\\\\n input wire [SIZE - 1: 0] STREAM_A,\\\\n input wire [SIZE - 1: 0] STREAM_B,\\\\n output wire [DWIDTH - 1: 0] STREAM_O\\\\n);\\\\n\\\\n MatrixMul4Cores #(\\\\n .DWIDTH(DWIDTH), \\\\n .CORES (CORES )\\\\n ) cores (\\\\n .CLOCK (CLOCK ),\\\\n .START (START ),\\\\n .STREAM_A(STREAM_A),\\\\n .STREAM_B(STREAM_B),\\\\n .STREAM_O(STREAM_O)\\\\n );\\\\n\\\\nendmodule', 'module MatrixMulManyCores #(\\\\n parameter\\\\n DWIDTH = 32,\\\\n CORES = 64,\\\\n SIZE = DWIDTH * CORES\\\\n\\\\n) (\\\\n input wire CLOCK ,\\\\n input wire START ,\\\\n input wire [SIZE - 1: 0] STREAM_A,\\\\n input wire [SIZE - 1: 0] STREAM_B,\\\\n output wire [DWIDTH - 1: 0] STREAM_O\\\\n);\\\\n\\\\n MatrixMul4Cores #(\\\\n .DWIDTH(DWIDTH), \\\\n .CORES (CORES )\\\\n ) cores (\\\\n .CLOCK (CLOCK ),\\\\n .START (START ),\\\\n .STREAM_A(STREAM_A),\\\\n .STREAM_B(STREAM_B),\\\\n .STREAM_O(STREAM_O)\\\\n );\\\\n\\\\nendmodule']
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