abi011020/eda_verilog_code_200k · Datasets at Hugging Face

code string
["module alu_control(\\\\n input wire [`ALU_OP_WIDTH-1 : 0] alu_op, \\\\n input wire [2 : 0] funct3,\\\\n input wire funct7_30, // SUB and SRA \\\\n input wire funct7_25, // RV32M extension \\\\n output reg [`AL...
["module ALU_control(\\\\n input [1:0] ALUop,\\\\n input [2:0] funct3,\\\\n input funct7,\\\\n input [4:0]opcode,\\\\n output reg [3:0] ALUsel\\\\n );\\\\n\\\\n always @(*)begin\\\\n case(ALUop)\\\\n 2'b00: ALUsel = `ALU_ADD; \\\\n 2'b01: ALUsel = `ALU_SUB;\\\\n 2'b11...
["module sum(\\\\n input clk, rst_n,\\\\n input a_valid, b_valid, c_valid, d_valid,\\\\n input [8:0] a_data_in, b_data_in, c_data_in, d_data_in,\\\\n \\\\n output reg [8:0] data_out,\\\\n output reg out_valid,\\\\n output reg [2:0] output_counter\\\\n );\\\\n \\\\n reg [10:0] input_reg [5:...
["module shift_reg (\\\\n input wire clk,\\\\n input wire clr,\\\\n input wire load, shift,\\\\n input wire [7:0] Data,\\\\n output reg tx_data\\\\n);\\\\n\\\\n reg [7:0] shr; // Register to hold the data bits\\\\n\\\\n // Output assignment\\\\n assign tx_data = shr[0]; // Output the LSB of the...
['module sine_stepper // #(.data_size(xx)) \\\\n(\\\\n input clock,\\\\n input [1:0]frequency, //200, 400, 800, 1600\\\\n output wire [5:0]step,\\\\n output wire [15:0]wave\\\\n);\\\\nparameter two_hundred = 0;\\\\nparameter four_hundred = 1;\\\\nparameter eight_hundred = 2;\\\\nparameter one_six_hundred =...
["module rand_gen(\\\\n input wire clk100,\\\\n input wire rst, \\\\n output reg [10:0] orbit_sin_addr, //rand number for sin ROM addr, [10:]\\\\n output reg [9:0] orbit_log_addr //rand number for log ROM addr, [9:0]\\\\n );\\\\n\\\\nwire [10:0] orbit_1;\\\\nwire [10:0] ...
["module test(\\\\n input clkp,\\\\n input clkn,\\\\n output led\\\\n);\\\\n wire clk;\\\\n\\\\n assign led = ~led_show;\\\\n\\\\n reg led_show;\\\\n\\\\n localparam CNT = 32'd200_000_000;\\\\n reg [31:0] num_cnt;\\\\n reg [7:0] state, next_state;\\\\n localparam ID00 = 8'h00, IW00 = 8'h01...
['module registro #(parameter WIDTH = 4)\\\\n(\\\\noutput reg [WIDTH-1 : 0] Q,\\\\noutput reg S_OUT,\\\\n\\\\ninput wire [WIDTH-1 : 0] D,\\\\ninput wire [1 : 0] MODO,\\\\ninput wire CLK, ENB, DIR, S_IN, ITER\\\\n);\\\\n\\\\nalways @ (posedge CLK) begin\\\\n if (~ENB) be...
["module mul_3_stage(\\\\n input [63:0] input_mul, //inputa[63:32] inputb[31:0]\\\\n input input_mul_stb, \\\\n output reg s_input_mul_ack, \\\\n input clk,\\\\n input rst,\\\\n output reg [31:0] z,\\\\n output reg s_output_z_stb, //output z valid\\...
["module simple_spi(CLOCK_50, GPIO_0, KEY, LEDR);\\\\n\\\\ninput MAX10_CLK1_50;\\\\ninput [35:0] GPIO;\\\\ninput [1:0] KEY;\\\\noutput [9:0] LEDR;\\\\n\\\\nwire sys_clk = MAX10_CLK1_50;\\\\nwire sys_rst_n = KEY[1];\\\\n\\\\nwire spi_sck = GPIO[0];\\\\nwire spi_cs = GPIO[1]...
["module volume_bar(input clk, [1:0] border, [1:0] bar, [6:0] bar_pos,\\\\n [6:0] pixel_x, [5:0] pixel_y, [3:0] vol,\\\\n output reg [15:0] pixel_data);\\\\n always @(posedge clk) begin\\\\n //border\\\\n if (pixel_x < 1 \|\| pixel_x > 94 \|\| pixel_y < 1 \|\| pixel_y > ...
['module queue_2bit (clk, rst, rst_front, dequeue, ld, ld_data, rear_index_in, data_out, finish);\\\\n input clk, rst, rst_front, dequeue, ld;\\\\n input [8:0] rear_index_in;\\\\n input [1:0] ld_data [0:256];\\\\n output reg[1:0] data_out;\\\\n output finish;\\\\n reg [1:0] queue_data[0:256];\\\\n ...
['module ALUControl (\\\\n input [5:0] Funct,\\\\n input [2:0] ALUCtrl,\\\\n output reg [3:0] ALUOp\\\\n );\\\\n\\\\n always @(*) begin\\\\n case (ALUCtrl)\\\\n `AluCtrl_R: begin\\\\n case (Funct)\\\\n `Funct_Add : ALUOp <= `AluOp_Add;\\\\n ...
["module AuxDivider(clk, rst_n, clk_out);\\\\n function integer Log2Ceil(input time cnt_max);\\\\n for (Log2Ceil = 0; cnt_max; Log2Ceil = Log2Ceil + 1)\\\\n cnt_max = cnt_max >> 1;\\\\n endfunction\\\\n parameter CntMax = `CNT_SEC(1);\\\\n parameter CntHalf = CntMax / 2;\\\\n localparam...
["module lsfr(clk, reset, enable, Y );\\\\n\\\\n input clk;\\\\n input reset;\\\\n input enable;\\\\n output [2:0] Y = 3'b001;\\\\n reg [2:0] Y, Y_next;\\\\n reg w1;\\\\n reg [2:0] w2;\\\\n \\\\n always @(posedge clk or negedge reset) begin\\\\n if (reset==1'b0) begin\\\\n Y...
["module top(\\\\n input wire clk_pix,\\\\n output wire [12:0] h,\\\\n output wire [12:0] v,\\\\n output wire [7:0] sdl_r,\\\\n output wire [7:0] sdl_g,\\\\n output wire [7:0] sdl_b,\\\\n output wire active\\\\n\\\\n);\\\\n\\\\n // Sync generator module\\\\n sync sync...
["module DataMemory(\\\\n input CLK,\\\\n input [31:0] address,\\\\n input [31:0] writeData,\\\\n input memWrite,\\\\n input memRead,\\\\n output [31:0] readData\\\\n );\\\\n \\\\n reg [7:0] memFile[0:31];\\\\n reg [31:0] readData;\\\\n \\\\n initial begin\\\\n memFile[0] = 8'...
['module line_shift(\\\\n input clk,\\\\n \\\\n input ycbcr_de,\\\\n input ycbcr_hs,\\\\n \\\\n input shiftin, \\\\n output taps0x, \\\\n output taps1x \\\\n);\\\\n\\\\nreg [2:0] clken_dly;\\\\nreg [9:0] ram_rd_addr;\\\\nreg [9:0] ram_rd_add...
["module instrMem(\\\\n input [31:0] A,\\\\n\\\\n output wire [31:0] RD\\\\n );\\\\n\\\\n reg [31:0] instr [256:0];\\\\n\\\\n initial\\\\n begin\\\\n // instr1\\\\n instr[0] <= {`lw, `gr0, `gr1, 16'h0003}; // lw gr1 <- address(32'b0+h0003)\\\\n instr[4] <= `nop;\\\\n...
["module divider(\\\\n input clk,\\\\n input rst,\\\\n input start, \\\\n input[31:0] dividend, \\\\n input[31:0] divisor, \\\\n output divide_zero, \\\\n output finish, \\\\n output[31:0] res, \\\\n output[31:0] rem \\\\n);\\\\n\\\\n reg status;\...
["module fir_core_core_fsm (\\\\n clk, rst, fsm_output\\\\n);\\\\n input clk;\\\\n input rst;\\\\n output [12:0] fsm_output;\\\\n reg [12:0] fsm_output;\\\\n\\\\n\\\\n // FSM State Type Declaration for fir_core_core_fsm_1\\\\n parameter\\\\n main_C_0 = 4'd0,\\\\n main_C_1 = 4'd1,\\\\n main_C_2 = 4'd2,\\...
["module AddressRegisterFile(Clock, I, OutCSel, OutDSel, FunSel, RegSel, OutC, OutD);\\\\n input wire Clock;\\\\n input wire [15:0] I;\\\\n input wire [1:0] OutCSel;\\\\n input wire [1:0] OutDSel;\\\\n input wire [2:0]FunSel;\\\\n input wire [2:0] RegSel;\\\\n output reg [15:0] OutC;\\\\n output...
["module sipo(\\\\n clk,\\\\n en,\\\\n data_in,\\\\n data_out\\\\n );\\\\n parameter [31:0]n = 1344;\\\\n parameter [31:0]m = 64;\\\\n input clk;\\\\n input en;\\\\n input [( m - 1 ):0] data_in;\\\\n output [( n - 1 ):0] data_out;\\\\n localparam regamount ...
["module top_module ( \\\\n input clk, \\\\n input [7:0] d, \\\\n input [1:0] sel, \\\\n output [7:0] q \\\\n);\\\\n wire clkWire1, clkWire2, clkWire3;\\\\n assign clkWire1 = clk;\\\\n assign clkWire2 = clkWire1;\\\\n assign clkWire3 = clkWire2;\\\\n // wire internalWire1, internalWire2, inte...
['module alu(\\\\n input [`RV_BIT_NUM-1:0] op1,\\\\n input [`RV_BIT_NUM-1:0] op2,\\\\n input [`RV_BIT_NUM-1:0] exe_adder,\\\\n input [`ALU_FUN_BIT_NUM-1:0] ctrl_alu_fun,\\\\n \\\\n output reg [`RV_BIT_NUM-1:0] exe_alu_out\\\\n );\\\\n \\\\n always@(*) begin\\\\n ...
["module top_module(\\\\n input clk,\\\\n input in,\\\\n input reset, // Synchronous reset\\\\n output [7:0] out_byte,\\\\n output done\\\\n); \\\\n // Use FSM from Fsm_serial\\\\n parameter idle=0,start=1,data=2,check=3,stop=4,error=5;\\\\n reg [2:0] state,nstate;\\\\n reg [3:0] cnt;\\\\n...
['module tmr_s1neuron #(parameter M=8, //# of input layer\\\\n parameter n=32,\\\\n parameter cl=8, //# of bits of fixed number \\\\n parameter intbits=12,\\\\n parameter fracbits=20)(\\\\n input [Mn-1:0] X,\\\\n input [M(n+cl...
['module universalRegister (\\\\n input wire SerialIn,\\\\n input wire [n-1:0] D,\\\\n input wire [2:0] ctrl,\\\\n input wire clk,\\\\n input wire rst_n,\\\\n output wire SerialOut,\\\\n output reg [n-1:0] Q\\\\n);\\\\n\\\\n parameter n = 4;\\\\n\\\\n // Behavioral description\\\\n always ...
['module bfu_nopipe (\\\\n input clk,\\\\n input reset,\\\\n input [`Datawidth:0] xin,\\\\n input [`Datawidth:0] yin,\\\\n input [`Datawidth:0] wr,\\\\n input en,\\\\n\\\\n output [`Datawidth:0] xout,\\\\n output [`Datawidth:0] yout,\\\\n output valid\\\\n);\\\\n\\\\n reg [`Datawidth+2:0] ...
["module fifo#(parameter WIDTH=8,DEPTH=16)(\\\\n input rst_n,\\\\n input [WIDTH-1:0]d_in,\\\\n input wr_en, w_clk,\\\\n input rd_en, rd_clk, \\\\n\\\\n output reg [WIDTH-1:0]d_out,\\\\n output full, empty);\\\\n \\\\n reg [$clog2(DEPTH)-1:0] rd_ptr;\\\\n reg [$clog2(DEPTH)-1:0] wr_ptr;\\\\n \\\\n //memory\\\...
["module AddressSelector(input [6:0] opcode,\\\\n input [4:0] cs_plus_1,\\\\n input [1:0] AddrCtl,\\\\n input alu_bcond,\\\\n output [4:0] next_state);\\\\n localparam ZERO = 5'd0;\\\\n \\\\n wire [1:0] branch_not_taken = {...
["module ALU(\\\\n input wire [31:0] Operand1,\\\\n input wire [31:0] Operand2,\\\\n input wire [3:0] AluContrl,\\\\n output reg [31:0] AluOut\\\\n );\\\\n \\\\n //ALU no need to modify, copy from lab1\\\\n // initial begin\\\\n // AluOut = 32'b0;\\\\n // end\\\\n\\\\n always @(*) b...
["module ALU(\\\\n input [1:0] opcode,\\\\n input [15:0] in0,\\\\n input [15:0] in1,\\\\n output reg [15:0] out\\\\n\\\\t //output reg [3:0] operation\\\\n );\\\\n \\\\n parameter low = 0;\\\\n \\\\n //subtractor wires\\\\n wire bin, bout;\\\\n wire [15:0] difference;\\\\n \\\\n /...
["module find_MAX(\\\\n input wire clk,\\\\n input wire rst_n,\\\\n input wire start,\\\\n input wire valid,\\\\n input wire [7:0] Data_A,\\\\n input wire [7:0] Data_B,\\\\n input wire one_left,\\\\n input wire [2:0] instruction,\\\\n output reg [7:0] maximum,\\\\n output reg finish\\\\n);...
["module tree(\\\\n input wire clk_25MHz,\\\\n input wire clk_1KHz,\\\\n input wire clk_100Hz,\\\\n input wire clk_50Hz,\\\\n input wire clk_25Hz,\\\\n input wire [31: 0] rand,\\\\n input wire rst,\\\\n input wire stop,\\\\n output reg [9: 0]x,\\\\n output reg [8: 0]y,\\\\n output reg [...
["module datamem (\\\\n input [31:0] WD,\\\\n input [31:0] A,\\\\n input clk,WE,rst,\\\\n output reg [31:0] RD\\\\n);\\\\n reg [31:0] Data_Mem [0:31];\\\\ninitial begin\\\\n Data_Mem[0] <= 32'h0x00000005;\\\\n Data_Mem[1] <= 32'h0xFFFFFFFB; //32'hFFC4A303; 0x8CDEFAB7\\\\n Data_Mem[2] <=...
["module clock_top\\\\n(\\\\ninput clk_ref_p,\\\\ninput clk_ref_n,\\\\ninput pcie_clk_p,\\\\ninput pcie_clk_n,\\\\noutput clk_out,\\\\noutput ref_clk,\\\\noutput clk_div\\\\n\\\\n);\\\\n\\\\n reg [1:0] clk_divide = 2'b00;\\\\n wire clk_out;\\\\n\\\\n IBUFDS diff_clk_200 (\\\\n .I (clk_ref_p),\\\\n .IB...
["module fifo_tx(clk_fifo_tx, data_in, next_frame, data_out);\\\\n\\\\n input[7:0] data_in;\\\\n input clk_fifo_tx;\\\\n input next_frame;\\\\n //output fifo_tx_status;\\\\n output reg[7:0] data_out;\\\\n \\\\n reg[15:0] fifo_tx_mem[7:0];\\\\n reg[3:0] wr_pt = 4'b0000;\\\...
["module counter(key_rst_en,key_ps_en,clk,numcount4_out,rst_n,numcount3_out,numcount2_out,numcount1_out);\\\\n input key_rst_en,key_ps_en,clk,rst_n;\\\\n\\\\toutput numcount4_out,numcount3_out,numcount2_out,numcount1_out;\\\\n\\\\t\\\\n\\\\treg [3:0]stcur_counter,stnext_counter,a;\\\\n\\\\treg [3:0]nu...
["module ALU_Control (\\\\n funct_i,\\\\n ALUOp_i,\\\\n ALUCtrl_o\\\\n);\\\\n\\\\n// Ports\\\\ninput [9:0] funct_i;\\\\ninput [1:0] ALUOp_i;\\\\noutput [2:0] ALUCtrl_o;\\\\n\\\\nreg [2:0] reg_o;\\\\n\\\\n// Output signal\\\\nalways @(funct_i or ALUOp_i) begin\\\\n if (ALUOp_i == 2'b10) begin...
["module ALU(\\\\n input wire[31:0] A,\\\\n input wire[3:0] alu_op,\\\\n //\\\\u9009\\\\u62e9\\\\n input wire[31:0] rd2,\\\\n input wire[31:0] sext, \\\\n input wire[2:0] sel,\\\\n //\\\\u8f93\\\\u51fa\\\\u4fe1\\\\u53f7\\\\n output reg f,\\\\n output reg[31:0] C\\\\n);\\\\n\\\\n reg[31:0] ...
["module alt_fmon8 #(\\\\n parameter SIM_HURRY = 1'b0,\\\\n parameter SIM_EMULATE = 1'b0\\\\n) (\\\\n\\\\tinput clk, \\\\n\\\\tinput [7:0] din,\\\\n\\\\tinput [2:0] din_sel,\\\\n\\\\toutput [15:0] dout,\\\\n\\\\toutput dout_fresh\\\\n);\\\\n\\\\n////////////////////////////\\\\n// divide down and cross domain\\\\...
['module top_BRAM(\\\\n input clk,\\\\n output reg [3:0] Max = 0\\\\n );\\\\n \\\\n wire [3:0] dout;\\\\n reg [3:0] addr_reg = 0, addr_next;\\\\n \\\\n always @(posedge clk)\\\\n begin\\\\n addr_reg <= addr_next;\\\\n end\\\\n \\\\n always @(*)\\\\n begi...
["module Control (\\\\n NoOp_i,\\\\n Op_i,\\\\n RegWrite_o,\\\\n MemtoReg_o,\\\\n MemRead_o,\\\\n MemWrite_o,\\\\n ALUOp_o,\\\\n ALUSrc_o,\\\\n Branch_o\\\\n);\\\\n\\\\ninput NoOp_i;\\\\ninput [6:0] Op_i;\\\\n\\\\noutput reg RegWrite_o;\\\\noutput reg MemtoReg_...
['module receiver(\\\\n input clk,\\\\n input start,\\\\n input rx,\\\\n output ready,\\\\n output[3:0] outputData\\\\n );\\\\n parameter END_OF_COUNTER = 10;\\\\n\\\\n reg state;\\\\n reg [8:0] data;\\\\n reg [7:0] counter;\\\\n reg [3:0] i;\\\\n\\\\n reg crcStart;\\\\n\\\\n alwa...
["module control ( opcode, I, isst, isld, isbeq, isbgt,isret,isimmediate, iswb,isubranch,iscall,alusignal );\\\\n\\\\noutput isst,isld,isbeq,isret,isimmediate,iswb,isubranch,iscall,isbgt;\\\\ninput [4:0] opcode; \\\\ninput I;\\\\noutput [4:0] alusignal;\\\\n \\\\nreg isst,isld,isbeq,isre...
["module Car_Bitmap\\\\n (input [3:0] i_Yofs,\\\\n output reg [7:0] o_Bits);\\\\n\\\\n always @ (*)\\\\n case (i_Yofs)\\\\n 0: o_Bits = 8'b0;\\\\n 1: o_Bits = 8'b1100;\\\\n 2: o_Bits = 8'b11001100;\\\\n 3: o_Bits = 8'b11111100;\\\\n 4: o_Bits = 8'b11101100;\\\\n 5: o_Bit...
["module BEext(opcode,aluout,be);\\\\n input [31:26] opcode ;//opcode \\\\n input [1:0] aluout ;//aluout last 2-bit\\\\n output [3:0] be ;//\\\\n\\\\n reg [3:0] be ;\\\\n \\\\n always @(*)\\\\n begin\\\\n if (opcode == `O_sw \| opcode == `O_lw)\\\\n be <= 4'b1111 ;\\\\...
["module carriergen (\\\\n input clk,\\\\n input rst,\\\\n input[9:0] addr_change,\\\\n output [7:0] carrier\\\\n);\\\\n parameter freq_car = 10'd40;\\\\n//-----------------------\\\\n\\\\twire[7:0]carrier_reg;\\\\n reg[9:0] cnt;\\\\n wire [7:0] addr_car ;\\\\n ...
["module top(\\\\n input clk,\\\\n input PS2Data,\\\\n input PS2Clk,\\\\n input btnC,\\\\n output [6:0] seg,\\\\n output [3:0] an,\\\\n output [3:0] vgaRed,\\\\n output [3:0] vgaGreen,\\\\n output [3:0] vgaBlue,\\\\n output Hsync,\\\\n output Vsync\\\\n);\\\\n ...
["module fan_btn(\\\\n input wire clk, reset_p,\\\\n input wire btn,\\\\n output wire [3:0] led,\\\\n output wire [6:0] duty\\\\n );\\\\n\\\\n parameter S_PWM0 = 5'b00001;\\\\n parameter S_PWM25 = 5'b00010;\\\\n parameter S_PWM50 = 5'b00100;\\\\n parameter S_PWM75 = 5'b01000;\\\\n paramete...
['module for Sequence detection: 1011\\\\nmodule seq_detect_1011(seq_seen, inp_bit, reset, clk);\\\\n\\\\n output seq_seen;\\\\n input inp_bit;\\\\n input reset;\\\\n input clk;\\\\n\\\\n parameter IDLE = 0,\\\\n SEQ_1 = 1, \\\\n SEQ_10 = 2,\\\\n SEQ_101 = 3,\\\\n SEQ_10...
["module FSM_CONTROLLER(\\\\n input reset, \\\\n input clk,\\\\n input player1,\\\\n input player2,\\\\n input illegal_move,\\\\n input no_space, \\\\n input winner,\\\\n output reg player1_turn,\\\\n output reg player2_turn\\\\n ); \\\\n\\\\n reg [1:0] curr_state;\\\\n reg [1:...
["module abc_alfabeta(\\\\n input sa,\\\\n input sb,\\\\n input sc,\\\\n input [58:0] vdc13,\\\\n input [58:0] vdcs3,\\\\n output [58:0] alfa,\\\\n output [58:0] beta\\\\n );\\\\n\\\\n wire [2:0] s; \\\\n assign s = {sa,sb,sc};\\\\n \\\\n reg [58:0] out1;\\\\n reg [58:0] out2...
["module CLK_1_MODULE (\\\\n clk,\\\\n rst_n,\\\\n in_valid,\\\\n seed_in,\\\\n out_idle,\\\\n out_valid,\\\\n seed_out,\\\\n\\\\n clk1_handshake_flag1,\\\\n clk1_handshake_flag2,\\\\n clk1_handshake_flag3,\\\\n clk1_handshake_flag4\\\\n);\\\\n\\\\ninput clk;\\\\ninput rst_n;\\\\ninput ...
['module WB(\\\\n input [`WORD-1:0] PC,\\\\n input [`WORD-1:0] inst,\\\\n input [7:0] CTRL_EX,\\\\n input [`REG_LOG*3-1:0] rs,\\\\n input [`WORD-1:0] CAL_res,\\\\n input [`WORD-1:0] data,\\\\n output REG_write_WB,\\\\n output [`REG_LOG-1:0] rd,\\\\n output [`WORD-1:0] WB_data\\\\n );\\\\n ...
["module UART(\\\\n input wire clk,\\\\n input wire tx_en,\\\\n input wire rx_en,\\\\n input wire begin_flag,\\\\n input wire rx,\\\\n input wire [7:0] tx_data,\\\\n input wire [7:0] access_addr,\\\\n input wire reg_w_en,\\\\n output wire tx,\\\\n output wire[7:0] rx_data,\\\\n output w...
["module data_ram(\\\\n input wire clk,\\\\n input wire ce,\\\\n input wire we,\\\\n input wire[`DataAddrBus] addr,\\\\n input wire[3:0] sel,\\\\n input wire[`DataBus] data_i,\\\\n output reg[`DataBus] data_o\\\\n);\\\\n\\\\n reg[`ByteWidth] data_mem0[0:`DataMemNum-1];\\\\n reg[`ByteWidth] da...
["module top_module(\\\\n input clk,\\\\n input areset, // Freshly brainwashed Lemmings walk left.\\\\n input bump_left,\\\\n input bump_right,\\\\n input ground,\\\\n input dig,\\\\n output walk_left,\\\\n output walk_right,\\\\n output aaah,\\\\n output digging );\\\\n \\\\n loc...
["module W_control7(\\\\n input wire clk,\\\\n output reg signed [`WBus] W_real,\\\\n output reg signed [`WBus] W_imag\\\\n );\\\\n \\\\n\\\\n/*************define wire and reg****************/\\\\n reg [`WCountBus] count = 9'b0;\\\\n \\\\n \\\\n /*******counter**...
["module signal_case(\\\\n input [4:0] curpos,\\\\n input [10:0] h_cnt,\\\\n input [10:0] v_cnt,\\\\n input clk,\\\\n input [3:0] curdata,\\\\n output reg [11:0] signal \\\\n); \\\\n parameter zero = 4'b0000;\\\\n parameter one = 4'b0001;\\\\n parameter two = 4'b0010;\\\\n parameter thre...
["module operator_12 (\\\\n input clk,\\\\n input rst,\\\\n input [1:0] level,\\\\n output reg out\\\\n );\\\\n \\\\n \\\\n \\\\n wire [4-1:0] M_led_strip_pixel;\\\\n wire [1-1:0] M_led_strip_led;\\\\n reg [1-1:0] M_led_strip_update;\\\\n reg [24-1:0] M_led_strip_color;\\\\n ws2812b_writer_27 led_s...
["module can_fifo_new\\\\n( \\\\n clk,\\\\n rst,\\\\n\\\\n wr,\\\\n\\\\n data_in,\\\\n addr,\\\\n data_out,\\\\n fifo_selected,\\\\n\\\\n reset_mode,\\\\n release_buffer,\\\\n extended_mode,\\\\n overrun,\\\\n info_empty,\\\\n info_cnt,\\\\n data_out_valid\\\\n\\\\n);\\\\n\\\\ninput clk;\\\\ninput...
["module keypad_decoder(\\\\n input clk,\\\\n input [3:0] row, // 4 buttons per row, Pmod JA pins 10 to 7\\\\n output reg [3:0] col, // 4 buttons per col, Pmod JA pins 4 to 1\\\\n output reg [3:0] dec_out // binary value of button press\\\\n );\\\\n\\\\n ...
["module debounce44(\\\\n input wire clk, nrst,\\\\n input wire [N-1:0] key_in,\\\\n output reg [N-1:0] key_out\\\\n );\\\\n\\\\n// localparam TIME_20MS = 1_000_000;\\\\n localparam TIME_20MS = 1_000; // just for test\\\\n parameter N = 1; //\\\\u8981\\\\u6d88\\\\u9664\\\\u7684\\\\u6309\\\\u9...
['module sigma_delta_dac(\\\\n output reg DACout, //Average Output feeding analog lowpass\\\\n input [MSBI:0] DACin, //DAC input (excess 2**MSBI)\\\\n input CLK,\\\\n input CEN,\\\\n input RESET\\\\n);\\\\n\\\\nparameter MSBI =...
["module keypad_unit (\\\\n input wire clk, rst_n,\\\\n \\\\n input wire [3:0] row_in,\\\\n output reg [3:0] col_out,\\\\n \\\\n output reg [7:0] key_coord\\\\n );\\\\n \\\\n localparam SCAN_COL_1 = 2'b00,\\\\n SCAN_COL_2 = 2'b01,\\\\n SCAN_COL_3 = 2'b1...
['module ALU(\\\\n input [`DMEM_DATA_WIDTH - 1:0] a,\\\\n input [`DMEM_DATA_WIDTH - 1:0] b,\\\\n output reg [`DMEM_DATA_WIDTH - 1:0] z,\\\\n input [2:0] func,\\\\n input enable\\\\n);\\\\n always @(*) begin\\\\n if (enable) begin\\\\n case (func)\\\\n `ALU_FUNC_ADD: z ...
["module kb_monitor_test(\\\\n\\\\n );\\\\n \\\\n \\\\n parameter T = 2, //clk period\\\\n T_PS2 = 50; //ps2c period\\\\n \\\\n parameter DBIT = 8, //bits of data in word\\\\n SB_TICK = 16, //ticks for stop bit. 16 = 1 bit, 24 for 1.5 bits, 32 for 2 bits\\\\n...
["module task5(\\\\n input CLK,\\\\n input rst_n,\\\\n output reg[3:0] ssd_ctl,\\\\n output reg[7:0] seg\\\\n );\\\\n wire CLK_temp;\\\\n reg [4:0]part10,part9,part8,part7,part6,part5,part4,part3,part2,part1,seg_number;\\\\n reg [17:0] counter;\\\\n reg [17:0] counter_next;\\\\n reg [2:0] ...
['module m_wishbonereg\\\\n (\\\\n input [31:0] DAT_I,\\\\n input STB_I,\\\\n input WE_I,\\\\n input [3:0] SEL_I,\\\\n input CLK_I,\\\\n output [31:0] DAT_O,\\\\n output ACK_O\\\\n );\\\\n\\\\n wire [3:0] ce;\\\\n reg [31:0] r;\\\\n\\\\n assign ce[0] = SEL_...
["module Block_Gen #\\\\n(\\\\n parameter BLOCK_SIZE = 32,\\\\n parameter BLOCK_WIDTH = 32\\\\n)\\\\n(\\\\n input CLK,\\\\n input RESET,\\\\n output DATA_OUT\\\\n);\\\\n\\\\nwire [BLOCK_SIZEBLOCK_WIDTH - 1:0] RANDOM_GEN_DATA_OUT;\\\\ngenvar i;\\\\ngenerate\\\\n for (i = 0; i < BLOCK_SIZEBLOCK_WID...
["module serial_tx #(\\\\n parameter CLK_FREQ = 48_000_000, // clock frequency (Hz)\\\\n parameter BAUD_RATE = 115_200 // baud rate (bits per second)\\\\n) (\\\\n input i_clk, // system clock\\\\n input i_wr, // write-request strobe\\\\n input [...
['module lfsr (\\\\n input wire clk, //! input clock\\\\n input wire rst_n, //! active-low asynchronous reset\\\\n input wire enable, //! active-high enable\\\\n input wire [WIDTH-1:0] taps, //! feedback tap array\\\\n output wire [WIDTH-1:0] seq //! outp...
["module Bullet_Judge (\\\\n input clk,rst,\\\\n input clk2,\\\\n input [9:0] p_x,p_y,\\\\n input [9:0] startp_x,startp_y,\\\\n input [9:0] x,y,\\\\n input collide, //0 for my bullet collide, 1 for my bullet exist\\\\n output reg [9:0] b_x,b_y,\\\\n output mybullet_en, //1 for my bullet can sh...
['module moore_1101 (\\\\n input clk,\\\\n input clr,\\\\n input din,\\\\n output reg dout\\\\n);\\\\n parameter S0=0, S1=1, S2=2, S3=3, S4=4;\\\\n reg[4:0] state;\\\\n reg[4:0] nstate;\\\\n \\\\n always@(posedge clk or posedge clr) begin\\\\n if(clr)\\\\n state <= S0;\\\\n...
["module SimpleCPU(\\\\n input clk,\\\\n input reset,\\\\n input [7:0] instruction,\\\\n output reg [7:0] acc\\\\n);\\\\n parameter FETCH = 2'b00, DECODE = 2'b01, EXECUTE = 2'b10;\\\\n reg [1:0] state;\\\\n reg [7:0] opcode, operand;\\\\n wire [7:0] alu_out;\\\\n wire alu_cout;\\\\n reg [3...
["module top_module(\\\\n input clk,\\\\n input load,\\\\n input [255:0] data,\\\\n output [255:0] q ); \\\\n \\\\n reg [17:0][17:0] array; // SystemVerilog syntax\\\\n \\\\n always @(*) begin\\\\n integer i, j;\\\\n // Copy 1D vector to 2D vector\\\\n for(i=1;i<=16;i=i+1) b...
['module top(p1h, p1l, p2h, p2l, p3h, p3l);\\\\n\\\\n (* LOC=\\\\"P3\\\\" ) output p1h;\\\\n ( LOC=\\\\"P4\\\\" ) output p1l;\\\\n ( LOC=\\\\"P5\\\\" ) output p2h;\\\\n ( LOC=\\\\"P6\\\\" ) output p2l;\\\\n ( LOC=\\\\"P7\\\\" ) output p3h;\\\\n ( LOC=\\\\"P8\\\\" *) output p3l;\\\\n\\\\n ...
["module multiplier #(parameter DATA_WIDTH=16, parameter FRAC_BIT = 8, parameter KERNEL_SIZE=5) (\\\\n // Inputs\\\\n input signed [(KERNEL_SIZE*2)DATA_WIDTH - 1:0] weights,\\\\n input signed [(KERNEL_SIZE*2)DATA_WIDTH - 1:0] pixel_data,\\\\n \\\\n // Output\\\\n output signed [(KERNEL_SIZE*2)DA...
['module d_mem(\\\\n input wire clk,\\\\n input wire rst,\\\\n input wire write,\\\\n input wire [`ADDR_BUS] addr,\\\\n input wire [`DATA_BUS] data_i,\\\\n \\\\n output reg [`DATA_BUS] data_o,\\\\n output reg error\\\\n );\\\\n \\\\n reg [`BYTE0]mem[0:`MEM_SIZE];\\\\n \\\\n initia...
["module parallel_pe(\\\\n input clk,\\\\n input rst_n,\\\\n input [511:0] neuron,\\\\n input [511:0] weight,\\\\n input [ 1:0] ctl,\\\\n input vld_i,\\\\n output [ 31:0] result,\\\\n output reg vld_o\\\\n...
["module regfile(\\\\n input wire clk,\\\\n input wire rst,\\\\n input wire [4:0] raddr1,\\\\n output wire [31:0] rdata1,\\\\n input wire [4:0] raddr2,\\\\n output wire [31:0] rdata2,\\\\n \\\\n input wire we,\\\\n input wire [4:0] waddr,\\\\n input wire [31:0] wdata,\\\\n\\\\n input wi...
["module Val2_Generator(\\\\n input imm,\\\\n input MEM_write_or_read_en,\\\\n input [11:0] shift_operand,\\\\n input [31:0] rm,\\\\n \\\\n output reg [31:0] val_2\\\\n);\\\\n \\\\n integer i;\\\\n \\\\n always @(*) begin\\\\n if (MEM_write_or_read_en) begin\\\\n val_...
["module id_stall(\\\\n input clk,\\\\n input rst,\\\\n input [5:0] op, \\\\n input [5:0] func,\\\\n input [4:0] rs,\\\\n input [4:0] rt,\\\\n input rf_rena1,\\\\n input rf_rena2,\\\\n\\\\n // Data from EXE \\\\n\\\\tinput [4:0] exe_rf_waddr, \\\\n input exe_rf_wena,\\\\n\\\\n\\\\t// Da...
["module traffic_light(\\\\n input wire clk,\\\\n input wire reset,\\\\n output reg [2:0] light_A,\\\\n output reg [2:0] light_B\\\\n);\\\\n \\\\n parameter FIRST_STATE = 3'b000;\\\\n parameter SECOND_STATE = 3'b001;\\\\n parameter THIRD_STATE = 3'b010;\\\\n parameter FOURTH_STATE = 3'b011;\\\\n ...
["module Draw_Symbol #\\\\n ( \\\\n parameter horizontal_start_limit = 1,\\\\n parameter vertical_start_limit = 1,\\\\n parameter color = 4,\\\\n parameter offset = 1, \\\\n parameter isactive = 1,\\\\n parameter number_of_fsm = 16\\\\n \\\\n )\\\\n \\\\n ...
['module char_walk(input clk, btnD, btnR, clr, [2:0] cd_cnt,\\\\n output reg win = 0, reg [6:0] x = 2, reg [5:0] y = 13);\\\\n reg [2:0] state = 0;\\\\n always @ (*) begin\\\\n state[0] = (x == 23 && y < 29) \| (x == 47 && y < 45) \| (x == 71 && y < 61);\\\\n state[1] = (y >= 31 && ...
["module gerador_jogadas_inicial(\\\\n input clock,\\\\n input reset,\\\\n input novaJogada,\\\\n output reg [2:0] coluna1,\\\\n output reg [2:0] linha1,\\\\n output reg [2:0] coluna2,\\\\n output reg [2:0] linha2,\\\\n output reg [2:0] coluna3,\\\\n output reg [2:0] linha3\\\\n);\\\\n\\\\...
["module ancho(\\\\n input clock,\\\\n input [2:0] speed,\\\\n input enable, \\\\n output PWM\\\\n );\\\\n reg [4:0] counter;\\\\n reg [4:0] width;\\\\n reg temp_PWM;\\\\n\\\\n always @ (posedge clock or posedge enable) begin\\\\n if (enable) begin\\\\n counter <= 0;...
['module ALU(\\\\n alu_op, // input\\\\n alu_in_1, // input \\\\n alu_in_2, // input\\\\n alu_result, // output\\\\n alu_bcond // output\\\\n );\\\\n \\\\n input [4:0]alu_op;\\\\n\\\\tinput [31:0] alu_in_1;\\\\n\\\\tinput [31:0] alu_in_2;\\\\n\\\\toutput reg [31:0] alu_result;\\...
['module top_module(\\\\n input clk,\\\\n input load,\\\\n input [255:0] data,\\\\n output [255:0] q ); \\\\n\\\\n reg [0:15] mat [0:15];\\\\n reg [0:15] sol [0:15];\\\\n reg [255:0] sol1;\\\\n \\\\n genvar i, j, k, l;\\\\n integer count [0:15] [0:15];\\\\n//-------------------------------...
["module basic_display(\\\\n input enable, clk, reset_display_button, \\\\n input [10:0] sw,\\\\n input [12:0] pixel_index,\\\\n output reg [15:0] colour_chooser\\\\n );\\\\n \\\\n wire frame_begin;\\\\n wire sending_pixels;\\\\n wire sample_pixel;\\\\n wire [7:0]x;\\\\n wire [6:0]y;\\\...
['module mytop (\\\\n\\\\tinput clock,\\\\n\\\\tinput ddr_in,\\\\n\\\\toutput ddr_out\\\\n);\\\\n reg [1:0] in_buffer;\\\\n reg [1:0] out_buffer;\\\\n initial begin\\\\n in_buffer = 0;\\\\n out_buffer = 0;\\\\n end\\\\n // Differential input, DDR data\\\\n defparam differential_input.PIN...
["module ripple_carry_adder (\\\\n clk ,\\\\n rst_n ,\\\\n a_in ,\\\\n b_in ,\\\\n carry_in ,\\\\n sum_out ,\\\\n carry_out\\\\n);\\\\n\\\\n input clk ;\\\\n input rst_n ;\\\\n input [15:0] a_in ;\\\\n input [15:0] b_in ;\\\\n input ...
['module Tcontrol(T,opcode,carry,SR,newT);\\\\n input [6:0] T;\\\\n input [7:0] opcode;\\\\n input carry;\\\\n input [7:0] SR;\\\\n output reg [6:0] newT = `emptyT;\\\\n\\\\n always @ (*) begin\\\\n newT = `emptyT;\\\\n if (opcode==`BRK) begin\\\\n case (T)\\\\n `Tz...
['module tb_main_control;\\\\n\\\\n reg i_bus_a_not_equal_bus_b;\\\\n reg i_instruction_is_nop;\\\\n reg [5 : 0] i_op;\\\\n reg [5 : 0] i_funct;\\\\n wire [19 : 0] o_ctrl_regs;\\\\n\\\\n main_control dut \\\\n (\\\\n .i_bus_a_not_equal_bus_b (i_bus_a_not_equal_bus_b),...
['module top_module(\\\\n input clk,\\\\n input reset,\\\\n input ena,\\\\n output pm,\\\\n output [7:0] hh,\\\\n output [7:0] mm,\\\\n output [7:0] ss); \\\\n\\\\n // Counters for hours, minutes, and seconds\\\\n always @(posedge clk) begin\\\\n if (reset) begin\\\\n hh <= ...
["module SINCOS\\\\n (\\\\n input clk_100M,\\\\n input rst_n,\\\\n\\\\t\\\\t\\\\t \\\\n input [23:0]fre,//1~16_777_215Hz\\\\n\\\\n output[15:0]SIN_sig,\\\\n output[15:0]COS_sig\\\\n );\\\\n\\\\nwire [47:0]temp = fre * 24'd11258999;\\\\nwire [31:0]K_12_20 = ...
["module ippcsge_carr_sense\\\\n (clk,//@txclk\\\\n rst_,\\\\n rep_mode,\\\\n transmitting,\\\\n receiving,\\\\n crs\\\\n );\\\\n\\\\n////////////////////////////////////////////////////////////////////////////////\\\\n// Port declarations\\\\ninput clk, rst_, rep_mode, transmitting, receiv...

["module alu_control(\\\\n input wire [`ALU_OP_WIDTH-1 : 0] alu_op, \\\\n input wire [2 : 0] funct3,\\\\n input wire funct7_30, // SUB and SRA \\\\n input wire funct7_25, // RV32M extension \\\\n output reg [`AL...

["module ALU_control(\\\\n input [1:0] ALUop,\\\\n input [2:0] funct3,\\\\n input funct7,\\\\n input [4:0]opcode,\\\\n output reg [3:0] ALUsel\\\\n );\\\\n\\\\n always @(*)begin\\\\n case(ALUop)\\\\n 2'b00: ALUsel = `ALU_ADD; \\\\n 2'b01: ALUsel = `ALU_SUB;\\\\n 2'b11...

["module sum(\\\\n input clk, rst_n,\\\\n input a_valid, b_valid, c_valid, d_valid,\\\\n input [8:0] a_data_in, b_data_in, c_data_in, d_data_in,\\\\n \\\\n output reg [8:0] data_out,\\\\n output reg out_valid,\\\\n output reg [2:0] output_counter\\\\n );\\\\n \\\\n reg [10:0] input_reg [5:...

["module shift_reg (\\\\n input wire clk,\\\\n input wire clr,\\\\n input wire load, shift,\\\\n input wire [7:0] Data,\\\\n output reg tx_data\\\\n);\\\\n\\\\n reg [7:0] shr; // Register to hold the data bits\\\\n\\\\n // Output assignment\\\\n assign tx_data = shr[0]; // Output the LSB of the...

['module sine_stepper // #(.data_size(xx)) \\\\n(\\\\n input clock,\\\\n input [1:0]frequency, //200, 400, 800, 1600\\\\n output wire [5:0]step,\\\\n output wire [15:0]wave\\\\n);\\\\nparameter two_hundred = 0;\\\\nparameter four_hundred = 1;\\\\nparameter eight_hundred = 2;\\\\nparameter one_six_hundred =...

["module rand_gen(\\\\n input wire clk100,\\\\n input wire rst, \\\\n output reg [10:0] orbit_sin_addr, //rand number for sin ROM addr, [10:]\\\\n output reg [9:0] orbit_log_addr //rand number for log ROM addr, [9:0]\\\\n );\\\\n\\\\nwire [10:0] orbit_1;\\\\nwire [10:0] ...

["module test(\\\\n input clkp,\\\\n input clkn,\\\\n output led\\\\n);\\\\n wire clk;\\\\n\\\\n assign led = ~led_show;\\\\n\\\\n reg led_show;\\\\n\\\\n localparam CNT = 32'd200_000_000;\\\\n reg [31:0] num_cnt;\\\\n reg [7:0] state, next_state;\\\\n localparam ID00 = 8'h00, IW00 = 8'h01...

['module registro #(parameter WIDTH = 4)\\\\n(\\\\noutput reg [WIDTH-1 : 0] Q,\\\\noutput reg S_OUT,\\\\n\\\\ninput wire [WIDTH-1 : 0] D,\\\\ninput wire [1 : 0] MODO,\\\\ninput wire CLK, ENB, DIR, S_IN, ITER\\\\n);\\\\n\\\\nalways @ (posedge CLK) begin\\\\n if (~ENB) be...

["module mul_3_stage(\\\\n input [63:0] input_mul, //inputa[63:32] inputb[31:0]\\\\n input input_mul_stb, \\\\n output reg s_input_mul_ack, \\\\n input clk,\\\\n input rst,\\\\n output reg [31:0] z,\\\\n output reg s_output_z_stb, //output z valid\\...

["module simple_spi(CLOCK_50, GPIO_0, KEY, LEDR);\\\\n\\\\ninput MAX10_CLK1_50;\\\\ninput [35:0] GPIO;\\\\ninput [1:0] KEY;\\\\noutput [9:0] LEDR;\\\\n\\\\nwire sys_clk = MAX10_CLK1_50;\\\\nwire sys_rst_n = KEY[1];\\\\n\\\\nwire spi_sck = GPIO[0];\\\\nwire spi_cs = GPIO[1]...

["module volume_bar(input clk, [1:0] border, [1:0] bar, [6:0] bar_pos,\\\\n [6:0] pixel_x, [5:0] pixel_y, [3:0] vol,\\\\n output reg [15:0] pixel_data);\\\\n always @(posedge clk) begin\\\\n //border\\\\n if (pixel_x < 1 || pixel_x > 94 || pixel_y < 1 || pixel_y > ...

['module queue_2bit (clk, rst, rst_front, dequeue, ld, ld_data, rear_index_in, data_out, finish);\\\\n input clk, rst, rst_front, dequeue, ld;\\\\n input [8:0] rear_index_in;\\\\n input [1:0] ld_data [0:256];\\\\n output reg[1:0] data_out;\\\\n output finish;\\\\n reg [1:0] queue_data[0:256];\\\\n ...

['module ALUControl (\\\\n input [5:0] Funct,\\\\n input [2:0] ALUCtrl,\\\\n output reg [3:0] ALUOp\\\\n );\\\\n\\\\n always @(*) begin\\\\n case (ALUCtrl)\\\\n `AluCtrl_R: begin\\\\n case (Funct)\\\\n `Funct_Add : ALUOp <= `AluOp_Add;\\\\n ...

["module AuxDivider(clk, rst_n, clk_out);\\\\n function integer Log2Ceil(input time cnt_max);\\\\n for (Log2Ceil = 0; cnt_max; Log2Ceil = Log2Ceil + 1)\\\\n cnt_max = cnt_max >> 1;\\\\n endfunction\\\\n parameter CntMax = `CNT_SEC(1);\\\\n parameter CntHalf = CntMax / 2;\\\\n localparam...

["module lsfr(clk, reset, enable, Y );\\\\n\\\\n input clk;\\\\n input reset;\\\\n input enable;\\\\n output [2:0] Y = 3'b001;\\\\n reg [2:0] Y, Y_next;\\\\n reg w1;\\\\n reg [2:0] w2;\\\\n \\\\n always @(posedge clk or negedge reset) begin\\\\n if (reset==1'b0) begin\\\\n Y...

["module top(\\\\n input wire clk_pix,\\\\n output wire [12:0] h,\\\\n output wire [12:0] v,\\\\n output wire [7:0] sdl_r,\\\\n output wire [7:0] sdl_g,\\\\n output wire [7:0] sdl_b,\\\\n output wire active\\\\n\\\\n);\\\\n\\\\n // Sync generator module\\\\n sync sync...

["module DataMemory(\\\\n input CLK,\\\\n input [31:0] address,\\\\n input [31:0] writeData,\\\\n input memWrite,\\\\n input memRead,\\\\n output [31:0] readData\\\\n );\\\\n \\\\n reg [7:0] memFile[0:31];\\\\n reg [31:0] readData;\\\\n \\\\n initial begin\\\\n memFile[0] = 8'...

['module line_shift(\\\\n input clk,\\\\n \\\\n input ycbcr_de,\\\\n input ycbcr_hs,\\\\n \\\\n input shiftin, \\\\n output taps0x, \\\\n output taps1x \\\\n);\\\\n\\\\nreg [2:0] clken_dly;\\\\nreg [9:0] ram_rd_addr;\\\\nreg [9:0] ram_rd_add...

["module instrMem(\\\\n input [31:0] A,\\\\n\\\\n output wire [31:0] RD\\\\n );\\\\n\\\\n reg [31:0] instr [256:0];\\\\n\\\\n initial\\\\n begin\\\\n // instr1\\\\n instr[0] <= {`lw, `gr0, `gr1, 16'h0003}; // lw gr1 <- address(32'b0+h0003)\\\\n instr[4] <= `nop;\\\\n...

["module divider(\\\\n input clk,\\\\n input rst,\\\\n input start, \\\\n input[31:0] dividend, \\\\n input[31:0] divisor, \\\\n output divide_zero, \\\\n output finish, \\\\n output[31:0] res, \\\\n output[31:0] rem \\\\n);\\\\n\\\\n reg status;\...

["module fir_core_core_fsm (\\\\n clk, rst, fsm_output\\\\n);\\\\n input clk;\\\\n input rst;\\\\n output [12:0] fsm_output;\\\\n reg [12:0] fsm_output;\\\\n\\\\n\\\\n // FSM State Type Declaration for fir_core_core_fsm_1\\\\n parameter\\\\n main_C_0 = 4'd0,\\\\n main_C_1 = 4'd1,\\\\n main_C_2 = 4'd2,\\...

["module AddressRegisterFile(Clock, I, OutCSel, OutDSel, FunSel, RegSel, OutC, OutD);\\\\n input wire Clock;\\\\n input wire [15:0] I;\\\\n input wire [1:0] OutCSel;\\\\n input wire [1:0] OutDSel;\\\\n input wire [2:0]FunSel;\\\\n input wire [2:0] RegSel;\\\\n output reg [15:0] OutC;\\\\n output...

["module sipo(\\\\n clk,\\\\n en,\\\\n data_in,\\\\n data_out\\\\n );\\\\n parameter [31:0]n = 1344;\\\\n parameter [31:0]m = 64;\\\\n input clk;\\\\n input en;\\\\n input [( m - 1 ):0] data_in;\\\\n output [( n - 1 ):0] data_out;\\\\n localparam regamount ...

["module top_module ( \\\\n input clk, \\\\n input [7:0] d, \\\\n input [1:0] sel, \\\\n output [7:0] q \\\\n);\\\\n wire clkWire1, clkWire2, clkWire3;\\\\n assign clkWire1 = clk;\\\\n assign clkWire2 = clkWire1;\\\\n assign clkWire3 = clkWire2;\\\\n // wire internalWire1, internalWire2, inte...

['module alu(\\\\n input [`RV_BIT_NUM-1:0] op1,\\\\n input [`RV_BIT_NUM-1:0] op2,\\\\n input [`RV_BIT_NUM-1:0] exe_adder,\\\\n input [`ALU_FUN_BIT_NUM-1:0] ctrl_alu_fun,\\\\n \\\\n output reg [`RV_BIT_NUM-1:0] exe_alu_out\\\\n );\\\\n \\\\n always@(*) begin\\\\n ...

["module top_module(\\\\n input clk,\\\\n input in,\\\\n input reset, // Synchronous reset\\\\n output [7:0] out_byte,\\\\n output done\\\\n); \\\\n // Use FSM from Fsm_serial\\\\n parameter idle=0,start=1,data=2,check=3,stop=4,error=5;\\\\n reg [2:0] state,nstate;\\\\n reg [3:0] cnt;\\\\n...

['module tmr_s1neuron #(parameter M=8, //# of input layer\\\\n parameter n=32,\\\\n parameter cl=8, //# of bits of fixed number \\\\n parameter intbits=12,\\\\n parameter fracbits=20)(\\\\n input [M*n-1:0] X,\\\\n input [M*(n+cl...

['module universalRegister (\\\\n input wire SerialIn,\\\\n input wire [n-1:0] D,\\\\n input wire [2:0] ctrl,\\\\n input wire clk,\\\\n input wire rst_n,\\\\n output wire SerialOut,\\\\n output reg [n-1:0] Q\\\\n);\\\\n\\\\n parameter n = 4;\\\\n\\\\n // Behavioral description\\\\n always ...

['module bfu_nopipe (\\\\n input clk,\\\\n input reset,\\\\n input [`Datawidth:0] xin,\\\\n input [`Datawidth:0] yin,\\\\n input [`Datawidth:0] wr,\\\\n input en,\\\\n\\\\n output [`Datawidth:0] xout,\\\\n output [`Datawidth:0] yout,\\\\n output valid\\\\n);\\\\n\\\\n reg [`Datawidth+2:0] ...

["module fifo#(parameter WIDTH=8,DEPTH=16)(\\\\n input rst_n,\\\\n input [WIDTH-1:0]d_in,\\\\n input wr_en, w_clk,\\\\n input rd_en, rd_clk, \\\\n\\\\n output reg [WIDTH-1:0]d_out,\\\\n output full, empty);\\\\n \\\\n reg [$clog2(DEPTH)-1:0] rd_ptr;\\\\n reg [$clog2(DEPTH)-1:0] wr_ptr;\\\\n \\\\n //memory\\\...

["module AddressSelector(input [6:0] opcode,\\\\n input [4:0] cs_plus_1,\\\\n input [1:0] AddrCtl,\\\\n input alu_bcond,\\\\n output [4:0] next_state);\\\\n localparam ZERO = 5'd0;\\\\n \\\\n wire [1:0] branch_not_taken = {...

["module ALU(\\\\n input wire [31:0] Operand1,\\\\n input wire [31:0] Operand2,\\\\n input wire [3:0] AluContrl,\\\\n output reg [31:0] AluOut\\\\n );\\\\n \\\\n //ALU no need to modify, copy from lab1\\\\n // initial begin\\\\n // AluOut = 32'b0;\\\\n // end\\\\n\\\\n always @(*) b...

["module ALU(\\\\n input [1:0] opcode,\\\\n input [15:0] in0,\\\\n input [15:0] in1,\\\\n output reg [15:0] out\\\\n\\\\t //output reg [3:0] operation\\\\n );\\\\n \\\\n parameter low = 0;\\\\n \\\\n //subtractor wires\\\\n wire bin, bout;\\\\n wire [15:0] difference;\\\\n \\\\n /...

["module find_MAX(\\\\n input wire clk,\\\\n input wire rst_n,\\\\n input wire start,\\\\n input wire valid,\\\\n input wire [7:0] Data_A,\\\\n input wire [7:0] Data_B,\\\\n input wire one_left,\\\\n input wire [2:0] instruction,\\\\n output reg [7:0] maximum,\\\\n output reg finish\\\\n);...

["module tree(\\\\n input wire clk_25MHz,\\\\n input wire clk_1KHz,\\\\n input wire clk_100Hz,\\\\n input wire clk_50Hz,\\\\n input wire clk_25Hz,\\\\n input wire [31: 0] rand,\\\\n input wire rst,\\\\n input wire stop,\\\\n output reg [9: 0]x,\\\\n output reg [8: 0]y,\\\\n output reg [...

["module datamem (\\\\n input [31:0] WD,\\\\n input [31:0] A,\\\\n input clk,WE,rst,\\\\n output reg [31:0] RD\\\\n);\\\\n reg [31:0] Data_Mem [0:31];\\\\ninitial begin\\\\n Data_Mem[0] <= 32'h0x00000005;\\\\n Data_Mem[1] <= 32'h0xFFFFFFFB; //32'hFFC4A303; 0x8CDEFAB7\\\\n Data_Mem[2] <=...

["module clock_top\\\\n(\\\\ninput clk_ref_p,\\\\ninput clk_ref_n,\\\\ninput pcie_clk_p,\\\\ninput pcie_clk_n,\\\\noutput clk_out,\\\\noutput ref_clk,\\\\noutput clk_div\\\\n\\\\n);\\\\n\\\\n reg [1:0] clk_divide = 2'b00;\\\\n wire clk_out;\\\\n\\\\n IBUFDS diff_clk_200 (\\\\n .I (clk_ref_p),\\\\n .IB...

["module fifo_tx(clk_fifo_tx, data_in, next_frame, data_out);\\\\n\\\\n input[7:0] data_in;\\\\n input clk_fifo_tx;\\\\n input next_frame;\\\\n //output fifo_tx_status;\\\\n output reg[7:0] data_out;\\\\n \\\\n reg[15:0] fifo_tx_mem[7:0];\\\\n reg[3:0] wr_pt = 4'b0000;\\\...

["module counter(key_rst_en,key_ps_en,clk,numcount4_out,rst_n,numcount3_out,numcount2_out,numcount1_out);\\\\n input key_rst_en,key_ps_en,clk,rst_n;\\\\n\\\\toutput numcount4_out,numcount3_out,numcount2_out,numcount1_out;\\\\n\\\\t\\\\n\\\\treg [3:0]stcur_counter,stnext_counter,a;\\\\n\\\\treg [3:0]nu...

["module ALU_Control (\\\\n funct_i,\\\\n ALUOp_i,\\\\n ALUCtrl_o\\\\n);\\\\n\\\\n// Ports\\\\ninput [9:0] funct_i;\\\\ninput [1:0] ALUOp_i;\\\\noutput [2:0] ALUCtrl_o;\\\\n\\\\nreg [2:0] reg_o;\\\\n\\\\n// Output signal\\\\nalways @(funct_i or ALUOp_i) begin\\\\n if (ALUOp_i == 2'b10) begin...

["module ALU(\\\\n input wire[31:0] A,\\\\n input wire[3:0] alu_op,\\\\n //\\\\u9009\\\\u62e9\\\\n input wire[31:0] rd2,\\\\n input wire[31:0] sext, \\\\n input wire[2:0] sel,\\\\n //\\\\u8f93\\\\u51fa\\\\u4fe1\\\\u53f7\\\\n output reg f,\\\\n output reg[31:0] C\\\\n);\\\\n\\\\n reg[31:0] ...

["module alt_fmon8 #(\\\\n parameter SIM_HURRY = 1'b0,\\\\n parameter SIM_EMULATE = 1'b0\\\\n) (\\\\n\\\\tinput clk, \\\\n\\\\tinput [7:0] din,\\\\n\\\\tinput [2:0] din_sel,\\\\n\\\\toutput [15:0] dout,\\\\n\\\\toutput dout_fresh\\\\n);\\\\n\\\\n////////////////////////////\\\\n// divide down and cross domain\\\\...

['module top_BRAM(\\\\n input clk,\\\\n output reg [3:0] Max = 0\\\\n );\\\\n \\\\n wire [3:0] dout;\\\\n reg [3:0] addr_reg = 0, addr_next;\\\\n \\\\n always @(posedge clk)\\\\n begin\\\\n addr_reg <= addr_next;\\\\n end\\\\n \\\\n always @(*)\\\\n begi...

["module Control (\\\\n NoOp_i,\\\\n Op_i,\\\\n RegWrite_o,\\\\n MemtoReg_o,\\\\n MemRead_o,\\\\n MemWrite_o,\\\\n ALUOp_o,\\\\n ALUSrc_o,\\\\n Branch_o\\\\n);\\\\n\\\\ninput NoOp_i;\\\\ninput [6:0] Op_i;\\\\n\\\\noutput reg RegWrite_o;\\\\noutput reg MemtoReg_...

['module receiver(\\\\n input clk,\\\\n input start,\\\\n input rx,\\\\n output ready,\\\\n output[3:0] outputData\\\\n );\\\\n parameter END_OF_COUNTER = 10;\\\\n\\\\n reg state;\\\\n reg [8:0] data;\\\\n reg [7:0] counter;\\\\n reg [3:0] i;\\\\n\\\\n reg crcStart;\\\\n\\\\n alwa...

["module control ( opcode, I, isst, isld, isbeq, isbgt,isret,isimmediate, iswb,isubranch,iscall,alusignal );\\\\n\\\\noutput isst,isld,isbeq,isret,isimmediate,iswb,isubranch,iscall,isbgt;\\\\ninput [4:0] opcode; \\\\ninput I;\\\\noutput [4:0] alusignal;\\\\n \\\\nreg isst,isld,isbeq,isre...

["module Car_Bitmap\\\\n (input [3:0] i_Yofs,\\\\n output reg [7:0] o_Bits);\\\\n\\\\n always @ (*)\\\\n case (i_Yofs)\\\\n 0: o_Bits = 8'b0;\\\\n 1: o_Bits = 8'b1100;\\\\n 2: o_Bits = 8'b11001100;\\\\n 3: o_Bits = 8'b11111100;\\\\n 4: o_Bits = 8'b11101100;\\\\n 5: o_Bit...

["module BEext(opcode,aluout,be);\\\\n input [31:26] opcode ;//opcode \\\\n input [1:0] aluout ;//aluout last 2-bit\\\\n output [3:0] be ;//\\\\n\\\\n reg [3:0] be ;\\\\n \\\\n always @(*)\\\\n begin\\\\n if (opcode == `O_sw | opcode == `O_lw)\\\\n be <= 4'b1111 ;\\\\...

["module carriergen (\\\\n input clk,\\\\n input rst,\\\\n input[9:0] addr_change,\\\\n output [7:0] carrier\\\\n);\\\\n parameter freq_car = 10'd40;\\\\n//-----------------------\\\\n\\\\twire[7:0]carrier_reg;\\\\n reg[9:0] cnt;\\\\n wire [7:0] addr_car ;\\\\n ...

["module top(\\\\n input clk,\\\\n input PS2Data,\\\\n input PS2Clk,\\\\n input btnC,\\\\n output [6:0] seg,\\\\n output [3:0] an,\\\\n output [3:0] vgaRed,\\\\n output [3:0] vgaGreen,\\\\n output [3:0] vgaBlue,\\\\n output Hsync,\\\\n output Vsync\\\\n);\\\\n ...

["module fan_btn(\\\\n input wire clk, reset_p,\\\\n input wire btn,\\\\n output wire [3:0] led,\\\\n output wire [6:0] duty\\\\n );\\\\n\\\\n parameter S_PWM0 = 5'b00001;\\\\n parameter S_PWM25 = 5'b00010;\\\\n parameter S_PWM50 = 5'b00100;\\\\n parameter S_PWM75 = 5'b01000;\\\\n paramete...

['module for Sequence detection: 1011\\\\nmodule seq_detect_1011(seq_seen, inp_bit, reset, clk);\\\\n\\\\n output seq_seen;\\\\n input inp_bit;\\\\n input reset;\\\\n input clk;\\\\n\\\\n parameter IDLE = 0,\\\\n SEQ_1 = 1, \\\\n SEQ_10 = 2,\\\\n SEQ_101 = 3,\\\\n SEQ_10...

["module FSM_CONTROLLER(\\\\n input reset, \\\\n input clk,\\\\n input player1,\\\\n input player2,\\\\n input illegal_move,\\\\n input no_space, \\\\n input winner,\\\\n output reg player1_turn,\\\\n output reg player2_turn\\\\n ); \\\\n\\\\n reg [1:0] curr_state;\\\\n reg [1:...

["module abc_alfabeta(\\\\n input sa,\\\\n input sb,\\\\n input sc,\\\\n input [58:0] vdc13,\\\\n input [58:0] vdcs3,\\\\n output [58:0] alfa,\\\\n output [58:0] beta\\\\n );\\\\n\\\\n wire [2:0] s; \\\\n assign s = {sa,sb,sc};\\\\n \\\\n reg [58:0] out1;\\\\n reg [58:0] out2...

["module CLK_1_MODULE (\\\\n clk,\\\\n rst_n,\\\\n in_valid,\\\\n seed_in,\\\\n out_idle,\\\\n out_valid,\\\\n seed_out,\\\\n\\\\n clk1_handshake_flag1,\\\\n clk1_handshake_flag2,\\\\n clk1_handshake_flag3,\\\\n clk1_handshake_flag4\\\\n);\\\\n\\\\ninput clk;\\\\ninput rst_n;\\\\ninput ...

['module WB(\\\\n input [`WORD-1:0] PC,\\\\n input [`WORD-1:0] inst,\\\\n input [7:0] CTRL_EX,\\\\n input [`REG_LOG*3-1:0] rs,\\\\n input [`WORD-1:0] CAL_res,\\\\n input [`WORD-1:0] data,\\\\n output REG_write_WB,\\\\n output [`REG_LOG-1:0] rd,\\\\n output [`WORD-1:0] WB_data\\\\n );\\\\n ...

["module UART(\\\\n input wire clk,\\\\n input wire tx_en,\\\\n input wire rx_en,\\\\n input wire begin_flag,\\\\n input wire rx,\\\\n input wire [7:0] tx_data,\\\\n input wire [7:0] access_addr,\\\\n input wire reg_w_en,\\\\n output wire tx,\\\\n output wire[7:0] rx_data,\\\\n output w...

["module data_ram(\\\\n input wire clk,\\\\n input wire ce,\\\\n input wire we,\\\\n input wire[`DataAddrBus] addr,\\\\n input wire[3:0] sel,\\\\n input wire[`DataBus] data_i,\\\\n output reg[`DataBus] data_o\\\\n);\\\\n\\\\n reg[`ByteWidth] data_mem0[0:`DataMemNum-1];\\\\n reg[`ByteWidth] da...

["module top_module(\\\\n input clk,\\\\n input areset, // Freshly brainwashed Lemmings walk left.\\\\n input bump_left,\\\\n input bump_right,\\\\n input ground,\\\\n input dig,\\\\n output walk_left,\\\\n output walk_right,\\\\n output aaah,\\\\n output digging );\\\\n \\\\n loc...

["module W_control7(\\\\n input wire clk,\\\\n output reg signed [`WBus] W_real,\\\\n output reg signed [`WBus] W_imag\\\\n );\\\\n \\\\n\\\\n/***************define wire and reg********************/\\\\n reg [`WCountBus] count = 9'b0;\\\\n \\\\n \\\\n /***********counter****...

["module signal_case(\\\\n input [4:0] curpos,\\\\n input [10:0] h_cnt,\\\\n input [10:0] v_cnt,\\\\n input clk,\\\\n input [3:0] curdata,\\\\n output reg [11:0] signal \\\\n); \\\\n parameter zero = 4'b0000;\\\\n parameter one = 4'b0001;\\\\n parameter two = 4'b0010;\\\\n parameter thre...

["module operator_12 (\\\\n input clk,\\\\n input rst,\\\\n input [1:0] level,\\\\n output reg out\\\\n );\\\\n \\\\n \\\\n \\\\n wire [4-1:0] M_led_strip_pixel;\\\\n wire [1-1:0] M_led_strip_led;\\\\n reg [1-1:0] M_led_strip_update;\\\\n reg [24-1:0] M_led_strip_color;\\\\n ws2812b_writer_27 led_s...

["module can_fifo_new\\\\n( \\\\n clk,\\\\n rst,\\\\n\\\\n wr,\\\\n\\\\n data_in,\\\\n addr,\\\\n data_out,\\\\n fifo_selected,\\\\n\\\\n reset_mode,\\\\n release_buffer,\\\\n extended_mode,\\\\n overrun,\\\\n info_empty,\\\\n info_cnt,\\\\n data_out_valid\\\\n\\\\n);\\\\n\\\\ninput clk;\\\\ninput...

["module keypad_decoder(\\\\n input clk,\\\\n input [3:0] row, // 4 buttons per row, Pmod JA pins 10 to 7\\\\n output reg [3:0] col, // 4 buttons per col, Pmod JA pins 4 to 1\\\\n output reg [3:0] dec_out // binary value of button press\\\\n );\\\\n\\\\n ...

["module debounce44(\\\\n input wire clk, nrst,\\\\n input wire [N-1:0] key_in,\\\\n output reg [N-1:0] key_out\\\\n );\\\\n\\\\n// localparam TIME_20MS = 1_000_000;\\\\n localparam TIME_20MS = 1_000; // just for test\\\\n parameter N = 1; //\\\\u8981\\\\u6d88\\\\u9664\\\\u7684\\\\u6309\\\\u9...

['module sigma_delta_dac(\\\\n output reg DACout, //Average Output feeding analog lowpass\\\\n input [MSBI:0] DACin, //DAC input (excess 2**MSBI)\\\\n input CLK,\\\\n input CEN,\\\\n input RESET\\\\n);\\\\n\\\\nparameter MSBI =...

["module keypad_unit (\\\\n input wire clk, rst_n,\\\\n \\\\n input wire [3:0] row_in,\\\\n output reg [3:0] col_out,\\\\n \\\\n output reg [7:0] key_coord\\\\n );\\\\n \\\\n localparam SCAN_COL_1 = 2'b00,\\\\n SCAN_COL_2 = 2'b01,\\\\n SCAN_COL_3 = 2'b1...

['module ALU(\\\\n input [`DMEM_DATA_WIDTH - 1:0] a,\\\\n input [`DMEM_DATA_WIDTH - 1:0] b,\\\\n output reg [`DMEM_DATA_WIDTH - 1:0] z,\\\\n input [2:0] func,\\\\n input enable\\\\n);\\\\n always @(*) begin\\\\n if (enable) begin\\\\n case (func)\\\\n `ALU_FUNC_ADD: z ...

["module kb_monitor_test(\\\\n\\\\n );\\\\n \\\\n \\\\n parameter T = 2, //clk period\\\\n T_PS2 = 50; //ps2c period\\\\n \\\\n parameter DBIT = 8, //bits of data in word\\\\n SB_TICK = 16, //ticks for stop bit. 16 = 1 bit, 24 for 1.5 bits, 32 for 2 bits\\\\n...

["module task5(\\\\n input CLK,\\\\n input rst_n,\\\\n output reg[3:0] ssd_ctl,\\\\n output reg[7:0] seg\\\\n );\\\\n wire CLK_temp;\\\\n reg [4:0]part10,part9,part8,part7,part6,part5,part4,part3,part2,part1,seg_number;\\\\n reg [17:0] counter;\\\\n reg [17:0] counter_next;\\\\n reg [2:0] ...

['module m_wishbonereg\\\\n (\\\\n input [31:0] DAT_I,\\\\n input STB_I,\\\\n input WE_I,\\\\n input [3:0] SEL_I,\\\\n input CLK_I,\\\\n output [31:0] DAT_O,\\\\n output ACK_O\\\\n );\\\\n\\\\n wire [3:0] ce;\\\\n reg [31:0] r;\\\\n\\\\n assign ce[0] = SEL_...

["module Block_Gen #\\\\n(\\\\n parameter BLOCK_SIZE = 32,\\\\n parameter BLOCK_WIDTH = 32\\\\n)\\\\n(\\\\n input CLK,\\\\n input RESET,\\\\n output DATA_OUT\\\\n);\\\\n\\\\nwire [BLOCK_SIZE*BLOCK_WIDTH - 1:0] RANDOM_GEN_DATA_OUT;\\\\ngenvar i;\\\\ngenerate\\\\n for (i = 0; i < BLOCK_SIZE*BLOCK_WID...

["module serial_tx #(\\\\n parameter CLK_FREQ = 48_000_000, // clock frequency (Hz)\\\\n parameter BAUD_RATE = 115_200 // baud rate (bits per second)\\\\n) (\\\\n input i_clk, // system clock\\\\n input i_wr, // write-request strobe\\\\n input [...

['module lfsr (\\\\n input wire clk, //! input clock\\\\n input wire rst_n, //! active-low asynchronous reset\\\\n input wire enable, //! active-high enable\\\\n input wire [WIDTH-1:0] taps, //! feedback tap array\\\\n output wire [WIDTH-1:0] seq //! outp...

["module Bullet_Judge (\\\\n input clk,rst,\\\\n input clk2,\\\\n input [9:0] p_x,p_y,\\\\n input [9:0] startp_x,startp_y,\\\\n input [9:0] x,y,\\\\n input collide, //0 for my bullet collide, 1 for my bullet exist\\\\n output reg [9:0] b_x,b_y,\\\\n output mybullet_en, //1 for my bullet can sh...

['module moore_1101 (\\\\n input clk,\\\\n input clr,\\\\n input din,\\\\n output reg dout\\\\n);\\\\n parameter S0=0, S1=1, S2=2, S3=3, S4=4;\\\\n reg[4:0] state;\\\\n reg[4:0] nstate;\\\\n \\\\n always@(posedge clk or posedge clr) begin\\\\n if(clr)\\\\n state <= S0;\\\\n...

["module SimpleCPU(\\\\n input clk,\\\\n input reset,\\\\n input [7:0] instruction,\\\\n output reg [7:0] acc\\\\n);\\\\n parameter FETCH = 2'b00, DECODE = 2'b01, EXECUTE = 2'b10;\\\\n reg [1:0] state;\\\\n reg [7:0] opcode, operand;\\\\n wire [7:0] alu_out;\\\\n wire alu_cout;\\\\n reg [3...

["module top_module(\\\\n input clk,\\\\n input load,\\\\n input [255:0] data,\\\\n output [255:0] q ); \\\\n \\\\n reg [17:0][17:0] array; // SystemVerilog syntax\\\\n \\\\n always @(*) begin\\\\n integer i, j;\\\\n // Copy 1D vector to 2D vector\\\\n for(i=1;i<=16;i=i+1) b...

['module top(p1h, p1l, p2h, p2l, p3h, p3l);\\\\n\\\\n (* LOC=\\\\"P3\\\\" *) output p1h;\\\\n (* LOC=\\\\"P4\\\\" *) output p1l;\\\\n (* LOC=\\\\"P5\\\\" *) output p2h;\\\\n (* LOC=\\\\"P6\\\\" *) output p2l;\\\\n (* LOC=\\\\"P7\\\\" *) output p3h;\\\\n (* LOC=\\\\"P8\\\\" *) output p3l;\\\\n\\\\n ...

["module multiplier #(parameter DATA_WIDTH=16, parameter FRAC_BIT = 8, parameter KERNEL_SIZE=5) (\\\\n // Inputs\\\\n input signed [(KERNEL_SIZE**2)*DATA_WIDTH - 1:0] weights,\\\\n input signed [(KERNEL_SIZE**2)*DATA_WIDTH - 1:0] pixel_data,\\\\n \\\\n // Output\\\\n output signed [(KERNEL_SIZE**2)*DA...

['module d_mem(\\\\n input wire clk,\\\\n input wire rst,\\\\n input wire write,\\\\n input wire [`ADDR_BUS] addr,\\\\n input wire [`DATA_BUS] data_i,\\\\n \\\\n output reg [`DATA_BUS] data_o,\\\\n output reg error\\\\n );\\\\n \\\\n reg [`BYTE0]mem[0:`MEM_SIZE];\\\\n \\\\n initia...

["module parallel_pe(\\\\n input clk,\\\\n input rst_n,\\\\n input [511:0] neuron,\\\\n input [511:0] weight,\\\\n input [ 1:0] ctl,\\\\n input vld_i,\\\\n output [ 31:0] result,\\\\n output reg vld_o\\\\n...

["module regfile(\\\\n input wire clk,\\\\n input wire rst,\\\\n input wire [4:0] raddr1,\\\\n output wire [31:0] rdata1,\\\\n input wire [4:0] raddr2,\\\\n output wire [31:0] rdata2,\\\\n \\\\n input wire we,\\\\n input wire [4:0] waddr,\\\\n input wire [31:0] wdata,\\\\n\\\\n input wi...

["module Val2_Generator(\\\\n input imm,\\\\n input MEM_write_or_read_en,\\\\n input [11:0] shift_operand,\\\\n input [31:0] rm,\\\\n \\\\n output reg [31:0] val_2\\\\n);\\\\n \\\\n integer i;\\\\n \\\\n always @(*) begin\\\\n if (MEM_write_or_read_en) begin\\\\n val_...

["module id_stall(\\\\n input clk,\\\\n input rst,\\\\n input [5:0] op, \\\\n input [5:0] func,\\\\n input [4:0] rs,\\\\n input [4:0] rt,\\\\n input rf_rena1,\\\\n input rf_rena2,\\\\n\\\\n // Data from EXE \\\\n\\\\tinput [4:0] exe_rf_waddr, \\\\n input exe_rf_wena,\\\\n\\\\n\\\\t// Da...

["module traffic_light(\\\\n input wire clk,\\\\n input wire reset,\\\\n output reg [2:0] light_A,\\\\n output reg [2:0] light_B\\\\n);\\\\n \\\\n parameter FIRST_STATE = 3'b000;\\\\n parameter SECOND_STATE = 3'b001;\\\\n parameter THIRD_STATE = 3'b010;\\\\n parameter FOURTH_STATE = 3'b011;\\\\n ...

["module Draw_Symbol #\\\\n ( \\\\n parameter horizontal_start_limit = 1,\\\\n parameter vertical_start_limit = 1,\\\\n parameter color = 4,\\\\n parameter offset = 1, \\\\n parameter isactive = 1,\\\\n parameter number_of_fsm = 16\\\\n \\\\n )\\\\n \\\\n ...

['module char_walk(input clk, btnD, btnR, clr, [2:0] cd_cnt,\\\\n output reg win = 0, reg [6:0] x = 2, reg [5:0] y = 13);\\\\n reg [2:0] state = 0;\\\\n always @ (*) begin\\\\n state[0] = (x == 23 && y < 29) | (x == 47 && y < 45) | (x == 71 && y < 61);\\\\n state[1] = (y >= 31 && ...

["module gerador_jogadas_inicial(\\\\n input clock,\\\\n input reset,\\\\n input novaJogada,\\\\n output reg [2:0] coluna1,\\\\n output reg [2:0] linha1,\\\\n output reg [2:0] coluna2,\\\\n output reg [2:0] linha2,\\\\n output reg [2:0] coluna3,\\\\n output reg [2:0] linha3\\\\n);\\\\n\\\\...

["module ancho(\\\\n input clock,\\\\n input [2:0] speed,\\\\n input enable, \\\\n output PWM\\\\n );\\\\n reg [4:0] counter;\\\\n reg [4:0] width;\\\\n reg temp_PWM;\\\\n\\\\n always @ (posedge clock or posedge enable) begin\\\\n if (enable) begin\\\\n counter <= 0;...

['module ALU(\\\\n alu_op, // input\\\\n alu_in_1, // input \\\\n alu_in_2, // input\\\\n alu_result, // output\\\\n alu_bcond // output\\\\n );\\\\n \\\\n input [4:0]alu_op;\\\\n\\\\tinput [31:0] alu_in_1;\\\\n\\\\tinput [31:0] alu_in_2;\\\\n\\\\toutput reg [31:0] alu_result;\\...

['module top_module(\\\\n input clk,\\\\n input load,\\\\n input [255:0] data,\\\\n output [255:0] q ); \\\\n\\\\n reg [0:15] mat [0:15];\\\\n reg [0:15] sol [0:15];\\\\n reg [255:0] sol1;\\\\n \\\\n genvar i, j, k, l;\\\\n integer count [0:15] [0:15];\\\\n//-------------------------------...

["module basic_display(\\\\n input enable, clk, reset_display_button, \\\\n input [10:0] sw,\\\\n input [12:0] pixel_index,\\\\n output reg [15:0] colour_chooser\\\\n );\\\\n \\\\n wire frame_begin;\\\\n wire sending_pixels;\\\\n wire sample_pixel;\\\\n wire [7:0]x;\\\\n wire [6:0]y;\\\...

['module mytop (\\\\n\\\\tinput clock,\\\\n\\\\tinput ddr_in,\\\\n\\\\toutput ddr_out\\\\n);\\\\n reg [1:0] in_buffer;\\\\n reg [1:0] out_buffer;\\\\n initial begin\\\\n in_buffer = 0;\\\\n out_buffer = 0;\\\\n end\\\\n // Differential input, DDR data\\\\n defparam differential_input.PIN...

["module ripple_carry_adder (\\\\n clk ,\\\\n rst_n ,\\\\n a_in ,\\\\n b_in ,\\\\n carry_in ,\\\\n sum_out ,\\\\n carry_out\\\\n);\\\\n\\\\n input clk ;\\\\n input rst_n ;\\\\n input [15:0] a_in ;\\\\n input [15:0] b_in ;\\\\n input ...

['module Tcontrol(T,opcode,carry,SR,newT);\\\\n input [6:0] T;\\\\n input [7:0] opcode;\\\\n input carry;\\\\n input [7:0] SR;\\\\n output reg [6:0] newT = `emptyT;\\\\n\\\\n always @ (*) begin\\\\n newT = `emptyT;\\\\n if (opcode==`BRK) begin\\\\n case (T)\\\\n `Tz...

['module tb_main_control;\\\\n\\\\n reg i_bus_a_not_equal_bus_b;\\\\n reg i_instruction_is_nop;\\\\n reg [5 : 0] i_op;\\\\n reg [5 : 0] i_funct;\\\\n wire [19 : 0] o_ctrl_regs;\\\\n\\\\n main_control dut \\\\n (\\\\n .i_bus_a_not_equal_bus_b (i_bus_a_not_equal_bus_b),...

['module top_module(\\\\n input clk,\\\\n input reset,\\\\n input ena,\\\\n output pm,\\\\n output [7:0] hh,\\\\n output [7:0] mm,\\\\n output [7:0] ss); \\\\n\\\\n // Counters for hours, minutes, and seconds\\\\n always @(posedge clk) begin\\\\n if (reset) begin\\\\n hh <= ...

["module SINCOS\\\\n (\\\\n input clk_100M,\\\\n input rst_n,\\\\n\\\\t\\\\t\\\\t \\\\n input [23:0]fre,//1~16_777_215Hz\\\\n\\\\n output[15:0]SIN_sig,\\\\n output[15:0]COS_sig\\\\n );\\\\n\\\\nwire [47:0]temp = fre * 24'd11258999;\\\\nwire [31:0]K_12_20 = ...

["module ippcsge_carr_sense\\\\n (clk,//@txclk\\\\n rst_,\\\\n rep_mode,\\\\n transmitting,\\\\n receiving,\\\\n crs\\\\n );\\\\n\\\\n////////////////////////////////////////////////////////////////////////////////\\\\n// Port declarations\\\\ninput clk, rst_, rep_mode, transmitting, receiv...