type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
functions | void qpnp_flash_led_delayed_reg_work(struct work_struct *work)
{
struct flash_node_data *flash_node = container_of(work,
struct flash_node_data, dwork.work);
int rc;
flash_node->boost_regulator = regulator_get(flash_node->cdev.dev,
"boost");
if (IS_ERR(flash_node->boost_regulator)) {
rc = PTR_ERR(fl... |
functions | int qpnp_flash_led_parse_each_led_dt(struct qpnp_flash_led *led,
struct flash_node_data *flash_node)
{
const char *temp_string;
struct device_node *node = flash_node->cdev.dev->of_node;
int rc = 0;
u32 val;
rc = of_property_read_string(node, "label", &temp_string);
if (!rc) {
if (strcmp(temp_string, "flas... |
functions | else if (rc < 0) {
dev_err(&led->spmi_dev->dev,
"Unable to read flash type\n");
return rc;
} |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev,
"Unable to read current settings\n");
return rc;
} |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev, "Unable to read clamp current\n");
return rc;
} |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev, "Unable to read led ID\n");
return rc;
} |
functions | else if (flash_node->id == FLASH_LED_1) {
flash_node->enable = FLASH_LED1_ENABLEMENT;
if (flash_node->type == TORCH)
flash_node->enable = FLASH_MODULE_ENABLE;
flash_node->current_addr =
FLASH_LED1_CURRENT(led->base);
flash_node->trigger = FLASH_LED1_TRIGGER;
} |
functions | int qpnp_flash_led_parse_common_dt(
struct qpnp_flash_led *led,
struct device_node *node)
{
int rc;
u32 val, temp_val;
const char *temp;
led->pdata->headroom = FLASH_LED_HEADROOM_DEFAULT_MV;
rc = of_property_read_u32(node, "qcom,headroom", &val);
if (!rc)
led->pdata->headroom = (u16)val;
else if (rc... |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev,
"Unable to read startup delay\n");
return rc;
} |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev,
"Unable to read clamp current\n");
return rc;
} |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev,
"Unable to read thermal derate threshold\n");
return rc;
} |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev,
"Unable to read ramp up steps\n");
return rc;
} |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev,
"Unable to read ramp down steps\n");
return rc;
} |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev,
"Unable to read VPH PWR droop threshold\n");
return rc;
} |
functions | else if (rc != -EINVAL) {
dev_err(&led->spmi_dev->dev,
"Unable to read VPH PWR droop debounce time\n");
return rc;
} |
functions | int qpnp_flash_led_probe(struct spmi_device *spmi)
{
struct qpnp_flash_led *led;
struct resource *flash_resource;
struct device_node *node, *temp;
int rc, i = 0, j, num_leds = 0;
u32 val;
node = spmi->dev.of_node;
if (node == NULL) {
dev_info(&spmi->dev, "No flash device defined\n");
return -ENODEV;
} |
functions | else if (rc < 0) {
dev_err(&led->spmi_dev->dev,
"Unable to read max current\n");
return rc;
} |
functions | int qpnp_flash_led_remove(struct spmi_device *spmi)
{
struct qpnp_flash_led *led = dev_get_drvdata(&spmi->dev);
int i, j;
for (i = led->num_leds - 1; i >= 0; i--) {
if (led->flash_node[i].boost_regulator)
regulator_put(led->flash_node[i].boost_regulator);
for (j = 0; j < ARRAY_SIZE(qpnp_flash_led_attrs); j+... |
functions | __init qpnp_flash_led_init(void)
{
return spmi_driver_register(&qpnp_flash_led_driver);
} |
functions | __exit qpnp_flash_led_exit(void)
{
spmi_driver_unregister(&qpnp_flash_led_driver);
} |
includes |
#include <arch/io.h> |
includes | #include <assert.h> |
includes | #include <console/console.h> |
includes | #include <delay.h> |
includes | #include <soc/addressmap.h> |
includes | #include <soc/clock.h> |
includes | #include <soc/grf.h> |
includes | #include <soc/soc.h> |
includes | #include <stdint.h> |
includes | #include <stdlib.h> |
includes | #include <string.h> |
defines |
#define PLL_DIVISORS(hz, _nr, _no) {\ |
defines | #define PLL_OD_MSK (0x0F) |
defines |
#define PLL_NR_MSK (0x3F << 8) |
defines | #define PLL_NR_SHIFT (8) |
defines | #define PLL_NF_MSK (0x1FFF) |
defines | #define PLL_BWADJ_MSK (0x0FFF) |
defines | #define PLL_RESET_MSK (1 << 5) |
defines | #define PLL_RESET (1 << 5) |
defines | #define PLL_RESET_RESUME (0 << 5) |
defines | #define CORE_SEL_PLL_MSK (1 << 15) |
defines | #define CORE_SEL_APLL (0 << 15) |
defines | #define CORE_SEL_GPLL (1 << 15) |
defines | #define A12_DIV_SHIFT (8) |
defines | #define A12_DIV_MSK (0x1F << 8) |
defines | #define MP_DIV_SHIFT (4) |
defines | #define MP_DIV_MSK (0xF << 4) |
defines | #define M0_DIV_MSK (0xF) |
defines | #define PD_BUS_SEL_PLL_MSK (1 << 15) |
defines | #define PD_BUS_SEL_CPLL (0 << 15) |
defines | #define PD_BUS_SEL_GPLL (1 << 15) |
defines | #define PD_BUS_PCLK_DIV_SHIFT (12) |
defines | #define PD_BUS_PCLK_DIV_MSK (0x7 << 12) |
defines | #define PD_BUS_HCLK_DIV_SHIFT (8) |
defines | #define PD_BUS_HCLK_DIV_MSK (0x3 << 8) |
defines | #define PD_BUS_ACLK_DIV0_SHIFT (3) |
defines | #define PD_BUS_ACLK_DIV0_MASK (0x1f << 3) |
defines | #define PD_BUS_ACLK_DIV1_SHIFT (0) |
defines | #define PD_BUS_ACLK_DIV1_MASK (0x7 << 0) |
defines | #define PERI_SEL_PLL_MSK (1 << 15) |
defines | #define PERI_SEL_CPLL (0 << 15) |
defines | #define PERI_SEL_GPLL (1 << 15) |
defines | #define PERI_PCLK_DIV_SHIFT (12) |
defines | #define PERI_PCLK_DIV_MSK (0x7 << 12) |
defines | #define PERI_HCLK_DIV_SHIFT (8) |
defines | #define PERI_HCLK_DIV_MSK (0x3 << 8) |
defines | #define PERI_ACLK_DIV_SHIFT (0x0) |
defines | #define PERI_ACLK_DIV_MSK (0x1F) |
defines | #define L2_DIV_MSK (0x7) |
defines |
#define ATCLK_DIV_MSK (0x1F << 4) |
defines | #define ATCLK_DIV_SHIFT (4) |
defines |
#define PCLK_DBG_DIV_MSK (0x1F << 9) |
defines | #define PCLK_DBG_DIV_SHIFT (9) |
defines |
#define APLL_MODE_MSK (0x3) |
defines | #define APLL_MODE_SLOW (0) |
defines | #define APLL_MODE_NORM (1) |
defines |
#define DPLL_MODE_MSK (0x3 << 4) |
defines | #define DPLL_MODE_SLOW (0 << 4) |
defines | #define DPLL_MODE_NORM (1 << 4) |
defines |
#define CPLL_MODE_MSK (0x3 << 8) |
defines | #define CPLL_MODE_SLOW (0 << 8) |
defines | #define CPLL_MODE_NORM (1 << 8) |
defines |
#define GPLL_MODE_MSK (0x3 << 12) |
defines | #define GPLL_MODE_SLOW (0 << 12) |
defines | #define GPLL_MODE_NORM (1 << 12) |
defines |
#define NPLL_MODE_MSK (0x3 << 14) |
defines | #define NPLL_MODE_SLOW (0 << 14) |
defines | #define NPLL_MODE_NORM (1 << 14) |
defines |
#define SOCSTS_DPLL_LOCK (1 << 5) |
defines | #define SOCSTS_APLL_LOCK (1 << 6) |
defines | #define SOCSTS_CPLL_LOCK (1 << 7) |
defines | #define SOCSTS_GPLL_LOCK (1 << 8) |
defines | #define SOCSTS_NPLL_LOCK (1 << 9) |
defines |
#define VCO_MAX_KHZ (2200 * (MHz/KHz)) |
defines | #define VCO_MIN_KHZ (440 * (MHz/KHz)) |
defines | #define OUTPUT_MAX_KHZ (2200 * (MHz/KHz)) |
defines | #define OUTPUT_MIN_KHZ 27500 |
defines | #define FREF_MAX_KHZ (2200 * (MHz/KHz)) |
defines | #define FREF_MIN_KHZ 269 |
structs | struct pll_div {
u32 nr;
u32 nf;
u32 no;
}; |
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