type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
structs | struct rk3288_cru_reg {
u32 cru_apll_con[4];
u32 cru_dpll_con[4];
u32 cru_cpll_con[4];
u32 cru_gpll_con[4];
u32 cru_npll_con[4];
u32 cru_mode_con;
u32 reserved0[3];
u32 cru_clksel_con[43];
u32 reserved1[21];
u32 cru_clkgate_con[19];
u32 reserved2;
u32 cru_glb_srst_fst_value;
u32 cru_glb_srst_snd_value;
u3... |
functions | int rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
{
/* All PLLs have same VCO and output frequency range restrictions. */
u32 vco_khz = OSC_HZ/KHz * div->nf / div->nr;
u32 output_khz = vco_khz / div->no;
printk(BIOS_DEBUG, "Configuring PLL at %p with NF = %d, NR = %d and "
"NO = %d (VCO = %uKHz, o... |
functions | int log2(unsigned int value)
{
unsigned int div = 0;
while (value != 1) {
div++;
value = ALIGN_UP(value, 2) / 2;
} |
functions | void rkclk_init(void)
{
u32 aclk_div;
u32 hclk_div;
u32 pclk_div;
/* pll enter slow-mode */
write32(&cru_ptr->cru_mode_con,
RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) |
RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW));
/* init pll */
rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg);
rkclk_set_pll(&... |
functions | void rkclk_configure_cpu(void)
{
/* pll enter slow-mode */
write32(&cru_ptr->cru_mode_con,
RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW));
rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg);
/* waiting for pll lock */
while (1) {
if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK)
break;
ude... |
functions | void rkclk_configure_ddr(unsigned int hz)
{
struct pll_div dpll_cfg;
switch (hz) {
case 300*MHz:
dpll_cfg = (struct pll_div){.nf = 25, .nr = 2, .no = 1} |
functions | void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy)
{
u32 phy_ctl_srstn_shift = 4 + 5 * ch;
u32 ctl_psrstn_shift = 3 + 5 * ch;
u32 ctl_srstn_shift = 2 + 5 * ch;
u32 phy_psrstn_shift = 1 + 5 * ch;
u32 phy_srstn_shift = 5 * ch;
write32(&cru_ptr->cru_softrst_con[10],
RK_CLRSETBITS(1 << phy_ctl_srstn_shift,
ph... |
functions | void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n)
{
u32 phy_ctl_srstn_shift = 4 + 5 * ch;
write32(&cru_ptr->cru_softrst_con[10],
RK_CLRSETBITS(1 << phy_ctl_srstn_shift,
n << phy_ctl_srstn_shift));
} |
functions | void rkclk_configure_spi(unsigned int bus, unsigned int hz)
{
int src_clk_div = GPLL_HZ / hz;
assert((src_clk_div - 1 < 127) && (src_clk_div * hz == GPLL_HZ));
switch (bus) { /*select gpll as spi src clk, and set div*/
case 0:
write32(&cru_ptr->cru_clksel_con[25],
RK_CLRSETBITS(1 << 7 | 0x1f << 0,
... |
functions | u32 clk_gcd(u32 a, u32 b)
{
while (b != 0) {
int r = b;
b = a % b;
a = r;
} |
functions | void rkclk_configure_i2s(unsigned int hz)
{
int n, d;
int v;
/* i2s source clock: gpll
i2s0_outclk_sel: clk_i2s
i2s0_clk_sel: divider ouput from fraction
i2s0_pll_div_con: 0*/
write32(&cru_ptr->cru_clksel_con[4],
RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0,
1 << 15 | 0 << 12 | 1 << ... |
functions | void rkclk_configure_crypto(unsigned int hz)
{
u32 div = PD_BUS_ACLK_HZ / hz;
assert((div - 1 < 4) && (div * hz == PD_BUS_ACLK_HZ));
assert(hz <= 150*MHz); /* Suggested max in TRM. */
write32(&cru_ptr->cru_clksel_con[26],
RK_CLRSETBITS(0x3 << 6, (div - 1) << 6));
} |
functions | void rkclk_configure_tsadc(unsigned int hz)
{
u32 div;
u32 src_clk = 32 * KHz; /* tsadc source clock is 32KHz*/
div = src_clk / hz;
assert((div - 1 < 64) && (div * hz == 32 * KHz));
write32(&cru_ptr->cru_clksel_con[2],
RK_CLRSETBITS(0x3f << 0, (div - 1) << 0));
} |
functions | int pll_para_config(u32 freq_hz, struct pll_div *div)
{
u32 ref_khz = OSC_HZ / KHz, nr, nf = 0;
u32 fref_khz;
u32 diff_khz, best_diff_khz;
const u32 max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
u32 vco_khz;
u32 no = 1;
u32 freq_khz = freq_hz / KHz;
if (!freq_hz) {
printk(BIOS_ERR, "%s: the frequency c... |
functions | void rkclk_configure_edp(void)
{
/* clk_edp_24M source: 24M */
write32(&cru_ptr->cru_clksel_con[28], RK_SETBITS(1 << 15));
/* rst edp */
write32(&cru_ptr->cru_softrst_con[6], RK_SETBITS(1 << 15));
udelay(1);
write32(&cru_ptr->cru_softrst_con[6], RK_CLRBITS(1 << 15));
} |
functions | void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
{
u32 div;
/* vop aclk source clk: cpll */
div = CPLL_HZ / aclk_hz;
assert((div - 1 < 64) && (div * aclk_hz == CPLL_HZ));
switch (vop_id) {
case 0:
write32(&cru_ptr->cru_clksel_con[31],
RK_CLRSETBITS(3 << 6 | 0x1f << 0,
0 << 6 | (div - 1) << ... |
functions | int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
{
struct pll_div npll_config = {0} |
functions | int rkclk_was_watchdog_reset(void)
{
/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
return read32(&cru_ptr->cru_glb_rst_st) & 0x30;
} |
includes |
#include <linux/slab.h> |
includes | #include <linux/init.h> |
includes | #include <linux/module.h> |
includes | #include <linux/mtd/mtd.h> |
includes | #include <linux/mtd/nand.h> |
includes | #include <linux/mtd/partitions.h> |
includes | #include <asm/io.h> |
includes | #include <asm/arch/hardware.h> |
includes | #include <asm/sizes.h> |
includes | #include <asm/arch/h1900-gpio.h> |
includes | #include <asm/arch/pxa-regs.h> |
includes | #include <asm/setup.h> |
includes | #include <asm/memory.h> |
includes | #include <asm/mach-types.h> |
defines |
#define NUM_PARTITIONS 1 |
functions | void h1910_hwcontrol(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
if (cmd != NAND_CMD_NONE)
writeb(cmd, (void __iomem *)((unsigned long)chip->IO_ADDR_W | ((ctrl & 0x6) << 1)));
} |
functions | int h1910_device_ready(struct mtd_info *mtd)
{
return (GPLR(55) & GPIO_bit(55));
} |
functions | __init h1910_init(void)
{
struct nand_chip *this;
const char *part_type = 0;
int mtd_parts_nb = 0;
struct mtd_partition *mtd_parts = 0;
void __iomem *nandaddr;
if (!machine_is_h1900())
return -ENODEV;
nandaddr = ioremap(0x08000000, 0x1000);
if (!nandaddr) {
printk("Failed to ioremap nand flash.\n");
ret... |
functions | endif
if (mtd_parts_nb == 0) {
mtd_parts = partition_info;
mtd_parts_nb = NUM_PARTITIONS;
part_type = "static";
} |
functions | __exit h1910_cleanup(void)
{
struct nand_chip *this = (struct nand_chip *)&h1910_nand_mtd[1];
/* Release resources, unregister device */
nand_release(h1910_nand_mtd);
/* Release io resource */
iounmap((void *)this->IO_ADDR_W);
/* Free the MTD device structure */
kfree(h1910_nand_mtd);
} |
includes | #include <errno.h> |
includes | #include <fcntl.h> |
includes | #include <netinet/in.h> |
includes | #include <stdio.h> |
includes | #include <signal.h> |
includes | #include <syslog.h> |
includes | #include <sys/stat.h> |
includes | #include <sys/time.h> |
includes | #include <sys/types.h> |
includes | #include <unistd.h> |
includes |
#include <bbftpd.h> |
includes | #include <common.h> |
includes | #include <daemon.h> |
includes | #include <status.h> |
includes | #include <structures.h> |
includes | #include <zlib.h> |
functions | int sendafile(int code) {
char receive_buffer[MAXMESSLEN] ;
char receive_buffer_sup[MAXMESSLEN] ;
char send_buffer[MAXMESSLEN] ;
int savederrno ;
char readbuffer[READBUFLEN] ;
char buffercomp[READBUFLEN] ;
struct mess_compress *msg_compress ;
#ifdef WITH_GZIP
u... |
functions | endif
if ( code == MSG_RETR ) {
compressiontype = NOCOMPRESSION ;
syslog(BBFTPD_DEBUG,"Retreiving file %s with %d children",readfilename,msg_store->nbport) ;
} |
functions | else if ( msg->code == MSG_CREATE_ZERO ) {
syslog(BBFTPD_INFO,"Send zero length file") ;
return 0 ;
} |
functions | else if ( msg->code != MSG_RETR_START ) {
syslog(BBFTPD_ERR,"Receive Unknown message code while waiting RETRSTART %d",msg->code) ;
return -1 ;
} |
functions | WITH_GZIP
if ( compressiontype == COMPRESSION ) {
/*
** In case of compression we are going to use
** a temporary buffer
*/
bufcomplen = READBUFLEN ;
buflen... |
functions | else if ( retcode == 0 ) {
syslog(BBFTPD_ERR,"Time out while sending") ;
close(fd) ;
i=ETIMEDOUT ;
close(sendsock) ;
exit(i) ;
} |
functions | else if ( retcode == 0 ) {
i = ECONNRESET ;
syslog(BBFTPD_ERR,"Connexion breaks") ;
close(fd) ;
close(sendsock) ;
exit(i) ;
} |
includes |
#include <linux/module.h> |
includes | #include <linux/kernel.h> |
includes | #include <linux/errno.h> |
includes | #include <linux/string.h> |
includes | #include <linux/mm.h> |
includes | #include <linux/delay.h> |
includes | #include <linux/fb.h> |
includes | #include <linux/ioport.h> |
includes | #include <linux/init.h> |
includes | #include <linux/pci.h> |
includes | #include <linux/vmalloc.h> |
includes | #include <linux/pagemap.h> |
includes | #include <linux/interrupt.h> |
includes |
#include <asm/io.h> |
defines |
#define PLLS_I8xx 0
|
defines | #define PLLS_I9xx 1
|
defines | #define PLLS_MAX 2
|
structs | struct pll_min_max {
int min_m, max_m, min_m1, max_m1;
int min_m2, max_m2, min_n, max_n;
int min_p, max_p, min_p1, max_p1;
int min_vco, max_vco, p_transition_clk, ref_clk;
int p_inc_lo, p_inc_hi;
}; |
functions | int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
{
u32 tmp;
if (!pdev || !dinfo)
return 1;
switch (pdev->device) {
case PCI_DEVICE_ID_INTEL_830M:
dinfo->name = "Intel(R) 830M";
dinfo->chipset = INTEL_830M;
dinfo->mobile = 1;
dinfo->pll_index = PLLS_I8xx;
return 0;... |
functions | int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
int *stolen_size)
{
struct pci_dev *bridge_dev;
u16 tmp;
int stolen_overhead;
if (!pdev || !aperture_size || !stolen_size)
return 1;
/* Find the bridge device. It is always 0:0.0 */
if (!(bridge_dev = pci_get_bus_and_slot(0, PC... |
functions | int intelfbhw_check_non_crt(struct intelfb_info *dinfo)
{
int dvo = 0;
if (INREG(LVDS) & PORT_ENABLE)
dvo |= LVDS_PORT;
if (INREG(DVOA) & PORT_ENABLE)
dvo |= DVOA_PORT;
if (INREG(DVOB) & PORT_ENABLE)
dvo |= DVOB_PORT;
if (INREG(DVOC) & PORT_ENABLE)
dvo |= DVOC_PORT;
return dvo;
} |
functions | int intelfbhw_validate_mode(struct intelfb_info *dinfo,
struct fb_var_screeninfo *var)
{
int bytes_per_pixel;
int tmp;
#if VERBOSE > 0
DBG_MSG("intelfbhw_validate_mode\n");
#endif
bytes_per_pixel = var->bits_per_pixel / 8;
if (bytes_per_pixel == 3)
bytes_per_pixel = 4;
/* Check if enough... |
functions | int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct intelfb_info *dinfo = GET_DINFO(info);
u32 offset, xoffset, yoffset;
#if VERBOSE > 0
DBG_MSG("intelfbhw_pan_display\n");
#endif
xoffset = ROUND_DOWN_TO(var->xoffset, 8);
yoffset = var->yoffset;
if ((xoffset + in... |
functions | void intelfbhw_do_blank(int blank, struct fb_info *info)
{
struct intelfb_info *dinfo = GET_DINFO(info);
u32 tmp;
#if VERBOSE > 0
DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
#endif
/* Turn plane A on or off */
tmp = INREG(DSPACNTR);
if (blank)
tmp &= ~DISPPLANE_PLANE_ENABLE;
else
tmp... |
functions | int intelfbhw_active_pipe(const struct intelfb_hwstate *hw)
{
int pipe = -1;
/* keep old default behaviour - prefer PIPE_A */
if (hw->disp_b_ctrl & DISPPLANE_PLANE_ENABLE) {
pipe = (hw->disp_b_ctrl >> DISPPLANE_SEL_PIPE_SHIFT);
pipe &= PIPE_MASK;
if (unlikely(pipe == PIPE_A))
return PIPE_A;
} |
functions | void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp)
{
u32 palette_reg = (dinfo->pipe == PIPE_A) ?
PALETTE_A : PALETTE_B;
#if VERBOSE > 0
DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
regno, red, green, blue);
... |
functions | int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
struct intelfb_hwstate *hw, int flag)
{
int i;
#if VERBOSE > 0
DBG_MSG("intelfbhw_read_hw_state\n");
#endif
if (!hw || !dinfo)
return -1;
/* Read in as much of the HW state as possible. */
hw->vga0_divisor = INREG(VGA0_DIVISOR);
hw-... |
functions | int calc_vclock3(int index, int m, int n, int p)
{
if (p == 0 || n == 0)
return 0;
return plls[index].ref_clk * m / n / p;
} |
functions | int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
int lvds)
{
struct pll_min_max *pll = &plls[index];
u32 m, vco, p;
m = (5 * (m1 + 2)) + (m2 + 2);
n += 2;
vco = pll->ref_clk * m / n;
if (index == PLLS_I8xx)
p = ((p1 + 2) * (1 << (p2 + 1)));
else
p = ((p1) * (p2 ? 5 : ... |
functions | void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
int *o_p1, int *o_p2)
{
int p1, p2;
if (IS_I9XX(dinfo)) {
if (dpll & DPLL_P1_FORCE_DIV2)
p1 = 1;
else
p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
p1 = ffs(p1);
p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
} |
functions | void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
struct intelfb_hwstate *hw)
{
#if REGDUMP
int i, m1, m2, n, p1, p2;
int index = dinfo->pll_index;
DBG_MSG("intelfbhw_print_hw_state\n");
if (!hw)
return;
/* Read in as much of the HW state as possible. */
printk("hw state dump start\... |
functions | int splitm(int index, unsigned int m, unsigned int *retm1,
unsigned int *retm2)
{
int m1, m2;
int testm;
struct pll_min_max *pll = &plls[index];
/* no point optimising too much - brute force m */
for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++)... |
functions | int splitp(int index, unsigned int p, unsigned int *retp1,
unsigned int *retp2)
{
int p1, p2;
struct pll_min_max *pll = &plls[index];
if (index == PLLS_I9xx) {
p2 = (p % 10) ? 1 : 0;
p1 = p / (p2 ? 5 : 10);
*retp1 = (unsigned int)p1;
*retp2 = (unsigned int)p2;
return 0;
} |
functions | int calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2,
u32 *retn, u32 *retp1, u32 *retp2, u32 *retclock)
{
u32 m1, m2, n, p1, p2, n1, testm;
u32 f_vco, p, p_best = 0, m, f_out = 0;
u32 err_max, err_target, err_best = 10000000;
u32 n_best = 0, m_best = 0, f_best, f_err;
u32 p_min, p_max, p_i... |
functions | int check_overflow(u32 value, u32 limit,
const char *description)
{
if (value > limit) {
WRN_MSG("%s value %d exceeds limit %d\n",
description, value, limit);
return 1;
} |
functions | int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
struct intelfb_hwstate *hw,
struct fb_var_screeninfo *var)
{
int pipe = intelfbhw_active_pipe(hw);
u32 *dpll, *fp0, *fp1;
u32 m1, m2, n, p1, p2, clock_target, clock;
u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
u32 vsync... |
functions | int intelfbhw_program_mode(struct intelfb_info *dinfo,
const struct intelfb_hwstate *hw, int blank)
{
u32 tmp;
const u32 *dpll, *fp0, *fp1, *pipe_conf;
const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg;
u32 hsync_reg, htotal_reg, hblank_reg;
u3... |
functions | u32 get_ring_space(struct intelfb_info *dinfo)
{
u32 ring_space;
if (dinfo->ring_tail >= dinfo->ring_head)
ring_space = dinfo->ring.size -
(dinfo->ring_tail - dinfo->ring_head);
else
ring_space = dinfo->ring_head - dinfo->ring_tail;
if (ring_space > RING_MIN_FREE)
ring_space -= RING_MIN_FREE;
... |
functions | int wait_ring(struct intelfb_info *dinfo, int n)
{
int i = 0;
unsigned long end;
u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
#if VERBOSE > 0
DBG_MSG("wait_ring: %d\n", n);
#endif
end = jiffies + (HZ * 3);
while (dinfo->ring_space < n) {
dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEA... |
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