type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
defines |
#define AFI_FPCI_BAR0 0x30 |
defines | #define AFI_FPCI_BAR1 0x34 |
defines | #define AFI_FPCI_BAR2 0x38 |
defines | #define AFI_FPCI_BAR3 0x3c |
defines | #define AFI_FPCI_BAR4 0x40 |
defines | #define AFI_FPCI_BAR5 0x44 |
defines |
#define AFI_CACHE_BAR0_SZ 0x48 |
defines | #define AFI_CACHE_BAR0_ST 0x4c |
defines | #define AFI_CACHE_BAR1_SZ 0x50 |
defines | #define AFI_CACHE_BAR1_ST 0x54 |
defines |
#define AFI_MSI_BAR_SZ 0x60 |
defines | #define AFI_MSI_FPCI_BAR_ST 0x64 |
defines | #define AFI_MSI_AXI_BAR_ST 0x68 |
defines |
#define AFI_MSI_VEC0_0 0x6c |
defines | #define AFI_MSI_VEC1_0 0x70 |
defines | #define AFI_MSI_VEC2_0 0x74 |
defines | #define AFI_MSI_VEC3_0 0x78 |
defines | #define AFI_MSI_VEC4_0 0x7c |
defines | #define AFI_MSI_VEC5_0 0x80 |
defines | #define AFI_MSI_VEC6_0 0x84 |
defines | #define AFI_MSI_VEC7_0 0x88 |
defines |
#define AFI_MSI_EN_VEC0_0 0x8c |
defines | #define AFI_MSI_EN_VEC1_0 0x90 |
defines | #define AFI_MSI_EN_VEC2_0 0x94 |
defines | #define AFI_MSI_EN_VEC3_0 0x98 |
defines | #define AFI_MSI_EN_VEC4_0 0x9c |
defines | #define AFI_MSI_EN_VEC5_0 0xa0 |
defines | #define AFI_MSI_EN_VEC6_0 0xa4 |
defines | #define AFI_MSI_EN_VEC7_0 0xa8 |
defines |
#define AFI_CONFIGURATION 0xac |
defines | #define AFI_CONFIGURATION_EN_FPCI (1 << 0) |
defines |
#define AFI_FPCI_ERROR_MASKS 0xb0 |
defines |
#define AFI_INTR_MASK 0xb4 |
defines | #define AFI_INTR_MASK_INT_MASK (1 << 0) |
defines | #define AFI_INTR_MASK_MSI_MASK (1 << 8) |
defines |
#define AFI_INTR_CODE 0xb8 |
defines | #define AFI_INTR_CODE_MASK 0x1f |
defines | #define AFI_INTR_MASTER_ABORT 4 |
defines | #define AFI_INTR_LEGACY 6 |
defines | #define AFI_INTR_PRSNT_SENSE 10 |
defines |
#define AFI_INTR_SIGNATURE 0xbc |
defines | #define AFI_SM_INTR_ENABLE 0xc4 |
defines |
#define AFI_AFI_INTR_ENABLE 0xc8 |
defines | #define AFI_INTR_EN_INI_SLVERR (1 << 0) |
defines | #define AFI_INTR_EN_INI_DECERR (1 << 1) |
defines | #define AFI_INTR_EN_TGT_SLVERR (1 << 2) |
defines | #define AFI_INTR_EN_TGT_DECERR (1 << 3) |
defines | #define AFI_INTR_EN_TGT_WRERR (1 << 4) |
defines | #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) |
defines | #define AFI_INTR_EN_AXI_DECERR (1 << 6) |
defines | #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) |
defines | #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) |
defines |
#define AFI_PCIE_PME 0x0f0 |
defines | #define AFI_PCIE_PME_TURN_OFF 0x101 |
defines | #define AFI_PCIE_PME_ACK 0x420 |
defines |
#define AFI_PCIE_CONFIG 0x0f8 |
defines | #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1) |
defines | #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2) |
defines | #define AFI_PCIE_CONFIG_XBAR_CONFIG_MASK (0xf << 20) |
defines | #define AFI_PCIE_CONFIG_XBAR_CONFIG_X2_X1 (0x0 << 20) |
defines | #define AFI_PCIE_CONFIG_XBAR_CONFIG_X4_X1 (0x1 << 20) |
defines |
#define AFI_FUSE 0x104 |
defines | #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) |
defines |
#define AFI_PEX0_CTRL 0x110 |
defines | #define AFI_PEX1_CTRL 0x118 |
defines | #define AFI_PEX_CTRL_RST (1 << 0) |
defines | #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) |
defines | #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) |
defines | #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) |
defines |
#define AFI_PLLE_CONTROL 0x160 |
defines | #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) |
defines | #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) |
defines | #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) |
defines | #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) |
defines |
#define AFI_PEXBIAS_CTRL_0 0x168 |
defines | #define AFI_WR_SCRATCH_0 0x120 |
defines | #define AFI_WR_SCRATCH_0_RESET_VAL 0x00202020 |
defines | #define AFI_WR_SCRATCH_0_DEFAULT_VAL 0x00000000 |
defines |
#define AFI_MSG_0 0x190 |
defines | #define AFI_MSG_PM_PME_MASK 0x00100010 |
defines | #define AFI_MSG_INTX_MASK 0x1f001f00 |
defines | #define AFI_MSG_PM_PME0 (1 << 4) |
defines | #define AFI_MSG_RP_INT_MASK 0x10001000 |
defines |
#define RP_VEND_XP 0x00000F00 |
defines | #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) |
defines | #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) |
defines | #define RP_VEND_XP_DL_UP (1 << 30) |
defines | #define RP_VEND_XP_UPDATE_FC_THRESHOLD (0xFF << 18) |
defines |
#define RP_LINK_CONTROL_STATUS 0x00000090 |
defines | #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 |
defines | #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 |
defines | #define RP_LINK_CONTROL_STATUS_NEG_LINK_WIDTH (0x3F << 20) |
defines | #define RP_LINK_CONTROL_STATUS_L0s_ENABLED 0x00000001 |
defines | #define RP_LINK_CONTROL_STATUS_L1_ENABLED 0x00000002 |
defines |
#define NV_PCIE2_RP_RSR 0x000000A0 |
defines | #define NV_PCIE2_RP_RSR_PMESTAT (1 << 16) |
defines |
#define NV_PCIE2_RP_INTR_BCR 0x0000003C |
defines | #define NV_PCIE2_RP_INTR_BCR_INTR_LINE (0xFF << 0) |
defines | #define NV_PCIE2_RP_INTR_BCR_SB_RESET (0x1 << 22) |
defines |
#define NV_PCIE2_RP_PRIV_XP_DL 0x00000494 |
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