type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
defines | #define TEGRA_PCIE_EMC_CLK_102 102000000 |
defines | #define TEGRA_PCIE_EMC_CLK_528 528000000 |
defines |
#define INT_PCI_MSI_NR (32 * 8) |
defines |
#define DEBUG 0 |
defines | #define PR_FUNC_LINE pr_info("PCIE: %s(%d)\n", __func__, __LINE__) |
defines | #define PR_FUNC_LINE do {} while (0) |
defines | #define pinctrl_compatible "nvidia,tegra210-pinmux" |
defines | #define pin_pex_l0_clkreq "pex_l0_clkreq_n_pa1" |
defines | #define pin_pex_l1_clkreq "pex_l1_clkreq_n_pa4" |
defines | #define pinctrl_compatible "nvidia,tegra124-pinmux" |
defines | #define pin_pex_l0_clkreq "pex_l0_clkreq_n_pdd2" |
defines | #define pin_pex_l1_clkreq "pex_l1_clkreq_n_pdd6" |
defines | #define MSELECT_CONFIG_BASE 0x50060000 |
defines | #define MSELECT_CONFIG_WRAP_TO_INCR_SLAVE1 BIT(28) |
defines | #define MSELECT_CONFIG_ERR_RESP_EN_SLAVE1 BIT(24) |
defines | #define FPGA_GEN2_SPEED_SUPPORT 0x90000001 |
defines | #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ |
defines |
#define DEFINE_ENTRY(__name) \ |
structs | struct tegra_pcie_soc_data {
unsigned int num_ports;
char **pcie_regulator_names;
int num_pcie_regulators;
}; |
structs | struct tegra_msi {
struct msi_chip chip;
DECLARE_BITMAP(used, INT_PCI_MSI_NR);
struct irq_domain *domain;
unsigned long pages;
struct mutex lock;
int irq;
}; |
structs | struct tegra_pcie {
struct device *dev;
void __iomem *pads;
void __iomem *afi;
int irq;
struct list_head buses;
struct list_head sys;
struct resource *cs;
struct resource *afi_res;
struct resource *pads_res;
struct resource io;
struct resource mem;
struct resource prefetch;
struct resource busn;
struc... |
structs | struct tegra_pcie_port {
struct tegra_pcie *pcie;
struct list_head list;
struct resource regs;
void __iomem *base;
unsigned int index;
unsigned int lanes;
int gpio_presence_detection;
bool disable_clock_request;
int status;
struct dentry *port_debugfs;
}; |
structs | struct tegra_pcie_bus {
struct vm_struct *area;
struct list_head list;
unsigned int nr;
}; |
structs | struct msi_map_entry {
bool used;
u8 index;
int irq;
}; |
functions | void afi_writel(struct tegra_pcie *pcie, u32 value,
unsigned long offset)
{
writel(value, offset + pcie->afi);
} |
functions | u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
{
return readl(offset + pcie->afi);
} |
functions | void pads_writel(struct tegra_pcie *pcie, u32 value,
unsigned long offset)
{
writel(value, offset + pcie->pads);
} |
functions | u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
{
return readl(offset + pcie->pads);
} |
functions | void rp_writel(struct tegra_pcie_port *port, u32 value,
unsigned long offset)
{
writel(value, offset + port->base);
} |
functions | int rp_readl(struct tegra_pcie_port *port,
unsigned long offset)
{
return readl(offset + port->base);
} |
functions | long tegra_pcie_conf_offset(unsigned int devfn, int where)
{
return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
(PCI_FUNC(devfn) << 8) | (where & 0xfc);
} |
functions | int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *value)
{
void __iomem *addr;
addr = tegra_pcie_conf_address(bus, devfn, where);
if (!addr) {
*value = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
} |
functions | int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 value)
{
void __iomem *addr;
u32 mask, tmp;
addr = tegra_pcie_conf_address(bus, devfn, where);
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;
if (size == 4) {
writel(value, addr);
return PCIBIOS_SUCCESSFUL;
} |
functions | void tegra_pcie_fixup_bridge(struct pci_dev *dev)
{
u16 reg;
if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
pci_read_config_word(dev, PCI_COMMAND, ®);
reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
pci_write_config_word(dev, PCI_COMMAND, reg);
} |
functions | void tegra_pcie_fixup_class(struct pci_dev *dev)
{
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
} |
functions | void tegra_pcie_relax_enable(struct pci_dev *dev)
{
pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
} |
functions | int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
{
struct tegra_pcie *pcie = sys_to_pcie(sys);
int err;
PR_FUNC_LINE;
err = devm_request_resource(pcie->dev, &iomem_resource, &pcie->mem);
if (err < 0)
return err;
err = devm_request_resource(pcie->dev, &iomem_resource,
&pcie->prefetch);
if (err < 0) ... |
functions | int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct tegra_pcie *pcie = sys_to_pcie(dev->bus->sysdata);
return pcie->irq;
} |
functions | void tegra_pcie_add_bus(struct pci_bus *bus)
{
struct tegra_pcie_bus *tbus;
struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
PR_FUNC_LINE;
/* bus 0 is root complex whose config space is already mapped */
if (!bus->number)
return;
if (IS_ENABLED(CONFIG_PCI_MSI))
bus->msi = &pcie->msi.chip;
/* Allocate m... |
functions | void tegra_pcie_teardown(int nr, struct pci_sys_data *sys)
{
struct tegra_pcie *pcie = sys_to_pcie(sys);
pci_iounmap_io(nr * resource_size(&pcie->io));
} |
functions | __init tegra_pcie_hotplug_init(void)
{
struct pci_sys_data *sys = NULL;
int ret, nr;
if (is_dock_conn_at_boot)
return;
PR_FUNC_LINE;
tegra_pcie_preinit();
for (nr = 0; nr < tegra_pcie_hw.nr_controllers; nr++) {
sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
if (!sys)
panic("PCI: unable to allo... |
functions | void tegra_pcie_enable_aer(struct tegra_pcie_port *port, bool enable)
{
unsigned int data;
PR_FUNC_LINE;
data = rp_readl(port, NV_PCIE2_RP_VEND_CTL1);
if (enable)
data |= PCIE2_RP_VEND_CTL1_ERPT;
else
data &= ~PCIE2_RP_VEND_CTL1_ERPT;
rp_writel(port, data, NV_PCIE2_RP_VEND_CTL1);
} |
functions | int tegra_pcie_attach(struct tegra_pcie *pcie)
{
struct pci_bus *bus = NULL;
struct tegra_pcie_port *port;
PR_FUNC_LINE;
if (!hotplug_event)
return 0;
/* rescan and recreate all pcie data structures */
while ((bus = pci_find_next_bus(bus)) != NULL)
pci_rescan_bus(bus);
/* unhide AER capability */
list_for... |
functions | int tegra_pcie_detach(struct tegra_pcie *pcie)
{
struct pci_dev *pdev = NULL;
struct tegra_pcie_port *port;
PR_FUNC_LINE;
if (hotplug_event)
return 0;
hotplug_event = true;
/* hide AER capability to avoid log spew */
list_for_each_entry(port, &pcie->ports, list)
tegra_pcie_enable_aer(port, false);
/* rem... |
functions | void tegra_pcie_prsnt_map_override(struct tegra_pcie_port *port,
bool prsnt)
{
unsigned int data;
PR_FUNC_LINE;
/* currently only hotplug on root port 0 supported */
data = rp_readl(port, NV_PCIE2_RP_PRIV_MISC);
data &= ~PCIE2_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
if (prsnt)
data |= PCIE2_RP_PRIV_MISC_PRSNT_MA... |
functions | void work_hotplug_handler(struct work_struct *work)
{
struct tegra_pcie *pcie_driver =
container_of(work, struct tegra_pcie, hotplug_detect);
int val;
PR_FUNC_LINE;
if (pcie_driver->plat_data->gpio_hot_plug == -1)
return;
val = gpio_get_value(pcie_driver->plat_data->gpio_hot_plug);
if (val == 0) {
dev_info... |
functions | irqreturn_t gpio_pcie_detect_isr(int irq, void *arg)
{
struct tegra_pcie *pcie = arg;
PR_FUNC_LINE;
schedule_work(&pcie->hotplug_detect);
return IRQ_HANDLED;
} |
functions | void handle_sb_intr(struct tegra_pcie *pcie)
{
u32 mesg;
PR_FUNC_LINE;
mesg = afi_readl(pcie, AFI_MSG_0);
if (mesg & AFI_MSG_INTX_MASK)
/* notify device isr for INTx messages from pcie devices */
dev_dbg(pcie->dev,
"Legacy INTx interrupt occurred %x\n", mesg);
else if (mesg & AFI_MSG_PM_PME_MASK) {
struc... |
functions | irqreturn_t tegra_pcie_isr(int irq, void *arg)
{
const char *err_msg[] = {
"Unknown",
"AXI slave error",
"AXI decode error",
"Target abort",
"Master abort",
"Invalid write",
"",
"Response decoding error",
"AXI response decoding error",
"Transcation timeout",
"",
"Slot Clock request change",
"... |
functions | void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
{
u32 fpci_bar, size, axi_address;
/* Bar 0: type 1 extended configuration space */
fpci_bar = 0xfe100000;
size = resource_size(pcie->cs);
axi_address = pcie->cs->start;
afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
afi_writel(pcie, size >> 12, AF... |
functions | int tegra_pcie_enable_pads(struct tegra_pcie *pcie, bool enable)
{
int err = 0;
PR_FUNC_LINE;
if (enable) {
if (pex_usb_pad_pll_reset_deassert())
dev_err(pcie->dev, "failed to deassert pex pll\n");
} |
functions | void tegra_pcie_enable_wrap(void)
{
#if defined(CONFIG_ARCH_TEGRA_21x_SOC)
u32 val;
void __iomem *msel_base;
PR_FUNC_LINE;
/* Config MSELECT to support wrap trans for normal NC & GRE mapping */
msel_base = ioremap(MSELECT_CONFIG_BASE, 4);
val = readl(msel_base);
/* Enable WRAP_TO_INCR_SLAVE1 */
val |= MSEL... |
functions | int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
{
u32 val;
struct tegra_pcie_port *port, *tmp;
PR_FUNC_LINE;
tegra_pcie_enable_wrap();
/* Enable PLL power down */
val = afi_readl(pcie, AFI_PLLE_CONTROL);
val &= ~AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL;
val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONT... |
functions | int tegra_pcie_enable_regulators(struct tegra_pcie *pcie)
{
int i;
PR_FUNC_LINE;
if (pcie->power_rails_enabled) {
dev_info(pcie->dev, "PCIE: Already power rails enabled\n");
return 0;
} |
functions | int tegra_pcie_disable_regulators(struct tegra_pcie *pcie)
{
int i;
PR_FUNC_LINE;
if (pcie->power_rails_enabled == 0) {
dev_info(pcie->dev, "PCIE: Already power rails disabled\n");
return 0;
} |
functions | int tegra_pcie_power_ungate(struct tegra_pcie *pcie)
{
int err;
int partition_id;
PR_FUNC_LINE;
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
partition_id = tegra_pd_get_powergate_id(tegra_pcie_pd);
if (partition_id < 0)
return -EINVAL;
#else
partition_id = TEGRA_POWERGATE_PCIE;
#endif
err = clk_prepare_enable(pcie->p... |
functions | int tegra_pcie_map_resources(struct tegra_pcie *pcie)
{
struct platform_device *pdev = to_platform_device(pcie->dev);
struct resource *pads, *afi, *res;
PR_FUNC_LINE;
pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
pcie->pads_res = __devm_request_region(&pdev->dev, &iomem_resource,
pads->st... |
functions | void tegra_pcie_unmap_resources(struct tegra_pcie *pcie)
{
struct platform_device *pdev = to_platform_device(pcie->dev);
PR_FUNC_LINE;
if (pcie->cs)
__devm_release_region(&pdev->dev, &iomem_resource,
pcie->cs->start,
resource_size(pcie->cs));
if (pcie->afi_res)
__devm_release_region(&pdev->dev, &iomem... |
functions | int tegra_pcie_fpga_phy_init(struct tegra_pcie *pcie)
{
struct tegra_pcie_port *port;
PR_FUNC_LINE;
/* Do reset for FPGA pcie phy */
afi_writel(pcie, AFI_WR_SCRATCH_0_RESET_VAL, AFI_WR_SCRATCH_0);
udelay(10);
afi_writel(pcie, AFI_WR_SCRATCH_0_DEFAULT_VAL, AFI_WR_SCRATCH_0);
udelay(10);
afi_writel(pcie, AFI_WR... |
functions | void tegra_pcie_pme_turnoff(struct tegra_pcie *pcie)
{
unsigned int data;
PR_FUNC_LINE;
if (tegra_platform_is_fpga())
return;
data = afi_readl(pcie, AFI_PCIE_PME);
data |= AFI_PCIE_PME_TURN_OFF;
afi_writel(pcie, data, AFI_PCIE_PME);
do {
data = afi_readl(pcie, AFI_PCIE_PME);
} |
functions | int tegra_pcie_power_on(struct tegra_pcie *pcie)
{
int err = 0;
PR_FUNC_LINE;
if (pcie->pcie_power_enabled) {
dev_info(pcie->dev, "PCIE: Already powered on");
goto err_exit;
} |
functions | int tegra_pcie_power_off(struct tegra_pcie *pcie, bool all)
{
int err = 0;
struct tegra_pcie_port *port;
int partition_id;
PR_FUNC_LINE;
if (pcie->pcie_power_enabled == 0) {
dev_info(pcie->dev, "PCIE: Already powered off");
goto err_exit;
} |
functions | int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
{
PR_FUNC_LINE;
/* get the PCIEXCLK */
pcie->pcie_xclk = clk_get_sys("tegra_pcie", "pciex");
if (IS_ERR_OR_NULL(pcie->pcie_xclk)) {
dev_err(pcie->dev, "unable to get PCIE Xclock\n");
return -EINVAL;
} |
functions | void tegra_pcie_clocks_put(struct tegra_pcie *pcie)
{
PR_FUNC_LINE;
if (pcie->pcie_xclk)
clk_put(pcie->pcie_xclk);
if (pcie->pcie_pcie)
clk_put(pcie->pcie_pcie);
if (pcie->pcie_afi)
clk_put(pcie->pcie_afi);
if (pcie->pcie_mselect)
clk_put(pcie->pcie_mselect);
if (pcie->pcie_pll_e)
clk_put(pcie->pcie_pll... |
functions | int tegra_pcie_get_resources(struct tegra_pcie *pcie)
{
struct platform_device *pdev = to_platform_device(pcie->dev);
int err;
PR_FUNC_LINE;
pcie->power_rails_enabled = 0;
pcie->pcie_power_enabled = 0;
err = tegra_pcie_clocks_get(pcie);
if (err) {
dev_err(pcie->dev, "PCIE: failed to get clocks: %d\n", err);
... |
functions | long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
{
unsigned long ret = 0;
switch (port->index) {
case 0:
ret = AFI_PEX0_CTRL;
break;
case 1:
ret = AFI_PEX1_CTRL;
break;
} |
functions | void tegra_pcie_port_reset(struct tegra_pcie_port *port)
{
unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
unsigned long value;
PR_FUNC_LINE;
/* pulse reset signal */
value = afi_readl(port->pcie, ctrl);
value &= ~AFI_PEX_CTRL_RST;
afi_writel(port->pcie, value, ctrl);
usleep_range(1000, 2000);
val... |
functions | void tegra_pcie_port_enable(struct tegra_pcie_port *port)
{
unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
unsigned long value;
PR_FUNC_LINE;
/* enable reference clock. Enable SW override so as to allow device
to get enumerated. SW override will be removed after enumeration
*/
value = afi_readl(po... |
functions | void tegra_pcie_port_disable(struct tegra_pcie_port *port)
{
u32 data;
PR_FUNC_LINE;
data = afi_readl(port->pcie, AFI_PCIE_CONFIG);
if (port->index)
data |= AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE;
else
data |= AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE;
afi_writel(port->pcie, data, AFI_PCIE_CONFIG);
} |
functions | bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
{
unsigned int retries = 3;
unsigned long value;
PR_FUNC_LINE;
do {
unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
do {
value = readl(port->base + RP_VEND_XP);
if (value & RP_VEND_XP_DL_UP)
break;
usleep_range(1000, 2000);
} |
functions | void tegra_pcie_apply_sw_war(struct tegra_pcie_port *port,
bool enum_done)
{
unsigned int data;
#if defined(CONFIG_ARCH_TEGRA_21x_SOC)
struct tegra_pcie *pcie = port->pcie;
#endif
struct pci_dev *pdev = NULL;
PR_FUNC_LINE;
#if defined(CONFIG_ARCH_TEGRA_21x_SOC)
/* T210 WAR for perf bugs required when LPDDR4 *... |
functions | void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
{
unsigned int data;
PR_FUNC_LINE;
if (port->pcie->prod_list) {
if (tegra_prod_set_by_name(
&(port->pcie->pads),
"prod_c_pad",
port->pcie->prod_list)) {
dev_info(port->pcie->dev,
"pad prod settings are not found in DT\n");
} |
functions | void tegra_pcie_update_lane_width(struct tegra_pcie_port *port)
{
port->lanes = rp_readl(port, RP_LINK_CONTROL_STATUS);
port->lanes = (port->lanes &
RP_LINK_CONTROL_STATUS_NEG_LINK_WIDTH) >> 20;
} |
functions | void mbist_war(struct tegra_pcie *pcie, bool apply)
{
struct tegra_pcie_port *port, *tmp;
u32 data;
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
/* nature of MBIST bug is such that it needs to be applied
* only for RootPort-0 even if there are no devices
* connected to it */
if (port->index =... |
functions | void tegra_pcie_check_ports(struct tegra_pcie *pcie)
{
struct tegra_pcie_port *port, *tmp;
PR_FUNC_LINE;
pcie->num_ports = 0;
#if defined(CONFIG_ARCH_TEGRA_21x_SOC)
mbist_war(pcie, true);
#endif
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
dev_info(pcie->dev, "probing port %u, using %u lanes and l... |
functions | int tegra_pcie_conf_gpios(struct tegra_pcie *pcie)
{
int irq, err = 0;
struct tegra_pcie_port *port, *tmp;
PR_FUNC_LINE;
if (gpio_is_valid(pcie->plat_data->gpio_hot_plug)) {
/* configure gpio for hotplug detection */
dev_info(pcie->dev, "acquiring hotplug_detect = %d\n",
pcie->plat_data->gpio_hot_plug);
... |
functions | int tegra_pcie_scale_voltage(struct tegra_pcie *pcie, bool isGen2)
{
int err = 0;
PR_FUNC_LINE;
if (isGen2) {
if (tegra_pcie_xclk_rate == TEGRA_PCIE_XCLK_500 &&
tegra_pcie_mselect_rate == TEGRA_PCIE_MSELECT_CLK_408 &&
tegra_pcie_emc_rate == TEGRA_PCIE_EMC_CLK_528)
goto skip;
/* Scale up voltage for Gen... |
functions | bool tegra_pcie_change_link_speed(struct tegra_pcie *pcie,
struct pci_dev *pdev, bool isGen2)
{
u16 val, link_sts_up_spd, link_sts_dn_spd;
u16 link_cap_up_spd, link_cap_dn_spd;
struct pci_dev *up_dev, *dn_dev;
PR_FUNC_LINE;
/* skip if current device is not PCI express capable */
/* or is either a root port o... |
functions | bool tegra_pcie_link_speed(struct tegra_pcie *pcie, bool isGen2)
{
struct pci_dev *pdev = NULL;
bool ret = false;
PR_FUNC_LINE;
/* Voltage scaling should happen before any device transition */
/* to Gen2 or after all devices has transitioned to Gen1 */
for_each_pci_dev(pdev) {
if (tegra_pcie_change_link_speed(... |
functions | void tegra_pcie_config_l1ss_tpwr_on(void)
{
struct pci_dev *pdev = NULL;
u32 data = 0, data1 = 0, data2 = 0, pos1 = 0, pos2 = 0;
unsigned long max1 = 0, max2 = 0;
PR_FUNC_LINE;
/* find max T_POWER_ON reported by RP & EP capability regs */
/* and program same in ctrl2 reg of both RP & EP */
for_each_pci_dev(pdev... |
functions | void tegra_pcie_config_l1ss_cm_rtime(void)
{
struct pci_dev *pdev = NULL;
u32 data = 0, max[MAX_PCIE_SUPPORTED_PORTS] = {0} |
functions | void tegra_pcie_config_l1ss_l12_thtime(void)
{
struct pci_dev *pdev = NULL;
u32 data = 0, pos = 0;
PR_FUNC_LINE;
/* program same LTR L1.2 threshold = 106us for all devices */
for_each_pci_dev(pdev) {
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
pci_read_config_dword(pdev, pos + PCI_L1SS_CTRL1, &d... |
functions | void tegra_pcie_enable_l1ss_support(void)
{
struct pci_dev *pdev = NULL;
u32 aspm = 0, data = 0, pos = 0;
PR_FUNC_LINE;
for_each_pci_dev(pdev) {
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
/* enable L1 substate as per device capability */
pci_read_config_dword(pdev, pos + PCI_L1SS_CAP, &aspm);
... |
functions | void tegra_pcie_enable_ltr_support(void)
{
struct pci_dev *pdev = NULL;
u16 val = 0;
u32 data = 0;
PR_FUNC_LINE;
/* enable LTR mechanism for L1.2 support */
for_each_pci_dev(pdev) {
pcie_capability_read_dword(pdev, PCI_EXP_DEVCAP2, &data);
if (data & PCI_EXP_DEVCAP2_LTR) {
pcie_capability_read_word(pdev, ... |
functions | void tegra_pcie_config_clkreq(struct tegra_pcie *pcie, bool enable)
{
static struct pinctrl_dev *pctl_dev = NULL;
unsigned long od_conf, tr_conf;
PR_FUNC_LINE;
if (!pctl_dev)
pctl_dev = pinctrl_get_dev_from_of_compatible(
pinctrl_compatible);
if (!pctl_dev) {
dev_err(pcie->dev,
"%s(): tegra pincontrol... |
functions | void tegra_pcie_enable_aspm(struct tegra_pcie *pcie)
{
#if defined(CONFIG_ARCH_TEGRA_21x_SOC)
struct pci_dev *pdev = NULL;
u32 aspm = 0;
int pos = 0;
bool config_l1ss = true;
#endif
PR_FUNC_LINE;
if (!pcie_aspm_support_enabled()) {
dev_info(pcie->dev, "PCIE: ASPM not enabled\n");
return;
} |
functions | void tegra_pcie_enable_features(struct tegra_pcie *pcie)
{
struct tegra_pcie_port *port;
PR_FUNC_LINE;
/* configure all links to gen2 speed by default */
if (!tegra_pcie_link_speed(pcie, true))
dev_info(pcie->dev, "PCIE: No Link speed change happened\n");
tegra_pcie_enable_aspm(pcie);
list_for_each_entry(port... |
functions | int tegra_pcie_init(struct tegra_pcie *pcie)
{
int err = 0;
struct platform_device *pdev = to_platform_device(pcie->dev);
pcibios_min_io = 0x1000ul;
PR_FUNC_LINE;
INIT_WORK(&pcie->hotplug_detect, work_hotplug_handler);
err = tegra_pcie_get_resources(pcie);
if (err) {
dev_err(pcie->dev, "PCIE: get resources f... |
functions | int tegra_msi_alloc(struct tegra_msi *chip)
{
int msi;
PR_FUNC_LINE;
mutex_lock(&chip->lock);
msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
if (msi < INT_PCI_MSI_NR)
set_bit(msi, chip->used);
else
msi = -ENOSPC;
mutex_unlock(&chip->lock);
return msi;
} |
functions | void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
{
struct device *dev = chip->chip.dev;
PR_FUNC_LINE;
mutex_lock(&chip->lock);
if (!test_bit(irq, chip->used))
dev_err(dev, "trying to free unused MSI#%lu\n", irq);
else
clear_bit(irq, chip->used);
mutex_unlock(&chip->lock);
} |
functions | irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
{
struct tegra_pcie *pcie = data;
struct tegra_msi *msi = &pcie->msi;
unsigned int i, processed = 0;
PR_FUNC_LINE;
for (i = 0; i < 8; i++) {
unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0_0 + i * 4);
while (reg) {
unsigned int offset = find_first_bit(... |
functions | int tegra_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
struct msi_desc *desc)
{
struct tegra_msi *msi = to_tegra_msi(chip);
struct msi_msg msg;
unsigned int irq;
int hwirq;
PR_FUNC_LINE;
hwirq = tegra_msi_alloc(msi);
if (hwirq < 0)
return hwirq;
irq = irq_create_mapping(msi->domain,... |
functions | void tegra_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
{
struct tegra_msi *msi = to_tegra_msi(chip);
struct irq_data *d = irq_get_irq_data(irq);
PR_FUNC_LINE;
tegra_msi_free(msi, d->hwirq);
} |
functions | int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
PR_FUNC_LINE;
irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
irq_set_chip_data(irq, domain->host_data);
set_irq_flags(irq, IRQF_VALID);
return 0;
} |
functions | int tegra_pcie_enable_msi(struct tegra_pcie *pcie, bool no_init)
{
struct platform_device *pdev = to_platform_device(pcie->dev);
struct tegra_msi *msi = &pcie->msi;
unsigned long base;
int err;
u32 reg;
PR_FUNC_LINE;
if (!msi->pages) {
if (no_init)
return true;
mutex_init(&msi->lock);
msi->chip.dev ... |
functions | int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
{
struct tegra_msi *msi = &pcie->msi;
unsigned int i, irq;
u32 value;
PR_FUNC_LINE;
if (pcie->pcie_power_enabled == 0)
return 0;
/* mask the MSI interrupt */
value = afi_readl(pcie, AFI_INTR_MASK);
value &= ~AFI_INTR_MASK_MSI_MASK;
afi_writel(pcie, value... |
functions | void tegra_pcie_read_plat_data(struct tegra_pcie *pcie)
{
struct device_node *node = pcie->dev->of_node;
PR_FUNC_LINE;
of_property_read_u32(node, "nvidia,boot-detect-delay",
&pcie->plat_data->boot_detect_delay);
pcie->plat_data->gpio_hot_plug =
of_get_named_gpio(node, "nvidia,hot-plug-gpio", 0);
pcie->plat_d... |
functions | int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
{
struct tegra_pcie_soc_data *soc = pcie->soc_data;
struct device_node *np = pcie->dev->of_node, *port;
struct of_pci_range_parser parser;
struct of_pci_range range;
u32 lanes = 0, mask = 0;
unsigned int lane = 0;
struct resource res;
int err;
PR_FUNC_LINE;
i... |
functions | int list_devices(struct seq_file *s, void *data)
{
struct pci_dev *pdev = NULL;
u16 vendor, device, devclass, speed;
bool pass = false;
int ret = 0;
for_each_pci_dev(pdev) {
pass = true;
ret = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
if (ret) {
pass = false;
break;
} |
functions | int apply_link_speed(struct seq_file *s, void *data)
{
bool pass = false;
struct tegra_pcie *pcie = (struct tegra_pcie *)(s->private);
seq_printf(s, "Changing link speed to %s... ",
(is_gen2_speed) ? "Gen2" : "Gen1");
pass = tegra_pcie_link_speed(pcie, is_gen2_speed);
if (pass)
seq_printf(s, "Done\n");
else... |
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