type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
defines | #define PCIE2_RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD (0x1FF << 1) |
defines |
#define NV_PCIE2_RP_RX_HDR_LIMIT 0x00000E00 |
defines | #define PCIE2_RP_RX_HDR_LIMIT_PW_MASK (0xFF00) |
defines | #define PCIE2_RP_RX_HDR_LIMIT_PW (0x0E << 8) |
defines |
#define NV_PCIE2_RP_TX_HDR_LIMIT 0x00000E08 |
defines | #define PCIE2_RP_TX_HDR_LIMIT_NPT_0 32 |
defines | #define PCIE2_RP_TX_HDR_LIMIT_NPT_1 4 |
defines |
#define NV_PCIE2_RP_TIMEOUT0 0x00000E24 |
defines | #define PCIE2_RP_TIMEOUT0_PAD_PWRUP_MASK (0xFF) |
defines | #define PCIE2_RP_TIMEOUT0_PAD_PWRUP (0xA) |
defines | #define PCIE2_RP_TIMEOUT0_PAD_PWRUP_CM_MASK (0xFFFF00) |
defines | #define PCIE2_RP_TIMEOUT0_PAD_PWRUP_CM (0x180 << 8) |
defines | #define PCIE2_RP_TIMEOUT0_PAD_SPDCHNG_GEN2_MASK (0xFF << 24) |
defines | #define PCIE2_RP_TIMEOUT0_PAD_SPDCHNG_GEN2 (0xA << 24) |
defines |
#define NV_PCIE2_RP_TIMEOUT1 0x00000E28 |
defines | #define PCIE2_RP_TIMEOUT1_RCVRY_SPD_SUCCESS_EIDLE_MASK (0xFF << 16) |
defines | #define PCIE2_RP_TIMEOUT1_RCVRY_SPD_SUCCESS_EIDLE (0x10 << 16) |
defines | #define PCIE2_RP_TIMEOUT1_RCVRY_SPD_UNSUCCESS_EIDLE_MASK (0xFF << 24) |
defines | #define PCIE2_RP_TIMEOUT1_RCVRY_SPD_UNSUCCESS_EIDLE (0x74 << 24) |
defines |
#define NV_PCIE2_RP_LTSSM_DBGREG 0x00000E44 |
defines | #define PCIE2_RP_LTSSM_DBGREG_LINKFSM15 (1 << 15) |
defines | #define PCIE2_RP_LTSSM_DBGREG_LINKFSM16 (1 << 16) |
defines | #define PCIE2_RP_LTSSM_DBGREG_LINKFSM17 (1 << 17) |
defines |
#define NV_PCIE2_RP_XP_REF 0x00000F30 |
defines | #define PCIE2_RP_XP_REF_MICROSECOND_LIMIT_MASK (0xFF) |
defines | #define PCIE2_RP_XP_REF_MICROSECOND_LIMIT (0x14) |
defines | #define PCIE2_RP_XP_REF_MICROSECOND_ENABLE (1 << 8) |
defines | #define PCIE2_RP_XP_REF_CPL_TO_OVERRIDE (1 << 13) |
defines | #define PCIE2_RP_XP_REF_CPL_TO_CUSTOM_VALUE_MASK (0x1FFFF << 14) |
defines | #define PCIE2_RP_XP_REF_CPL_TO_CUSTOM_VALUE (0x1770 << 14) |
defines |
#define NV_PCIE2_RP_PRIV_MISC 0x00000FE0 |
defines | #define PCIE2_RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) |
defines | #define PCIE2_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) |
defines | #define PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD (0xF << 16) |
defines | #define PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE (1 << 23) |
defines | #define PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xF << 24) |
defines | #define PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31) |
defines |
#define NV_PCIE2_RP_VEND_XP1 0x00000F04 |
defines | #define NV_PCIE2_RP_VEND_XP2 0x00000F08 |
defines | #define NV_PCIE2_RP_VEND_XP_LINK_PVT_CTL_L1_ASPM_SUPPORT (1 << 21) |
defines | #define NV_PCIE2_RP_VEND_XP1_RNCTRL_MAXWIDTH_MASK (0x3F << 0) |
defines | #define NV_PCIE2_RP_VEND_XP1_RNCTRL_EN (1 << 7) |
defines |
#define NV_PCIE2_RP_VEND_CTL0 0x00000F44 |
defines | #define PCIE2_RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xF << 12) |
defines | #define PCIE2_RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) |
defines |
#define NV_PCIE2_RP_VEND_CTL1 0x00000F48 |
defines | #define PCIE2_RP_VEND_CTL1_ERPT (1 << 13) |
defines |
#define NV_PCIE2_RP_VEND_XP_BIST 0x00000F4C |
defines | #define PCIE2_RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) |
defines |
#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN 0x00000F50 |
defines | #define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_L1_EN (1 << 0) |
defines | #define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC_EN (1 << 1) |
defines | #define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED_EN (1 << 2) |
defines | #define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_L1_CLKREQ_EN (1 << 15) |
defines | #define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1PP (3 << 5) |
defines | #define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1P (2 << 3) |
defines | #define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1PP (3 << 3) |
defines | #define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_CLKREQ_L1P (2 << 16) |
defines | #define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_CLKREQ_L1PP (3 << 16) |
defines |
#define NV_PCIE2_RP_PRIV_XP_RX_L0S_ENTRY_COUNT 0x00000F8C |
defines | #define NV_PCIE2_RP_PRIV_XP_TX_L0S_ENTRY_COUNT 0x00000F90 |
defines | #define NV_PCIE2_RP_PRIV_XP_TX_L1_ENTRY_COUNT 0x00000F94 |
defines | #define NV_PCIE2_RP_LTR_REP_VAL 0x00000C10 |
defines | #define NV_PCIE2_RP_L1_1_ENTRY_COUNT 0x00000C14 |
defines | #define PCIE2_RP_L1_1_ENTRY_COUNT_RESET (1 << 31) |
defines | #define NV_PCIE2_RP_L1_2_ENTRY_COUNT 0x00000C18 |
defines | #define PCIE2_RP_L1_2_ENTRY_COUNT_RESET (1 << 31) |
defines |
#define NV_PCIE2_RP_VEND_CTL2 0x00000FA8 |
defines | #define PCIE2_RP_VEND_CTL2_PCA_ENABLE (1 << 7) |
defines |
#define NV_PCIE2_RP_PRIV_XP_CONFIG 0x00000FAC |
defines | #define NV_PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION_MASK 0x3 |
defines | #define NV_PCIE2_RP_PRIV_XP_DURATION_IN_LOW_PWR_100NS 0x00000FB0 |
defines |
#define NV_PCIE2_RP_XP_CTL_1 0x00000FEC |
defines | #define PCIE2_RP_XP_CTL_1_SPARE_BIT29 (1 << 29) |
defines |
#define NV_PCIE2_RP_L1_PM_SUBSTATES_CYA 0x00000C00 |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_CYA_CM_RTIME_MASK (0xFF << 8) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_CYA_CM_RTIME_SHIFT (8) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_CYA_T_PWRN_SCL_MASK (0x3 << 16) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_CYA_T_PWRN_SCL_SHIFT (16) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_CYA_T_PWRN_VAL_MASK (0xF8 << 19) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_CYA_T_PWRN_VAL_SHIFT (19) |
defines |
#define NV_PCIE2_RP_L1_PM_SUBSTATES_1_CYA 0x00000C04 |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_1_CYA_PWR_OFF_DLY_MASK (0x1FFF) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_1_CYA_PWR_OFF_DLY (0x26) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_1_CYA_CLKREQ_ASSERTED_DLY_MASK (0x1FF << 13) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_1_CYA_CLKREQ_ASSERTED_DLY (0x27 << 13) |
defines |
#define NV_PCIE2_RP_L1_PM_SUBSTATES_2_CYA 0x00000C08 |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_2_CYA_T_L1_2_DLY_MASK (0x1FFF) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_2_CYA_T_L1_2_DLY (0x4D) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_2_CYA_MICROSECOND_MASK (0xFF << 13) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_2_CYA_MICROSECOND (0x13 << 13) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_2_CYA_MICROSECOND_COMP_MASK (0xF << 21) |
defines | #define PCIE2_RP_L1_PM_SUBSTATES_2_CYA_MICROSECOND_COMP (0x2 << 21) |
defines |
#define PCIE2_RP_L1_PM_SS_CONTROL 0x00000148 |
defines | #define PCIE2_RP_L1_PM_SS_CONTROL_ASPM_L11_ENABLE 0x00000008 |
defines | #define PCIE2_RP_L1_PM_SS_CONTROL_ASPM_L12_ENABLE 0x00000004 |
defines |
#define TEGRA_PCIE_MSELECT_CLK_204 204000000 |
defines | #define TEGRA_PCIE_MSELECT_CLK_408 408000000 |
defines | #define TEGRA_PCIE_XCLK_500 500000000 |
defines | #define TEGRA_PCIE_XCLK_250 250000000 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.