qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compilation.order

.\src\alu\ALU.v
.\src\data_memory\DataMemory.v
.\src\instruction_memory\InstructionMemory.v
.\src\register_file\RegisterFile.v
.\src\control_unit\ControlUnit.v
.\src\integration\parameter.v
.\src\integration\ClockGenerator.v
.\src\integration\PipelineProcessor.v
.\src\stages\IFStage.v
.\src\stages\MEMStage.v
.\src\stages\EXEStage.v
.\src\stages\IDStage.v
.\src\register\MEM_2_WB.v
.\src\register\EXE_2_MEM.v
.\src\register\ID_2_EXE.v
.\src\register\IF_2_ID.v
.\src\utilities\mux.v
.\src\utilities\Extender.v
.\src\utilities\Compare.v