data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | linux-arm-kernel | Hi,
This series creates an enum to represent the output color format as an
enum instead of a bitmask, and consolidate the HDMI helpers to use the
new enum.
This should make Nicolas' work easier.
It has been build tested, and passes kunit tests.
Let me know what you think,
Maxime
---
Changes in v2:
- Add missing co... | null | null | null | [PATCH v2 00/14] drm: Create drm_output_color_format enum | Now that all users of DRM_COLOR_FORMAT_* defines have been converted to
the new enum, we can get rid of those defines.
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
---
include/drm/drm_connector.h | 5 -----
1 file changed, 5 deletions(-)
diff --git a/include/drm/drm... | {
"author": "Maxime Ripard <mripard@kernel.org>",
"date": "Fri, 27 Feb 2026 14:59:57 +0100",
"is_openbsd": false,
"thread_id": "20260227-drm-rework-color-formats-v2-13-8bd278e2af9d@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Hi,
This series creates an enum to represent the output color format as an
enum instead of a bitmask, and consolidate the HDMI helpers to use the
new enum.
This should make Nicolas' work easier.
It has been build tested, and passes kunit tests.
Let me know what you think,
Maxime
---
Changes in v2:
- Add missing co... | null | null | null | [PATCH v2 00/14] drm: Create drm_output_color_format enum | The hdmi_colorspace enum was defined to represent the colorspace value
of the HDMI infoframes. It was later used by some HDMI drivers to
express the output format they should be setting up.
During the introduction of the HDMI helpers, it then was used to
represent it in the drm_connector_hdmi_state structure.
However... | {
"author": "Maxime Ripard <mripard@kernel.org>",
"date": "Fri, 27 Feb 2026 14:59:58 +0100",
"is_openbsd": false,
"thread_id": "20260227-drm-rework-color-formats-v2-13-8bd278e2af9d@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | From: eillon <yezhenyu2@huawei.com>
HDBSS is enabled via an ioctl from userspace (e.g. QEMU) at the start of
migration. This feature is only supported in VHE mode.
Initially, S2 PTEs doesn't contain the DBM attribute. During migration,
write faults are handled by user_mem_abort, which relaxes permissions
and adds the... | null | null | null | [PATCH v3 4/5] KVM: arm64: Enable HDBSS support and handle HDBSSF events | From: eillon <yezhenyu2@huawei.com>
This patch adds support to set the DBM (Dirty Bit Modifier) attribute
in S2 PTE during user_mem_abort(). This bit, introduced in ARMv8.1,
enables hardware to automatically promote write-clean pages to write-dirty.
This prevents the guest from being trapped in EL2 due to missing writ... | {
"author": "Tian Zheng <zhengtian10@huawei.com>",
"date": "Wed, 25 Feb 2026 12:04:18 +0800",
"is_openbsd": false,
"thread_id": "20260225040421.2683931-1-zhengtian10@huawei.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | From: eillon <yezhenyu2@huawei.com>
HDBSS is enabled via an ioctl from userspace (e.g. QEMU) at the start of
migration. This feature is only supported in VHE mode.
Initially, S2 PTEs doesn't contain the DBM attribute. During migration,
write faults are handled by user_mem_abort, which relaxes permissions
and adds the... | null | null | null | [PATCH v3 4/5] KVM: arm64: Enable HDBSS support and handle HDBSSF events | A new ioctl (KVM_CAP_ARM_HW_DIRTY_STATE_TRACK) provides a mechanism for
userspace to configure the HDBSS buffer size during live migration,
enabling hardware-assisted dirty page tracking.
Signed-off-by: eillon <yezhenyu2@huawei.com>
Signed-off-by: Tian Zheng <zhengtian10@huawei.com>
---
Documentation/virt/kvm/api.rst... | {
"author": "Tian Zheng <zhengtian10@huawei.com>",
"date": "Wed, 25 Feb 2026 12:04:21 +0800",
"is_openbsd": false,
"thread_id": "20260225040421.2683931-1-zhengtian10@huawei.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | From: eillon <yezhenyu2@huawei.com>
HDBSS is enabled via an ioctl from userspace (e.g. QEMU) at the start of
migration. This feature is only supported in VHE mode.
Initially, S2 PTEs doesn't contain the DBM attribute. During migration,
write faults are handled by user_mem_abort, which relaxes permissions
and adds the... | null | null | null | [PATCH v3 4/5] KVM: arm64: Enable HDBSS support and handle HDBSSF events | This series of patches add support to the Hardware Dirty state tracking
Structure(HDBSS) feature, which is introduced by the ARM architecture
in the DDI0601(ID121123) version.
The HDBSS feature is an extension to the architecture that enhances
tracking translation table descriptors' dirty state, identified as
FEAT_HDB... | {
"author": "Tian Zheng <zhengtian10@huawei.com>",
"date": "Wed, 25 Feb 2026 12:04:16 +0800",
"is_openbsd": false,
"thread_id": "20260225040421.2683931-1-zhengtian10@huawei.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | From: eillon <yezhenyu2@huawei.com>
HDBSS is enabled via an ioctl from userspace (e.g. QEMU) at the start of
migration. This feature is only supported in VHE mode.
Initially, S2 PTEs doesn't contain the DBM attribute. During migration,
write faults are handled by user_mem_abort, which relaxes permissions
and adds the... | null | null | null | [PATCH v3 4/5] KVM: arm64: Enable HDBSS support and handle HDBSSF events | From: eillon <yezhenyu2@huawei.com>
The ARM architecture added the HDBSS feature and descriptions of
related registers (HDBSSBR/HDBSSPROD) in the DDI0601(ID121123) version,
add them to Linux.
Signed-off-by: eillon <yezhenyu2@huawei.com>
Signed-off-by: Tian Zheng <zhengtian10@huawei.com>
---
arch/arm64/include/asm/es... | {
"author": "Tian Zheng <zhengtian10@huawei.com>",
"date": "Wed, 25 Feb 2026 12:04:17 +0800",
"is_openbsd": false,
"thread_id": "20260225040421.2683931-1-zhengtian10@huawei.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | From: eillon <yezhenyu2@huawei.com>
HDBSS is enabled via an ioctl from userspace (e.g. QEMU) at the start of
migration. This feature is only supported in VHE mode.
Initially, S2 PTEs doesn't contain the DBM attribute. During migration,
write faults are handled by user_mem_abort, which relaxes permissions
and adds the... | null | null | null | [PATCH v3 4/5] KVM: arm64: Enable HDBSS support and handle HDBSSF events | From: eillon <yezhenyu2@huawei.com>
Armv9.5 introduces the Hardware Dirty Bit State Structure (HDBSS) feature,
indicated by ID_AA64MMFR1_EL1.HAFDBS == 0b0100. A CPU capability is added
to notify the user of the feature.
Add KVM_CAP_ARM_HW_DIRTY_STATE_TRACK ioctl and basic framework for
ARM64 HDBSS support. Since the ... | {
"author": "Tian Zheng <zhengtian10@huawei.com>",
"date": "Wed, 25 Feb 2026 12:04:19 +0800",
"is_openbsd": false,
"thread_id": "20260225040421.2683931-1-zhengtian10@huawei.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | From: eillon <yezhenyu2@huawei.com>
HDBSS is enabled via an ioctl from userspace (e.g. QEMU) at the start of
migration. This feature is only supported in VHE mode.
Initially, S2 PTEs doesn't contain the DBM attribute. During migration,
write faults are handled by user_mem_abort, which relaxes permissions
and adds the... | null | null | null | [PATCH v3 4/5] KVM: arm64: Enable HDBSS support and handle HDBSSF events | Hi Tian, eillon,
On Wed, Feb 25, 2026 at 12:04:20PM +0800, Tian Zheng wrote:
I wonder if it would not be better just to use the feature if available,
instead of needing to have userspace enabling it.
That way we have to actually take a fault for every write you do after
migration starts.
What if, instead, we put... | {
"author": "Leonardo Bras <leo.bras@arm.com>",
"date": "Wed, 25 Feb 2026 17:46:58 +0000",
"is_openbsd": false,
"thread_id": "20260225040421.2683931-1-zhengtian10@huawei.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | From: eillon <yezhenyu2@huawei.com>
HDBSS is enabled via an ioctl from userspace (e.g. QEMU) at the start of
migration. This feature is only supported in VHE mode.
Initially, S2 PTEs doesn't contain the DBM attribute. During migration,
write faults are handled by user_mem_abort, which relaxes permissions
and adds the... | null | null | null | [PATCH v3 4/5] KVM: arm64: Enable HDBSS support and handle HDBSSF events | On 2/26/2026 1:46 AM, Leonardo Bras wrote:
I agree. If we decide to make HDBSS automatically enabled, then
userspace would no longer need an explicit ioctl to turn it on. In that
case, the only userspace‑visible control we may still need is a
parameter to specify the HDBSS buffer size, with the kernel providing a
... | {
"author": "Tian Zheng <zhengtian10@huawei.com>",
"date": "Fri, 27 Feb 2026 18:47:25 +0800",
"is_openbsd": false,
"thread_id": "20260225040421.2683931-1-zhengtian10@huawei.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | From: eillon <yezhenyu2@huawei.com>
HDBSS is enabled via an ioctl from userspace (e.g. QEMU) at the start of
migration. This feature is only supported in VHE mode.
Initially, S2 PTEs doesn't contain the DBM attribute. During migration,
write faults are handled by user_mem_abort, which relaxes permissions
and adds the... | null | null | null | [PATCH v3 4/5] KVM: arm64: Enable HDBSS support and handle HDBSSF events | On Fri, Feb 27, 2026 at 06:47:25PM +0800, Tian Zheng wrote:
I suggest we allocate the buffers and enable HDBSS during the first step of
live migration, this way we don't need o have this memory usage during the
lifetime of the VM, and we turn on HDBSS only when needed.
Got it! Thanks for making it clear!
I would j... | {
"author": "Leonardo Bras <leo.bras@arm.com>",
"date": "Fri, 27 Feb 2026 14:10:00 +0000",
"is_openbsd": false,
"thread_id": "20260225040421.2683931-1-zhengtian10@huawei.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series cleans up the AT91 watchdog header and refactors the
sama5d4 watchdog driver.
The header reorganization introduces consistent register naming and
makes the WDDIS bit handling explicit for modern (SAM9X60, SAMA7G5,
SAM9X7) and legacy (SAMA5, AT91SAM9261) SoCs. The driver refactor
improves readability and fi... | null | null | null | [PATCH 0/3] watchdog: at91/sama5d4: header cleanup and driver refactor | From: Andrei Simion <andrei.simion@microchip.com>
This patch reorganizes the header file by renaming the registers using
a general pattern also this patch simplifies the watchdog disable logic
in the at91sam9_wdt.h header by differentiating between modern
(SAM9X60, SAMA7G5, SAM9X7) and legacy (SAMA5, AT91SAM9261) chip... | {
"author": "Balakrishnan Sambath <balakrishnan.s@microchip.com>",
"date": "Fri, 27 Feb 2026 13:01:14 +0530",
"is_openbsd": false,
"thread_id": "2026022708054233bc5648@mail.local.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series cleans up the AT91 watchdog header and refactors the
sama5d4 watchdog driver.
The header reorganization introduces consistent register naming and
makes the WDDIS bit handling explicit for modern (SAM9X60, SAMA7G5,
SAM9X7) and legacy (SAMA5, AT91SAM9261) SoCs. The driver refactor
improves readability and fi... | null | null | null | [PATCH 0/3] watchdog: at91/sama5d4: header cleanup and driver refactor | Replace AT91_WDT_WDDIS with AT91_WDT_WDDIS_LEGACY to match the updated
bit definition naming.
Signed-off-by: Balakrishnan Sambath <balakrishnan.s@microchip.com>
---
drivers/watchdog/at91sam9_wdt.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/wat... | {
"author": "Balakrishnan Sambath <balakrishnan.s@microchip.com>",
"date": "Fri, 27 Feb 2026 13:01:16 +0530",
"is_openbsd": false,
"thread_id": "2026022708054233bc5648@mail.local.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series cleans up the AT91 watchdog header and refactors the
sama5d4 watchdog driver.
The header reorganization introduces consistent register naming and
makes the WDDIS bit handling explicit for modern (SAM9X60, SAMA7G5,
SAM9X7) and legacy (SAMA5, AT91SAM9261) SoCs. The driver refactor
improves readability and fi... | null | null | null | [PATCH 0/3] watchdog: at91/sama5d4: header cleanup and driver refactor | From: Andrei Simion <andrei.simion@microchip.com>
This patch cleans up and refactors the Atmel SAMA5D4 Watchdog Driver
to be more readable and to fixup Reset issue introduced
by commit 266da53c35fc ("watchdog: sama5d4: readout initial state").
Signed-off-by: Andrei Simion <andrei.simion@microchip.com>
[Use per-device... | {
"author": "Balakrishnan Sambath <balakrishnan.s@microchip.com>",
"date": "Fri, 27 Feb 2026 13:01:15 +0530",
"is_openbsd": false,
"thread_id": "2026022708054233bc5648@mail.local.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series cleans up the AT91 watchdog header and refactors the
sama5d4 watchdog driver.
The header reorganization introduces consistent register naming and
makes the WDDIS bit handling explicit for modern (SAM9X60, SAMA7G5,
SAM9X7) and legacy (SAMA5, AT91SAM9261) SoCs. The driver refactor
improves readability and fi... | null | null | null | [PATCH 0/3] watchdog: at91/sama5d4: header cleanup and driver refactor | On 2/26/26 23:31, Balakrishnan Sambath wrote:
That is inappropriate as a bug fix. Ther bug fix should come first,
in a form that can be backported, followed by an optional cleanup.
Guenter | {
"author": "Guenter Roeck <linux@roeck-us.net>",
"date": "Thu, 26 Feb 2026 23:44:04 -0800",
"is_openbsd": false,
"thread_id": "2026022708054233bc5648@mail.local.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series cleans up the AT91 watchdog header and refactors the
sama5d4 watchdog driver.
The header reorganization introduces consistent register naming and
makes the WDDIS bit handling explicit for modern (SAM9X60, SAMA7G5,
SAM9X7) and legacy (SAMA5, AT91SAM9261) SoCs. The driver refactor
improves readability and fi... | null | null | null | [PATCH 0/3] watchdog: at91/sama5d4: header cleanup and driver refactor | On 27/02/2026 13:01:14+0530, Balakrishnan Sambath wrote:
This is bad naming, we are going to end up with
AT91_WDT_WDDIS_LEGACY_LEGACY, AT91_WDT_WDDIS_MODERN_LEGACY and
AT91_WDT_WDDIS_MODERN next time. The proper name would use the name of
the SoC introducing the new position.
--
Alexandre Belloni, co-owner and COO,... | {
"author": "Alexandre Belloni <alexandre.belloni@bootlin.com>",
"date": "Fri, 27 Feb 2026 08:52:39 +0100",
"is_openbsd": false,
"thread_id": "2026022708054233bc5648@mail.local.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series cleans up the AT91 watchdog header and refactors the
sama5d4 watchdog driver.
The header reorganization introduces consistent register naming and
makes the WDDIS bit handling explicit for modern (SAM9X60, SAMA7G5,
SAM9X7) and legacy (SAMA5, AT91SAM9261) SoCs. The driver refactor
improves readability and fi... | null | null | null | [PATCH 0/3] watchdog: at91/sama5d4: header cleanup and driver refactor | On 27/02/2026 13:01:15+0530, Balakrishnan Sambath wrote:
Introducing this should simply remove the need for 3/3, use this instead
of AT91_WDT_WDDIS everywhere.
The previous name was better.
This is unrelated to the actual fix. This patch does to much and is
difficult to review and to backport, please separate the ... | {
"author": "Alexandre Belloni <alexandre.belloni@bootlin.com>",
"date": "Fri, 27 Feb 2026 09:05:42 +0100",
"is_openbsd": false,
"thread_id": "2026022708054233bc5648@mail.local.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Dragan Simic already had warned me of potential issues with 5.0 GT/s
speed operation in Rockchip PCIe. However, in recent interactions
with Shawn Lin from Rockchip it came to my attention there's grave
danger in the unknown errata regarding 5.0 GT/s operational speed
of their PCIe core.
Drop all code related to 5.0 GT... | null | null | null | [PATCH v4 0/4] PCI: rockchip: 5.0 GT/s speed discouraged by Rockchip | Drop the 2.5 GT/s Link Speed defines from Rockchip PCIe header
definitions. The reason is that Shawn Lin from Rockchip has
reiterated that there may be danger of "catastrophic failure"
in using their PCIe with 5.0 GT/s speeds.
While Rockchip has done so informally without issuing a proper
errata, and the particulars a... | {
"author": "Geraldo Nascimento <geraldogabriel@gmail.com>",
"date": "Fri, 27 Feb 2026 02:35:54 -0300",
"is_openbsd": false,
"thread_id": "87zf4ujf5b.fsf@posteo.net.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Dragan Simic already had warned me of potential issues with 5.0 GT/s
speed operation in Rockchip PCIe. However, in recent interactions
with Shawn Lin from Rockchip it came to my attention there's grave
danger in the unknown errata regarding 5.0 GT/s operational speed
of their PCIe core.
Drop all code related to 5.0 GT... | null | null | null | [PATCH v4 0/4] PCI: rockchip: 5.0 GT/s speed discouraged by Rockchip | Configure the core to be driven at 2.5 GT/s Link Speed and error
out on any other speed. The reason is that Shawn Lin from Rockchip
has reiterated that there may be danger of "catastrophic failure"
in using their PCIe with 5.0 GT/s speeds.
While Rockchip has done so informally without issuing a proper
errata, and the ... | {
"author": "Geraldo Nascimento <geraldogabriel@gmail.com>",
"date": "Fri, 27 Feb 2026 02:36:10 -0300",
"is_openbsd": false,
"thread_id": "87zf4ujf5b.fsf@posteo.net.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Dragan Simic already had warned me of potential issues with 5.0 GT/s
speed operation in Rockchip PCIe. However, in recent interactions
with Shawn Lin from Rockchip it came to my attention there's grave
danger in the unknown errata regarding 5.0 GT/s operational speed
of their PCIe core.
Drop all code related to 5.0 GT... | null | null | null | [PATCH v4 0/4] PCI: rockchip: 5.0 GT/s speed discouraged by Rockchip | Drop the 5.0 GT/s Link Speed retraining from Rockchip PCIe Root
Complex Mode Operation, so called host driver.
The reason is that Shawn Lin from Rockchip has reiterated that there
may be danger of "catastrophic failure" in using their PCIe with
5.0 GT/s speeds.
While Rockchip has done so informally without issuing a ... | {
"author": "Geraldo Nascimento <geraldogabriel@gmail.com>",
"date": "Fri, 27 Feb 2026 02:36:27 -0300",
"is_openbsd": false,
"thread_id": "87zf4ujf5b.fsf@posteo.net.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Dragan Simic already had warned me of potential issues with 5.0 GT/s
speed operation in Rockchip PCIe. However, in recent interactions
with Shawn Lin from Rockchip it came to my attention there's grave
danger in the unknown errata regarding 5.0 GT/s operational speed
of their PCIe core.
Drop all code related to 5.0 GT... | null | null | null | [PATCH v4 0/4] PCI: rockchip: 5.0 GT/s speed discouraged by Rockchip | Drop the 5.0 GT/s Link Speed retraining code block from Rockchip PCIe
header definitions. The reason is that Shawn Lin from Rockchip has
reiterated that there may be danger of "catastrophic failure" in
using their PCIe with 5.0 GT/s speeds.
While Rockchip has done so informally without issuing a proper
errata, and the... | {
"author": "Geraldo Nascimento <geraldogabriel@gmail.com>",
"date": "Fri, 27 Feb 2026 02:36:44 -0300",
"is_openbsd": false,
"thread_id": "87zf4ujf5b.fsf@posteo.net.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Dragan Simic already had warned me of potential issues with 5.0 GT/s
speed operation in Rockchip PCIe. However, in recent interactions
with Shawn Lin from Rockchip it came to my attention there's grave
danger in the unknown errata regarding 5.0 GT/s operational speed
of their PCIe core.
Drop all code related to 5.0 GT... | null | null | null | [PATCH v4 0/4] PCI: rockchip: 5.0 GT/s speed discouraged by Rockchip | Geraldo Nascimento <geraldogabriel@gmail.com> writes:
This commit alone won't compile right? PCIE_CLIENT_GEN_SEL_2 is still
referenced by rockchip_pcie_init_port():
if (rockchip->link_gen == 2)
rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
PCIE_CL... | {
"author": "Charalampos Mitrodimas <charmitro@posteo.net>",
"date": "Fri, 27 Feb 2026 16:53:00 +0000",
"is_openbsd": false,
"thread_id": "87zf4ujf5b.fsf@posteo.net.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Dragan Simic already had warned me of potential issues with 5.0 GT/s
speed operation in Rockchip PCIe. However, in recent interactions
with Shawn Lin from Rockchip it came to my attention there's grave
danger in the unknown errata regarding 5.0 GT/s operational speed
of their PCIe core.
Drop all code related to 5.0 GT... | null | null | null | [PATCH v4 0/4] PCI: rockchip: 5.0 GT/s speed discouraged by Rockchip | Geraldo Nascimento <geraldogabriel@gmail.com> writes:
Patch body says "header definitions" but the change is to the drivers'
source. Maybe you need to reword in a way that is clear as to what
happened?
Cheers! | {
"author": "Charalampos Mitrodimas <charmitro@posteo.net>",
"date": "Fri, 27 Feb 2026 17:00:03 +0000",
"is_openbsd": false,
"thread_id": "87zf4ujf5b.fsf@posteo.net.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Hi,
it was a known limitation, in the SCMI Clock protocol support, the lack of
dynamic allocation around per-clock rates discovery: fixed size statically
per-clock rates arrays did not scale and was increasingly a waste of memory
(see [1]).
This series aim at solving this in successive steps:
- simplify and reduce ... | null | null | null | [PATCH 00/11] SCMI Clock rates discovery rework | On Fri, 27 Feb 2026 15:32:15 +0000
Cristian Marussi <cristian.marussi@arm.com> wrote:
simplifications
Hi Cristian,
Drive by review follows. It's Friday afternoon an only a few mins to beer
o'clock :)
Does the rate ever end up different by doing this than it would if you
just dropped these short cuts? If not I wo... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Fri, 27 Feb 2026 16:50:09 +0000",
"is_openbsd": false,
"thread_id": "20260227153225.2778358-8-cristian.marussi@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Hi,
it was a known limitation, in the SCMI Clock protocol support, the lack of
dynamic allocation around per-clock rates discovery: fixed size statically
per-clock rates arrays did not scale and was increasingly a waste of memory
(see [1]).
This series aim at solving this in successive steps:
- simplify and reduce ... | null | null | null | [PATCH 00/11] SCMI Clock rates discovery rework | On Fri, 27 Feb 2026 15:32:24 +0000
Cristian Marussi <cristian.marussi@arm.com> wrote:
Why? Far as I can see it's still always zero if you get here. | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Fri, 27 Feb 2026 16:53:39 +0000",
"is_openbsd": false,
"thread_id": "20260227153225.2778358-8-cristian.marussi@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | Neutron is NXP's Neural Processing Unit (NPU) and it's integrated on
the i.MX95 SoC. It is capable of running inferences on a large range
of ML models and targets edge AI applications.
Signed-off-by: Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
---
Documentation/accel/index.rst | 1 +
Documentation... | {
"author": "Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>",
"date": "Thu, 26 Feb 2026 15:40:41 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | Introduce a flag that allows a user to request non-coherent buffers
allocated via the GEM DMA helper for bidirectional use.
Keep current behaviour (DMA_TO_DEVICE mapping) as default, with no change
required for existing GEM DMA users.
While it hasn't been the case until now, some devices like NXP's Neutron
Neural Pro... | {
"author": "Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>",
"date": "Thu, 26 Feb 2026 15:40:40 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | Add the bindings for Neutron, a Neural Processing Unit from NXP.
Signed-off-by: Jiwei Fu <jiwei.fu@nxp.com>
Signed-off-by: Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
---
.../devicetree/bindings/npu/nxp,imx95-neutron.yaml | 95 ++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/Documentatio... | {
"author": "Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>",
"date": "Thu, 26 Feb 2026 15:40:42 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | Add a driver for the Neutron Neural Processing Unit from NXP.
Neutron NPU provides machine learning (ML) acceleration for edge AI
applications. Neutron is integrated on NXP SoCs such as the i.MX95.
More information can be found under Documentation/accel/neutron.
For now introduce basic functionalities only: device pr... | {
"author": "Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>",
"date": "Thu, 26 Feb 2026 15:40:43 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | The driver communicates with the Neutron firmware via eight
register-backed mailboxes. A subset of the mailbox registers are
used to pass commands from driver to Neutron, while the rest are
written by Neutron firmware with status/ack info.
Signed-off-by: Jiwei Fu <jiwei.fu@nxp.com>
Signed-off-by: Ioana Ciocoi-Radulesc... | {
"author": "Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>",
"date": "Thu, 26 Feb 2026 15:40:45 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | Expose the Neutron firmware log via debugfs interface. The log resides
in internal device memory.
Signed-off-by: Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
---
drivers/accel/neutron/Makefile | 2 +
drivers/accel/neutron/neutron_debugfs.c | 34 ++++++++++++++++
drivers/accel/neutron/neutron_debugfs.... | {
"author": "Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>",
"date": "Thu, 26 Feb 2026 15:40:47 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | Add the following IOCTLs:
- CREATE_BO - for creating a new buffer object and passing BO info
back to user
- SYNC_BO - for explicit DMA sync operations on the BO memory, since
Neutron isn't guaranteed to be cache coherent. User controls which
portions of the buffer memory to sync and the direction.
The Neutron device r... | {
"author": "Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>",
"date": "Thu, 26 Feb 2026 15:40:44 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | Neutron can execute a single job at a time. For now, only inference
jobs are supported. Each job has exactly one BO associated with it.
When submitting a job, user also provides a syncobj handle on which it
will wait for job completion.
We use the DRM GPU scheduler for job management. Large part of the job
submission... | {
"author": "Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>",
"date": "Thu, 26 Feb 2026 15:40:46 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | Add the node for Neutron NPU. Also add a reserved memory region
for allocating Neutron buffers, which have a 1MB alignment
constraint.
Signed-off-by: Jiwei Fu <jiwei.fu@nxp.com>
Signed-off-by: Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx95.dtsi | 28 +++++++++++++++++++++++... | {
"author": "Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>",
"date": "Thu, 26 Feb 2026 15:40:48 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | On 2/26/26 14:40, Ioana Ciocoi-Radulescu wrote:
I've just pushed a patch set to drm-misc-next which makes the fence_lock superflous in most cases. Just provide NULL as lock when calling to dma_fence_init().
Not mandatory but you might also want to forward that as error to your dma_fence, see dma_fence_set_error().
... | {
"author": "=?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>",
"date": "Thu, 26 Feb 2026 15:59:49 +0100",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | On Thu, Feb 26, 2026 at 03:40:42PM +0200, Ioana Ciocoi-Radulescu wrote:
You are the author and submitter. What did Jiwei do?
clocks should be done as reg is, with the descriptions in the !-names
property. Not really keen on the names either, these are all npu clocks
so the npu prefix is odd.
Additionally, why is th... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 18:20:44 +0000",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | Hi Ioana,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f]
url: https://github.com/intel-lab-lkp/linux/commits/Ioana-Ciocoi-Radulescu/drm-gem-dma-Add-flag-for-bidirectional-mapping-of-non-coherent-GEM-DMA-buffers/20260226-221222
base: ... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Fri, 27 Feb 2026 05:15:49 +0800",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | On 2/26/26 20:20, Conor Dooley wrote:
[..]
The only dts nodes I could find using accel subsystem are from rockhip. And they use npu@
e.g:
» rknn_core_0: npu@fdab0000 {
» » compatible = "rockchip,rk3588-rknn-core";
Also, Ethos-U64 introduced by Rob with [1] is using npu@.
So, I think we should go w... | {
"author": "Daniel Baluta <daniel.baluta@oss.nxp.com>",
"date": "Fri, 27 Feb 2026 08:45:29 +0200",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | On 26/02/2026 14:40, Ioana Ciocoi-Radulescu wrote:
A nit, subject: drop second/last, redundant "bindings for". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
Why is this flex... | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 27 Feb 2026 08:06:20 +0100",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Introduce a new accel driver for the Neutron Neural Processing Unit
(NPU), along with associated dt-bindings and DTS node.
The first patch extends the GEM DMA helper APIs to allow bidirectional
mapping of non-coherent DMA buffers. While not part of the Neutron
driver, it's a prerequisite allowing us to use the GEM DMA... | null | null | null | [PATCH 0/9] accel: New driver for NXP's Neutron NPU | On Fri, Feb 27, 2026 at 08:45:29AM +0200, Daniel Baluta wrote:
accelerator, npu, makes no difference to me, so sure. | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Fri, 27 Feb 2026 09:04:01 +0000",
"is_openbsd": false,
"thread_id": "20260227-shakable-mummified-ba7bb54e0e05@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | On a heterogeneous arm64 system, KVM's PMU emulation is based on the
features of a single host PMU instance. When a vCPU is migrated to a
pCPU with an incompatible PMU, counters such as PMCCNTR_EL0 stop
incrementing.
Although this behavior is permitted by the architecture, Windows does
not handle it gracefully and may... | null | null | null | [PATCH v3 0/2] KVM: arm64: PMU: Use multiple host PMUs | Assert the following:
- KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY is unset at initialization.
- KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY can be set.
- Setting KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY for the first time
after setting an event filter results in EBUSY.
- KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY can be set ag... | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Wed, 25 Feb 2026 13:31:16 +0900",
"is_openbsd": false,
"thread_id": "20260225-hybrid-v3-0-46e8fe220880@rsg.ci.i.u-tokyo.ac.jp.mbox.gz"
} |
lkml_critique | linux-arm-kernel | On a heterogeneous arm64 system, KVM's PMU emulation is based on the
features of a single host PMU instance. When a vCPU is migrated to a
pCPU with an incompatible PMU, counters such as PMCCNTR_EL0 stop
incrementing.
Although this behavior is permitted by the architecture, Windows does
not handle it gracefully and may... | null | null | null | [PATCH v3 0/2] KVM: arm64: PMU: Use multiple host PMUs | On a heterogeneous arm64 system, KVM's PMU emulation is based on the
features of a single host PMU instance. When a vCPU is migrated to a
pCPU with an incompatible PMU, counters such as PMCCNTR_EL0 stop
incrementing.
Although this behavior is permitted by the architecture, Windows does
not handle it gracefully and may... | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Wed, 25 Feb 2026 13:31:15 +0900",
"is_openbsd": false,
"thread_id": "20260225-hybrid-v3-0-46e8fe220880@rsg.ci.i.u-tokyo.ac.jp.mbox.gz"
} |
lkml_critique | linux-arm-kernel | On a heterogeneous arm64 system, KVM's PMU emulation is based on the
features of a single host PMU instance. When a vCPU is migrated to a
pCPU with an incompatible PMU, counters such as PMCCNTR_EL0 stop
incrementing.
Although this behavior is permitted by the architecture, Windows does
not handle it gracefully and may... | null | null | null | [PATCH v3 0/2] KVM: arm64: PMU: Use multiple host PMUs | Hi Akihiko,
On Wed, Feb 25, 2026 at 01:31:15PM +0900, Akihiko Odaki wrote:
We only need to set the request if the vCPU has migrated to a different
PMU implementation, no?
My strong preference would be to squash the migration handling into
kvm_vcpu_reload_pmu(). It is already reprogramming PMU events in
response to ... | {
"author": "Oliver Upton <oupton@kernel.org>",
"date": "Thu, 26 Feb 2026 03:54:42 -0800",
"is_openbsd": false,
"thread_id": "20260225-hybrid-v3-0-46e8fe220880@rsg.ci.i.u-tokyo.ac.jp.mbox.gz"
} |
lkml_critique | linux-arm-kernel | On a heterogeneous arm64 system, KVM's PMU emulation is based on the
features of a single host PMU instance. When a vCPU is migrated to a
pCPU with an incompatible PMU, counters such as PMCCNTR_EL0 stop
incrementing.
Although this behavior is permitted by the architecture, Windows does
not handle it gracefully and may... | null | null | null | [PATCH v3 0/2] KVM: arm64: PMU: Use multiple host PMUs | On 2026/02/26 20:54, Oliver Upton wrote:
Indeed. I was too lazy to implement such a check since it won't affect
performance unless the new feature is requested, but having one may be
still nice.
Can you share a reason for that?
In terms of complexity, I don't think it will help reducing complexity
since the only... | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Thu, 26 Feb 2026 23:43:21 +0900",
"is_openbsd": false,
"thread_id": "20260225-hybrid-v3-0-46e8fe220880@rsg.ci.i.u-tokyo.ac.jp.mbox.gz"
} |
lkml_critique | linux-arm-kernel | On a heterogeneous arm64 system, KVM's PMU emulation is based on the
features of a single host PMU instance. When a vCPU is migrated to a
pCPU with an incompatible PMU, counters such as PMCCNTR_EL0 stop
incrementing.
Although this behavior is permitted by the architecture, Windows does
not handle it gracefully and may... | null | null | null | [PATCH v3 0/2] KVM: arm64: PMU: Use multiple host PMUs | On 2026/02/26 23:43, Akihiko Odaki wrote:
I think I misunderstood what you meant. Letting
perf_event_create_kernel_counter() to figure out what a PMU to use may
be a good idea. I'll give a try with the next version. | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Thu, 26 Feb 2026 23:47:54 +0900",
"is_openbsd": false,
"thread_id": "20260225-hybrid-v3-0-46e8fe220880@rsg.ci.i.u-tokyo.ac.jp.mbox.gz"
} |
lkml_critique | linux-arm-kernel | On a heterogeneous arm64 system, KVM's PMU emulation is based on the
features of a single host PMU instance. When a vCPU is migrated to a
pCPU with an incompatible PMU, counters such as PMCCNTR_EL0 stop
incrementing.
Although this behavior is permitted by the architecture, Windows does
not handle it gracefully and may... | null | null | null | [PATCH v3 0/2] KVM: arm64: PMU: Use multiple host PMUs | On Thu, Feb 26, 2026 at 11:47:54PM +0900, Akihiko Odaki wrote:
I'd definitely like to see this.
I prefer it in terms of code organization. We should have a single
helper that refreshes the backing perf events when something has
globally changed for the vPMU.
Besides this, "create" is confusing since the vPMU has al... | {
"author": "Oliver Upton <oupton@kernel.org>",
"date": "Thu, 26 Feb 2026 15:05:26 -0800",
"is_openbsd": false,
"thread_id": "20260225-hybrid-v3-0-46e8fe220880@rsg.ci.i.u-tokyo.ac.jp.mbox.gz"
} |
lkml_critique | linux-arm-kernel | On a heterogeneous arm64 system, KVM's PMU emulation is based on the
features of a single host PMU instance. When a vCPU is migrated to a
pCPU with an incompatible PMU, counters such as PMCCNTR_EL0 stop
incrementing.
Although this behavior is permitted by the architecture, Windows does
not handle it gracefully and may... | null | null | null | [PATCH v3 0/2] KVM: arm64: PMU: Use multiple host PMUs | On 2026/02/27 8:05, Oliver Upton wrote:
I see. I'll squash it into kvm_vcpu_reload_pmu().
I think I'm going to use it to check if the vCPU is covered by the perf
events currently enabled before requesting KVM_REQ_RELOAD_PMU.
I tried this, but unfortunately it didn't work well. Simply using
PERF_TYPE_RAW let perf... | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Fri, 27 Feb 2026 18:34:40 +0900",
"is_openbsd": false,
"thread_id": "20260225-hybrid-v3-0-46e8fe220880@rsg.ci.i.u-tokyo.ac.jp.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Perform the minimal initialization required for GICv5 support. GICv5
support can be requested with --with-gic=v5.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
Makefile.am | 7 ++
arch/aarch64/include/asm/cpu.h | 11 +++
common/gic-v5.c | 133 +++++++++++++++++++++++... | null | null | null | [BOOTWRAPPER PATCH 2/2] Add support for GICv5 | Small series adding GICv5 to the list of supported GIC
versions. Minimal implementation, just enough for Fast Models.
Thanks!
Vladimir Murzin (2):
Introduce --with-gic option
Add support for GICv5
Makefile.am | 15 +++-
arch/aarch64/include/asm/cpu.h | 11 +++
common/{gic.c => gic-v2.c} ... | {
"author": "Vladimir Murzin <vladimir.murzin@arm.com>",
"date": "Fri, 27 Feb 2026 10:20:47 +0000",
"is_openbsd": false,
"thread_id": "20260227102049.8015-2-vladimir.murzin@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Perform the minimal initialization required for GICv5 support. GICv5
support can be requested with --with-gic=v5.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
Makefile.am | 7 ++
arch/aarch64/include/asm/cpu.h | 11 +++
common/gic-v5.c | 133 +++++++++++++++++++++++... | null | null | null | [BOOTWRAPPER PATCH 2/2] Add support for GICv5 | We are about adding support for another GIC version, so introduce a
new --with-gic option to select the desired GIC version at configure
time. The default remains v2, preserving existing behavior. Howevere,
for GICv3, we replace the previous --enable-gicv3 option with
--with-gic=v3 which is backward-incompatible chang... | {
"author": "Vladimir Murzin <vladimir.murzin@arm.com>",
"date": "Fri, 27 Feb 2026 10:20:48 +0000",
"is_openbsd": false,
"thread_id": "20260227102049.8015-2-vladimir.murzin@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Perform the minimal initialization required for GICv5 support. GICv5
support can be requested with --with-gic=v5.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
Makefile.am | 7 ++
arch/aarch64/include/asm/cpu.h | 11 +++
common/gic-v5.c | 133 +++++++++++++++++++++++... | null | null | null | [BOOTWRAPPER PATCH 2/2] Add support for GICv5 | Hi!
On Fri, Feb 27, 2026 at 10:20:49AM +0000, Vladimir Murzin wrote:
What about SW_PPI (3) and NS_DB_PPI (2)? Are the left out for a reason?
Thanks,
Joey | {
"author": "Joey Gouly <joey.gouly@arm.com>",
"date": "Fri, 27 Feb 2026 11:06:26 +0000",
"is_openbsd": false,
"thread_id": "20260227102049.8015-2-vladimir.murzin@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Perform the minimal initialization required for GICv5 support. GICv5
support can be requested with --with-gic=v5.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
Makefile.am | 7 ++
arch/aarch64/include/asm/cpu.h | 11 +++
common/gic-v5.c | 133 +++++++++++++++++++++++... | null | null | null | [BOOTWRAPPER PATCH 2/2] Add support for GICv5 | Hi Joey!
On 2/27/26 11:06, Joey Gouly wrote:
[snip]
No reason, I just missed them. Thanks for catching that!
Cheers
Vladimir | {
"author": "Vladimir Murzin <vladimir.murzin@arm.com>",
"date": "Fri, 27 Feb 2026 11:19:24 +0000",
"is_openbsd": false,
"thread_id": "20260227102049.8015-2-vladimir.murzin@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Perform the minimal initialization required for GICv5 support. GICv5
support can be requested with --with-gic=v5.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
Makefile.am | 7 ++
arch/aarch64/include/asm/cpu.h | 11 +++
common/gic-v5.c | 133 +++++++++++++++++++++++... | null | null | null | [BOOTWRAPPER PATCH 2/2] Add support for GICv5 | On Fri, 2026-02-27 at 11:19 +0000, Vladimir Murzin wrote:
Hi both,
I don't fully agree here.
I think that the SW_PPI should be assigned to NS - it is a sane default
so that normal software can use it. There's no pre-defined use case for
this PPI, so it is just used however software chooses to use it. A
pote... | {
"author": "Sascha Bischoff <Sascha.Bischoff@arm.com>",
"date": "Fri, 27 Feb 2026 14:24:51 +0000",
"is_openbsd": false,
"thread_id": "20260227102049.8015-2-vladimir.murzin@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Perform the minimal initialization required for GICv5 support. GICv5
support can be requested with --with-gic=v5.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
Makefile.am | 7 ++
arch/aarch64/include/asm/cpu.h | 11 +++
common/gic-v5.c | 133 +++++++++++++++++++++++... | null | null | null | [BOOTWRAPPER PATCH 2/2] Add support for GICv5 | Hi Sascha,
On 2/27/26 14:24, Sascha Bischoff wrote:
Thanks for such detailed explanation, really appreciate that! Bootwrapper
doesn't run services in Secure world, so perhaps we can leave things as
they are and add any additional PPIs on as needed basis.
What do you reckon?
Vladimir | {
"author": "Vladimir Murzin <vladimir.murzin@arm.com>",
"date": "Fri, 27 Feb 2026 14:47:28 +0000",
"is_openbsd": false,
"thread_id": "20260227102049.8015-2-vladimir.murzin@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Patch 1 is a binding update to add missing #clock-cells, otherwise
there is CHECK_DTBS warning.
clock-controller@40410000 (fsl,imx7ulp-smc1): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
And the clock will be used for cpufreq as done in patch 2.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
C... | null | null | null | [PATCH v2 0/2] ARM: dts: Add CPU clock and OPP table for i.MX7ULP | From: Peng Fan <peng.fan@nxp.com>
The SMC1 block on i.MX7ULP is already used as a clock provider in
imx7ulp.dtsi, but the corresponding dt-binding schema does not define
the required '#clock-cells' property. This results in CHECK_DTBS schema
validation errors.
Functionally, SMC1 controls the CPU run mode configuratio... | {
"author": "\"Peng Fan (OSS)\" <peng.fan@oss.nxp.com>",
"date": "Fri, 27 Feb 2026 14:30:43 +0800",
"is_openbsd": false,
"thread_id": "20260227-incredible-eggplant-lionfish-b3a5bf@quoll.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Patch 1 is a binding update to add missing #clock-cells, otherwise
there is CHECK_DTBS warning.
clock-controller@40410000 (fsl,imx7ulp-smc1): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
And the clock will be used for cpufreq as done in patch 2.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
C... | null | null | null | [PATCH v2 0/2] ARM: dts: Add CPU clock and OPP table for i.MX7ULP | From: Peng Fan <peng.fan@nxp.com>
Add missing CPU clock definitions and operating-points-v2 table for the
Cortex-A7 on i.MX7ULP to enable proper CPU frequency scaling and
integration with the cpufreq/OPP frameworks.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi | 28 ++++++++++... | {
"author": "\"Peng Fan (OSS)\" <peng.fan@oss.nxp.com>",
"date": "Fri, 27 Feb 2026 14:30:44 +0800",
"is_openbsd": false,
"thread_id": "20260227-incredible-eggplant-lionfish-b3a5bf@quoll.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Patch 1 is a binding update to add missing #clock-cells, otherwise
there is CHECK_DTBS warning.
clock-controller@40410000 (fsl,imx7ulp-smc1): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
And the clock will be used for cpufreq as done in patch 2.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
C... | null | null | null | [PATCH v2 0/2] ARM: dts: Add CPU clock and OPP table for i.MX7ULP | On Fri, Feb 27, 2026 at 02:30:43PM +0800, Peng Fan (OSS) wrote:
This looks like a fix, especially that you make the cells required, so
missing Fixes tag.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 27 Feb 2026 10:46:48 +0100",
"is_openbsd": false,
"thread_id": "20260227-incredible-eggplant-lionfish-b3a5bf@quoll.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 07:57:40 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 07:57:41 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 07:57:42 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 07:57:43 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 07:57:45 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | This configuration option exists so "that we don't provide the symbol
when there's no possibility of there being a usable clocksource".
However it only covers __vdso_gettimeofday() and none of the other vDSO
functions which should be affected by the same circumstances.
As these are more widely used than gettimeofday() ... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 07:57:44 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality.
Add some build-time validations to make sure the architecture-specific
glue satisfies this requirement.
Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de>
---
lib/vdso/gettimeofday.c | 8 +++... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 07:57:46 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | On Fri, Feb 27, 2026, at 07:57, Thomas Weißschuh wrote:
The #ifdef was originally been added in commit 7d2aa4bb90f5 ("mips:
Fix gettimeofday() in the vdso library") as a bug fix. This may not
have been the correct fix because I don't see how it addressed the
case of a kernel with MIPS_CLOCK_VSYSCALL enabled running on... | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Fri, 27 Feb 2026 09:46:23 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | On Fri, Feb 27, 2026, at 07:57, Thomas Weißschuh wrote:
Good idea
Reviewed-by: Arnd Bergmann <arnd@arndb.de> | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Fri, 27 Feb 2026 09:49:49 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | On Fri, Feb 27, 2026, at 09:51, Arnd Bergmann wrote:
Actually, I need to revise that. I think gettimeofday() should be
guarded by CONFIG_COMPAT_32BIT_TIME for both the syscall and the
vdso. Looking back at the history, I see that we added the #ifdef
for each syscall we modified to have both time32 and time64 version.
... | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Fri, 27 Feb 2026 09:58:35 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | On Fri, Feb 27, 2026 at 09:46:23AM +0100, Arnd Bergmann wrote:
I can't make sense out of this commit. The generic vDSO automatically falls
back to the syscall if it can not handle the current clocksource.
There is no explanation *why* this should be broken on MIPS.
It works correctly on my x86 machines.
I will try to ... | {
"author": "Thomas =?utf-8?Q?Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 10:31:58 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | On Fri, Feb 27, 2026 at 09:58:35AM +0100, Arnd Bergmann wrote:
gettimeofday() is currently the only way to get the timezone of the kernel.
But I guess this is a legacy thing anyways. If you say we should drop it,
let's drop it.
Thomas | {
"author": "Thomas =?utf-8?Q?Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 10:34:31 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | On Fri, Feb 27, 2026, at 10:31, Thomas Weißschuh wrote:
Agreed, the explanation is incomplete at best. Maybe Vincenzo remembers
more details as he did the original patch.
Maybe the fallback logic didn't exist at the time of that fix?
Not sure, maybe nobody noticed the bug yet, or maybe both
vdso_gettimeofday() and... | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Fri, 27 Feb 2026 11:03:30 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | If CONFIG_COMPAT_32BIT_TIME is disabled then the vDSO should not
provide any 32-bit time related functionality. This is the intended
effect of the kconfig option and also the fallback system calls would
also not be implemented.
Currently the kconfig option does not affect the gettimeofday() syscall,
so also keep that ... | null | null | null | [PATCH 0/7] vDSO: Respect COMPAT_32BIT_TIME | On Fri, Feb 27, 2026 at 11:03:30AM +0100, Arnd Bergmann wrote:
That would be great.
It did, and as far as I can see it looks fine.
This is my suspicion.
If I mark the R4K and GIC clocksources as not vDSO compatible,
the automatic syscall fallback works correctly in my tests.
We would still have the problem that... | {
"author": "Thomas =?utf-8?Q?Wei=C3=9Fschuh?= <thomas.weissschuh@linutronix.de>",
"date": "Fri, 27 Feb 2026 11:17:27 +0100",
"is_openbsd": false,
"thread_id": "20260227-vdso-compat_32bit_time-v1-0-3f0286a7bac3@linutronix.de.mbox.gz"
} |
lkml_critique | linux-arm-kernel | There are some clocks where the rounding is managed by the hardware, and
the determine_rate() clk ops is just a noop that simply returns 0. Based
on discussions with Stephen at Linux Plumbers Conference, he suggested
adding a flag for this particular case. So let's add a new flag, and
update the clk core so that the de... | null | null | null | [PATCH 00/13] clk: add new flag CLK_ROUNDING_FW_MANAGED | On Thu, Feb 26, 2026 at 01:16:45PM -0500, Brian Masney wrote:
...
Based on a conversation in the Renesas driver change, I think we should
rename this flag to CLK_ROUNDING_NOOP. Let me know if there are any
objections, or suggestions for a better name. I'll let let this sit out
there for about a week or so before sendi... | {
"author": "Brian Masney <bmasney@redhat.com>",
"date": "Fri, 27 Feb 2026 11:38:42 -0500",
"is_openbsd": false,
"thread_id": "aaHIkpuK7AFXbeM-@redhat.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The do_sea() function defaults to using firmware-first mode, if supported.
It invoke acpi/apei/ghes ghes_notify_sea() to report and handling the SEA
error, The GHES uses a buffer to cache the most recent 4 kinds of SEA
errors. If the same kind SEA error continues to occur, GHES will skip to
reporting this SEA error and... | null | null | null | [PATCH] ACPI: APEI: Handle repeated SEA error interrupts storm scenarios | On Thu, Oct 30, 2025 at 8:13 AM Junhao He <hejunhao3@h-partners.com> wrote:
This needs a response from the APEI reviewers as per MAINTAINERS, thanks! | {
"author": "\"Rafael J. Wysocki\" <rafael@kernel.org>",
"date": "Mon, 3 Nov 2025 17:19:43 +0100",
"is_openbsd": false,
"thread_id": "9817f221-5b5f-7c25-ab94-cb04a854553a@h-partners.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The do_sea() function defaults to using firmware-first mode, if supported.
It invoke acpi/apei/ghes ghes_notify_sea() to report and handling the SEA
error, The GHES uses a buffer to cache the most recent 4 kinds of SEA
errors. If the same kind SEA error continues to occur, GHES will skip to
reporting this SEA error and... | null | null | null | [PATCH] ACPI: APEI: Handle repeated SEA error interrupts storm scenarios | 在 2025/11/4 00:19, Rafael J. Wysocki 写道:
Hi, Rafael and Junhao,
Sorry for late response, I try to reproduce the issue, it seems that
EINJ systems broken in 6.18.0-rc1+.
[ 3950.741186] CPU: 36 UID: 0 PID: 74112 Comm: einj_mem_uc Tainted: G E 6.18.0-rc1+ #227 PREEMPT(none)
[ 3950.751749] Tainted: [E]=... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Tue, 4 Nov 2025 09:32:11 +0800",
"is_openbsd": false,
"thread_id": "9817f221-5b5f-7c25-ab94-cb04a854553a@h-partners.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The do_sea() function defaults to using firmware-first mode, if supported.
It invoke acpi/apei/ghes ghes_notify_sea() to report and handling the SEA
error, The GHES uses a buffer to cache the most recent 4 kinds of SEA
errors. If the same kind SEA error continues to occur, GHES will skip to
reporting this SEA error and... | null | null | null | [PATCH] ACPI: APEI: Handle repeated SEA error interrupts storm scenarios | On 2025/11/4 9:32, Shuai Xue wrote:
Hi shuai xue,
Sorry for my late reply. Thank you for the review.
To clarify the issue:
This problem was introduced in v6.18-rc1 via a suspicious ARM64
memory mapping change [1]. I can reproduce the crash consistently
using the v6.18-rc1 kernel with this patch applied.
Crucially, t... | {
"author": "hejunhao <hejunhao3@h-partners.com>",
"date": "Fri, 27 Feb 2026 20:12:35 +0800",
"is_openbsd": false,
"thread_id": "9817f221-5b5f-7c25-ab94-cb04a854553a@h-partners.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by Ultrapower(UQSoft) as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/p... | null | null | null | [PATCH v2 0/3] board: sunxi: Add TaiqiCat (TQC) A01 | TaiqiCat (TQC) A01 is a set-top box powered by an Allwinner H6 SoC,
equipped with an AXP305 PMIC, 1GB LPDDR3 RAM, 8GB eMMC, an AP6212
WiFi/BT combo module, one 100M Ethernet port, one USB 3.0 Type-A port,
one USB 2.0 Type-A port, one Micro USB port, HDMI, SPDIF, Micro-SD, and
infrared input.
It is a blockchain-based t... | {
"author": "Jun Yan <jerrysteve1101@gmail.com>",
"date": "Fri, 27 Feb 2026 23:57:59 +0800",
"is_openbsd": false,
"thread_id": "20260227155801.211376-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by Ultrapower(UQSoft) as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/p... | null | null | null | [PATCH v2 0/3] board: sunxi: Add TaiqiCat (TQC) A01 | Beijing Ultrapower Software Co., Ltd. is a company focusing on global
mobile games, ICT services, cloud computing, and artificial intelligence
solutions.
TaiqiCat A01 is a blockchain-based terminal product launched by UQSoft
(Beijing UQSoft Interactive Technology Co., Ltd.), a wholly-owned
subsidiary of Ultrapower. It... | {
"author": "Jun Yan <jerrysteve1101@gmail.com>",
"date": "Fri, 27 Feb 2026 23:57:58 +0800",
"is_openbsd": false,
"thread_id": "20260227155801.211376-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by Ultrapower(UQSoft) as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/p... | null | null | null | [PATCH v2 0/3] board: sunxi: Add TaiqiCat (TQC) A01 | TaiqiCat (TQC) A01 is a set-top box powered by an Allwinner H6 SoC,
equipped with an AXP305 PMIC, 1GB LPDDR3 RAM, 8GB eMMC, an AP6212
WiFi/BT combo module, one 100M Ethernet port, one USB 3.0 Type-A port,
one USB 2.0 Type-A port, one Micro USB port, HDMI, SPDIF, Micro-SD, and
infrared input.
It was released by Ultrapo... | {
"author": "Jun Yan <jerrysteve1101@gmail.com>",
"date": "Fri, 27 Feb 2026 23:58:00 +0800",
"is_openbsd": false,
"thread_id": "20260227155801.211376-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Hi,
The UFS 5.0 standard was published today, introducing support for HS-G6
(23.2 Gbps per lane) through the new UniPro V3.0 interconnect layer and
M-PHY V6.0 physical layer specifications. To achieve reliable operation
at these higher speeds, UniPro V3.0 introduces TX Equalization and
Pre-Coding mechanisms that are e... | null | null | null | [PATCH 00/11] scsi: ufs: Add TX Equalization support for UFS 5.0 | Before power mode change to a target power mode, TX Equalzation Training
(EQTR) needs be done for that target power mode. In addition, before TX
EQTR we need to change the power mode to HS-G1. These cannot happen
before the vops pwr_change_notify(PRE_CHANGE) because we don't know the
negotiated target power mode yet. I... | {
"author": "Can Guo <can.guo@oss.qualcomm.com>",
"date": "Fri, 27 Feb 2026 08:07:58 -0800",
"is_openbsd": false,
"thread_id": "20260227160809.2620598-2-can.guo@oss.qualcomm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The folio_referenced() is used to test whether a folio was referenced during
reclaim. Moreover, ZONE_DEVICE folios are controlled by their device driver,
have a lifetime tied to that driver, and are never placed on the LRU list.
That means we should never try to reclaim ZONE_DEVICE folios, so add a warning
to catch thi... | null | null | null | [PATCH v2 3/6] mm: rmap: add a ZONE_DEVICE folio warning in folio_referenced() | Use the batched helper test_and_clear_young_ptes_notify() to check and clear
the young flag to improve the performance during large folio reclamation when
MGLRU is enabled.
Meanwhile, we can also support batched checking the young and dirty flag
when MGLRU walks the mm's pagetable to update the folios' generation
coun... | {
"author": "Baolin Wang <baolin.wang@linux.alibaba.com>",
"date": "Fri, 27 Feb 2026 17:44:39 +0800",
"is_openbsd": false,
"thread_id": "f84233f95f209d59c3bc9c72a757af09337f0d40.1772185080.git.baolin.wang@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The folio_referenced() is used to test whether a folio was referenced during
reclaim. Moreover, ZONE_DEVICE folios are controlled by their device driver,
have a lifetime tied to that driver, and are never placed on the LRU list.
That means we should never try to reclaim ZONE_DEVICE folios, so add a warning
to catch thi... | null | null | null | [PATCH v2 3/6] mm: rmap: add a ZONE_DEVICE folio warning in folio_referenced() | Currently, MGLRU will call ptep_test_and_clear_young_notify() to check and
clear the young flag for each PTE sequentially, which is inefficient for
large folios reclamation.
Moreover, on Arm64 architecture, which supports contiguous PTEs, the Arm64-
specific ptep_test_and_clear_young() already implements an optimizati... | {
"author": "Baolin Wang <baolin.wang@linux.alibaba.com>",
"date": "Fri, 27 Feb 2026 17:44:38 +0800",
"is_openbsd": false,
"thread_id": "f84233f95f209d59c3bc9c72a757af09337f0d40.1772185080.git.baolin.wang@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The folio_referenced() is used to test whether a folio was referenced during
reclaim. Moreover, ZONE_DEVICE folios are controlled by their device driver,
have a lifetime tied to that driver, and are never placed on the LRU list.
That means we should never try to reclaim ZONE_DEVICE folios, so add a warning
to catch thi... | null | null | null | [PATCH v2 3/6] mm: rmap: add a ZONE_DEVICE folio warning in folio_referenced() | Implement the Arm64 architecture-specific test_and_clear_young_ptes() to enable
batched checking of young flags, improving performance during large folio
reclamation when MGLRU is enabled.
While we're at it, simplify ptep_test_and_clear_young() by calling
test_and_clear_young_ptes(). Since callers guarantee that PTEs ... | {
"author": "Baolin Wang <baolin.wang@linux.alibaba.com>",
"date": "Fri, 27 Feb 2026 17:44:40 +0800",
"is_openbsd": false,
"thread_id": "f84233f95f209d59c3bc9c72a757af09337f0d40.1772185080.git.baolin.wang@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The folio_referenced() is used to test whether a folio was referenced during
reclaim. Moreover, ZONE_DEVICE folios are controlled by their device driver,
have a lifetime tied to that driver, and are never placed on the LRU list.
That means we should never try to reclaim ZONE_DEVICE folios, so add a warning
to catch thi... | null | null | null | [PATCH v2 3/6] mm: rmap: add a ZONE_DEVICE folio warning in folio_referenced() | Rename ptep/pmdp_clear_young_notify() to ptep/pmdp_test_and_clear_young_notify()
to make the function names consistent.
Suggested-by: David Hildenbrand (Arm) <david@kernel.org>
Signed-off-by: Baolin Wang <baolin.wang@linux.alibaba.com>
---
mm/internal.h | 8 ++++----
mm/vmscan.c | 8 ++++----
2 files changed, 8 ins... | {
"author": "Baolin Wang <baolin.wang@linux.alibaba.com>",
"date": "Fri, 27 Feb 2026 17:44:36 +0800",
"is_openbsd": false,
"thread_id": "f84233f95f209d59c3bc9c72a757af09337f0d40.1772185080.git.baolin.wang@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The folio_referenced() is used to test whether a folio was referenced during
reclaim. Moreover, ZONE_DEVICE folios are controlled by their device driver,
have a lifetime tied to that driver, and are never placed on the LRU list.
That means we should never try to reclaim ZONE_DEVICE folios, so add a warning
to catch thi... | null | null | null | [PATCH v2 3/6] mm: rmap: add a ZONE_DEVICE folio warning in folio_referenced() | This is a follow-up to the previous work [1], to support batched checking
of the young flag for MGLRU.
Similarly, batched checking of young flag for large folios can improve
performance during large-folio reclamation when MGLRU is enabled. I
observed noticeable performance improvements (see patch 5) on an Arm64
machin... | {
"author": "Baolin Wang <baolin.wang@linux.alibaba.com>",
"date": "Fri, 27 Feb 2026 17:44:34 +0800",
"is_openbsd": false,
"thread_id": "f84233f95f209d59c3bc9c72a757af09337f0d40.1772185080.git.baolin.wang@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The folio_referenced() is used to test whether a folio was referenced during
reclaim. Moreover, ZONE_DEVICE folios are controlled by their device driver,
have a lifetime tied to that driver, and are never placed on the LRU list.
That means we should never try to reclaim ZONE_DEVICE folios, so add a warning
to catch thi... | null | null | null | [PATCH v2 3/6] mm: rmap: add a ZONE_DEVICE folio warning in folio_referenced() | People have already complained that these *_clear_young_notify() related
macros are very ugly, so let's use inline helpers to make them more readable.
In addition, we cannot implement these inline helper functions in the
mmu_notifier.h file, because some arch-specific files will include the
mmu_notifier.h, which intro... | {
"author": "Baolin Wang <baolin.wang@linux.alibaba.com>",
"date": "Fri, 27 Feb 2026 17:44:35 +0800",
"is_openbsd": false,
"thread_id": "f84233f95f209d59c3bc9c72a757af09337f0d40.1772185080.git.baolin.wang@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Currently, the runtime_const_ptr() uses 4 instructions to move a long
imm to GP, but when ARM64_VA_BITS <= 48(which is true for android and
armbian), the top 8bits of runtime cont ptr is all '1', so we can make
use of the movn instruction to construct the imm's top 8bits and lower
16bits at the same time, thus save one... | null | null | null | [PATCH] arm64: runtime-const: save one instruction when ARM64_VA_BITS <= 48 | On Wed, Feb 25, 2026 at 10:46:13PM +0800, Jisheng Zhang wrote:
^^^^^
8 or 16?
This works as long as KASAN_{SW,HW}_TAGS is disabled, otherwise the top
byte of a pointer is not guaranteed to be 0xff. I think both
filename_init() and dcache_init() can pass tagged pointers.
You c... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Fri, 27 Feb 2026 16:34:04 +0000",
"is_openbsd": false,
"thread_id": "aaHHfCL4hdV4z9Uo@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Since Armv9.6, FEAT_LSUI introduces load/store instructions that allow
privileged code to access user memory without clearing the PSTATE.PAN bit.
Add CPU feature detection for FEAT_LSUI and enable its use
when FEAT_PAN is present so that removes the need for SW_PAN handling
when using LSUI instructions.
Signed-off-by... | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Wed, 25 Feb 2026 18:27:01 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | expose FEAT_LSUI to guest.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/kvm/sys_regs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_... | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Wed, 25 Feb 2026 18:27:02 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Add test coverage for FEAT_LSUI.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
---
tools/testing/selftests/kvm/arm64/set_id_regs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testing/selftests/kvm/arm64/set... | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Wed, 25 Feb 2026 18:27:03 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Refactor futex atomic operations using ll/sc method with
clearing PSTATE.PAN to prepare to apply FEAT_LSUI on them.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/include/asm/futex.h | 137 +++++++++++++++++++++------------
1 file changed, 87 ins... | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Wed, 25 Feb 2026 18:27:04 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Current futex atomic operations are implemented with ll/sc instructions
and clearing PSTATE.PAN.
Since Armv9.6, FEAT_LSUI supplies not only load/store instructions but
also atomic operation for user memory access in kernel it doesn't need
to clear PSTATE.PAN bit anymore.
With theses instructions some of futex atomic ... | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Wed, 25 Feb 2026 18:27:05 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | The purpose of supporting LSUI is to eliminate PAN toggling.
CPUs that support LSUI are unlikely to support a 32-bit runtime.
Since environments that support both LSUI and
a 32-bit runtimeare expected to be extremely rare,
not to emulate the SWP instruction using LSUI instructions
in order to remove PAN toggling, and i... | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Wed, 25 Feb 2026 18:27:06 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Use the CASLT instruction to swap the guest descriptor when FEAT_LSUI
is enabled, avoiding the need to clear the PAN bit.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
arch/arm64/include/asm/cpucaps.h | 2 ++
arch/arm64/include/asm/futex.h | 17 +----------------
arch/arm64/include/asm/lsui.h | 27 ++++++... | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Wed, 25 Feb 2026 18:27:07 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
Add Kconfig option entry for FEAT_LSUI.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/Kconfig | ... | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Wed, 25 Feb 2026 18:27:08 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | On Wed, 25 Feb 2026 18:27:07 +0000,
Yeoreum Yun <yeoreum.yun@arm.com> wrote:
It would make more sense to move this hunk to the first patch, where
you deal with features and capabilities, instead of having this in a
random KVM-specific patch.
Similarly, fold this into the patch that introduces FEAT_LSUI support
for f... | {
"author": "Marc Zyngier <maz@kernel.org>",
"date": "Thu, 26 Feb 2026 11:16:23 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | On 25/02/2026 18:27, Yeoreum Yun wrote:
minor nit:
You don't need the cpucap_is_possible() as it is already checked via
cpus_have_final_cap()->alternative_has_cap_unlikely()
Suzuki | {
"author": "Suzuki K Poulose <suzuki.poulose@arm.com>",
"date": "Thu, 26 Feb 2026 11:28:05 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | On Wed, Feb 25, 2026 at 06:27:07PM +0000, Yeoreum Yun wrote:
The other two flavors of this use relaxed ordering, why can't we do the
same with LSUI?
Thanks,
Oliver | {
"author": "Oliver Upton <oupton@kernel.org>",
"date": "Thu, 26 Feb 2026 03:38:30 -0800",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Hi Oliver,
Right. I've misunderstood caslt is relaxed symantic.
I should change with CAST.
Thanks!
--
Sincerely,
Yeoreum Yun | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Thu, 26 Feb 2026 13:52:45 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Hi Suzuki,
Right. It seems a little bit of redundant.
I'll remove it.
Thanks!
--
Sincerely,
Yeoreum Yun | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Thu, 26 Feb 2026 13:53:49 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Hi Marc,
Okay. But as Suzuki mention, I think it seems to be redundant.
I'll remove it.
Okay. I'll fold it into #5.
That was my origin thought but there was relevant discussion about this:
- https://lore.kernel.org/all/aW5dzb0ldp8u8Rdm@willie-the-truck/
- https://lore.kernel.org/all/aYtZfpWjRJ1r23nw@arm.com/
... | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Thu, 26 Feb 2026 14:05:39 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | On 26/02/2026 14:05, Yeoreum Yun wrote:
No, this is required and Marc is right. This hunk should be part of the
original patch that adds the cap. What I am saying is that you don't
need to explicitly call the cpucap_is_poissible() down, but it is
implicitly called by cpus_have_final_cap().
Kind regards
Suzuki | {
"author": "Suzuki K Poulose <suzuki.poulose@arm.com>",
"date": "Thu, 26 Feb 2026 14:52:47 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Since Armv9.6, FEAT_LSUI supplies the load/store instructions for
previleged level to access to access user memory without clearing
PSTATE.PAN bit.
This patchset support FEAT_LSUI and applies it mainly in
futex atomic operation and others.
This patch based on v7.0-rc1
Patch History
==============
form v13 to v14:
... | null | null | null | [PATCH v14 0/8] support FEAT_LSUI | Ah. my bad eyes, I miss alternative_has_cap_unlikely() calls
cpucap_is_poissible().
Thanks to point out this!
--
Sincerely,
Yeoreum Yun | {
"author": "Yeoreum Yun <yeoreum.yun@arm.com>",
"date": "Fri, 27 Feb 2026 08:31:16 +0000",
"is_openbsd": false,
"thread_id": "20260225182708.3225211-1-yeoreum.yun@arm.com.mbox.gz"
} |
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