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lkml_critique | linux-arm-kernel | With the introduction of the RK3588 SoC, and RK3576 afterwards, two more
register blocks have been provided for the video decoder unit.
However, the binding does not properly describe the new hardware layout,
as it breaks the convention expecting the unit address to indicate the
start of the first register range, i.e.... | null | null | null | [PATCH v4 1/3] media: dt-bindings: rockchip,vdec: Add alternative
reg-names order for RK35{76,88} | On Thu, Feb 26, 2026 at 04:56:30PM -0500, Nicolas Dufresne wrote:
I think this is the only bit that really still needs a reply, this can
be solved by adding reg-names as "required" to the existing conditional
portion of the binding. There's probably hundreds of examples if one
does a search for "then:\n.*required:" t... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Fri, 27 Feb 2026 17:18:11 +0000",
"is_openbsd": false,
"thread_id": "20260227-omission-stoic-417d7109ad4d@spud.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The Arm errata entries are in a messy sort-of-consistent-but-not order
that's awkward for actual reading, rather than specifically searching.
For the sake of sanity, order them consistently by Component (but
keeping the distinction of CPU vs. system IP) and Erratum ID.
Signed-off-by: Robin Murphy <robin.murphy@arm.com... | null | null | null | [PATCH 3/3] arm64: errata: Sort Arm entries | We have some inconsistency where multiple errata for the same component
share the same Kconfig workaround; some are one ID per line, some are
smooshed together, and some are entirely separate entries. Standardise
on the single entry, one ID per line format so that things render nice
and consistently in the HTML docs, a... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Thu, 26 Feb 2026 18:10:20 +0000",
"is_openbsd": false,
"thread_id": "aaGR-i8pIO8WYH9E@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The Arm errata entries are in a messy sort-of-consistent-but-not order
that's awkward for actual reading, rather than specifically searching.
For the sake of sanity, order them consistently by Component (but
keeping the distinction of CPU vs. system IP) and Erratum ID.
Signed-off-by: Robin Murphy <robin.murphy@arm.com... | null | null | null | [PATCH 3/3] arm64: errata: Sort Arm entries | Hi all,
As promised (well OK, it's not Monday...), here's a more comprehensive
SMMU errata update since I finally found time to pick through all the
latest SDENs in detail. Includes some bonus cleanup since I despair at
just adding to a messy table, but that could be split up if you have a
preference for what to base ... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Thu, 26 Feb 2026 18:10:19 +0000",
"is_openbsd": false,
"thread_id": "aaGR-i8pIO8WYH9E@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The Arm errata entries are in a messy sort-of-consistent-but-not order
that's awkward for actual reading, rather than specifically searching.
For the sake of sanity, order them consistently by Component (but
keeping the distinction of CPU vs. system IP) and Erratum ID.
Signed-off-by: Robin Murphy <robin.murphy@arm.com... | null | null | null | [PATCH 3/3] arm64: errata: Sort Arm entries | MMU-700 r1p1 has subsequently fixed some of the errata for which we've
been applying the workarounds unconditionally, so we can now make those
conditional. However, there have also been some more new cases
identified where we must rely on range invalidation commands, and thus
still nominally avoid DVM being inadvertent... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Thu, 26 Feb 2026 18:10:21 +0000",
"is_openbsd": false,
"thread_id": "aaGR-i8pIO8WYH9E@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | The Arm errata entries are in a messy sort-of-consistent-but-not order
that's awkward for actual reading, rather than specifically searching.
For the sake of sanity, order them consistently by Component (but
keeping the distinction of CPU vs. system IP) and Erratum ID.
Signed-off-by: Robin Murphy <robin.murphy@arm.com... | null | null | null | [PATCH 3/3] arm64: errata: Sort Arm entries | On Thu, Feb 26, 2026 at 06:10:19PM +0000, Robin Murphy wrote:
For the errata doc changes:
Acked-by: Catalin Marinas <catalin.marinas@arm.com> | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Fri, 27 Feb 2026 12:45:46 +0000",
"is_openbsd": false,
"thread_id": "aaGR-i8pIO8WYH9E@arm.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | On 26/02/2026 15:36, Bartosz Golaszewski wrote:
This will surprise all out-of-tree non-defconfig users, because their
boards will stop working (drivers depend on ARCH_LAN969X|ARCH_SPARX5
which will be now disabled), but I like the consistency.
I guess this will go via Microchip arm64 soc tree.
Reviewed-by: Krzysztof... | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Thu, 26 Feb 2026 15:49:06 +0100",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | On Thu, Feb 26, 2026 at 3:49 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
I'm not following, ARCH_SPARX5 remains enabled in defconfig and
ARCH_LAN969X was already disabled by default.
I think this should be picked up directly into the ARM SoC tree to
avoid conflicts later into the cycle.
Bartosz | {
"author": "Bartosz Golaszewski <brgl@kernel.org>",
"date": "Fri, 27 Feb 2026 09:42:26 +0100",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | On Fri, Feb 27, 2026, at 09:42, Bartosz Golaszewski wrote:
Your patch to the in-kernel defconfig is fine, but most users don't
use that but instead have their own defconfig files which they now
need to update.
Arnd | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Fri, 27 Feb 2026 09:48:43 +0100",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | On Fri, Feb 27, 2026 at 9:49 AM Arnd Bergmann <arnd@arndb.de> wrote:
Ah ok, I see. Do you want me to do:
config ARCH_SPARX5
def_bool y if ARCH_MICROCHIP
?
That should fix it, right?
Bart | {
"author": "Bartosz Golaszewski <brgl@kernel.org>",
"date": "Fri, 27 Feb 2026 09:51:45 +0100",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | On 27/02/2026 09:42, Bartosz Golaszewski wrote:
That's why I said non-defconfig.
Best regards,
Krzysztof | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 27 Feb 2026 10:19:25 +0100",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | On 27/02/2026 09:51, Bartosz Golaszewski wrote:
No, because they still won't have ARCH_MICROCHIP. The out-of-tree
person's config is for example only:
CONFIG_ARCH_SPARX5=y
now, this will be silently discarded with all the drivers depending on
it, because the ARCH_MICROCHIP is missing.
I don't think this is fixable,... | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 27 Feb 2026 10:21:25 +0100",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | On Fri, Feb 27, 2026, at 10:21, Krzysztof Kozlowski wrote:
Agreed. I remember when we split up the ethernet drivers into per-vendor
subdirectories and had to add 'default y' to each one in 88f07484ccdf
("drivers/net/ethernet/*: Enabled vendor Kconfig options"). Changing the
default to 'n' would be a regression now as... | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Fri, 27 Feb 2026 10:28:53 +0100",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | On Fri, Feb 27, 2026 at 10:28:53AM +0100, Arnd Bergmann wrote:
Here's the previous discussion when this was added not too long ago:
https://lore.kernel.org/all/20250811122053.4bfyoefln7wpz2a4@DEN-DL-M70577/
Daniel is probably the one that "needs" to answer this, I think the
lan969x is added recently enough for this t... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Fri, 27 Feb 2026 10:15:20 +0000",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | On 27/02/2026 11:15, Conor Dooley wrote:
I don't get arguments there. The policy is one ARCH per vendor, so why
exactly upstream would like to "having more granular control with
separate"? That's downstream or vendor wishlist, not upstream.
Best regards,
Krzysztof | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 27 Feb 2026 11:37:23 +0100",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/Kconfig.platforms | 10 ++++----... | null | null | null | [PATCH] arm64: Kconfig: provide a top-level switch for Microchip platforms | The out-of-tree defconfig impact is minimal for us. As Conor mentioned, lan969x
was added fairly recently, so the number of affected users should be small.
/Daniel | {
"author": "Daniel Machon <daniel.machon@microchip.com>",
"date": "Fri, 27 Feb 2026 12:17:48 +0100",
"is_openbsd": false,
"thread_id": "9599d8e4-26f5-4322-baf5-881c50a38ffe@kernel.org.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by UQsoft as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/product.html
... | null | null | null | [PATCH 0/3] board: sunxi: Add TaiqiCat A01 | Beijing UQ Interactive is a company focused on mobile game development,
global publishing, and blockchain-based cloud terminal services.
Signed-off-by: Jun Yan <jerrysteve1101@gmail.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devi... | {
"author": "Jun Yan <jerrysteve1101@gmail.com>",
"date": "Thu, 26 Feb 2026 16:48:45 +0800",
"is_openbsd": false,
"thread_id": "20260227154358.206060-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by UQsoft as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/product.html
... | null | null | null | [PATCH 0/3] board: sunxi: Add TaiqiCat A01 | TaiqiCat (TQC) A01 is a set-top box powered by an Allwinner H6 SoC,
equipped with an AXP305 PMIC, 1GB LPDDR3 RAM, 8GB eMMC, an AP6212
WiFi/BT combo module, one 100M Ethernet port, one USB 3.0 Type-A port,
one USB 2.0 Type-A port, one Micro USB port, HDMI, SPDIF, Micro-SD, and
infrared input.
It was released by UQsoft ... | {
"author": "Jun Yan <jerrysteve1101@gmail.com>",
"date": "Thu, 26 Feb 2026 16:48:46 +0800",
"is_openbsd": false,
"thread_id": "20260227154358.206060-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by UQsoft as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/product.html
... | null | null | null | [PATCH 0/3] board: sunxi: Add TaiqiCat A01 | TaiqiCat (TQC) A01 is a set-top box powered by an Allwinner H6 SoC,
equipped with an AXP305 PMIC, 1GB LPDDR3 RAM, 8GB eMMC, an AP6212
WiFi/BT combo module, one 100M Ethernet port, one USB 3.0 Type-A port,
one USB 2.0 Type-A port, one Micro USB port, HDMI, SPDIF, Micro-SD, and
infrared input.
It was released by UQsoft ... | {
"author": "Jun Yan <jerrysteve1101@gmail.com>",
"date": "Thu, 26 Feb 2026 16:48:47 +0800",
"is_openbsd": false,
"thread_id": "20260227154358.206060-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by UQsoft as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/product.html
... | null | null | null | [PATCH 0/3] board: sunxi: Add TaiqiCat A01 | On 26/02/2026 09:48, Jun Yan wrote:
And the domain or US stock ticker is?
Best regards,
Krzysztof | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Thu, 26 Feb 2026 10:16:17 +0100",
"is_openbsd": false,
"thread_id": "20260227154358.206060-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by UQsoft as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/product.html
... | null | null | null | [PATCH 0/3] board: sunxi: Add TaiqiCat A01 | On 26/02/2026 09:48, Jun Yan wrote:
This name and footer at that page suggests name "ultrapower" not "uqsoft".
Best regards,
Krzysztof | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Thu, 26 Feb 2026 10:17:29 +0100",
"is_openbsd": false,
"thread_id": "20260227154358.206060-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by UQsoft as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/product.html
... | null | null | null | [PATCH 0/3] board: sunxi: Add TaiqiCat A01 | UQSoft (Beijing UQSOFT Interactive Technology Co., Ltd.) is a wholly-owned subsidiary of
Ultrapower (Beijing Ultrapower Software Co., Ltd.).
TaiqiCat A01 was released by UQSoft, with its product homepage[1] hosted on Ultrapower's
official website[2].
It should be noted that UQSoft's official website is no longer op... | {
"author": "Jun Yan <jerrysteve1101@gmail.com>",
"date": "Thu, 26 Feb 2026 23:27:02 +0800",
"is_openbsd": false,
"thread_id": "20260227154358.206060-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | This series adds support for the TaiqiCat (TQC) A01 —
a set-top box based on the Allwinner H6 SoC.
Originally released by UQsoft as a blockchain terminal,
the device has been discontinued and is no longer officially
supported.
https://web.archive.org/web/20190409213228/https://tq.ultrapower.com.cn/product.html
... | null | null | null | [PATCH 0/3] board: sunxi: Add TaiqiCat A01 | On Thu, Feb 26, 2026 at 11:27:02PM +0800, Jun Yan wrote:
Yes, please use ultrapower in such case. You can mention all this in the
vendor-prefix patch.
Best regards,
Krzysztof | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 27 Feb 2026 11:40:17 +0100",
"is_openbsd": false,
"thread_id": "20260227154358.206060-1-jerrysteve1101@gmail.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Hi All
This has been in the pipeline for a while, but I've finally cleaned
up our HEVC decoder driver to be in a shape to upstream.
John Cox has done almost all of the work under contract to Raspberry
Pi, and I'm largely just doing the process of patch curation and
sending.
Thanks
Dave
v4l2-compliance 1.33.0-5448,... | null | null | null | [PATCH v5 0/6] Raspberry Pi HEVC decoder driver | From: John Cox <john.cox@raspberrypi.com>
Clarify exactly what bit_size and data_byte_offset mean when there are
multiple slices in the bitstream data.
Signed-off-by: John Cox <john.cox@raspberrypi.com>
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
---
Documentation/userspace-api/media/v4l/ext-ctrls... | {
"author": "Dave Stevenson <dave.stevenson@raspberrypi.com>",
"date": "Fri, 27 Feb 2026 17:19:06 +0000",
"is_openbsd": false,
"thread_id": "20260227-media-rpi-hevc-dec-v5-1-9bb3fc1816de@raspberrypi.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Hi All
This has been in the pipeline for a while, but I've finally cleaned
up our HEVC decoder driver to be in a shape to upstream.
John Cox has done almost all of the work under contract to Raspberry
Pi, and I'm largely just doing the process of patch curation and
sending.
Thanks
Dave
v4l2-compliance 1.33.0-5448,... | null | null | null | [PATCH v5 0/6] Raspberry Pi HEVC decoder driver | The Raspberry Pi HEVC decoder uses a tiled format based on
columns for 8 and 10 bit YUV images, so document them as
NV12MT_COL128 and NV12MT_10_COL128.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
---
.../userspace-api/media/v4l/pixfmt-yuv-planar.rst | 42 ++++++++++++++++++++++
1 file changed, 42 ... | {
"author": "Dave Stevenson <dave.stevenson@raspberrypi.com>",
"date": "Fri, 27 Feb 2026 17:19:07 +0000",
"is_openbsd": false,
"thread_id": "20260227-media-rpi-hevc-dec-v5-1-9bb3fc1816de@raspberrypi.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Hi All
This has been in the pipeline for a while, but I've finally cleaned
up our HEVC decoder driver to be in a shape to upstream.
John Cox has done almost all of the work under contract to Raspberry
Pi, and I'm largely just doing the process of patch curation and
sending.
Thanks
Dave
v4l2-compliance 1.33.0-5448,... | null | null | null | [PATCH v5 0/6] Raspberry Pi HEVC decoder driver | Add V4L2_PIXFMT_NV12MT_COL128 and V4L2_PIXFMT_NV12MT_10_COL128
to describe the Raspberry Pi HEVC decoder NV12 multiplanar formats.
NV12MT_COL128 has been added to v4l2_format_info.
NV12MT_10_COL128 has not as the block width is not a power of 2,
but the framework uses ALIGN with the value.
Signed-off-by: Dave Stevens... | {
"author": "Dave Stevenson <dave.stevenson@raspberrypi.com>",
"date": "Fri, 27 Feb 2026 17:19:08 +0000",
"is_openbsd": false,
"thread_id": "20260227-media-rpi-hevc-dec-v5-1-9bb3fc1816de@raspberrypi.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Hi All
This has been in the pipeline for a while, but I've finally cleaned
up our HEVC decoder driver to be in a shape to upstream.
John Cox has done almost all of the work under contract to Raspberry
Pi, and I'm largely just doing the process of patch curation and
sending.
Thanks
Dave
v4l2-compliance 1.33.0-5448,... | null | null | null | [PATCH v5 0/6] Raspberry Pi HEVC decoder driver | Adds a binding for the HEVC decoder IP owned by Raspberry Pi.
Instantiations of the decoder IP can currently be found in
the Broadcom BCM2711 and BCM2712 SoCs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
---
.../bindings/media/raspb... | {
"author": "Dave Stevenson <dave.stevenson@raspberrypi.com>",
"date": "Fri, 27 Feb 2026 17:19:09 +0000",
"is_openbsd": false,
"thread_id": "20260227-media-rpi-hevc-dec-v5-1-9bb3fc1816de@raspberrypi.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | Hi All
This has been in the pipeline for a while, but I've finally cleaned
up our HEVC decoder driver to be in a shape to upstream.
John Cox has done almost all of the work under contract to Raspberry
Pi, and I'm largely just doing the process of patch curation and
sending.
Thanks
Dave
v4l2-compliance 1.33.0-5448,... | null | null | null | [PATCH v5 0/6] Raspberry Pi HEVC decoder driver | Add the configuration information for the HEVC decoder.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
---
arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi | 4 ++++
arch/arm/boot/dts/broadcom/bcm2711.dtsi | 9 +++++++++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/broadcom/bcm2711... | {
"author": "Dave Stevenson <dave.stevenson@raspberrypi.com>",
"date": "Fri, 27 Feb 2026 17:19:11 +0000",
"is_openbsd": false,
"thread_id": "20260227-media-rpi-hevc-dec-v5-1-9bb3fc1816de@raspberrypi.com.mbox.gz"
} |
lkml_critique | linux-arm-kernel | MT7621 also has compatible T-PHY which attached to the XHCI interface.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
drivers/phy/mediatek/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index ba6461350..fa69df3f1 100644
... | null | null | null | [PATCH] phy: mediatek: allow building T-PHY driver for MT7621 MIPS SoC | Il 19/02/26 13:53, Shiji Yang ha scritto:
MT7621 seems to be a bit special among the mips/ralink platforms, so I agree.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | {
"author": "AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>",
"date": "Mon, 23 Feb 2026 14:47:09 +0100",
"is_openbsd": false,
"thread_id": "20260227172607.e5x3izmhzwf6tfka@skbuf.mbox.gz"
} |
lkml_critique | linux-arm-kernel | MT7621 also has compatible T-PHY which attached to the XHCI interface.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
drivers/phy/mediatek/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index ba6461350..fa69df3f1 100644
... | null | null | null | [PATCH] phy: mediatek: allow building T-PHY driver for MT7621 MIPS SoC | On Mon, Feb 23, 2026 at 02:47:09PM +0100, AngeloGioacchino Del Regno wrote:
I wanted to see for myself, but I didn't find it.
arch/mips/boot/dts/ralink/mt7621.dtsi:
usb: usb@1e1c0000 {
compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
reg = <0x1e1c0000 0x1000
0x1e1d0700 0x0100>;
reg-names = "... | {
"author": "Vladimir Oltean <olteanv@gmail.com>",
"date": "Fri, 27 Feb 2026 19:26:07 +0200",
"is_openbsd": false,
"thread_id": "20260227172607.e5x3izmhzwf6tfka@skbuf.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is r... | null | null | null | [PATCH net-next v2 1/8] riscv: dts: microchip: add tsu clock to macb on mpfs | From: Conor Dooley <conor.dooley@microchip.com>
Hey folks,
After doing some debugging of broken tsu/ptp support on mpfs, I've come
up with some very rfc patches that I'd like opinions on - particularly
because they impact a bunch of platforms that I have no access to at all
and have no idea how they work. The at91 pl... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 11:03:15 +0000",
"is_openbsd": false,
"thread_id": "20260226-snowshoe-amusable-6716d4ddea11@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is r... | null | null | null | [PATCH net-next v2 1/8] riscv: dts: microchip: add tsu clock to macb on mpfs | From: Conor Dooley <conor.dooley@microchip.com>
Calling this structure macb_default_usrio is misleading, I believe, as
it implies that it should be used if your platform has nothing special
to do in usrio. Since usrio is platform dependant, the default here is
probably for each usrio to do nothing, with the macb docum... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 11:03:17 +0000",
"is_openbsd": false,
"thread_id": "20260226-snowshoe-amusable-6716d4ddea11@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is r... | null | null | null | [PATCH net-next v2 1/8] riscv: dts: microchip: add tsu clock to macb on mpfs | From: Conor Dooley <conor.dooley@microchip.com>
USRIO is disabled on this platform, having a pointer to a usrio config
structure doesn't actually do anything other than look weird.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/net/ethernet/cadence/macb_main.c | 2 +-
1 file changed, 1 insertio... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 11:03:18 +0000",
"is_openbsd": false,
"thread_id": "20260226-snowshoe-amusable-6716d4ddea11@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is r... | null | null | null | [PATCH net-next v2 1/8] riscv: dts: microchip: add tsu clock to macb on mpfs | From: Conor Dooley <conor.dooley@microchip.com>
The GEM IP has two methods for modifying the ptp timer. The first of
these, named "increment mode", relies on software controlling the timer
by setting tsu_timer_incr and tsu_timer_incr_sub_nsec and performing
once-off adjustments via the tsu_timer_adjust register. This ... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 11:03:19 +0000",
"is_openbsd": false,
"thread_id": "20260226-snowshoe-amusable-6716d4ddea11@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is r... | null | null | null | [PATCH net-next v2 1/8] riscv: dts: microchip: add tsu clock to macb on mpfs | From: Conor Dooley <conor.dooley@microchip.com>
The ptp portion of this driver controls the tsu's timer using the
controls for "increment mode", which is not compatible with the hardware
trying to control it via the gem_tsu_inc_ctrl and gem_tsu_ms inputs in
"timer adjust mode". Abort probe if the property signalling t... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 11:03:20 +0000",
"is_openbsd": false,
"thread_id": "20260226-snowshoe-amusable-6716d4ddea11@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is r... | null | null | null | [PATCH net-next v2 1/8] riscv: dts: microchip: add tsu clock to macb on mpfs | From: Conor Dooley <conor.dooley@microchip.com>
On mpfs the driver needs to make sure the tsu clock source is not the
fabric, as this requires that the hardware is in Timer Adjust mode,
which is not compatible with the linux driver trying to control the
hardware. It is unlikely that this will be set, as the peripheral... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 11:03:21 +0000",
"is_openbsd": false,
"thread_id": "20260226-snowshoe-amusable-6716d4ddea11@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is r... | null | null | null | [PATCH net-next v2 1/8] riscv: dts: microchip: add tsu clock to macb on mpfs | From: Conor Dooley <conor.dooley@microchip.com>
The Candence GEM IP has a configuration parameter which determines the
source of the clock used for the timestamp unit (if it is enabled),
switching it between using the pclk and a dedicated input.
When ptp support was added to the macb driver, a new tsu_clk was added
t... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 11:03:22 +0000",
"is_openbsd": false,
"thread_id": "20260226-snowshoe-amusable-6716d4ddea11@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is r... | null | null | null | [PATCH net-next v2 1/8] riscv: dts: microchip: add tsu clock to macb on mpfs | From: Conor Dooley <conor.dooley@microchip.com>
tsu_clk is grabbed during probe, so doesn't need to be re-grabbed here.
pclk is mandatory, probe will fail if it is err/NULL, so there's no need
to check it here or have a !pclk 3rd arm. Simplify gem_get_tsu_rate() to
account for these facts.
Signed-off-by: Conor Dooley... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 11:03:23 +0000",
"is_openbsd": false,
"thread_id": "20260226-snowshoe-amusable-6716d4ddea11@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is r... | null | null | null | [PATCH net-next v2 1/8] riscv: dts: microchip: add tsu clock to macb on mpfs | _______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 11:09:35 +0000",
"is_openbsd": false,
"thread_id": "20260226-snowshoe-amusable-6716d4ddea11@spud.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Allow the driver to use DMA phandle args a... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Tue, 20 Jan 2026 09:37:04 +0800",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | The DMA controller on CV1800B needs to use the DMA phandle args
as the channel number instead of hardware handshake number, so
add a new compatible for the DMA controller on CV1800B.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 1 +
1 file change... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Tue, 20 Jan 2026 09:37:03 +0800",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | Change the DMA controller compatible to the sophgo,cv1800b-axi-dma,
which supports setting DMA channel number in DMA phandle args.
Fixes: 514951a81a5e ("riscv: dts: sophgo: cv18xx: add DMA controller")
Reported-by: Anton D. Stavinskii <stavinsky@gmail.com>
Closes: https://github.com/sophgo/linux/issues/9
Signed-off-by... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Tue, 20 Jan 2026 09:37:05 +0800",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | _______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Tue, 20 Jan 2026 19:56:50 +0000",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | On Tue, Jan 20, 2026 at 09:37:04AM +0800, Inochi Amaoto wrote:
Reviewed-by: Frank Li <Frank.Li@nxp.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Thu, 29 Jan 2026 17:36:03 -0500",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | On 20-01-26, 09:37, Inochi Amaoto wrote:
Applied this manually, please check if that is okay after push
--
~Vinod
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Vinod Koul <vkoul@kernel.org>",
"date": "Wed, 25 Feb 2026 16:00:04 +0530",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | On Wed, Feb 25, 2026 at 04:00:04PM +0530, Vinod Koul wrote:
Hi Vinod,
I have send a new version for v7.0-rc1.
https://lore.kernel.org/all/20260225104042.1138901-1-inochiama@gmail.com
Can you try it?
Regards,
Inochi
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infrade... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Wed, 25 Feb 2026 18:43:42 +0800",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | On Tue, 20 Jan 2026 09:37:02 +0800, Inochi Amaoto wrote:
Applied, thanks!
[1/3] dt-bindings: dma: snps,dw-axi-dmac: Add CV1800B compatible
commit: 5eda5f42d2fee87127b568206a9fcc07a2f6eab6
[2/3] dmaengine: dw-axi-dmac: Add support for CV1800B DMA
commit: 02a380ea7ed2d737a42693d7957ec8c33a92d9fd
Best regar... | {
"author": "Vinod Koul <vkoul@kernel.org>",
"date": "Wed, 25 Feb 2026 16:54:13 +0530",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | On Wed, Feb 25, 2026 at 04:54:13PM +0530, Vinod Koul wrote:
Hi, Vinod
I guess you applied the version 4, but replied to the version 3?
Regards,
Inochi
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Thu, 26 Feb 2026 06:13:25 +0800",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v3 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | On 26-02-26, 06:13, Inochi Amaoto wrote:
Nope, I had already picked 3. so reply went on that.
--
~Vinod
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Vinod Koul <vkoul@kernel.org>",
"date": "Thu, 26 Feb 2026 12:35:50 +0530",
"is_openbsd": false,
"thread_id": "20260120013706.436742-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | The crash memory alloc, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
handling them in the crash core would eliminate a lot of duplication, so
do them in the common code.
To achieve the above goal, three architecture-specific functions are
intr... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Tue, 24 Feb 2026 16:53:39 +0800",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | The crash memory exclude of crashk_res and crashk_cma memory on powerpc
are almost identical to the generic crash_exclude_core_ranges().
By introducing the architecture-specific arch_crash_exclude_mem_range()
function with a default implementation of crash_exclude_mem_range(),
and using crash_exclude_mem_range_guarded... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Tue, 24 Feb 2026 16:53:40 +0800",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | The crash memory allocation, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
This patch set handle them in crash core in a general way, which eliminate
a lot of duplication code.
And add support for crashkernel CMA reservation for arm64 and riscv... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Tue, 24 Feb 2026 16:53:37 +0800",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | Commit 35c18f2933c5 ("Add a new optional ",cma" suffix to the
crashkernel= command line option") and commit ab475510e042 ("kdump:
implement reserve_crashkernel_cma") added CMA support for kdump
crashkernel reservation.
Crash kernel memory reservation wastes production resources if too
large, risks kdump failure if too... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Tue, 24 Feb 2026 16:53:41 +0800",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | Commit 35c18f2933c5 ("Add a new optional ",cma" suffix to the
crashkernel= command line option") and commit ab475510e042 ("kdump:
implement reserve_crashkernel_cma") added CMA support for kdump
crashkernel reservation. This allows the kernel to dynamically allocate
contiguous memory for crash dumping when needed, rathe... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Tue, 24 Feb 2026 16:53:42 +0800",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | Jinjie Ruan <ruanjinjie@huawei.com> writes:
I had gone through the generic implementation v/s the powerpc specific
remove_mem_range() implementation, when it was posted by Sourabh
separately. And it make sense to use the generic implementation in this
case, rather than keeping a duplicate powerpc specific version. S... | {
"author": "Ritesh Harjani (IBM) <ritesh.list@gmail.com>",
"date": "Wed, 25 Feb 2026 08:45:56 +0530",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | On Tue, Feb 24, 2026 at 04:53:41PM +0800, Jinjie Ruan wrote:
Why do we need to add cma ranges here? They are anyway will be excluded in
crash_exclude_core_ranges().
The same comment applies to riscv patch.
--
Sincerely yours,
Mike.
_______________________________________________
linux-riscv mailing list
linux-ris... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Wed, 25 Feb 2026 17:48:41 +0200",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | On Tue, Feb 24, 2026 at 04:53:37PM +0800, Jinjie Ruan wrote:
Overall LGTM, I had a comment about arm64 and riscv patches, but other than
that
Acked-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
--
Sincerely yours,
Mike.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.in... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Wed, 25 Feb 2026 17:50:45 +0200",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | On 2026/2/25 23:48, Mike Rapoport wrote:
Indeed, it should not be placed here. In the kexec DT code, these memory
regions need to be included in the "usable-memory-range",which is
equivalent to the x86 crash_setup_memmap_entries() function.
_______________________________________________
linux-riscv mailing list
lin... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Thu, 26 Feb 2026 11:24:45 +0800",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | On 02/24/26 at 04:53pm, Jinjie Ruan wrote:
LGTM,
Acked-by: Baoquan He <bhe@redhat.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Baoquan He <bhe@redhat.com>",
"date": "Thu, 26 Feb 2026 17:29:26 +0800",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | On 02/24/26 at 04:53pm, Jinjie Ruan wrote:
~~~~
This should be written as 'PPC', even though it's not introduced in this patch.
===
PPC PowerPC architecture is enabled.
===
Other than this nit, the overral looks good to me.
......snip...
______________________________... | {
"author": "Baoquan He <bhe@redhat.com>",
"date": "Thu, 26 Feb 2026 17:33:36 +0800",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | null | null | null | [PATCH v6 1/5] powerpc/crash: sort crash memory ranges before preparing elfcorehdr | On 2026/2/26 17:24, Baoquan He wrote:
Ack, I'll add my Signed-off-by in the next revision.
Thanks,
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Thu, 26 Feb 2026 17:35:14 +0800",
"is_openbsd": false,
"thread_id": "aaASdtAQk6ZvIK-M@MiWiFi-R3L-srv.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | From: Anshuman Khandual <anshuman.khandual@arm.com>
Replace READ_ONCE() with a standard page table accessor i.e pudp_get() that
anyways defaults into READ_ONCE() in cases where platform does not override
Link: https://lkml.kernel.org/r/20251006055214.1845342-1-anshuman.khandual@arm.com
Signed-off-by: Anshuman Khandua... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:16 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | From: Anshuman Khandual <anshuman.khandual@arm.com>
Replace READ_ONCE() with standard page table accessors i.e pxdp_get() which
anyways default into READ_ONCE() in cases where platform does not override.
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ke... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:17 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | From: Anshuman Khandual <anshuman.khandual@arm.com>
Replace READ_ONCE() with standard page table accessors i.e pxdp_get()
which anyways default into READ_ONCE() in cases where platform does not
override. Also convert ptep_get_lockless() into ptep_get() as well.
Link: https://lkml.kernel.org/r/20251001042502.1400726-... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:14 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Some platforms need to fix up the values when reading or writing page
tables. Because of this, the accessors must always be used; it is not
valid to simply dereference a pXX_t pointer.
Move these definitions up by a few lines, so they will be in scope
everywhere that currently dereferences a pXX_t pointer.
Signed-off... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:18 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | From: Anshuman Khandual <anshuman.khandual@arm.com>
Replace all READ_ONCE() with a standard page table accessors i.e
pxdp_get() that defaults into READ_ONCE() in cases where platform does not
override.
Link: https://lkml.kernel.org/r/20251007063100.2396936-1-anshuman.khandual@arm.com
Signed-off-by: Anshuman Khandual ... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:15 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Architectures may have special rules for accessing the hardware page
tables (for example, atomicity/ordering requirements), so the generic MM
code provides the pXXp_get() and set_pXX() hooks for architectures to
implement. These accessor functions are often omitted where a raw
pointer dereference is believed to be safe... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:20 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Use the semantically appropriate accessor function instead of open
coding the implementation. This will become important once these
functions start transforming the PTE value on some platforms.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v2)
Changes in v2:
- New patch for v2
ar... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:22 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | The two existing definitions are equivalent because _PAGE_MTMASK is
defined as 0 on riscv32.
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v1)
arch/riscv/include/asm/pgtable-32.h | 5 -----
arch/riscv/include/asm/pgtable-64.h | ... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:25 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | RISC-V uses the same page table entry format and has the same atomicity
requirements at all page table levels, so these setter functions use the
same underlying implementation at all levels. Checking the translation
mode to pick between two identical branches only serves to make these
functions less efficient.
Signed-... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:24 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | When the Svnapot or Svpbmt extension is not implemented, the
corresponding page table bits are reserved, and must be zero. There is
no need to show them in the ptdump output.
When the Kconfig option for an extension is disabled, we assume it is
not implemented. In that case, the kernel may provide a fallback
definitio... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:26 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Use the semantically appropriate accessor function instead of a raw
pointer dereference. This will become important once these functions
start transforming the PTE value on some platforms.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v2)
Changes in v2:
- New patch for v2
arch/ri... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:23 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Currently, Linux on RISC-V has three ways to specify the cacheability
and ordering PMAs of a page:
1) Do nothing; assume the system is entirely cache-coherent and rely on
the hardware for any ordering requirements
2) Use the page table bits specified by Svpbmt
3) Use the page table bits specified by XTheadMae
T... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:27 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Some platforms need to fix up the values when reading or writing page
tables. Because of this, the accessors must always be used; it is not
valid to simply dereference a pXX_t pointer.
Fix all of the instances of this pattern in generic code, mostly by
applying the below coccinelle semantic patch, repeated for each pa... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:19 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | ALT_FIXUP_MT() is already using ALTERNATIVE_2(), but it needs to be
extended to handle a fourth case. Add ALTERNATIVE_3(), which extends
ALTERNATIVE_2() with another block of new content.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes sinc... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:29 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | pgtable-32.h and pgtable-64.h are not usable by assembly code files, so
move all page table field definitions to pgtable-bits.h. This allows
handling more complex PTE transformations in out-of-line assembly code.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v1)
arch/riscv/include/... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:28 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Alternative assembly code may wish to use an alternate link register to
minimize the number of clobbered registers. Apply the offset fix to all
jalr (not jr) instructions, i.e. where rd is not x0.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v1)
arch/riscv/kernel/alternative.c | 4... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:30 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | DMA_DIRECT_REMAP allows the kernel to make pages coherent for DMA by
remapping them in the page tables with a different pgprot_t value. On
RISC-V, this is supported by the page-based memory type extensions
(Svpbmt and Xtheadmae). It is independent from the software cache
maintenance extensions (Zicbom and Xtheadcmo).
... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:31 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Currently, some functions such as pte_offset_map() are passed both
pointers to hardware page tables, and pointers to previously-read PMD
entries on the stack. To ensure correctness in the first case, these
functions must use the page table accessor function (pmdp_get()) to
dereference the supplied pointer. However, thi... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:21 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | EIC7700 provides a physical memory region which is a noncached alias of
normal cacheable DRAM. Declare this alias in the devicetree so Linux can
allocate noncached pages for noncoherent DMA, and M-mode firmware can
protect the noncached alias with PMPs.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
Ch... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:35 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Information about physical memory regions is needed by both the kernel
and M-mode firmware. For example, the kernel needs to know about
noncacheable aliases of cacheable memory in order to allocate coherent
memory pages for DMA. M-mode firmware needs to know about those aliases
so it can protect itself from lower-privi... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:32 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | JH7100 provides a physical memory region which is a noncached alias of
normal cacheable DRAM. Now that Linux can apply PMAs by selecting
between aliases of a physical memory region, any page of DRAM can be
marked as noncached for use with DMA, and the preallocated DMA pool is
no longer needed. This allows portable kern... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:34 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On some RISC-V platforms, RAM is mapped simultaneously to multiple
physical address ranges, with each alias having a different set of
statically-determined Physical Memory Attributes (PMAs). Software alters
the PMAs for a particular page at runtime by selecting a PFN from among
the aliases of that page's physical addre... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:33 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, 2025-11-12 at 17:45 -0800, Samuel Holland wrote:
[]
[]
Seems like a lot of matches
$ git grep -P '(?<!pte_t |p[mu4g]d_t |izeof\()\*\(?(vmf(\.|->))?(pte|p[mu4g]d)p?\b' | \
grep -v '^arch/' | wc -l
766
Is this really appropriate?
trivia:
izeof is really odd looking. I'd prefer sizeof.
___________________... | {
"author": "Joe Perches <joe@perches.com>",
"date": "Wed, 12 Nov 2025 18:21:01 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 2025-11-12 8:21 PM, Joe Perches wrote:
Other patches in this series remove 277 of these matches. But it looks like a
couple of driver systems (iommu, dm) use variables that match this pattern as
well. Limiting the check to include/ and mm/ avoids the false positives.
I agree, but my perl complains "Variable lengt... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 20:36:03 -0600",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13/11/25 7:15 am, Samuel Holland wrote:
Reviewed-by: Dev Jain <dev.jain@arm.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Dev Jain <dev.jain@arm.com>",
"date": "Thu, 13 Nov 2025 09:35:41 +0530",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hi Samuel,
kernel test robot noticed the following build errors:
[auto build test ERROR on 24172e0d79900908cf5ebf366600616d29c9b417]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/mm-ptdump-replace-READ_ONCE-with-standard-page-table-accessors/20251113-095117
base: 24172e0d79900908cf5ebf36660... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Thu, 13 Nov 2025 12:53:18 +0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hi Samuel,
kernel test robot noticed the following build errors:
[auto build test ERROR on 24172e0d79900908cf5ebf366600616d29c9b417]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/mm-ptdump-replace-READ_ONCE-with-standard-page-table-accessors/20251113-095117
base: 24172e0d79900908cf5ebf36660... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Thu, 13 Nov 2025 13:46:28 +0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hi Samuel,
kernel test robot noticed the following build errors:
[auto build test ERROR on 24172e0d79900908cf5ebf366600616d29c9b417]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/mm-ptdump-replace-READ_ONCE-with-standard-page-table-accessors/20251113-095117
base: 24172e0d79900908cf5ebf36660... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Thu, 13 Nov 2025 15:19:38 +0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13.11.25 02:45, Samuel Holland wrote:
Acked-by: David Hildenbrand (Red Hat) <david@kernel.org>
--
Cheers
David
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 13 Nov 2025 20:10:33 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13.11.25 02:45, Samuel Holland wrote:
It is not immediately clear to me from the description why that is
required. Can you summarize the core problem here, and why we have to
route everything through these accessors?
--
Cheers
David
_______________________________________________
linux-riscv mailing list
linu... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 13 Nov 2025 20:13:52 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13.11.25 03:36, Samuel Holland wrote:
That is indeed concerning.
I recall that we discussed an alternative approach with Ryan in the
past: I don't remember all the details, but essentially it was about
using separate types, such that dereferencing would not get you the type
the other functions would be expectin... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 13 Nov 2025 20:17:22 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Le 13/11/2025 à 02:45, Samuel Holland a écrit :
...
And this commit has the same problem as the series from Anshuman, see [2]:
Before the patch, as an exemple on powerpc/32 mm_find_pmd() was:
00001860 <mm_find_pmd>:
1860: 80 63 00 18 lwz r3,24(r3)
1864: 54 84 65 3a rlwinm r4,r4,12... | {
"author": "\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>",
"date": "Wed, 26 Nov 2025 12:08:19 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13/11/2025 01:45, Samuel Holland wrote:
There should absolutely never be any instances of core code directly setting an
entry at any level. This *must* always go via the arch code helpers. Did you
find any instances of this? If so, I would consider these bugs and suggest
sending as a separate bugfix patch. Bad thin... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 11:09:48 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 12:09, Ryan Roberts wrote:
We do have mm_pmd_folded()/p4d_folded() etc, could that help to sort
this out internally?
--
Cheers
David
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 13:16:35 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 13:16, David Hildenbrand (Red Hat) wrote:
Just stumbled over the reply from Christope:
https://lkml.kernel.org/r/0019d675-ce3d-4a5c-89ed-f126c45145c9@kernel.org
And wonder if we could handle that somehow directly in the pgdp_get() etc.
--
Cheers
David
_______________________________________________
l... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 13:19:00 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 01:19:00PM +0100, David Hildenbrand (Red Hat) wrote:
I find that kind of gross to be honest. Isn't the whole point of folding that we
don't have to think about it...
And we're now modifying how we do things for ppc32 specifically? Or are there
arches with fewer cobwebs on them that are actuall... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Wed, 26 Nov 2025 12:27:56 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 13:27, Lorenzo Stoakes wrote:
If we could adjust generic pgdp_get() and friends to not do a
READ_ONCE() once folded we might not have to think about that in the
callers.
Just an idea, though, not sure if that would fly the way I envision it.
--
Cheers
David
__________________________________________... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 13:35:17 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 26/11/2025 12:35, David Hildenbrand (Red Hat) wrote:
I certainly don't like the suggestion of doing the is_folded() test outside the
helper, but if we can push that logic down into pXdp_get() that would be pretty
neat. Anshuman and I did briefly play with the idea of doing a C dereference if
the level is folded and... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 13:03:42 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 01:03:42PM +0000, Ryan Roberts wrote:
[...]
You mean sth like:
static inline pmd_t pmdp_get(pmd_t *pmdp)
{
#ifdef __PAGETABLE_PMD_FOLDED
return *pmdp;
#else
return READ_ONCE(*pmdp);
#endif
}
--
Wei Yang
Help you, Help me
_______________________________________________
linux-riscv mailing... | {
"author": "Wei Yang <richard.weiyang@gmail.com>",
"date": "Wed, 26 Nov 2025 13:47:26 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 26/11/2025 13:47, Wei Yang wrote:
Yes. But I'm not convinced it's correct.
I *think* (but please correct me if I'm wrong) if the PMD is folded, the PUD and
P4D must also be folded, and you effectively have a 2 level pgtable consisting
of the PGD table and the PTE table. p4dp_get(), pudp_get() and pmdp_get() are
al... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 14:22:13 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
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