text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
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/*
*/
#pragma once
#include
#include
#include "soc/systimer_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/system_struct.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions even no... | 358 |
..) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void systimer_ll_reset_register(void)
{
SYSTEM.perip_rst_en0.systimer_rst = 1;
SYSTEM.perip_rst_en0.systimer_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
... | 358 |
hi.timer_unit_load_hi = value >> 32;
dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
}
__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
{
return dev->unit_val[counter_id].lo.timer_unit_value_lo;
}
__att... | 358 |
hi.timer_target_hi) target_val[alarm_id].lo.timer_target_lo;
}
__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
{
dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
}
__attribute__((always_inline)) static i... | 358 |
target_period;
}
__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
{
dev->comp_load[alarm_id].val = 0x01;
}
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
{
if (en... | 358 |
/*
*/
#pragma once
#include
#include "riscv/csr.h"
/*fast gpio*/
#define CSR_GPIO_OEN_USER 0x803
#define CSR_GPIO_IN_USER 0x804
#define CSR_GPIO_OUT_USER 0x805
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
{
RV_W... | 359 |
/*
*/
// The LL layer for Cache register operations
#pragma once
#include
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32c2/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE... | 360 |
Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);... | 360 |
EXTMEM_ICACHE_SHUT_DBUS : 0);
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
/**
*/
__attribute__((always_inline))
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
{
bool valid = false;
uint32_t vaddr_end = vaddr_start + le... | 360 |
/*
*/
#include
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/* This LL is currently unused for ESP32-C2 - cleanup is TODO ESP32-C2 IDF-2375 */
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
{
abort();
}
static inline void mpu_ll_set_region_rw(uint32_t addr)... | 361 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include "gpspi_flash_ll.h"
#include "spimem_flash_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
... | 362 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/assert.h"
#include "soc/periph_defs.h"
#include "soc/system_reg.h"
#include "soc/syscon_reg.h"
#include "soc/dport_access.h"
#include "soc/soc_caps.h"
#include "esp_attr.h"
static inline uint32_t periph_ll_get_clk_en_mask(p... | 363 |
= 0;
}
static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(SY... | 363 |
/*
*/
#pragma once
#include
#include
#include "hal/assert.h"
#include "hal/ecc_types.h"
#include "soc/ecc_mult_reg.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ECC_PARAM_PX = 0x0,
ECC_PARAM_PY,
ECC_PARAM_K,
} ecc_ll_param_t;
/**
*/
static inline void ecc_ll... | 364 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; ecc_ll_reset_register(__VA_ARGS__)
static inline void ecc_ll_enable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);
}
static inline void ecc_ll_disable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0)... | 364 |
/*
*/
#pragma once
#include
#include
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/clk_tree_defs.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/adc_typ... | 365 |
> 8;
uint8_t lsb = param & 0xFF;
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
}
/*
Oneshot Read
*/
/**
*/
static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bit... | 365 |
saradc_saradc_onetime_start = val;
}
/**
*/
static inline void adc_oneshot_ll_clear_event(uint32_t event_mask)
{
APB_SARADC.saradc_int_clr.val |= event_mask;
}
/**
*/
static inline bool adc_oneshot_ll_get_event(uint32_t event_mask)
{
return (APB_SARADC.saradc_int_raw.val & event_mask);
}
/**
*/
static inl... | 365 |
saradc_onetime_sample.saradc_saradc1_onetime_sample = 0;
APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0;
}
/**
*/
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
(void)adc_n;
(void)channel;
// Attenuation is for all channels... | 365 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include "soc/spi_periph.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include // For MIN/MAX
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
//NOTE: These macros are changed on ESP32-C2 for build. MODIFY these wh... | 366 |
dma_seg_trans_en = 0;
}
/**
*/
static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
{
dev->ctrl.hold_pol = pol_val;
}
/**
*/
static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
{
return (dev->cmd.usr == 0);
}
/**
*/
static inline void gpspi_flash_ll_get_buffer_d... | 366 |
hold_pol = 1;
dev->cmd.update = 1;
while (dev->cmd.update);
dev->cmd.usr = 1;
}
/**
*/
static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev)
{
// Not supported on GPSPI
}
/**
*/
static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
{
return dev->cmd.usr == 0;
}
/**
*/
static... | 366 |
val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
case SPI_FLASH_SLOWRD:
break;
case SPI_FLASH_QIO:
ctrl.fread_quad = 1;
ctrl.faddr_quad = 1;
user.fwrite_quad = 1;
break;
case SPI_FLASH_Q... | 366 |
ms_data_bitlen = bitlen - 1;
}
}
/**
*/
static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
if (bitlen) {
dev->ms_dlen.ms_data_bitlen = bitlen - 1;
}
}
/**
*/
static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8... | 366 |
0 : UINT32_MAX >> bitlen);
dev->addr = (addr addr = addr;
}
/**
*/
static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
{
dev->user.usr_dummy = dummy_n ? 1 : 0;
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
}
/**
*/
static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev,... | 366 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
{
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
WRITE_PERI_REG(RTC_CNTL_S... | 367 |
/*
*/
/
/
#pragma once
#include
#include "soc/rtc_cntl_struct.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_brownout.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void brownout_ll_enable_flash_power_down(bool enable)
{
RTCCNTL.brown_out.close_flash_ena = enable;
}
/**
*/
static inl... | 368 |
int_ena.rtc_brown_out = enable;
}
/**
*/
static inline void brownout_ll_ana_reset_enable(bool enable)
{
RTCCNTL.brown_out.ana_rst_en = enable;
}
/**
*/
__attribute__((always_inline))
static inline void brownout_ll_intr_clear(void)
{
RTCCNTL.int_clr.rtc_brown_out = 1;
}
/**
*/
static inline void brownout_l... | 368 |
/*
*/
/
/
// The LL layer for ESP32-C2 GPIO register operations
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// Get GPIO hardware instance with giving gp... | 369 |
func_sel;
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
}
/**
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num... | 369 |
procpu_int;
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
*status = 0; // Less than 32 GPIOs in ESP32-C2
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t... | 369 |
enable_w1tc = (0x1 enable_w1ts.enable_w1ts = (0x1 pin[gpio_num].pad_driver = 0;
}
/**
*/
static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].pad_driver = 1;
}
/**
*/
static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint... | 369 |
GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
}
/**
*/
static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
{
if (gpio_num func_in_sel_cfg[signal_idx].sig_in_sel = 0;
PIN_INPUT_ENABLE(IO_MUX_GP... | 369 |
val = hw->func_in_sel_cfg[in_sig_idx].val;
return (reg.sig_in_sel ? reg.func_sel : -1);
}
/**
*/
static inline void gpio_ll_force_hold_all(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
SET_PERI_REG... | 369 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "soc/timer_periph.h"
#include "soc/timer_group_struct.h"
#include "soc/pcr_struct.h"
#inc... | 370 |
wdt_en = 1;
abort();
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtconfig0.wdt_en = 0;
abort();
}
/**
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650
// return (hw->wdtconfig0.wdt_en) ?... | 370 |
wdt_stg3 = behavior;
// hw->wdtconfig5.wdt_stg3_hold = timeout;
// break;
// default:
// HAL_ASSERT(false && "unsupported WDT stage");
// break;
// }
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
abort();
}
/**
*/
FORCE_I... | 370 |
wdt_conf_update_en = 1;
abort();
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtconfig0.wdt_cpu_reset_length = length;
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_up... | 370 |
g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
// // We take care of the "read-modify-write" procedure by ourselves.
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler);
// //Config registers are updated asynchronously
// hw->wdtconfig0... | 370 |
wdt_int_ena = (enable) ? 1 : 0;
abort();
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src)
{
// TODO: [ESP32C5] IDF-8650
// uint8_t clk_id = 0;
// switch (clk_src) {
// case MWDT_CLK_SRC_XTAL:
// clk_id = 0;
// break;
// case ... | 370 |
timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en;
// }
abort();
}
#ifdef __cplusplus
}
#endif
| 370 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include // For MIN/MAX
#include
#include
#include "soc/spi_periph.h"
#include "soc/spi_mem_struct.h"
#include "soc/spi_mem_reg.h"
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#inc... | 371 |
flash_ce = 1;
}
/**
*/
static inline void spimem_flash_ll_erase_sector(spi_mem_dev_t *dev)
{
dev->ctrl.val = 0;
dev->cmd.flash_se = 1;
}
/**
*/
static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev)
{
dev->cmd.flash_be = 1;
}
/**
*/
static inline void spimem_flash_ll_suspend(spi_mem_dev_t ... | 371 |
sus_timeout_cnt = 5;
dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en;
}
/**
static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool res_check_sus_en)
{
dev->flash_sus_ctrl.sus_timeout_cnt = 5;
dev->flash_sus_ctrl.per_end_en = res_check_sus_en;
}
/**
*/
static inline void spimem_... | 371 |
flash_per_wait_en = auto_waiti;
dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti;
}
/**
*/
static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy)
{
// Not supported on this chip.
}
/**
*/
static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
{
... | 371 |
usr_dummy = 0;
spimem_flash_ll_set_buffer_data(dev, buffer, length);
dev->cmd.flash_pp = 1;
}
/**
*/
static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev, bool pe_ops)
{
uint32_t usr_pe = (pe_ops ? 0x60000 : 0x40000);
dev->cmd.val |= usr_pe;
}
/**
*/
static inline bool spimem_flash_ll_ho... | 371 |
val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
break;
case SPI_FLASH_QIO:
ctrl.fread_qio = 1;
break;
case SPI_FLASH_QOUT:
ctrl.fread_quad = 1;
break;
case SPI_FLASH_DIO:
ctrl.fread_dio = 1;
... | 371 |
usr_mosi = bitlen > 0;
dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0;
}
/**
*/
static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen)
{
dev->user.usr_command = 1;
typeof(dev->user2) user2 = {
.usr_command_value = command,
.usr_co... | 371 |
usr_dummy = dummy_n ? 1 : 0;
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
}
/**
*/
static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
{
dev->ctrl2.cs_hold_time = hold_n - 1;
dev->user.cs_hold = (hold_n > 0? 1: 0);
}
static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev... | 371 |
h`
if (clkdiv == 1) {
div_parameter = (1 ctrl.wp = level;
}
/**
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif
| 371 |
/*
*/
// The LL layer for I2C register operations
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2c_periph.h"
#include "soc/soc_caps.h"
#include "soc/i2c_struct.h"
#include "soc/pcr_struct.h"
#include "hal/i2c_types.h"
#include "soc/clk_tree_defs.h"
#include "hal/misc.h"
#ifdef... | 372 |
conf_upgate = 1;
}
/**
*/
static inline void i2c_ll_enable_bus_clock(int i2c_port, bool enable)
{
PCR.i2c[i2c_port].i2c_conf.i2c_clk_en = enable;
}
/**
*/
static inline void i2c_ll_reset_register(int i2c_port)
{
PCR.i2c[i2c_port].i2c_conf.i2c_rst_en = 1;
PCR.i2c[i2c_port].i2c_conf.i2c_rst_en = 0;
}
/**... | 372 |
scl_stop_setup_time = bus_cfg->setup - 1;
//hold
hw->scl_start_hold.scl_start_hold_time = bus_cfg->hold - 1;
hw->scl_stop_hold.scl_stop_hold_time = bus_cfg->hold - 1;
hw->to.time_out_value = bus_cfg->tout;
hw->to.time_out_en = 1;
}
/**
*/
static inline void i2c_ll_master_set_fractional_divider(i2c... | 372 |
val = mask;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
}
/**
*/
_... | 372 |
stretch_cause) {
case 0:
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
break;
case 1:
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_TX_EMPTY;
break;
case 2:
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_RX_FULL;
break;
case 3:
*stretch_cause = I2C_... | 372 |
val = cmd.val;
}
/**
*/
static inline void i2c_ll_master_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
{
hw->scl_rstart_setup.scl_rstart_setup_time = start_setup;
hw->scl_start_hold.scl_start_hold_time = start_hold - 1;
}
/**
*/
static inline void i2c_ll_master_set_stop_timing(i2c_dev_t *... | 372 |
tx_lsb_first = tx_mode;
hw->ctr.rx_lsb_first = rx_mode;
}
/**
*/
static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sda_hold)
{
*sda_hold = hw->sda_hold.sda_hold_time;
*sda_sample = hw->sda_sample.sda_sample_time;
}
/**
*/
static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t... | 372 |
trans_start = 1;
}
/**
*/
static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
{
*setup_time = hw->scl_rstart_setup.scl_rstart_setup_time;
*hold_time = hw->scl_start_hold.scl_start_hold_time + 1;
}
/**
*/
static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *set... | 372 |
fifo_addr_cfg_en = addr_wr_en;
}
/**
*/
static inline void i2c_ll_master_set_filter(i2c_dev_t *hw, uint8_t filter_num)
{
if (filter_num > 0) {
hw->filter_cfg.scl_filter_thres = filter_num;
hw->filter_cfg.sda_filter_thres = filter_num;
hw->filter_cfg.scl_filter_en = 1;
hw->filter_cf... | 372 |
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
}
/**
*/
static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_clk)
{
// src_clk : (1) for RTC_CLK, (0) for XTAL
PCR.i2c[0].i2c_sclk_conf.i2c_sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0;
}
/**
*/
stati... | 372 |
slv_tx_auto_start_en = slv_ex_auto_en;
}
/**
*/
static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev)
{
return &dev->int_status;
}
/**
*/
static inline void i2c_ll_slave_enable_scl_stretch(i2c_dev_t *dev, bool enable)
{
dev->scl_stretch_conf.slave_scl_stretch_en = enable;
}
/**
*/
_... | 372 |
2)
*/
static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int low_period, int wait_high_period)
{
hw->scl_low_period.scl_low_period = low_period;
hw->scl_high_period.scl_high_period = high_period;
hw->scl_high_period.scl_wait_high_period = wait_high_period;
}
/**
*/
static inlin... | 372 |
end_detect_int_st) {
*event = I2C_INTR_EVENT_END_DET;
} else if (int_sts.trans_complete_int_st) {
*event = I2C_INTR_EVENT_TRANS_DONE;
} else {
*event = I2C_INTR_EVENT_ERR;
}
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_ev... | 372 |
val = UINT32_MAX;
hw->int_ena.val = I2C_LL_MASTER_RX_INT;
}
/**
*/
static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT);
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_... | 372 |
scl_high_period = hight_period - 10;
hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.scl_high_period;
}
/**
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*... | 372 |
/*
*/
#pragma once
#include /* Required for NULL constant */
#include
#include
#include "hal/gdma_types.h"
#include "soc/gdma_struct.h"
#include "soc/gdma_reg.h"
#include "soc/soc_etm_source.h"
#include "soc/pcr_struct.h"
#include "soc/retention_periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GDMA_... | 373 |
raw.val;
} else {
return dev->in_intr[channel].st.val;
}
}
/**
*/
static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->in_intr[channel].ena.val |= mask;
} else {
dev->in_intr[channel].ena.val &= ~mask... | 373 |
in_conf0.in_data_burst_en = enable;
}
/**
*/
static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf0.indscr_burst_en = enable;
}
/**
*/
__attri... | 373 |
infifo_status.val & 0x02;
}
/**
*/
static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.infifo_status.infifo_cnt;
}
/**
*/
static inline ui... | 373 |
in_link.inlink_start = 1;
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_stop = 1;
}
/**
*/
__attribute__((always_inline... | 373 |
in_link.inlink_park;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.in_suc_eof_des_addr.val;
}
/**
*/
_... | 373 |
in_pri.rx_pri = prio;
}
/**
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_peri_sel.peri_in_sel = periph_id;
... | 373 |
raw.val;
} else {
return dev->out_intr[channel].st.val;
}
}
/**
*/
static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->out_intr[channel].ena.val |= mask;
} else {
dev->out_intr[channel].ena.val &= ~m... | 373 |
out_conf0.out_data_burst_en = enable;
}
/**
*/
static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.outdscr_burst_en = enable;
}
/**
*/
st... | 373 |
out_conf0.out_rst = 1;
ch->out.out_conf0.out_rst = 0;
}
/**
*/
static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.outfifo_status.val & 0x01;... | 373 |
out_push.outfifo_wdata = data;
ch->out.out_push.outfifo_push = 1;
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch-... | 373 |
out_link.outlink_restart = 1;
}
/**
*/
static inline bool gdma_ll_tx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.out_link.outlink_park;
}
/**
*/
__attribute__((always_inline))
static... | 373 |
out_pri.tx_pri = prio;
}
/**
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
{
(void)periph;
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_peri_sel.peri... | 373 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash Encryption.
#include
#include
#include "soc/hp_system_reg.h"
// #include "soc/xts_aes_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef e... | 374 |
= 0x3) {
// }
abort();
}
/**
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
// TODO: [ESP32C5] IDF-8622, IDF-8649
// REG_SET_BIT(XTS_AES_DESTROY_REG(0), XTS_AES_DESTROY);
abort();
}
/**
*/
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
{
// TODO:... | 374 |
/*
*/
// The LL layer for RTC(LP) watchdog register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/lpwdt_ll.h"
typedef lp_wdt_dev_t rwdt_dev_t;
#define RWDT_DEV_GET() &LP_WDT
#define rwdt_ll_enabl... | 375 |
/*
*/
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include "esp_attr.h"
#include "hal/misc.h"
#include "hal/uart_types.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/lp_uart_reg.h"
#include ... | 376 |
uart0_##reg_suffix, uart0_##field_suffix, (val)) \
} else { \
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \
}
#define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? \
HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, ua... | 376 |
lpperi.lp_uart_clk_sel) {
default:
case 0:
*source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST;
break;
case 1:
*source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
break;
}
}
/**
*/
static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_clk_sr... | 376 |
clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
uart_ll_update(hw);
}
/**
*/
static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable)
{
(void)hw_id;
LPPERI.clk_en.lp_uart_ck_en = enable;... | 376 |
uart0_conf.uart0_clk_en && !PCR.uart0_conf.uart0_rst_en;
case 1:
return PCR.uart1_conf.uart1_clk_en && !PCR.uart1_conf.uart1_rst_en;
case 2: // LP_UART
return LPPERI.clk_en.lp_uart_ck_en && !LPPERI.reset_en.lp_uart_reset_en;
default:
// Unknown uart port number
HAL_ASSERT(fal... | 376 |
= &LP_UART) {
UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en);
} else {
// LP_UART reset shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
abort();
}
}
/*... | 376 |
c
abort();
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
if ((hw) != &LP_UART) {
uint32_t sel_value = 0;
switch (source_clk) {
case UART_SCLK_XTAL:
sel_value = 0;
break;
case UART_SCLK_RTC:
... | 376 |
clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
if ((hw) == &LP_UART) {
abort();
} else {
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
}
#undef DIV_UP
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_de... | 376 |
val;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_clr.val = mask;
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
{
return hw->int_ena.val;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, ... | 376 |
txfifo_rst = 1;
uart_ll_update(hw);
hw->conf0_sync.txfifo_rst = 0;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
{
return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t... | 376 |
= UART_PARITY_DISABLE) {
hw->conf0_sync.parity = parity_mode & 0x1;
}
hw->conf0_sync.parity_en = (parity_mode >> 1) & 0x1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
{
if (hw->conf0_sync.parity_en) {
*parity_mode =... | 376 |
txd_brk = 1;
} else {
hw->conf0_sync.txd_brk = 0;
}
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
{
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
if (flow_ctrl & U... | 376 |
xonoff_del = 1;
hw->swfc_conf0_sync.sw_flow_con_en = 1;
hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
... | 376 |
bit_num = data_bit;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
{
hw->conf0_sync.sw_rts = level & 0x1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
{
hw->conf1.sw_dtr = leve... | 376 |
rs485rxby_tx_en = 1;
hw->conf0_sync.irda_en = 0;
hw->conf0_sync.sw_rts = 0;
hw->conf0_sync.irda_en = 0;
hw->rs485_conf_sync.dl0_en = 1;
hw->rs485_conf_sync.dl1_en = 1;
hw->rs485_conf_sync.rs485_en = 1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(u... | 376 |
dl1_en = 1;
hw->rs485_conf_sync.rs485_en = 1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
// lp_uart_dev_t has no following fields (reserved), but no harm si... | 376 |
rs485_en = 0;
hw->rs485_conf_sync.rs485tx_rx_en = 0;
hw->rs485_conf_sync.rs485rxby_tx_en = 0;
hw->conf0_sync.sw_rts = 0;
hw->conf0_sync.irda_en = 1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
... | 376 |
active_threshold + UART_LL_MIN_WAKEUP_THRESH;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
{
*data_bit = (uart_word_length_t)hw->conf0_sync.bit_num;
}
/**
*/
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
{
return ((((hw->status.txfifo_cnt... | 376 |
val = hw->conf0_sync.val;
conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0;
conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0;
conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0;
hw->conf0_... | 376 |
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