text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
< Power down RTC SLOW memory
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO re... | 303 |
< EXT0 GPIO wakeup
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only)
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup
#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only)
#define RTC_WIFI_TRIG_EN BIT(5) //!< WIFI... | 303 |
< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
uint32_t clkctl_init : 1; //!< Perform c... | 303 |
bbpll_fpu = 0, \
.cpu_waiti_clk_gate = 1, \
.cali_ocode = 0 \
}
/**
*/
void rtc_init(rtc_config_t cfg);
/**
*/
typedef struct {
uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
uint32_t enable : 1; //!< Enable VDDSDIO regulator
uint3... | 303 |
< XTAL
#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M or 320M)
#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator
/**
*/
typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscil... | 303 |
/*
*/
#pragma once
#include
#include
#include
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
//
/ THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE /
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
//
/**
*/
#define MHZ (1000000... | 304 |
< The clock from which CPU clock is derived
uint32_t source_freq_mhz; //!< Source clock frequency
uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div
uint32_t freq_mhz; //!< CPU clock frequency
} rtc_cpu_freq_config_t;
#define RTC_CLK_CAL_FRACT 19 //!< Number... | 304 |
< RTC_FAST_CLK clock source to choose
soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
uint32_t clk_rtc_clk_div : 8;
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
uint32_t slow_clk_dcap :... | 304 |
wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
.rtc_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.rtc_wait_cycles = OTHER_BLOCKS_WAIT, \
.dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
.rtc_mem_powerup_cycles = OTH... | 304 |
< Set to 1 to power down digital part in sleep
uint32_t rtc_fpu : 1; //!< Set to 1 to power down RTC memories in sleep
uint32_t cpu_fpu : 1; //!< Set to 1 to power down digital memories and CPU in sleep
uint32_t i2s_fpu : 1; //!< Set to 1 to power down I2S in sleep
uint32_t bb_fpu : 1; //!<... | 304 |
< power down RTC fast memory
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
uin... | 304 |
< circuit control parameter, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep
uint32_t deep_slp_reject : 1; ... | 304 |
< Power down Internal 8M oscillator
#define RTC_SLEEP_PD_XTAL BIT(8) //!< Power down main XTAL
//These flags are not power domains, but will affect some sleep parameters
#define RTC_SLEEP_DIG_USE_8M BIT(16)
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
#define RTC_SLEEP_NO_ULTRA_LOW ... | 304 |
< WIFI wakeup (light sleep only)
#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup
#define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup
#define RTC_BT_TRIG_EN BIT(10)... | 304 |
< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
uint32_t clkctl_init : 1; //!< Perform c... | 304 |
bbpll_fpu = 0, \
.cpu_waiti_clk_gate = 1, \
.cali_ocode = 0\
}
/**
*/
void rtc_init(rtc_config_t cfg);
/**
*/
typedef struct {
uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
uint32_t enable : 1; //!< Enable VDDSDIO regulator
uint32... | 304 |
h instead.
/**
*/
typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL
#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M or 320M)
#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 8M RTC oscillator
#define RTC_CPU_FREQ_SRC_APLL SOC... | 304 |
< 40 MHz XTAL
/* Alias of frequency related macros */
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
#define RTC_SLOW_CLK_FREQ_90K SOC_CLK_RC_SLOW_FREQ_APPROX
#define RTC_SLOW_CLK_FREQ_8MD256 SOC_CLK_RC_FAST_D256_FREQ_APPROX
#def... | 304 |
/*
*/
#pragma once
#include "sdkconfig.h"
#define MSPI_TIMING_CONFIG_NUM_MAX 32 //This should be larger than the max available timing config num
#define MSPI_TIMING_TEST_DATA_LEN 128
#define MSPI_TIMING_PSRAM_TEST_DATA_ADDR 0x80
#define MSPI_TIMING_DELAYLINE_TEST_NUMS 100
#define MSPI_TIM... | 305 |
/*
*/
#pragma once
#include
#include
#include
#include "soc/pmu_struct.h"
#include "hal/pmu_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
// FOR XTAL FORCE PU IN SLEEP
#define PMU_PD_CUR_SLEEP_ON 0
#define PMU_BIASSLP_SLEEP_ON 0
// FOR BOTH LIGHTSLEEP & DEEPSLEEP
#define PMU_PD_CUR_SLEEP_DEFAULT 1... | 306 |
h used for the PMU state machine in sleep flow*/
typedef union {
struct {
uint32_t reserved0 : 21;
uint32_t dcdc_switch_pd_en: 1;
uint32_t mem_dslp : 1;
uint32_t mem_pd_en : 1;
uint32_t reserved1 : 6;
uint32_t cnnt_pd_en : 1;
uint32_t top_pd_en : 1;... | 306 |
6 us */
#define PMU_LP_WAKEUP_DELAY_CYCLES (0)
#define PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES (30) /* Slow OSC as PMU slow clock source is about 201 us */
#define PMU_LP_ANALOG_WAIT_TARGET_CYCLES (23) /* Slow OSC as PMU slow clock source is about 154 us */
#define PMU_LP_DIGITAL_POWER_SUPPLY... | 306 |
hp_sys = { \
.dig_power = { \
.cnnt_pd_en = ((pd_flags) & PMU_SLEEP_PD_CNNT) ? 1 : 0, \
.top_pd_en = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
.... | 306 |
xtal = { \
.xpd_xtal = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \
} \
}, \
.lp_sys[PMU_M... | 306 |
xpd_lppll = 1, \
.xpd_xtal32k = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \
.xpd_rc32k = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
.xpd_fosc = 1 \
} ... | 306 |
clk_power = { \
.xpd_lppll = 0,\
.xpd_xtal32k = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \
.xpd_rc32k = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
.xpd_fosc = ((pd_flags) & PMU_SLEEP_PD_RC_FAS... | 306 |
0 : 1, \
} \
}
typedef struct {
struct {
pmu_hp_analog_t analog;
} hp_sys;
struct {
pmu_lp_analog_t analog;
} lp_sys[PMU_MODE_LP_MAX];
} pmu_sleep_analog_config_t;
#define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd... | 306 |
lp_sys[PMU_MODE_LP_ACTIVE] = { \
.analog = { \
.slp_xpd = 0, \
.slp_dbias = 0, \
.xpd = 1, \
.db... | 306 |
xpd = PMU_LP_XPD_SLEEP_DEFAULT, \
.dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT, \
.dbias = PMU_LP_DBIAS_LIGHTSLEEP_0V7 \
} \
} ... | 306 |
analog = { \
.xpd = 1, \
.dbias = 0x1a, \
.slp_xpd = 0, \
.slp_dbias = 0, \
.drv_b ... | 306 |
dbg_atten = PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT, \
.dbias = PMU_LP_DBIAS_DEEPSLEEP_0V7 \
} \
} \
}
typedef struct {
pmu_hp_param_t hp_sys;
... | 306 |
pll_stable_wait_cycle = PMU_HP_PLL_STABLE_WAIT_CYCLES \
}, \
.lp_sys = { \
.min_slp_slow_clk_cycle = PMU_LP_SLEEP_MIN_SLOW_CLK_CY... | 306 |
lp = { \
.min_slp_time_us = 450, \
.wakeup_wait_cycle = 4, \
.analog_wait_time_us = 154, \
.xtal_wait_stable_time_us = 250, \
.clk_switch_cycle = 1, \
.clk_power_on_wai... | 306 |
regdma_a2s_work_time_us = 338, \
.regdma_rf_on_work_time_us = 70, \
.regdma_rf_off_work_time_us = 23, \
.xtal_wait_stable_time_us = 250, \
.pll_wait_stable_time_us = 1 \
} \
}
#ifdef __cplusplus
}
#endi... | 306 |
/*
*/
#pragma once
#include
#include
#include
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "hal/hal_utils.h"
#ifdef __cplusplus
extern "C" {
#endif
//
/ THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE /
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
//
/*... | 307 |
< The clock from which CPU clock is derived
uint32_t source_freq_mhz; //!< Source clock frequency
hal_utils_clk_div_t div; //!< Divider, freq_mhz = SOC_ROOT_CLK freq_mhz / div
uint32_t freq_mhz; //!< CPU clock frequency
} rtc_cpu_freq_config_t;
#define RTC_CLK_CAL_FRACT 19 //!< ... | 307 |
< Internal 20MHz RC oscillator
RTC_CAL_RC_SLOW = 8, //!< Internal 150kHz RC oscillator
RTC_CAL_RC32K = 9, //!< Internal 32kHz RC oscillator, as one type of 32k clock
RTC_CAL_32K_XTAL = 10, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_LP_PLL = 11, //!< 8MHz LP_PL... | 307 |
< RC_FAST clock adjustment parameter (higher value leads to higher frequency)
uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency)
} rtc_clk_config_t;
/**
*/
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = CONFIG_XTAL_FREQ, \
... | 307 |
/*
*/
#pragma once
#include
#include
#include "esp_err.h"
#include "hal/pcnt_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct pcnt_unit_t *pcnt_unit_handle_t;
/**
*/
typedef struct pcnt_chan_t *pcnt_channel_handle_t;
/**
*/
typedef struct {
int watch_point_value; ... | 308 |
< Whether to accumulate the count value when overflows at the high/low limit */
} flags; /*!< Extra flags */
} pcnt_unit_config_t;
/**
*/
typedef struct {
int edge_gpio_num; /*!< GPIO number used by the edge signal, input mode with pull up enabled. Set to -1 if unused */
int level_gpio_num; /*!< GP... | 308 |
< Channel config flags */
} pcnt_chan_config_t;
/**
*/
typedef struct {
uint32_t max_glitch_ns; /*!< Pulse width smaller than this threshold will be treated as glitch and ignored, in the unit of ns */
} pcnt_glitch_filter_config_t;
/**
*/
esp_err_t pcnt_new_unit(const pcnt_unit_config_t *config, pcnt_unit_handl... | 308 |
< clear signal config flags */
} pcnt_clear_signal_config_t;
/**
*/
esp_err_t pcnt_unit_set_clear_signal(pcnt_unit_handle_t unit, const pcnt_clear_signal_config_t *config);
#endif
/**
*/
esp_err_t pcnt_unit_enable(pcnt_unit_handle_t unit);
/**
*/
esp_err_t pcnt_unit_disable(pcnt_unit_handle_t unit);
/**
*/
esp_... | 308 |
/*
*/
#pragma once
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#if CONFIG_IDF_TARGET_ESP32P4
#define TEST_PCNT_GPIO_A 20
#define TEST_PCNT_GPIO_B 21
#define TEST_PCNT_GPIO_Z 22
#else
#define TEST_PCNT_GPIO_A 0
#define TEST_PCNT_GPIO_B 2
#define TEST_PCNT_GPIO_Z 4
#endif
#if CONFIG_PCNT_ISR_IRAM_S... | 309 |
/*
*/
#pragma once
#include "esp_err.h"
#include "esp_openthread.h"
#include "esp_openthread_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
typedef void (*esp_openthread_task_t)(void *);
/**
esp_err_t esp_openthread_task_queue_init(const esp_openthread_platform_config_t *config);
/**
esp_err_t esp_openthrea... | 310 |
/*
*/
#pragma once
#include "sdkconfig.h"
/**
#define OPENTHREAD_CONFIG_PLATFORM_INFO CONFIG_IDF_TARGET
/**
#define OPENTHREAD_CONFIG_PLATFORM_ASSERT_MANAGEMENT 1
/**
#define OPENTHREAD_CONFIG_PLATFORM_FLASH_API_ENABLE 0
/**
*/
#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED
... | 311 |
/*
*/
#pragma once
#include
#include "esp_err.h"
#include "esp_openthread_types.h"
#include "openthread/instance.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
esp_err_t esp_openthread_radio_init(const esp_openthread_platform_config_t *config);
/**
void esp_openthread_radio_deinit(void);
/**
void esp_openthread... | 312 |
/*
*/
#pragma once
#define OT_PLAT_LOG_TAG "OPENTHREAD"
#ifndef MS_PER_S
#define MS_PER_S 1000
#endif
#ifndef US_PER_MS
#define US_PER_MS 1000
#endif
#ifndef US_PER_S
#define US_PER_S (MS_PER_S * US_PER_MS)
#endif
#define ESP_OPENTHREAD_UART_BUFFER_SIZE CONFIG_OPENTHREAD_UART_BUFFER_SIZE
| 313 |
/*
*/
#pragma once
#include "esp_err.h"
#include "esp_openthread_types.h"
#include "openthread/instance.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
esp_err_t esp_openthread_uart_init_port(const esp_openthread_uart_config_t *config);
/**
esp_err_t esp_openthread_host_cli_uart_init(const esp_openthread_platform_c... | 314 |
/*
*/
#pragma once
#include "sdkconfig.h"
/**
#define OPENTHREAD_CONFIG_PLATFORM_INFO CONFIG_IDF_TARGET
/**
#define OPENTHREAD_CONFIG_PLATFORM_ASSERT_MANAGEMENT 1
/**
#define OPENTHREAD_CONFIG_PLATFORM_FLASH_API_ENABLE 0
/**
*/
#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED
/... | 315 |
/*
*/
#include
#if CONFIG_OPENTHREAD_NCP_VENDOR_HOOK
#define SPINEL_PROP_VENDOR_ESP_SET_COORDINATOR (SPINEL_PROP_VENDOR_ESP__BEGIN + 1)
#define SPINEL_PROP_VENDOR_ESP_SET_PENDINGMODE (SPINEL_PROP_VENDOR_ESP__BEGIN + 2)
#endif
| 316 |
/*
*/
#pragma once
#include "esp_openthread.h"
#include "openthread/ip6.h"
#include "openthread/instance.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
void esp_openthread_netif_glue_update(esp_openthread_mainloop_context_t *mainloop);
/**
esp_err_t esp_openthread_netif_glue_process(otInstance *instance, const esp... | 317 |
/*
*/
#pragma once
#include
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
esp_err_t esp_openthread_state_event_init(otInstance *instance);
#ifdef __cplusplus
}
#endif
| 318 |
/*
*/
#pragma once
#include "esp_err.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_FREERTOS_USE_TICKLESS_IDLE
/**
esp_err_t esp_openthread_sleep_init(void);
/**
void esp_openthread_sleep_process(void);
/**
void esp_openthread_wakeup_process(void);
#endif
#ifdef __cplusplus
}
#en... | 319 |
/*
*/
#pragma once
#include "esp_openthread.h"
#include "esp_openthread_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
esp_err_t esp_openthread_host_rcp_spi_init(const esp_openthread_platform_config_t *config);
/**
void esp_openthread_spi_slave_deinit(void);
#ifdef __cplusplus
} /* extern "C" */
#endif
| 320 |
/*
*/
#pragma once
#include "esp_err.h"
#include "esp_openthread_types.h"
#include "openthread/error.h"
#include "openthread/instance.h"
#ifdef __cplusplus
extern "C" {
#endif
#define WORKFLOW_MAX_NAMELEN 16
/**
typedef void (*esp_openthread_update_func)(esp_openthread_mainloop_context_t *mainloop);
/**
typedef ... | 321 |
/*
*/
#pragma once
#include "esp_err.h"
#include "esp_openthread_types.h"
#include "openthread/instance.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
esp_err_t esp_openthread_alarm_init(void);
/**
*/
void esp_openthread_alarm_deinit(void);
/**
void esp_openthread_alarm_update(esp_openthread_mainloop_context_t *... | 322 |
/*
*/
#pragma once
#include "sdkconfig.h"
/**
#define OPENTHREAD_CONFIG_PLATFORM_INFO CONFIG_IDF_TARGET
/**
#define OPENTHREAD_CONFIG_PLATFORM_ASSERT_MANAGEMENT 1
/**
#define OPENTHREAD_CONFIG_PLATFORM_FLASH_API_ENABLE 0
/**
*/
#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED
... | 323 |
CONFIG_OPENTHREAD_RADIO_NATIVE
/**
#ifndef OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT
#define OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT 3
#endif
/**
#ifndef OPENTHREAD_POSIX_CONFIG_RCP_TIME_SYNC_INTERVAL
#define OPENTHREAD_POSIX_CONFIG_RCP_TIME_SYNC_INTERVAL (60 * 1000 * 1000)
#endif
#endif
/**
#def... | 323 |
/*
*/
#pragma once
/**
#ifndef OPENTHREAD_SPINEL_CONFIG_OPENTHREAD_MESSAGE_ENABLE
#define OPENTHREAD_SPINEL_CONFIG_OPENTHREAD_MESSAGE_ENABLE 0
#endif
/**
#ifndef OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT
// TZ-567: Set OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT to 3 after adding rcp failure notific... | 324 |
/*
*/
#pragma once
#include "esp_openthread.h"
#include "lwip/netdb.h"
#ifdef __cplusplus
extern "C" {
#endif
// The network data change callback sets the dns server address of index 0, while the CLI sets the dns server address of index 1.
#define OPENTHREAD_DNS_SERVER_INDEX 0
/**
esp_err_t esp_openthread_dns64_cl... | 325 |
/*
*/
#pragma once
#include "esp_err.h"
#include "esp_openthread_types.h"
#include "openthread/dataset.h"
#include "openthread/error.h"
#include "openthread/instance.h"
#include "lwip/ip_addr.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
esp_err_t esp_openthread_init(const esp_openthread_platform_config_t *init_co... | 326 |
/*
*/
#include "esp_openthread.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
void esp_openthread_cli_init(void);
/**
esp_err_t esp_openthread_cli_input(const char *line);
/**
void esp_openthread_cli_create_task(void);
#ifdef __cplusplus
}
#endif
| 327 |
/*
*/
#pragma once
#include
#include "esp_err.h"
#include "freertos/FreeRTOS.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
esp_err_t esp_openthread_lock_init(void);
/**
void esp_openthread_lock_deinit(void);
/**
bool esp_openthread_lock_acquire(TickType_t block_ticks);
/**
void esp_openthread_lock_release(voi... | 328 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include "esp_ieee802154_types.h"
#include "driver/uart.h"
#include "soc/gpio_num.h"
#define ESP_SPINEL_LOG_TAG "ESP_RADIO_SPINEL"
#define SPINEL_PROP_VENDOR_ESP_SET_COORDINATOR (SPINEL_PROP_VENDOR_ESP__BEGIN + 1) /* Vendor command for coordinat... | 329 |
*/
struct timeval timeout; /* The timeout.*/
} esp_radio_spinel_mainloop_context_t;
typedef struct {
uart_port_t port; /*!< UART port number */
uart_config_t uart_config; /*!< UART configuration, see uart_config_t docs */
gpio_num_t rx_pin; /*!< UART RX pin */
gp... | 329 |
*/
void (*transmit_done)(const uint8_t *frame, const uint8_t *ack, esp_ieee802154_frame_info_t *ack_frame_info); /* Callback for Transmit Done.*/
void (*transmit_failed)(esp_ieee802154_tx_error_t error); /* Callback for Transmit Failed.*/
void (*energy... | 329 |
*/
void (*diag_transmit_failed)(esp_ieee802154_tx_error_t error); /* Callback for Transmit Failed (diag).*/
#endif // OPENTHREAD_CONFIG_DIAG_ENABLE
} esp_radio_spinel_callbacks_t; /* ... | 329 |
/*
*/
#pragma once
#include "esp_netif.h"
#include "esp_netif_types.h"
#include "esp_openthread.h"
#include "openthread/instance.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
void esp_openthread_set_backbone_netif(esp_netif_t *backbone_netif);
/**
esp_err_t esp_openthread_border_router_init(void);
/**
esp_err_t ... | 330 |
/*
*/
#pragma once
#include "esp_err.h"
#include "esp_netif.h"
#include "esp_openthread_types.h"
#include "openthread/instance.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define ESP_NETIF_INHERENT_DEFAULT_OPENTHREAD() \
{ \
.flags = 0, \
ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY... | 331 |
/*
*/
#pragma once
#include
#include
#include "esp_event_base.h"
#include "driver/gpio.h"
#include "driver/spi_master.h"
#include "driver/spi_slave.h"
#include "driver/uart.h"
#include "driver/usb_serial_jtag.h"
#include "hal/gpio_types.h"
#include "hal/uart_types.h"
#include "openthread/thread.h"
#ifdef __cplu... | 332 |
< UART port number */
uart_config_t uart_config; /*!< UART configuration, see uart_config_t docs */
gpio_num_t rx_pin; /*!< UART RX pin */
gpio_num_t tx_pin; /*!< UART TX pin */
} esp_openthread_uart_config_t;
/**
typedef struct {
spi_host_device_t host_device; /*!< SPI... | 332 |
< Use the native 15.4 radio */
RADIO_MODE_UART_RCP, /*!< UART connection to a 15.4 capable radio co-processor (RCP) */
RADIO_MODE_SPI_RCP, /*!< SPI connection to a 15.4 capable radio co-processor (RCP) */
RADIO_MODE_MAX, /*!< Using for parameter check */
} esp_openthread_radio_mode_t... | 332 |
< The uart configuration to RCP */
esp_openthread_spi_host_config_t radio_spi_config; /*!< The spi configuration to RCP */
};
} esp_openthread_radio_config_t;
/**
typedef struct {
esp_openthread_host_connection_mode_t host_connection_mode; /*!< The host connection mode */
union {
esp_opent... | 332 |
< The radio configuration */
esp_openthread_host_connection_config_t host_config; /*!< The host connection configuration */
esp_openthread_port_config_t port_config; /*!< The port configuration */
} esp_openthread_platform_config_t;
typedef void (*esp_openthread_rcp_failure_handler)(void);
#ifdef... | 332 |
/*
*/
#pragma once
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "hal/ledc_types.h"
#include "driver/gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_LEDC_SUPPORT_APB_CLOCK
/**
*/
#define LEDC_APB_CLK_HZ _Pragma ("GCC warning \"'LEDC_APB_CLK_HZ' macro is deprecated\"") (APB_CLK_FREQ)
#endif
#if ... | 333 |
< Total number of steps in one hardware fade [0, 2**SOC_LEDC_FADE_PARAMS_BIT_WIDTH-1] */
} ledc_fade_param_config_t;
/**
*/
esp_err_t ledc_set_multi_fade(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t start_duty, const ledc_fade_param_config_t *fade_params_list, uint32_t list_len);
/**
*/
esp_err_t ledc_s... | 333 |
/*
*/
#pragma once
#include
#include
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "spiffs.h"
#include "esp_compiler.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_SPIFFS_PATH_MAX 15
/**
*/
typedef struct {
spiffs *fs; /*!... | 334 |
< Cache Buffer */
uint32_t cache_sz; /*!< Cache Buffer Length */
} esp_spiffs_t;
s32_t spiffs_api_read(spiffs *fs, uint32_t addr, uint32_t size, uint8_t *dst);
s32_t spiffs_api_write(spiffs *fs, uint32_t addr, uint32_t size, uint8_t *src);
s32_t spiffs_api_erase(spiffs *fs, uint32_t addr, ui... | 334 |
/*
*/
#ifndef _ESP_SPIFFS_H_
#define _ESP_SPIFFS_H_
#include
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct {
const char* base_path; /*!< File path prefix associated with the filesystem. */
const char* partition_label; /*!< Optional, label of SPIFFS ... | 335 |
/*
*/
/*
*/
#ifndef SPIFFS_CONFIG_H_
#define SPIFFS_CONFIG_H_
// 8
#include
#include
#include
#include
#include
#include
#include
#include
#include "esp_assert.h"
// compile time switches
#define SPIFFS_TAG "SPIFFS"
// Set generic spiffs debug output call.
#if CONFIG_SPIFFS_DBG
#define SPIFFS_DBG(...) ... | 336 |
Once decided for a configuration,
// this can be disabled to reduce flash.
#define SPIFFS_BUFFER_HELP 0
// Enables/disable memory read caching of nucleus file system operations.
// If enabled, memory area must be provided for cache in SPIFFS_mount.
#ifdef CONFIG_SPIFFS_CACHE
#define SPIFFS_CACHE ... | 336 |
#define SPIFFS_GC_MAX_RUNS CONFIG_SPIFFS_GC_MAX_RUNS
// Enable/disable statistics on gc. Debug/test purpose only.
#ifdef CONFIG_SPIFFS_GC_STATS
#define SPIFFS_GC_STATS (1)
#else
#define SPIFFS_GC_STATS (0)
#endif
// Garbage collecting examines all pages in a block which and sums ... | 336 |
#define SPIFFS_GC_HEUR_W_ERASE_AGE (50)
// Object name maximum length. Note that this length include the
// zero-termination character, meaning maximum string of characters
// can at most be SPIFFS_OBJ_NAME_LEN - 1.
#define SPIFFS_OBJ_NAME_LEN (CONFIG_SPIFFS_OBJ_NAME_LEN)
// Maximum length of the me... | 336 |
// Lower value generates more read/writes. No meaning having it bigger
// than logical page size.
#define SPIFFS_COPY_BUFFER_STACK (256)
// Enable this to have an identifiable spiffs filesystem. This will look for
// a magic in all sectors to determine if this is a valid spiffs system or
// not on mount point.... | 336 |
This will reduce calculations, flash and memory accesses.
// Parts of configuration must be defined below instead of at time of mount.
#define SPIFFS_SINGLETON 0
// Enable this if your target needs aligned data for index tables
#define SPIFFS_ALIGNED_OBJECT_INDEX_TABLES 0
// Enable this if you want the HAL call... | 336 |
// HAL functions for erasing and writing to spi-flash may be null. Cache
// can be disabled for even further binary size reduction (and ram savings).
// Functions modifying the fs will return SPIFFS_ERR_RO_NOT_IMPL.
// If the file system cannot be mounted due to aborted erase operation and
// SPIFFS_USE_MAGIC is enabl... | 336 |
// The css is accessed for each html file that is opened, meaning it is
// accessed almost every second time a file is opened. Another example could be
// a log file that is often opened, written, and closed.
// The size of the cache is number of given file descriptors, as it piggybacks
// on the fd update mechanism. ... | 336 |
However, it must
// be between 1 (no gain for hitting a cached entry often) and 255.
#define SPIFFS_TEMPORAL_CACHE_HIT_SCORE 4
// Enable to be able to map object indices to memory.
// This allows for faster and more deterministic reading if cases of reading
// large files and when changing file offset by seek... | 336 |
This function will visualize all filesystem using given printf
// function.
#ifdef CONFIG_SPIFFS_TEST_VISUALISATION
#define SPIFFS_TEST_VISUALISATION 1
#else
#define SPIFFS_TEST_VISUALISATION 0
#endif
#if SPIFFS_TEST_VISUALISATION
#ifndef spiffs_printf
#define spiffs_printf(...) ... | 336 |
Make sure the size of this type can hold
// the highest number of all blocks - i.e. spiffs_file_system_size / log_block_size
typedef u16_t spiffs_block_ix;
// Page index type. Make sure the size of this type can hold
// the highest page number of all pages - i.e. spiffs_file_system_size / log_page_size
typedef u16_t s... | 336 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "soc/timer_periph.h"
#include "soc/timer_group_struct.h"
#include "hal/wdt_types.h"
#incl... | 337 |
wdt_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
hw->wdtconfig0.wdt_en = 0;
}
/**
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
return (hw->wdtconfig0.wdt_en) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_... | 337 |
wdt_conf_update_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
{
switch (stage) {
case WDT_STAGE0:
hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
... | 337 |
wdt_sys_reset_length = length;
//Config registers are updated asynchronously
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
{
hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
//Config registers are updated asynchronou... | 337 |
wdt_wkey = 0;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
{
hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
{
hw->int_clr_timers.wdt_int_clr = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_set_intr_ena... | 337 |
/*
*/
/
/
#pragma once
#include
#include "soc/hwcrypto_reg.h"
#include "hal/aes_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
typedef enum {
ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */
ESP_AES_STATE_BUSY, /* Transform in progress */
ESP_AES_STATE_DONE, /* Transform completed ... | 338 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include // For MIN/MAX
#include
#include
#include "soc/spi_periph.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SP... | 339 |
val = 0;
dev->cmd.flash_se = 1;
}
/**
*/
static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev)
{
dev->cmd.flash_be = 1;
}
/**
*/
static inline void spimem_flash_ll_suspend(spi_mem_dev_t *dev)
{
dev->flash_sus_ctrl.flash_pes = 1;
}
/**
*/
static inline void spimem_flash_ll_resume(spi_mem_d... | 339 |
wait_pesr_command = pesr_cmd;
}
/**
static inline void spimem_flash_ll_sus_check_sus_setup(spi_mem_dev_t *dev, bool sus_check_sus_en)
{
dev->flash_sus_ctrl.sus_timeout_cnt = 5;
dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en;
}
/**
static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, b... | 339 |
waiti_cmd = 0x05;
dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti;
dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti;
}
/**
*/
static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy)
{
// Not supported on this chip.
}
/**
*/
static inline bool spimem_fl... | 339 |
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