text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
flash_wren = 1;
}
}
/**
*/
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
// If everything is word-aligned, do a faster memcpy
memcpy(buffer, (void *)dev->data_buf, read_len);
... | 339 |
usr_dummy = 0;
spimem_flash_ll_set_buffer_data(dev, buffer, length);
dev->cmd.flash_pp = 1;
}
/**
*/
static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev, bool pe_ops)
{
uint32_t usr_pe = (pe_ops ? 0x60000 : 0x40000);
dev->cmd.val |= usr_pe;
}
/**
*/
static inline bool spimem_flash_ll_ho... | 339 |
val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
break;
case SPI_FLASH_QIO:
ctrl.fread_qio = 1;
break;
case SPI_FLASH_... | 339 |
usr_mosi = bitlen > 0;
dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0;
}
/**
*/
static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen)
{
dev->user.usr_command = 1;
typeof(dev->user2) user2 = {
.usr_command_value = command,
.usr_co... | 339 |
usr_dummy = dummy_n ? 1 : 0;
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
}
/**
*/
static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t out_en, uint32_t out_lev)
{
dev->ctrl.fdummy_out = out_en;
dev->ctrl.q_pol = out_lev;
dev->ctrl.d_pol = out_lev;
}
/**
*/
static inline voi... | 339 |
h`
if (clkdiv == 1) {
div_parameter = (1 ctrl.wp = level;
}
/**
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif
| 339 |
/*
*/
// The LL layer for I2C register operations
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2c_periph.h"
#include "soc/soc_caps.h"
#include "soc/i2c_struct.h"
#include "hal/i2c_types.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/clk_tree_defs.h"
#include "soc/system_struct... | 340 |
conf_upgate = 1;
}
/**
*/
static inline void i2c_ll_enable_bus_clock(int i2c_port, bool enable)
{
(void)i2c_port;
SYSTEM.perip_clk_en0.i2c_ext0_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC... | 340 |
hw->scl_low_period.scl_low_period = bus_cfg->scl_low - 1;
hw->scl_high_period.scl_high_period = bus_cfg->scl_high;
hw->scl_high_period.scl_wait_high_period = bus_cfg->scl_wait_high;
//sda sample
hw->sda_hold.sda_hold_time = bus_cfg->sda_hold - 1;
hw->sda_sample.sda_sample_time = bus_cfg->sda_sa... | 340 |
tx_fifo_rst = 1;
hw->fifo_conf.tx_fifo_rst = 0;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_rxfifo_rst(i2c_dev_t *hw)
{
hw->fifo_conf.rx_fifo_rst = 1;
hw->fifo_conf.rx_fifo_rst = 0;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uin... | 340 |
time_out_value = tout;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cmd, int cmd_idx)
{
hw->command[cmd_idx].val = cmd.val;
}
/**
*/
static inline void i2c_ll_master_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
{
hw... | 340 |
rxfifo_wm_thrhd = full_thr;
}
/**
*/
static inline void i2c_ll_set_data_mode(i2c_dev_t *hw, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mode)
{
hw->ctr.tx_lsb_first = tx_mode;
hw->ctr.rx_lsb_first = rx_mode;
}
/**
*/
static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sda_hold)
{... | 340 |
txfifo_cnt;
}
/**
*/
static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
{
*timeout = hw->to.time_out_value;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
/**
*/
static inline void i2c_ll_get_start_timing(i2c_de... | 340 |
scl_filter_thres = filter_num;
hw->filter_cfg.sda_filter_thres = filter_num;
hw->filter_cfg.scl_filter_en = 1;
hw->filter_cfg.sda_filter_en = 1;
} else {
hw->filter_cfg.scl_filter_en = 0;
hw->filter_cfg.sda_filter_en = 0;
}
}
/**
*/
static inline void i2c_ll_master_get_... | 340 |
sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0;
}
/**
*/
static inline void i2c_ll_enable_controller_clock(i2c_dev_t *hw, bool en)
{
hw->clk_conf.sclk_active = en;
}
/**
*/
static inline void i2c_ll_master_init(i2c_dev_t *hw)
{
typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0;
ctrl_reg.ms_mode = 1;
... | 340 |
0)//////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I2C master TX interrupt bitmap
#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_... | 340 |
scl_high_period;
*wait_high_period = hw->scl_high_period.scl_wait_high_period;
*low_period = hw->scl_low_period.scl_low_period;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
i2c_int_status_reg_t int_sts;
int_sts.val = hw->i... | 340 |
val = UINT32_MAX;
hw->int_ena.val = I2C_LL_MASTER_RX_INT;
}
/**
*/
static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT);
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_... | 340 |
scl_high_period + hw->scl_high_period.scl_wait_high_period;
*low_period = hw->scl_low_period.scl_low_period + 1;
}
#ifdef __cplusplus
}
#endif
| 340 |
/*
*/
#pragma once
#include /* Required for NULL constant */
#include
#include
#include "hal/gdma_types.h"
#include "soc/gdma_struct.h"
#include "soc/gdma_reg.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
#define GDMA_LL_CHANNE... | 341 |
st.val & GDMA_LL_RX_EVENT_MASK;
}
}
/**
*/
static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK);
} else {
dev->intr[channel].ena.val &= ~(mask & GDMA_LL_RX_... | 341 |
in.in_conf0.in_data_burst_en = enable;
}
/**
*/
static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->channel[channel].in.in_conf0.indscr_burst_en = enable;
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev,... | 341 |
in.in_pop.infifo_pop = 1;
return dev->channel[channel].in.in_pop.infifo_rdata;
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
dev->channel[channel].in.in_link.addr = addr;
}
/**
*/
__attribute__((always_inline))
static ... | 341 |
in.in_link.park;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->channel[channel].in.in_suc_eof_des_addr;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_de... | 341 |
in.in_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.in_conf0.mem_trans_en = false;
}
///////////////////////////////////// TX /////////////////////////////////////////
/**
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channe... | 341 |
st);
}
/**
*/
static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->channel[channel].out.out_conf1.out_check_owner = enable;
}
/**
*/
static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->channel[channel].out.... | 341 |
out.out_conf0.out_rst = 1;
dev->channel[channel].out.out_conf0.out_rst = 0;
}
/**
*/
static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->channel[channel].out.outfifo_status.val & 0x01;
}
/**
*/
static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_... | 341 |
out.out_link.addr = addr;
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_link.start = 1;
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
{
dev->channe... | 341 |
out.out_dscr;
}
/**
*/
static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->channel[channel].out.out_pri.tx_pri = prio;
}
/**
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
{
... | 341 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#include "hal/efuse_ll.h"
#include_next "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void efuse_hal_set_timing(uint32_t apb_freq_hz);
/**
*/
void efuse_hal_read(void);
/**
*/
void efuse_hal_clear_program_registers(void);
/**
... | 342 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash Encryption.
#include
#include
#include "soc/system_reg.h"
#include "soc/xts_aes_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Choose type of chip you want to encrypt manully
typedef enum
{
... | 343 |
= 0x3) {
}
}
/**
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
REG_WRITE(XTS_AES_DESTROY_REG, 1);
}
/**
*/
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
{
return ((address % length) == 0) ? true : false;
}
#ifdef __cplusplus
}
#endif
| 343 |
/*
*/
/**
*/
#pragma once
#include
#include "soc/soc.h"
#include "soc/rtc_cntl_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PWDET_CONF_REG 0x6004EB60
#define PWDET_SAR_POWER_FORCE BIT(7)
#define PWDET_SAR_POWER_CNTL BIT(6)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled... | 344 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/wdt_types.h"
#include "soc/rtc_cntl_periph.h"
#include "hal/efuse_ll.h"
#include "es... | 345 |
en = 1;
}
/**
*/
FORCE_INLINE_ATTR void rwdt_ll_disable(rtc_cntl_dev_t *hw)
{
hw->wdt_config0.en = 0;
}
/**
*/
FORCE_INLINE_ATTR bool rwdt_ll_check_if_enabled(rtc_cntl_dev_t *hw)
{
return (hw->wdt_config0.en) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stag... | 345 |
stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->wdt_config0.stg3 = WDT_STAGE_ACTION_OFF;
break;
defau... | 345 |
pause_in_slp = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t *hw, bool enable)
{
hw->wdt_config0.chip_reset_en = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width)
{
hw->wdt_config0.chip_reset_width ... | 345 |
rtc_wdt = 1;
}
#ifdef __cplusplus
}
#endif
| 345 |
/*
*/
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "hal/uart_types.h"
#include "hal/misc.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/syste... | 346 |
tx_sclk_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
{
hw->clk_conf.sclk_en = 0;
hw->clk_conf.rx_sclk_en = 0;
hw->clk_conf.tx_sclk_en = 0;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
ca... | 346 |
div_int = clk_div >> 4;
hw->clk_div.div_frag = clk_div & 0xf;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
{
typeof(hw->clk_div) div_reg;
div_reg.val = hw->clk_div.va... | 346 |
val;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{
for (int i = 0; i ahb_fifo.rw_byte;
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
// Write to the FIFO should make sure only involve w... | 346 |
txfifo_cnt;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
{
hw->conf0.stop_bit_num = stop_bit;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
{
*stop_bit = (uart_stop_bits_t)hw->conf0.stop_bit_num;
}
/**
... | 346 |
txfifo_empty_thrhd = empty_thrhd;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
{
hw->idle_conf.rx_idle_thrhd = rx_idle_thr;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
{
hw->idle_conf.tx_idle_num = idle_num;
}
/... | 346 |
tx_flow_en = 1;
} else {
hw->conf0.tx_flow_en = 0;
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
{
*flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
if (hw->conf1.rx_flow_en) {
*flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow... | 346 |
sw_flow_con_en = 0;
hw->flow_conf.xonoff_del = 0;
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char... | 346 |
active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
{
hw->rs485_conf.en = 0;
hw->rs485_conf.tx_rx_en = 0;
hw->rs485_conf.rx_busy_tx_en = 0;
hw->conf0.irda_en = 0;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_ap... | 346 |
rx_busy_tx_en = 0;
hw->conf0.irda_en = 0;
hw->rs485_conf.dl0_en = 1;
hw->rs485_conf.dl1_en = 1;
hw->rs485_conf.en = 1;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
{
hw->conf0.irda_en = 0;
// Enable full-duplex mode
hw->rs485_conf.tx_rx_en = 1;
// T... | 346 |
active_threshold + UART_LL_MIN_WAKEUP_THRESH;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
{
*data_bit = (uart_word_length_t)hw->conf0.bit_num;
}
/**
*/
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
{
return ((hw->status.txfifo_cnt == 0) ... | 346 |
val = hw->conf0.val;
conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0;
conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0;
conf0_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0;
conf0_reg.dsr_i... | 346 |
rx_tout_en > 0) {
tout_thrd = hw->mem_conf.rx_tout_thrhd;
}
return tout_thrd;
}
/**
*/
FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
{
return UART_RX_TOUT_THRHD_V;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
{
REG_CLR_BIT(UART_FLOW_CONF_REG(uar... | 346 |
err_wr_mask = discard ? 1 : 0;
}
#ifdef __cplusplus
}
#endif
| 346 |
/*
*/
/
/
// The LL layer for SPI register operations
#pragma once
#include //for abs()
#include
#include "esp_attr.h"
#include "esp_types.h"
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "soc/system_struct.h"
#include "soc/lldesc.h"
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal... | 347 |
mst_clk_sel = 0;
break;
default:
hw->clk_gate.mst_clk_sel = 1;
break;
}
}
/**
*/
static inline void spi_ll_master_init(spi_dev_t *hw)
{
//Reset timing
hw->user1.cs_setup_time = 0;
hw->user1.cs_hold_time = 0;
//use all 64 bytes of the buffer
hw->user... | 347 |
usr_miso_highpart = 0;
hw->user.usr_mosi_highpart = 0;
// Configure DMA In-Link to not be terminated when transaction bit counter exceeds
hw->dma_conf.rx_eof_en = 0;
hw->dma_conf.dma_seg_trans_en = 0;
//Disable unneeded ints
hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK;
}
/**
*/
static inl... | 347 |
usr = 1;
}
/**
*/
static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw)
{
return hw->cmd.val;
}
/**
*/
static inline void spi_ll_slave_reset(spi_dev_t *hw)
{
hw->slave.soft_reset = 1;
hw->slave.soft_reset = 0;
}
/**
*/
static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
{
hw->dma_con... | 347 |
outfifo_empty_err = 1;
}
/*
**/
/**
*/
static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable)
{
hw->dma_conf.dma_rx_ena = enable;
}
/**
*/
static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable)
{
hw->dma_conf.dma_tx_ena = enable;
}
/**
*/
static inline void spi_ll_dma_set_rx_eof... | 347 |
master_cs_pol |= (1 misc.master_cs_pol &= ~(1 ctrl.wr_bit_order = lsbfirst;
}
/**
*/
static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst)
{
hw->ctrl.rd_bit_order = lsbfirst;
}
/**
*/
static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode)
{
//Configure polarity
if (mode... | 347 |
rsck_i_edge = 1;
hw->user.tsck_i_edge = 1;
hw->slave.clk_mode_13 = 1;
} else if (mode == 2) {
hw->misc.ck_idle_edge = 1;
hw->user.rsck_i_edge = 1;
hw->user.tsck_i_edge = 1;
hw->slave.clk_mode_13 = 0;
} else if (mode == 3) {
hw->misc.ck_idle_edge = 1;
... | 347 |
faddr_dual = (line_mode.addr_lines == 2);
hw->ctrl.faddr_quad = (line_mode.addr_lines == 4);
hw->ctrl.fread_dual = (line_mode.data_lines == 2);
hw->user.fwrite_dual = (line_mode.data_lines == 2);
hw->ctrl.fread_quad = (line_mode.data_lines == 4);
hw->user.fwrite_quad = (line_mode.data_lines == 4);
}... | 347 |
val = *(uint32_t *)val;
}
/**
*/
static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
{
return (fapb / (pre * n));
}
/**
*/
static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg)
{
typeof(GPSPI2.clock) reg;
int eff_clk;
//In hw, n, h and l ... | 347 |
int pre, n, h, l;
int bestn = -1;
int bestpre = -1;
int besterr = 0;
int errval;
for (n = 2; n 16) {
pre = 16;
}
errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz);
if (bestn == -1 || errval user1.cs_hold_time = ho... | 347 |
usr_command_bitlen = bitlen - 1;
hw->user.usr_command = bitlen ? 1 : 0;
}
/**
*/
static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen)
{
hw->user1.usr_addr_bitlen = bitlen - 1;
hw->user.usr_addr = bitlen ? 1 : 0;
}
/**
*/
static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr,... | 347 |
usr_dummy = dummy_n ? 1 : 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
}
/**
*/
static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable)
{
hw->user.usr_miso = enable;
}
/**
*/
static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable)
{
hw->user.usr_mosi =... | 347 |
wr_buf_done, dma_int_clr.wr_buf_done, dma_int_set.wr_buf_done_int_set) \
item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done, dma_int_set.rd_dma_done_int_set) \
item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, ... | 347 |
cmd9, dma_int_set.cmd9_int_set) \
item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda, dma_int_set.cmda_int_set)
static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
{
#define ENA_INTR(intr_bit, en_re... | 347 |
..) if (intr_mask & (intr_bit)) hw->clr_reg = 1;
FOR_EACH_ITEM(CLR_INTR, INTR_LIST);
#undef CLR_INTR
}
static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
{
#define GET_INTR(intr_bit, _, raw_reg, ...) if (intr_mask & (intr_bit) && hw->raw_reg) return true;
FOR_EACH_ITEM(GET_INTR, INTR_LI... | 347 |
1 : 0;
hw->slave.wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
hw->slave.rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
hw->slave.wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
}
static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw... | 347 |
data_lines == 2) {
if (line_mode.addr_lines == 2) {
cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit
} else {
cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit
}
} else if (line_mode.data_lines == 4) {
if (line_mode.addr_lines == 4) {
cmd_mod ... | 347 |
/*
*/
// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
// This Low Level driver only serve the General Purpose Timer function.
#pragma once
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/timer_types.h"
#include "soc... | 348 |
config.tx_alarm_en = en;
}
/**
*/
static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider)
{
HAL_ASSERT(divider >= 2 && divider = 65536) {
divider = 0;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
hw->hw_time... | 348 |
update.tx_update = 1;
// Timer register is in a different clock domain from Timer hardware logic
// We need to wait for the update to take effect before fetching the count value
while (hw->hw_timer[timer_num].update.tx_update) {
}
}
/**
*/
__attribute__((always_inline))
static inline uint64_t timer_ll... | 348 |
loadlo.tx_load_lo = (uint32_t) load_val;
}
/**
*/
__attribute__((always_inline))
static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
{
return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi hw_timer[timer_num].loadlo.tx_load_lo);
}
/**
*/
__attribute__((always_inline))
stat... | 348 |
clk_en = en;
}
/**
*/
static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
{
return &hw->int_st_timers.val;
}
#ifdef __cplusplus
}
#endif
| 348 |
/*
*/
#pragma once
#include
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/system_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h"
#include "hal/assert.h"
#include "hal/log.h"
#include "esp32c2/rom/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
#def... | 349 |
= 0 && xtal_freq_reg != UINT32_MAX) {
return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
}
// If the format in reg is invalid
return 0;
}
/**
*/
static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint32_t apb_freq_hz)
{
uint32_t val = apb_freq_hz >> 12;
WRITE... | 349 |
/*
*/
#pragma once
#include
#include
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/ eFuse fields /
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flas... | 350 |
rd_blk2_data1.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return EFUSE.rd_blk2_data1.wafer_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_... | 350 |
rd_blk2_data2.ocode_1 << 2) + EFUSE.rd_blk2_data1.ocode;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void)
{
// DIG_DBIAS_HVT, EFUSE_BLK2, 105, 5, BLOCK2 digital dbias when hvt
return EFUSE.rd_blk2_data3.dig_dbias_hvt;
}
__attribute__(... | 350 |
rd_blk2_data4.dig_ldo_act_dbias26_1 << 3) + EFUSE.rd_blk2_data3.dig_ldo_act_dbias26;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_act_stepd10(void)
{
// DIG_LDO_ACT_STEPD10, EFUSE_BLK2, 131, 4, BLOCK2 DIG_LDO_ACT_STEPD10
return EFUSE.rd_blk2_data4.d... | 350 |
rd_blk2_data4.rtc_ldo_slp_dbias31;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_act_dbias31(void)
{
// RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, BLOCK2 DIG_LDO_ACT_DBIAS31
return (EFUSE.rd_blk2_data5.rtc_ldo_act_dbias31_1 << 3) + EFUSE.rd_blk2_data4.... | 350 |
cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.o... | 350 |
/*
*/
#include
#include "esp_attr.h"
#include "soc/system_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
{
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
}
/**
*/
FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int co... | 351 |
/*
*/
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/regi2c_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void regi2c_ctrl_ll_i2c_reset(void)
{
SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
}
/**
*/
static inline void regi2c_ctrl_ll_i... | 352 |
/*
*/
#pragma once
#include
#include "soc/hwcrypto_reg.h"
#include "hal/sha_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void sha_ll_start_block(esp_sha_type sha_type)
{
REG_WRITE(SHA_MODE_REG, sha_type);
REG_WRITE(SHA_START_REG, 1);
}
/**
*/
static inline void sha_ll_continue_b... | 353 |
/*
*/
// The LL layer for MMU register operations
#pragma once
#include
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
{
return vaddr & SO... | 354 |
0 : (size == MMU_PAGE_32KB) ? 1 : 2;
REG_SET_FIELD(EXTMEM_CACHE_CONF_MISC_REG, EXTMEM_CACHE_MMU_PAGE_SIZE, reg_val);
}
/**
*/
__attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
{
(void)mmu_id;
uint32... | 354 |
false : true;
}
/**
*/
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
{
(void)mmu_id;
return MMU_TARGET_FLASH0;
}
/**
*/
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
{
(void)mmu_id;
HAL_ASSERT(entry_id < SOC_MMU_ENT... | 354 |
/*
*/
// The LL layer for DEBUG_ASSIST peripheral
#pragma once
#include "soc/assist_debug_reg.h"
#define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
#ifndef __ASSEMBLER__
#include
#include
#include "esp_attr.h"
#include "hal/assert.h"
#ifdef __cplus... | 355 |
/*
*/
/
/
// The LL for temperature sensor
#pragma once
#include
#include
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
#include "soc/apb_saradc_struct.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/system_struct.h"
#include "hal/temperature_sensor_types.h"
#include "hal/assert.h"... | 356 |
..) do {(void)__DECLARE_RCC_ATOMIC_ENV; temperature_sensor_ll_bus_clk_enable(__VA_ARGS__);} while(0)
/**
*/
static inline void temperature_sensor_ll_reset_module(void)
{
SYSTEM.perip_rst_en1.tsens_rst = 1;
SYSTEM.perip_rst_en1.tsens_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it ... | 356 |
saradc_tsens_clk_sel = clk_sel;
}
/**
*/
static inline void temperature_sensor_ll_set_range(uint32_t range)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range);
}
/**
*/
static inline uint32_t temperature_sensor_ll_get_raw_value(void)
{
return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.saradc_apb_tse... | 356 |
/*
*/
// The LL layer for LEDC register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include "hal/ledc_types.h"
#include "soc/ledc_periph.h"
#include "soc/system_struct.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LEDC... | 357 |
timer[timer_sel].conf.para_up = 1;
}
/**
*/
static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
{
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1;
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0;
}
/**
*/
static inline void ledc_ll_timer_p... | 357 |
timer[timer_sel].conf.clk_div;
}
/**
*/
static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src)
{
*clk_src = LEDC_SCLK;
}
/**
*/
static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_... | 357 |
channel[channel_num].hpoint.hpoint = hpoint_val;
}
/**
*/
static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val)
{
*hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint;
}
/**
*/
static inline void ledc_ll_set_duty... | 357 |
conf1.duty_num = duty_num;
}
/**
*/
static inline void ledc_ll_set_duty_cycle(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_cycle)
{
hw->channel_group[speed_mode].channel[channel_num].conf1.duty_cycle = duty_cycle;
}
/**
*/
static inline void ledc_ll_set_duty_scale(ledc_dev_t... | 357 |
conf1.val = conf1_reg.val;
}
/**
*/
__attribute__((always_inline))
static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool sig_out_en)
{
hw->channel_group[speed_mode].channel[channel_num].conf0.sig_out_en = sig_out_en;
}
/**
*/
static inline void ledc_l... | 357 |
val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num))));
}
/**
*/
static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_status)
{
uint32_t value = hw->int_st.val;
uint32_t int_en_base = LEDC_DUTY_CHN... | 357 |
channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus
}
#endif
| 357 |
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