text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus
}
#endif
| 427 |
/*
*/
#pragma once
#include
#include
#include "soc/systimer_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/system_struct.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions even no... | 428 |
..) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void systimer_ll_reset_register(void)
{
SYSTEM.perip_rst_en0.reg_systimer_rst = 1;
SYSTEM.perip_rst_en0.reg_systimer_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical ... | 428 |
hi.timer_unit_load_hi = value >> 32;
dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
}
__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
{
return dev->unit_val[counter_id].lo.timer_unit_value_lo;
}
__att... | 428 |
hi.timer_target_hi) target_val[alarm_id].lo.timer_target_lo;
}
__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
{
dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
}
__attribute__((always_inline)) static i... | 428 |
target_period;
}
__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
{
dev->comp_load[alarm_id].val = 0x01;
}
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
{
if (en... | 428 |
/*
*/
#pragma once
#include
#include "riscv/csr.h"
/*fast gpio*/
#define CSR_GPIO_OEN_USER 0x803
#define CSR_GPIO_IN_USER 0x804
#define CSR_GPIO_OUT_USER 0x805
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
{
RV_W... | 429 |
/*
*/
// The LL layer for Cache register operations
#pragma once
#include
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32c3/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE... | 430 |
Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);... | 430 |
EXTMEM_ICACHE_SHUT_DBUS : 0);
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
/**
*/
__attribute__((always_inline))
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
{
bool valid = false;
uint32_t vaddr_end = vaddr_start + le... | 430 |
/*
*/
#include
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/* This LL is currently unused for ESP32-C3 - cleanup is TODO ESP32-C3 IDF-2375 */
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
{
abort();
}
static inline void mpu_ll_set_region_rw(uint32_t addr)
... | 431 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include "gpspi_flash_ll.h"
#include "spimem_flash_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
... | 432 |
/*
*/
#pragma once
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;
// Disable software control USB D+ D- pullup pulldown (Dev... | 433 |
/*
*/
// The LL layer for UHCI register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (N... | 434 |
val = hw->esc_conf0.val;
esc_conf0_reg.seper_char = seper_char->seper_chr;
esc_conf0_reg.seper_esc_char0 = seper_char->sub_chr1;
esc_conf0_reg.seper_esc_char1 = seper_char->sub_chr2;
hw->esc_conf0.val = esc_conf0_reg.val;
hw->escape_conf.tx_c0_esc_en = 1;
hw->escape_conf... | 434 |
seq1 = sub_ctr->xon_chr;
esc_conf2_reg.seq1_char0 = sub_ctr->xon_sub1;
esc_conf2_reg.seq1_char1 = sub_ctr->xon_sub2;
esc_conf3_reg.seq2 = sub_ctr->xoff_chr;
esc_conf3_reg.seq2_char0 = sub_ctr->xoff_sub1;
esc_conf3_reg.seq2_char1 = sub_ctr->xoff_sub2;
escape_conf_reg.tx_11... | 434 |
val = intr_mask;
}
static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
{
return hw->int_st.val;
}
static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
hw->conf0.uart_rx_brk_eof_en = 1;
}
if (eof_mode & UHCI_RX_IDLE_EOF) {
... | 434 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/assert.h"
#include "soc/periph_defs.h"
#include "soc/system_reg.h"
#include "soc/syscon_reg.h"
#include "soc/dport_access.h"
#include "soc/soc_caps.h"
#include "esp_attr.h"
static inline uint32_t periph_ll_get_clk_en_mask(p... | 435 |
return (SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST);
} else {
//Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
return SYSTEM_CRYPTO_AES_RST;
}
case PERIPH_SHA_MODULE:
if (enable == true) {
// Clear r... | 435 |
= 0;
}
static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(SY... | 435 |
/*
*/
#pragma once
#include
#include
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/clk_tree_defs.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/adc_typ... | 436 |
APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_THRES1_LOW_INT_ST_M)
/*
Oneshot
*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
/*
DMA
*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC... | 436 |
> offset)); // Clear old data
tab |= ((uint32_t)(pattern.val & 0x3F) > offset; // Fill in the new data
APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back
}
/**
*/
static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{
APB_SARADC.ctrl.sa... | 436 |
ctrl2.timer_en = 1;
}
/**
*/
static inline void adc_ll_digi_trigger_disable(void)
{
APB_SARADC.ctrl2.timer_en = 0;
}
/**
*/
static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num... | 436 |
filter_ctrl0.filter_channel0 = ((adc_n + 1) RTC(1) > Digital(0);
*/
__attribute__((always_inline))
static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig, uint8_t pri_pwdet)
{
if (pri_rtc != pri_dig && pri_rtc != pri_pwdet && pri_dig != pri_pwdet) {
APB_SARADC.apb_adc_arb_ctrl.adc... | 436 |
apb_adc_arb_ctrl.adc_arb_apb_force = 1;
APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0;
APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0;
} else {
APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0;
APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0;
... | 436 |
*/
/**
*/
static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{
if (en) {
REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3);
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, AP... | 436 |
onetime_sample.adc1_onetime_sample = 0;
APB_SARADC.onetime_sample.onetime_channel = 0xf;
REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0);
REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0);
CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_S... | 436 |
onetime_sample.adc1_onetime_sample = 1;
} else {
APB_SARADC.onetime_sample.adc2_onetime_sample = 1;
}
}
/**
*/
static inline void adc_oneshot_ll_disable_all_unit(void)
{
APB_SARADC.onetime_sample.adc1_onetime_sample = 0;
APB_SARADC.onetime_sample.adc2_onetime_sample = 0;
}
/**
*/
static inli... | 436 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include // For MIN/MAX
#include
#include
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
//NOTE: These macros ... | 437 |
rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_seg_trans_en = 0;
}
/**
*/
static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
{
return (dev->cmd.usr == 0);
}
/**
*/
static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 ... | 437 |
update = 1;
while (dev->cmd.update);
dev->cmd.usr = 1;
}
/**
*/
static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev)
{
// Not supported on GPSPI
}
/**
*/
static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
{
dev->ctrl.hold_pol = pol_val;
}
/**
*/
static inline ... | 437 |
val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
case SPI_FLASH_SLOWRD:
... | 437 |
val = *clock_val;
}
/**
*/
static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_miso = bitlen > 0;
if (bitlen) {
dev->ms_dlen.ms_data_bitlen = bitlen - 1;
}
}
/**
*/
static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
{... | 437 |
usr_addr = bitlen ? 1 : 0;
}
/**
*/
static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
// The blank region should be all ones
uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen);
dev->addr = (addr addr = addr;
}
/**
*/
static inline void gpsp... | 437 |
1 : 0);
dev->user1.cs_setup_time = cs_setup_time - 1;
}
/**
*/
static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
{
uint32_t div_parameter;
// See comments of `clock` in `spi_struct.h`
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((... | 437 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
{
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
WRITE_PERI_REG(RTC_CNTL_S... | 438 |
/*
*/
/
/
#pragma once
#include
#include "soc/rtc_cntl_struct.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_brownout.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void brownout_ll_enable_flash_power_down(bool enable)
{
RTCCNTL.brown_out.close_flash_ena = enable;
}
/**
*/
static inl... | 439 |
int_ena.rtc_brown_out = enable;
}
/**
*/
static inline void brownout_ll_ana_reset_enable(bool enable)
{
RTCCNTL.brown_out.ana_rst_en = enable;
}
/**
*/
__attribute__((always_inline))
static inline void brownout_ll_intr_clear(void)
{
RTCCNTL.int_clr.rtc_brown_out = 1;
}
/**
*/
static inline void brownout_l... | 439 |
/*
*/
/
/
// The LL layer for ESP32-C3 GPIO register operations
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/usb_serial_jtag_reg.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#ifdef __cplusplus... | 440 |
pad_driver;
*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
*sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
}
/**
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{... | 440 |
int_type = intr_type;
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
*status = hw->pcpu_int.intr;
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, ... | 440 |
int_ena = 0; //disable GPIO intr
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
}
/**
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpi... | 440 |
pad_driver = 1;
}
/**
*/
static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
// Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
... | 440 |
GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
}
/**
*/
static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
{
if (gpio_num func_in_sel_cfg[signal_idx].sig_in_sel = 0;
PIN_INPUT_ENABLE(IO_MUX_GP... | 440 |
oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_func_sel(hw, gpio_num, func);
}
/**
*/
static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx)
{
typeof(hw->func_in_sel_cfg[in_sig_idx]) reg;
reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
... | 440 |
/*
*/
#pragma once
#include
#include
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define TWAI_EXTD_ID_MASK 0x1FFFFFFF /** 256
#define TWAI_TIMING_CONFIG_1KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolut... | 441 |
sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_16KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 400000, .brp = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_20KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 400000, ... | 441 |
tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_125KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 4000000, .brp = 0, .tseg_1 = 23, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_250KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .qua... | 441 |
clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 625000, .brp = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_50KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 1000000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
#de... | 441 |
sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_800KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 20000000, .brp = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
#define TWAI_TIMING_CONFIG_1MBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 200000... | 441 |
Unused for received. */
uint32_t self: 1; /**< Transmit as a Self Reception Request. Unused for received. */
uint32_t dlc_non_comp: 1; /**< Message's Data length code is larger than 8. This will break compliance with ISO 11898-1 */
uint32_t reserved: 27; /**< Reserv... | 441 |
Note: the value of `brp` will reflected by this field if it's non-zero, otherwise, `brp` needs to be set manually */
uint32_t brp; /**< Baudrate prescale (i.e., clock divider). Any even number from 2 to 128 for ESP32, 2 to 32768 for non-ESP32 chip.
... | 441 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/* padlock.c and aesni.c rely on these values! */
#define ESP_AES_ENCRYPT 1
#define ESP_AES_DECRYPT 0
/* DMA AES working modes*/
typedef enum {
ESP_AES_BLOCK_MODE_ECB = 0,
ESP_AES_BLOCK_MODE_CBC,
ESP_AES_BLOCK_MODE_OFB,
ESP_AES_BLOCK... | 442 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
LDO_UNIT_1 = 1, ///< LDO 1
LDO_UNIT_2, ///< LDO 2
LDO_UNIT_3, ///< LDO 3
LDO_UNIT_4, ///< LDO 4
} ldo_unit_t;
#ifdef __cplusplus
}
#endif
| 443 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
/*
This header is shared across all targets. Resolve to an empty header for targets
that don't support USB OTG.
*/
#if SOC_USB_OTG_SUPPORTED
#include
#include
#include "soc/usb_dwc_struct.h"
#include "soc/usb_dwc_cfg.h"
#include "hal/usb_dwc_types.h"
#include "hal/misc.... | 444 |
glbllntrmsk = 1;
}
static inline void usb_dwc_ll_gahbcfg_dis_global_intr(usb_dwc_dev_t *hw)
{
hw->gahbcfg_reg.glbllntrmsk = 0;
}
// GUSBCFG Register
static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
{
hw->gusbcfg_reg.forcehstmode = 1;
}
static inline void usb_dwc_ll_gusbcfg_dis_hnp_... | 444 |
ahbidle;
}
static inline bool usb_dwc_ll_grstctl_is_dma_req_in_progress(usb_dwc_dev_t *hw)
{
return hw->grstctl_reg.dmareq;
}
static inline void usb_dwc_ll_grstctl_flush_nptx_fifo(usb_dwc_dev_t *hw)
{
hw->grstctl_reg.txfnum = 0; //Set the TX FIFO number to 0 to select the non-periodic TX FIFO
hw->grst... | 444 |
frmcntrrst = 1;
}
static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw)
{
hw->grstctl_reg.csftrst = 1;
}
static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw)
{
return hw->grstctl_reg.csftrst;
}
// GINTSTS Register
/**
*/
static inline uint32_t usb_dwc... | 444 |
val &= ~intr_mask;
}
// GRXFSIZ Register
static inline void usb_dwc_ll_grxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t num_lines)
{
//Set size in words
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->grxfsiz_reg, rxfdep, num_lines);
}
// GNPTXFSIZ Register
static inline void usb_dwc_ll_gnptxfsiz_set_fifo_size(usb_... | 444 |
val;
*ghwcfg3 = hw->ghwcfg3_reg.val;
*ghwcfg4 = hw->ghwcfg4_reg.val;
}
// HPTXFSIZ Register
static inline void usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines)
{
usb_dwc_hptxfsiz_reg_t hptxfsiz;
hptxfsiz.val = hw->hptxfsiz_reg.val;
HAL_FORCE_MODIFY_U32_... | 444 |
frlisten = frlisten;
}
static inline void usb_dwc_ll_hcfg_en_scatt_gatt_dma(usb_dwc_dev_t *hw)
{
hw->hcfg_reg.descdma = 1;
}
static inline void usb_dwc_ll_hcfg_set_fsls_supp_only(usb_dwc_dev_t *hw)
{
hw->hcfg_reg.fslssupp = 1;
}
static inline void usb_dwc_ll_hcfg_set_fsls_pclk_sel(usb_dwc_dev_t *hw)
{
hw... | 444 |
val = hw->hfir_reg.val;
hfir.hfirrldctrl = 0; //Disable dynamic loading
/*
Set frame interval to be equal to 1ms
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
*/
hfir.frint = ... | 444 |
ptxqspcavail;
}
static inline uint32_t usb_dwc_ll_ptxsts_get_ptxf_space_avail(usb_dwc_dev_t *hw)
{
return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxfspcavail);
}
// HAINT Register
static inline uint32_t usb_dwc_ll_haint_get_chan_intrs(usb_dwc_dev_t *hw)
{
return HAL_FORCE_READ_U32_REG_FIELD(hw->hain... | 444 |
prtspd;
}
static inline uint32_t usb_dwc_ll_hprt_get_test_ctl(usb_dwc_dev_t *hw)
{
return hw->hprt_reg.prttstctl;
}
static inline void usb_dwc_ll_hprt_set_test_ctl(usb_dwc_dev_t *hw, uint32_t test_mode)
{
usb_dwc_hprt_reg_t hprt;
hprt.val = hw->hprt_reg.val;
hprt.prttstctl = test_mode;
hw->hprt_re... | 444 |
val = hw->hprt_reg.val;
hprt.prtrst = reset;
hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
}
static inline bool usb_dwc_ll_hprt_get_port_reset(usb_dwc_dev_t *hw)
{
return hw->hprt_reg.prtrst;
}
static inline void usb_dwc_ll_hprt_set_port_suspend(usb_dwc_dev_t *hw)
{
usb_dwc_hprt_reg_t hprt... | 444 |
prtres;
}
static inline bool usb_dwc_ll_hprt_get_port_overcur(usb_dwc_dev_t *hw)
{
return hw->hprt_reg.prtovrcurract;
}
static inline bool usb_dwc_ll_hprt_get_port_en(usb_dwc_dev_t *hw)
{
return hw->hprt_reg.prtena;
}
static inline void usb_dwc_ll_hprt_port_dis(usb_dwc_dev_t *hw)
{
usb_dwc_hprt_reg_t hpr... | 444 |
val = hw->hprt_reg.val;
hw->hprt_reg.val = ((hprt.val & ~USB_DWC_LL_HPRT_ENA_MSK) & ~USB_DWC_LL_HPRT_W1C_MSK) | intr_mask;
}
//Per Channel registers
// HCCHARi Register
static inline void usb_dwc_ll_hcchar_enable_chan(volatile usb_dwc_host_chan_regs_t *chan)
{
chan->hcchar_reg.chena = 1;
}
static inline b... | 444 |
eptype = (uint32_t)type;
}
//Indicates whether channel is commuunicating with a LS device connected via a FS hub. Setting this bit to 1 will cause
//each packet to be preceded by a PREamble packet
static inline void usb_dwc_ll_hcchar_set_lspddev(volatile usb_dwc_host_chan_regs_t *chan, bool is_ls)
{
chan->hcchar_r... | 444 |
val = chan->hcint_reg.val;
chan->hcint_reg.val = hcint.val;
return hcint.val;
}
// HCINTMSKi Register
static inline void usb_dwc_ll_hcintmsk_set_intr_mask(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mask)
{
chan->hcintmsk_reg.val = mask;
}
// HCTSIZi Register
static inline void usb_dwc_ll_hcts... | 444 |
val = hctsiz.val;
}
static inline void usb_dwc_ll_hctsiz_init(volatile usb_dwc_host_chan_regs_t *chan)
{
usb_dwc_hctsiz_reg_t hctsiz;
hctsiz.val = chan->hctsiz_reg.val;
hctsiz.dopng = 0; //Don't do ping
/*
Set SCHED_INFO which occupies xfersize[7:0]
It is always set to 0xFF for full spe... | 444 |
val = hctsiz.val;
}
// HCDMAi Register
static inline void usb_dwc_ll_hcdma_set_qtd_list_addr(volatile usb_dwc_host_chan_regs_t *chan, void *dmaaddr, uint32_t qtd_idx)
{
usb_dwc_hcdma_reg_t hcdma;
/*
Set the base address portion of the field which is dmaaddr[31:9]. This is
the based address of the QT... | 444 |
//Note: 0x2 is reserved
#define USB_DWC_LL_QTD_STATUS_BUFFER 0x3 //AHB error occurred.
#define USB_DWC_LL_QTD_STATUS_NOT_EXECUTED 0x4 //QTD as never processed
/**
*/
static inline void usb_dwc_ll_qtd_set_in(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc)
{
qtd->buffer = data_... | 444 |
is_setup = 1;
}
if (hoc) {
qtd->in_non_iso.intr_cplt = 1; //We need to set this to distinguish between a halt due to a QTD
qtd->in_non_iso.eol = 1; //Used to halt the channel at this qtd
}
qtd->out_non_iso.active = 1;
}
/**
*/
static inline void usb_dwc_ll_qtd_set_null(usb_dwc_... | 444 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_GPTIMER_SUPPORTED
/**
*/
typedef soc_periph_gptimer_clk_src_t gptimer_clock_source_t;
#else
/**
*/
typedef int gptimer_clock_source_t;
#endif
/**
*/
typedef enum {... | 445 |
< Maximum number of events */
} gptimer_etm_event_type_t;
#ifdef __cplusplus
}
#endif
| 445 |
/*
*/
/
/
#pragma once
#include
#include
#include "hal/ecdsa_types.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
*/
typedef struct {
ecdsa_mode_t mode; /* Mode of operation */
ecdsa_curve_t curve; /* Curve to use for operation */
ecdsa_sha_mode_t sh... | 446 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "soc/soc_caps.h"
#if SOC_MEMPROT_SUPPORTED
#include "soc/memprot_defs.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_MEMPROT_SUPPORTED
/**
typedef enum {
MEMP_HAL_OK = 0,
MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE = 2,
MEMP_HAL_ERR_SPLIT_ADDR_INVALI... | 447 |
= 0) { return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; }
#define MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA 0x0 //0b00
#define MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA 0x2 //0b10
#define MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA 0x3 //0b11
#endif
#ifdef __cplusplus
... | 447 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "esp_assert.h"
/**
*/
typedef enum {
UART_NUM_0, /*! 2
UART_NUM_2, /*! 3
UART_NUM_3, /... | 448 |
< Xon flow control char*/
uint8_t xoff_char; /*!< Xoff flow control char*/
uint8_t xon_thrd; /*!< If the software flow control is enabled and the data amount in rxfifo is less than xon_thrd, an xon_char will be sent*/
uint8_t xoff_thrd; /*!< If the software flow control is enabled and the da... | 448 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
ECDSA_MODE_SIGN_VERIFY,
ECDSA_MODE_SIGN_GEN,
ECDSA_MODE_EXPORT_PUBKEY,
} ecdsa_mode_t;
/**
*/
typedef enum {
ECDSA_CURVE_SECP192R1,
ECDSA_CURVE_SECP256R1,
} ecdsa_curve_t;
/**
*/
typedef enum {
ECDSA_Z_USE_SH... | 449 |
/*
*/
/
/
#pragma once
#include
#include
#include
#include "hal/mpi_types.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
size_t mpi_hal_calc_hardware_words(size_t words);
/**
void mpi_hal_enable_hardware_hw_op(void);
/**
void mpi_hal_disable_hardware_hw_op(void);
/**
*/
void mpi... | 450 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
typedef enum {
HAL_DIV_ROUND_DOWN, /*!= 1/2, round down if fraction 2 when calculate the division with fractal part */
hal_utils_div_round_opt_t round_opt; /*!> 4) | ((n & 0x0f) > 2) | ((n & 0x33) > 1) | ((n & 0x55) << 1);... | 451 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "hal/color_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_LCD_I80_SUPPORTED || SOC_LCD_RGB_SUPPORTED
/**
*/
typedef soc_periph_lcd_clk_src_t lcd_clock_source_t;
#else
typedef int lcd_clock_source_t;
#endif // SOC_LCD_I80... | 452 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include "soc/soc_caps.h"
/**
*/
#if SOC_LP_TIMER_SUPPORTED
typedef struct {
union {
struct {
uint32_t lo: SOC_LP_TIMER_BIT_WIDTH_LO; /*!< Low part of counter value */
uint32_t hi: SOC_LP_TIMER_BIT_WIDTH_HI;... | 453 |
/*
*/
#pragma once
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_SDM_SUPPORTED
typedef soc_periph_sdm_clk_src_t sdm_clock_source_t; // sigma delta modulator clock source
#else
typedef int sdm_clock_source_t; // sigma delta modulator clock source, fallback t... | 454 |
/*
*/
#pragma once
#include
#include "hal/color_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
PPA_ENGINE_TYPE_SR, /*!< PPA Scaling and Rotating (SR) engine, used to perform scale_and_rotate */
PPA_ENGINE_TYPE_BLEND, /*!< PPA Blending engine, used to perform bl... | 455 |
< PPA SR color mode: RGB565 */
PPA_SR_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA SR color mode: YUV420 */
} ppa_sr_color_mode_t;
/**
*/
typedef enum {
PPA_BLEND_COLOR_MODE_ARGB8888 = COLOR_TYPE_ID(COLOR_SPACE_ARGB, COLOR_PIXEL_ARGB8888), /*!< PPA Blending colo... | 455 |
< PPA Blending color mode: A8, only available on blending foreground input */
PPA_BLEND_COLOR_MODE_A4 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A4), /*!< PPA Blending color mode: A4, only available on blending foreground input */
} ppa_blend_color_mode_t;
#ifdef __cplusplus
}
#endif
| 455 |
/*
*/
/
/
// The HAL layer for LEDC.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#include "soc/soc_caps.h"
#include "hal/ledc_types.h"
#if SOC_LEDC_SUPPORTED
#include "hal/ledc_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if... | 456 |
/*
*/
/
/
#pragma once
#include
#include
#include "hal/hmac_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void hmac_hal_start(void);
/**
*/
uint32_t hmac_hal_configure(hmac_hal_output_t config, uint32_t key_id);
/**
*/
void hmac_hal_write_one_block_512(const void *block);
/**
*/
void hmac_hal_w... | 457 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
PARLIO_SAMPLE_EDGE_NEG, /*! LSB
*/
typedef enum {
PARLIO_BIT_PACK_ORDER_LSB, /*!< Bit pack order: LSB */
PARLIO_BIT_PACK_ORDER_MSB, /*!< Bit pac... | 458 |
/*
*/
#pragma once
#include
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#if SOC_RMT_SUPPORTED
typedef soc_periph_rmt_clk_src_t rmt_clock_source_t;
#else
typedef int rmt_clock_source_t;
#endif
/**
*/
typedef union {
struct {
uint16_t duratio... | 459 |
/*
*/
/
/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include
#include "soc/soc_caps.h"
typedef struct {
uint8_t threshold;
bool enabled;
bool reset_enabled;
bool flash_power_down;
bool rf_power_down;
} brownout_hal_config_t;
/**
*/
void brownout_hal_config(con... | 460 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "esp_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
#if SOC_SYSTIMER_SUPPORTED
typedef struct {
union {
struct {
uint64_t lo : SOC_SYSTIMER_BIT_WIDTH_LO; /*!< Low part of counter value */
uint64_t hi : SOC_SYST... | 461 |
/*
*/
#pragma once
#include "hal/gdma_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
void gdma_axi_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr);
void gdma_axi_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma... | 462 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/*
Color Space
*/
/**
*/
typedef enum {
COLOR_SPACE_RAW = 1, ///> COLOR_PIXEL_FORMAT_BITWIDTH) & ((1 RGB conversion standard: BT.601 */
COLOR_CONV_STD_RGB_YUV_BT709, /*!RGB conversion standard: BT.709 */
} color_... | 463 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
typedef enum {
#if SOC_LEDC_SUPPORT_HS_MODE
LEDC_HIGH_SPEED_MODE = 0, /*! 6
LEDC_CHANNEL_6, /*! 14
LEDC_TIMER_15_BIT, /*!< LEDC PWM duty resolution of 15 bits ... | 464 |
/*
*/
#pragma once
#include
#include "hal/lcd_types.h"
#include "hal/mipi_dsi_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct dsi_host_dev_t *mipi_dsi_host_soc_handle_t;
/**
*/
typedef struct dsi_brg_dev_t *mipi_dsi_bridge_soc_handle_t;
/**
*/
typedef struct {
mipi_dsi_host_soc_hand... | 465 |
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