text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
/*
*/
/
/
#pragma once
#include "stdint.h"
#include
#include "soc/soc_caps.h"
#include "hal/ecc_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void ecc_hal_set_mode(ecc_mode_t mode);
/**
*/
void ecc_hal_set_curve(ecc_curve_t curve);
/**
void ecc_hal_start_calc(void);
/**
*/
int ecc_hal_is_calc_fin... | 466 |
/*
*/
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/reg_base.h"
/* Do not use INTC on targets that have harware CLIC */
#if SOC_CPU_HAS_FLEXIBLE_INTC && !SOC_INT_CLIC_SUPPORTED
#include "soc/interrupt_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
FORCE_INLINE_ATTR void... | 467 |
/*
*/
#pragma once
#include
#include "usb_dwc_types.h"
#include "usb_phy_types.h"
#include "soc/soc_caps.h"
#if SOC_USB_OTG_SUPPORTED
#include "soc/usb_wrap_struct.h"
#endif
#if SOC_USB_SERIAL_JTAG_SUPPORTED
#include "soc/usb_serial_jtag_struct.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_USB_OTG_SUPP... | 468 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void efuse_hal_get_mac(uint8_t *mac);
/**
*/
uint32_t efuse_hal_chip_revision(void);
/**
*/
uint32_t efuse_hal_blk_version(void);
/**
*/
bool efuse_hal_flash_encryption_enabled(void);
/**
*/
boo... | 469 |
/*
*/
#pragma once
#include "esp_err.h"
#include "soc/soc_caps.h"
#include "hal/dma_types.h"
#include "hal/adc_types.h"
#include "hal/adc_hal_common.h"
#if SOC_ADC_DMA_SUPPORTED
#include "hal/adc_ll.h"
#endif
#if SOC_GDMA_SUPPORTED
#include "hal/gdma_ll.h"
#endif
#if CONFIG_IDF_TARGET_ESP32S2
//ADC utilises SPI3 D... | 470 |
SOC_GDMA_SUPPORTED
/**
*/
intptr_t adc_hal_get_desc_addr(adc_hal_dma_ctx_t *hal);
/**
*/
bool adc_hal_check_event(adc_hal_dma_ctx_t *hal, uint32_t mask);
#endif
/**
*/
adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len);
/**
... | 470 |
/*
*/
/
/
/*
*/
#pragma once
#include "esp_types.h"
#include "esp_err.h"
#include "soc/soc_caps.h"
#include "soc/gdma_channel.h"
#include "hal/spi_types.h"
#include "hal/dma_types.h"
#if SOC_GPSPI_SUPPORTED
#include "hal/spi_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_GPSPI_SUPPORTED
//NOTE!! ... | 471 |
uint32_t rx_dma_chan; ///< RX DMA channel used.
bool append_mode; ///< True for DMA append mode, false for segment mode
uint32_t spics_io_num; ///< CS GPIO pin for this device
uint8_t mode; ... | 471 |
spi_slave_hd_hal_desc_append_t *dmadesc_rx; ///< Head of the RX DMA descriptors.
/* address of the hardware */
spi_dev_t *dev; ///< Beginning address of the peripheral registers.
spi_dma_dev_t *dma_in; ///< Address of... | 471 |
Calculated from ``bus_max_transfer_size``.
spi_slave_hd_hal_desc_append_t *tx_cur_desc; ///< Current TX DMA descriptor that could be linked (set up).
spi_slave_hd_hal_desc_append_t *tx_dma_head; ///< Head of the linked TX DMA descriptors which are not used by hardware
spi_slave_hd_hal... | 471 |
*/
uint32_t intr_not_triggered;
bool tx_dma_started;
bool rx_dma_started;
} spi_slave_hd_hal_context_t;
/**
*/
void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config);
/**
*/
bo... | 471 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/** RTCIO output/input mode type. */
typedef enum {
RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad input */
RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad output */
RTC_GPIO_MODE_INPUT_OUTPUT, /*!< Pad input + output */
RTC_GPIO_MODE_DISABLED, /*!< Pad (outp... | 472 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
MODEM_CLOCK_DOMAIN_MODEM_APB = 0,
MODEM_CLOCK_DOMAIN_MODEM_PERIPH,
MODEM_CLOCK_DOMAIN_WIFI,
MODEM_CLOCK_DOMAIN_BT,
MODEM_CLOCK_DOMAIN_MODEM_FE,
MODEM_CLOCK_DOMAIN_IEEE802154,
MODEM_CLOCK_DOMAIN_LP_APB,
MODEM_CLO... | 473 |
/*
*/
// The HAL layer for MODEM CLOCK
#pragma once
#include "soc/soc_caps.h"
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
#include "hal/modem_syscon_ll.h"
#include "hal/modem_lpcon_ll.h"
#include "hal/modem_clock_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
modem_syscon_dev_t *syscon_dev;
modem... | 474 |
/*
*/
/
/
#pragma once
#include
#include
#include
#include "soc/soc_caps.h"
#include "hal/aes_types.h"
#if SOC_AES_SUPPORTED
#include "hal/aes_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
uint8_t aes_hal_setkey(const uint8_t *key, size_t key_bytes, int mode);
/**
*/
void aes_hal_transform_bl... | 475 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "hal/color_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
Misc
*/
#if SOC_ISP_SUPPORTED
typedef soc_periph_isp_clk_src_t isp_clk_src_t; ///< Clock source type of ISP
#else
typedef int ... | 476 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
PCNT_CHANNEL_LEVEL_ACTION_KEEP, /*! decrease, decrease -> increase) */
PCNT_CHANNEL_LEVEL_ACTION_HOLD, /*!0 */
PCNT_UNIT_ZERO_CROSS_NEG_ZERO, /*!0 */
PCNT_UNIT_ZERO_CROSS_NEG_POS, /*!+M */
PCNT_UNIT_ZERO_CROS... | 477 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ECC_MODE_POINT_MUL = 0x0, // (Rx, Ry) = K * (Px, Py)
ECC_MODE_INVERSE_MUL, // R = K^(-1) * Py
ECC_MODE_VERIFY, // Check if (Px, Py) are points on the curve
ECC_MODE_VERIFY_T... | 478 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#include "hal/color_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#define JPEG_HUFFMAN_BITS_LEN_TABLE_LEN (16)
#define JPEG_HUFFMAN_AC_VALUE_TABLE_LEN (256)
#define JPEG_HUFFMAN_DC_VALUE_TABLE_LEN (16)
#define JPEG_QUANTIZATION... | 479 |
< Sample by YUV444 */
JPEG_DOWN_SAMPLING_YUV422 = 1, /*!< Sample by YUV422 */
JPEG_DOWN_SAMPLING_YUV420 = 2, /*!< Sample by YUV420 */
JPEG_DOWN_SAMPLING_GRAY = 3, /*!< Sample the gray picture */
JPEG_DOWN_SAMPLING_MAX, /*!< Max value of sample enumeration */
} jpeg_d... | 479 |
/*
*/
#pragma once
#include
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
*/
enum {
/* These codes should be consistent with esp_err_t errors. However, error codes with the same values are not
ESP_ERR_FLASH_SIZE_NOT_MATCH = ESP_ERR_INVALID_SIZE, ///spi field).
#define ESP_ERR_FLASH_UNS... | 480 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
CACHE_TYPE_DATA,
CACHE_TYPE_INSTRUCTION,
CACHE_TYPE_ALL //This means both ICache and DCache will be used. On some chips, I/D are controlled by a shared Cache. Also use this enum under this condition. See... | 481 |
/*
*/
#pragma once
#include
#include
#include "hal/hal_utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct lcd_cam_dev_t *lcd_soc_handle_t;
/**
*/
typedef struct {
lcd_soc_handle_t dev; // SOC layer handle
} lcd_hal_context_t;
/**
*/
void lcd_hal_init(lcd_hal_context_t *hal, int id);
... | 482 |
/*
*/
/
/
#pragma once
#include
#include
#include
#include "hal/ds_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void ds_hal_start(void);
/**
*/
void ds_hal_finish(void);
/**
*/
void ds_hal_configure_iv(const uint32_t *iv);
/**
*/
void ds_hal_write_message(const uint8_t *msg, size_t size);
/*... | 483 |
/*
*/
#pragma once
#include
#include
#include
#include
#include "esp_bit_defs.h"
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
I2S_SLOT_MODE_MONO = 1, /*! 1
/* The following enumerators are only used in multi-line PDM RX ... | 484 |
< I2S PDM receives the right slot on line 3 */
I2S_PDM_RX_LINE3_SLOT_LEFT = BIT(7), /*!< I2S PDM receives the left slot on line 3 */
I2S_PDM_LINE_SLOT_ALL = 0x00ff, /*!< I2S PDM receives all slots */
#endif
} i2s_pdm_slot_mask_t;
#if SOC_I2S_SUPPORTS_TDM
/**
*/
typedef enum ... | 484 |
< I2S slot 10 enabled */
I2S_TDM_SLOT11 = BIT(11), /*!< I2S slot 11 enabled */
I2S_TDM_SLOT12 = BIT(12), /*!< I2S slot 12 enabled */
I2S_TDM_SLOT13 = BIT(13), /*!< I2S slot 13 enabled */
I2S_TDM_SLOT14 = BIT(14), /*!< I2S slot 14 enabled */
I2S_TDM... | 484 |
/*
*/
/
/
// The HAL layer for UART.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/uart_ll.h"
#include "hal/uart_types.h"
/**
*/
typedef struct {
uart_dev_t *dev;
} uart_hal_con... | 485 |
/*
*/
#pragma once
#include
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src);
/**
*/
uint32_t clk_hal_cpu_get_freq_hz(void);
/**
*/
uint32_t clk_hal_apb_get_freq_hz(void);
/**
*/
uint... | 486 |
/*
*/
#pragma once
#include
#include
#include
#include "soc/soc_caps.h"
#include "soc/soc.h"
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_LP_TIMER_SUPPORTED
/*
*/
void lp_timer_hal_set_alarm_target(uint8_t timer_id, uint64_t value);
/**
*/
u... | 487 |
/*
*/
/*
Note: This header file contains USB2.0 related types and macros that can be used by code specific to the DWC_OTG
controller (i.e., the HW specific layers of the USB host stack). Thus, this header is only meant to be used below (and
including) the HAL layer. For types and macros that are HW implementation agn... | 488 |
/*
*/
/
/
// The HAL layer for sigma delta modulator.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef struct gpio_sd_dev_t *sdm_soc_handle_t; // Sigma-Delta SOC layer handle
/**
*/
typedef ... | 489 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
MMU_MEM_CAP_EXEC = BIT(0),
MMU_MEM_CAP_READ = BIT(1),
MMU_MEM_CAP_WRITE = BIT(2),
MMU_MEM_CAP_32BIT = BIT(3),
MMU_MEM_CAP_8BIT = BIT(4),
} mmu_mem_caps_t;
/**
*/
typedef enum {
MMU_PAGE_8... | 490 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
APM_REGION_PMS_X = 0x1, /*!< Region executive authority. */
APM_REGION_PMS_W = 0x2, /*!< Region write authority. */
APM_REGION_PMS_R = 0x4, /*!< Region read authority. */
} apm_region_pms_t;
#ifdef __cplusplus
}
#endif
| 491 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Mask of interrupts sending to the host.
typedef enum {
SDIO_SLAVE_HOSTINT_BIT0 = BIT(0), ///< General purpose interrupt bit 0.
SDIO_SLAVE_HOSTINT_BIT1 = BIT(1),
SDIO_SLAVE_HOSTINT_BIT2 = BIT(2),
SDIO_SLAVE_HOS... | 492 |
} sdio_slave_sending_mode_t;
#ifdef __cplusplus
}
#endif
| 492 |
/*
*/
#pragma once
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WDT_RWDT = 0, /*!< RTC Watchdog Timer (RWDT) */
WDT_MWDT0, /*!< Main System Watchdog Timer (MWDT) of Timer Group 0 */
WDT_MWDT1, /*!< Main System Watchdog Timer (MWDT) of Timer Group 1 */... | 493 |
*/
WDT_STAGE_ACTION_RESET_RTC = 4, /*!< Reset the main system and the RTC when the stage expires. ONLY AVAILABLE FOR RWDT */
} wdt_stage_action_t;
/**
*/
typedef enum {
WDT_RESET_SIG_LENGTH_100ns = 0, /*!< 100 ns */
WDT_RESET_SIG_LENGTH_200ns = 1, /*!< 200 ns */
WDT_RESET_SIG_LENGTH_300ns =... | 493 |
/*
*/
/
/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct mcpwm_dev_t *mcpwm_soc_handle_t; // MCPWM SOC layer handle
/**
*/
typedef struct {
int group_id; // Indicate the MCPWM hardware group
} mcpwm_hal_init_config_t;
/**
*/
typedef struct {
mcpwm_soc_handle_t dev; // MC... | 494 |
/*
*/
/
/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct timg_dev_t *gptimer_soc_handle_t; // GPTimer SOC layer handle
/**
*/
typedef struct {
gptimer_soc_handle_t dev; // Timer SOC layer handle (i.e. register base address)
uint32_t timer_id; // Timer ID (i.e. index... | 495 |
/*
*/
/
/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct soc_etm_dev_t *etm_soc_handle_t; // ETM SOC layer handle
/**
*/
typedef struct {
etm_soc_handle_t regs; /*!< ETM Register base address */
} etm_hal_context_t;
/**
*/
void etm_hal_init(etm_hal_context_t *hal);
/**
*/
... | 496 |
/*
*/
// Though the UHCI driver hasn't been published, some types are defined here
// for users to develop over the HAL. See example: controller_hci_uart_esp32c3
#pragma once
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct {
uint8_t seper_chr; /*!< escape sequence ch... | 497 |
/*
*/
#include
#include "esp_err.h"
#include "hal/mpu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void mpu_hal_set_region_access(int id, mpu_access_t access);
#ifdef __cplusplus
}
#endif
| 498 |
/*
*/
/
/
// The HAL layer for SPI master (common part)
// SPI HAL usages (without DMA):
// 1. initialize the bus
// 2. setup the clock speed (since this takes long time)
// 3. call setup_device to update parameters for the specific device
// 4. call setup_trans to update parameters for the specific transaction
//... | 499 |
uint32_t duty_cycle; ///< Expected duty cycle of SPI clock
uint32_t input_delay_ns; /**< Maximum delay between SPI launch clock and the data to be valid.
*/
bool use_gpio; ///< True if the GPIO matrix is used, otherwise... | 499 |
Note when the compensation is enabled, some extra dummy bits may be appended.
int tx_bitlen; ///< TX length, in bits
int rx_bitlen; ///< RX length, in bits
uint64_t addr; ///< Address value to be sent
uint8_t *send_buffer; ///... | 499 |
Device specific
spi_hal_timing_conf_t timing_conf; /**< This structure holds the pre-calculated timing configuration for the device
*/
struct {
uint32_t sio : 1; ///< Whether to use SIO mode, device specific
uint32_t half_duplex : 1; ... | 499 |
/*
*/
/
/
#pragma once
#include
#include "hal/isp_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct {
void *hw; ///< Beginning address of the ISP registers
} isp_hal_context_t;
/**
*/
void isp_hal_init(isp_hal_context_t *hal, int isp_id);
/*
AF
*/
/**
*/
v... | 500 |
/*
*/
/
/
// The HAL layer for GPIO
#pragma once
#include "soc/gpio_periph.h"
#include "soc/soc_caps.h"
#include "hal/gpio_ll.h"
#include "hal/gpio_types.h"
#ifdef __cplusplus
extern "C" {
#endif
// Get GPIO hardware instance with giving gpio num
#define GPIO_HAL_GET_HW(num) GPIO_LL_GET_HW(num)
/**
*/
typede... | 501 |
SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
*/
#define gpio_hal_deep_sleep_hold_en(hal) gpio_ll_deep_sleep_hold_en((hal)->dev)
/**
*/
#define gpio_hal_deep_sleep_hold_dis(hal) gpio_ll_deep_sleep_hold_dis((hal)->dev)
/**
*/
#define gpio_hal_deep_sleep_hold_is_en(hal) gpio_ll_deep_sleep_hold_is_en((hal)->dev)
#en... | 501 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GDMA_TRIG_PERIPH_M2M, /*!< GDMA trigger peripheral: M2M */
GDMA_TRIG_PERIPH_UHCI, /*!< GDMA trigger peripheral: UHCI */
GDMA_TRIG_PERIPH_SPI, /*!< GDMA trigger peripheral: SPI */
GDMA_TRIG_PERIPH_I2S, /*!< GDMA trigg... | 502 |
< GDMA channel direction: TX */
GDMA_CHANNEL_DIRECTION_RX, /*!< GDMA channel direction: RX */
} gdma_channel_direction_t;
/**
*/
typedef enum {
GDMA_ETM_EVENT_EOF, /*!< Event that the GDMA engine meets EOF descriptor */
GDMA_ETM_EVENT_MAX, /*!< Maximum number of events */
} gdma_etm_event_type_t;
/**
*/... | 502 |
/*
*/
#pragma once
#include
#include
#include "esp_assert.h"
#include "esp_err.h"
#include "hal/eth_types.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_EMAC_SUPPORTED
#include "hal/emac_ll.h"
/**
*/
#define STR(s) #s
#define TYPE_SIZE_ERR_MSG(DATATYPE, SIZE) #DATATYPE " should occ... | 503 |
/*
*/
#pragma once
#include
#include "esp_assert.h"
#include "hal/assert.h"
#include "hal/color_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct dma2d_descriptor_align8_s dma2d_descriptor_align8_t;
struct dma2d_descriptor_align8_s {
struct {
uint32_t vb_size : 14; /*!< Verti... | 504 |
< Whether to enable 2D functionality */
uint32_t suc_eof : 1; /*!< Whether the descriptor is the last one in the link */
uint32_t owner : 1; /*!< Who is allowed to access the buffer that this descriptor points to, select DMA2D_DESCRIPTOR_BUFFER_OWNER_CPU or DMA2D_DESCRIPTOR_BUFFER_OWNE... | 504 |
< Number of bytes per pixel (make use of dma2d_desc_pixel_format_to_pbyte_value to get the value)
When dma2d_en field is 0, this field has no use */
}; /*!< Descriptor Word 1 */
struct {
uint32_t y : 14; /*!< The y-co... | 504 |
< Descriptor Word 2 */
void *buffer; /*!< Pointer to the buffer (of ha * va picture)
For RX buffer, there is 4-byte alignment addr and size requirement (spiram and axi bus restriction, otherwises, could overwrite other data or be overwritten) */
dma... | 504 |
< 2D-DMA data block single R/W mode, only r/w one hb * vb block */
#define DMA2D_DESCRIPTOR_BLOCK_RW_MODE_MULTIPLE (1) /*!< 2D-DMA data block multiple R/W mode, continues r/w hb * vb blocks until the ha * va picture is done */
#define DMA2D_DESCRIPTOR_PBYTE_0B5_PER_PIXEL (0) /*!< 2D-DMA ... | 504 |
< 2D-DMA trigger peripheral: M2M */
DMA2D_TRIG_PERIPH_JPEG_ENCODER, /*!< 2D-DMA trigger peripheral: JPEG Encoder */
DMA2D_TRIG_PERIPH_JPEG_DECODER, /*!< 2D-DMA trigger peripheral: JPEG Decoder */
DMA2D_TRIG_PERIPH_PPA_SR, /*!< 2D-DMA trigger peripheral: PPA SR engine */
DMA2D_TRIG_PERI... | 504 |
< 2D-DMA block size: 128 bytes */
DMA2D_DATA_BURST_LENGTH_INVALID, /*!< Invalid 2D-DMA block size */
} dma2d_data_burst_length_t;
/**
*/
typedef enum {
DMA2D_MACRO_BLOCK_SIZE_NONE, /*!< 2D-DMA no macro block */
DMA2D_MACRO_BLOCK_SIZE_8_8, /*!< 2D-DMA 8 pixel x 8 pixel macro block */
... | 504 |
< 2D-DMA pixel data scrambled as BYTE0-2-1 */
DMA2D_SCRAMBLE_ORDER_BYTE0_1_2, /*!< 2D-DMA pixel data scrambled as BYTE0-1-2 */
DMA2D_SCRAMBLE_ORDER_INVALID, /*!< Invalid 2D-DMA pixel data scramble order */
} dma2d_scramble_order_t;
//BT601//
// Y = 16 + 0.257 * R + 0.504 * g + 0.098 * b ... | 504 |
164 *(Y - 16) + 2.114 *(Cb - 128) //
//BT709//
// 256 * Q = A[9:0] * x + B[10:0] * y + C[9:0] * z + D[17:0]
#define DMA2D_COLOR_SPACE_CONV_PARAM_RGB2YUV_BT601 \
{ \
{ 66, 129, 25, 4096}, \
{ -38, -74, 112, 32768... | 504 |
< 2D-DMA TX perform no CSC */
DMA2D_CSC_TX_SCRAMBLE, /*!< 2D-DMA TX perform only data scramble */
DMA2D_CSC_TX_RGB888_TO_RGB565, /*!< 2D-DMA TX perform RGB888 to RGB565 conversion */
DMA2D_CSC_TX_RGB565_TO_RGB888, /*!< 2D-DMA TX perform RGB565 to RGB888 convers... | 504 |
< 2D-DMA TX perform YUV444 to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_TX_YUV422_TO_RGB888_601, /*!< 2D-DMA TX perform YUV422-MIPI to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_TX_YUV422_TO_RGB888_709, /*!< 2D-DMA TX perform YUV422-MIPI to RGB888 conversion (follow BT... | 504 |
< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT709 standa... | 504 |
< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT709 standa... | 504 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include
#include
#include
#include "esp_attr.h"
#define KEY_MGR_ASSIST_INFO_LEN 64
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
ESP_KEY_MGR_STATE_IDLE = 0, /* Key Manager is idle */
ESP_KEY_MGR_STATE_LOAD = ... | 505 |
/*
*/
#include
#include "hal/assert.h"
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/reg_base.h"
#if SOC_INT_CLIC_SUPPORTED
#include "soc/clic_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RV_TOTAL_INT_COUNT 48
/**
*/
FORCE_INLINE_ATTR void interrupt_clic_ll_route... | 506 |
= 0;
}
/**
FORCE_INLINE_ATTR void interrupt_clic_ll_set_vectored(int rv_int_num, bool vectored)
{
REG_SET_FIELD(CLIC_INT_CTRL_REG(rv_int_num), CLIC_INT_ATTR_SHV, vectored ? 1 : 0);
}
#ifdef __cplusplus
}
#endif
#endif // SOC_INT_PLIC_SUPPORTED
| 506 |
/*
*/
#pragma once
#include "hal/gdma_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
void gdma_ahb_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr);
void gdma_ahb_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma... | 507 |
/*
*/
/
/
// The HAL layer for I2C
#pragma once
#include "soc/soc_caps.h"
#include "hal/i2c_types.h"
#if SOC_I2C_SUPPORTED
#include "hal/i2c_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_I2C_SUPPORTED
/**
*/
typedef struct {
i2c_dev_t *dev;
} i2c_hal_context_t;
/**
*/
typedef struct {
... | 508 |
..) do {(void)__DECLARE_RCC_ATOMIC_ENV; _i2c_hal_set_bus_timing(__VA_ARGS__);} while(0)
#else
#define i2c_hal_set_bus_timing(...) _i2c_hal_set_bus_timing(__VA_ARGS__)
#endif
/**
*/
void i2c_hal_master_fsm_rst(i2c_hal_context_t *hal);
/**
*/
void i2c_hal_master_handle_tx_event(i2c_hal_context_t *hal, i2c_intr_even... | 508 |
..) do {(void)__DECLARE_RCC_ATOMIC_ENV; _i2c_hal_deinit(__VA_ARGS__);} while(0)
#else
#define i2c_hal_deinit(...) _i2c_hal_deinit(__VA_ARGS__)
#endif
/**
*/
void i2c_hal_master_trans_start(i2c_hal_context_t *hal);
/**
*/
void i2c_hal_get_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *timing_config... | 508 |
/*
*/
/
/
// The HAL layer for RTC IO master (common part)
#pragma once
#include
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#if SOC_RTCIO_PIN_COUNT > 0
#include "soc/rtc_io_periph.h"
#include "hal/rtc_io_ll.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#include "hal/rtc_io_types.h"
#endif
#endif //SOC_RTCIO_PIN... | 509 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/gpio_num.h"
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
GPIO_PORT_0 = 0,
GPIO_PORT_MAX,
} gpio_port_t;
#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG
#define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG
#define GP... | 510 |
< Disable GPIO interrupt */
GPIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */
GPIO_INTR_NEGEDGE = 2, /*!< GPIO interrupt type : falling edge */
GPIO_INTR_ANYEDGE = 3, /*!< GPIO interrupt type : both rising and falling ed... | 510 |
< GPIO mode : input only */
GPIO_MODE_OUTPUT = GPIO_MODE_DEF_OUTPUT, /*!< GPIO mode : output only mode */
GPIO_MODE_OUTPUT_OD = ((GPIO_MODE_DEF_OUTPUT) | (GPIO_MODE_DEF_OD)), /*!... | 510 |
< Enable GPIO pull-down resistor */
} gpio_pulldown_t;
typedef enum {
GPIO_PULLUP_ONLY, /*!< Pad pull up */
GPIO_PULLDOWN_ONLY, /*!< Pad pull down */
GPIO_PULLUP_PULLDOWN, /*!< Pad pull up + pull down*/
GPIO_FLOATING, /*!< Pad fl... | 510 |
< Pad input hysteresis disable by software */
GPIO_HYS_SOFT_ENABLE, /*!< Pad input hysteresis enable by software */
} gpio_hys_ctrl_mode_t;
#endif
#ifdef __cplusplus
}
#endif
| 510 |
/*
*/
/
/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include "soc/soc_caps.h"
#include "hal/wdt_types.h"
#include "hal/mwdt_ll.h"
#include "hal/rwdt_ll.h"
/**
*/
typedef struct {
wdt_inst_t inst; /**< Which WDT instance this HAL context is using (i.e. MWDT0, MWDT1, RWDT)*/... | 511 |
/*
*/
/
/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct rmt_dev_t *rmt_soc_handle_t; // RMT SOC layer handle
/**
*/
typedef struct {
rmt_soc_handle_t regs; /*!< RMT Register base address */
} rmt_hal_context_t;
/**
*/
void rmt_hal_init(rmt_hal_context_t *hal);
/**
*/
void... | 512 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_ADC_ARBITER_SUPPORTED
/*
Arbiter
*/
/**
*/
typedef enum {
ADC_ARB_MODE_SHIELD, ///< Force shield arbiter, Select the highest priority controller to work
ADC_ARB_MODE_FIX, ///< Fixed priority switch controller mo... | 513 |
pwdet_pri = 2, \
}
#endif //#if SOC_ADC_ARBITER_SUPPORTED
#ifdef __cplusplus
}
#endif
| 513 |
/*
*/
#pragma once
#include "sdkconfig.h"
/* Use enum from rom for backwards compatibility */
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/sha.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/sha.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/sha.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp... | 514 |
/*
*/
/
/
#pragma once
#include
#include "hal/parlio_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct parl_io_dev_t *parlio_soc_handle_t; // Parallel IO SOC layer handle
/**
*/
typedef struct {
parlio_soc_handle_t regs; /*!< Parallel IO Register base address */
} parlio_hal_context_t;
/**
... | 515 |
/*
*/
#pragma once
#include
#include
#include "hal/cache_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void cache_hal_init(void);
/**
*/
void cache_hal_disable(uint32_t cache_level, cache_type_t type);
/**
*/
void cache_hal_enable(uint32_t cache_level, cache_type_t type);
/**
*/
void cache_hal_s... | 516 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include "esp_assert.h"
#include "rom/km.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HUK_INFO_SIZE 384
#define HUK_RISK_ALERT_LEVEL 4
/**
*/
typedef enum {
ESP_HUK_MODE_RECOVERY = 0, /* HUK recovery mode */
... | 517 |
/*
*/
#pragma once
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#if SOC_TEMP_SENSOR_SUPPORTED
typedef soc_periph_temperature_sensor_clk_src_t temperature_sensor_clk_src_t;
#else
typedef int temperature_sensor_clk_src_t;
#endif // SOC_TEMP_SENSOR_SUPPORTED
... | 518 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#if SOC_XT_WDT_SUPPORTED
#include "hal/xt_wdt_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_XT_WDT_SUPPORTED
typedef struct {
rtc_cntl_dev_t *dev; /* Pointer to the RTC register struct */
} xt_wdt_hal_context_t; /* HAL con... | 519 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
HMAC_OUTPUT_USER = 0, /**< Let user provide a message and read the HMAC result */
HMAC_OUTPUT_DS = 1, /**< HMAC is provided to the DS peripheral to decrypt DS private key parameters */
HMAC_OUTPUT_JTAG_... | 520 |
/*
*/
#pragma once
#include
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void mmu_hal_init(void);
/**
*/
void mmu_hal_unmap_all(void);
/**
*/
uint32_t mmu_hal_pages_to_bytes(uint32_t mmu_id, uint32_t page_num);
/**
*/
uint32_t mmu_hal_bytes_to_pages(uint32_t mmu_id, uint32_t byt... | 521 |
/*
*/
/
/
// The HAL layer for SPI Flash Encryption
#include "hal/spi_flash_encrypted_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void spi_flash_encryption_hal_enable(void);
/**
*/
void spi_flash_encryption_hal_disable(void);
/**
*/
void spi_flash_encryption_hal_prepare(uint32_t address, const uint3... | 522 |
/*
*/
/*
Note: This header file contains USB2.0 related types and macros that can be used by code specific to the DWC_OTG
controller (i.e., the HW specific layers of the USB host stack). Thus, this header is only meant to be used below (and
including) the HAL layer. For types and macros that are HW implementation agn... | 523 |
5 Mbit/s) */
USB_PHY_SPEED_FULL, /**< USB Full Speed (12 Mbit/s) */
USB_PHY_SPEED_HIGH, /**< USB High Speed (480 Mbit/s) */
USB_PHY_SPEED_MAX,
} usb_phy_speed_t;
#ifdef __cplusplus
}
#endif
| 523 |
/*
*/
#pragma once
#include
#include
#include "esp_attr.h"
#include "soc/soc_caps.h"
#if SOC_ASSIST_DEBUG_SUPPORTED
#include "hal/assist_debug_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_ASSIST_DEBUG_SUPPORTED
FORCE_INLINE_ATTR void assist_debug_hal_sp_int_enable(uint32_t core_id)
{
assist_de... | 524 |
/*
*/
/
/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef struct pcnt_dev_t *pcnt_soc_handle_t; // PCNT SOC layer handle
/**
*/
typedef struct {
pcnt_soc_handle_t dev; // PCNT SOC layer handle
} pcnt_hal_context_t;
/**
*/
void pcnt_hal_init(pcnt_hal_context_t *hal, int group_id);
#ifdef __cpl... | 525 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
/*
This header is shared across all targets. Resolve to an empty header for targets
that don't support USB OTG.
*/
#if SOC_USB_OTG_SUPPORTED
#include
#include
#include "hal/usb_dwc_ll.h"
#include "hal/usb_dwc_types.h"
#include "hal/assert.h"
#endif // SOC_USB_OTG_SUPPOR... | 526 |
num_allocd == 0); //Cannot reset if there are still allocated channels
usb_dwc_ll_hprt_set_port_reset(hal->dev, enable);
}
/**
*/
void usb_dwc_hal_port_enable(usb_dwc_hal_context_t *hal);
/**
*/
static inline void usb_dwc_hal_port_disable(usb_dwc_hal_context_t *hal)
{
usb_dwc_ll_hprt_port_dis(hal->dev);
}
... | 526 |
= NULL);
usb_dwc_ll_hflbaddr_set_base_addr(hal->dev, (uint32_t)hal->periodic_frame_list);
usb_dwc_ll_hcfg_set_num_frame_list_entries(hal->dev, hal->frame_list_len);
usb_dwc_ll_hcfg_en_perio_sched(hal->dev);
hal->flags.periodic_sched_enabled = 1;
}
/**
*/
static inline void usb_dwc_hal_port_periodic_di... | 526 |
dbnc_lock_enabled = 0;
//Clear Conenction and disconenction interrupt in case it triggered again
usb_dwc_ll_gintsts_clear_intrs(hal->dev, USB_DWC_LL_INTR_CORE_DISCONNINT);
usb_dwc_ll_hprt_intr_clear(hal->dev, USB_DWC_LL_INTR_HPRT_PRTCONNDET);
//Reenable the hprt (connection) and disconnection interrupts... | 526 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.