text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
chan_obj->flags.active);
usb_dwc_ll_hcchar_set_dir(chan_obj->regs, is_in);
}
/**
*/
static inline void usb_dwc_hal_chan_set_pid(usb_dwc_hal_chan_t *chan_obj, int pid)
{
//Cannot change pid whilst channel is still active or in error
HAL_ASSERT(!chan_obj->flags.active);
//Update channel object and set t... | 526 |
active = 0;
}
/**
*/
static inline usb_dwc_hal_chan_error_t usb_dwc_hal_chan_get_error(usb_dwc_hal_chan_t *chan_obj)
{
return chan_obj->error;
}
// Transfer Descriptor List
/**
*/
static inline void usb_dwc_hal_xfer_desc_fill(void *desc_list, uint32_t desc_idx, uint8_t *xfer_data_buff, int xfer_len, uint32_t... | 526 |
/*
*/
/
/
// The HAL layer for SPI Flash (common part)
#pragma once
#include "hal/spi_flash_ll.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include "esp_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Hardware host-specific constants */
#define SPI_FLASH_HAL_MAX_WRITE_BYTES 64
#define SPI... | 527 |
};
spi_flash_ll_clock_reg_t clock_conf; ///< Pre-calculated clock configuration value
esp_flash_io_mode_t base_io_mode; ///< Default IO mode mask for common commands
uint32_t flags; ///< Flags for configurations with one set of driver code. (e.g. QPI mode, auto-suspend mode, 64-bit... | 527 |
int freq_mhz; /// Flash clock frequency.
uint8_t tsus_val; ///< Tsus value of suspend (us)
} spi_flash_hal_context_t;
ESP_STATIC_ASSERT(sizeof(spi_flash_hal_context_t) == 48, "size of spi_flash_hal_context_t incorrect. Please check data compatibility with the ROM");
/// This struct provide M... | 527 |
};
spi_flash_hal_timing_config_t timing_reg; ///< Reconfigure timing tuning regs.
};
bool iomux; ///< Whether the IOMUX is used, used for timing compensation.
int input_delay_ns; ///< Input delay on the MISO pin after the launch clock, used for timing compensation.
enum... | 527 |
int clock_src_freq; ///< SPI flash clock source (MHZ).
uint8_t tsus_val; ///< Tsus value of suspend (us)
} spi_flash_hal_config_t;
/**
*/
esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_hal_config_t *cfg);
/**
*/
esp_err_t spi_flash_hal_device_config(spi_flash_host_in... | 527 |
/*
*/
#pragma once
#include
#include
#include "hal/systimer_types.h"
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct systimer_dev_t *systimer_soc_handle_t; // systimer SOC layer handle
// the definitions of the following functions are provided by ... | 528 |
< function to convert microseconds to ticks */
} systimer_hal_tick_rate_ops_t;
/**
*/
typedef soc_periph_systimer_clk_src_t systimer_clock_source_t;
/**
*/
void systimer_hal_init(systimer_hal_context_t *hal);
/**
*/
void systimer_hal_deinit(systimer_hal_context_t *hal);
/**
*/
void systimer_hal_set_tick_rate_op... | 528 |
SOC_SYSTIMER_FIXED_DIVIDER
/**
*/
void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_source, uint32_t steps);
#endif
/**
*/
systimer_clock_source_t systimer_hal_get_clock_source(systimer_hal_context_t *hal);
#ifdef __cplusplus
}
#endif
| 528 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
PMU_MODE_HP_ACTIVE = 0, /*!< PMU in HP_ACTIVE mode */
#if !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-5731 Use a soc caps
PMU_MODE_HP_MODEM, /*!< PMU in HP_MODEM mode... | 529 |
....
typedef enum {
PMU_HP_PD_TOP = 0, /* Power domain of digital top */
PMU_HP_PD_CNNT = 1, /* Power domain of HP CPU */
PMU_HP_PD_HPMEM = 2, /* HP_MEM */
PMU_HP_PD_RESERVED, /* Reserved power domain*/
PMU_HP_PD_MAX
} pmu_hp_power_domain_t;
#endif
#ifdef __cplusplus
}
#e... | 529 |
/*
*/
#pragma once
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER || (SOC_GPIO_FLEX_GLITCH_FILTER_NUM > 0)
typedef soc_periph_glitch_filter_clk_src_t glitch_filter_clock_source_t; // glitch filter clock source
#else
typedef int... | 530 |
/*
*/
/
/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#include "soc/lldesc.h"
#include "hal/sha_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
void sha_hal_hash_block(esp_sha_type sha_type, const void *data_block, size_t block_word_len, bool first_block);
/**
void sha_hal_wait_idle(void)... | 531 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
/**
*/
typedef enum {
I2C_NUM_0 = 0, /*!= 2
I2C_NUM_1, /*!= 2 */
#if SOC_LP_I2C_NUM >= 1
LP_I2C_NUM_0, /*= 1 */
I2C_NUM... | 532 |
< I2C start and stop condition setup period */
uint16_t hold; /*!< I2C start and stop condition hold period */
uint16_t tout; /*!< I2C bus timeout period */
} i2c_hal_clk_config_t;
typedef enum{
#if SOC_I2C_SUPPORT_SLAVE
I2C_MODE_SLAVE = 0, /*!< I2C slave mode */
#endif
I2C... | 532 |
< I2C ack for each byte read */
I2C_MASTER_NACK = 0x1, /*!< I2C nack for each byte read */
I2C_MASTER_LAST_NACK = 0x2, /*!< I2C nack for the last byte*/
I2C_MASTER_ACK_MAX,
} i2c_ack_type_t;
/**
*/
typedef enum {
I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH = 0, /*!< Stretching SCL low when the sla... | 532 |
/*
*/
#pragma once
#include
#include
#include "esp_flash_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Definition of a common transaction. Also holds the return value. */
typedef struct {
uint8_t reserved; ///< Reserved, must be 0.
uint8_t mosi_len; ///< Output data length, in byt... | 533 |
uint16_t command; ///< Command to send
uint8_t dummy_bitlen; ///< Basic dummy bits to use
uint32_t io_mode; ///< Flash working mode when `SPI_FLASH_IGNORE_BASEIO` is specified.
} spi_flash_trans_t;
/**
*/
typedef enum esp_flash_speed_s {
ESP_FLASH_5MHZ = 5, ///< The flash ru... | 533 |
#define SPI_FLASH_CONFIG_CONF_BITS BIT(31) ///< OR the io_mode with this mask, to enable the dummy output feature or replace the first several dummy bits into address to meet the requirements of conf bits. (Used in DIO/QIO/OIO mode)
/** @brief Mode used for reading from SPI flash */
typedef enum {
SPI_FLASH_... | 533 |
} esp_flash_io_mode_t;
/// Configuration structure for the flash chip suspend feature.
typedef struct {
uint32_t sus_mask; ///< SUS/SUS1/SUS2 bit in flash register.
struct {
uint32_t cmd_rdsr :8; ///< Read flash status register(2) command.
uint32_t sus_cmd :8; ... | 533 |
*/
struct spi_flash_host_driver_s {
/**
*/
esp_err_t (*dev_config)(spi_flash_host_inst_t *host);
/**
*/
esp_err_t (*common_command)(spi_flash_host_inst_t *host, spi_flash_trans_t *t);
/**
*/
esp_err_t (*read_id)(spi_flash_host_inst_t *host, uint32_t *id);
/**
*/
void... | 533 |
/*
*/
#pragma once
#include
#include
#include
#include "hal/mipi_csi_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct csi_host_dev_t *mipi_csi_host_soc_handle_t;
/**
*/
typedef struct csi_brg_dev_t *mipi_csi_bridge_soc_handle_t;
/**
*/
typedef struct {
mipi_csi_host_soc_handle_t ho... | 534 |
/*
*/
#pragma once
#include
#include "soc/clk_tree_defs.h"
#include "esp_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
MIPI_DSI_DT_VSYNC_START = 0x01, /*!< V Sync Start */
MIPI_DSI_DT_VSYNC_END = 0x11, /*!< V Sync End */
MIPI_DSI_DT_HSYNC_STA... | 535 |
< Generic Short Write, with 2 byte parameter */
MIPI_DSI_DT_GENERIC_READ_REQUEST_0 = 0x04, /*!< Generic Read Request, with no parameter */
MIPI_DSI_DT_GENERIC_READ_REQUEST_1 = 0x14, /*!< Generic Read Request, with 1 byte parameter */
MIPI_DSI_DT_GENERIC_READ_REQUEST_2 = 0x24, /*!< Generic Rea... | 535 |
< DCS Long Write */
MIPI_DSI_DT_PACKED_PIXEL_STREAM_RGB_16 = 0x0E, /*!< Packed Pixel Stream, RGB565 */
MIPI_DSI_DT_PACKED_PIXEL_STREAM_RGB_18 = 0x1E, /*!< Packed Pixel Stream, RGB666 */
MIPI_DSI_DT_LOOSELY_PIXEL_STREAM_RGB_18 = 0x2E, /*!< Loosely Pixel Stream, RGB666 */
MIPI_DSI_DT_PACKED_PIXEL_STREAM... | 535 |
/*
*/
#pragma once
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
/**
*/
typedef enum adc_hal_work_mode_t {
ADC_HAL_SINGLE_READ_MODE,
ADC_HAL_CONTINUOUS_READ_MODE,
ADC_HAL_PWDET_MODE,
ADC_HAL_ULP_FSM_MODE,
} adc_hal_work_mode_t;
/**
... | 536 |
/*
*/
// The HAL layer for PAU (Power Assist Unit)
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/soc_caps.h"
#if SOC_PAU_SUPPORTED
#include "hal/pau_ll.h"
#include "hal/pau_types.h"
typedef struct {
pau_dev_t *dev;
} pau_hal_context_t;
/**
*/
void pau_hal_set_regdma_entry_link_addr(pau_... | 537 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
MPI_MULT = 0x0, // (X * Y)
MPI_MODMULT, // (X * Y) Mod M
MPI_MODEXP, // (X ^ Y) Mod M
} mpi_op_t;
typedef enum {
MPI_PARAM_X = 0x0,
MPI_PARAM_Y,
MPI_PARAM_Z,
MPI_PARAM_M,
... | 538 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_err.h"
#include "soc/soc_caps.h"
#if SOC_APM_SUPPORTED
#include "hal/apm_ll.h"
/**
*/
typedef struct {
uint32_t regn_num; /* Address Region number cover by this configuration data. */
uint32_t regn_start_addr; /* Addre... | 539 |
*/
uint32_t regn_count; /* Access Ctrl region count. */
uint32_t master_ids; /* Bit mask for masters to be part of this secure mode. */
apm_ctrl_region_config_data_t *pms_data; /* Region configuration data. */
} apm_ctrl_secure_mode_config_t;
/**
*/
void apm_tee_ha... | 539 |
/*
*/
/
/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct dma2d_dev_t *dma2d_soc_handle_t; // 2D-DMA SOC layer handle
/**
*/
typedef struct {
dma2d_soc_handle_t dev; // 2D-DMA SOC layer handle (i.e. register base address)
} dma2d_hal_context_t;
/**
*/
void dma2d_hal_init(dma2... | 540 |
/*
*/
/
/
// The HAL layer for touch sensor (common part)
#pragma once
#if SOC_TOUCH_SENSOR_SUPPORTED
#include "hal/touch_sensor_ll.h"
#include "hal/touch_sensor_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_TOUCH_SENSOR_SUPPORTED
typedef struct {
touch_high_volt_t refh;
touch_low_volt_... | 541 |
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
DAC_CHAN_0 = 0, /*!< DAC channel 0 is GPIO25(ESP32) / GPIO17(ESP32S2) */
DAC_CHAN_1 = 1, /*!< DAC channel 1 is GPIO26(ESP32) / GPIO18(ESP32S2) */
DAC_CHANNEL_1 __attribute__((deprecated("please use 'DAC_CHAN_0' instead"))) = 0, ... | 542 |
< 1/8 amplitude of the DAC cosine wave */
} dac_cosine_atten_t;
/**
*/
typedef enum {
DAC_COSINE_PHASE_0 = 0x02, /*!< Phase shift +0° */
DAC_COSINE_PHASE_180 = 0x03, /*!< Phase shift +180° */
} dac_cosine_phase_t;
#ifdef __cplusplus
}
#endif
| 542 |
/*
*/
#pragma once
#include
#include "hal/color_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
uint32_t color_hal_pixel_format_get_bit_depth(color_space_pixel_format_t color_type_id);
#ifdef __cplusplus
}
#endif
| 543 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#include "hal/gdma_types.h"
// TODO: don't expose the SOC header files, we can typedef a new type for the register dev pointer
#if SOC_AHB_GDMA_VERSION == 1
#include "soc/gdma_struct.h"
#endif
#if SOC_AHB_GDMA_VERSION == 2
#include "soc/ahb_dma_struct... | 544 |
g. the interrupt event mask of interest
// for now, the AXI DMA and AHB DMA are sharing the same interrupt mask, so we don't need to store it here
// If one day they become incompatible, we shall save a copy for each of them as a private data
} gdma_hal_priv_data_t;
/**
*/
struct gdma_hal_context_t {
/// ... | 544 |
/*
*/
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/reg_base.h"
#if SOC_INT_PLIC_SUPPORTED
#include "soc/interrupt_reg.h"
#include "soc/plic_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
FORCE_INLINE_ATTR void interrupt_plic_ll_route(int intr_src, int intr_num)
{
... | 545 |
/*
*/
#pragma once
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "soc/regdma.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_PAU_SUPPORTED
#define PAU_REGDMA_LINK_NUM (REGDMA_LINK_ENTRY_NUM)
/**
*/
typedef regdma_entry_buf_t pau_regdma_link_addr_t;
#endif
#ifdef __cplusplus
}
#endif
| 546 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
typedef void** mpu_region_table_t;
#endif
typedef enum {
MPU_REGION_ILLEGAL,
#if SOC_MPU_REGION_RO_SUPPORTED
MPU_REGION_RO, // read-only
#endif
#if SOC_MPU_REGION_WO... | 547 |
/*
*/
#pragma once
#include "hal/adc_types.h"
#include "hal/adc_hal_common.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct sens_dev_t *adc_oneshot_soc_handle_t;
typedef struct adc_oneshot_hal_cfg_t {
adc_unit_t unit; ///< ADC unit
adc_hal_work_mode_t wor... | 548 |
/*
*/
#pragma once
#include "esp_assert.h"
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "hal/color_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_MIPI_CSI_SUPPORTED
/**
*/
typedef soc_periph_mipi_csi_phy_clk_src_t mipi_csi_phy_clock_source_t;
#else
typedef int mipi_csi_phy_clock_sour... | 549 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
typedef enum {
EMAC_DATA_INTERFACE_RMII, /*!< Reduced Media Independent Interface */
EMAC_DATA_INTERFACE_MII, /*!< Media Independent Interface */
} eth_data_interface_t;
/**
typedef enum {
ETH_LINK_UP, /*!< Ethernet link is up */
... | 550 |
/*
*/
#pragma once
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#if SOC_MCPWM_SUPPORTED
typedef soc_periph_mcpwm_timer_clk_src_t mcpwm_timer_clock_source_t;
#else
typedef int mcpwm_timer_clock_source_t;
#endif // SOC_MCPWM_SUPPORTED
/**
*/
#if SOC_MCPWM_... | 551 |
< MCPWM timer counts to peak (i.e. counter is full) */
MCPWM_TIMER_EVENT_INVALID, /*!< MCPWM timer invalid event */
} mcpwm_timer_event_t;
/**
*/
typedef enum {
MCPWM_TIMER_COUNT_MODE_PAUSE, /*!< MCPWM timer paused */
MCPWM_TIMER_COUNT_MODE_UP, /*!< MCPWM timer counting up */
MCPWM_TIMER_COUNT_... | 551 |
< Generator action: Keep the same level */
MCPWM_GEN_ACTION_LOW, /*!< Generator action: Force to low level */
MCPWM_GEN_ACTION_HIGH, /*!< Generator action: Force to high level */
MCPWM_GEN_ACTION_TOGGLE, /*!< Generator action: Toggle level */
} mcpwm_generator_action_t;
/**
*/
typedef enum {
MCPW... | 551 |
/*
*/
#pragma once
#include
#include "esp_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct dma_descriptor_s dma_descriptor_t;
struct dma_descriptor_s {
struct {
uint32_t size : 12; /*!< Buffer size */
uint32_t length : 12; /*!< Number of valid bytes in the ... | 552 |
< Buffer size */
uint32_t length : 12; /*!< Number of valid bytes in the buffer */
uint32_t reversed24_27 : 4; /*!< Reserved */
uint32_t err_eof : 1; /*!< Whether the received buffer contains error */
uint32_t reserved29 : 1; /*!< Reserved */
uint32_t suc_eof : 1; ... | 552 |
< DMA buffer is allowed to be accessed by DMA engine */
#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */
#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED (4095-3) /*!< Maximum size of the buffer that can be attached to descriptor, and aligned to 4B *... | 552 |
/*
*/
/
/
#pragma once
#include
#include "hal/jpeg_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct jpeg_dev_t *jpeg_soc_handle_t; // JPEG SOC layer handle
/**
*/
typedef struct {
jpeg_soc_handle_t dev; // JPEG SOC layer handle (i.e. register base address)
} jpeg_hal_context_t;
/**
*/
void... | 553 |
/*
*/
#pragma once
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
/*
*/
typedef enum {
JPEG_M_SOF0 = 0xFFC0, ///< Start of Frame 0
JPEG_M_SOF1 = 0xFFC1, ///< Start of Frame 1
JPEG_M_SOF2 = 0xFFC2, ///< Start of Frame 2
JPEG_M_SOF3 = 0xFFC3, ///< Start of Frame ... | 554 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "hal/gpio_types.h"
#include "sdkconfig.h"
#if !CONFIG_IDF_TARGET_ESP32P4 && ! CONFIG_IDF_TARGET_ESP32C5 //TODO: IDF-7532, [ESP32C5] IDF-8636
#if !SOC_LP_TIMER_SUPPORTED
#include "hal/rtc_cntl_ll.h"
#endif
#endif //#if !CONFIG_IDF_TARGET_ESP32P4 && ! C... | 555 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
DW_GDMA_BLOCK_TRANSFER_CONTIGUOUS, /*!< Contiguous buffer address */
DW_GDMA_BLOCK_TRANSFER_RELOAD, /*!< Reload transfer configuration automatically */
DW_GDMA_BLOCK_TRANSFER_SHADOW, /*!< Shadow register */
D... | 556 |
< Target is FIFO memory of peripheral: DSI */
DW_GDMA_ROLE_PERIPH_CSI, /*!< Target is FIFO memory of peripheral: CSI */
DW_GDMA_ROLE_PERIPH_ISP, /*!< Target is FIFO memory of peripheral: ISP */
} dw_gdma_role_t;
/**
*/
typedef enum {
DW_GDMA_LOCK_LEVEL_FULL_TRANS, /*!< Lock over complete DMA transfer *... | 556 |
< The address remains the same after each transfer */
} dw_gdma_burst_mode_t;
/**
*/
typedef enum {
DW_GDMA_BURST_ITEMS_1, /*!< 1 data items in a burst transaction */
DW_GDMA_BURST_ITEMS_4, /*!< 4 data items in a burst transaction */
DW_GDMA_BURST_ITEMS_8, /*!< 8 data items in a burst transaction... | 556 |
/*
*/
#pragma once
#include
#include
#include "sdkconfig.h"
#include "esp_attr.h"
#include "esp_bit_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Touch pad channel */
typedef enum {
TOUCH_PAD_NUM0 = 0, /*! 10
TOUCH_PAD_NUM10, /*!< Touch channel 10 is GPIO10(ESP32-S2) */
... | 557 |
6V */
TOUCH_HVOLT_2V7, /*!<Touch sensor high reference voltage, 2.7V */
TOUCH_HVOLT_MAX,
} touch_high_volt_t;
/** Touch sensor low reference voltage */
typedef enum {
TOUCH_LVOLT_KEEP = -1, /*!<Touch sensor low reference voltage, no change */
TOUCH_LVOLT_0V5 = 0, /*!<Touch sensor low referen... | 557 |
<Touch sensor high reference voltage attenuation, 0.5V attenuation */
TOUCH_HVOLT_ATTEN_0V, /*!<Touch sensor high reference voltage attenuation, 0V attenuation */
TOUCH_HVOLT_ATTEN_MAX,
} touch_volt_atten_t;
/** Touch sensor charge/discharge speed */
typedef enum {
TOUCH_PAD_SLOPE_0 = 0, ... | 557 |
<Initial level of charging voltage, low level */
TOUCH_PAD_TIE_OPT_HIGH = 1, /*!<Initial level of charging voltage, high level */
TOUCH_PAD_TIE_OPT_MAX,
} touch_tie_opt_t;
/** Touch sensor FSM mode */
typedef enum {
TOUCH_FSM_MODE_TIMER = 0, /*!<To start touch FSM by timer */
TOUCH_FSM_MODE_SW, ... | 557 |
< If set touch threshold max value, The touch sensor can't be in touched status */
#elif SOC_TOUCH_SENSOR_VERSION == 2
#define TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF) /*!< If set touch threshold max value, The touch sensor can't be in touched status */
#elif SOC_TOUCH_SENSOR_VERSION == 3
#define TOUCH_PAD_THRES... | 557 |
<The wakeup trigger source can be SET1 or both SET1 and SET2 */
#endif // CONFIG_IDF_TARGET ESP32
#if !CONFIG_IDF_TARGET_ESP32
/**
*/
#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT (0xf) /*!<The number of sleep cycle in each measure process of touch channels.
The timer ... | 557 |
*/
TOUCH_PAD_INTR_MASK_ACTIVE = BIT(1), /*!<Active for one of the enabled channels. */
TOUCH_PAD_INTR_MASK_INACTIVE = BIT(2), /*!<Inactive for one of the enabled channels. */
TOUCH_PAD_INTR_MASK_SCAN_DONE = BIT(3), /*!<Measurement done for all the enabled channels. */
TOUCH_PAD_INTR_MASK_TIMEOUT = ... | 557 |
<All touch interrupt type enable. */
#else
TOUCH_PAD_INTR_MASK_MAX
#define TOUCH_PAD_INTR_MASK_ALL (TOUCH_PAD_INTR_MASK_TIMEOUT \
| TOUCH_PAD_INTR_MASK_SCAN_DONE \
| TOUCH_PAD_INTR_MASK_INACTIVE \
| TOUCH_PAD_INTR_MA... | 557 |
4pf */
TOUCH_PAD_DENOISE_CAP_L2 = 2, /*!<Denoise channel internal reference capacitance is 7.8pf */
TOUCH_PAD_DENOISE_CAP_L3 = 3, /*!<Denoise channel internal reference capacitance is 9.2pf */
TOUCH_PAD_DENOISE_CAP_L4 = 4, /*!<Denoise channel internal reference capacitance is 10.6pf */
TOUCH_PAD_D... | 557 |
Ensure that the denoise readings are closest to the readings of the channel being measured.
Use `touch_pad_denoise_read_data` to get the reading of denoise channel.
The equivalent capacit... | 557 |
<The max equivalent capacitance in shield channel is 240pf */
TOUCH_PAD_SHIELD_DRV_L6, /*!<The max equivalent capacitance in shield channel is 280pf */
TOUCH_PAD_SHIELD_DRV_L7, /*!<The max equivalent capacitance in shield channel is 320pf */
TOUCH_PAD_SHIELD_DRV_MAX
} touch_pad_shield_driver_t;
/** T... | 557 |
The larger the parasitic capacitance on the shielding channel, the higher the drive capability needs to be set.
The equivalent capacitance of the shield channel can be estimated through the reading value of the denoise chan... | 557 |
<The filter mode is first-order IIR filter. The coefficient is 16 (Typical value). */
TOUCH_PAD_FILTER_IIR_32, /*!<The filter mode is first-order IIR filter. The coefficient is 32. */
TOUCH_PAD_FILTER_IIR_64, /*!<The filter mode is first-order IIR filter. The coefficient is 64. */
TOUCH_PAD_FILTER_IIR... | 557 |
< Counting the output of touch channel as data.
*/
TOUCH_PAD_OUT_AS_CLOCK, /*!< Counting the output of touch channel as clock.
*/
} touch_out_mode_t;
#endif
/** Touch sensor filter configuration */
typedef struct touch_filter_config {
touch_... | 557 |
Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; */
uint32_t jitter_step; /*!<Set jitter filter step size. Range: 0 ~ 15 */
touch_smooth_mode_t smh_lvl;/*!<Level of filter applied on the original data against large noise interference. */
#define TOUC... | 557 |
/*
*/
#pragma once
#include
#include "esp_attr.h"
#include "esp_bit_defs.h"
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
//SPI1 can be used as GPSPI only on ESP32
SPI1_HOST=0, /// 2
SPI3_HOST=2, ///< SPI... | 558 |
SPI_EV_CMD9 = BIT(6), ///< Received CMD9 from master.
SPI_EV_CMDA = BIT(7), ///< Received CMDA from master.
/* Common Event */
SPI_EV_TRANS = BIT(8), ///< A transaction has done
} spi_event_t;
/**
*/
typedef struct {
uint8_t cmd_lines; ///< The line width of comman... | 558 |
/*
*/
/
/
// The HAL layer for I2S.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#include "soc/soc_caps.h"
#if SOC_I2S_SUPPORTED
#include "hal/i2s_types.h"
#include "hal/i2s_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_... | 559 |
SOC_I2S_SUPPORTS_GDMA
/**
*/
#define i2s_hal_tx_enable_dma(hal) i2s_ll_enable_dma((hal)->dev,true)
/**
*/
#define i2s_hal_rx_enable_dma(hal) i2s_ll_enable_dma((hal)->dev,true)
/**
*/
#define i2s_hal_tx_disable_dma(hal) i2s_ll_enable_dma((hal)->dev,false)
/**
*/
#define i2s_hal_rx_disable_dma(hal) i2s_ll_enable_d... | 559 |
/*
*/
#pragma once
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct dw_gdma_dev_t *dw_gdma_soc_handle_t;
/**
*/
typedef struct {
dw_gdma_soc_handle_t dev; /*!< Pointer to the DW_GDMA registers */
} dw_gdma_hal_context_t;
/**
*/
typedef struct {
} dw_gdma_hal_config_t;
/**... | 560 |
/*
*/
/
/
// The HAL layer for SPI slave (common part)
// SPI slave HAL usages:
// 1. initialize the bus
// 2. initialize the DMA descriptors if DMA used
// 3. call setup_device to update parameters for the device
// 4. prepare data to send, and prepare the receiving buffer
// 5. trigger user defined SPI transacti... | 561 |
/*
*/
/
/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct sdmmc_dev_t *sdmmc_soc_handle_t;
/**
*/
typedef struct {
sdmmc_soc_handle_t dev; // SDMMC SOC layer handle (i.e. register base address)
} sdmmc_hal_context_t;
/**
*/
void sdmmc_hal_init(sdmmc_hal_context_t *hal);
#... | 562 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#if SOC_IEEE802154_SUPPORTED
#include "soc/ieee802154_reg.h"
#include "soc/ieee802154_struct.h"
#include "esp_attr.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_IEEE802154_SUPPORTED
/**
*/
typedef enum {
IEEE802154_CMD_TX_START ... | 563 |
cmd.cmd = cmd;
}
static inline void ieee802154_ll_enable_events(ieee802154_ll_events events)
{
IEEE802154.event_en.events |= events;
}
static inline void ieee802154_ll_disable_events(ieee802154_ll_events events)
{
IEEE802154.event_en.events &= ~events;
}
FORCE_INLINE_ATTR void ieee802154_ll_clear_events(ieee... | 563 |
tx_abort_event_en.tx_abort_en |= events;
}
static inline void ieee802154_ll_disable_tx_abort_events(ieee802154_ll_rx_abort_events events)
{
IEEE802154.tx_abort_event_en.tx_abort_en &= ~events;
}
FORCE_INLINE_ATTR void ieee802154_ll_set_rx_addr(uint8_t *addr)
{
IEEE802154.dma_rx_addr = (uint32_t)addr;
}
FORCE... | 563 |
tx_status.tx_abort_reason);
}
FORCE_INLINE_ATTR ieee802154_ll_tx_security_failed_reason_t ieee802154_ll_get_tx_security_failed_reason(void)
{
return (ieee802154_ll_tx_security_failed_reason_t)(IEEE802154.tx_status.tx_security_error);
}
static inline uint8_t ieee802154_ll_get_freq(void)
{
return IEEE802154.cha... | 563 |
conf.multipan_mask |= BIT(index);
IEEE802154.multipan[index].short_addr.addr = short_addr;
}
static inline uint16_t ieee802154_ll_get_multipan_short_addr(ieee802154_ll_multipan_index_t index)
{
return IEEE802154.multipan[index].short_addr.addr;
}
static inline void ieee802154_ll_set_multipan_ext_addr(ieee8021... | 563 |
ed_cfg.ed_rss;
}
static inline void ieee802154_ll_set_cca_mode(ieee802154_ll_cca_mode_t cca_mode)
{
IEEE802154.ed_cfg.cca_mode = cca_mode;
}
static inline void ieee802154_ll_set_cca_threshold(int8_t cca_threshold)
{
IEEE802154.ed_cfg.cca_threshold = cca_threshold;
}
static inline void ieee802154_ll_set_ed_sa... | 563 |
conf.auto_ack_rx;
}
static inline void ieee802154_ll_set_rx_auto_ack(bool enable)
{
IEEE802154.conf.auto_ack_rx = enable;
}
FORCE_INLINE_ATTR bool ieee802154_ll_get_tx_enhance_ack(void)
{
return IEEE802154.conf.auto_enhack;
}
static inline void ieee802154_ll_set_tx_enhance_ack(bool enable)
{
IEEE802154.c... | 563 |
timer0_value;
}
static inline void ieee802154_ll_timer1_set_threshold(uint32_t value)
{
IEEE802154.timer1_threshold = value;
}
static inline uint32_t ieee802154_ll_timer1_get_value(void)
{
return IEEE802154.timer1_value;
}
FORCE_INLINE_ATTR void ieee802154_ll_set_transmit_security(bool enable)
{
IEEE8021... | 563 |
security_key0 = (security_key[0] << 0) | (security_key[1] << 8) | (security_key[2] << 16) | (security_key[3] << 24);
IEEE802154.security_key1 = (security_key[4] << 0) | (security_key[5] << 8) | (security_key[6] << 16) | (security_key[7] << 24);
IEEE802154.security_key2 = (security_key[8] << 0) | (secur... | 563 |
debug_ed_abort_cnt;
}
static inline uint32_t ieee802154_ll_get_cca_fail_cnt(void)
{
return IEEE802154.debug_cca_fail_cnt;
}
static inline uint32_t ieee802154_ll_get_rx_fliter_fail_cnt(void)
{
return IEEE802154.debug_rx_filter_fail_cnt;
}
static inline uint32_t ieee802154_ll_get_no_rss_detect_cnt(void)
{
... | 563 |
debug_rx_ack_timeout_cnt;
}
static inline uint32_t ieee802154_ll_get_tx_break_coex_cnt(void)
{
return IEEE802154.debug_tx_break_coex_cnt;
}
static inline uint32_t ieee802154_ll_get_tx_security_error_cnt(void)
{
return IEEE802154.debug_tx_security_error_cnt;
}
static inline uint32_t ieee802154_ll_get_cca_busy... | 563 |
/*
*/
/
/
#pragma once
#include
#include
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#if SOC_TWAI_SUPPORTED
#include "hal/twai_types.h"
#include "hal/twai_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_TWAI_SUPPORTED
/* Defines and Typedefs */
#define TWAI_HAL_SET_BITS(var, flag) ... | 564 |
/*
*/
#pragma once
#include
#include
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
ADC_UNIT_1, /// ADC2 -> ADC1 -> ADC2 .....
} adc_digi_convert_mode_t;
/**
*/
typedef enum {
ADC_... | 565 |
<true: use APLL clock; false: use APB clock. */
uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
Note: When a higher frequency clock is used (the division factor is less than 9),
the ADC reading value will be slightly offset. */
uint32_t div_b; ... | 565 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
DS_KEY_INPUT_OK = 0, /**< The decryption key is ready. */
DS_NO_KEY_INPUT, /**< Dependent peripheral providing key hasn't been activated. */
DS_OTHER_WRONG, /**< Dependent peripheral running but problem receiving th... | 566 |
/*
*/
/
/
// The HAL layer for SDIO slave (common part)
// SDIO slave HAL usages:
/*
Architecture:
The whole SDIO slave peripheral consists of three parts: the registers (including the interrupt
control and shared registers), a send FIFO, and a receive FIFO. The document
``esp_slave_protocol.rst`` describes the ... | 567 |
For the FIFOs, the peripheral provides counters as registers so that the host can always know whether the slave
is ready to send/receive data. The HAL resets the counters during initialization, and the host should somehow
inform the slave to reset the counters again if it should reboot (or lose the counter value for ... | 567 |
associate the descriptor with the buffer.
The HAL initialize this descriptors with the determined length and maybe some extra data.
receiving buffer to the HAL.
When the DMA is started, the descriptors is loaded onto the DMA linked-list, and the
counter of receiving buffers is... | 567 |
- Sending part:
The sending driver is slightly different, since we are not using the re-start feature.
(TODO: re-write this part if the stitch mode is released)
If there is already any data queued, it will ne ready to be sent to host now.
If the interrupt is enabled, the ISR will be invoked... | 567 |
purpose interrupts or cancel all kinds of interrupts send to the host. These interrupts are
set/cleared in a concurrent-safe way, so the slave can call these functions safely.
the host to the slave. These interrupts will also be cleared after the calls.
general purpose shared between th... | 567 |
// Should Initialize the member `data` of `send_desc_queue` of the HAL context
// with size of this desc * N.
/// DMA descriptor with extra fields
typedef struct sdio_slave_hal_send_desc_s {
sdio_slave_ll_desc_t dma_desc; ///< Used by Hardware, has pointer linking to next desc
uint32_t pkt_len; ///< Ac... | 567 |
*/
sdio_slave_timing_t timing; /**< Timing mode (launch edge and latch edge settings). Should be manually
*/
//some boolean flags
struct {
uint32_t no_highspeed: 1; /**< Disable the highs... | 567 |
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