text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
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/*
*/
#pragma once
#include
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"
#include "soc/dport_reg.h"
#include "soc/syscon_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h"
#include "soc/regi2c_apll.h"
#include "hal/assert.h"
#include "e... | 604 |
303031 MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
#define CLK_LL_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
/**
*/
typedef enum {
CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL, //! 0);
REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, div... | 604 |
= 0 && xtal_freq_reg != UINT32_MAX) {
return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
}
// If the format in reg is invalid or haven't written XTAL value into RTC_XTAL_FREQ_REG
return 0;
}
/**
*/
static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint32_t apb_freq_... | 604 |
/*
*/
/
/
#pragma once
#include
#include
#include "hal/misc.h"
#include "soc/dac_periph.h"
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "hal/dac_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DAC_LL_CW_PHASE_0 0x02
#define DAC_LL_CW_PHASE_180 0x03
/**
*/
static inli... | 605 |
pad_dac[channel], dac, value);
}
}
/**
*/
static inline void dac_ll_rtc_sync_by_adc(bool enable)
{
SENS.sar_meas_ctrl2.sar1_dac_xpd_fsm = enable;
}
//
/* DAC cosine wave generator API's */
//
/**
*/
static inline void dac_ll_cw_generator_enable(void)
{
SENS.sar_dac_ctrl1.sw_tone_en = 1;
}
/**
*/
stat... | 605 |
dac_scale1 = atten;
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_scale2 = atten;
}
}
/**
*/
static inline void dac_ll_cw_set_phase(dac_channel_t channel, dac_cosine_phase_t phase)
{
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_inv1 = phase;
} else if (channel == DA... | 605 |
sar_dac_ctrl1.dac_dig_force = enable;
SENS.sar_dac_ctrl1.dac_clk_inv = enable;
}
#ifdef __cplusplus
}
#endif
| 605 |
/*
*/
/**
*/
#pragma once
#include
#include
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/rmt_struct.h"
#include "soc/dport_reg.h"
#include "hal/rmt_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RMT_LL_EVENT_TX_DONE(channel) (1 conf_ch[0].conf0.clk_en = enable; // register... | 606 |
conf1.ref_always_on = 1;
break;
case RMT_CLK_SRC_REF_TICK:
dev->conf_ch[channel].conf1.ref_always_on = 0;
break;
default:
HAL_ASSERT(false && "unsupported RMT clock source");
break;
}
}
/**
*/
static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en)
{
... | 606 |
conf1.mem_rd_rst = 1;
dev->conf_ch[channel].conf1.mem_rd_rst = 0;
dev->conf_ch[channel].conf1.apb_mem_rst = 1;
dev->conf_ch[channel].conf1.apb_mem_rst = 0;
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.tx_star... | 606 |
idle_out_en = enable;
dev->conf_ch[channel].conf1.idle_out_lv = level;
}
/**
*/
static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->tx_lim_ch[channel].limit = limit;
}
/**
*/
static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel,... | 606 |
carrier_out_lv = level;
}
////////////////////////////////////////RX Channel Specific/////////////////////////////////////////////////////////////
/**
*/
static inline void rmt_ll_rx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask)
{
for (int i = 0; i conf_ch[i].conf1.ref_cnt_rst = 1;
}
... | 606 |
conf1.rx_en = enable;
}
/**
*/
static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->conf_ch[channel].conf0.mem_size = block_num;
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres... | 606 |
val |= mask;
} else {
dev->int_ena.val &= ~mask;
}
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_clear_interrupt_status(rmt_dev_t *dev, uint32_t mask)
{
dev->int_clr.val = mask;
}
/**
*/
static inline volatile void *rmt_ll_get_interrupt_status_reg(rmt_dev_t *dev)
{
return... | 606 |
val & RMT_LL_EVENT_RX_MASK(channel);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
/////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
/////////////////////////////They migh... | 606 |
conf0, div_cnt);
return div == 0 ? 256 : div;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
{
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
return div == 0 ? 256 : div;
}
__attribute__((always_... | 606 |
conf1.ref_always_on) {
return RMT_CLK_SRC_APB;
}
return RMT_CLK_SRC_REF_TICK;
}
__attribute__((always_inline))
static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_en;
}
__attribute__((always_inline))
static inline uint32_t rm... | 606 |
val;
return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7) |
((status & 0x2000) >> 9) | ((status & 0x10000) >> 11) | ((status & 0x80000) >> 13) | ((status & 0x400000) >> 15);
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_tx_err_int... | 606 |
val;
return (status & 0xFF000000) >> 24;
}
#ifdef __cplusplus
}
#endif
| 606 |
/*
*/
/
/
// The LL layer for ESP32 MCPWM register operations
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/mcpwm_struct.h"
#include "soc/dport_reg.h"
#include "hal/mcpwm_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// Get MCPWM group register ba... | 607 |
global_force_up = 1;
mcpwm->update_cfg.global_force_up = 0;
}
//////////////////////////////////////////Interrupt Specific////////////////////////////////////////////////////////////
/**
*/
static inline volatile void *mcpwm_ll_intr_get_status_reg(mcpwm_dev_t *mcpwm)
{
return &mcpwm->int_st;
}
/**
*/
stati... | 607 |
timer_cfg0, timer_prescale, prescale - 1);
}
/**
*/
__attribute__((always_inline))
static inline void mcpwm_ll_timer_set_peak(mcpwm_dev_t *mcpwm, int timer_id, uint32_t peak, bool symmetric)
{
if (!symmetric) { // in asymmetric mode, period = [0,peak-1]
HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id... | 607 |
timer_cfg0.timer_period_upmethod |= 0x02;
} else {
mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x02;
}
}
/**
*/
static inline void mcpwm_ll_timer_set_count_mode(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_count_mode_t mode)
{
switch (mode) {
case MCPWM_TIMER_COUNT_MODE_PAUSE:... | 607 |
timer_cfg1.timer_start = 0;
break;
case MCPWM_TIMER_STOP_FULL:
mcpwm->timer[timer_id].timer_cfg1.timer_start = 1;
break;
case MCPWM_TIMER_START_NO_STOP:
mcpwm->timer[timer_id].timer_cfg1.timer_start = 2;
break;
case MCPWM_TIMER_START_STOP_EMPTY:
mcpwm->timer[t... | 607 |
timer_sync.timer_synci_en = enable;
}
/**
*/
static inline void mcpwm_ll_timer_propagate_input_sync(mcpwm_dev_t *mcpwm, int timer_id)
{
// sync_out is selected to sync_in
mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 0;
}
/**
*/
static inline void mcpwm_ll_timer_sync_out_on_timer_event(mcpwm_dev_t *mc... | 607 |
timer_sync_sw = ~mcpwm->timer[timer_id].timer_sync.timer_sync_sw;
}
/**
*/
static inline void mcpwm_ll_timer_set_sync_phase_value(mcpwm_dev_t *mcpwm, int timer_id, uint32_t phase_value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_sync, timer_phase, phase_value);
}
/**
*/
static inline void mcp... | 607 |
gen_stmp_cfg.val |= (1 operators[operator_id].gen_stmp_cfg.val &= ~((1 operators[operator_id].gen_stmp_cfg.val |= (1 operators[operator_id].gen_stmp_cfg.val &= ~((1 operators[operator_id].gen_stmp_cfg.val |= (1 operators[operator_id].gen_stmp_cfg.val &= ~((1 operators[operator_id].gen_stmp_cfg.val |= (1 operators[opera... | 607 |
gen_cfg_upmethod |= 1 operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 operators[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 operators[operator_id].gen_cfg0.val &= ~(0x07 operators[operator_id].gen_cfg0.val |= (fault_gpio_id operators[operator_id].gen_cfg0.... | 607 |
generator[generator_id].val &= ~(0x03 operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) operators[operator_id].generator[generator_id].val &= ~(0x03 operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) operators[operator_id].generator[ge... | 607 |
fh_cfg0.val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) operators[operator_id].gen_force.gen_a_nciforce = ~mcpwm->operators[operator_id].gen_force.gen_a_nciforce;
} else {
mcpwm->operators[operator_id].gen_force.gen_b_nciforce = ~mcpwm->operators[operator_id].gen_force.gen_b_nciforce;
}
}
/**
*/
static ... | 607 |
gen_force.gen_b_nciforce_mode = 0;
}
}
/**
*/
static inline void mcpwm_ll_gen_set_continue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level)
{
mcpwm->operators[operator_id].gen_force.gen_cntuforce_upmethod = 0; // update force method immediately
if (generator_id == 0) {
... | 607 |
dt_cfg.dt_clk_sel = 0;
break;
case MCPWM_LL_DEADTIME_CLK_SRC_TIMER:
mcpwm->operators[operator_id].dt_cfg.dt_clk_sel = 1;
break;
default:
HAL_ASSERT(false);
}
}
/**
*/
static inline void mcpwm_ll_deadtime_red_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generato... | 607 |
dt_cfg.dt_deb_mode = enable;
}
/**
*/
static inline uint32_t mcpwm_ll_deadtime_get_switch_topology(mcpwm_dev_t *mcpwm, int operator_id)
{
return (mcpwm->operators[operator_id].dt_cfg.dt_deb_mode operators[operator_id].dt_cfg.dt_b_outswap operators[operator_id].dt_cfg.dt_a_outswap operators[operator_id].dt_cfg.dt_... | 607 |
dt_cfg.dt_red_upmethod = 0;
}
/**
*/
static inline void mcpwm_ll_deadtime_enable_update_delay_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable)
{
if (enable) {
mcpwm->operators[operator_id].dt_cfg.dt_fed_upmethod |= 1 operators[operator_id].dt_cfg.dt_red_upmethod |= 1 operators[operator_id].dt_cfg.... | 607 |
carrier_cfg.carrier_en = enable;
}
/**
*/
static inline void mcpwm_ll_carrier_set_prescale(mcpwm_dev_t *mcpwm, int operator_id, uint8_t prescale)
{
HAL_ASSERT(prescale > 0 && prescale operators[operator_id].carrier_cfg.carrier_prescale = prescale - 1;
}
/**
*/
static inline void mcpwm_ll_carrier_set_duty(mcpwm_... | 607 |
carrier_cfg.carrier_oshtwth = pulse_width - 1;
}
////////////////////////////////////////MCPWM Fault Specific////////////////////////////////////////////////////////////
/**
*/
static inline void mcpwm_ll_fault_enable_detection(mcpwm_dev_t *mcpwm, int fault_sig, bool enable)
{
if (enable) {
mcpwm->fault_... | 607 |
val &= ~(1 operators[operator_id].fh_cfg0.fh_sw_cbc = enable;
}
/**
*/
static inline void mcpwm_ll_brake_enable_soft_ost(mcpwm_dev_t *mcpwm, int operator_id, bool enable)
{
mcpwm->operators[operator_id].fh_cfg0.fh_sw_ost = enable;
}
/**
*/
static inline void mcpwm_ll_brake_trigger_soft_cbc(mcpwm_dev_t *mcpwm, i... | 607 |
cap_timer_en = enable;
}
/**
*/
static inline void mcpwm_ll_capture_enable_channel(mcpwm_dev_t *mcpwm, int channel, bool enable)
{
mcpwm->cap_chn_cfg[channel].capn_en = enable;
}
/**
*/
static inline void mcpwm_ll_capture_set_sync_phase_value(mcpwm_dev_t *mcpwm, uint32_t phase_value)
{
mcpwm->cap_timer_phas... | 607 |
val |= 1 cap_chn_cfg[channel].val &= ~(1 cap_chn_cfg[channel].val |= 1 cap_chn_cfg[channel].val &= ~(1 cap_chn_cfg[channel].capn_in_invert = invert;
}
/**
*/
static inline void mcpwm_ll_trigger_soft_capture(mcpwm_dev_t *mcpwm, int channel)
{
mcpwm->cap_chn_cfg[channel].capn_sw = 1; // auto clear
}
/**
*/
__attr... | 607 |
0)//////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
{
return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->clk_cfg, clk_prescale) + 1;
}
static i... | 607 |
timestamp[compare_id], gen);
}
__attribute__((always_inline))
static inline uint32_t mcpwm_ll_intr_get_capture_status(mcpwm_dev_t *mcpwm)
{
return (mcpwm->int_st.val >> 27) & 0x07;
}
__attribute__((always_inline))
static inline void mcpwm_ll_intr_clear_capture_status(mcpwm_dev_t *mcpwm, uint32_t capture_mask)
{
... | 607 |
/*
*/
#pragma once
#include
#include
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F > 8) & 0x3;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void)
{
retu... | 608 |
blk0_rdata3.rd_chip_package_4bit 4) {
return false;
}
uint32_t error_reg = EFUSE.dec_status.dec_warnings;
return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block - 1) != 0;
}
/ eFuse control functions /
__attribute__((always_inline)) static inline bool efuse_ll_get_cmd(void)
{
return EFUSE.cmd.val... | 608 |
clk.clk_sel0 = value;
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel1(uint32_t value)
{
EFUSE.clk.clk_sel1 = value;
}
/ eFuse control functions /
#ifdef __cplusplus
}
#endif
| 608 |
/*
*/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/gpio_sd_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void sdm_ll_enable_clock(gpio_sd_dev_t *hw, bool en)
{
// The clk enable register does not exist on ESP32.
}
/**
*/
__attribute__((always_inl... | 609 |
/*
*/
#include "esp_attr.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
{
if (core_id == 0) {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
} else {
DPORT_WRITE_PERI_REG(DPORT_CPU_INT... | 610 |
/*
*/
/
/
// The Lowlevel layer for Touch Sensor
#pragma once
#include
#include
#include "hal/misc.h"
#include "soc/touch_sensor_periph.h"
#include "soc/sens_struct.h"
#include "soc/rtc_io_struct.h"
#include "soc/rtc_cntl_struct.h"
#include "hal/touch_sensor_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//... | 611 |
sar_touch_enable.touch_pad_outen1 |= TOUCH_LL_BITS_SWAP(group1_mask);
SENS.sar_touch_enable.touch_pad_outen2 |= TOUCH_LL_BITS_SWAP(group2_mask);
}
/**
*/
static inline void touch_ll_get_group_mask(uint16_t *group1_mask, uint16_t *group2_mask)
{
*group1_mask = TOUCH_LL_BITS_SWAP(SENS.sar_touch_enable.touch_pad... | 611 |
int_ena.rtc_touch = 1;
}
/**
*/
static inline void touch_ll_intr_disable(void)
{
RTCCNTL.int_ena.rtc_touch = 0;
}
/**
*/
static inline void touch_ll_intr_clear(void)
{
RTCCNTL.int_clr.rtc_touch = 1;
}
/**
*/
static inline uint32_t touch_ll_read_raw_data(touch_pad_t touch_num)
{
touch_pad_t tp_wrap = t... | 611 |
/*
*/
#pragma once
#include
#include "soc/soc.h"
#include "soc/regi2c_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void regi2c_ctrl_ll_i2c_reset(void)
{
SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
}
/**
*/
static inline void regi2c_ctrl_ll_i2c_bbpll_e... | 612 |
However,
// ESP32 does not use it to support those features.
// In order to make it convenient for compiling other targets, left a blank function here.
}
#ifdef __cplusplus
}
#endif
| 612 |
/*
*/
#pragma once
#include
#include "hal/sha_types.h"
#include "soc/hwcrypto_reg.h"
#include "soc/dport_access.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SHA_LL_TYPE_OFFSET 0x10
/**
*/
inline static uint32_t SHA_LOAD_REG(esp_sha_type sha_type)
{
return SHA_1_LOAD_REG + sha_type ... | 613 |
for (size_t i = 0; i < digest_word_len; i += 2) {
digest_state_words[i + 1] = DPORT_SEQUENCE_REG_READ((uint32_t)®_addr_buf[i]);
digest_state_words[i] = DPORT_SEQUENCE_REG_READ((uint32_t)®_addr_buf[i + 1]);
}
DPORT_INTERRUPT_RESTORE(); // restore the previous inte... | 613 |
/*
*/
// The LL layer for MMU register operations
#pragma once
#include
#include "soc/ext_mem_defs.h"
#include "soc/dport_reg.h"
#include "soc/dport_access.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MMU_LL_PSRAM_ENTRY_START_ID 1152
/**
*/
static inli... | 614 |
MMU_TARGET_PSRAM0 : MMU_TARGET_FLASH0;
}
/**
*/
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
{
(void)mmu_id;
HAL_ASSERT(entry_id = MMU_LL_PSRAM_ENTRY_START_ID) ? (mmu_value = 64 && entry_id = 128 && entry_id = 192 && entry_id = MMU_LL_PSRAM_ENTRY_START_ID) {
... | 614 |
/*
*/
/
/
#pragma once
#include
#include "soc/rtc_io_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_periph.h"
#define RTCIO_LL_PIN_FUNC 0
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
RTCIO_LL_FUNC_RTC = 0x0, /*!> rtcio_num) & 0x1;
}
/**
*/
static inline void rtcio_ll_set_dri... | 615 |
reg, rtc_io_desc[rtcio_num].pullup);
}
}
/**
*/
static inline void rtcio_ll_pullup_disable(int rtcio_num)
{
if (rtc_io_desc[rtcio_num].pullup) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup);
}
}
/**
*/
static inline void rtcio_ll_pulldown_enable(int rtcio_num)
{... | 615 |
hold_force);
REG_CLR_BIT(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].hold);
}
/**
*/
static inline void rtcio_ll_force_hold_all(void)
{
SET_PERI_REG_BITS(RTC_CNTL_HOLD_FORCE_REG, 0x3FFFF, 0x3FFFF, 0);
}
/**
*/
static inline void rtcio_ll_force_unhold_all(void)
{
SET_PERI_REG_BITS(RTC_CNTL_HOLD_FO... | 615 |
slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpoe);
}
}
/**
*/
static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpie);
}
/**
*/
static inline void rtcio_ll_disable_input_in_sle... | 615 |
/*
*/
/
/
// The LL layer for ESP32 I2S register operations
#pragma once
#include
#include "hal/misc.h"
#include "soc/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/dport_reg.h"
#include "hal/i2s_types.h"
#include "hal/hal_utils.h"
#ifdef __cplusplus
extern "C" {
#endif
// Get I2S hardware instance w... | 616 |
check_owner = en;
}
/**
*/
static inline void i2s_ll_dma_enable_auto_write_back(i2s_dev_t *hw, bool en)
{
hw->lc_conf.out_auto_wrback = en;
}
/**
*/
static inline void i2s_ll_dma_enable_eof_on_fifo_empty(i2s_dev_t *hw, bool en)
{
hw->lc_conf.out_eof_mode = en;
}
/**
*/
static inline void i2s_ll_enable_bus... | 616 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; i2s_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void i2s_ll_reset_register(int i2s_id)
{
if (i2s_id == 0) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
} else ... | 616 |
clk_en) {
hw->clkm_conf.clk_en = 0;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define i2s_ll_enable_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; i2s_ll_enable_core_... | 616 |
rx_fifo_mod_force_en = enable;
}
/**
*/
static inline void i2s_ll_tx_set_slave_mod(i2s_dev_t *hw, bool slave_en)
{
hw->conf.tx_slave_mod = slave_en;
}
/**
*/
static inline void i2s_ll_rx_set_slave_mod(i2s_dev_t *hw, bool slave_en)
{
hw->conf.rx_slave_mod = slave_en;
}
/**
*/
static inline void i2s_ll_tx_re... | 616 |
clka_en = (src == I2S_CLK_SRC_APLL) ? 1 : 0;
}
/**
*/
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
//0: disable APLL clock, I2S module will using PLL_D2_CLK(160M) as source clock
//1: Enable APLL clock, I2S module will using APLL as source clock
hw->clkm_conf.clka_en = (s... | 616 |
rx_bck_div_num = val;
}
/**
*/
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div)
{
// TX and RX channel on ESP32 shares a same mclk
i2s_ll_tx_set_mclk(hw, mclk_div);
}
/**
*/
static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
{
uint32_t i... | 616 |
val;
}
/**
*/
static inline volatile void *i2s_ll_get_interrupt_status_reg(i2s_dev_t *hw)
{
return (volatile void *)(&hw->int_st);
}
/**
*/
__attribute__((always_inline))
static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t clr_mask)
{
hw->int_clr.val = clr_mask;
}
/**
*/
static inline void... | 616 |
addr = link_addr;
hw->in_link.start = 1;
}
/**
*/
static inline void i2s_ll_tx_stop(i2s_dev_t *hw)
{
hw->conf.tx_start = 0;
}
/**
*/
static inline void i2s_ll_rx_stop(i2s_dev_t *hw)
{
hw->conf.rx_start = 0;
}
/**
*/
static inline void i2s_ll_tx_stop_link(i2s_dev_t *hw)
{
hw->out_link.stop = 1;
}
... | 616 |
tx_bits_mod = val;
}
/**
*/
static inline void i2s_ll_tx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit)
{
hw->fifo_conf.tx_fifo_mod = (chan_bit sample_rate_conf.tx_bits_mod = data_bit;
}
/**
*/
static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit)
{
hw->fi... | 616 |
tx_msb_shift = msb_shift_enable;
}
/**
*/
static inline void i2s_ll_rx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enable)
{
hw->conf.rx_msb_shift = msb_shift_enable;
}
/**
*/
static inline void i2s_ll_tx_select_pdm_slot(i2s_dev_t *hw, i2s_pdm_slot_mask_t slot_mask, bool is_mono)
{
if (is_mono) {
... | 616 |
tx_chan_mod = 0;
break;
default:
break;
}
}
}
/**
*/
static inline void i2s_ll_rx_select_pdm_slot(i2s_dev_t *hw, i2s_pdm_slot_mask_t slot_mask)
{
switch (slot_mask)
{
case I2S_PDM_SLOT_RIGHT:
hw->conf_chan.rx_chan_mod = 1;
break;
case I2S_PDM... | 616 |
tx_chan_mod = 1;
break;
case I2S_STD_SLOT_LEFT:
hw->conf_chan.tx_chan_mod = 2;
break;
case I2S_STD_SLOT_BOTH:
hw->conf_chan.tx_chan_mod = 0;
break;
default:
break;
}
}
}
/**
*/
static inline void i2s_ll_rx_sele... | 616 |
sig_loopback = loopback_en;
}
/I2S PDM Configurations/
/**
*/
static inline void i2s_ll_rx_set_pdm_dsr(i2s_dev_t *hw, i2s_pdm_dsr_t dsr)
{
hw->pdm_conf.rx_sinc_dsr_16_en = dsr;
}
/**
*/
static inline void i2s_ll_rx_get_pdm_dsr(i2s_dev_t *hw, i2s_pdm_dsr_t *dsr)
{
*dsr = (i2s_pdm_dsr_t)hw->pdm_conf.rx_sinc... | 616 |
tx_hp_in_shift = sig_scale;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_lp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale)
{
hw->pdm_conf.tx_lp_in_shift = sig_scale;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_sinc_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale)
{
hw->pdm_conf.tx_sinc_in_shift =... | 616 |
tx_pdm_fs;
}
/I2S ADC/DAC Configurations/
/**
*/
static inline void i2s_ll_enable_lcd(i2s_dev_t *hw, bool enable)
{
hw->conf2.lcd_en = enable;
}
/**
*/
static inline void i2s_ll_enable_camera(i2s_dev_t *hw, bool enable)
{
hw->conf2.camera_en = enable;
}
/**
*/
static inline void i2s_ll_enable_builtin_a... | 616 |
/*
*/
// The LL layer for LEDC register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include "hal/ledc_types.h"
#include "soc/ledc_periph.h"
#include "soc/ledc_struct.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LED... | 617 |
timer[timer_sel].conf.low_speed_update = 1;
}
/**
*/
static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
{
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1;
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0;
}
/**
*/
static inline void ledc_l... | 617 |
timer[timer_sel].conf.clock_divider;
}
/**
*/
static inline void ledc_ll_set_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t clk_src)
{
hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = (clk_src == LEDC_APB_CLK);
}
/**
*/
static inline void ledc_ll_get_cloc... | 617 |
timer[timer_sel].conf.duty_resolution;
}
/**
*/
static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *max_duty)
{
*max_duty = (1 channel_group[speed_mode].channel[channel_num].conf0.low_speed_update = 1;
}
/**
*/
static inline void ledc_ll_set_hpoint(l... | 617 |
channel[channel_num].conf1.duty_inc = duty_direction;
}
/**
*/
static inline void ledc_ll_set_duty_num(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_num)
{
hw->channel_group[speed_mode].channel[channel_num].conf1.duty_num = duty_num;
}
/**
*/
static inline void ledc_ll_set_du... | 617 |
val = hw->channel_group[speed_mode].channel[channel_num].conf1.val;
conf1_reg.duty_inc = dir;
conf1_reg.duty_num = step;
conf1_reg.duty_cycle = cycle;
conf1_reg.duty_scale = scale;
hw->channel_group[speed_mode].channel[channel_num].conf1.val = conf1_reg.val;
}
/**
*/
__attribute__((always_inline))... | 617 |
val;
uint32_t int_en_base = (speed_mode == LEDC_LOW_SPEED_MODE) ? LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S : LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S;
hw->int_ena.val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num))));
}
/**
*/
static inline void ledc_ll_get_fade... | 617 |
channel[channel_num].conf0.timer_sel = timer_sel;
}
/**
*/
static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel)
{
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusp... | 617 |
/*
*/
// The LL layer for Cache register operations
#pragma once
#include
#include "soc/dport_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_ID_ALL 2 //All of the caches in a typ... | 618 |
CACHE_BUS_IBUS2 : 0));
} else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IROM0_... | 618 |
/*
*/
/
/
// The LL layer for ESP32 eMAC register operations
#pragma once
#include
#include
#include "hal/misc.h"
#include "hal/eth_types.h"
#include "soc/emac_dma_struct.h"
#include "soc/emac_mac_struct.h"
#include "soc/emac_ext_struct.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/* R... | 619 |
h) */
#define EMAC_LL_DMA_TRANSMIT_FINISH_INTR 0x00000001U
#define EMAC_LL_DMA_TRANSMIT_STOP_INTR 0x00000002U
#define EMAC_LL_DMA_TRANSMIT_BUFF_UNAVAILABLE_INTR 0x00000004U
#define EMAC_LL_DMA_TRANSMIT_TIMEOUT_INTR 0x00000008U
#define EMAC_LL_DMA_RECEIVE_OVERFLOW_INTR ... | 619 |
h) */
#define EMAC_LL_INTR_TRANSMIT_ENABLE 0x00000001U
#define EMAC_LL_INTR_TRANSMIT_STOP_ENABLE 0x00000002U
#define EMAC_LL_INTR_TRANSMIT_BUFF_UNAVAILABLE_ENABLE 0x00000004U
#define EMAC_LL_INTR_TRANSMIT_TIMEOUT_ENABLE 0x00000008U
#define EMAC_LL_INTR_OVERFLOW_ENABLE ... | 619 |
miicsrclk = div_mode;
}
static inline bool emac_ll_is_mii_busy(emac_mac_dev_t *mac_regs)
{
return mac_regs->emacgmiiaddr.miibusy ? true : false;
}
static inline void emac_ll_set_phy_addr(emac_mac_dev_t *mac_regs, uint32_t addr)
{
mac_regs->emacgmiiaddr.miidev = addr;
}
static inline void emac_ll_set_phy_reg(... | 619 |
interframegap = gap;
}
static inline void emac_ll_carrier_sense_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacconfig.disablecrs = !enable;
}
static inline void emac_ll_set_port_speed(emac_mac_dev_t *mac_regs, eth_speed_t speed)
{
if (speed == ETH_SPEED_10M || speed == ETH_SPEED_100M) {
... | 619 |
rxipcoffload = mode;
}
static inline void emac_ll_retry_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacconfig.retry = !enable;
}
static inline void emac_ll_auto_pad_crc_strip_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacconfig.padcrcstrip = enable;
}
static inline void emac_ll... | 619 |
receive_all = enable;
}
static inline void emac_ll_set_src_addr_filter(emac_mac_dev_t *mac_regs, uint32_t filter)
{
mac_regs->gmacff.safe = filter;
}
static inline void emac_ll_sa_inverse_filter_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacff.saif = enable;
}
static inline void emac_ll_set_p... | 619 |
dzpq = !enable;
}
static inline void emac_ll_set_pause_low_threshold(emac_mac_dev_t *mac_regs, uint32_t threshold)
{
mac_regs->gmacfc.plt = threshold;
}
static inline void emac_ll_unicast_pause_frame_detect_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacfc.upfd = enable;
}
static inline void e... | 619 |
sw_rst = 1;
}
static inline bool emac_ll_is_reset_done(emac_dma_dev_t *dma_regs)
{
return dma_regs->dmabusmode.sw_rst ? false : true;
}
/* dmarxbaseaddr / dmatxbaseaddr */
static inline void emac_ll_set_rx_desc_addr(emac_dma_dev_t *dma_regs, uint32_t addr)
{
dma_regs->dmarxbaseaddr = addr;
}
static inline vo... | 619 |
tx_str_fwd = enable;
}
static inline void emac_ll_flush_trans_fifo_enable(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmaoperation_mode.flush_tx_fifo = enable;
}
static inline bool emac_ll_get_flush_trans_fifo(emac_dma_dev_t *dma_regs)
{
return dma_regs->dmaoperation_mode.flush_tx_fifo;
}
static inlin... | 619 |
rx_thresh_ctrl = threshold;
}
static inline void emac_ll_opt_second_frame_enable(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmaoperation_mode.opt_second_frame = enable;
}
static inline void emac_ll_start_stop_dma_receive(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmaoperation_mode.start_stop_r... | 619 |
prog_burst_len = dma_burst_len == ETH_DMA_BURST_LEN_1 ? EMAC_LL_DMA_BURST_LENGTH_1BEAT :
dma_burst_len == ETH_DMA_BURST_LEN_2 ? EMAC_LL_DMA_BURST_LENGTH_2BEAT :
dma_burst_len == ETH_DMA_BURST_LEN_4 ? EMAC_LL_DMA_BURST_LENGTH_4BEAT... | 619 |
dma_arb_sch = enable;
}
static inline void emac_ll_set_priority_ratio(emac_dma_dev_t *dma_regs, uint32_t ratio)
{
dma_regs->dmabusmode.pri_ratio = ratio;
}
/* dmain_en */
static inline void emac_ll_enable_all_intr(emac_dma_dev_t *dma_regs)
{
dma_regs->dmain_en.val = 0xFFFFFFFF;
}
static inline void emac_ll_d... | 619 |
val = bits;
}
__attribute__((always_inline)) static inline void emac_ll_clear_all_pending_intr(emac_dma_dev_t *dma_regs)
{
dma_regs->dmastatus.val = 0xFFFFFFFF;
}
/* dmatxpolldemand / dmarxpolldemand */
static inline void emac_ll_transmit_poll_demand(emac_dma_dev_t *dma_regs, uint32_t val)
{
dma_regs->dmatxpo... | 619 |
phy_intf_sel = 4;
/* ref clk for phy is input in rmii mode, the clk can be offered by mac layer or external crystal.
config pin as output to generate ref clk by esp32 mac layer or input to obtain the clock from external crystal */
ext_regs->ex_clk_ctrl.ext_en = 1;
ext_regs->ex_clk_ctrl.int_en = 0;
e... | 619 |
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