text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
sbd_flowctrl = enable;
}
/ End of ext regs operation /
#ifdef __cplusplus
}
#endif
| 619 |
/*
*/
#include
#include "soc/soc_caps.h"
#include "xt_instr_macros.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
{
// vpn - id
// 0x00000000 = 0
// 0x20000000 = 1
// 0x40000000 = 2
// 0x60000000 = 3
// 0x80000000 = 4
// 0xa0000000 = 5
... | 620 |
/*
*/
/
/
#pragma once
#include
#include
#include "esp_bit_defs.h"
#include "hal/assert.h"
#include "soc/clk_tree_defs.h"
#include "soc/sdmmc_struct.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SDMMC_LL_GET_HW(id) (((id) == 0) ? (&SDMMC) : NULL)
/**
*/
#define SDMMC_LL_SLOT_... | 621 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw)
{
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_SDIO_HOST_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_SDIO_HOST_RST);
}
/// use a macro to wrap... | 621 |
val = 0;
}
/**
*/
static inline uint32_t sdmmc_ll_get_clock_div(sdmmc_dev_t *hw)
{
return hw->clock.div_factor_h + 1;
}
/**
*/
static inline void sdmmc_ll_init_phase_delay(sdmmc_dev_t *hw)
{
// 180 degree phase on input and output clocks
hw->clock.phase_dout = 4;
hw->clock.phase_din = 4;
hw->clo... | 621 |
card0 == 0);
card_div = hw->clkdiv.div0;
} else if (slot == 1) {
HAL_ASSERT(hw->clksrc.card1 == 1);
card_div = hw->clkdiv.div1;
} else {
HAL_ASSERT(false);
}
return card_div;
}
/**
*/
static inline void sdmmc_ll_enable_card_clock_low_power(sdmmc_dev_t *hw, uint32_t slo... | 621 |
cards & BIT(slot);
return is_protected;
}
/**
*/
static inline void sdmmc_ll_enable_ddr_mode(sdmmc_dev_t *hw, uint32_t slot, bool en)
{
if (en) {
hw->uhs.ddr |= BIT(slot);
hw->emmc_ddr_reg |= BIT(slot);
} else {
hw->uhs.ddr &= ~BIT(slot);
hw->emmc_ddr_reg &= ~BIT(slot);
... | 621 |
val;
}
/**
*/
static inline void sdmmc_ll_enable_interrupt(sdmmc_dev_t *hw, uint32_t mask, bool en)
{
if (en) {
hw->intmask.val |= mask;
} else {
hw->intmask.val &= ~mask;
}
}
/**
*/
static inline void sdmmc_ll_clear_interrupt(sdmmc_dev_t *hw, uint32_t mask)
{
hw->rintsts.val = mask;... | 621 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include // For MIN/MAX
#include
#include
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SPI_FLASH_LL_... | 622 |
#define spi_flash_ll_set_dummy_out(dev, out_en, out_lev)
// On ESP32, we extent 4 bits to occupy `Continuous Read Mode` bits. (same to origin code.)
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (4)
/// type to store pre-calculated register value in above layers
typedef typeof(SPI1.clock.val) spi_flash_ll_clock_reg_... | 622 |
flash_wren = 1;
}
}
/**
*/
static inline void spi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
// If everything is word-aligned, do a faster memcpy
memcpy(buffer, (void *)dev->data_buf, read_len);
} el... | 622 |
usr_dummy = 0;
spi_flash_ll_set_buffer_data(dev, buffer, length);
dev->cmd.flash_pp = 1;
}
/**
*/
static inline void spi_flash_ll_user_start(spi_dev_t *dev, bool pe_ops)
{
dev->cmd.usr = 1;
}
/**
*/
static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
{
return dev->ext2.st == 0;
}
/*
**... | 622 |
fread_quad = 1;
break;
case SPI_FLASH_DIO:
ctrl.fread_dio = 1;
break;
case SPI_FLASH_DOUT:
ctrl.fread_dual = 1;
break;
case SPI_FLASH_SLOWRD:
ctrl.fastrd_mode = 0;
break;
default:
abort();
}
dev->ctrl.val = ctrl.val;
}
/**
*/
stat... | 622 |
usr_command_value = command,
.reserved16 = 0,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2.val = user2.val;
}
/**
static inline int spi_flash_ll_get_addr_bitlen(spi_dev_t *dev)
{
return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
}
/**
*/
static inline void spi_flash_ll_... | 622 |
hold_time = hold_n;
dev->user.cs_hold = (hold_n > 0? 1: 0);
}
static inline void spi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
{
dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
dev->ctrl2.setup_time = cs_setup_time - 1;
}
/**
*/
static inline uint32_t spi_flash_ll_get_source_clock_f... | 622 |
/*
*/
/
/
// The HAL layer for touch sensor (esp32 specific part)
#pragma once
#include "hal/touch_sensor_ll.h"
#include "hal/touch_sensor_types.h"
#include_next "hal/touch_sensor_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define touch_hal_set_meas_time(meas_time) touch_ll_set_meas_time(meas_time)
... | 623 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "esp_attr.h"
#include "hal/assert.h"
#include "soc/periph_defs.h"
#include "soc/dport_reg.h"
#include "soc/soc_caps.h"
static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
{
switch (periph) {
case PER... | 624 |
return (DPORT_PERI_EN_AES | DPORT_PERI_EN_DIGITAL_SIGNATURE | DPORT_PERI_EN_SECUREBOOT);
} else {
//Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
return DPORT_PERI_EN_AES;
}
case PERIPH_SHA_MODULE:
if (enable == ... | 624 |
= 0;
}
static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN_M);
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(DPORT... | 624 |
/*
*/
#pragma once
#include
#include "hal/adc_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/adc_periph.h"
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "soc/sens_reg.h"
#include "soc/syscon_struct.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/clk_tree_defs.h"
#ifde... | 625 |
saradc_sar2_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val > offset; // Fill in the new data
SYSCON.saradc_sar2_patt_tab[index] = tab; // Write back
}
}
/**
*/
static inline void adc_ll_digi_clear_... | 625 |
cct set to the same value with PHY. */
return SENS.sar_start_force.sar2_pwdet_cct;
}
/*
RTC controller setting
*/
/**
*/
static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div)
{
if (adc_n == ADC_UNIT_1) {
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_c... | 625 |
sar_start_force.sar1_bit_width = reg_val;
SENS.sar_read_ctrl.sar1_sample_bit = reg_val;
} else { // adc_n == ADC_UNIT_2
SENS.sar_start_force.sar2_bit_width = reg_val;
SENS.sar_read_ctrl2.sar2_sample_bit = reg_val;
}
}
/**
*/
static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_... | 625 |
sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas_start1.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas_start1.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map... | 625 |
sar_touch_ctrl1.xpd_hall_force = 0; // 1: SW control HALL power; 0: ULP FSM control HALL power.
SENS.sar_touch_ctrl1.hall_phase_force = 0; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
break;
case ADC_LL_CTRL_DIG:
SENS.sar_read_ctrl.sar... | 625 |
sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital co... | 625 |
SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
break;
case ADC_LL_CTRL_DIG:
SENS.sar_me... | 625 |
sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital co... | 625 |
sar_meas_wait1, sar_amp_wait1, 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait2, 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait2, sar_amp_wait3, 1);
}
/*
Hall sensor setting
*/
/**
*/
static inline void adc_ll_hall_enable(void)
{
RTCIO.hall_sens.xpd_hall = ... | 625 |
= ADC_UNIT_2) {
return;
}
if (en) {
RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode
//set dtest (MUX_SEL : 0 -> RTC; 1-> vdd_sar2)
RTCCNTL.test_mux.dtest_rtc = 1; //Config test mux to route v_ref to ADC2 Channels
//set ent
RTCCNTL.... | 625 |
sar_meas_start2.sar2_en_pad = 0;
}
}
#ifdef __cplusplus
}
#endif
| 625 |
/*
*/
/
/
// The LL layer for ESP32 PCNT register operations
#pragma once
#include
#include
#include
#include
#include "soc/pcnt_struct.h"
#include "hal/pcnt_types.h"
#include "hal/misc.h"
#include "soc/dport_access.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PCNT_LL_GET_HW(... | 626 |
conf0.ch1_neg_mode = neg_act;
}
}
/**
*/
static inline void pcnt_ll_set_level_action(pcnt_dev_t *hw, uint32_t unit, uint32_t channel, pcnt_channel_level_action_t high_act, pcnt_channel_level_action_t low_act)
{
if (channel == 0) {
hw->conf_unit[unit].conf0.ch0_hctrl_mode = high_act;
hw->conf_u... | 626 |
val;
}
/**
*/
__attribute__((always_inline))
static inline void pcnt_ll_clear_intr_status(pcnt_dev_t *hw, uint32_t status)
{
hw->int_clr.val = status;
}
/**
*/
static inline void pcnt_ll_enable_high_limit_event(pcnt_dev_t *hw, uint32_t unit, bool enable)
{
hw->conf_unit[unit].conf0.thr_h_lim_en = enable;
}
... | 626 |
conf0.val &= ~(PCNT_LL_WATCH_EVENT_MASK conf_unit[unit].conf2) conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_h_lim = value;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
type... | 626 |
conf2) conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_h_lim;
return value;
}
/**
*/
static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
typeof(hw->conf_unit[unit].conf2) conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
... | 626 |
val & 0x03);
}
/**
*/
__attribute__((always_inline))
static inline uint32_t pcnt_ll_get_event_status(pcnt_dev_t *hw, uint32_t unit)
{
return hw->status_unit[unit].val >> 2;
}
/**
*/
static inline void pcnt_ll_set_glitch_filter_thres(pcnt_dev_t *hw, uint32_t unit, uint32_t filter_val)
{
hw->conf_unit[unit].c... | 626 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; pcnt_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void pcnt_ll_reset_register(int group_id)
{
(void)group_id;
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST);
}
/// use a macro ... | 626 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "esp_attr.h"
#include "clk_tree_ll.h"
#include "esp_rom_sys.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
{
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
WRITE_PER... | 627 |
RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST;
REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst);
}
FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
}
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
{
SET_PERI_REG_MASK(RTC_CNTL_TI... | 627 |
/*
*/
/
/
// The LL layer for ESP32 SDIO slave register operations
// It's strange but `tx_*` regs for host->slave transfers while `rx_*` regs for slave->host transfers
// To reduce ambiguity, we call (host->slave, tx) transfers receiving and (slave->host, rx) transfers receiving
#pragma once
#include "hal/sdio_s... | 628 |
typedef enum {
SDIO_SLAVE_LL_SLVINT_0 = BIT(0), ///slc0_int_ena.val = 0;
slc->conf0.slc0_rx_auto_wrback = 1;
slc->conf0.slc0_token_auto_clr = 0;
slc->conf0.slc0_rx_loop_test = 0;
slc->conf0.slc0_tx_loop_test = 0;
slc->conf1.slc0_rx_stitch_en = 0;
slc->conf1.slc0_tx_stitch_en = 0;
s... | 628 |
frc_sdio20 = 0;
host->conf.frc_sdio11 = 0x1f;
host->conf.frc_pos_samp = 0x1f;
host->conf.frc_neg_samp = 0;
break;
case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
host->conf.frc_sdio20 = 0;
host->conf.frc_sdio11 = 0x1f;
host->conf.frc_pos_... | 628 |
slc0_rx_rst = 1;
slc->conf0.slc0_rx_rst = 0;
}
/**
*/
static inline void sdio_slave_ll_send_start(slc_dev_t *slc, const sdio_slave_ll_desc_t *desc)
{
slc->slc0_rx_link.addr = (uint32_t)desc;
slc->slc0_rx_link.start = 1;
}
/**
*/
static inline void sdio_slave_ll_send_write_len(slc_dev_t *slc, uint32_t le... | 628 |
stop = 1;
}
/**
*/
static inline void sdio_slave_ll_send_intr_ena(slc_dev_t *slc, bool ena)
{
slc->slc0_int_ena.rx_eof = (ena? 1: 0);
}
/**
*/
static inline void sdio_slave_ll_send_intr_clr(slc_dev_t *slc)
{
slc->slc0_int_clr.rx_eof = 1;
}
/**
*/
static inline bool sdio_slave_ll_send_done(slc_dev_t *slc)
... | 628 |
val = FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_WDATA, 0) | FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_WR, 1);
}
/**
*/
static inline bool sdio_slave_ll_recv_done(slc_dev_t *slc)
{
return slc->slc0_int_raw.tx_done != 0;
}
/**
*/
static inline void sdio_slave_ll_recv_done_clear(slc_dev_t *slc)
{
slc->slc0_int_clr.tx_done = 1;
}
... | 628 |
val;
}
/**
*/
static inline void sdio_slave_ll_host_set_intena(host_dev_t *host, const sdio_slave_hostint_t *mask)
{
host->slc0_func1_int_ena.val = (*mask);
}
/**
*/
static inline void sdio_slave_ll_host_intr_clear(host_dev_t* host, const sdio_slave_hostint_t *mask)
{
host->slc0_int_clr.val = (*mask);
}
/*... | 628 |
val & 0xff);
*out_slv_int = slv_int;
slc->slc0_int_clr.val = slv_int;
}
#ifdef __cplusplus
}
#endif
| 628 |
/*
*/
/
/
#pragma once
#include
#include "soc/rtc_cntl_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void brownout_ll_enable_flash_power_down(bool enable)
{
RTCCNTL.brown_out.close_flash_ena = enable;
}
/**
*/
static inline void brownout_ll_enable_rf_power_down(bool enable)
{
R... | 629 |
int_clr.rtc_brown_out = 1;
}
/**
*/
static inline void brownout_ll_clear_count(void)
{
// Not supported on esp32
}
#ifdef __cplusplus
}
#endif
| 629 |
/*
*/
/
/
// The LL layer for ESP32 GPIO register operations
#pragma once
#include
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"
#include "hal/gpio_types.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
//... | 630 |
val) & bit_mask) >> bit_shift;
*od = hw->pin[gpio_num].pad_driver;
*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
*sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
}
/**
*/
static inline ... | 630 |
true : false;
}
/**
*/
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
}
/**
*/
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
}
/**
*/
static in... | 630 |
true : false;
}
/**
*/
static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type)
{
hw->pin[gpio_num].int_type = intr_type;
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
*... | 630 |
int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr
} else {
hw->pin[gpio_num].int_ena = GPIO_LL_APP_CPU_INTR_ENA; //enable app cpu intr
}
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].int_ena = ... | 630 |
pad_driver = 1;
}
/**
*/
static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
PIN_FUNC_SELECT(DR_REG_IO_MUX_BASE + GPIO_PIN_MUX_REG_OFFSET[gpio_num], func);
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_set_level(gpio_dev_t *h... | 630 |
GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
}
/**
*/
static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
{
SET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
}
/**
*/
stati... | 630 |
sig_in_sel = 0;
PIN_INPUT_ENABLE(DR_REG_IO_MUX_BASE + GPIO_PIN_MUX_REG_OFFSET[gpio]);
}
/**
*/
static inline __attribute__((always_inline)) void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
PIN_FUNC_SELECT(pin_name, func);
}
/**
*/
static inline __attribute__((always_inline)) void gpio_ll_set_... | 630 |
/*
*/
#pragma once
#include
#include
#include
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/pcr_reg.h"
#include "soc/pcr_struct.h"
#include "soc/rsa_reg.h"
#include "soc/mpi_periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void mpi_ll_enable_bus_clock(bool enable)
{
... | 631 |
If num_words is higher than the number of words (n) in the bignum then
these additional words will be zeroed in the memory buffer.
*/
static inline void mpi_ll_write_to_mem_block(mpi_param_t param, size_t offset, const uint32_t* p, size_t n, size_t num_words)
{
uint32_t mem_base = MPI_LL_BLOCK_BASES[param] ... | 631 |
Reads z_words words from block.
*/
static inline void mpi_ll_read_from_mem_block(uint32_t* p, size_t n, size_t num_words)
{
uint32_t mem_base = MPI_LL_BLOCK_BASES[MPI_PARAM_Z];
/* Copy data from memory block registers */
const size_t REG_WIDTH = sizeof(uint32_t);
for (size_t i = 0; i < num_words; i... | 631 |
/*
*/
/
/
// The Lowlevel layer for TWAI
#pragma once
#include
#include
#include
#include "esp_assert.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/twai_types.h"
#include "soc/twai_struct.h"
#include "soc/pcr_struct.h"
#define TWAI_LL_GET_HW(controller_id) ((controller_id == 0) ? (&TWAI0) : (... | 632 |
listen_only_mode = 0;
hw->mode.self_test_mode = 1;
} else if (mode == TWAI_MODE_LISTEN_ONLY) { //Listen Only Mode
hw->mode.listen_only_mode = 1;
hw->mode.self_test_mode = 0;
}
}
/* Command Register */
/**
*/
__attribute__((always_inline))
static inline void twai_ll_set_cmd_tx(twai_d... | 632 |
self_rx_request = 1;
}
/**
*/
__attribute__((always_inline))
static inline void twai_ll_set_cmd_self_rx_single_shot(twai_dev_t *hw)
{
hw->cmd.val = 0x12; //Set cmd.self_rx_request and cmd.abort_tx simultaneously for single shot self reception request
}
/* Status Register */
/**
*/
__attribute__((always_inlin... | 632 |
val = intr_mask;
}
/* Bus Timing Registers */
/**
*/
__attribute__((always_inline))
static inline bool twai_ll_check_brp_validation(uint32_t brp)
{
bool valid = (brp >= SOC_TWAI_BRP_MIN) && (brp bus_timing_0.baud_presc = (brp / 2) - 1;
hw->bus_timing_0.sync_jump_width = sjw - 1;
hw->bus_timing_1.time_s... | 632 |
val;
}
/* RX Error Count Register */
/**
*/
__attribute__((always_inline))
static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
{
return hw->rx_err_cnt.val;
}
/**
*/
__attribute__((always_inline))
static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_e... | 632 |
acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
}
hw->mode.acceptance_filter_mode = single_filter;
}
/* TX/RX Buffer Registers */
/**
*/
__attribute__((always_inline))
static inline void twai_... | 632 |
1 : 0;
tx_frame->single_shot = (flags & TWAI_MSG_FLAG_SS) ? 1 : 0;
//Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required
if (is_extd) {
uint32_t id_temp = HAL_SWAP32((id & TWAI_EXTD_ID_MASK) > 8*(3-i))
for (int i = 0; i extended.id[i] = (id_temp >> ... | 632 |
The ID registers are big endian and left aligned, therefore a bswap will be required
if (rx_frame->frame_format) {
uint32_t id_temp = 0;
for (int i = 0; i extended.id[i] > 3; //((byte[i] > 3)
*id = id_temp & TWAI_EXTD_ID_MASK;
} else {
uint32_t id_temp = 0;
for (int i =... | 632 |
clock_off = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, 255);
} else {
hw->clock_divider.clock_off = 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, 0);
}
}
#ifdef __cplusplus
}
#endif
| 632 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "soc/timer_periph.h"
#include "soc/timer_group_struct.h"
#include "soc/pcr_struct.h"
#inc... | 633 |
wdt_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
hw->wdtconfig0.wdt_en = 0;
}
/**
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
return (hw->wdtconfig0.wdt_en) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_... | 633 |
wdt_conf_update_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
{
switch (stage) {
case WDT_STAGE0:
hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
... | 633 |
wdt_sys_reset_length = length;
//Config registers are updated asynchronously
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
{
hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
//Config registers are updated asynchronou... | 633 |
wdt_wkey = 0;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
{
hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
{
hw->int_clr_timers.wdt_int_clr = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_set_intr_ena... | 633 |
timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en;
} else {
PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en;
}
}
#ifdef __cplusplus
}
#endif
| 633 |
/*
*/
#pragma once
#include
#include
#include "soc/hwcrypto_reg.h"
#include "hal/aes_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
typedef enum {
ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */
ESP_AES_STATE_BUSY, /* Transform in progress */
ESP_AES_STATE_DONE, /* Transform comple... | 634 |
0 : MODE_DECRYPT_BIT;
/* See TRM for the mapping between keylength and mode bit */
REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2));
}
/**
*/
static inline void aes_ll_write_block(const void *input)
{
uint32_t input_word;
for (int i = 0; i < AES_BLOCK_WORDS; i++) {
memcpy(&inp... | 634 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include // For MIN/MAX
#include
#include
#include "soc/spi_periph.h"
#include "soc/spi_mem_struct.h"
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include "soc/pcr_struct.h"
#ifd... | 635 |
val = 0;
dev->cmd.flash_se = 1;
}
/**
*/
static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev)
{
dev->cmd.flash_be = 1;
}
/**
*/
static inline void spimem_flash_ll_suspend(spi_mem_dev_t *dev)
{
dev->flash_sus_ctrl.flash_pes = 1;
}
/**
*/
static inline void spimem_flash_ll_resume(spi_mem_d... | 635 |
sus_timeout_cnt = 5;
dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en;
}
/**
static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool res_check_sus_en)
{
dev->flash_sus_ctrl.sus_timeout_cnt = 5;
dev->flash_sus_ctrl.per_end_en = res_check_sus_en;
}
/**
*/
static inline void spimem_... | 635 |
flash_per_wait_en = auto_waiti;
dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti;
}
/**
*/
static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy)
{
// Not supported on this chip.
}
/**
*/
static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
{
... | 635 |
usr_dummy = 0;
spimem_flash_ll_set_buffer_data(dev, buffer, length);
dev->cmd.flash_pp = 1;
}
/**
*/
static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev, bool pe_ops)
{
uint32_t usr_pe = (pe_ops ? 0x60000 : 0x40000);
dev->cmd.val |= usr_pe;
}
/**
*/
static inline bool spimem_flash_ll_ho... | 635 |
val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
break;
case SPI_FLASH_QIO:
ctrl.fread_qio = 1;
break;
case SPI_FLASH_QOUT:
ctrl.fread_quad = 1;
break;
case SPI_FLASH_DIO:
ctrl.fread_dio = 1;
... | 635 |
usr_mosi = bitlen > 0;
dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0;
}
/**
*/
static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen)
{
dev->user.usr_command = 1;
typeof(dev->user2) user2 = {
.usr_command_value = command,
.usr_co... | 635 |
usr_dummy = dummy_n ? 1 : 0;
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
}
/**
*/
static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
{
dev->ctrl2.cs_hold_time = hold_n - 1;
dev->user.cs_hold = (hold_n > 0? 1: 0);
}
static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev... | 635 |
mspi_clk_conf.mspi_fast_ls_div_num) {
case 0:
clock_val = 40;
break;
case 1:
clock_val = 20;
break;
case 2:
clock_val = 10;
break;
default:
HAL_ASSERT(false);
}
}
return clock_val;
}
/**... | 635 |
/*
*/
// The LL layer for I2C register operations
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2c_periph.h"
#include "soc/soc_caps.h"
#include "soc/i2c_struct.h"
#include "soc/pcr_struct.h"
#include "hal/i2c_types.h"
#include "soc/clk_tree_defs.h"
#include "soc/lp_clkrst_struc... | 636 |
conf_upgate = 1;
}
/**
*/
static inline void i2c_ll_enable_bus_clock(int i2c_port, bool enable)
{
(void)i2c_port;
PCR.i2c_conf.i2c_clk_en = enable;
}
/**
*/
static inline void i2c_ll_reset_register(int i2c_port)
{
(void)i2c_port;
PCR.i2c_conf.i2c_rst_en = 1;
PCR.i2c_conf.i2c_rst_en = 0;
}
/**
... | 636 |
sda_hold_time = bus_cfg->sda_hold - 1;
hw->sda_sample.sda_sample_time = bus_cfg->sda_sample - 1;
//setup
hw->scl_rstart_setup.scl_rstart_setup_time = bus_cfg->setup - 1;
hw->scl_stop_setup.scl_stop_setup_time = bus_cfg->setup - 1;
//hold
hw->scl_start_hold.scl_start_hold_time = bus_cfg->hold - 1... | 636 |
rx_fifo_rst = 1;
hw->fifo_conf.rx_fifo_rst = 0;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask)
{
hw->int_clr.val = mask;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask)
{
hw-... | 636 |
addr_broadcasting_en = broadcast_en;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
{
switch (hw->sr.stretch_cause) {
case 0:
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
break;
c... | 636 |
slave_addr = slave_addr;
}
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cmd, int cmd_idx)
{
hw->command[cmd_idx].val = cmd.val;
}
/**
*/
static inline void i2c_ll_master_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
... | 636 |
fifo_prt_en = 1;
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
}
/**
*/
static inline void i2c_ll_set_data_mode(i2c_dev_t *hw, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mode)
{
hw->ctr.tx_lsb_first = tx_mode;
hw->ctr.rx_lsb_first = rx_mode;
}
/**
*/
static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw... | 636 |
txfifo_cnt;
}
/**
*/
static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
{
*timeout = hw->to.time_out_value;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
/**
*/
static inline void i2c_ll_get_start_timing(i2c_de... | 636 |
fifo_addr_cfg_en = addr_wr_en;
}
/**
*/
static inline void i2c_ll_master_set_filter(i2c_dev_t *hw, uint8_t filter_num)
{
if (filter_num > 0) {
hw->filter_cfg.scl_filter_thres = filter_num;
hw->filter_cfg.sda_filter_thres = filter_num;
hw->filter_cfg.scl_filter_en = 1;
hw->filter_cf... | 636 |
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
}
/**
*/
static inline void i2c_ll_master_rx_full_ack_level(i2c_dev_t *hw, int ack_level)
{
hw->ctr.rx_full_ack_level = ack_level;
}
/**
*/
static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_clk)
{
if (hw =... | 636 |
lpperi is a shared register, so this function must be used in an atomic way
#define lp_i2c_ll_set_source_clk(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_i2c_ll_set_source_clk(__VA_ARGS__)
/**
*/
static inline void lp_i2c_ll_enable_bus_clock(int hw_id, bool enable)
{
(void)hw_id;
LPPERI.clk_en.lp_ext_i2c_ck_en = e... | 636 |
i2c_sclk_conf.i2c_sclk_en = en;
}
/**
*/
static inline void i2c_ll_master_init(i2c_dev_t *hw)
{
typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0;
ctrl_reg.ms_mode = 1;
ctrl_reg.sda_force_out = 1;
ctrl_reg.scl_force_out = 1;
hw->ctr.val = ctrl_reg.val;
}
/**
*/
static inline void i2c_ll_slave_init(... | 636 |
slave_scl_stretch_clr = 1;
}
/**
*/
__attribute__((always_inline))
static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
{
return hw->command[cmd_idx].command_done;
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
//////... | 636 |
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