text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
hmac_key_idx = DS_KEY_BLOCK_1,
// results of message array encrypted with these keys
.expected_results = {
// Message 0
{ 0x835d38bf, 0xe5d63f67, 0x9969a043, 0xdf213e48, 0x5395a017, 0x78987b04, 0xec668fef, 0x138cea9d, 0xd2959a98, 0xca4bcc37, 0x73bb1fb9, 0xcfbf5c65, 0xac990953, 0x1010be27, ... | 583 |
iv = { 0xf8, 0x40, 0x6d, 0xc2, 0x14, 0xcf, 0x51, 0xfa, 0xba, 0x22, 0x6c, 0x84, 0x62, 0xe8, 0x55, 0x1f },
.p_data = {
.Y = { 0x535e76e1, 0xbb4a17dd, 0x20d3dbb5, 0x5f7ec17c, 0x6977a611, 0xa1ae5fa4, 0xc594568c, 0x2d438edf, 0x4d509cf3, 0x25cef8dd, 0x7d2697c6, 0xa1f3fea3, 0xfe25c7d3, 0x4bfd0fe8, 0x3eca82... | 583 |
M_prime = 0x0dd35669,
.length = 31, // 1024 bit
},
.expected_c = { 0xe0, 0x77, 0x7a, 0xd4, 0xf2, 0xdc, 0x37, 0x20, 0xd9, 0xc7, 0x46, 0x3a, 0xf8, 0x36, 0x1f, 0x17, 0x1c, 0x28, 0x5e, 0xa3, 0x12, 0x8e, 0x60, 0x15, 0xdd, 0x11, 0xd9, 0xdb, 0x1c, 0xf1, 0x02, 0x32, 0x82, 0xff, 0xe0, 0x29, 0x30, 0x7... | 583 |
hmac_key_idx = DS_KEY_BLOCK_1,
// results of message array encrypted with these keys
.expected_results = {
// Message 0
{ 0xf310f445, 0xef8a7e16, 0x3305705e, 0x8425f05d, 0x7c52803b, 0x3683f157, 0x66aed50c, 0xf25c6a91, 0x7f527392, 0x12961c88, 0x36371944, 0x559457b5, 0xd00a275b, 0x5e5d03d6, ... | 583 |
iv = { 0x07, 0x26, 0x01, 0x00, 0x07, 0x30, 0x8f, 0x4b, 0x20, 0x54, 0x05, 0x88, 0xcb, 0xf6, 0x05, 0xe5 },
.p_data = {
.Y = { 0xb97e9089, 0x92bb938b, 0x9892be06, 0xc1a2a5ca, 0xa9cb1028, 0x55c8f928, 0x7665d7ff, 0x287b020f, 0xc503d1ea, 0x0843b294, 0x8a412553, 0xc4652f7e, 0xf1b761df, 0xe8153cfd, 0x4425f8... | 583 |
M = { 0xbbd1af17, 0x0be7a601, 0x53608285, 0x4eb25cc2, 0xf3119d6b, 0x94919f21, 0x2397852d, 0x52c5be66, 0x025c7cfa, 0x1ba0c334, 0xc79f18ba, 0x3de18e0a, 0x6c72a97e, 0xac7e9991, 0x4bed0b9b, 0x1ab7ff4c, 0x4fb33c28, 0x27d6712c, 0xe43b3b2c, 0x8e633f56, 0x71e67903, 0xa2678cfc, 0x734ab7e9, 0xb9451207, 0xcdccf854, 0x6caaf571, 0x... | 583 |
Rb = { 0xd1451d74, 0x2526ed62, 0x9804f511, 0x84be11f7, 0xc7c65580, 0x100c8136, 0xa968d71c, 0x11711eba, 0x006ea4cc, 0x8694d270, 0xadf746f7, 0x887b34af, 0x7e9029d5, 0x3ad9959c, 0xae5fbb3c, 0x8192414e, 0x94a82f47, 0xdb34be1d, 0x1acd0d11, 0x54c1d13f, 0x56825835, 0x6a0150c6, 0xbebb3296, 0x85a152c0, 0x4349e49c, 0xcb9c766a, 0... | 583 |
M_prime = 0xb8838759,
.length = 95, // 3072 bit
},
.expected_c = { 0x74, 0x3a, 0x44, 0x62, 0xa7, 0x7a, 0x9a, 0x00, 0xe6, 0x18, 0xdd, 0x5e, 0xaf, 0x37, 0x77, 0x31, 0x1b, 0x19, 0x6b, 0xc1, 0x67, 0x2c, 0x19, 0x23, 0xed, 0xa8, 0x49, 0x08, 0xf7, 0x98, 0x24, 0x8f, 0x24, 0x5b, 0xfb, 0x11, 0x35, 0x1... | 583 |
iv = { 0xc6, 0x09, 0xa6, 0x69, 0x05, 0xf2, 0x42, 0xa4, 0xd4, 0x92, 0x33, 0xc2, 0xe3, 0x09, 0x09, 0x56 },
.p_data = {
.Y = { 0xfb66eac1, 0x26184a9b, 0xaf48c7ba, 0xd1cb4e8e, 0x92838968, 0x7017a7c8, 0xa580dad8, 0x6e2d45a9, 0xda9642f7, 0x07a9da71, 0x9c0f85c1, 0x9b7985aa, 0xc60c6e44, 0x04e48499, 0x19ca1a... | 583 |
Rb = { 0xd268e1d4, 0x63c4157b, 0x5cdca862, 0x75f9f81c, 0x2f7f0531, 0xc9d99227, 0x9b344bea, 0x7ffbe131, 0x3e0f9e90, 0x4d88cef6, 0xc3461df7, 0x6961aff4, 0x8eb212eb, 0x8a8845e2, 0x0a47e1c0, 0xae5cfc5a, 0x48a1f7d8, 0xc215bd10, 0x1c98a17f, 0xac34eb25, 0x0ef594f2, 0x4da5ffb7, 0x86a62fab, 0xca408fe7, 0xf050fae6, 0xcd5d780a, 0... | 583 |
hmac_key_idx = DS_KEY_BLOCK_1,
// results of message array encrypted with these keys
.expected_results = {
// Message 0
{ 0xfc598d13, 0x1d473088, 0x7ffd4112, 0x05e516ab, 0xc7a44c14, 0x613d4f1d, 0xea1783c6, 0xe5a2af06, 0x4606a9a4, 0x8df1d612, 0x33e34d14, 0x86c3c728, 0x6c207e61, 0xd99dbf4e, ... | 583 |
iv = { 0xdc, 0x0f, 0x35, 0x44, 0x22, 0x00, 0x92, 0x16, 0xb6, 0x05, 0x77, 0x21, 0x81, 0x7b, 0x04, 0x91 },
.p_data = {
.Y = { 0xb8e66fe1, 0xfb4b3a40, 0x8efd30fa, 0x5c7aeb64, 0x1b1c0d2d, 0x670be326, 0x75ae690a, 0x7923ae77, 0x6a656153, 0xf69d0c47, 0xad23d132, 0x9ecd650e, 0x583ce8d7, 0xae5eb003, 0xfbc594... | 583 |
M_prime = 0x350c6bf9,
.length = 31, // 1024 bit
},
.expected_c = { 0xf8, 0x04, 0xa8, 0xfb, 0x42, 0x1d, 0x28, 0x97, 0x84, 0xb7, 0x31, 0xe4, 0x0d, 0xdd, 0xe5, 0xd3, 0xf8, 0x25, 0x0d, 0x3b, 0x50, 0x3b, 0xa5, 0x3f, 0xdc, 0xbc, 0x01, 0xf5, 0xd4, 0x5f, 0x10, 0x7e, 0xb9, 0xe4, 0xaf, 0x7b, 0x2a, 0xd... | 583 |
hmac_key_idx = DS_KEY_BLOCK_3,
// results of message array encrypted with these keys
.expected_results = {
// Message 0
{ 0x01e2dc01, 0x633fdca6, 0x7cd9d77d, 0x98ab8b40, 0x90c880f5, 0xb8ac2b6c, 0x9f1c1674, 0x8e588407, 0xc161ea0d, 0x72650a07, 0xa0dc2aea, 0x90a933b8, 0x45c3a758, 0xc028546e, ... | 583 |
/*
*/
#pragma once
#include
#include
#include
#if SOC_SHA_SUPPORTED
#include "soc/periph_defs.h"
#include "esp_private/periph_ctrl.h"
#include "hal/sha_hal.h"
#include "test_params.h"
#if defined(SOC_SHA_SUPPORT_SHA1)
void sha1_block(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char... | 584 |
/*
*/
#pragma once
#include
#include
#include
#if SOC_SHA_SUPPORTED
#include "soc/periph_defs.h"
#include "esp_private/periph_ctrl.h"
#include "hal/sha_hal.h"
#include "test_params.h"
#if defined(SOC_SHA_SUPPORT_SHA1)
void sha1_dma(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *... | 585 |
/*
#pragma once
#include "soc/soc_caps.h"
#include "hal/sha_types.h"
#if SOC_SHA_SUPPORTED
#define PUT_UINT32_BE(n,b,i) \
{ \
(b)[(i) ] = (unsigned char) ( (n) >> 24 ); \
(b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); ... | 586 |
< number of bytes processed */
uint32_t state[5]; /*!< intermediate digest state */
unsigned char buffer[64]; /*!< data block being processed */
int first_block; /*!< if first then true else false */
esp_sha_type mode;
esp_sha_state sha_state;
} sha1_ctx;
#endif /* defined(S... | 586 |
< number of bytes processed */
uint64_t state[8]; /*!< intermediate digest state */
unsigned char buffer[128]; /*!< data block being processed */
int first_block;
uint32_t t_val; /*!< t_val for 512/t mode */
esp_sha_type mode;
esp_sha_state sha_state;
} sha512_ctx;
#if S... | 586 |
/*
static const uint8_t ecc_p192_point_x[] = {
0x18, 0x8D, 0xA8, 0x0E, 0xB0, 0x30, 0x90, 0xF6,
0x7C, 0xBF, 0x20, 0xEB, 0x43, 0xA1, 0x88, 0x00,
0xF4, 0xFF, 0x0A, 0xFD, 0x82, 0xFF, 0x10, 0x12
};
static const uint8_t ecc_p192_point_y[] = {
0x07, 0x19, 0x2B, 0x95, 0xFF, 0xC8, 0xDA, 0x78,
0x63, 0x10, 0... | 587 |
/*
*/
#pragma once
#include
#if SOC_AES_SUPPORTED
void aes_crypt_cbc_block(int mode,
uint8_t key_bytes,
const uint8_t key[32],
size_t length,
unsigned char iv[16],
const unsigned char *input,
... | 588 |
/*
#include "soc/soc_caps.h"
#if SOC_AES_SUPPORTED
#define ESP_AES_ENCRYPT 1 /**< AES encryption. */
#define ESP_AES_DECRYPT 0 /**< AES decryption. */
#define TEST_AES_MALLOC_CAPS (MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA)
static const uint8_t key_256[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0... | 589 |
/*
*/
#include
#include "esp_err.h"
#include "hal/i2c_types.h"
#include "hal/i2c_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct {
int scl_pin; /*!< SCL PIN, -1 means not change the current pin*/
int sda_pin; /*!< SDA PIN, -1 means not change the current pin*/
ui... | 590 |
/*
*/
#pragma once
#include
#include
#include
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/dport_reg.h"
#include "soc/hwcrypto_periph.h"
#include "soc/mpi_periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void mpi_ll_enable_bus_clock(bool enable)
{
if (enable) {
... | 591 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; mpi_ll_reset_register(__VA_ARGS__)
/* Round up number of words to nearest
512 bit (16 word) block count.
*/
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return (words + 0xF) & ~0xF;
}
static inline void mpi_ll_clear_power_control_bit(void)
{
DPORT... | 591 |
If num_words is higher than the number of words (n) in the bignum then
these additional words will be zeroed in the memory buffer.
*/
/* Please see detailed note inside the function body below.
https://github.com/espressif/esp-idf/issues/8710
https://github.com/espressif/esp-idf/issu... | 591 |
/*
*/
/
/
// The Lowlevel layer for TWAI
#pragma once
#include
#include
#include
#include "esp_assert.h"
#include "sdkconfig.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/twai_types.h"
#include "soc/twai_periph.h"
#include "soc/twai_struct.h"
#include "soc/dport_reg.h"
#define TWAI_LL_GET_HW(... | 592 |
lom = 0;
hw->mode_reg.stm = 0;
} else if (mode == TWAI_MODE_NO_ACK) { //Self Test Mode (No Ack)
hw->mode_reg.lom = 0;
hw->mode_reg.stm = 1;
} else if (mode == TWAI_MODE_LISTEN_ONLY) { //Listen Only Mode
hw->mode_reg.lom = 1;
hw->mode_reg.stm = 0;
}
}
/* Com... | 592 |
cdo = 1;
}
/**
*/
__attribute__((always_inline))
static inline void twai_ll_set_cmd_self_rx_request(twai_dev_t *hw)
{
hw->command_reg.srr = 1;
}
/**
*/
__attribute__((always_inline))
static inline void twai_ll_set_cmd_self_rx_single_shot(twai_dev_t *hw)
{
hw->command_reg.val = 0x12;
}
/* Status Register ... | 592 |
Need to mask it out
hw->interrupt_enable_reg.val = (hw->interrupt_enable_reg.val & 0x10) | intr_mask;
#else
hw->interrupt_enable_reg.val = intr_mask;
#endif
}
/* Bus Timing Registers */
/**
*/
__attribute__((always_inline))
static inline bool twai_ll_check_brp_validation(uint32_t brp)
{
bool valid = (... | 592 |
tseg1 = tseg1 - 1;
hw->bus_timing_1_reg.tseg2 = tseg2 - 1;
hw->bus_timing_1_reg.sam = triple_sampling;
}
/* ALC Register */
/**
*/
__attribute__((always_inline))
static inline void twai_ll_clear_arb_lost_cap(twai_dev_t *hw)
{
(void)hw->arbitration_lost_captue_reg.val;
}
/* ECC Register */
/**
*/
_... | 592 |
val;
}
/* RX Error Count Register */
/**
*/
__attribute__((always_inline))
static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
{
return hw->rx_error_counter_reg.val;
}
/**
*/
__attribute__((always_inline))
static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
{
HAL_FORCE_MODIFY_U32_REG_FIEL... | 592 |
acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
}
hw->mode_reg.afm = single_filter;
}
/* TX/RX Buffer Registers */
/**
*/
__attribute__((always_inline))
static inline void twai_ll_set_tx_buffe... | 592 |
1 : 0;
tx_frame->single_shot = (flags & TWAI_MSG_FLAG_SS) ? 1 : 0;
//Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required
if (is_extd) {
uint32_t id_temp = HAL_SWAP32((id & TWAI_EXTD_ID_MASK) > 8*(3-i))
for (int i = 0; i extended.id[i] = (id_temp >> ... | 592 |
The ID registers are big endian and left aligned, therefore a bswap will be required
if (rx_frame->frame_format) {
uint32_t id_temp = 0;
for (int i = 0; i extended.id[i] > 3; //((byte[i] > 3)
*id = id_temp & TWAI_EXTD_ID_MASK;
} else {
uint32_t id_temp = 0;
for (int i =... | 592 |
cd = (divider / 2) - 1;
} else if (divider == 1) {
//Setting the divider reg to max value (7) means a divider of 1
hw->clock_divider_reg.co = 0;
hw->clock_divider_reg.cd = 7;
} else {
hw->clock_divider_reg.co = 1;
hw->clock_divider_reg.cd = 0;
}
}
/**
*/
__attribute... | 592 |
val;
for (int i = 0; i acr_reg[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte);
reg_save->amr_reg[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte);
}
reg_save->rx_error_counter_reg = (uint8_t) hw->rx_error_counter_reg.val;
reg_save->tx_error_counter_reg... | 592 |
amr[i], byte, reg_save->amr_reg[i]);
}
hw->rx_error_counter_reg.val = reg_save->rx_error_counter_reg;
hw->tx_error_counter_reg.val = reg_save->tx_error_counter_reg;
hw->clock_divider_reg.val = reg_save->clock_divider_reg;
}
#endif //defined(CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID) || defined(CONFIG_TWA... | 592 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/timer_periph.h"
#include "soc/timer_gr... | 593 |
wdt_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
hw->wdtconfig0.wdt_en = 0;
}
/**
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
return (hw->wdtconfig0.wdt_en) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_... | 593 |
wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
bre... | 593 |
wdt_flashboot_mod_en = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescaler, prescaler);
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
{
hw->wdtfeed.wdt_feed = 1;
}
/**
... | 593 |
/*
*/
#pragma once
#include "soc/hwcrypto_reg.h"
#include "soc/dport_access.h"
#include "hal/aes_types.h"
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
typedef enum {
ESP_AES_STATE_BUSY = 0, /* Transform in progress */
ESP_AES_STATE_IDLE, /* AES accelerator is idle */
} esp_aes_state_t;
/**
... | 594 |
0 : MODE_DECRYPT_BIT;
/* See TRM for the mapping between keylength and mode bit */
DPORT_REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2));
}
/**
*/
static inline void aes_ll_write_block(const uint8_t *input)
{
const uint32_t *input_words = (const uint32_t *)input;
uint32_t i0;
uint... | 594 |
/*
*/
// The LL layer for I2C register operations
#pragma once
#include
#include "hal/misc.h"
#include "soc/i2c_periph.h"
#include "soc/i2c_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/dport_reg.h"
#include "hal/i2c_types.h"
#include "esp_attr.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#... | 595 |
en) {
if (hw->scl_filter_cfg.thres scl_filter_cfg.thres scl_filter_cfg.thres + 6;
}
} else {
scl_high -= 7;
}
hw->scl_high_period.period = scl_high;
//sda sample
hw->sda_hold.time = bus_cfg->sda_hold;
hw->sda_sample.time = bus_cfg->sda_sample;
//setup
hw->scl_rsta... | 595 |
val = mask;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
}
/**
*/
_... | 595 |
addr = addr_14_7 || addr_6_0;
} else {
hw->slave_addr.addr = slave_addr;
}
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cmd, int cmd_idx)
{
hw->command[cmd_idx].val = cmd.val;
}
/**
*/
static inline void i2c_ll_master_set_s... | 595 |
nonfifo_rx_thres = full_thr;
hw->fifo_conf.rx_fifo_full_thrhd = full_thr;
}
/**
*/
static inline void i2c_ll_set_data_mode(i2c_dev_t *hw, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mode)
{
hw->ctr.tx_lsb_first = tx_mode;
hw->ctr.rx_lsb_first = rx_mode;
}
/**
*/
static inline void i2c_ll_get_sda_timin... | 595 |
tout;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
/**
*/
static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
{
*setup_time = hw->scl_rstart_setup.time;
*hold_time = hw->scl_start_h... | 595 |
en = 1;
} else {
hw->scl_filter_cfg.en = 0;
hw->sda_filter_cfg.en = 0;
}
}
/**
*/
static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
{
*filter_conf = hw->sda_filter_cfg.thres;
}
/**
*/
static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
{
;//ESP32 do ... | 595 |
val = 0;
ctrl_reg.sda_force_out = 1;
ctrl_reg.scl_force_out = 1;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_update(i2c_dev_t *hw)
{
;// ESP32 do not support
}
/**
*/
static inline void i2c_ll_enable_bus_clock(... | 595 |
0)//////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I2C master TX interrupt bitmap
#define I2C_LL_MASTER_TX_INT (I2C_ACK_ERR_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LO... | 595 |
period = low_period;
hw->scl_high_period.period = high_period;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.tx_fifo_empty) {
*event = I2C... | 595 |
end_detect) {
*event = I2C_INTR_EVENT_END_DET;
} else if (int_sts.trans_complete) {
*event = I2C_INTR_EVENT_TRANS_DONE;
} else {
*event = I2C_INTR_EVENT_ERR;
}
}
/**
*/
static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw)
{
hw->int_ena.val |= I2C_LL_SLAVE_TX_INT;
}
/**
... | 595 |
val = UINT32_MAX;
hw->int_ena.val = I2C_LL_MASTER_RX_INT;
}
/**
*/
static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT);
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_... | 595 |
period;
*low_period = hw->scl_low_period.period;
}
#ifdef __cplusplus
}
#endif
| 595 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#include "hal/efuse_ll.h"
#include_next "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
uint32_t efuse_hal_get_rated_freq_mhz(void);
/**
*/
void efuse_hal_set_timing(uint32_t apb_freq_mhz);
/**
*/
void efuse_hal_read(void);
/**
... | 596 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash Encryption.
#include "soc/dport_reg.h"
#include "soc/flash_encryption_reg.h"
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void spi_flash_encrypt_ll_enable(void)
{
DPORT_REG_SET_BIT(DPORT_SLAVE_SPI_CONFIG_REG, DPORT_SLAVE_SPI_MASK_PRO | D... | 597 |
true : false;
}
#ifdef __cplusplus
}
#endif
| 597 |
/*
*/
/**
*/
#pragma once
#include
#include "soc/sens_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on
SAR_CTRL_LL_POWER_OFF, //SAR power off
} sar_ctrl_ll_power_t;
/*
... | 598 |
/*
*/
#pragma once
#include
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline void trace_ll_mem_enable(int cpu, bool enable)
{
int reg[] = {DPORT_PRO_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_REG};
DPORT_WRITE_PERI_REG(reg[cpu], enable);
}
static inline void trace_ll_set_mode... | 599 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/wdt_types.h"
#include "soc/rtc_cntl_periph.h"
#include "soc/rtc_cntl_struct.h"
#incl... | 600 |
en = 1;
}
/**
*/
FORCE_INLINE_ATTR void rwdt_ll_disable(rtc_cntl_dev_t *hw)
{
hw->wdt_config0.en = 0;
}
/**
*/
FORCE_INLINE_ATTR bool rwdt_ll_check_if_enabled(rtc_cntl_dev_t *hw)
{
return (hw->wdt_config0.en) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stag... | 600 |
stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->wdt_config0.stg3 = WDT_STAGE_... | 600 |
flashboot_mod_en = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR void rwdt_ll_set_procpu_reset_en(rtc_cntl_dev_t* hw, bool enable)
{
hw->wdt_config0.procpu_reset_en = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR void rwdt_ll_set_appcpu_reset_en(rtc_cntl_dev_t* hw, bool enable)
{
hw->wdt_config0.appcpu_reset_... | 600 |
rtc_wdt) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void rwdt_ll_clear_intr_status(rtc_cntl_dev_t* hw)
{
hw->int_clr.rtc_wdt = 1;
}
#ifdef __cplusplus
}
#endif
| 600 |
/*
*/
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "hal/misc.h"
#include "esp_attr.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/dport_reg.h"
#include "hal/uart_types.h"
... | 601 |
tick_ref_always_on) {
default:
case 0:
*source_clk = (soc_module_clk_t)UART_SCLK_REF_TICK;
break;
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_APB;
break;
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t ba... | 601 |
val;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_clr.val = mask;
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
{
return hw->int_ena.val;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, ... | 601 |
txfifo_rst = 1;
hw->conf0.txfifo_rst = 0;
}
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
{
uint32_t fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
typeof(hw->mem_rx_status) rx_status;
rx_status.val = hw->mem_rx_status.val;
uint32_t len = 0;
... | 601 |
if(stop_bit == UART_STOP_BITS_2) {
hw->rs485_conf.dl1_en = 1;
hw->conf0.stop_bit_num = 0x1;
} else {
hw->rs485_conf.dl1_en = 0;
hw->conf0.stop_bit_num = stop_bit;
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
{
//w... | 601 |
parity);
} else {
*parity_mode = UART_PARITY_DISABLE;
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
{
hw->conf1.rxfifo_full_thrhd = full_thrhd;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
... | 601 |
if(flow_ctrl & UART_HW_FLOWCTRL_RTS) {
hw->conf1.rx_flow_thrhd = rx_thrs;
hw->conf1.rx_flow_en = 1;
} else {
hw->conf1.rx_flow_en = 0;
}
if(flow_ctrl & UART_HW_FLOWCTRL_CTS) {
hw->conf0.tx_flow_en = 1;
} else {
hw->conf0.tx_flow_en = 0;
}
}
/**
*/
FORCE... | 601 |
sw_flow_con_en = 0;
hw->flow_conf.xonoff_del = 0;
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char... | 601 |
active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
{
hw->rs485_conf.en = 0;
hw->rs485_conf.tx_rx_en = 0;
hw->rs485_conf.rx_busy_tx_en = 0;
hw->conf0.irda_en = 0;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_a... | 601 |
irda_en = 0;
// Transmitters output signal loop back to the receivers input signal
hw->rs485_conf.tx_rx_en = 1 ;
// Transmitter should send data when the receiver is busy
hw->rs485_conf.rx_busy_tx_en = 1;
hw->conf0.sw_rts = 0;
hw->rs485_conf.en = 1;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_... | 601 |
active_threshold + UART_LL_MIN_WAKEUP_THRESH;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
{
*data_bit = (uart_word_length_t)hw->conf0.bit_num;
}
/**
*/
FORCE_INLINE_ATTR IRAM_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
{
typeof(hw->status) status;
... | 601 |
irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0;
conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0;
conf0_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0;
conf0_reg.dsr_inv = (inv_mask & UART_SIGNAL_DSR_INV) ? 1 : 0;
conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 :... | 601 |
rx_tout_en > 0) {
if (hw->conf0.tick_ref_always_on == 0) {
tout_thrd = (uint16_t)(hw->conf1.rx_tout_thrhd / UART_LL_TOUT_REF_FACTOR_DEFAULT);
} else {
tout_thrd = (uint16_t)(hw->conf1.rx_tout_thrhd conf0.tick_ref_always_on == 0) {
tout_thrd = (uint16_t)(UART_RX_TOUT_THRH... | 601 |
min_cnt;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
{
/* Note: Set `UART_FORCE_XOFF` can't stop new Tx request. */
REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num)
{
REG_CLR_BIT(UART_FLOW_CON... | 601 |
/*
*/
/
/
// The LL layer for ESP32 SPI register operations
#pragma once
#include
#include //for abs()
#include "esp_types.h"
#include "esp32/rom/lldesc.h"
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "soc/dport_reg.h"
#include "hal/misc.h"
#include "hal/spi_types.h"
#include "hal/assert.h"
... | 602 |
val = 0;
//use all 64 bytes of the buffer
hw->user.usr_miso_highpart = 0;
hw->user.usr_mosi_highpart = 0;
//Disable unneeded ints
hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK;
}
/**
*/
static inline void spi_ll_slave_init(spi_dev_t *hw)
{
//Configure slave
hw->clock.val = 0;
hw->user.val... | 602 |
usr = 1;
}
/**
*/
static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw)
{
return hw->cmd.val;
}
/**
*/
static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
{
//This is not used in esp32
}
/**
*/
static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw)
{
//This is not used in esp32
}
/*... | 602 |
master_cs_pol |= (1 pin.master_cs_pol &= ~(1 ctrl.wr_bit_order = lsbfirst;
}
/**
*/
static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst)
{
hw->ctrl.rd_bit_order = lsbfirst;
}
/**
*/
static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode)
{
//Configure polarity
if (mode ... | 602 |
miso_delay_num = 0;
hw->ctrl2.mosi_delay_mode = 2;
hw->ctrl2.mosi_delay_num = 2;
} else if (mode == 1) {
hw->pin.ck_idle_edge = 1;
hw->user.ck_i_edge = 1;
hw->ctrl2.miso_delay_mode = 2;
hw->ctrl2.miso_delay_num = 0;
hw->ctrl2.mosi_delay_mode = 0;
hw->c... | 602 |
ck_idle_edge = 0;
hw->user.ck_i_edge = 1;
hw->ctrl2.miso_delay_mode = 0;
hw->ctrl2.miso_delay_num = 2;
hw->ctrl2.mosi_delay_mode = 0;
hw->ctrl2.mosi_delay_num = 3;
} else if (mode == 2) {
hw->pin.ck_idle_edge = 1;
hw->user.ck_i_... | 602 |
data_lines) {
case 2:
if (line_mode.addr_lines == 1) {
// 1-line-cmd + 1-line-addr + 2-line-data
hw->ctrl.fread_dual = 1;
hw->user.fwrite_dual = 1;
} else if (line_mode.addr_lines == 2) {
// 1-line-cmd + 2-line-addr + 2-line-data
hw->ctrl.f... | 602 |
cs0_dis = (cs_id == 0) ? 0 : 1;
hw->pin.cs1_dis = (cs_id == 1) ? 0 : 1;
hw->pin.cs2_dis = (cs_id == 2) ? 0 : 1;
}
/**
*/
static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active)
{
hw->pin.cs_keep_active = (keep_active != 0) ? 1 : 0;
}
/*
**/
/**
*/
static inline void spi_ll_master_set_c... | 602 |
clk_equ_sysclk = 1;
eff_clk = fapb;
} else {
//For best duty cycle resolution, we want n to be as close to 32 as possible, but
//we also need a pre/n combo that gets us as close as possible to the intended freq.
//To do this, we bruteforce n and calculate the best pre to go along wit... | 602 |
miso_delay_num = delay_num;
}
/**
*/
static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
{
hw->user.usr_dummy = dummy_n ? 1 : 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
}
/**
*/
static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold)
{
hw->ct... | 602 |
bit_len = bitlen - 1;
}
/**
*/
static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen)
{
hw->user2.usr_command_bitlen = bitlen - 1;
hw->user.usr_command = bitlen ? 1 : 0;
}
/**
*/
static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen)
{
hw->user1.usr_addr_bitlen = bitlen - ... | 602 |
usr_miso = enable;
}
/**
*/
static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable)
{
hw->user.usr_mosi = enable;
}
/**
*/
static inline void spi_ll_slave_reset(spi_dev_t *hw)
{
hw->slave.sync_reset = 1;
hw->slave.sync_reset = 0;
}
/**
*/
static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi... | 602 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; spi_dma_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
}
/// use a m... | 602 |
start = 1;
}
/**
*/
static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32_t channel, bool enable)
{
//This is not supported in esp32
}
/**
*/
static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32_t channel, bool enable)
{
dma_in->dma_conf.indscr_burst_en... | 602 |
outdscr_burst_en = enable;
}
/**
*/
static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uint32_t channel, bool enable)
{
dma_out->dma_conf.out_eof_mode = enable;
}
/**
*/
static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uint32_t channel, bool enable)
{
//... | 602 |
/*
*/
// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
// This Low Level driver only serve the General Purpose Timer function.
#pragma once
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/timer_types.h"
#include "soc... | 603 |
config.tx_autoreload = en;
}
/**
*/
static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction)
{
hw->hw_timer[timer_num].config.tx_increase = direction == GPTIMER_COUNT_UP;
}
/**
*/
__attribute__((always_inline))
static inline void timer_ll_enable_co... | 603 |
hi.tx_hi hw_timer[timer_num].lo.tx_lo);
}
/**
*/
__attribute__((always_inline))
static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value)
{
hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32);
hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (u... | 603 |
load.tx_load = 1;
}
/**
*/
__attribute__((always_inline))
static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en)
{
if (en) {
hw->int_ena_timers.val |= mask;
} else {
hw->int_ena_timers.val &= ~mask;
}
}
/**
*/
__attribute__((always_inline))
static inline uint32_t... | 603 |
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