text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
e.
*/
addr = HAL_SWAP32(addr);
//otherwise only addr register is sent
hw->addr = addr;
} else {
// shift the address to MSB of addr register.
// output address will be sent from MSB to LSB of addr register
hw->addr = addr user2, usr_command_value, cmd);
} ... | 770 |
data_bitlen;
}
/*
**/
//helper macros to generate code for each interrupts
#define FOR_EACH_ITEM(op, list) do { list(op) } while(0)
#define INTR_LIST(item) \
item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_in... | 770 |
dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \
item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7, dma_int_set.cmd7_int_set) \
item(SPI_LL_INTR_CMD8, ... | 770 |
..) if (intr_mask & (intr_bit)) hw->en_reg = 0;
FOR_EACH_ITEM(DIS_INTR, INTR_LIST);
#undef DIS_INTR
}
static inline void spi_ll_set_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
{
#define SET_INTR(intr_bit, _, __, ___, set_reg) if (intr_mask & (intr_bit)) hw->set_reg = 1;
FOR_EACH_ITEM(SET_INTR, INTR_LIST);
#un... | 770 |
trans_done = 1;
}
/**
*/
static inline void spi_ll_set_int_stat(spi_dev_t *hw)
{
hw->dma_int_set.trans_done_int_set = 1;
}
/**
*/
static inline void spi_ll_enable_int(spi_dev_t *hw)
{
hw->dma_int_ena.trans_done = 1;
}
/*
**/
static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_c... | 770 |
data_lines == 2) {
if (line_mode.addr_lines == 2) {
cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit
} else {
cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit
}
} else if (line_mode.data_lines == 4) {
if (line_mode.addr_lines == 4) {
cmd_mod ... | 770 |
/*
*/
// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
// This Low Level driver only serve the General Purpose Timer function.
#pragma once
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/timer_types.h"
#include "soc... | 771 |
config.tn_alarm_en = en;
}
/**
*/
static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider)
{
HAL_ASSERT(divider >= 2 && divider = 65536) {
divider = 0;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tn_divider, divider);
hw->hw_time... | 771 |
update.tn_update = 1;
// Timer register is in a different clock domain from Timer hardware logic
// We need to wait for the update to take effect before fetching the count value
while (hw->hw_timer[timer_num].update.tn_update) {
}
}
/**
*/
__attribute__((always_inline))
static inline uint64_t timer_ll... | 771 |
loadlo.tn_load_lo = (uint32_t)reload_val;
}
/**
*/
__attribute__((always_inline))
static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
{
return ((uint64_t)hw->hw_timer[timer_num].loadhi.tn_load_hi hw_timer[timer_num].loadlo.tn_load_lo);
}
/**
*/
__attribute__((always_inline))
sta... | 771 |
clk_en = en;
}
/**
*/
static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
{
return &hw->int_st_timers;
}
#ifdef __cplusplus
}
#endif
| 771 |
/*
*/
#pragma once
#include
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/system_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/regi2c_defs.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h"
#include "hal/assert.h"
#include "hal/log.h"
#include "esp32s3/rom/rtc.h"
#ifdef __cplusp... | 772 |
xtal_xpd_st; enabled = !disabled
bool enabled = !xtal_xpd_sw || xtal_xpd_st;
return enabled;
}
/**
*/
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CL... | 772 |
= 0 && xtal_freq_reg != UINT32_MAX) {
return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
}
// If the format in reg is invalid
return 0;
}
/**
*/
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
{
REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
... | 772 |
/*
*/
// The LL layer for xtal32k WDT register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "soc/rtc_cntl_periph.h"
#ifdef __cplusplus
extern "C" {
#endif
#define XT_WDT_LL_XTAL32_DEAD_INTR_MASK RTC_CNTL_XTAL32K_DEAD_INT_ST_M
/*... | 773 |
xtal32k_auto_backup = enable;
}
/**
*/
inline void xt_wdt_ll_intr_enable(rtc_cntl_dev_t *hw, bool enable)
{
hw->int_ena.rtc_xtal32k_dead = enable;
}
#ifdef __cplusplus
}
#endif
| 773 |
/*
*/
/
/
#pragma once
#include /* For size_t type */
#include
#include "soc/hwcrypto_reg.h"
#include "soc/system_struct.h"
#include "hal/hmac_types.h"
#define SHA256_BLOCK_SZ 64
#define SHA256_DIGEST_SZ 32
#define HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_JTAG 6
#define HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_DIGITAL_SIGNATURE ... | 774 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; hmac_ll_reset_register(__VA_ARGS__)
/**
*/
static inline void hmac_ll_start(void)
{
REG_WRITE(HMAC_SET_START_REG, 1);
}
/**
*/
static inline void hmac_ll_config_output(hmac_hal_output_t config)
{
switch(config) {
case HMAC_OUTPUT_USER:
REG_WRITE(HMAC_SET_PARA_... | 774 |
= 0);
}
/**
*/
static inline void hmac_ll_write_block_512(const uint32_t *block)
{
const size_t REG_WIDTH = sizeof(uint32_t);
for (size_t i = 0; i < SHA256_BLOCK_SZ / REG_WIDTH; i++) {
REG_WRITE(HMAC_WDATA_BASE + (i * REG_WIDTH), block[i]);
}
REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1);
}
/**
*/... | 774 |
/*
*/
/**
*/
#pragma once
#include
#include
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/rmt_struct.h"
#include "soc/system_struct.h"
#include "hal/rmt_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RMT_LL_EVENT_TX_DONE(channel) (1 sys_conf.clk_en = enable; // register clo... | 775 |
sclk_div_a = divider_numerator;
dev->sys_conf.sclk_div_b = divider_denominator;
switch (src) {
case RMT_CLK_SRC_APB:
dev->sys_conf.sclk_sel = 1;
break;
case RMT_CLK_SRC_RC_FAST:
dev->sys_conf.sclk_sel = 2;
break;
case RMT_CLK_SRC_XTAL:
dev->sys_conf.sclk_sel =... | 775 |
mem_rd_rst_chn = 1;
dev->chnconf0[channel].mem_rd_rst_chn = 0;
dev->chnconf0[channel].apb_mem_rst_chn = 1;
dev->chnconf0[channel].apb_mem_rst_chn = 0;
}
/**
*/
static inline void rmt_ll_tx_enable_dma(rmt_dev_t *dev, uint32_t channel, bool enable)
{
HAL_ASSERT(channel == 3 && "only TX channel 3 has DMA... | 775 |
mem_size_chn = block_num;
}
/**
*/
static inline void rmt_ll_tx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0[channel].mem_tx_wrap_en_chn = enable;
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
{
d... | 775 |
loop_stop_en_chn = enable;
}
/**
*/
static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable)
{
dev->tx_sim.tx_sim_en = enable;
}
/**
*/
static inline void rmt_ll_tx_clear_sync_group(rmt_dev_t *dev)
{
dev->tx_sim.val &= ~(0x0F);
}
/**
*/
static inline void rmt_ll_tx_sync_group_add_channels(rmt... | 775 |
carrier_en_chn = enable;
}
/**
*/
static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->chnconf0[channel].carrier_out_lv_chn = level;
}
/**
*/
static inline void rmt_ll_tx_enable_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0... | 775 |
conf1.apb_mem_rst_chm = 1;
dev->chmconf[channel].conf1.apb_mem_rst_chm = 0;
}
/**
*/
static inline void rmt_ll_rx_enable_dma(rmt_dev_t *dev, uint32_t channel, bool enable)
{
HAL_ASSERT(channel == 3 && "only RX channel 3 has DMA ability");
dev->chmconf[channel].conf0.dma_access_en_chm = enable;
}
/**
*/
... | 775 |
conf1.mem_owner_chm = owner;
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[channel].conf1.rx_filter_en_chm = enable;
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t ... | 775 |
conf0.carrier_en_chm = enable;
}
/**
*/
static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->chmconf[channel].conf0.carrier_out_lv_chm = level;
}
/**
*/
static inline void rmt_ll_rx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[ch... | 775 |
val & RMT_LL_EVENT_TX_MASK(channel);
}
/**
*/
static inline uint32_t rmt_ll_tx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel)
{
return dev->int_raw.val & (RMT_LL_EVENT_TX_MASK(channel) | RMT_LL_EVENT_TX_ERROR(channel));
}
/**
*/
static inline uint32_t rmt_ll_rx_get_interrupt_status_raw(rmt_dev_t *de... | 775 |
val;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmstatus[channel].val;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
{
uint32_t div = HAL_FORCE_RE... | 775 |
conf0.mem_size_chm;
}
__attribute__((always_inline))
static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnconf0[channel].tx_conti_mode_chn;
}
__attribute__((always_inline))
static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel)
{
... | 775 |
mem_force_pd) || !(dev->sys_conf.mem_force_pu);
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmconf[channel].conf1.mem_owner_chm;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t... | 775 |
val >> 8) & 0x0F;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 24) & 0x0F;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 12) &... | 775 |
/*
*/
/
/
// The LL layer for ESP32-S3 MCPWM register operations
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/mcpwm_struct.h"
#include "hal/mcpwm_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
// Get MCPWM group regi... | 776 |
global_force_up = 1;
mcpwm->update_cfg.global_force_up = 0;
}
//////////////////////////////////////////Interrupt Specific////////////////////////////////////////////////////////////
/**
*/
static inline volatile void *mcpwm_ll_intr_get_status_reg(mcpwm_dev_t *mcpwm)
{
return &mcpwm->int_st;
}
/**
*/
stati... | 776 |
timer_cfg0, timer_prescale, prescale - 1);
}
/**
*/
__attribute__((always_inline))
static inline void mcpwm_ll_timer_set_peak(mcpwm_dev_t *mcpwm, int timer_id, uint32_t peak, bool symmetric)
{
if (!symmetric) { // in asymmetric mode, period = [0,peak-1]
HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id... | 776 |
timer_cfg0.timer_period_upmethod |= 0x02;
} else {
mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x02;
}
}
/**
*/
static inline void mcpwm_ll_timer_set_count_mode(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_count_mode_t mode)
{
switch (mode) {
case MCPWM_TIMER_COUNT_MODE_PAUSE:... | 776 |
timer_cfg1.timer_start = 0;
break;
case MCPWM_TIMER_STOP_FULL:
mcpwm->timer[timer_id].timer_cfg1.timer_start = 1;
break;
case MCPWM_TIMER_START_NO_STOP:
mcpwm->timer[timer_id].timer_cfg1.timer_start = 2;
break;
case MCPWM_TIMER_START_STOP_EMPTY:
mcpwm->timer[t... | 776 |
timer_status.timer_direction) { // down direction
return (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value) + 1) %
(HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + 1);
}
// up direction
return (HAL_FORCE_READ_U32_REG_FIELD(m... | 776 |
timer_sync.timer_synco_sel = 0;
}
/**
*/
static inline void mcpwm_ll_timer_sync_out_on_timer_event(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_event_t event)
{
switch (event) {
case MCPWM_TIMER_EVENT_EMPTY:
mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 1;
break;
case MCPWM_TIMER_EV... | 776 |
timer_sync, timer_phase, phase_value);
}
/**
*/
static inline void mcpwm_ll_timer_set_sync_phase_direction(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_direction_t direction)
{
mcpwm->timer[timer_id].timer_sync.timer_phase_direction = direction;
}
/**
*/
static inline void mcpwm_ll_timer_set_gpio_sync_input(mc... | 776 |
gen_stmp_cfg.val &= ~((1 operators[operator_id].gen_stmp_cfg.val |= (1 operators[operator_id].gen_stmp_cfg.val &= ~((1 operators[operator_id].timestamp[compare_id], gen, compare_value);
}
/**
*/
static inline void mcpwm_ll_operator_update_action_at_once(mcpwm_dev_t *mcpwm, int operator_id)
{
mcpwm->operators[oper... | 776 |
gen_cfg0.val |= (fault_gpio_id operators[operator_id].gen_cfg0.val &= ~(0x07 operators[operator_id].gen_cfg0.val |= (3 operators[operator_id].generator[generator_id].val = 0;
}
/**
*/
static inline void mcpwm_ll_generator_set_action_on_timer_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id,
... | 776 |
generator[generator_id].val &= ~(0x03 operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) operators[operator_id].generator[generator_id].val &= ~(0x03 operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) operators[operator_id].generator[ge... | 776 |
gen_force.gen_cntuforce_upmethod = 0; // update force method immediately
if (generator_id == 0) {
mcpwm->operators[operator_id].gen_force.gen_a_cntuforce_mode = 0;
} else {
mcpwm->operators[operator_id].gen_force.gen_b_cntuforce_mode = 0;
}
}
/**
*/
static inline void mcpwm_ll_gen_disable_... | 776 |
gen_force.gen_b_cntuforce_mode = level + 1;
}
}
/**
*/
static inline void mcpwm_ll_gen_set_noncontinue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level)
{
if (generator_id == 0) {
mcpwm->operators[operator_id].gen_force.gen_a_nciforce_mode = level + 1;
} else {
... | 776 |
dt_cfg.dt_red_insel = generator;
}
/**
*/
static inline void mcpwm_ll_deadtime_fed_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generator)
{
mcpwm->operators[operator_id].dt_cfg.dt_fed_insel = generator;
}
/**
*/
static inline void mcpwm_ll_deadtime_bypass_path(mcpwm_dev_t *mcpwm, int operator_id, ... | 776 |
dt_red_insel operators[operator_id].dt_cfg.dt_fed_outinvert operators[operator_id].dt_cfg.dt_red_outinvert operators[operator_id].dt_cfg.dt_a_outbypass operators[operator_id].dt_cfg.dt_b_outbypass operators[operator_id].dt_fed_cfg, dt_fed, fed - 1);
}
/**
*/
static inline void mcpwm_ll_deadtime_set_rising_delay(mcpwm... | 776 |
dt_cfg.dt_red_upmethod &= ~(1 operators[operator_id].dt_cfg.dt_fed_upmethod |= 1 operators[operator_id].dt_cfg.dt_red_upmethod |= 1 operators[operator_id].dt_cfg.dt_fed_upmethod &= ~(1 operators[operator_id].dt_cfg.dt_red_upmethod &= ~(1 operators[operator_id].dt_cfg.dt_fed_upmethod |= 1 operators[operator_id].dt_cfg.d... | 776 |
carrier_cfg.carrier_duty = carrier_duty;
}
/**
*/
static inline void mcpwm_ll_carrier_out_invert(mcpwm_dev_t *mcpwm, int operator_id, bool invert)
{
mcpwm->operators[operator_id].carrier_cfg.carrier_out_invert = invert;
}
/**
*/
static inline void mcpwm_ll_carrier_in_invert(mcpwm_dev_t *mcpwm, int operator_id, ... | 776 |
val &= ~(1 operators[operator_id].fh_cfg1.fh_clr_ost = 0;
mcpwm->operators[operator_id].fh_cfg1.fh_clr_ost = 1;
}
/**
*/
static inline void mcpwm_ll_brake_enable_oneshot_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable)
{
if (enable) {
mcpwm->operators[operator_id].fh_cfg0.val |= (... | 776 |
fh_cfg1.fh_force_cbc;
}
/**
*/
static inline void mcpwm_ll_brake_trigger_soft_ost(mcpwm_dev_t *mcpwm, int operator_id)
{
mcpwm->operators[operator_id].fh_cfg1.fh_force_ost = ~mcpwm->operators[operator_id].fh_cfg1.fh_force_ost;
}
/**
*/
static inline bool mcpwm_ll_ost_brake_active(mcpwm_dev_t *mcpwm, int operato... | 776 |
cap_timer_phase = phase_value;
}
/**
*/
static inline void mcpwm_ll_capture_enable_timer_sync(mcpwm_dev_t *mcpwm, bool enable)
{
mcpwm->cap_timer_cfg.cap_synci_en = enable;
}
/**
*/
static inline void mcpwm_ll_capture_set_timer_sync(mcpwm_dev_t *mcpwm, int sync_out_timer)
{
mcpwm->cap_timer_cfg.cap_synci_se... | 776 |
capn_sw = 1; // auto clear
}
/**
*/
__attribute__((always_inline))
static inline uint32_t mcpwm_ll_capture_get_value(mcpwm_dev_t *mcpwm, int channel)
{
return mcpwm->cap_chn[channel].capn_value;
}
/**
*/
__attribute__((always_inline))
static inline mcpwm_capture_edge_t mcpwm_ll_capture_get_edge(mcpwm_dev_t *mcp... | 776 |
val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}
static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, bool symmetric)
{
return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + (symmetric ? 0 : 1);
}
static inline mcpwm_ti... | 776 |
val >> 27) & 0x07;
}
__attribute__((always_inline))
static inline void mcpwm_ll_intr_clear_capture_status(mcpwm_dev_t *mcpwm, uint32_t capture_mask)
{
mcpwm->int_clr.val = (capture_mask & 0x07) << 27;
}
#ifdef __cplusplus
}
#endif
| 776 |
/*
*/
#pragma once
#include /* For NULL declaration */
#include
#include
#include "hal/misc.h"
#include "soc/lcd_cam_reg.h"
#include "soc/lcd_cam_struct.h"
#include "hal/assert.h"
#include "hal/lcd_types.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LCD_LL_GET_HW(id) (((id) == ... | 777 |
perip_rst_en1.lcd_cam_rst = 0x00;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define lcd_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; lcd_ll_reset_register(__VA_ARGS_... | 777 |
lcd_clkm_div_a = div_a;
dev->lcd_clock.lcd_clkm_div_b = div_b;
}
/**
*/
__attribute__((always_inline))
static inline void lcd_ll_set_clock_idle_level(lcd_cam_dev_t *dev, bool level)
{
dev->lcd_clock.lcd_ck_idle_edge = level;
}
/**
*/
__attribute__((always_inline))
static inline void lcd_ll_set_pixel_clock_e... | 777 |
lcd_conv_mode_8bits_on = (width == 8) ? 1 : 0;
}
/**
*/
static inline void lcd_ll_set_input_color_range(lcd_cam_dev_t *dev, lcd_color_range_t range)
{
if (range == LCD_COLOR_RANGE_LIMIT) {
dev->lcd_rgb_yuv.lcd_conv_data_in_mode = 0;
} else if (range == LCD_COLOR_RANGE_FULL) {
dev->lcd_rgb_yuv.... | 777 |
lcd_conv_trans_mode = 1;
dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 3;
switch (yuv_sample) {
case LCD_YUV_SAMPLE_422:
dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 0;
break;
case LCD_YUV_SAMPLE_420:
dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 1;
break;
case LCD_YUV_SAMPLE_411:
... | 777 |
= dst_sample);
dev->lcd_rgb_yuv.lcd_conv_trans_mode = 1;
switch (src_sample) {
case LCD_YUV_SAMPLE_422:
dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 0;
break;
case LCD_YUV_SAMPLE_420:
dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 1;
break;
case LCD_YUV_SAMPLE_411:
dev->lcd_rgb... | 777 |
lcd_dummy = (dummy_cycles > 0);
dev->lcd_user.lcd_dout = (data_cycles > 0);
dev->lcd_user.lcd_cmd_2_cycle_en = cmd_cycles > 1;
dev->lcd_user.lcd_dummy_cyclelen = dummy_cycles - 1;
dev->lcd_user.lcd_dout_cyclelen = data_cycles - 1;
}
/**
*/
static inline void lcd_ll_set_blank_cycles(lcd_cam_dev_t *dev,... | 777 |
lcd_always_out_en = en;
}
/**
*/
__attribute__((always_inline))
static inline void lcd_ll_start(lcd_cam_dev_t *dev)
{
dev->lcd_user.lcd_update = 1; // update parameters before start transaction
dev->lcd_user.lcd_start = 1;
}
/**
*/
__attribute__((always_inline))
static inline void lcd_ll_stop(lcd_cam_dev_t ... | 777 |
lcd_8bits_order = en;
}
/**
*/
static inline void lcd_ll_set_swizzle_mode(lcd_cam_dev_t *dev, lcd_ll_swizzle_mode_t mode)
{
HAL_ASSERT(mode == LCD_LL_SWIZZLE_AB2BA);
}
/**
*/
__attribute__((always_inline))
static inline void lcd_ll_fifo_reset(lcd_cam_dev_t *dev)
{
dev->lcd_misc.lcd_afifo_reset = 1; // self ... | 777 |
lcd_cmd_value = command;
}
/**
*/
static inline void lcd_ll_enable_rgb_mode(lcd_cam_dev_t *dev, bool en)
{
dev->lcd_ctrl.lcd_rgb_mode_en = en;
}
/**
*/
static inline void lcd_ll_enable_auto_next_frame(lcd_cam_dev_t *dev, bool en)
{
// in RGB mode, enabling "next frame" means LCD controller keeps sending fra... | 777 |
lcd_ht_width = hsw + hbp + active_width + hfp - 1;
}
/**
*/
static inline void lcd_ll_set_vertical_timing(lcd_cam_dev_t *dev, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp)
{
dev->lcd_ctrl2.lcd_vsync_width = vsw - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lcd_ctrl1, lcd_vb_front, vbp + vsw - 1... | 777 |
lcd_de_mode = de_delay;
}
/**
*/
static inline void lcd_ll_set_data_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay)
{
uint32_t reg_val = 0;
for (int i = 0; i lcd_data_dout_mode.val = reg_val;
}
/**
*/
static inline void lcd_ll_enable_interrupt(lcd_cam_dev_t *dev, uint32_t mask, bool en)
{
if (en) {
... | 777 |
/*
*/
#pragma once
#include
#include
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/ eFuse fields /
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flas... | 778 |
rd_repeat_data2.secure_boot_en;
}
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_spi_sys_5.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip... | 778 |
rd_repeat_data4.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
return EFUSE.rd_mac_spi_sys_3.pkg_version;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void)
{
// EFUSE_BLK2, 141, 8, ADC OCode
return... | 778 |
rd_mac_spi_sys_5.v_dig_dbias20;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void)
{
// EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt
return EFUSE.rd_mac_spi_sys_5.dig_dbias_hvt;
}
/ eFuse control functions /
__attribute__((always_inline)) static inline bool ... | 778 |
conf.op_code = EFUSE_WRITE_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
EFUSE.dac_conf.dac_num = val;
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
EFUSE.dac_conf.dac_clk_div = val;
}
__attribute__((always_inlin... | 778 |
/*
*/
#pragma once
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/gpio_sd_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void sdm_ll_enable_clock(gpio_sd_dev_t *hw, bool en)
{
hw->misc.function_clk_en = en;
}
/**
*/
__attribute__((always_inline))
static inline v... | 779 |
/*
*/
#include "soc/system_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
{
if (core_id == 0) {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
} else {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_C... | 780 |
/*
*/
/
/
// The Lowlevel layer for Touch Sensor
#pragma once
#include
#include
#include "hal/misc.h"
#include "soc/touch_sensor_periph.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "soc/soc_caps.h"
#include "hal/touch_sensor_types.h"
#ifdef __cplusplu... | 781 |
touch_scan_ctrl.touch_scan_pad_map \
& TOUCH_PAD_BIT_MASK_ALL;
}
/**
*/
static inline void touch_ll_clear_channel_mask(uint16_t disable_mask)
{
SENS.sar_touch_conf.touch_outen &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
RTCCNTL.touch_scan_ctrl.touch_scan_pad_map &= ~(disable_mask & TOUCH_... | 781 |
touch_ctrl2.touch_reset = 0;
RTCCNTL.touch_ctrl2.touch_reset = 1;
RTCCNTL.touch_ctrl2.touch_reset = 0; // Should be set 0.
}
/**
*/
static inline void touch_ll_set_idle_channel_connect(touch_pad_conn_type_t type)
{
RTCCNTL.touch_scan_ctrl.touch_inactive_connection = type;
}
/**
*/
static inline void ... | 781 |
rtc_touch_inactive_w1ts = 1;
}
if (int_mask & TOUCH_PAD_INTR_MASK_SCAN_DONE) {
RTCCNTL.int_ena_w1ts.rtc_touch_scan_done_w1ts = 1;
}
if (int_mask & TOUCH_PAD_INTR_MASK_TIMEOUT) {
RTCCNTL.int_ena_w1ts.rtc_touch_timeout_w1ts = 1;
}
if (int_mask & TOUCH_PAD_INTR_MASK_PROXI_MEAS_DONE)... | 781 |
rtc_touch_timeout_w1tc = 1;
}
if (int_mask & TOUCH_PAD_INTR_MASK_PROXI_MEAS_DONE) {
RTCCNTL.int_ena_w1tc.rtc_touch_approach_loop_done_w1tc = 1;
}
}
/**
*/
static inline void touch_ll_intr_clear(touch_pad_intr_mask_t int_mask)
{
if (int_mask & TOUCH_PAD_INTR_MASK_DONE) {
RTCCNTL.int_clr... | 781 |
touch_timeout_ctrl.touch_timeout_en = 1;
}
/**
*/
static inline void touch_ll_timeout_disable(void)
{
RTCCNTL.touch_timeout_ctrl.touch_timeout_en = 0;
}
/**
*/
static inline void touch_ll_timeout_set_threshold(uint32_t threshold)
{
RTCCNTL.touch_timeout_ctrl.touch_timeout_num = threshold;
}
/**
*/
static ... | 781 |
*/
if (touch_num == TOUCH_PAD_MAX) {
SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_ALL;
} else {
SENS.sar_touch_chn_st.touch_channel_clr = (1U << touch_num);
}
}
/**
*/
static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
{
RTCCNTL.touch_fil... | 781 |
touch_filter_ctrl.touch_debounce;
}
/**
*/
static inline void touch_ll_filter_set_noise_thres(uint32_t noise_thr)
{
RTCCNTL.touch_filter_ctrl.touch_noise_thres = noise_thr;
RTCCNTL.touch_filter_ctrl.config2 = noise_thr;
RTCCNTL.touch_filter_ctrl.config1 = 0xF;
RTCCNTL.touch_filter_ctrl.config3 = 2;
}
... | 781 |
touch_scan_ctrl.touch_denoise_en = 1;
}
/**
*/
static inline void touch_ll_denoise_disable(void)
{
RTCCNTL.touch_scan_ctrl.touch_denoise_en = 0;
}
/**
*/
static inline void touch_ll_denoise_set_cap_level(touch_pad_denoise_cap_t cap_level)
{
RTCCNTL.touch_ctrl2.touch_refc = cap_level;
}
/**
*/
static inlin... | 781 |
touch_scan_ctrl.touch_out_ring = pad_num;
}
/**
*/
static inline void touch_ll_waterproof_get_guard_pad(touch_pad_t *pad_num)
{
*pad_num = (touch_pad_t)(RTCCNTL.touch_scan_ctrl.touch_out_ring);
}
/**
*/
static inline void touch_ll_waterproof_set_sheild_driver(touch_pad_shield_driver_t driver_level)
{
RTCCNT... | 781 |
touch_approach_pad1 = prox_pad[1];
SENS.sar_touch_conf.touch_approach_pad2 = prox_pad[2];
}
/**
*/
static inline void touch_ll_proximity_get_channel_num(touch_pad_t prox_pad[])
{
prox_pad[0] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad0);
prox_pad[1] = (touch_pad_t)(SENS.sar_touch_conf.touch_app... | 781 |
sar_touch_conf.touch_approach_pad1 == touch_num) {
*cnt = SENS.sar_touch_appr_status.touch_approach_pad1_cnt;
} else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) {
*cnt = SENS.sar_touch_appr_status.touch_approach_pad2_cnt;
}
}
/**
*/
static inline bool touch_ll_proximity_pad_check... | 781 |
touch_slp_thres.touch_slp_th = touch_thres;
}
/**
*/
static inline void touch_ll_sleep_get_threshold(uint32_t *touch_thres)
{
*touch_thres = RTCCNTL.touch_slp_thres.touch_slp_th;
}
/**
*/
static inline void touch_ll_sleep_enable_approach(void)
{
RTCCNTL.touch_slp_thres.touch_slp_approach_en = 1;
}
/**
*/
... | 781 |
touch_slp_thres.touch_slp_pad;
SENS.sar_touch_conf.touch_data_sel = TOUCH_LL_READ_RAW;
*raw_data = SENS.sar_touch_status[touch_num - 1].touch_pad_data;
}
static inline void touch_ll_sleep_reset_benchmark(void)
{
RTCCNTL.touch_approach.touch_slp_channel_clr = 1;
}
/**
*/
static inline void touch_ll_sleep_... | 781 |
/*
*/
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/regi2c_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void regi2c_ctrl_ll_i2c_reset(void)
{
SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
}
/**
*/
static inline void regi2c_ctrl_ll_i... | 782 |
/*
*/
#pragma once
#include
#include
#include
#include "soc/hwcrypto_reg.h"
#include "soc/soc_caps.h"
#include "soc/system_struct.h"
#include "hal/ds_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void ds_ll_enable_bus_clock(bool enable)
{
SYSTEM.perip_clk_en1.crypto_ds_clk_en = enab... | 783 |
true : false;
}
/**
*/
static inline void ds_ll_wait_busy(void)
{
while (ds_ll_busy());
}
/**
*/
static inline ds_key_check_t ds_ll_key_error_source(void)
{
uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG);
if (key_error == 0) {
return DS_NO_KEY_INPUT;
} else {
return DS_OTHER_... | 783 |
len);
from += frags[i].len;
}
}
/**
*/
static inline void ds_ll_start_sign(void)
{
REG_WRITE(DS_SET_ME_REG, 1);
}
/**
*/
static inline ds_signature_check_t ds_ll_check_signature(void)
{
uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
switch (result) {
case 0:
return DS_SIGNATURE_... | 783 |
/*
*/
#pragma once
#include
#include "soc/hwcrypto_reg.h"
#include "hal/sha_types.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void sha_ll_start_block(esp_sha_type sha_type)
{
REG_WRITE(SHA_MODE_REG, sha_type);
REG_WRITE(SHA_START_REG, 1);
}
/**
*/
static in... | 784 |
/*
*/
// The LL layer for MMU register operations
#pragma once
#include "esp_types.h"
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
{
retu... | 785 |
SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | SOC_MMU_VALID;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
{
(void)mmu_id;
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NU... | 785 |
false : true;
}
/**
*/
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
{
(void)mmu_id;
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
bool target_code = (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_TYPE;
return (target_code == SOC_MMU_ACCESS_FLASH) ? M... | 785 |
/*
*/
/
/
#pragma once
#include
#include "soc/rtc_io_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_periph.h"
#include "soc/io_mux_reg.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RTCIO_LL_PIN_FUNC 0
typedef enum {
... | 786 |
pullup) {
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup);
}
}
/**
*/
static inline void rtcio_ll_pullup_disable(int rtcio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to ... | 786 |
reg, rtc_io_desc[rtcio_num].pulldown);
}
}
/**
*/
static inline void rtcio_ll_pulldown_disable(int rtcio_num)
{
if (rtc_io_desc[rtcio_num].pulldown) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pulldown);
}
}
/**
*/
static inline void rtcio_ll_force_hold_enable(int rt... | 786 |
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