text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
wakeup_enable = 1;
RTCIO.pin[rtcio_num].int_type = type;
}
/**
*/
static inline void rtcio_ll_wakeup_disable(int rtcio_num)
{
RTCIO.pin[rtcio_num].wakeup_enable = 0;
RTCIO.pin[rtcio_num].int_type = RTCIO_LL_WAKEUP_DISABLE;
}
/**
*/
static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num)
{
... | 786 |
reg, rtc_io_desc[rtcio_num].slpsel);
}
/**
*/
static inline void rtcio_ll_disable_sleep_setting(int rtcio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpsel);
}
/**
*/
static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level)
{
REG_SET_FIELD(RTC_IO_EXT_WAKEU... | 786 |
/*
*/
// The LL layer for I2S register operations
/
/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/system_struct.h"
#include "hal/i2s_types.h"
#include "hal/hal_utils.h"
#ifdef __cplusplus
extern "C" {
#endif
#define I... | 787 |
perip_clk_en0.i2s0_clk_en = enable;
} else if (i2s_id == 1) {
SYSTEM.perip_clk_en0.i2s1_clk_en = enable;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define i2s_ll_e... | 787 |
clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define i2s_ll_enable_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; i2s_ll_enable_core_clock(__VA_ARGS__)
/**
*/
stati... | 787 |
tx_slave_mod = slave_en;
}
/**
*/
static inline void i2s_ll_rx_set_slave_mod(i2s_dev_t *hw, bool slave_en)
{
hw->rx_conf.rx_slave_mod = slave_en;
}
/**
*/
static inline void i2s_ll_tx_reset(i2s_dev_t *hw)
{
hw->tx_conf.tx_reset = 1;
hw->tx_conf.tx_reset = 0;
}
/**
*/
static inline void i2s_ll_rx_reset... | 787 |
tx_clk_sel = 3;
break;
default:
HAL_ASSERT(false && "unsupported clock source");
break;
}
}
/**
*/
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
switch (src)
{
case I2S_CLK_SRC_XTAL:
hw->rx_clkm_conf.rx_clk_sel = 0;
break;
... | 787 |
tx_clkm_div_x = x;
div.tx_clkm_div_y = y;
div.tx_clkm_div_z = z;
div.tx_clkm_div_yn1 = yn1;
hw->tx_clkm_div_conf.val = div.val;
}
/**
*/
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{
/* Set the integer part of mclk... | 787 |
mclk_div->denominator - mclk_div->numerator : mclk_div->numerator;
div_x = mclk_div->denominator / div_z - 1;
div_y = mclk_div->denominator % div_z;
}
i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integer, div_x, div_y, div_z, div_yn1);
}
/**
*/
static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_... | 787 |
tx_update = 1;
while (hw->tx_conf.tx_update);
hw->tx_conf.tx_start = 1;
}
/**
*/
static inline void i2s_ll_rx_start(i2s_dev_t *hw)
{
// Have to update registers before start
hw->rx_conf.rx_update = 1;
while (hw->rx_conf.rx_update);
hw->rx_conf.rx_start = 1;
}
/**
*/
static inline void i2s_ll... | 787 |
tx_tdm_chan_bits = chan_bit - 1;
}
/**
*/
static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit)
{
hw->rx_conf1.rx_bits_mod = data_bit - 1;
hw->rx_conf1.rx_tdm_chan_bits = chan_bit - 1;
}
/**
*/
static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_samp... | 787 |
rx_tdm_tot_chan_num = total_num - 1;
}
/**
*/
static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
{
uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
tdm_ctrl &= 0xFFFF0000;
tdm_ctrl |= chan_mask;
hw->tx_tdm_ctrl.val = tdm_ctrl;
}
/**
*/
static inline void i2s_ll_rx_set_activ... | 787 |
rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
case I2S_STD_SLOT_RIGHT:
chan_mask |= 0x02;
break;
case I2S_STD_SLOT_BOTH:
chan_mask |= 0x03;
... | 787 |
pcm2pdm_conv_en = false;
}
/**
*/
static inline void i2s_ll_rx_enable_tdm(i2s_dev_t *hw)
{
hw->rx_conf.rx_pdm_en = false;
hw->rx_conf.rx_tdm_en = true;
hw->rx_conf.rx_pdm2pcm_en = false;
}
/**
*/
static inline void i2s_ll_tx_enable_std(i2s_dev_t *hw)
{
i2s_ll_tx_enable_tdm(hw);
}
/**
*/
static inl... | 787 |
tx_pdm_fp = fp;
hw->tx_pcm2pdm_conf1.tx_pdm_fs = fs;
}
/**
*/
static inline uint32_t i2s_ll_tx_get_pdm_fp(i2s_dev_t *hw)
{
return hw->tx_pcm2pdm_conf1.tx_pdm_fp;
}
/**
*/
static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw)
{
return hw->tx_pcm2pdm_conf1.tx_pdm_fs;
}
/**
*/
static inline void i2s... | 787 |
tx_sigmadelta_in_shift = sig_scale;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_hp_filter_param0(i2s_dev_t *hw, uint32_t param)
{
hw->tx_pcm2pdm_conf1.tx_iir_hp_mult12_0 = param;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_hp_filter_param5(i2s_dev_t *hw, uint32_t param)
{
hw->tx_pcm2pdm_conf1.tx_iir_hp_... | 787 |
rx_pdm_sinc_dsr_16_en;
}
/**
*/
static inline void i2s_ll_tx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg)
{
hw->tx_conf.tx_pcm_conf = pcm_cfg;
hw->tx_conf.tx_pcm_bypass = !pcm_cfg;
}
/**
*/
static inline void i2s_ll_rx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg)
{
hw->rx_conf.rx_p... | 787 |
rx_bit_order = lsb_order_ena;
}
/**
*/
static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
{
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
*/
static inline void i2s_ll_set_single_data(i2s_dev_t *hw, uint32_t data)
{
hw->conf_single_data = data;
}
/**
*/
static inline... | 787 |
tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 1 : 2;
} else {
hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 4 : 3;
}
} else {
hw->tx_conf.tx_chan_mod = 0;
}
}
/**
*/
static inline void i2s_ll_tx_pdm_line_mode(i2s_dev_t *hw, i2s_pdm_tx_line_mode_t line_mode)
{
hw->tx... | 787 |
/*
*/
/
/
// The LL for temperature sensor
#pragma once
#include
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
#include "soc/apb_saradc_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/sens_struct.h"
#include "hal/temperature_sensor_types.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C"... | 788 |
..) do {(void)__DECLARE_RCC_ATOMIC_ENV; temperature_sensor_ll_bus_clk_enable(__VA_ARGS__);} while(0)
/**
*/
static inline void temperature_sensor_ll_reset_module(void)
{
SENS.sar_peri_reset_conf.tsens_reset = 1;
SENS.sar_peri_reset_conf.tsens_reset = 0;
}
/// use a macro to wrap the function, force the calle... | 788 |
tsens_dump_out = 1;
while (!SENS.sar_tctrl.tsens_ready) {
}
SENS.sar_tctrl.tsens_dump_out = 0;
return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_tctrl, tsens_out);
}
/**
*/
static inline uint32_t temperature_sensor_ll_get_offset(void)
{
return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC);
}
/**... | 788 |
/*
*/
// The LL layer for LEDC register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include "hal/ledc_types.h"
#include "soc/ledc_periph.h"
#include "soc/ledc_struct.h"
#include "soc/system_struct.h"
#include "hal/assert.h"
#ifdef __cplusplus
exte... | 789 |
timer[timer_sel].conf.low_speed_update = 1;
}
/**
*/
static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
{
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1;
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0;
}
/**
*/
static inline void ledc_l... | 789 |
timer[timer_sel].conf.clock_divider;
}
/**
*/
static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src)
{
*clk_src = LEDC_APB_CLK;
}
/**
*/
static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer... | 789 |
channel[channel_num].hpoint.hpoint = hpoint_val;
}
/**
*/
static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val)
{
*hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint;
}
/**
*/
static inline void ledc_ll_set_duty... | 789 |
conf1.duty_num = duty_num;
}
/**
*/
static inline void ledc_ll_set_duty_cycle(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_cycle)
{
hw->channel_group[speed_mode].channel[channel_num].conf1.duty_cycle = duty_cycle;
}
/**
*/
static inline void ledc_ll_set_duty_scale(ledc_dev_t... | 789 |
conf1.val = conf1_reg.val;
}
/**
*/
__attribute__((always_inline))
static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool sig_out_en)
{
hw->channel_group[speed_mode].channel[channel_num].conf0.sig_out_en = sig_out_en;
}
/**
*/
static inline void ledc_l... | 789 |
val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num))));
}
/**
*/
static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_status)
{
uint32_t value = hw->int_st.val;
uint32_t int_en_base = LEDC_DUTY_CHN... | 789 |
channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus
}
#endif
| 789 |
/*
*/
#pragma once
#include
#include
#include "soc/systimer_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/system_struct.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions even no... | 790 |
..) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void systimer_ll_reset_register(void)
{
SYSTEM.perip_rst_en0.systimer_rst = 1;
SYSTEM.perip_rst_en0.systimer_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
... | 790 |
hi.timer_unit_load_hi = value >> 32;
dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
}
__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
{
return dev->unit_val[counter_id].lo.timer_unit_value_lo;
}
__att... | 790 |
hi.timer_target_hi) target_val[alarm_id].lo.timer_target_lo;
}
__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
{
dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
}
__attribute__((always_inline)) static i... | 790 |
target_period;
}
__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
{
dev->comp_load[alarm_id].val = 0x01;
}
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
{
if (en... | 790 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "xt_instr_macros.h"
#include "xtensa/config/specreg.h"
#include "xtensa/config/extreg.h"
#include "esp_bit_defs.h"
#include "esp_attr.h"
#include "xtensa/config/core.h"
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inl... | 791 |
/*
*/
// The LL layer for Cache register operations
#pragma once
#include
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32s3/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK ... | 792 |
Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
if (cache_id == 0) {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0);
} else {
... | 792 |
Use `cache_ll_l1_get_bus()` to get your bus first
uint32_t ibus_mask = REG_READ(EXTMEM_ICACHE_CTRL1_REG);
if (cache_id == 0) {
mask = (cache_bus_mask_t)(mask | ((!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_IBUS0 : 0));
} else {
mask = (cache_bus_mask_t)(mask | ((!(ibus_mask & ... | 792 |
EXTMEM_ICACHE_SHUT_CORE0_BUS : 0);
} else {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0);
}
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
if (cache_id == 1) {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXT... | 792 |
/*
*/
#include
#include "soc/soc_caps.h"
#include "xt_instr_macros.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
{
// vpn - id
// 0x00000000 = 0
// 0x20000000 = 1
// 0x40000000 = 2
// 0x60000000 = 3
// 0x80000000 = 4
// 0xa0000000 = 5
... | 793 |
/*
*/
/
/
#pragma once
#include
#include
#include "esp_bit_defs.h"
#include "hal/assert.h"
#include "soc/clk_tree_defs.h"
#include "soc/sdmmc_struct.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SDMMC_LL_GET_HW(id) (((id) == 0) ? (&SDMMC) : NULL)
/**
*/
#define SDMMC_LL_S... | 794 |
perip_rst_en1.sdio_host_rst = 1;
SYSTEM.perip_rst_en1.sdio_host_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sdmmc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMI... | 794 |
val = 0;
}
/**
*/
static inline uint32_t sdmmc_ll_get_clock_div(sdmmc_dev_t *hw)
{
return hw->clock.div_factor_l + 1;
}
/**
*/
static inline void sdmmc_ll_init_phase_delay(sdmmc_dev_t *hw)
{
hw->clock.phase_core = 0;
/* 90 deg. delay for cclk_out to satisfy large hold time for SDR12 (up to 25MHz) and SD... | 794 |
cclk_enable |= BIT(slot);
} else {
hw->clkena.cclk_enable &= ~BIT(slot);
}
}
/**
*/
static inline void sdmmc_ll_set_card_clock_div(sdmmc_dev_t *hw, uint32_t slot, uint32_t card_div)
{
if (slot == 0) {
hw->clksrc.card0 = 0;
hw->clkdiv.div0 = card_div;
} else if (slot == 1) {
... | 794 |
cclk_low_power &= ~BIT(slot);
}
}
/**
*/
static inline void sdmmc_ll_set_data_timeout(sdmmc_dev_t *hw, uint32_t timeout_cycles)
{
if (timeout_cycles > 0xffffff) {
timeout_cycles = 0xffffff;
}
hw->tmout.data = timeout_cycles;
}
/**
*/
static inline void sdmmc_ll_set_response_timeout(sdmmc_de... | 794 |
dma_enable = en;
hw->ctrl.use_internal_dma = en;
hw->bmod.enable = en;
hw->bmod.fb = en;
}
/**
*/
static inline void sdmmc_ll_poll_demand(sdmmc_dev_t *hw)
{
hw->pldmnd = 1;
}
/**
*/
static inline uint32_t sdmmc_ll_get_intr_status(sdmmc_dev_t *hw)
{
return hw->mintsts.val;
}
/**
*/
static inlin... | 794 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include "gpspi_flash_ll.h"
#include "spimem_flash_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
... | 795 |
/*
*/
/
/
// The HAL layer for touch sensor (ESP32-S3 specific part)
#pragma once
#include "hal/touch_sensor_ll.h"
#include "hal/touch_sensor_types.h"
#include_next "hal/touch_sensor_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define touch_hal_reset() touch_ll_reset()
/**
*/
#define touch_hal_set_... | 796 |
/*
*/
#pragma once
#include
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/system_struct.h"
#include "soc/usb_wrap_struct.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_... | 797 |
phy_sel = 0;
// Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
hw->conf0.pad_pull_override = 0;
// Enable USB D+ pullup
hw->conf0.dp_pullup = 1;
// Enable USB pad function
hw->conf0.usb_pad_enable = 1;
// phy_sel is controlled by the following register value
... | 797 |
val = hw->otg_conf.val;
conf.pad_pull_override = 1;
conf.dp_pullup = dp_pu;
conf.dp_pulldown = dp_pd;
conf.dm_pullup = dm_pu;
conf.dm_pulldown = dm_pd;
hw->otg_conf.val = conf.val;
}
/**
*/
static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
{
hw->otg_... | 797 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)
/**
*/
FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void)
{
SYSTEM.perip_rst_en0.usb_rst = 1;
SYSTEM.perip_rst_en0.usb_rst = 0;
}
// SYSTEM.perip_clk_enx are shared registers, so this function must be... | 797 |
/*
*/
// The LL layer for UHCI register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (N... | 798 |
val = hw->esc_conf0.val;
esc_conf0_reg.seper_char = seper_char->seper_chr;
esc_conf0_reg.seper_esc_char0 = seper_char->sub_chr1;
esc_conf0_reg.seper_esc_char1 = seper_char->sub_chr2;
hw->esc_conf0.val = esc_conf0_reg.val;
hw->escape_conf.tx_c0_esc_en = 1;
hw->escape_conf... | 798 |
seq1 = sub_ctr->xon_chr;
esc_conf2_reg.seq1_char0 = sub_ctr->xon_sub1;
esc_conf2_reg.seq1_char1 = sub_ctr->xon_sub2;
esc_conf3_reg.seq2 = sub_ctr->xoff_chr;
esc_conf3_reg.seq2_char0 = sub_ctr->xoff_sub1;
esc_conf3_reg.seq2_char1 = sub_ctr->xoff_sub2;
escape_conf_reg.tx_11... | 798 |
val = intr_mask;
}
static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
{
return hw->int_st.val;
}
static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
hw->conf0.uart_rx_brk_eof_en = 1;
}
if (eof_mode & UHCI_RX_IDLE_EOF) {
... | 798 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "esp_attr.h"
#include "hal/assert.h"
#include "soc/periph_defs.h"
#include "soc/system_reg.h"
#include "soc/syscon_reg.h"
#include "soc/dport_access.h"
#include "soc/soc_caps.h"
static inline uint32_t periph_ll_get_clk_en_mask(p... | 799 |
return (SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST);
} else {
//Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
return SYSTEM_CRYPTO_AES_RST;
}
case PERIPH_SHA_MODULE:
if (enable == true) {
// Clear r... | 799 |
= 0;
}
static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(SY... | 799 |
/*
*/
#pragma once
#include
#include
#include "soc/adc_periph.h"
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/apb_saradc_struct.h"
#include "soc/sens_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
#include "soc... | 800 |
0), The data is invalid. */
};
uint16_t val;
};
} adc_ll_rtc_output_data_t;
#ifdef _MSC_VER
#pragma pack(pop)
#endif /* _MSC_VER */
/*
Digital controller setting
*/
/**
*/
static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_w... | 800 |
ctrl, sar_clk_div, div);
}
/**
*/
static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num);
}
/**
*/
static inline void adc_ll_digi_convert_limit_enable(bool enable)
{
APB_SARADC.ctrl2.meas_num_limit = enable;
}
/**
... | 800 |
ctrl.sar1_patt_len = patt_len - 1;
} else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl.sar2_patt_len = patt_len - 1;
}
}
/**
*/
static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{
uint32_t tab;
uint8_t index = pattern_index ... | 800 |
sar2_patt_tab = tab; //Write back
}
}
/**
*/
static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{
if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl.sar1_patt_p_clear = 1;
APB_SARADC.ctrl.sar1_patt_p_clear = 0;
} else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl.sar2_p... | 800 |
ctrl2.timer_sel = 1;
APB_SARADC.ctrl2.timer_en = 1;
}
/**
*/
static inline void adc_ll_digi_trigger_disable(void)
{
APB_SARADC.ctrl2.timer_en = 0;
}
/**
*/
static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_... | 800 |
filter_ctrl0.filter_reset = 0;
}
/**
*/
static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_unit_t adc_n, adc_channel_t channel, adc_digi_iir_filter_coeff_t coeff)
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val =... | 800 |
= pri_dig && pri_rtc != pri_pwdet && pri_dig != pri_pwdet) {
APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_priority = pri_rtc;
APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_priority = pri_dig;
APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_priority = pri_pwdet;
}
/* Should select highest priority controll... | 800 |
adc_arb_wifi_force = 0;
} else {
APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0;
APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0;
APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1;
}
}
}
/**
*/
static inline void adc_ll_enable_sleep_controller(void)
{
... | 800 |
*/
if (adc_n == ADC_UNIT_1) {
if (internal_gnd) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
} else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
}
} else { //adc_n == ADC_UNIT_2
if (internal_gnd) {
REGI2C_W... | 800 |
sar_reader1_ctrl, sar1_clk_div, div);
} else { // adc_n == ADC_UNIT_2
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div);
}
}
/**
*/
static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits)
{
//ESP32S3 only supports 12bit, leave here for compat... | 800 |
sar_reader2_ctrl.sar2_data_inv = inv_en; // Enable / Disable ADC data invert
}
}
/**
*/
static inline void adc_ll_rtc_intr_enable(adc_unit_t adc_n)
{
if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_int_en = 1;
RTCCNTL.int_ena.rtc_saradc1 = 1;
} else { // adc_n == ADC_UNIT_2
... | 800 |
sar_atten1 = ( SENS.sar_atten1 & ~(0x3 > (channel * 2)) & 0x3);
} else {
return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3);
}
}
static inline uint32_t adc_ll_adc1_read(void)
{
//On ESP32S3, valid data width is 12-bit
return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff);
}
... | 800 |
/*
*/
/
/
// The LL layer for ESP32-S3 PCNT register operations
#pragma once
#include
#include
#include
#include "soc/pcnt_struct.h"
#include "hal/pcnt_types.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PCNT_LL_GET_HW(num) (((num) == 0) ? (&PCNT) : NULL)
#define PCNT_... | 801 |
conf0.ch0_hctrl_mode_un = high_act;
hw->conf_unit[unit].conf0.ch0_lctrl_mode_un = low_act;
} else {
hw->conf_unit[unit].conf0.ch1_hctrl_mode_un = high_act;
hw->conf_unit[unit].conf0.ch1_lctrl_mode_un = low_act;
}
}
/**
*/
__attribute__((always_inline))
static inline int pcnt_ll_get_cou... | 801 |
val = status;
}
/**
*/
static inline void pcnt_ll_enable_high_limit_event(pcnt_dev_t *hw, uint32_t unit, bool enable)
{
hw->conf_unit[unit].conf0.thr_h_lim_en_un = enable;
}
/**
*/
static inline void pcnt_ll_enable_low_limit_event(pcnt_dev_t *hw, uint32_t unit, bool enable)
{
hw->conf_unit[unit].conf0.thr_l... | 801 |
conf2.val = conf2_reg.val;
}
/**
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_l_lim_un = value;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
*/
static... | 801 |
val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_l_lim_un;
return value;
}
/**
*/
static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres)
{
int16_t value;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thre... | 801 |
conf0.filter_thres_un = filter_val;
}
/**
*/
static inline uint32_t pcnt_ll_get_glitch_filter_thres(pcnt_dev_t *hw, uint32_t unit)
{
return hw->conf_unit[unit].conf0.filter_thres_un;
}
/**
*/
static inline void pcnt_ll_enable_glitch_filter(pcnt_dev_t *hw, uint32_t unit, bool enable)
{
hw->conf_unit[unit].co... | 801 |
pcnt_rst = 1;
SYSTEM.perip_rst_en0.pcnt_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define pcnt_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; pcnt_ll_reset_regi... | 801 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include // For MIN/MAX
#include
#include
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define gpspi_flash_l... | 802 |
val = 0;
dev->ctrl.val = 0;
dev->clk_gate.clk_en = 1;
dev->clk_gate.mst_clk_active = 1;
dev->clk_gate.mst_clk_sel = 1;
dev->dma_conf.val = 0;
dev->dma_conf.tx_seg_trans_clr_en = 1;
dev->dma_conf.rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_seg_trans_en = 0;
}
/**
*/
static inline bool ... | 802 |
update = 1;
while (dev->cmd.update);
dev->cmd.usr = 1;
}
/**
*/
static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev)
{
// Not supported on GPSPI
}
/**
*/
static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
{
dev->ctrl.hold_pol = pol_val;
}
/**
*/
static inline ... | 802 |
val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
case SPI_FLASH_SLOWRD:
... | 802 |
val = *clock_val;
}
/**
*/
static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_miso = bitlen > 0;
if (bitlen) {
dev->ms_dlen.ms_data_bitlen = bitlen - 1;
}
}
/**
*/
static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
{... | 802 |
usr_addr = bitlen ? 1 : 0;
}
/**
*/
static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
// The blank region should be all ones
uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen);
dev->addr = (addr addr = addr;
}
/**
*/
static inline void gpsp... | 802 |
1 : 0);
dev->user1.cs_setup_time = cs_setup_time - 1;
}
/**
*/
static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
{
uint32_t div_parameter;
// See comments of `clock` in `spi_struct.h`
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((... | 802 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#include "esp_attr.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RTC_CNTL_LL_RETENTION_TARGET_CPU (BIT(0))
#define RTC_CNTL_LL_RETENTION_TARGET_TAGMEM (BIT(1))
FORCE_INLINE_AT... | 803 |
cpu: 1, tagmem: 2, cpu + tagmem: 3 */
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | RTC_CNTL_LL_RETENTION_TARGET_TAGMEM));
}
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_icache_tagmem_retent... | 803 |
cpu: 1, tagmem: 2, cpu + tagmem: 3 */
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target & ~RTC_CNTL_LL_RETENTION_TARGET_TAGMEM));
}
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_icache_tagmem_rete... | 803 |
RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST;
REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst);
}
FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
}
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
{
SET_PERI_REG_MASK(RTC_CNTL_TI... | 803 |
/*
*/
/
/
#pragma once
#include
#include "soc/rtc_cntl_struct.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_brownout.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void brownout_ll_enable_flash_power_down(bool enable)
{
RTCCNTL.brown_out.close_flash_ena = enable;
}
/**
*/
static inl... | 804 |
brown_out.int_wait = cycle;
}
/**
*/
static inline void brownout_ll_intr_enable(bool enable)
{
RTCCNTL.int_ena.rtc_brown_out = enable;
}
/**
*/
static inline void brownout_ll_ana_reset_enable(bool enable)
{
RTCCNTL.brown_out.ana_rst_en = enable;
}
/**
*/
__attribute__((always_inline))
static inline void b... | 804 |
/*
*/
/
/
// The LL layer for ESP32-S3 GPIO register operations
#pragma once
#include
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"
#include "soc/usb_serial_jtag_reg.h"
#include "hal/gpio_types.h"
#include "soc/gpio_struct.h"
#ifdef __cplusplus
exter... | 805 |
val) & bit_mask) >> bit_shift;
*od = hw->pin[gpio_num].pad_driver;
*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
*sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
}
/**
*/
static inline ... | 805 |
int_type = intr_type;
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
// On ESP32S3, pcpu_int register represents GPIO0-31 interrupt status on both cores
(void)core_id;
*status = hw->pcpu_int;
}
/**
*/
__attribute... | 805 |
pin[gpio_num].int_ena = GPIO_LL_INTR_ENA; //enable intr
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].int_ena = 0; //disable GPIO intr
}
/**
*/
__attribute__((always_inline))
static inline v... | 805 |
data = (0x1 enable_w1ts = (0x1 enable1_w1ts.data = (0x1 pin[gpio_num].pad_driver = 0;
}
/**
*/
static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].pad_driver = 1;
}
/**
*/
static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num... | 805 |
wakeup_enable = 1;
}
/**
*/
static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 0;
}
/**
*/
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
{
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_nu... | 805 |
GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
}
/**
*/
static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
{
SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
}
/**
*/
sta... | 805 |
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