text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
update.tx_update = 1;
// Timer register is in a different clock domain from Timer hardware logic
// We need to wait for the update to take effect before fetching the count value
while (hw->hw_timer[timer_num].update.tx_update) {
}
}
/**
*/
__attribute__((always_inline))
static inline uint64_t timer_ll... | 822 |
loadlo.tx_load_lo = (uint32_t) load_val;
}
/**
*/
__attribute__((always_inline))
static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
{
return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi hw_timer[timer_num].loadlo.tx_load_lo);
}
/**
*/
__attribute__((always_inline))
stat... | 822 |
clk_en = en;
}
/**
*/
static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
{
return &hw->int_st_timers.val;
}
#ifdef __cplusplus
}
#endif
| 822 |
/*
*/
#pragma once
#include
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/dport_reg.h"
#include "soc/syscon_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h"
#include "soc/regi2c_apll.h"
#include "hal/assert.h"
#include "esp32s2/rom/rtc.h"
#ifdef __... | 823 |
/*
*/
// The LL layer for xtal32k WDT register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "soc/rtc_cntl_periph.h"
#ifdef __cplusplus
extern "C" {
#endif
#define XT_WDT_LL_XTAL32_DEAD_INTR_MASK RTC_CNTL_XTAL32K_DEAD_INT_ST_M
/*... | 824 |
xtal32k_auto_backup = enable;
}
/**
*/
inline void xt_wdt_ll_intr_enable(rtc_cntl_dev_t *hw, bool enable)
{
hw->int_ena.rtc_xtal32k_dead = enable;
}
#ifdef __cplusplus
}
#endif
| 824 |
/*
*/
/
/
#pragma once
#include
#include
#include "hal/misc.h"
#include "soc/dac_periph.h"
#include "hal/dac_types.h"
#include "soc/apb_saradc_struct.h"
#include "soc/sens_struct.h"
#include "soc/rtc_io_struct.h"
#include "soc/apb_saradc_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DAC_LL_CW_PHASE_0 ... | 825 |
sar_dac_ctrl2.dac_cw_en1 = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_cw_en2 = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
}
}
/**
*/
static inline void dac_ll_rtc_reset(vo... | 825 |
sar_dac_ctrl2.dac_cw_en2 = enable;
}
}
/**
*/
static inline void dac_ll_cw_set_freq(uint32_t freq, uint32_t rtc8m_freq)
{
uint32_t sw_freq = (uint32_t)(((uint64_t)freq 0xFFFF) ? 0xFFFF : sw_freq);
}
/**
*/
static inline void dac_ll_cw_set_atten(dac_channel_t channel, dac_cosine_atten_t atten)
{
if (cha... | 825 |
sar_dac_ctrl2, dac_dc1, offset);
} else if (channel == DAC_CHAN_1) {
if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_LL_CW_PHASE_180) {
offset = -offset;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset);
}
}
/*
Digital controller setting
*/
/... | 825 |
apb_dac_alter_mode = is_alternate;
}
/**
*/
static inline void dac_ll_digi_fifo_reset(void)
{
APB_SARADC.apb_dac_ctrl.dac_reset_fifo = 1;
APB_SARADC.apb_dac_ctrl.dac_reset_fifo = 0;
}
/**
*/
static inline void dac_ll_digi_reset(void)
{
APB_SARADC.apb_dac_ctrl.apb_dac_rst = 1;
APB_SARADC.apb_dac_ctrl... | 825 |
/*
*/
/**
*/
#pragma once
#include
#include
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/rmt_struct.h"
#include "soc/system_reg.h"
#include "hal/rmt_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RMT_LL_EVENT_TX_DONE(channel) (1 apb_conf.clk_en = enable; // register clock ... | 826 |
conf1.ref_always_on_chn = 1;
break;
case RMT_CLK_SRC_REF_TICK:
dev->conf_ch[channel].conf1.ref_always_on_chn = 0;
break;
default:
HAL_ASSERT(false && "unsupported RMT clock source");
break;
}
}
/**
*/
static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool... | 826 |
conf1.mem_rd_rst_chn = 1;
dev->conf_ch[channel].conf1.mem_rd_rst_chn = 0;
dev->conf_ch[channel].conf1.apb_mem_rst_chn = 1;
dev->conf_ch[channel].conf1.apb_mem_rst_chn = 0;
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channe... | 826 |
tx_loop_num_chn = count;
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_reset_loop_count(rmt_dev_t *dev, uint32_t channel)
{
dev->chn_tx_lim[channel].loop_count_reset_chn = 1;
dev->chn_tx_lim[channel].loop_count_reset_chn = 0;
}
/**
*/
__attribute__((always_inline))
static inline void ... | 826 |
conf1.idle_out_en_chn = enable;
dev->conf_ch[channel].conf1.idle_out_lv_chn = level;
}
/**
*/
static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->chn_tx_lim[channel].tx_lim_chn = limit;
}
/**
*/
static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *de... | 826 |
conf0.carrier_out_lv_chn = level;
}
/**
*/
static inline void rmt_ll_tx_enable_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.carrier_eff_en_chn = !enable;
}
////////////////////////////////////////RX Channel Specific////////////////////////////////////////////////... | 826 |
conf1.apb_mem_rst_chn = 1;
dev->conf_ch[channel].conf1.apb_mem_rst_chn = 0;
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_en_chn = enable;
}
/**
*/
static inline void rmt_ll_rx_set_mem_blocks(rmt_de... | 826 |
conf1.rx_filter_en_chn = enable;
}
/**
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres_chn, thres);
}
/**
*/
__attribute__((always_inline))
static inlin... | 826 |
carrier_en_chn = enable;
}
/**
*/
static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf0.carrier_out_lv_chn = level;
}
//////////////////////////////////////////Interrupt Specific////////////////////////////////////////////////////////////
/... | 826 |
val & (RMT_LL_EVENT_TX_MASK(channel) | RMT_LL_EVENT_TX_ERROR(channel));
}
/**
*/
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel)
{
return dev->int_raw.val & (RMT_LL_EVENT_RX_MASK(channel) | RMT_LL_EVENT_RX_ERROR(channel));
}
/**
*/
__att... | 826 |
val;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnstatus[channel].val;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
{
uint32_t div = HAL_FORCE_RE... | 826 |
conf0.mem_size_chn;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_size_chn;
}
__attribute__((always_inline))
static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev... | 826 |
mem_force_pd) || !(dev->apb_conf.mem_force_pu);
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.mem_owner_chn;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t... | 826 |
val;
return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8);
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xF000) >> 12;
}
__attribute_... | 826 |
/*
*/
#pragma once
#include
#include
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/ eFuse fields /
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flas... | 827 |
rd_mac_spi_sys_3.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return (EFUSE.rd_mac_spi_sys_3.wafer_version_minor_hi > 16) & 0x7) << 4) + (EFUSE.rd_sys_part1_data4.val & ... | 827 |
conf.op_code = EFUSE_READ_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
}
/ eFuse control functions /
#ifdef __cplusplus
}
#endif
| 827 |
/*
*/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/gpio_sd_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void sdm_ll_enable_clock(gpio_sd_dev_t *hw, bool en)
{
hw->misc.function_clk_en = en;
}
/**
*/
__attribute__((always_inline))
static inline v... | 828 |
/*
*/
#include "soc/dport_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void crosscore_int_ll_clear_interrupt(int core_id)
{
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
}
/**
*/
static inline void crosscore_int_ll_trigger_interrupt(int core_id)
{
D... | 829 |
/*
*/
/
/
// The Lowlevel layer for Touch Sensor
#pragma once
#include
#include
#include "hal/misc.h"
#include "soc/touch_sensor_periph.h"
#include "soc/soc_caps.h"
#include "soc/sens_struct.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_io_struct.h"
#include "hal/touch_sensor_types.h"
#ifdef __cplusplu... | 830 |
touch_scan_ctrl.touch_scan_pad_map \
& TOUCH_PAD_BIT_MASK_ALL;
}
/**
*/
static inline void touch_ll_clear_channel_mask(uint16_t disable_mask)
{
SENS.sar_touch_conf.touch_outen &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
RTCCNTL.touch_scan_ctrl.touch_scan_pad_map &= ~(disable_mask & TOUCH_... | 830 |
touch_ctrl2.touch_reset = 0;
RTCCNTL.touch_ctrl2.touch_reset = 1;
RTCCNTL.touch_ctrl2.touch_reset = 0; // Should be set 0.
}
/**
*/
static inline void touch_ll_set_idle_channel_connect(touch_pad_conn_type_t type)
{
RTCCNTL.touch_scan_ctrl.touch_inactive_connection = type;
}
/**
*/
static inline void ... | 830 |
int_ena.rtc_touch_scan_done = 1;
}
if (int_mask & TOUCH_PAD_INTR_MASK_TIMEOUT) {
RTCCNTL.int_ena.rtc_touch_timeout = 1;
}
}
/**
*/
static inline void touch_ll_intr_disable(touch_pad_intr_mask_t int_mask)
{
if (int_mask & TOUCH_PAD_INTR_MASK_DONE) {
RTCCNTL.int_ena.rtc_touch_done = 0;
... | 830 |
int_clr.rtc_touch_inactive = 1;
}
if (int_mask & TOUCH_PAD_INTR_MASK_SCAN_DONE) {
RTCCNTL.int_clr.rtc_touch_scan_done = 1;
}
if (int_mask & TOUCH_PAD_INTR_MASK_TIMEOUT) {
RTCCNTL.int_clr.rtc_touch_timeout = 1;
}
}
/**
*/
static inline uint32_t touch_ll_read_intr_status_mask(void)
{... | 830 |
touch_timeout_ctrl.touch_timeout_en = 1;
}
/**
*/
static inline void touch_ll_timeout_disable(void)
{
RTCCNTL.touch_timeout_ctrl.touch_timeout_en = 0;
}
/**
*/
static inline void touch_ll_timeout_set_threshold(uint32_t threshold)
{
RTCCNTL.touch_timeout_ctrl.touch_timeout_num = threshold;
}
/**
*/
static ... | 830 |
*/
if (touch_num == TOUCH_PAD_MAX) {
SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_ALL;
} else {
SENS.sar_touch_chn_st.touch_channel_clr = (1U << touch_num);
}
}
/**
*/
static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
{
RTCCNTL.touch_fil... | 830 |
touch_filter_ctrl.touch_debounce;
}
/**
*/
static inline void touch_ll_filter_set_noise_thres(uint32_t noise_thr)
{
RTCCNTL.touch_filter_ctrl.touch_noise_thres = noise_thr;
RTCCNTL.touch_filter_ctrl.config2 = noise_thr;
RTCCNTL.touch_filter_ctrl.config1 = 0xF;
RTCCNTL.touch_filter_ctrl.config3 = 2;
}
... | 830 |
touch_scan_ctrl.touch_denoise_en = 1;
}
/**
*/
static inline void touch_ll_denoise_disable(void)
{
RTCCNTL.touch_scan_ctrl.touch_denoise_en = 0;
}
/**
*/
static inline void touch_ll_denoise_set_cap_level(touch_pad_denoise_cap_t cap_level)
{
RTCCNTL.touch_ctrl2.touch_refc = cap_level;
}
/**
*/
static inlin... | 830 |
touch_scan_ctrl.touch_out_ring = pad_num;
}
/**
*/
static inline void touch_ll_waterproof_get_guard_pad(touch_pad_t *pad_num)
{
*pad_num = (touch_pad_t)(RTCCNTL.touch_scan_ctrl.touch_out_ring);
}
/**
*/
static inline void touch_ll_waterproof_set_sheild_driver(touch_pad_shield_driver_t driver_level)
{
RTCCNT... | 830 |
touch_approach_pad1 = prox_pad[1];
SENS.sar_touch_conf.touch_approach_pad2 = prox_pad[2];
}
/**
*/
static inline void touch_ll_proximity_get_channel_num(touch_pad_t prox_pad[])
{
prox_pad[0] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad0);
prox_pad[1] = (touch_pad_t)(SENS.sar_touch_conf.touch_app... | 830 |
sar_touch_conf.touch_approach_pad1 == touch_num) {
*cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad1_cnt);
} else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) {
*cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad2_cnt);
... | 830 |
touch_slp_thres.touch_slp_th = touch_thres;
}
/**
*/
static inline void touch_ll_sleep_get_threshold(uint32_t *touch_thres)
{
*touch_thres = RTCCNTL.touch_slp_thres.touch_slp_th;
}
/**
*/
static inline void touch_ll_sleep_enable_approach(void)
{
RTCCNTL.touch_slp_thres.touch_slp_approach_en = 1;
}
/**
*/
... | 830 |
touch_slp_thres.touch_slp_pad;
SENS.sar_touch_conf.touch_data_sel = TOUCH_LL_READ_RAW;
*raw_data = SENS.sar_touch_status[touch_num - 1].touch_pad_data;
}
static inline void touch_ll_sleep_reset_benchmark(void)
{
RTCCNTL.touch_approach.touch_slp_channel_clr = 1;
}
/**
*/
static inline void touch_ll_sleep_... | 830 |
/*
*/
#pragma once
#include
#include "soc/soc.h"
#include "soc/regi2c_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void regi2c_ctrl_ll_i2c_reset(void)
{
SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
}
/**
*/
static inline void regi2c_ctrl_ll_i2c_bbpll_e... | 831 |
/*
*/
#pragma once
#include
#include "soc/hwcrypto_reg.h"
#include "hal/sha_types.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void sha_ll_start_block(esp_sha_type sha_type)
{
REG_WRITE(SHA_MODE_REG, sha_type);
REG_WRITE(SHA_START_REG, 1);
}
/**
*/
static in... | 832 |
/*
*/
// The LL layer for MMU register operations
#pragma once
#include
#include
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
{
return ... | 833 |
= MMU_VADDR_DATA) {
return 0;
}
entry_id -= 0x140;
vaddr_base = 0x3f000000;
} else {
HAL_ASSERT(false);
}
return vaddr_base + (entry_id << 16);
}
#ifdef __cplusplus
}
#endif
| 833 |
/*
*/
/
/
#pragma once
#include
#include "soc/rtc_io_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_periph.h"
#include "soc/sens_struct.h"
#define RTCIO_LL_PIN_FUNC 0
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
RTCIO_LL_FUNC_RTC = 0x0, /*!> rtcio_num) & 0x1;
}
/**
*/
static... | 834 |
pullup) {
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup);
}
}
/**
*/
static inline void rtcio_ll_pullup_disable(int rtcio_num)
{
if (rtc_io_desc[rtcio_num].pullup) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup);
}
}
/**
*/
s... | 834 |
hold_force);
}
/**
*/
static inline void rtcio_ll_force_hold_all(void)
{
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
}
/**
*/
static inline void rtcio_ll_force_unhold_all(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
}
/**
*/
static inline void rtcio_ll_wake... | 834 |
slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpoe);
}
}
/**
*/
static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpie);
}
/**
*/
static inline void rtcio_ll_disable_input_in_sle... | 834 |
/*
*/
/
/
// The LL layer for ESP32-S2 I2S register operations
#pragma once
#include
#include "hal/misc.h"
#include "soc/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/system_reg.h"
#include "soc/dport_access.h"
#include "hal/i2s_types.h"
#include "hal/hal_utils.h"
#ifdef __cplusplus
extern "C" {
#end... | 835 |
check_owner = en;
}
/**
*/
static inline void i2s_ll_dma_enable_auto_write_back(i2s_dev_t *hw, bool en)
{
hw->lc_conf.out_auto_wrback = en;
}
/**
*/
static inline void i2s_ll_dma_enable_eof_on_fifo_empty(i2s_dev_t *hw, bool en)
{
hw->lc_conf.out_eof_mode = en;
}
/**
*/
static inline void i2s_ll_enable_bus... | 835 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; i2s_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void i2s_ll_reset_register(int i2s_id)
{
if (i2s_id == 0) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
} else {... | 835 |
clk_en) {
hw->clkm_conf.clk_en = 0;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define i2s_ll_enable_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; i2s_ll_enable_core_... | 835 |
rx_fifo_mod_force_en = enable;
}
/**
*/
static inline void i2s_ll_tx_set_slave_mod(i2s_dev_t *hw, bool slave_en)
{
hw->conf.tx_slave_mod = slave_en;
}
/**
*/
static inline void i2s_ll_rx_set_slave_mod(i2s_dev_t *hw, bool slave_en)
{
hw->conf.rx_slave_mod = slave_en;
}
/**
*/
static inline void i2s_ll_tx_r... | 835 |
clk_sel = (src == I2S_CLK_SRC_APLL) ? 1 : 2;
}
/**
*/
static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
{
hw->sample_rate_conf.tx_bck_div_num = val;
}
/**
*/
static inline void i2s_ll_set_raw_mclk_div(i2s_dev_t *hw, uint32_t mclk_div, uint32_t a, uint32_t b)
{
HAL_FORCE_MODIFY_U32_RE... | 835 |
val;
if (en) {
int_ena_mask |= mask;
} else {
int_ena_mask &= ~mask;
}
hw->int_ena.val = int_ena_mask;
}
/**
*/
static inline void i2s_ll_tx_enable_intr(i2s_dev_t *hw)
{
hw->int_ena.out_eof = 1;
}
/**
*/
static inline void i2s_ll_tx_disable_intr(i2s_dev_t *hw)
{
hw->int_ena.o... | 835 |
val = clr_mask;
}
/**
*/
static inline void i2s_ll_tx_reset_dma(i2s_dev_t *hw)
{
hw->lc_conf.out_rst = 1;
hw->lc_conf.out_rst = 0;
}
/**
*/
static inline void i2s_ll_rx_reset_dma(i2s_dev_t *hw)
{
hw->lc_conf.in_rst = 1;
hw->lc_conf.in_rst = 0;
}
/**
*/
static inline void i2s_ll_tx_enable_std(i2s_d... | 835 |
rx_start = 1;
}
/**
*/
static inline void i2s_ll_tx_start_link(i2s_dev_t *hw, uint32_t link_addr)
{
i2s_ll_set_out_link_addr(hw, link_addr);
i2s_ll_start_out_link(hw);
}
/**
*/
static inline void i2s_ll_rx_start_link(i2s_dev_t *hw, uint32_t link_addr)
{
hw->in_link.addr = link_addr;
hw->in_link.star... | 835 |
tx_fifo_mod = (chan_bit sample_rate_conf.tx_bits_mod = data_bit;
}
/**
*/
static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit)
{
hw->fifo_conf.rx_fifo_mod = (chan_bit sample_rate_conf.rx_bits_mod = data_bit;
}
/**
*/
static inline void i2s_ll_enable_dma(i2s_dev_t *hw, bool ... | 835 |
tx_short_sync = 1;
hw->conf.tx_msb_shift = 0;
}
/**
*/
static inline void i2s_ll_rx_set_pcm_short(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 1;
hw->conf.rx_msb_shift = 0;
}
/**
*/
static inline void i2s_ll_tx_set_pcm_long(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 0;
}
... | 835 |
tx_chan_mod = 3;
break;
case I2S_STD_SLOT_LEFT:
hw->conf_chan.tx_chan_mod = 4;
break;
case I2S_STD_SLOT_BOTH:
hw->conf_chan.tx_chan_mod = 1; // 1 & 2 has same effect
break;
default:
break;
}
} else {
swit... | 835 |
2 : 1;
break;
case I2S_STD_SLOT_BOTH:
hw->conf_chan.rx_chan_mod = 0;
break;
default:
break;
}
}
/**
*/
static inline void i2s_ll_tx_set_bits_mod(i2s_dev_t *hw, uint32_t val)
{
hw->sample_rate_conf.tx_bits_mod = val;
}
/**
*/
static inline void i2s_ll_tx_enable_dma_eq... | 835 |
lcd_en = enable;
}
/**
*/
static inline void i2s_ll_tx_stop_on_fifo_empty(i2s_dev_t *hw, bool en)
{
hw->conf1.tx_stop_en = en;
}
/**
*/
static inline void i2s_ll_tx_bypass_pcm(i2s_dev_t *hw, bool bypass)
{
hw->conf1.tx_pcm_bypass = bypass;
}
#ifdef __cplusplus
}
#endif
| 835 |
/*
*/
/
/
// The LL for temperature sensor
#pragma once
#include
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
#include "soc/apb_saradc_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/sens_struct.h"
#include "hal/temperature_sensor_types.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C"... | 836 |
..) do {(void)__DECLARE_RCC_ATOMIC_ENV; temperature_sensor_ll_bus_clk_enable(__VA_ARGS__);} while(0)
/**
*/
static inline void temperature_sensor_ll_reset_module(void)
{
SENS.sar_tctrl2.tsens_reset = 1;
SENS.sar_tctrl2.tsens_reset = 0;
}
/// use a macro to wrap the function, force the caller to use it in a c... | 836 |
SENS.sar_tctrl.tsens_ready) {
}
SENS.sar_tctrl.tsens_dump_out = 0;
return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_tctrl, tsens_out);
}
/**
*/
static inline uint32_t temperature_sensor_ll_get_offset(void)
{
return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC);
}
/**
*/
static inline uint32_t temp... | 836 |
/*
*/
// The LL layer for LEDC register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include "hal/ledc_types.h"
#include "soc/ledc_periph.h"
#include "soc/ledc_struct.h"
#include "soc/dport_reg.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "... | 837 |
timer[timer_sel].conf.low_speed_update = 1;
}
/**
*/
static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
{
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1;
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0;
}
/**
*/
static inline void ledc_l... | 837 |
timer[timer_sel].conf.clock_divider;
}
/**
*/
static inline void ledc_ll_set_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t clk_src)
{
if (clk_src == LEDC_REF_TICK) {
hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 1;
} else {
hw->timer... | 837 |
timer[timer_sel].conf.duty_resolution;
}
/**
*/
static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *max_duty)
{
*max_duty = (1 channel_group[speed_mode].channel[channel_num].conf0.low_speed_update = 1;
}
/**
*/
static inline void ledc_ll_set_hpoint(l... | 837 |
channel[channel_num].conf1.duty_inc = duty_direction;
}
/**
*/
static inline void ledc_ll_set_duty_num(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_num)
{
hw->channel_group[speed_mode].channel[channel_num].conf1.duty_num = duty_num;
}
/**
*/
static inline void ledc_ll_set_du... | 837 |
val = hw->channel_group[speed_mode].channel[channel_num].conf1.val;
conf1_reg.duty_inc = dir;
conf1_reg.duty_num = step;
conf1_reg.duty_cycle = cycle;
conf1_reg.duty_scale = scale;
hw->channel_group[speed_mode].channel[channel_num].conf1.val = conf1_reg.val;
}
/**
*/
__attribute__((always_inline))... | 837 |
val;
uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S;
hw->int_ena.val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num))));
}
/**
*/
static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_sta... | 837 |
channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus
}
#endif
| 837 |
/*
*/
#pragma once
#include
#include
#include "soc/systimer_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/system_reg.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions even no gc... | 838 |
timer_value_valid;
}
__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value)
{
(void)counter_id;
dev->load_hi.timer_load_hi = value >> 32;
dev->load_lo.timer_load_lo = value;
}
__attribute__((always_inline)) static inline ui... | 838 |
timer_xtal_step = step;
}
/ Alarm /
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value)
{
dev->target_val[alarm_id].hi.timer_target_hi = value >> 32;
dev->target_val[alarm_id].lo.timer_target_lo = value;
}
__attribute__((alway... | 838 |
target_period_mode = 1;
}
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
{
HAL_ASSERT(period target_conf[alarm_id].target_period = period;
}
__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(s... | 838 |
/*
*/
#pragma once
#include
#include "soc/memprot_defs.h"
#include "soc/dport_access.h"
#include "soc/periph_defs.h"
#include "hal/memprot_types.h"
#include "hal/memprot_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void memprot_ll_peri1_clear_intr(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_PM... | 839 |
DPORT_PMS_PRO_DPORT_7_REG is missing op_type bit
*op_subtype = (uint32_t)status_bits & PERI1_INTR_ST_OP_TYPE_BIT;
}
static inline bool memprot_ll_peri1_is_assoc_intr(void)
{
return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_7_REG, DPORT_PMS_PRO_DPORT_ILG_INTR) > 0;
}
static inline uint32_t memprot_ll_peri1_... | 839 |
PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 : 0;
return (intptr_t)(fault_address | high_bits);
}
static inline bool memprot_ll_peri1_rtcslow_is_intr_mine(void)
{
if (memprot_ll_dram0_is_assoc_intr()) {
uint32_t faulting_address = (uint32_t)memprot_ll_peri1_rtcslow_get_fault_address();
return faulting... | 839 |
1 : 0);
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R, hr ? 1 : 0);
}
static inline void memprot_ll_peri1_rtcslow_set_write_perm(bool lw, bool hw)
{
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W, lw ? 1 : 0);
DPORT_REG_SET_FIELD(DPORT_PMS_P... | 839 |
= 0) {
return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
}
uint32_t reg_split_addr = PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr);
//prepare high & low permission mask
uint32_t permission_mask = 0;
if (lw) {
permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W;
}
if (lr) {
permissi... | 839 |
1 : 0);
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R, hr ? 1 : 0);
}
static inline void memprot_ll_peri2_rtcslow_0_set_write_perm(bool lw, bool hw)
{
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W, lw ? 1 : 0);
DPORT_REG_SET_FIELD(DPORT_PMS_PRO... | 839 |
= 0) {
return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
}
uint32_t reg_split_addr = PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr);
//prepare high & low permission mask
uint32_t permission_mask = 0;
if (lw) {
permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W;
}
if (lr) {
permissi... | 839 |
1 : 0);
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R, hr ? 1 : 0);
}
static inline void memprot_ll_peri2_rtcslow_1_set_write_perm(bool lw, bool hw)
{
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W, lw ? 1 : 0);
DPORT_REG_SET_FIELD(DPORT_PMS_PRO... | 839 |
/*
*/
/
/
// CP DMA HAL usages:
// 1. Initialize HAL layer by cp_dma_hal_init, pass in the allocated descriptors for TX and RX
// 2. Enable DMA and interrupt by cp_dma_hal_start
// 3. Prepare descriptors used for TX and RX
// 4. Restart the DMA engine in case it's not in working
#pragma once
#ifdef __cplusplus
ex... | 840 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
{
uint32_t value = 0;
asm volatile("get_gpio_in %0" : "=r"(value) : :);
return value;
}
__attribute__((always_inline))
static inline uint32_t dedic_... | 841 |
/*
*/
// The LL layer for Cache register operations
#pragma once
#include
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32s2/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#de... | 842 |
CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW) {
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_... | 842 |
CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DROM0_ADDRESS_LOW) {
mask = (cache_bus_m... | 842 |
EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = ... | 842 |
EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
REG_SET_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
dbus_mask = ... | 842 |
/*
*/
#include
#include "soc/soc_caps.h"
#include "xt_instr_macros.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
{
// vpn - id
// 0x00000000 = 0
// 0x20000000 = 1
// 0x40000000 = 2
// 0x60000000 = 3
// 0x80000000 = 4
// 0xa0000000 = 5
... | 843 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include "gpspi_flash_ll.h"
#include "spimem_flash_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
... | 844 |
/*
*/
/
/
// The HAL layer for touch sensor (ESP32-S2 specific part)
#pragma once
#include "hal/touch_sensor_ll.h"
#include "hal/touch_sensor_types.h"
#include_next "hal/touch_sensor_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define touch_hal_reset() touch_ll_reset()
/**
*/
#define touch_hal_set_... | 845 |
/*
*/
#pragma once
#include
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/system_reg.h"
#include "soc/usb_wrap_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
{
hw->otg_conf.phy_sel = 0;
}
/**
*/
static inline void usb... | 846 |
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