text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
val = UINT32_MAX;
hw->int_ena.val = I2C_LL_MASTER_RX_INT;
}
/**
*/
static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT);
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_... | 863 |
scl_high_period = hight_period - 10;
hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.scl_high_period;
}
/**
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*... | 863 |
/*
*/
/**
*/
#pragma once
#include
#include
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/soc_etm_source.h"
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_RX_EVENT_MASK (0x1F)
#define GDMA_LL_TX_EVENT_MASK (0x0F)
#define GDMA_LL_INVALID_PERIPH_ID ... | 864 |
soc_clk_ctrl1.reg_ahb_pdma_sys_clk_en = enable;
} else {
HP_SYS_CLKRST.soc_clk_ctrl1.reg_axi_pdma_sys_clk_en = enable;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#d... | 864 |
/*
*/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/ana_cmpr_struct.h"
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ANALOG_CMPR_LL_GET_HW(unit) (&ANALOG_CMPR[unit])
#define ANALOG_CMPR_LL_GET_UNIT(hw) ((hw) == (&ANALOG_CMPR[0]) ? 0 : 1)... | 865 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#include "hal/efuse_ll.h"
#include_next "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
//TODO: IDF-7512
/**
*/
uint32_t efuse_hal_get_chip_revision(void);
/**
*/
void efuse_hal_set_timing(uint32_t apb_freq_hz);
/**
*/
void efuse_hal_re... | 866 |
/*
*/
#pragma once
#include
#include
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/hal_utils.h"
#include "hal/gdma_types.h"
#include "hal/gdma_ll.h"
#include "soc/ahb_dma_struct.h"
#include "soc/ahb_dma_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#define AHB_DMA_LL_GET_HW(id) (((id) == 0... | 867 |
raw.val;
} else {
return dev->in_intr[channel].st.val;
}
}
/**
*/
static inline void ahb_dma_ll_rx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->in_intr[channel].ena.val |= mask;
} else {
dev->in_intr[channel].ena.val &=... | 867 |
in.in_conf0.in_data_burst_en_chn = enable;
}
/**
*/
static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
{
dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable;
}
/**
*/
__attribute__((always_inline))
static inline void ahb_dma_ll_rx_reset_channel... | 867 |
infifo_cnt_chn;
}
/**
*/
static inline uint32_t ahb_dma_ll_rx_pop_data(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_pop.infifo_pop_chn = 1;
return dev->channel[channel].in.in_pop.infifo_rdata_chn;
}
/**
*/
__attribute__((always_inline))
static inline void ahb_dma_ll_rx_set_desc_addr(a... | 867 |
in.in_link.inlink_auto_ret_chn = enable;
}
/**
*/
static inline bool ahb_dma_ll_rx_is_desc_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel)
{
return dev->channel[channel].in.in_link.inlink_park_chn;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t ahb_dma_ll_rx_get_success_eof_desc_addr(ahb_dma_dev_... | 867 |
in.in_peri_sel.peri_in_sel_chn = periph_id;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
}
/**
*/
static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PER... | 867 |
ena.val |= mask;
} else {
dev->out_intr[channel].ena.val &= ~mask;
}
}
/**
*/
__attribute__((always_inline))
static inline void ahb_dma_ll_tx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->out_intr[channel].clr.val = mask;
}
/**
*/
static inline volatile void ... | 867 |
out.out_conf0.out_eof_mode_chn = mode;
}
/**
*/
static inline void ahb_dma_ll_tx_enable_auto_write_back(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
{
dev->channel[channel].out.out_conf0.out_auto_wrback_chn = enable;
}
/**
*/
__attribute__((always_inline))
static inline void ahb_dma_ll_tx_reset_channel(ah... | 867 |
outfifo_cnt_chn;
}
/**
*/
static inline void ahb_dma_ll_tx_push_data(ahb_dma_dev_t *dev, uint32_t channel, uint32_t data)
{
dev->channel[channel].out.out_push.outfifo_wdata_chn = data;
dev->channel[channel].out.out_push.outfifo_push_chn = 1;
}
/**
*/
__attribute__((always_inline))
static inline void ahb_dma... | 867 |
out.out_link.outlink_park_chn;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t ahb_dma_ll_tx_get_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
{
return dev->channel[channel].out.out_eof_des_addr.val;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t ahb_dma_ll_tx_get_prefetched... | 867 |
out.out_conf0.out_etm_en_chn = enable;
}
///////////////////////////////////// CRC-TX /////////////////////////////////////////
/**
*/
static inline void ahb_dma_ll_tx_crc_clear(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->out_crc[channel].crc_clear.out_crc_clear_chn_reg = 1;
dev->out_crc[channel].crc_clear.... | 867 |
crc_width.tx_crc_latch_flag_chn = 1;
dev->out_crc[channel].crc_width.tx_crc_latch_flag_chn = 0;
}
/**
*/
static inline void ahb_dma_ll_tx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
uint32_t lfsr_mask, uint32_t data_mask, b... | 867 |
crc_clear.in_crc_clear_chn_reg = 1;
dev->in_crc[channel].crc_clear.in_crc_clear_chn_reg = 0;
}
/**
*/
static inline void ahb_dma_ll_rx_crc_set_width(ahb_dma_dev_t *dev, uint32_t channel, uint32_t width)
{
HAL_ASSERT(width in_crc[channel].crc_width.rx_crc_width_chn = (width - 1) / 8;
}
/**
*/
static inline v... | 867 |
crc_en_addr.rx_crc_en_addr_chn = crc_bit;
dev->in_crc[channel].crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask;
dev->in_crc[channel].crc_data_en_addr.rx_crc_data_en_addr_chn = crc_bit;
if (reverse_data_mask) {
// "& 0xff" because the hardware only support 8-bit data
data_mask = hal_utils_bi... | 867 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash Encryption.
#include
#include
#include "soc/hp_system_reg.h"
#include "soc/spi_mem_c_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Choose type of chip you want to encrypt manully
typedef enu... | 868 |
= 0x3) {
}
}
/**
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
REG_SET_BIT(SPI_MEM_C_XTS_DESTROY_REG, SPI_MEM_C_XTS_DESTROY);
}
/**
*/
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
{
return ((address % length) == 0) ? true : false;
}
#ifdef __cplusplus
}
... | 868 |
/*
*/
/**
*/
#pragma once
#include
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
//TODO: IDF-7460
#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_... | 869 |
/*
*/
/
/
#pragma once
#include
#include
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/spi_mem_s_struct.h"
#include "soc/spi_mem_s_reg.h"
#include "soc/spi1_mem_s_reg.h"
#include "soc/spi1_mem_s_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/clk_tree_defs.h"
#include "rom/o... | 870 |
mem_sram_drd_cmd.mem_cache_sram_usr_rd_cmd_bitlen = cmd_bitlen - 1;
SPIMEM2.mem_sram_drd_cmd.mem_cache_sram_usr_rd_cmd_value = cmd_val;
}
/**
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_addr_bitlen(uint32_t mspi_id, uint32_t addr_bitlen)
{
(void)mspi_id;
HAL_ASSERT(addr_bitlen ... | 870 |
mem_cache_sctrl.mem_usr_rd_sram_dummy = 1;
SPIMEM2.mem_cache_sctrl.mem_sram_rdummy_cyclelen = dummy_n - 1;
}
/**
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_variable_dummy(uint32_t mspi_id, bool en)
{
if (mspi_id == PSRAM_CTRLR_LL_MSPI_ID_2) {
SPIMEM2.smem_ddr.smem_var_d... | 870 |
smem_ddr.smem_ddr_wdat_swp = en;
}
/**
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_ddr_rd_data_swap(uint32_t mspi_id, bool en)
{
(void)mspi_id;
SPIMEM2.smem_ddr.smem_ddr_rdat_swp = en;
}
/**
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_oct_line_mo... | 870 |
mem_axi_req_en = en;
SPIMEM2.mem_cache_fctrl.close_axi_inf_en = !en;
}
/**
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_wr_splice(uint32_t mspi_id, bool en)
{
(void)mspi_id;
SPIMEM2.mem_ctrl1.mem_aw_splice_en = en;
}
/**
*/
__attribute__((always_inline))
static inline void ... | 870 |
hp_rst_en0.reg_rst_en_dual_mspi_axi = 1;
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dual_mspi_axi = 0;
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dual_mspi_apb = 1;
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dual_mspi_apb = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the crit... | 870 |
peri_clk_ctrl00.reg_psram_pll_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_psram_clk_src_sel = clk_val;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define psram_ctrlr_ll_select_... | 870 |
smem_ac.smem_cs_setup = 1;
SPIMEM2.smem_ac.smem_cs_setup_time = setup_n - 1;
}
/**
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_cs_hold(uint32_t mspi_id, uint32_t hold_n)
{
(void)mspi_id;
HAL_ASSERT(hold_n > 0);
SPIMEM2.smem_ac.smem_cs_hold = 1;
SPIMEM2.smem_ac.smem_cs_h... | 870 |
smem_ac.smem_ecc_skip_page_corner = en;
}
/**
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_split_trans(uint32_t mspi_id, bool en)
{
(void)mspi_id;
SPIMEM2.smem_ac.smem_split_trans_en = en;
}
/**
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_ecc_addr... | 870 |
smem_ecc_ctrl.smem_page_size;
switch(reg_val) {
case 0:
page_size = 256;
break;
case 1:
page_size = 512;
break;
case 2:
page_size = 1024;
break;
case 3:
page_size = 2048;
break;
default:
HAL_ASSERT(false);
}
return ... | 870 |
smem_pmsn_attr[region_id].smem_pms_wr_attr = 1;
}
if (attr_mask & PSRAM_CTRLR_LL_PMS_ATTR_READABLE) {
SPIMEM2.smem_pmsn_attr[region_id].smem_pms_rd_attr = 1;
}
}
/**
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_pms_region_start_addr(uint32_t mspi_id, uint32_t region_id, ... | 870 |
smem_pmsn_addr[region_id].smem_pms_addr_s;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t psram_ctrlr_ll_get_pms_region_size(uint32_t mspi_id, uint32_t region_id)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
return SPIMEM2.smem_pmsn_size[region_id].smem_pms_size... | 870 |
cmd = cmd,
.cmdBitLen = cmd_bitlen,
.addr = &addr,
.addrBitLen = addr_bitlen,
.txData = (uint32_t *)mosi_data,
.txDataBitLen = mosi_bitlen,
.rxData = (uint32_t *)miso_data,
.rxDataBitLen = miso_bitlen,
.dummyBitLen = dummy_bits,
};
esp_rom_spi_cmd_... | 870 |
/*
*/
#pragma once
#include
#include
#include "esp_attr.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/isp_types.h"
#include "hal/color_types.h"
#include "soc/isp_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ISP_LL_G... | 871 |
isp_in_src = 1;
hw->cntl.mipi_data_en = 0;
break;
case ISP_INPUT_DATA_SOURCE_DWGDMA:
hw->cntl.isp_in_src = 2;
hw->cntl.mipi_data_en = 0;
break;
default:
HAL_ASSERT(false);
}
}
/**
*/
static inline bool isp_ll_set_input_data_color_format(isp_dev_t *hw, color_... | 871 |
hadr_num = pixel_num - 1;
}
/**
*/
static inline void isp_ll_set_intput_data_v_row_num(isp_dev_t *hw, uint32_t row_num)
{
hw->frame_cfg.vadr_num = row_num - 1;
}
/**
*/
static inline bool isp_ll_set_output_data_color_format(isp_dev_t *hw, color_space_pixel_format_t format)
{
bool valid = false;
if (for... | 871 |
isp_out_type = 4;
hw->cntl.demosaic_en = 1;
hw->cntl.rgb2yuv_en = 1;
hw->cntl.yuv2rgb_en = 1;
valid = true;
break;
default:
break;
}
} else if (format.color_space == COLOR_SPACE_YUV) {
switch(format.pixel_format) {
... | 871 |
hsync_end_exist = en;
}
/**
*/
static inline bool isp_ll_is_demosaic_enabled(isp_dev_t *hw)
{
return hw->cntl.demosaic_en;
}
/**
*/
static inline bool isp_ll_is_rgb2yuv_enabled(isp_dev_t *hw)
{
return hw->cntl.rgb2yuv_en;
}
/*
AF
*/
/**
*/
static inline void isp_ll_af_clk_enable(isp_... | 871 |
= 0);
hw->af_threshold.af_threshold = thresh;
}
/**
*/
static inline void isp_ll_af_set_auto_edge_thresh_pixel_num(isp_dev_t *hw, uint32_t pixel_num)
{
HAL_ASSERT(hw->af_threshold.af_threshold == 0);
hw->af_ctrl1.af_thpixnum = pixel_num;
}
/**
*/
static inline void isp_ll_af_set_window_range(isp_dev_t... | 871 |
af_rpoint_c = bottom_right_x;
hw->af_vscale_c.af_bpoint_c = bottom_right_y;
break;
default:
HAL_ASSERT(false);
}
}
/**
*/
static inline uint32_t isp_ll_af_get_window_sum(isp_dev_t *hw, uint32_t window_id)
{
switch (window_id) {
case 0:
return hw->af_sum_a.af_suma;
c... | 871 |
af_env_user_threshold_sum = 0x0;
hw->af_env_user_th_lum.af_env_user_threshold_lum = 0x0;
}
//nothing to do to if using abs mode, it'll be enabled after `isp_ll_af_env_monitor_set_thresh()`
}
/**
*/
static inline void isp_ll_af_env_monitor_set_thresh(isp_dev_t *hw, uint32_t sum_thresh, uint32_t lum_th... | 871 |
bf_en = enable;
}
/*
CCM
*/
/**
*/
static inline void isp_ll_ccm_clk_enable(isp_dev_t *hw, bool enable)
{
hw->clk_en.clk_ccm_force_on = enable;
}
/**
*/
static inline void isp_ll_ccm_enable(isp_dev_t *hw, bool enable)
{
hw->cntl.ccm_en = enable;
}
/*
Color
*/
/**... | 871 |
val;
}
/**
*/
__attribute__((always_inline))
static inline void isp_ll_clear_intr(isp_dev_t *hw, uint32_t mask)
{
hw->int_clr.val = mask;
}
#ifdef __cplusplus
}
#endif
| 871 |
/*
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/parlio_types.h"
#include "hal/hal_utils.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/parl_io_struct.h"
#include "soc/hp_s... | 872 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; parlio_ll_rx_set_clock_div(__VA_ARGS__)
/**
*/
static inline void parlio_ll_rx_reset_clock(parl_io_dev_t *dev)
{
(void)dev;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_parlio_rx = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_parlio_rx = 0;
}
/// use a macro to wrap the function, for... | 872 |
rx_eof_gen_sel = cond;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_start(parl_io_dev_t *dev, bool en)
{
dev->rx_start_cfg.rx_start = en;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_set_recv_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
{
dev->rx_data_cf... | 872 |
rx_smp_mode_sel = 1;
dev->rx_mode_cfg.rx_pulse_submode_sel = submode;
dev->rx_mode_cfg.rx_ext_en_inv = pulse_inv;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_set_soft_recv_mode(parl_io_dev_t *dev)
{
dev->rx_mode_cfg.rx_smp_mode_sel = 2;
}
/**
*/
static inline void parlio_ll_r... | 872 |
rx_bus_wid_sel = width_sel;
}
/**
*/
static inline void parlio_ll_rx_reset_fifo(parl_io_dev_t *dev)
{
dev->fifo_cfg.rx_fifo_srst = 1;
dev->fifo_cfg.rx_fifo_srst = 0;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32_t line_num)
{
dev... | 872 |
rx_reg_update);
}
///////////////////////////////////TX Unit///////////////////////////////////////
/**
*/
static inline void parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_ll_clock_source_t src)
{
(void)dev;
uint32_t clk_sel = 0;
switch (src) {
case PARLIO_LL_CLK_SRC_XTAL:
clk_sel ... | 872 |
peri_clk_ctrl119, reg_parlio_tx_clk_div_denominator, clk_div->denominator);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl119, reg_parlio_tx_clk_div_numerator, clk_div->numerator);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section ne... | 872 |
peri_clk_ctrl118.reg_parlio_tx_clk_en = en;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define parlio_ll_tx_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; parlio_ll_tx_enable_cloc... | 872 |
tx_valid_output_en = en;
}
/**
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
}
/**
*/
static inline void parlio_ll_tx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_o... | 872 |
tx_fifo_srst = 1;
dev->fifo_cfg.tx_fifo_srst = 0;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value)
{
dev->tx_genrl_cfg.tx_idle_value = value;
}
/**
*/
__attribute__((always_inline))
static inline bool parlio_ll_tx_is_ready(parl_i... | 872 |
val = mask;
}
/**
*/
static inline volatile void *parlio_ll_get_interrupt_status_reg(parl_io_dev_t *dev)
{
return &dev->int_st;
}
#ifdef __cplusplus
}
#endif
| 872 |
/*
*/
// The LL layer for RTC(LP) watchdog register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/lpwdt_ll.h"
//TODO: IDF-7539
typedef lp_wdt_dev_t rwdt_dev_t;
#define RWDT_DEV_GET() &LP_WDT
#def... | 873 |
/*
*/
#pragma once
#include
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/hal_utils.h"
#include "hal/mipi_csi_types.h"
#include "hal/mipi_csi_brg_ll.h"
#include "hal/mipi_csi_phy_ll.h"
#include "hal/mipi_csi_host_ll.h"
#include "soc/hp_sys_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#en... | 874 |
hp_rst_en0.reg_rst_en_csi_brg = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define mipi_csi_ll_reset_brg_module_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_csi_ll_reset_brg_mo... | 874 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_csi_ll_set_phy_clock_source(__VA_ARGS__)
/**
*/
static inline void mipi_csi_ll_enable_phy_config_clock(int group_id, bool en)
{
(void)group_id;
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_cfg_clk_en = en;
}
/// use a macro to wrap the function, force the caller to... | 874 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_csi_ll_enable_host_bus_clock(__VA_ARGS__)
/**
*/
static inline void mipi_csi_ll_reset_host_clock(int group_id)
{
(void)group_id;
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_csi_host = 1;
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_csi_host = 0;
}
/// use a macro to wrap the funct... | 874 |
/*
*/
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include "esp_attr.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/uart_types.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc... | 875 |
reg_update = 1;
while (hw->reg_update.reg_update);
}
/ LP_UART Specific /
/**
*/
FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
(void)hw;
switch (LPPERI.core_clk_sel.lp_uart_clk_sel) {
default:
case 0:
*source_clk = (soc_module_clk_t)LP_UART_SCLK... | 875 |
core_clk_sel is a shared register, so this function must be used in an atomic way
#define lp_uart_ll_set_source_clk(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_set_source_clk(__VA_ARGS__)
/**
*/
FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b... | 875 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void lp_uart_ll_reset_register(int hw_id)
{
(void)hw_id;
LPPERI.reset_en.rst_en_lp_uart = 1;
LPPERI.reset_en.rst_en_lp_uart = 0;
}
// LPPERI.reset_en is a shared register, so this function must be used in an... | 875 |
soc_clk_ctrl2.reg_uart1_apb_clk_en;
uart_sys_en = HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart1_sys_clk_en;
break;
case 2:
uart_rst_en = HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart2_apb;
uart_apb_en = HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart2_apb_clk_en;
uart_sys_en = HP_SYS_CLKRST.soc_clk_... | 875 |
uart_rst_en && uart_apb_en && uart_sys_en);
}
/**
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
switch (uart_num) {
case 0:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart0_apb_clk_en = enable;
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart0_sys_clk_en = enable;
break;... | 875 |
soc_clk_ctrlx are shared registers, so this function must be used in an atomic way
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num) {
case 0:
HP_SYS_CLK... | 875 |
hp_rst_en1 is a shared register, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
*/
FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
{
if ((hw) == &UART0) {
HP_SYS_CLKRST.peri_clk_ctrl110.... | 875 |
peri_clk_ctrl110.reg_uart0_clk_en = 0;
} else if ((hw) == &UART1) {
HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart1_clk_en = 0;
} else if ((hw) == &UART2) {
HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart2_clk_en = 0;
} else if ((hw) == &UART3) {
HP_SYS_CLKRST.peri_clk_ctrl113.reg_uart3_clk_en = 0;... | 875 |
peri_clk_ctrl110.reg_uart0_clk_src_sel = sel_value;
} else if ((hw) == &UART1) {
HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart1_clk_src_sel = sel_value;
} else if ((hw) == &UART2) {
HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart2_clk_src_sel = sel_value;
} else if ((hw) == &UART3) {
HP_SYS_CLKRST... | 875 |
reg_uart0_clk_src_sel;
} else if ((hw) == &UART1) {
sel_value = HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart1_clk_src_sel;
} else if ((hw) == &UART2) {
sel_value = HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart2_clk_src_sel;
} else if ((hw) == &UART3) {
sel_value = HP_SYS_CLKRST.peri_clk_ctrl113... | 875 |
clkdiv = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
//needs force u32 write
if ((hw) == &UART0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl111, reg_uart0_sclk_div_num, sclk_div - 1);
} else if ((hw) == &UART1) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRS... | 875 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_baudrate(__VA_ARGS__)
#endif
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
{
typeof(hw->clkdiv_sync) div_reg;
div_reg.val = hw->clkdiv_sync.val;
int sclk_div = 0;
if ((hw) == &UART0) {
sclk_div = HAL_F... | 875 |
val = hw->int_ena.val | mask;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val = hw->int_ena.val & (~mask);
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
{
return hw->int_raw.val;
}
/**
*/
FORCE_INLINE_ATTR uint32_t ua... | 875 |
// Therefore, use 32-bit access to avoid any potential problem.
for (int i = 0; i fifo.val = (int)buf[i];
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
{
hw->conf0_sync.rxfifo_rst = 1;
uart_ll_update(hw);
hw->conf0_sync.rxfifo_rst = 0;
uart_ll_update(hw);
}
/**
*/... | 875 |
stop_bit_num = stop_bit;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
{
*stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
{
if (... | 875 |
tx_idle_num = idle_num;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
{
if (break_num > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num);
hw->conf0_sync.txd_brk = 1;
} else {
hw->conf0_sync.tx... | 875 |
rx_flow_en) {
*flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_RTS);
}
if (hw->conf0_sync.tx_flow_en) {
*flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_CTS);
}
}
/**
*/
FORCE_INLINE_ATTR void u... | 875 |
bit_num = data_bit;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
{
hw->conf0_sync.sw_rts = level & 0x1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
{
hw->conf1.sw_dtr = leve... | 875 |
rs485rxby_tx_en = 1;
hw->conf0_sync.irda_en = 0;
hw->conf0_sync.sw_rts = 0;
hw->conf0_sync.irda_en = 0;
hw->rs485_conf_sync.dl0_en = 1;
hw->rs485_conf_sync.dl1_en = 1;
hw->rs485_conf_sync.rs485_en = 1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(u... | 875 |
dl1_en = 1;
hw->rs485_conf_sync.rs485_en = 1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
// lp_uart_dev_t has no following fields (reserved), but no harm si... | 875 |
rs485_en = 0;
hw->rs485_conf_sync.rs485tx_rx_en = 0;
hw->rs485_conf_sync.rs485rxby_tx_en = 0;
hw->conf0_sync.sw_rts = 0;
hw->conf0_sync.irda_en = 1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
... | 875 |
active_threshold + UART_LL_MIN_WAKEUP_THRESH;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
{
*data_bit = (uart_word_length_t)hw->conf0_sync.bit_num;
}
/**
*/
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
{
return ((((hw->status.txfifo_cnt... | 875 |
val = hw->conf0_sync.val;
conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0;
conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0;
conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0;
hw->conf0_... | 875 |
rx_tout_en = 0;
}
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->tout_conf_sync.rx_tout_en > 0) {
tout_thrd = hw->tout_conf_sync.rx_tout_thrhd;
}
return tout_thrd;
}
/**
*/
FORCE_INLINE_ATTR uint16_t ua... | 875 |
negedge_min_cnt;
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
{
return hw->highpulse.highpulse_min_cnt;
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
{
return hw->lowpulse.lowpulse_min_cnt;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_force_xoff... | 875 |
err_wr_mask = discard ? 1 : 0;
uart_ll_update(hw);
}
#ifdef __cplusplus
}
#endif
| 875 |
/*
*/
#pragma once
#include
#include
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/jpeg_struct.h"
#include "hal/jpeg_types.h"
#include "soc/hp_sys_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define JPEG_LL_GET_HW(num) (&JPEG)
typedef enum {
JPEG_LL_DONE = (1 d... | 876 |
dht_val_ac1 = (uint32_t)huffman_value_table[idx];
}
}
/**
*/
static inline void jpeg_ll_dht_dc0_write_codeword(jpeg_dev_t *hw, uint8_t *huffman_bits_table, uint32_t *minimum_code_table)
{
uint32_t element_number = 0;
for (int idx = 0; idx dht_totlen_dc0.dht_totlen_dc0 = element_number;
hw->dht_cod... | 876 |
dht_val_dc1 = (uint32_t)huffman_value_table[idx];
}
}
/**
*/
static inline void jpeg_ll_set_qnr_presition(jpeg_dev_t *hw, uint8_t qnr_presition)
{
hw->config.qnr_presition = qnr_presition;
}
/**
*/
static inline void jpeg_ll_write_quantization_coefficient_t0(jpeg_dev_t *hw, uint32_t *quantization_table)
{
... | 876 |
t3_qnr_val = quantization_table[q];
}
}
/**
*/
static inline void jpeg_ll_set_picture_height(jpeg_dev_t *hw, uint32_t height)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->pic_size, va, height);
}
/**
*/
static inline void jpeg_ll_set_picture_width(jpeg_dev_t *hw, uint32_t width)
{
HAL_FORCE_MODIFY_U32_REG_FIELD... | 876 |
c1_y_factor = vertical_factor;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->c1, c1_dqt_tbl_sel, qun_table_id);
}
/**
*/
static inline void jpeg_ll_set_frame_info_component2(jpeg_dev_t *hw, uint8_t identifier, uint8_t horizontal_factor, uint8_t vertical_factor, uint8_t qun_table_id)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->... | 876 |
c0_x_factor;
component_factor->vertical = hw->c0.c0_y_factor;
}
/**
*/
static inline void jpeg_ll_get_component1_factor(jpeg_dev_t *hw, jpeg_component_factor_t *component_factor)
{
component_factor->horizontal = hw->c1.c1_x_factor;
component_factor->vertical = hw->c1.c1_y_factor;
}
/**
*/
static inline ... | 876 |
qnr_fifo_en = mode;
}
/**
*/
static inline void jpeg_ll_set_decode_component_num(jpeg_dev_t *hw, uint8_t component_num)
{
// ESP32P4 only support to decode color component not larger than 4
HAL_ASSERT(component_num decode_conf, component_num, component_num);
}
/**
*/
static inline void jpeg_ll_sample_mode_s... | 876 |
ff_check_en = ff_check_en;
}
/**
*/
static inline void jpeg_ll_luminance_qnr_table_id(jpeg_dev_t *hw, uint8_t lqnr_id)
{
hw->config.lqnr_tbl_sel = lqnr_id;
}
/**
*/
static inline void jpeg_ll_chrominance_qnr_table_id(jpeg_dev_t *hw, uint8_t cqnr_id)
{
hw->config.cqnr_tbl_sel = cqnr_id;
}
/**
*/
static inl... | 876 |
val;
}
#ifdef __cplusplus
}
#endif
| 876 |
/*
*/
/
/
#pragma once
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include
#include
#include
#include "hal/huk_types.h"
#include "soc/huk_reg.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/* @brief Configure the HUK mode */
static inline void huk_ll_configure_mode(const e... | 877 |
/*
*/
/
/
// The LL layer for SPI register operations
#pragma once
#include //for abs()
#include
#include "esp_types.h"
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "soc/lldesc.h"
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/spi_types.h"
#include "soc/hp_sys_clkrst_struct.h"
... | 878 |
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