text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
val &= ~(1 operators[operator_id].fh_cfg1.tz_clr_ost = 0;
mcpwm->operators[operator_id].fh_cfg1.tz_clr_ost = 1;
}
/**
*/
static inline void mcpwm_ll_brake_enable_oneshot_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable)
{
if (enable) {
mcpwm->operators[operator_id].fh_cfg0.val |= (... | 886 |
fh_cfg1.tz_force_cbc;
}
/**
*/
static inline void mcpwm_ll_brake_trigger_soft_ost(mcpwm_dev_t *mcpwm, int operator_id)
{
mcpwm->operators[operator_id].fh_cfg1.tz_force_ost = ~mcpwm->operators[operator_id].fh_cfg1.tz_force_ost;
}
/**
*/
static inline bool mcpwm_ll_ost_brake_active(mcpwm_dev_t *mcpwm, int operato... | 886 |
cap_phase = phase_value;
}
/**
*/
static inline void mcpwm_ll_capture_enable_timer_sync(mcpwm_dev_t *mcpwm, bool enable)
{
mcpwm->cap_timer_cfg.cap_synci_en = enable;
}
/**
*/
static inline void mcpwm_ll_capture_set_timer_sync(mcpwm_dev_t *mcpwm, int sync_out_timer)
{
mcpwm->cap_timer_cfg.cap_synci_sel = sy... | 886 |
capn_sw = 1; // auto clear
}
/**
*/
__attribute__((always_inline))
static inline uint32_t mcpwm_ll_capture_get_value(mcpwm_dev_t *mcpwm, int channel)
{
return mcpwm->cap_chn[channel].capn_value;
}
/**
*/
__attribute__((always_inline))
static inline mcpwm_capture_edge_t mcpwm_ll_capture_get_edge(mcpwm_dev_t *mcp... | 886 |
timer_cfg0, timer_period) + (symmetric ? 0 : 1);
}
static inline mcpwm_timer_count_mode_t mcpwm_ll_timer_get_count_mode(mcpwm_dev_t *mcpwm, int timer_id)
{
switch (mcpwm->timer[timer_id].timer_cfg1.timer_mod) {
case 1:
return MCPWM_TIMER_COUNT_MODE_UP;
case 2:
return MCPWM_TIMER_COUNT_MODE_... | 886 |
/*
*/
#pragma once
#include /* For NULL declaration */
#include
#include
#include "hal/misc.h"
#include "soc/lcd_cam_reg.h"
#include "soc/lcd_cam_struct.h"
#include "hal/assert.h"
#include "hal/lcd_types.h"
#include "soc/hp_sys_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LCD_LL_GET_HW(id) (((... | 887 |
..) (void)__DECLARE_RCC_RC_ATOMIC_ENV; lcd_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void lcd_ll_reset_register(int group_id)
{
(void)group_id;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_lcdcam = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_lcdcam = 0;
}
/// use a macro to wrap the function, force the cal... | 887 |
peri_clk_ctrl19.reg_lcd_clk_src_sel = 0;
break;
case LCD_CLK_SRC_PLL160M:
HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 1;
break;
case LCD_CLK_SRC_APLL:
HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 2;
break;
default:
// disable the clock
H... | 887 |
peri_clk_ctrl110, reg_lcd_clk_div_num, div_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl110, reg_lcd_clk_div_denominator, div_a);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl110, reg_lcd_clk_div_numerator, div_b);
}
/// use a macro to wrap the function, force the caller to use ... | 887 |
lcd_clk_equ_sysclk = 1;
} else {
dev->lcd_clock.lcd_clk_equ_sysclk = 0;
scale = prescale - 1;
}
dev->lcd_clock.lcd_clkcnt_n = scale;
}
/**
*/
static inline void lcd_ll_enable_rgb_yuv_convert(lcd_cam_dev_t *dev, bool en)
{
dev->lcd_rgb_yuv.lcd_conv_enable = en;
}
/**
*/
static inline ... | 887 |
lcd_conv_data_out_mode = 1;
}
}
/**
*/
static inline void lcd_ll_set_yuv_convert_std(lcd_cam_dev_t *dev, lcd_yuv_conv_std_t std)
{
if (std == LCD_YUV_CONV_STD_BT601) {
dev->lcd_rgb_yuv.lcd_conv_protocol_mode = 0;
} else if (std == LCD_YUV_CONV_STD_BT709) {
dev->lcd_rgb_yuv.lcd_conv_protoco... | 887 |
lcd_conv_trans_mode = 0;
dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 3;
switch (yuv_sample) {
case LCD_YUV_SAMPLE_422:
dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 0;
break;
case LCD_YUV_SAMPLE_420:
dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 1;
break;
case LCD_YUV_SAMPLE_411:
... | 887 |
lcd_conv_yuv2yuv_mode = 0;
break;
case LCD_YUV_SAMPLE_420:
dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 1;
break;
case LCD_YUV_SAMPLE_411:
dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 2;
break;
default:
abort();
}
}
/**
*/
__attribute__((always_inline))
static i... | 887 |
lcd_vbk_cyclelen = bk_cycles - 1;
}
/**
*/
static inline void lcd_ll_set_dma_read_stride(lcd_cam_dev_t *dev, uint32_t stride)
{
switch (stride) {
case 8:
dev->lcd_user.lcd_byte_mode = 0;
break;
case 16:
dev->lcd_user.lcd_byte_mode = 1;
break;
case 24:
dev->lcd_u... | 887 |
lcd_update_reg = 1; // update parameters before start transaction
dev->lcd_user.lcd_start = 1;
}
/**
*/
__attribute__((always_inline))
static inline void lcd_ll_stop(lcd_cam_dev_t *dev)
{
dev->lcd_user.lcd_start = 0;
dev->lcd_user.lcd_update_reg = 1; // self clear
}
/**
*/
static inline void lcd_ll_rese... | 887 |
lcd_dout_byte_swizzle_mode = mode;
}
/**
*/
__attribute__((always_inline))
static inline void lcd_ll_fifo_reset(lcd_cam_dev_t *dev)
{
dev->lcd_misc.lcd_afifo_reset = 1; // self clear
}
/**
*/
__attribute__((always_inline))
static inline void lcd_ll_set_dc_level(lcd_cam_dev_t *dev, bool idle_phase, bool cmd_phas... | 887 |
val = command & 0xFF;
dev->lcd_latter_cmd_val.val = (command >> 8) & 0xFF;
} else if (data_width == 16) {
dev->lcd_first_cmd_val.val = command;
}
}
/**
*/
static inline void lcd_ll_enable_rgb_mode(lcd_cam_dev_t *dev, bool en)
{
dev->lcd_ctrl.lcd_rgb_mode_en = en;
}
/**
*/
static inline v... | 887 |
lcd_hsync_width = hsw - 1;
dev->lcd_ctrl.lcd_hb_front = hbp + hsw - 1;
dev->lcd_ctrl1.lcd_ha_width = active_width - 1;
dev->lcd_ctrl1.lcd_ht_width = hsw + hbp + active_width + hfp - 1;
}
/**
*/
static inline void lcd_ll_set_vertical_timing(lcd_cam_dev_t *dev, uint32_t vsw, uint32_t vbp, uint32_t active_he... | 887 |
lcd_hsync_mode = hsync_delay;
dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_delay;
dev->lcd_dly_mode_cfg1.lcd_de_mode = de_delay;
}
/**
*/
static inline void lcd_ll_enable_interrupt(lcd_cam_dev_t *dev, uint32_t mask, bool en)
{
if (en) {
dev->lc_dma_int_ena.val |= mask & 0x03;
} else {
... | 887 |
/*
*/
#pragma once
#include
#include
#include "hal/ppa_types.h"
#include "hal/color_types.h"
#include "soc/ppa_struct.h"
#include "soc/ppa_reg.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/assert.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PPA_LL_GET_HW &PPA
#define PPA_L... | 888 |
sr_rotate_angle = val;
}
/**
*/
static inline void ppa_ll_sr_enable_mirror_x(ppa_dev_t *dev, bool enable)
{
dev->sr_scal_rotate.sr_mirror_x = enable;
}
/**
*/
static inline void ppa_ll_sr_enable_mirror_y(ppa_dev_t *dev, bool enable)
{
dev->sr_scal_rotate.sr_mirror_y = enable;
}
/**
*/
static inline void p... | 888 |
sr_tx_cm = val;
}
/**
*/
static inline void ppa_ll_sr_set_yuv2rgb_std(ppa_dev_t *dev, color_conv_std_rgb_yuv_t std)
{
switch (std) {
case COLOR_CONV_STD_RGB_YUV_BT601:
dev->sr_color_mode.yuv2rgb_protocol = 0;
break;
case COLOR_CONV_STD_RGB_YUV_BT709:
dev->sr_color_mode.yuv2rgb_prot... | 888 |
yuv_rx_range = 0;
break;
case COLOR_RANGE_FULL:
dev->sr_color_mode.yuv_rx_range = 1;
break;
default:
// Unsupported color range
abort();
}
}
/**
*/
static inline void ppa_ll_sr_set_tx_yuv_range(ppa_dev_t *dev, color_range_t range)
{
switch (range) {
case COL... | 888 |
sr_rx_alpha_mod = 0;
dev->sr_fix_alpha.sr_rx_alpha_inv = 0;
break;
case PPA_LL_RX_ALPHA_FIX_VALUE:
dev->sr_fix_alpha.sr_rx_alpha_mod = 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sr_fix_alpha, sr_rx_fix_alpha, val);
dev->sr_fix_alpha.sr_rx_alpha_inv = 0;
break;
case PP... | 888 |
blend_bypass = 0;
dev->blend_trans_mode.blend_fix_pixel_fill_en = 0;
break;
case PPA_LL_BLEND_TRANS_MODE_FILL:
dev->blend_trans_mode.blend_bypass = 0;
dev->blend_trans_mode.blend_fix_pixel_fill_en = 1;
break;
case PPA_LL_BLEND_TRANS_MODE_BYPASS_BLEND:
dev->blend_t... | 888 |
blend0_rx_cm = val;
}
/**
*/
static inline void ppa_ll_blend_set_rx_fg_color_mode(ppa_dev_t *dev, ppa_blend_color_mode_t color_mode)
{
uint32_t val = 0;
switch (color_mode) {
case PPA_BLEND_COLOR_MODE_ARGB8888:
val = 0;
break;
case PPA_BLEND_COLOR_MODE_RGB888:
val = 1;
... | 888 |
blend_tx_cm = val;
}
/**
*/
static inline void ppa_ll_blend_enable_rx_bg_rgb_swap(ppa_dev_t *dev, bool enable)
{
dev->blend_byte_order.blend0_rx_rgb_swap_en = enable;
}
/**
*/
static inline void ppa_ll_blend_enable_rx_fg_rgb_swap(ppa_dev_t *dev, bool enable)
{
dev->blend_byte_order.blend1_rx_rgb_swap_en = e... | 888 |
blend0_rx_alpha_mod = 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_fix_alpha, blend0_rx_fix_alpha, val);
dev->blend_fix_alpha.blend0_rx_alpha_inv = 0;
break;
case PPA_LL_RX_ALPHA_SCALE:
dev->blend_fix_alpha.blend0_rx_alpha_mod = 2;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_fi... | 888 |
blend1_rx_alpha_mod = 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_fix_alpha, blend1_rx_fix_alpha, val);
dev->blend_fix_alpha.blend1_rx_alpha_inv = 0;
break;
case PPA_LL_RX_ALPHA_SCALE:
dev->blend_fix_alpha.blend1_rx_alpha_mod = 2;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_fi... | 888 |
val = rgb;
}
/*
*/
/**
*/
static inline void ppa_ll_blend_configure_rx_bg_ck_range(ppa_dev_t *dev, uint32_t rgb_thres_low, uint32_t rgb_thres_high)
{
dev->ck_bg_low.val = rgb_thres_low;
dev->ck_bg_high.val = rgb_thres_high;
}
/**
*/
static inline void ppa_ll_blend_configure_rx_fg_ck_range(ppa_dev_t *dev, ... | 888 |
blend_clut_mem_force_pu = 1; // force clut mem remain power when memory domain PD
}
/**
*/
static inline void ppa_ll_blend_disable_clut_mem(ppa_dev_t *dev)
{
dev->clut_conf.blend_clut_mem_clk_ena = 0;
dev->clut_conf.blend_clut_mem_force_pu = 0;
}
/**
*/
static inline void ppa_ll_blend_reset_rx_bg_clut_mem(p... | 888 |
rdwr_word_blend1_clut = data;
}
/**
*/
static inline void ppa_ll_blend_wr_rx_bg_clut_data_by_mem(ppa_dev_t *dev, uint32_t idx, uint32_t data)
{
volatile uint32_t *blend0_clut_mem = (uint32_t *)((uint32_t)dev + PPA_LL_BLEND0_CLUT_MEM_ADDR_OFFSET);
blend0_clut_mem[idx] = data;
}
/**
*/
static inline void ppa_... | 888 |
/*
*/
#pragma once
#include
#include
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/ eFuse fields /
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flas... | 889 |
rd_mac_sys_2.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return EFUSE.rd_mac_sys_2.wafer_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_ge... | 889 |
conf.cfg_ecdsa_blk = efuse_blk;
}
/ eFuse control functions /
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
{
return EFUSE.cmd.read_cmd;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
{
return EFUSE.cmd.pgm_cmd;
}
__attribute__((always_inline))... | 889 |
wr_tim_conf2.pwr_off_num = value;
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
{
EFUSE.wr_tim_conf0_rs_bypass.update = 1;
}
/ eFuse control functions /
#ifdef __cplusplus
}
#endif
| 889 |
/*
*/
#pragma once
#include
#include
#include "hal/assert.h"
#include "soc/mipi_dsi_bridge_struct.h"
#include "hal/mipi_dsi_types.h"
#include "hal/lcd_types.h"
#define MIPI_DSI_LL_GET_BRG(bus_id) (bus_id == 0 ? &MIPI_DSI_BRIDGE : NULL)
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
MIPI_DSI_LL_FLOW_C... | 890 |
credit_thrd = threshold;
}
/**
*/
static inline void mipi_dsi_brg_ll_credit_set_burst_threshold(dsi_brg_dev_t *dev, uint32_t threshold)
{
dev->raw_buf_credit_ctl.credit_burst_thrd = threshold;
}
/**
*/
static inline void mipi_dsi_brg_ll_credit_reset(dsi_brg_dev_t *dev)
{
dev->raw_buf_credit_ctl.credit_reset... | 890 |
data_in_type = 0;
break;
case LCD_COLOR_SPACE_YUV:
dev->pixel_type.data_in_type = 1;
break;
default:
abort();
}
}
/**
*/
static inline void mipi_dsi_brg_ll_set_vertical_timing(dsi_brg_dev_t *dev, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp)
{
dev->d... | 890 |
dpi_en = en;
}
/**
*/
static inline void mipi_dsi_brg_ll_update_dpi_config(dsi_brg_dev_t *dev)
{
dev->dpi_config_update.dpi_config_update = 1;
}
/**
*/
static inline void mipi_dsi_brg_ll_enable_ref_clock(dsi_brg_dev_t *dev, bool en)
{
dev->host_ctrl.dsi_cfg_ref_clk_en = en;
}
/**
*/
static inline void mip... | 890 |
/*
*/
#pragma once
#include
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/mipi_dsi_host_struct.h"
#include "hal/mipi_dsi_types.h"
#include "hal/lcd_types.h"
#define MIPI_DSI_LL_GET_HOST(bus_id) (bus_id == 0 ? &MIPI_DSI_HOST : NULL)
#define MIPI_DSI_LL_MAX_DPI_CLK_DIV 256
#ifdef __cplusplu... | 891 |
auto_clklane_ctrl = 1;
dev->lpclk_ctrl.phy_txrequestclkhs = 1;
break;
case MIPI_DSI_LL_CLOCK_LANE_STATE_HS:
dev->lpclk_ctrl.auto_clklane_ctrl = 0;
dev->lpclk_ctrl.phy_txrequestclkhs = 1;
break;
case MIPI_DSI_LL_CLOCK_LANE_STATE_LP:
dev->lpclk_ctrl.auto_clklane_ctr... | 891 |
dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG1 + sub_config;
break;
case LCD_COLOR_PIXEL_FORMAT_RGB666:
dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_18BIT_CONFIG1 + sub_config;
break;
case LCD_COLOR_PIXEL_FORMAT_RGB888:
dev->dpi_color_coding.dpi_color_... | 891 |
colorm_active_low = color_mode_active_low;
}
/**
*/
static inline void mipi_dsi_host_ll_dpi_enable_frame_ack(dsi_host_dev_t *dev, bool en)
{
dev->vid_mode_cfg.frame_bta_ack_en = en;
}
/**
*/
static inline void mipi_dsi_host_ll_dpi_enable_lp_horizontal_timing(dsi_host_dev_t *dev, bool en_hbp, bool en_hfp)
{
... | 891 |
vid_mode_type = type;
}
/**
*/
static inline void mipi_dsi_host_ll_dpi_set_pattern_type(dsi_host_dev_t *dev, mipi_dsi_pattern_type_t type)
{
switch (type) {
case MIPI_DSI_PATTERN_BAR_HORIZONTAL:
dev->vid_mode_cfg.vpg_mode = 0;
dev->vid_mode_cfg.vpg_orientation = 1;
dev->vid_mode_cfg.vp... | 891 |
vid_num_chunks = trunks_num;
}
/**
*/
static inline void mipi_dsi_host_ll_dpi_set_video_packet_pixel_num(dsi_host_dev_t *dev, uint32_t packet_pixels)
{
dev->vid_pkt_size.vid_pkt_size = packet_pixels;
}
/**
*/
static inline void mipi_dsi_host_ll_dpi_set_vertical_timing(dsi_host_dev_t *dev, uint32_t vsw, uint32_t... | 891 |
tear_fx_en = en;
}
/**
*/
static inline void mipi_dsi_host_ll_enable_cmd_ack(dsi_host_dev_t *dev, bool enable)
{
dev->cmd_mode_cfg.ack_rqst_en = enable;
}
/**
*/
static inline void mipi_dsi_host_ll_set_dcs_short_wr_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed)
{
... | 891 |
dcs_sr_0p_tx = speed;
break;
default:
HAL_ASSERT(false);
}
}
/**
*/
static inline void mipi_dsi_host_ll_set_gen_short_wr_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed)
{
switch (num_of_params) {
case 0: // Generic short write command with n... | 891 |
gen_sr_0p_tx = speed;
break;
case 1: // Generic short read command with one parameter
dev->cmd_mode_cfg.gen_sr_1p_tx = speed;
break;
case 2: // Generic short read command with two parameters
dev->cmd_mode_cfg.gen_sr_2p_tx = speed;
break;
default:
HAL_ASSERT(fa... | 891 |
ecc_rx_en = enable;
}
/**
*/
static inline void mipi_dsi_host_ll_enable_bta(dsi_host_dev_t *dev, bool enable)
{
dev->pckhdl_cfg.bta_en = enable;
}
/**
*/
static inline void mipi_dsi_host_ll_set_lp_largest_cmd_packet_size(dsi_host_dev_t *dev, uint32_t in_vact, uint32_t out_vact)
{
HAL_FORCE_MODIFY_U32_REG_FI... | 891 |
gen_rd_cmd_busy;
}
/**
*/
static inline bool mipi_dsi_host_ll_gen_is_read_fifo_full(dsi_host_dev_t *dev)
{
return dev->cmd_pkt_status.gen_pld_r_full;
}
/**
*/
static inline bool mipi_dsi_host_ll_gen_is_read_fifo_empty(dsi_host_dev_t *dev)
{
return dev->cmd_pkt_status.gen_pld_r_empty;
}
/**
*/
static inlin... | 891 |
gen_vcid_tear_auto = vcid;
}
/**
*/
static inline void mipi_dsi_host_ll_gen_set_tx_vcid(dsi_host_dev_t *dev, uint32_t vcid)
{
dev->gen_vcid.gen_vcid_tx_auto = vcid;
}
#ifdef __cplusplus
}
#endif
| 891 |
/*
*/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/gpio_ext_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void sdm_ll_enable_clock(gpio_sd_dev_t *hw, bool en)
{
hw->misc.function_clk_en = en;
}
/**
*/
__attribute__((always_inline))
static inline ... | 892 |
/*
*/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/mipi_csi_host_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void mipi_csi_phy_ll_write_clock(csi_host_dev_t *dev, uint32_t clock_level, bool clear)
{
dev->phy_test_ctrl0.val = clock_level phy_test_... | 893 |
/*
*/
/
/
#pragma once
#include
#include
#include "esp_bit_defs.h"
#include "hal/assert.h"
#include "soc/pmu_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define LDO_LL_UNIT_NUM 4
/**
*/
#define LDO_LL_EXT_LDO_DREF_VOL_H_BASE 1000
#define LDO_LL_EXT_LDO_DREF_VOL_H_STEP 100
#define LDO_LL_EXT_... | 894 |
pmu_ext_ldo.force_tieh_sel = 1;
PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo_ana.dref = dref;
PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo_ana.mul = mul;
}
#ifdef __cplusplus
}
#endif
| 894 |
/*
*/
// The HAL layer for Key Manager
#pragma once
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include "hal/key_mgr_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/* @brief Start the key manager at IDLE state */
void key_mgr_hal_start(void);
/* @brief Continue the key manager operation */
void key... | 895 |
/*
*/
#include
#include "esp_attr.h"
#include "soc/hp_system_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
{
if (core_id == 0) {
WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG, 0);
} else {
WRITE_PERI_REG(HP_SYST... | 896 |
/*
*/
#pragma once
#include
#include
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/misc.h"
#include "hal/mipi_dsi_host_ll.h"
#include "hal/mipi_dsi_brg_ll.h"
#include "hal/mipi_dsi_phy_ll.h"
#define MIPI_DSI_LL_NUM_BUS 1 // 1 MIPI DSI bus
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void m... | 897 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_reset_register(__VA_ARGS__)
/**
*/
static inline void mipi_dsi_ll_enable_dpi_clock(int group_id, bool enable)
{
(void)group_id;
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in ... | 897 |
peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 1;
break;
default:
abort();
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define mipi_dsi_ll_set_dpi_clock_sourc... | 897 |
peri_clk_ctrl03.reg_mipi_dsi_dphy_cfg_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define mipi_dsi_ll_enable_phy_config_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mip... | 897 |
peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 0;
break;
case MIPI_DSI_PHY_CLK_SRC_RC_FAST:
HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 1;
break;
case MIPI_DSI_PHY_CLK_SRC_PLL_F25M:
HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 2;
break;... | 897 |
/*
*/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/mipi_csi_host_struct.h"
#include "hal/mipi_csi_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MIPI_CSI_HOST_LL_GET_HW(num) (((num) == 0) ? (&MIPI_CSI_HOST) : NULL)
#define MIPI_CSI_HOST_LL_LANE_NUM_MAX 2
/**
*... | 898 |
/*
*/
/
/
#pragma once
#include
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/touch_sensor_periph.h"
#include "soc/lp_analog_peri_struct.h"
#include "soc/touch_struct.h"
#include "soc/pmu_struct.h"
#include "soc/soc_caps.h"
#include "hal/touch_sensor_types.h"
#ifdef __cplusplus
extern "C"... | 899 |
touch_scan_ctrl1.touch_scan_pad_map = mask;
LP_ANA_PERI.touch_filter2.touch_outen = mask;
}
/**
*/
static inline void touch_ll_channel_power_on(uint16_t chan_mask)
{
uint32_t curr_mask = LP_ANA_PERI.touch_mux1.touch_xpd;
LP_ANA_PERI.touch_mux1.touch_xpd = chan_mask | curr_mask;
}
/**
*/
static inline vo... | 899 |
touch_status_clr = 1;
}
/**
*/
__attribute__((always_inline))
static inline void touch_ll_read_chan_data(uint32_t touch_num, uint8_t sampler_id, uint8_t type, uint32_t *data)
{
HAL_ASSERT(sampler_id 0;
LP_ANA_PERI.touch_ana_para.touch_touch_en_cal = enable;
LP_ANA_PERI.touch_ana_para.touch_touch_dcap_cal... | 899 |
touch_filter2.touch_bypass_neg_noise_thres = always_update;
LP_ANA_PERI.touch_filter1.touch_neg_noise_disupdate_baseline_en = stop_update;
LP_ANA_PERI.touch_filter1.touch_neg_noise_thres = always_update || stop_update ? 0 : neg_noise_thresh;
LP_ANA_PERI.touch_filter1.touch_neg_noise_limit = always_update ||... | 899 |
touch_update_baseline_sw = 1;
// waiting for update
while (LP_ANA_PERI.touch_filter3.touch_update_baseline_sw);
}
/ Waterproof register setting /
/**
*/
static inline void touch_ll_waterproof_set_guard_chan(uint32_t pad_num)
{
LP_ANA_PERI.touch_scan_ctrl2.touch_out_ring = pad_num;
}
/**
*/
static inlin... | 899 |
touch_approach.touch_approach_pad1 = touch_num;
break;
case 2:
LP_ANA_PERI.touch_approach.touch_approach_pad2 = touch_num;
break;
default:
// invalid approach channel
abort();
}
}
/**
*/
static inline void touch_ll_approach_set_measure_ti... | 899 |
aprch_ch_data, approach_pad0_cnt);
break;
case 1:
*cnt = HAL_FORCE_READ_U32_REG_FIELD(LP_TOUCH.aprch_ch_data, approach_pad1_cnt);
break;
case 2:
*cnt = HAL_FORCE_READ_U32_REG_FIELD(LP_TOUCH.aprch_ch_data, approach_pad2_cnt);
break;
defa... | 899 |
touch_slp0.touch_slp_pad);
}
/**
*/
static inline void touch_ll_sleep_set_threshold(uint8_t sampler_id, uint32_t touch_thresh)
{
switch (sampler_id) {
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_ANA_PERI.touch_slp0, touch_slp_th0, touch_thresh);
break;
case 1:
HAL... | 899 |
touch_mux0.touch_data_sel = type;
*data = HAL_FORCE_READ_U32_REG_FIELD(LP_TOUCH.slp_ch_data, slp_data);
}
/**
static inline void touch_ll_sleep_reset_benchmark(void)
{
LP_ANA_PERI.touch_slp0.touch_slp_channel_clr = 1;
}
/**
*/
static inline void touch_ll_sleep_read_debounce(uint32_t *debounce)
{
*debounc... | 899 |
/*
*/
#pragma once
#include
#include
#include "esp_assert.h"
#include "hal/misc.h"
#include "hal/dw_gdma_types.h"
#include "soc/dw_gdma_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/reg_base.h"
#define DW_GDMA_LL_GET_HW() (&DW_GDMA)
#define DW_GDMA_LL_GROUPS 1 // there's one DW-GDMA ... | 900 |
dmac_rst = 1;
while (dev->reset0.dmac_rst);
}
/**
*/
static inline void dw_gdma_ll_enable_controller(dw_gdma_dev_t *dev, bool en)
{
dev->cfg0.dmac_en = en;
}
/**
*/
static inline void dw_gdma_ll_enable_intr_global(dw_gdma_dev_t *dev, bool en)
{
dev->cfg0.int_en = en;
}
/**
*/
static inline volatile vo... | 900 |
val &= ~mask;
}
}
/**
*/
static inline uint32_t dw_gdma_ll_get_common_intr_status(dw_gdma_dev_t *dev)
{
return dev->common_int_st0.val;
}
/**
*/
static inline void dw_gdma_ll_channel_enable_intr_generation(dw_gdma_dev_t *dev, uint8_t channel, uint32_t mask, bool en)
{
if (en) {
dev->ch[channel].... | 900 |
int_clr0.val = mask;
}
/**
*/
static inline void dw_gdma_ll_channel_enable(dw_gdma_dev_t *dev, uint8_t channel, bool en)
{
if (en) {
dev->chen0.val = 0x101 chen0.val = 0x100 chen0.val = 0x1010000 chen0.val = 0x1000000 chen1.val = 0x101 ch[channel].sar0.sar0 = src_addr;
}
/**
*/
__attribute__((always_inl... | 900 |
ctl0.dms = DW_GDMA_LL_MASTER_PORT_MIPI_DSI;
} else {
dev->ch[channel].ctl0.dms = DW_GDMA_LL_MASTER_PORT_MEMORY;
}
}
/**
*/
__attribute__((always_inline))
static inline void dw_gdma_ll_channel_set_src_burst_mode(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_burst_mode_t mode)
{
dev->ch[channel].ctl0... | 900 |
ctl0.src_msize = items;
}
/**
*/
__attribute__((always_inline))
static inline void dw_gdma_ll_channel_set_dst_burst_items(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_burst_items_t items)
{
dev->ch[channel].ctl0.dst_msize = items;
}
/**
*/
__attribute__((always_inline))
static inline void dw_gdma_ll_channel_set... | 900 |
ctl1.val;
ctrl1.shadowreg_or_lli_last = is_last;
ctrl1.ioc_blktfr = en_intr;
ctrl1.shadowreg_or_lli_valid = is_valid;
dev->ch[channel].ctl1.val = ctrl1.val;
}
/**
*/
__attribute__((always_inline))
static inline void dw_gdma_ll_channel_enable_src_periph_status_write_back(dw_gdma_dev_t *dev, uint8_t cha... | 900 |
ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_M2M_DMAC;
break;
case _MAKE_GDMA_FLOW_CTRL_CODE(0, 1, DW_GDMA_FLOW_CTRL_SELF):
dev->ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_M2P_DMAC;
break;
case _MAKE_GDMA_FLOW_CTRL_CODE(1, 0, DW_GDMA_FLOW_CTRL_SELF):
dev->ch[channel].cfg1.tt_fc = DW_GD... | 900 |
cfg1.tt_fc = DW_GDMA_LL_FLOW_P2P_DST;
break;
default:
abort();
break;
}
}
/**
*/
static inline void dw_gdma_ll_channel_set_src_handshake_interface(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_handshake_type_t hs)
{
dev->ch[channel].cfg1.hs_sel_src = hs;
}
/**
*/
static inline voi... | 900 |
cfg1.dst_per = DW_GDMA_LL_HW_HANDSHAKE_PERIPH_DSI;
break;
case DW_GDMA_ROLE_PERIPH_CSI:
dev->ch[channel].cfg1.dst_per = DW_GDMA_LL_HW_HANDSHAKE_PERIPH_CSI;
break;
case DW_GDMA_ROLE_PERIPH_ISP:
dev->ch[channel].cfg1.dst_per = DW_GDMA_LL_HW_HANDSHAKE_PERIPH_ISP;
break;
... | 900 |
cfg1.src_osr_lmt = limit - 1;
}
/**
*/
static inline void dw_gdma_ll_channel_set_dst_outstanding_limit(dw_gdma_dev_t *dev, uint8_t channel, uint32_t limit)
{
dev->ch[channel].cfg1.dst_osr_lmt = limit - 1;
}
/**
*/
static inline void dw_gdma_ll_channel_set_link_list_head_addr(dw_gdma_dev_t *dev, uint8_t channel,... | 900 |
blk_tfr_resumereq0.val = 0x01;
}
/**
*/
static inline void dw_gdma_ll_channel_set_src_periph_status_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr)
{
dev->ch[channel].sstatar0.sstatar0 = addr;
}
/**
*/
static inline void dw_gdma_ll_channel_set_dst_periph_status_addr(dw_gdma_dev_t *dev, uint8_t channel,... | 900 |
sms = DW_GDMA_LL_MASTER_PORT_MIPI_CSI;
} else {
lli->ctrl_lo.sms = DW_GDMA_LL_MASTER_PORT_MEMORY;
}
}
/**
*/
__attribute__((always_inline))
static inline void dw_gdma_ll_lli_set_dst_master_port(dw_gdma_link_list_item_t *lli, intptr_t mem_addr)
{
if (mem_addr == MIPI_DSI_BRG_MEM_BASE) {
lli... | 900 |
sinc = mode;
}
/**
*/
__attribute__((always_inline))
static inline void dw_gdma_ll_lli_set_dst_burst_mode(dw_gdma_link_list_item_t *lli, dw_gdma_burst_mode_t mode)
{
lli->ctrl_lo.dinc = mode;
}
/**
*/
__attribute__((always_inline))
static inline void dw_gdma_ll_lli_set_src_burst_items(dw_gdma_link_list_item_t *... | 900 |
ioc_blktfr = en_intr;
lli->ctrl_hi.shadowreg_or_lli_last = is_last;
lli->ctrl_hi.shadowreg_or_lli_valid = is_valid;
}
/**
*/
__attribute__((always_inline))
static inline void dw_gdma_ll_lli_enable_src_periph_status_write_back(dw_gdma_link_list_item_t *lli, bool en)
{
lli->ctrl_hi.src_stat_en = en;
}
/**
... | 900 |
loc0 = addr >> 6;
lli->llp_hi.val = 0;
}
/**
*/
static inline uint32_t dw_gdma_ll_lli_get_trans_amount(dw_gdma_link_list_item_t *lli)
{
return lli->status_lo.cmpltd_blk_tfr_size;
}
/**
*/
static inline uint32_t dw_gdma_ll_lli_get_fifo_remain(dw_gdma_link_list_item_t *lli)
{
return lli->status_hi.data_le... | 900 |
/*
*/
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/regi2c_defs.h"
#include "soc/hp_sys_clkrst_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_cpll_calibration_start(void)
{
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CT... | 901 |
/*
*/
/
/
#pragma once
#include
#include
#include
#include "soc/hwcrypto_reg.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/soc_caps.h"
#include "hal/ds_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void ds_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.peri_clk_ctrl25.... | 902 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; ds_ll_reset_register(__VA_ARGS__)
static inline void ds_ll_start(void)
{
REG_WRITE(DS_SET_START_REG, 1);
}
/**
*/
static inline bool ds_ll_busy(void)
{
return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false;
}
/**
*/
static inline void ds_ll_wait_busy(void)
{
while ... | 902 |
addr, from, frags[i].len);
asm volatile ("fence");
from += frags[i].len;
}
}
/**
*/
static inline void ds_ll_start_sign(void)
{
REG_WRITE(DS_SET_CONTINUE_REG, 1);
}
/**
*/
static inline ds_signature_check_t ds_ll_check_signature(void)
{
uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
... | 902 |
/*
*/
// The LL layer for MMU register operations
#pragma once
#include "soc/spi_mem_c_reg.h"
#include "soc/spi_mem_s_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#include "hal/efuse_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
///> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
ret... | 903 |
MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0);
}
#ifdef __cplusplus
}
#endif
| 903 |
/*
*/
/
/
#pragma once
#include
#include "esp_bit_defs.h"
#include "soc/soc_caps.h"
#include "soc/lp_gpio_struct.h"
#include "soc/lp_iomux_struct.h"
#include "soc/lp_gpio_sig_map.h"
#include "soc/pmu_struct.h"
#include "hal/misc.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RTCIO_LL_... | 904 |
pad[rtcio_num].rue = 0;
}
/**
*/
static inline void rtcio_ll_pulldown_enable(int rtcio_num)
{
/* Enable internal weak pull-down */
LP_IOMUX.pad[rtcio_num].rde = 1;
}
/**
*/
static inline void rtcio_ll_pulldown_disable(int rtcio_num)
{
/* Enable internal weak pull-down */
LP_IOMUX.pad[rtcio_num].rde ... | 904 |
imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
}
/**
*/
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
LP_GPIO.pin[rtcio_num].wakeup_enable = 1;
LP_GPIO.pin[rtcio_num].int_type = type;
}
/**
*/
static inline void rtcio_ll_wakeup_disable(int rtcio_num)
{
LP_GPIO.pin[... | 904 |
pad[rtcio_num].slp_sel = 0;
}
/**
*/
static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num)
{
HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function");
return LP_GPIO.pin[rtcio_num].wakeup_enable;
}
/**
*/
static inline uint32_t rtcio_ll_get_in... | 904 |
/*
*/
// The LL layer for I2S register operations
/
/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/i2s_types.h"
#include "hal/hal_utils.h"
#ifdef __cplusplus
extern "C" {
#endif
#de... | 905 |
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