text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
soc_clk_ctrl2.reg_i2s0_apb_clk_en = enable;
return;
case 1:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s1_apb_clk_en = enable;
return;
case 2:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s2_apb_clk_en = enable;
return;
}
}
/// use a macro to wrap the functio... | 905 |
hp_rst_en2.reg_rst_en_i2s2_apb = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s2_apb = 0;
return;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define i2s_ll_... | 905 |
peri_clk_ctrl13.reg_i2s0_tx_clk_en = 1;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_tx_clk_en = 1;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_tx_clk_en = 1;
return;
}
}
/// use a macro to wrap the function, force the... | 905 |
peri_clk_ctrl17.reg_i2s2_rx_clk_en = 1;
return;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define i2s_ll_rx_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _i2s_... | 905 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; i2s_ll_tx_disable_clock(__VA_ARGS__)
/**
*/
static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw)
{
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
switch (I2S_LL_GET_ID(hw)) {
case 0:
... | 905 |
peri_clk_ctrl14.reg_i2s0_mst_clk_sel = 1;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_mst_clk_sel = 1;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_mst_clk_sel = 1;
return;
}
}
/// use a macro to wrap the function, for... | 905 |
peri_clk_ctrl17.reg_i2s1_mst_clk_sel = 0;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_mst_clk_sel = 0;
return;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RC... | 905 |
tx_fifo_reset = 1;
hw->tx_conf.tx_fifo_reset = 0;
}
/**
*/
static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
{
hw->rx_conf.rx_fifo_reset = 1;
hw->rx_conf.rx_fifo_reset = 0;
}
static inline uint32_t i2s_ll_get_clk_src(i2s_clock_src_t src)
{
switch (src)
{
case I2S_CLK_SRC_XTAL:
... | 905 |
peri_clk_ctrl15.reg_i2s1_tx_clk_src_sel = clk_src;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_tx_clk_src_sel = clk_src;
return;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declar... | 905 |
peri_clk_ctrl17.reg_i2s2_rx_clk_src_sel = clk_src;
return;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define i2s_ll_rx_clk_set_src(...) (void)__DECLARE_RCC_ATOMIC_... | 905 |
reg_i2s0_tx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_yn1 = yn1;
return;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl16, reg_i2s1_tx_div_n, div_int);
HP_SYS_CLKRS... | 905 |
peri_clk_ctrl12, reg_i2s0_rx_div_n, div_int);
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_x = x;
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_yn1 = yn1;
... | 905 |
peri_clk_ctrl18.reg_i2s2_rx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_yn1 = yn1;
return;
}
}
/**
*/
static inline void _i2s_ll_tx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div)
{
/* Workaround for inaccurate clock while switching from a relatively low sampl... | 905 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; _i2s_ll_tx_set_mclk(__VA_ARGS__)
/**
*/
static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
{
hw->rx_conf.rx_bck_div_num = val - 1;
}
/**
*/
static inline void _i2s_ll_rx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div)
{
/* Workaround fo... | 905 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; _i2s_ll_rx_set_mclk(__VA_ARGS__)
/**
*/
static inline void i2s_ll_tx_start(i2s_dev_t *hw)
{
// Have to update registers before start
hw->tx_conf.tx_update = 1;
while (hw->tx_conf.tx_update);
hw->tx_conf.tx_start = 1;
}
/**
*/
static inline void i2s_ll_rx_start(i2s... | 905 |
rx_eof_num = eof_num;
}
/**
*/
static inline void i2s_ll_tx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit)
{
hw->tx_conf1.tx_bits_mod = data_bit - 1;
hw->tx_conf1.tx_tdm_chan_bits = chan_bit - 1;
}
/**
*/
static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bi... | 905 |
rx_msb_shift = msb_shift_enable;
}
/**
*/
static inline void i2s_ll_tx_set_chan_num(i2s_dev_t *hw, int total_num)
{
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = total_num - 1;
}
/**
*/
static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
{
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1;
}
... | 905 |
tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
case I2S_STD_SLOT_RIGHT:
chan_mask |= 0x02;
break;
case I2S_STD_SLOT_BOTH:
chan_mask |= 0x03;
... | 905 |
tx_chan_mod = mod;
}
/**
*/
static inline void i2s_ll_tx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
{
hw->tx_conf.tx_ws_idle_pol = ws_pol_level;
}
/**
*/
static inline void i2s_ll_rx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
{
hw->rx_conf.rx_ws_idle_pol = ws_pol_level;
}
/**
*/
static inlin... | 905 |
pcm2pdm_conv_en = true;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_prescale(i2s_dev_t *hw, bool prescale)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_pcm2pdm_conf, tx_pdm_prescale, prescale);
}
/**
*/
static inline void i2s_ll_tx_set_pdm_hp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale)
{
hw->tx_pcm2pdm... | 905 |
tx_iir_hp_mult12_5 = param;
}
/**
*/
static inline void i2s_ll_tx_enable_pdm_hp_filter(i2s_dev_t *hw, bool enable)
{
hw->tx_pcm2pdm_conf.tx_pdm_hp_bypass = !enable;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_sd_dither(i2s_dev_t *hw, uint32_t dither)
{
hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_dither = dither... | 905 |
tx_pdm_fs;
}
/**
*/
static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw)
{
hw->rx_conf.rx_pdm_en = 1;
hw->rx_conf.rx_tdm_en = 0;
hw->rx_pdm2pcm_conf.rx_pdm2pcm_en = 1;
}
/**
*/
static inline void i2s_ll_rx_set_pdm_dsr(i2s_dev_t *hw, i2s_pdm_dsr_t dsr)
{
hw->rx_pdm2pcm_conf.rx_pdm_sinc_dsr_16_en = ... | 905 |
rx_pdm_hp_bypass = !enable;
}
/**
*/
static inline void i2s_ll_tx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg)
{
hw->tx_conf.tx_pcm_conf = pcm_cfg;
hw->tx_conf.tx_pcm_bypass = !pcm_cfg;
}
/**
*/
static inline void i2s_ll_rx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg)
{
hw->rx_con... | 905 |
rx_bit_order = lsb_order_ena;
}
/**
*/
static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
{
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
*/
static inline void i2s_ll_set_single_data(i2s_dev_t *hw, uint32_t data)
{
hw->conf_single_data.val = data;
}
/**
*/
static in... | 905 |
tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 1 : 2;
} else {
hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 4 : 3;
}
} else {
hw->tx_conf.tx_chan_mod = 0;
}
}
/**
*/
static inline void i2s_ll_tx_pdm_line_mode(i2s_dev_t *hw, i2s_pdm_tx_line_mode_t line_mode)
{
hw->tx... | 905 |
tx_bck_cnt;
}
#ifdef __cplusplus
}
#endif
| 905 |
/*
*/
/
/
// The LL for temperature sensor
#pragma once
#include
#include
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
#include "soc/tsens_struct.h"
#include "soc/lpperi_struct.h"
#include "soc/tsens_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/interrupts.h"
#include "soc/s... | 906 |
ctrl.power_up = enable;
}
/**
*/
static inline void temperature_sensor_ll_bus_clk_enable(bool enable)
{
LPPERI.clk_en.ck_en_lp_tsens = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable i... | 906 |
}
/**
*/
static inline void temperature_sensor_ll_set_range(uint32_t range)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range);
}
/**
*/
__attribute__((always_inline))
static inline uint32_t temperature_sensor_ll_get_raw_value(void)
{
return HAL_FORCE_READ_U32_REG_FIELD(LP_TSENS.ctrl, out);
}
/... | 906 |
wakeup_ctrl.wakeup_over_upper_th;
}
/**
*/
static inline void temperature_sensor_ll_wakeup_enable(bool en)
{
LP_TSENS.wakeup_ctrl.wakeup_en = en;
}
/**
*/
static inline void temperature_sensor_ll_set_th_low_val(uint8_t th_low)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_TSENS.wakeup_ctrl, wakeup_th_low, th_low);
}
... | 906 |
sample_rate, sample_rate, rate);
}
#ifdef __cplusplus
}
#endif
| 906 |
/*
*/
// The LL layer for LEDC register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include "hal/assert.h"
#include "hal/ledc_types.h"
#include "soc/ledc_struct.h"
#include "soc/ledc_reg.h"
#include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst... | 907 |
timer[timer_sel].conf.rst = 1;
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0;
}
/**
*/
static inline void ledc_ll_timer_pause(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
{
hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 1;
}
/**
*/
static inline void ledc_ll_timer_r... | 907 |
timer[timer_sel].conf.tick_sel == 0);
*clk_src = LEDC_SCLK;
}
/**
*/
static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution)
{
hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res = duty_resolution;
}
/**
*/
static inline... | 907 |
channel[channel_num].hpoint.hpoint = hpoint_val;
}
/**
*/
static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val)
{
*hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint;
}
/**
*/
static inline void ledc_ll_set_duty... | 907 |
val;
}
/**
*/
static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num)
{
hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num = range_num;
}
/**
*/
static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_c... | 907 |
channel[channel_num].conf0.sig_out_en = sig_out_en;
}
/**
*/
static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool duty_start)
{
hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start;
}
/**
*/
__attribute__((always_inline))
... | 907 |
val;
uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
*intr_status = (value >> int_en_base) & 0xff;
}
/**
*/
static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num)
{
uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
hw->... | 907 |
/*
*/
#pragma once
#include
#include
#include "soc/systimer_struct.h"
#include "soc/clk_tree_defs.h"
#include "hal/assert.h"
#include "soc/hp_sys_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions ... | 908 |
peri_clk_ctrl21.reg_systimer_clk_src_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL;
}
/**
*/
static inline void systimer_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl2.reg_systimer_apb_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical... | 908 |
etm_en = en;
}
/ Counter /
__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en)
{
if (en) {
dev->conf.val |= 1 conf.val &= ~(1 conf.val |= 1 conf.val &= ~(1 unit_op[counter_id].timer_unit_update = 1;
}
__attribute__((always_inline... | 908 |
hi.timer_unit_value_hi;
}
__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id)
{
dev->unit_load[counter_id].val = 0x01;
}
/ Alarm /
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t a... | 908 |
target_period_mode = 0;
}
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
{
dev->target_conf[alarm_id].target_period_mode = 1;
}
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t al... | 908 |
val |= 1 << alarm_id;
}
#ifdef __cplusplus
}
#endif
| 908 |
/*
*/
// The LL layer for ESP32-P4 LP_Timer register operations
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_system_reg.h"
#include "hal/lp_timer_types.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INL... | 909 |
main_timer_update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.soc_wakeup_int_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_a... | 909 |
/*
*/
// The LL layer for Cache register operations
#pragma once
#include
#include "soc/cache_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32p4/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define CACHE_LL_L2MEM_NON_CACHE_ADDR(addr) ((intpt... | 910 |
/*
*/
/
/
// The LL layer for ESP32P4 eMAC register operations
#pragma once
#include
#include
#include "hal/misc.h"
#include "hal/eth_types.h"
#include "soc/emac_dma_struct.h"
#include "soc/emac_mac_struct.h"
#include "soc/hp_system_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/lp_clkrst_struct... | 911 |
h) */
#define EMAC_LL_DMA_TRANSMIT_FINISH_INTR 0x00000001U
#define EMAC_LL_DMA_TRANSMIT_STOP_INTR 0x00000002U
#define EMAC_LL_DMA_TRANSMIT_BUFF_UNAVAILABLE_INTR 0x00000004U
#define EMAC_LL_DMA_TRANSMIT_TIMEOUT_INTR 0x00000008U
#define EMAC_LL_DMA_RECEIVE_OVERFLOW_INTR ... | 911 |
h) */
#define EMAC_LL_INTR_TRANSMIT_ENABLE 0x00000001U
#define EMAC_LL_INTR_TRANSMIT_STOP_ENABLE 0x00000002U
#define EMAC_LL_INTR_TRANSMIT_BUFF_UNAVAILABLE_ENABLE 0x00000004U
#define EMAC_LL_INTR_TRANSMIT_TIMEOUT_ENABLE 0x00000008U
#define EMAC_LL_INTR_OVERFLOW_ENABLE ... | 911 |
miicsrclk = div_mode;
}
static inline bool emac_ll_is_mii_busy(emac_mac_dev_t *mac_regs)
{
return mac_regs->emacgmiiaddr.miibusy ? true : false;
}
static inline void emac_ll_set_phy_addr(emac_mac_dev_t *mac_regs, uint32_t addr)
{
mac_regs->emacgmiiaddr.miidev = addr;
}
static inline void emac_ll_set_phy_reg(... | 911 |
interframegap = gap;
}
static inline void emac_ll_carrier_sense_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacconfig.disablecrs = !enable;
}
static inline void emac_ll_set_port_speed(emac_mac_dev_t *mac_regs, eth_speed_t speed)
{
if (speed == ETH_SPEED_10M || speed == ETH_SPEED_100M) {
... | 911 |
rxipcoffload = mode;
}
static inline void emac_ll_retry_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacconfig.retry = !enable;
}
static inline void emac_ll_auto_pad_crc_strip_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacconfig.padcrcstrip = enable;
}
static inline void emac_ll... | 911 |
receive_all = enable;
}
static inline void emac_ll_set_src_addr_filter(emac_mac_dev_t *mac_regs, uint32_t filter)
{
mac_regs->gmacff.safe = filter;
}
static inline void emac_ll_sa_inverse_filter_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacff.saif = enable;
}
static inline void emac_ll_set_p... | 911 |
dzpq = !enable;
}
static inline void emac_ll_set_pause_low_threshold(emac_mac_dev_t *mac_regs, uint32_t threshold)
{
mac_regs->gmacfc.plt = threshold;
}
static inline void emac_ll_unicast_pause_frame_detect_enable(emac_mac_dev_t *mac_regs, bool enable)
{
mac_regs->gmacfc.upfd = enable;
}
static inline void e... | 911 |
val;
}
/* emacmiidata */
static inline void emac_ll_set_phy_data(emac_mac_dev_t *mac_regs, uint32_t data)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(mac_regs->emacmiidata, mii_data, data);
}
static inline uint32_t emac_ll_get_phy_data(emac_mac_dev_t *mac_regs)
{
return HAL_FORCE_READ_U32_REG_FIELD(mac_regs->emacmiidata... | 911 |
dis_drop_tcpip_err_fram = !enable;
}
static inline void emac_ll_recv_store_forward_enable(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmaoperation_mode.rx_store_forward = enable;
}
static inline void emac_ll_flush_recv_frame_enable(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmaoperation_mode.di... | 911 |
start_stop_transmission_command = enable;
}
static inline void emac_ll_forward_err_frame_enable(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmaoperation_mode.fwd_err_frame = enable;
}
static inline void emac_ll_forward_undersized_good_frame_enable(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmao... | 911 |
dmaaddralibea = enable;
}
static inline void emac_ll_use_separate_pbl_enable(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmabusmode.use_sep_pbl = enable;
}
static inline void emac_ll_set_rx_dma_pbl(emac_dma_dev_t *dma_regs, uint32_t pbl)
{
dma_regs->dmabusmode.rx_dma_pbl = pbl;
}
static inline void em... | 911 |
alt_desc_size = enable;
}
static inline void emac_ll_set_desc_skip_len(emac_dma_dev_t *dma_regs, uint32_t len)
{
dma_regs->dmabusmode.desc_skip_len = len;
}
static inline void emac_ll_fixed_arbitration_enable(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmabusmode.dma_arb_sch = enable;
}
static inline ... | 911 |
val;
}
/* dmastatus */
__attribute__((always_inline)) static inline uint32_t emac_ll_get_intr_status(emac_dma_dev_t *dma_regs)
{
return dma_regs->dmastatus.val;
}
__attribute__((always_inline)) static inline void emac_ll_clear_corresponding_intr(emac_dma_dev_t *dma_regs, uint32_t bits)
{
dma_regs->dmastatus.v... | 911 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; emac_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void emac_ll_reset_register(int group_id)
{
(void)group_id;
LP_AON_CLKRST.hp_sdmmc_emac_rst_ctrl.rst_en_emac = 1;
LP_AON_CLKRST.hp_sdmmc_emac_rst_ctrl.rst_en_emac = 0;
}
/// use a macro to wrap the function, fo... | 911 |
peri_clk_ctrl00.reg_emac_rmii_clk_src_sel = 0;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_src_sel = 1; // 0-pad_emac_txrx_clk, 1-pad_emac_rx_clk
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_rx_clk_div_num = 0; // 25MHz
HP_SYS_CLKRST.peri_clk_ctrl01.re... | 911 |
sys_gmac_ctrl0.sys_phy_intf_sel = 0x4; // set RMII
HP_SYS_CLKRST.peri_clk_ctrl00.reg_pad_emac_ref_clk_en = 0;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rmii_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rmii_clk_src_sel = 0; // 0-pad_emac_txrx_clk, 1-pad_emac_rx_clk, 2-pad_emac_tx_clk
HP_SYS_CLKRST... | 911 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; emac_ll_clock_enable_rmii_input(__VA_ARGS__)
static inline void emac_ll_clock_rmii_rx_tx_div(void *ext_regs, int div)
{
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_rx_clk_div_num = div;
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_div_num = div;
}
/// use a macro to wrap the fu... | 911 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; emac_ll_clock_enable_rmii_output(__VA_ARGS__)
static inline void emac_ll_pause_frame_enable(void *ext_regs, bool enable)
{
HP_SYSTEM.sys_gmac_ctrl0.sys_phy_intf_sel = enable;
}
#ifdef __cplusplus
}
#endif
| 911 |
/*
*/
// The HAL layer for PMU
#pragma once
#include "soc/soc_caps.h"
#include "hal/pmu_ll.h"
#include "hal/pmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
pmu_dev_t *dev;
} pmu_hal_context_t;
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_w... | 912 |
/*
*/
#include
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
//TODO: IDF-7542
/* Copied from C3 */
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
{
abort();
}
static inline void mpu_ll_set_region_rw(uint32_t addr)
{
abort();
}
static inline void mpu_ll_... | 913 |
/*
*/
/
/
#pragma once
#include
#include
#include "esp_bit_defs.h"
#include "hal/assert.h"
#include "soc/clk_tree_defs.h"
#include "soc/sdmmc_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/lp_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SDMMC_LL_GET_HW(id) (((id) == 0) ? (&... | 914 |
hp_sdmmc_emac_rst_ctrl.rst_en_sdmmc = 1;
LP_AON_CLKRST.hp_sdmmc_emac_rst_ctrl.rst_en_sdmmc = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sdmmc_ll_reset_register(...) (v... | 914 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_select_clk_source(__VA_ARGS__)
/**
*/
static inline void sdmmc_ll_set_clock_div(sdmmc_dev_t *hw, uint32_t div)
{
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_h = div / 2 - 1;
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_n = div - 1;
HP_SYS_CLKRST.pe... | 914 |
reg_sdio_ls_clk_edge_l + 1;
}
/**
*/
static inline void sdmmc_ll_init_phase_delay(sdmmc_dev_t *hw)
{
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_drv_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_slf_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctr... | 914 |
peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x1;
break;
case SDMMC_LL_DELAY_PHASE_2:
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x2;
break;
case SDMMC_LL_DELAY_PHASE_3:
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x3;
... | 914 |
card0 = 0;
hw->clkdiv.clk_divider0 = card_div;
} else if (slot == 1) {
hw->clksrc.card1 = 1;
hw->clkdiv.clk_divider1 = card_div;
} else {
HAL_ASSERT(false);
}
}
/**
*/
static inline uint32_t sdmmc_ll_get_card_clock_div(sdmmc_dev_t *hw, uint32_t slot)
{
uint32_t card_div... | 914 |
data_timeout = timeout_cycles;
}
/**
*/
static inline void sdmmc_ll_set_response_timeout(sdmmc_dev_t *hw, uint32_t timeout_cycles)
{
hw->tmout.response_timeout = timeout_cycles;
}
/**
*/
static inline bool sdmmc_ll_is_card_detected(sdmmc_dev_t *hw, uint32_t slot)
{
return ((hw->cdetect.card_detect_n & BIT(s... | 914 |
block_size = block_size;
}
/**
*/
static inline void sdmmc_ll_set_desc_addr(sdmmc_dev_t *hw, uint32_t desc_addr)
{
hw->dbaddr.dbaddr_reg = desc_addr;
}
/**
*/
static inline void sdmmc_ll_enable_dma(sdmmc_dev_t *hw, bool en)
{
hw->ctrl.dma_enable = en;
hw->ctrl.use_internal_dma = en;
hw->bmod.enable ... | 914 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include "gpspi_flash_ll.h"
#include "spimem_flash_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
... | 915 |
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (8)
typedef union {
gpspi_flash_ll_clock_reg_t gpspi;
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_... | 915 |
/*
*/
/
/
#pragma once
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include
#include
#include
#include "hal/assert.h"
#include "hal/key_mgr_types.h"
#include "soc/keymng_reg.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static in... | 916 |
hp_rst_en2.reg_rst_en_km = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_km = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define key_mgr_ll_reset_register(...) (void)__DECLARE_RCC_AT... | 916 |
/*
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/soc_etm_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void etm_ll_enable_bus... | 917 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; etm_ll_reset_register(__VA_ARGS__)
/**
*/
static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan ch_ena_ad0_set.val = 1 ch_ena_ad1_set.val = 1 ch_ena_ad0_clr.val = 1 ch_ena_ad1_clr.val = 1 ch_ena_ad0.val & (1 ch_ena_ad1.val & (1 channel[chan].evt_... | 917 |
/*
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/gpio_ext_struct.h"
#include "soc/soc_etm_source.h"
#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch))
#define GPIO_LL... | 918 |
etm_chn_event_en = enable;
}
/**
*/
static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
{
int g_p = gpio_num / 4;
int g_idx = gpio_num % 4;
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
reg_val &= ~(0x07 etm_task_pn_cfg[g_p].val = reg_val;
}
... | 918 |
/*
*/
#pragma once
#include
#include
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/hal_utils.h"
#include "hal/gdma_types.h"
#include "hal/gdma_ll.h"
#include "soc/axi_dma_struct.h"
#include "soc/axi_dma_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#define AXI_DMA_LL_GET_HW(id) (((id) == 0... | 919 |
axim_rst_wr_inter = 1;
dev->misc_conf.axim_rst_wr_inter = 0;
}
///////////////////////////////////// RX /////////////////////////////////////////
/**
*/
__attribute__((always_inline))
static inline uint32_t axi_dma_ll_rx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, bool raw)
{
if (raw) {
... | 919 |
intr.st);
}
/**
*/
static inline void axi_dma_ll_rx_enable_owner_check(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in[channel].conf.in_conf1.in_check_owner_chn = enable;
}
/**
*/
static inline void axi_dma_ll_rx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
}
/**
*/
stat... | 919 |
conf.in_link2.inlink_addr_chn = addr;
}
/**
*/
__attribute__((always_inline))
static inline void axi_dma_ll_rx_start(axi_dma_dev_t *dev, uint32_t channel)
{
dev->in[channel].conf.in_link1.inlink_start_chn = 1;
}
/**
*/
__attribute__((always_inline))
static inline void axi_dma_ll_rx_stop(axi_dma_dev_t *dev, uint... | 919 |
conf.in_suc_eof_des_addr.val;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t axi_dma_ll_rx_get_error_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
{
return dev->in[channel].conf.in_err_eof_des_addr.val;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t axi_dma_ll_rx_get_prefet... | 919 |
conf.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
dev->in[channel].conf.in_conf0.mem_trans_en_chn = false;
}
/**
*/
static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in[channel].conf.in_conf0.in_etm_en_chn = enable;
}
//////////////////////... | 919 |
intr.clr.val = mask;
}
/**
*/
static inline volatile void *axi_dma_ll_tx_get_interrupt_status_reg(axi_dma_dev_t *dev, uint32_t channel)
{
return (volatile void *)(&dev->out[channel].intr.st);
}
/**
*/
static inline void axi_dma_ll_tx_enable_owner_check(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
de... | 919 |
conf.out_conf0.out_auto_wrback_chn = enable;
}
/**
*/
__attribute__((always_inline))
static inline void axi_dma_ll_tx_reset_channel(axi_dma_dev_t *dev, uint32_t channel)
{
dev->out[channel].conf.out_conf0.out_rst_chn = 1;
dev->out[channel].conf.out_conf0.out_rst_chn = 0;
}
/**
*/
static inline void axi_dma_... | 919 |
conf.out_link1.outlink_stop_chn = 1;
}
/**
*/
__attribute__((always_inline))
static inline void axi_dma_ll_tx_restart(axi_dma_dev_t *dev, uint32_t channel)
{
dev->out[channel].conf.out_link1.outlink_restart_chn = 1;
}
/**
*/
static inline bool axi_dma_ll_tx_is_desc_fsm_idle(axi_dma_dev_t *dev, uint32_t channel)... | 919 |
conf.out_peri_sel.peri_out_sel_chn = periph_id;
}
/**
*/
static inline void axi_dma_ll_tx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
{
dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
}
/**
*/
static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev,... | 919 |
crc.out_crc_init_data.out_crc_init_data_chn = value;
}
/**
*/
static inline uint32_t axi_dma_ll_tx_crc_get_result(axi_dma_dev_t *dev, uint32_t channel)
{
return dev->out[channel].crc.out_crc_final_result.out_crc_final_result_chn;
}
/**
*/
static inline void axi_dma_ll_tx_crc_latch_config(axi_dma_dev_t *dev, uin... | 919 |
crc.tx_crc_data_en_wr_data, tx_crc_data_en_wr_data_chn, data_mask);
}
///////////////////////////////////// CRC-RX /////////////////////////////////////////
/**
*/
static inline void axi_dma_ll_rx_crc_clear(axi_dma_dev_t *dev, uint32_t channel)
{
dev->in[channel].crc.in_crc_clear.in_crc_clear_chn_reg = 1;
de... | 919 |
crc.rx_crc_width.rx_crc_latch_flag_chn = 1;
dev->in[channel].crc.rx_crc_width.rx_crc_latch_flag_chn = 0;
}
/**
*/
static inline void axi_dma_ll_rx_crc_set_lfsr_data_mask(axi_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
uint32_t lfsr_mask, uint32_t dat... | 919 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/misc.h"
#include "hal/wdt_types.h"
#include "soc/rtc_cntl_periph.h"
#include "soc/ef... | 920 |
wdt_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
{
hw->config0.wdt_en = 0;
}
/**
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
{
return (hw->config0.wdt_en) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void
lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_sta... | 920 |
wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->config0.wdt_stg3 = WDT_ST... | 920 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.