text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
1 : 0;
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{
hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable)
{
hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
}
/**
... | 920 |
lp_wdt_int_ena = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
{
return (hw->int_st.lp_wdt_int_st) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw)
{
hw->int_clr.lp_wdt_int_clr = 1;
}
#ifdef __cplusplus
}
#endif
| 920 |
/*
*/
#pragma once
#include
#include
#include "soc/periph_defs.h"
#include "soc/soc.h"
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
{
switch (periph) {
... | 921 |
= 0;
}
#ifdef __cplusplus
}
#endif
| 921 |
/*
*/
#pragma once
#include
#include
#include "hal/assert.h"
#include "soc/ecdsa_reg.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/ecdsa_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
ECDSA_PARAM_R,
ECDSA_PARAM_S,
ECDSA_PARAM_Z,
ECDSA_PARAM_QAX,
ECDSA_PARAM_QAY... | 922 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; ecdsa_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void ecdsa_ll_reset_register(void)
{
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ecdsa = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ecdsa = 0;
}
/**
*/
static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
{
... | 922 |
/*
*/
#pragma once
#include
#include
#include "hal/assert.h"
#include "hal/ecc_types.h"
#include "soc/ecc_mult_reg.h"
#include "soc/hp_sys_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ECC_PARAM_PX = 0x0,
ECC_PARAM_PY,
ECC_PARAM_K,
ECC_PARAM_QX,
ECC_PARAM_QY,
ECC_P... | 923 |
hp_rst_en2.reg_rst_en_ecdsa = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ecc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; ecc_ll_reset_register(__VA_ARGS__)
sta... | 923 |
/*
*/
/
/
// The LL layer for ESP32-P4 PCNT register operations
#pragma once
#include
#include
#include
#include "soc/pcnt_struct.h"
#include "hal/pcnt_types.h"
#include "hal/misc.h"
#include "soc/hp_sys_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PCNT_LL_GET_HW(num) (((num) == 0) ? ... | 924 |
conf0.ch0_hctrl_mode = high_act;
hw->conf_unit[unit].conf0.ch0_lctrl_mode = low_act;
} else {
hw->conf_unit[unit].conf0.ch1_hctrl_mode = high_act;
hw->conf_unit[unit].conf0.ch1_lctrl_mode = low_act;
}
}
/**
*/
__attribute__((always_inline))
static inline int pcnt_ll_get_count(pcnt_dev_... | 924 |
val |= unit_mask;
} else {
hw->int_ena.val &= ~unit_mask;
}
}
/**
*/
__attribute__((always_inline))
static inline uint32_t pcnt_ll_get_intr_status(pcnt_dev_t *hw)
{
return hw->int_st.val;
}
/**
*/
__attribute__((always_inline))
static inline void pcnt_ll_clear_intr_status(pcnt_dev_t *hw, uint32_... | 924 |
conf0.thr_thres0_en = enable;
} else {
hw->conf_unit[unit].conf0.thr_thres1_en = enable;
}
}
/**
*/
static inline void pcnt_ll_disable_all_events(pcnt_dev_t *hw, uint32_t unit)
{
hw->conf_unit[unit].conf0.val &= ~(PCNT_LL_WATCH_EVENT_MASK conf_unit[unit].conf2.val;
conf2_reg.cnt_h_lim = value... | 924 |
val;
}
/**
*/
static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_h_lim ;
return value;
}
/**
*/
static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint... | 924 |
val & 0x03);
}
/**
*/
__attribute__((always_inline))
static inline uint32_t pcnt_ll_get_event_status(pcnt_dev_t *hw, uint32_t unit)
{
return hw->status_unit[unit].val >> 2;
}
/**
*/
static inline void pcnt_ll_set_glitch_filter_thres(pcnt_dev_t *hw, uint32_t unit, uint32_t filter_val)
{
hw->conf_unit[unit].c... | 924 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; pcnt_ll_enable_bus_clock(__VA_ARGS__)
/**
*/
static inline void pcnt_ll_reset_register(int group_id)
{
(void)group_id;
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_pcnt = 1;
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_pcnt = 0;
}
/// use a macro to wrap the function, force the caller t... | 924 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include // For MIN/MAX
#include
#include
#include "hal/misc.h"
//TODO: IDF-7499
#ifdef __cplusplus
extern "C" {
#endif
//NO... | 925 |
rx_seg_trans_clr_en = 1;
// dev->dma_conf.dma_seg_trans_en = 0;
abort(); //TODO: IDF-7499
}
/**
*/
static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
{
return (dev->cmd.usr == 0);
}
/**
*/
static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len... | 925 |
hold_pol = 1;
dev->cmd.update = 1;
while (dev->cmd.update);
dev->cmd.usr = 1;
}
/**
*/
static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev)
{
// Not supported on GPSPI
}
/**
*/
static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
{
dev->ctrl.hold_pol = pol_val... | 925 |
val;
typeof (dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the ... | 925 |
val = (*clock_val).val;
}
/**
*/
static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_miso = bitlen > 0;
if (bitlen) {
dev->ms_dlen.ms_data_bitlen = bitlen - 1;
}
}
/**
*/
static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bit... | 925 |
usr_addr = bitlen ? 1 : 0;
}
/**
*/
static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
// // The blank region should be all ones
// uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen);
// dev->addr = (addr addr = addr;
abort(); //TODO: IDF... | 925 |
1 : 0);
dev->user1.cs_setup_time = cs_setup_time - 1;
}
/**
*/
static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
{
uint32_t div_parameter;
// See comments of `clock` in `spi_struct.h`
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((... | 925 |
/*
*/
/
/
// The LL layer for ESP32-P4 GPIO register operations
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/io_mux_struct.h"
#include "soc/hp_system_struct.h"
#include "soc/lp_iomux_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#i... | 926 |
val : hw->enable1.val) & bit_mask) >> bit_shift;
*od = hw->pin[gpio_num].pad_driver;
*drv = IOMUX.gpio[gpio_num].fun_drv;
*fun_sel = IOMUX.gpio[gpio_num].mcu_sel;
*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
*slp_sel = IOMUX.gpio[gpio_num].slp_sel;
}
/**
*/
static inline void gpio_ll_pullup... | 926 |
If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
// One more noticable point is P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately.
// We only consider the default connection he... | 926 |
New feature! Need to fix this function later.
*status = hw->intr_0.int_0;
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
(void)core_id; // TODO: IDF-7995 There are 4 interrupt sources for GPIO on P4. New feature! ... | 926 |
int_ena = 0; //disable GPIO intr
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].fun_ie = 0;
}
/**
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gp... | 926 |
gpio_o_hys_ctrl1.reg_gpio_0_hys_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
if (gpio_num enable_w1tc.enable_w1tc = (0x1 enable1_w1tc.enable1_w1tc = (0x1 func_out_sel_cfg[g... | 926 |
in1_data_next >> (gpio_num - 32)) & 0x1;
}
}
/**
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 1;
}
/**
*/
static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 0;
}
/**
*/
... | 926 |
gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
}
/**
*/
__attribute__((always_inline))
static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
{
uint64_t bit_mask = 1ULL > SOC_RTCIO_PIN_COUNT));
} else {
// GPIO 48... | 926 |
conf0.usb_pad_enable = 0;
} else if (pin_name == IO_MUX_GPIO26_REG || pin_name == IO_MUX_GPIO27_REG) {
USB_WRAP.otg_conf.usb_pad_enable = 0;
}
PIN_FUNC_SELECT(pin_name, func);
}
/**
*/
static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shif... | 926 |
usb_pad_enable = 0;
}
IOMUX.gpio[gpio_num].mcu_sel = func;
}
/**
*/
static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_func_sel(hw, gpio_num,... | 926 |
val = hw->func_in_sel_cfg[in_sig_idx].val;
return (reg.sig_in_sel ? reg.in_sel : -1);
}
/**
*/
static inline void gpio_ll_force_hold_all(void)
{
// WT flag, it gets self-cleared after the configuration is done
PMU.imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
}
/**
*/
static inline void gpio_ll_force... | 926 |
gpio[gpio_num].mcu_wpd = 1;
}
/**
*/
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_wpd = 0;
}
/**
*/
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_ie = 0;
}
/**
*/
static inline ... | 926 |
/*
*/
#pragma once
#include "freertos/FreeRTOS.h"
#include "esp_types.h"
#include "esp_intr_alloc.h"
#include "esp_err.h"
#include "driver/gpio.h"
#include "hal/twai_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Default initializers and flags */
/** @cond */ //Doxy command to hide preprocessor definition... | 927 |
intr_flags = ESP_INTR_FLAG_LEVEL1}
/**
*/
#define TWAI_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) TWAI_GENERAL_CONFIG_DEFAULT_V2(0, tx_io_num, rx_io_num, op_mode)
/**
*/
#define TWAI_ALERT_TX_IDLE 0x00000001 /**< Alert(1): No more messages to transmit */
#define TWAI_ALERT_TX_SUCCESS ... | 927 |
TWAI controller can no longer influence bus */
#define TWAI_ALERT_RX_FIFO_OVERRUN 0x00004000 /**< Alert(16384): An RX FIFO overrun has occurred */
#define TWAI_ALERT_TX_RETRIED 0x00008000 /**< Alert(32768): An message transmission was cancelled and retried due to an errata workaround */
#defin... | 927 |
The TWAI controller will not participate in any TWAI bus activities */
TWAI_STATE_RUNNING, /**< Running state. The TWAI controller can transmit and receive messages */
TWAI_STATE_BUS_OFF, /**< Bus-off state. The TWAI controller cannot participate in bus activities until it has recovered... | 927 |
Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused) */
int intr_flags; /**< Interrupt flags to set the priority of the driver's ISR. Note that to use the ESP_INTR_FLAG_IRAM, the CONFIG_TWAI_ISR_IN_IRAM option should be enabled first. */
} twai_general_config_t;
/**
*/
typedef ... | 927 |
/*
*/
#ifndef _DRIVER_I2C_H_
#define _DRIVER_I2C_H_
#ifdef __cplusplus
extern "C" {
#endif
#include
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "driver/gpio.h"
#include "soc/soc_caps.h"
... | 928 |
/*
*/
#pragma once
/**
*/
int test_tp_print_to_scope(float *data, unsigned char channel_num);
/**
*/
esp_err_t test_tp_scope_debug_init(uint8_t uart_num, int tx_io_num, int rx_io_num, int baud_rate);
| 929 |
/*
*/
#pragma once
#include
#include
#include
/**
*/
void test_fill_random_to_buffers_dualboard(uint32_t seed, uint8_t *dut0_buffer, uint8_t *dut1_buffer, size_t buffer_size);
/**
*/
void test_fill_random_to_buffer(uint32_t seed, uint8_t *buffer, size_t buffer_size);
/**
*/
void test_prepare_buffer_pool(size... | 930 |
/*
*/
#ifndef _TEST_COMMON_SPI_H_
#define _TEST_COMMON_SPI_H_
#include
#include
#include
#include
#include
#include "freertos/FreeRTOS.h"
#include "freertos/ringbuf.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/task.h"
#include "unity.h"
#include "param_test.h"
#include "soc/io_m... | 931 |
5*2)
#define ESP_SPI_SLAVE_TV (12.5*3.5)
#define WIRE_DELAY 12.5
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4
#define SLAVE_IOMUX_PIN_MISO -1
#define SLAVE_IOMUX_PIN_MOSI -1
#define SLAVE_IOMUX_PIN_SCLK -1
#define SLAVE_IOMUX_PIN_CS -1
#def... | 931 |
5ns
#define TV_WITH_ESP_SLAVE_GPIO (TV_INT_CONNECT_GPIO+WIRE_DELAY)
#define TV_WITH_ESP_SLAVE (TV_INT_CONNECT+WIRE_DELAY)
//currently ESP32 slave only supports up to 20MHz, but 40MHz on the same board
#define ESP_SPI_SLAVE_MAX_FREQ 20 * 1000 * 1000
#define ESP_SPI_SLAVE_MAX_FREQ_SYNC 40 * 1000 * 1000
#def... | 931 |
void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, uint8_t cs_num);
#endif //_TEST_COMMON_SPI_H_
| 931 |
/*
*/
/*
#define PGROUP_NAME_LEN 20 ///< name length of parameter group
#define PGROUP_NAME(name) PGROUP_##name ///< param group name
#define PTEST_MASTER_NAME(name) PTEST_MASTER_##name ///< test function name of master
#define PTEST_SLAVE_NAME(name) PTEST_SLAVE_##name ///< test function name ... | 932 |
void (*loop)(const void* pset, void* context); ///< Function execute each param set
} ptest_func_t;
/**
*/
void test_serializer(const param_group_t *param_group, const ptest_func_t* test_func);
#define PARAM_GROUP_DECLARE_TYPE(group_name, pset_type, pgroup) \
static const param_group_t PGROUP_NAME(pgroup) =... | 932 |
/*
*/
#pragma once
#include
#include
/** Context used by the ``esp_serial_slave_link`` component.
*/
struct essl_dev_t {
void *args;
esp_err_t (*init)(void *ctx, uint32_t wait_ms);
esp_err_t (*wait_for_ready)(void *ctx, uint32_t wait_ms);
esp_err_t (*update_tx_buffer_num)(void *ctx, uint32_t wa... | 933 |
/*
*/
#pragma once
// NOTE: From the view of master
#define CMD_HD_WRBUF_REG 0x01
#define CMD_HD_RDBUF_REG 0x02
#define CMD_HD_WRDMA_REG 0x03
#define CMD_HD_RDDMA_REG 0x04
#define CMD_HD_ONEBIT_MODE 0x00
#define CMD_HD_DOUT_MODE 0x10
#define CMD_HD_QOUT_MODE 0x20
#define CMD_HD_DIO_MODE 0x50
... | 934 |
/*
*/
#pragma once
// NOTE: From the view of master
#define CMD_HD_WRBUF_REG 0x01
#define CMD_HD_RDBUF_REG 0x02
#define CMD_HD_WRDMA_REG 0x03
#define CMD_HD_RDDMA_REG 0x04
#define CMD_HD_ONEBIT_MODE 0x00
#define CMD_HD_DOUT_MODE 0x10
#define CMD_HD_QOUT_MODE 0x20
#define CMD_HD_DIO_MODE 0x50
... | 935 |
/*
*/
#pragma once
// NOTE: From the view of master
#define CMD_HD_WRBUF_REG 0x01
#define CMD_HD_RDBUF_REG 0x02
#define CMD_HD_WRDMA_REG 0x03
#define CMD_HD_RDDMA_REG 0x04
#define CMD_HD_ONEBIT_MODE 0x00
#define CMD_HD_DOUT_MODE 0x10
#define CMD_HD_QOUT_MODE 0x20
#define CMD_HD_DIO_MODE 0x50
... | 936 |
/*
*/
#pragma once
// NOTE: From the view of master
#define CMD_HD_WRBUF_REG 0x01
#define CMD_HD_RDBUF_REG 0x02
#define CMD_HD_WRDMA_REG 0x03
#define CMD_HD_RDDMA_REG 0x04
#define CMD_HD_ONEBIT_MODE 0x00
#define CMD_HD_DOUT_MODE 0x10
#define CMD_HD_QOUT_MODE 0x20
#define CMD_HD_DIO_MODE 0x50
... | 937 |
/*
*/
#pragma once
/**
*/
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
//interrupts
uint32_t new_packet_intr_mask;
} essl_sdio_def_t;
/// Definitions of ESP32 SDIO Slave hardware
extern essl_sdio_def_t ESSL_SDIO_DEF_ESP32;
/// Definitions of ESP32C6 SDIO Slave hardware
extern essl_sd... | 938 |
/*
*/
#pragma once
#include "esp_err.h"
#include "driver/spi_master.h"
#include "esp_serial_slave_link/essl.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Configuration of ESSL SPI device
typedef struct {
spi_device_handle_t *spi; ///< Pointer to SPI device handle.
uint32_t tx_buf_size... | 939 |
//
// * You can use the ``essl_spi_init_dev`` and ``essl_spi_deinit_dev`` together with APIs in ``essl.h`` to communicate
// with ESP SPI Slaves in Half Duplex DMA Append Mode. See example for SPI SLAVE HALFDUPLEX APPEND MODE.
// * You can also use the following APIs to create your own logic.
///////////////////////... | 939 |
/*
*/
#pragma once
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
struct essl_dev_t;
/// Handle of an ESSL device
typedef struct essl_dev_t *essl_handle_t;
/**
*/
esp_err_t essl_init(essl_handle_t handle, uint32_t wait_ms);
/** Wait for interrupt of an ESSL slave device.
*/
esp_err_t essl_wait_for... | 940 |
*/
esp_err_t essl_send_packet(essl_handle_t handle, const void *start, size_t length, uint32_t wait_ms);
/** Get a packet from ESSL slave.
*/
esp_err_t essl_get_packet(essl_handle_t handle, void *out_data, size_t size, size_t *out_length, uint32_t wait_ms);
/** Write general purpose R/W registers (8-bit) of ESSL s... | 940 |
The slave only sends interrupt on the line when there is a bit both the raw status and the enable are set.
*/
esp_err_t essl_set_intr_ena(essl_handle_t handle, uint32_t ena_mask, uint32_t wait_ms);
/** Get interrupt enable bits of ESSL slave.
*/
esp_err_t essl_get_intr_ena(essl_handle_t handle, uint32_t *ena_mask_o... | 940 |
/*
*/
// ESP SDIO slave link used by the ESP host to communicate with ESP SDIO slave.
#pragma once
#include "esp_err.h"
#include "driver/sdmmc_types.h"
#include "driver/sdmmc_host.h"
#include "esp_serial_slave_link/essl.h"
#include "essl_sdio_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Configuration for t... | 941 |
/*
*/
#pragma once
#include
#include
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
#define IR_TOOLS_FLAGS_PROTO_EXT (1 << 0) /*!< Enable Extended IR protocol */
#define IR_TOOLS_FLAGS_INVERSE (1 << 1) /*!< Inverse the IR signal, i.e. take high level as low, and vice versa */
/**
typedef void *ir... | 942 |
< Size of the internal buffer used by IR builder */
ir_dev_t dev_hdl; /*!< IR device handle */
uint32_t flags; /*!< Flags for IR builder, different flags will enable different features */
} ir_builder_config_t;
/**
typedef struct {
ir_dev_t dev_hdl; /*!< IR device handle */
uint32_t flags; ... | 942 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
#define NEC_LEADING_CODE_HIGH_US (9000)
#define NEC_LEADING_CODE_LOW_US (4500)
#define NEC_PAYLOAD_ONE_HIGH_US (560)
#define NEC_PAYLOAD_ONE_LOW_US (1690)
#define NEC_PAYLOAD_ZERO_HIGH_US (560)
#define NEC_PAYLOAD_ZERO_LOW_US (560)
#define NEC_REPEAT_COD... | 943 |
/*
*/
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SAMPLE_RATE (48000)
#define SAMPLE_BITS (16)
#if CONFIG_IDF_TARGET_ESP32
#define MASTER_MCK_IO 0
#define MASTER_BCK_IO 4
#define MASTER_WS_IO 5
#define SLAVE_BCK_IO 21
#define SLAVE_WS_IO 22
#define DATA_IN_IO 19
#define DATA_OUT_IO... | 944 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#if SOC_TOUCH_SENSOR_SUPPORTED
#include "driver/touch_sensor.h"
#endif
| 946 |
/*
*/
#pragma once
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "hal/touch_sensor_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
esp_err_t touch_pad_init(void);
/**
*/
esp_err_t touch_pad_deinit(void);
/**
*/
esp_err_t touch_pad_io_init(touch_pad_t touch_num);
/**
*/
esp_err_t touch_pad... | 947 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "driver/touch_sensor_common.h"
/**
*/
esp_err_t touch_pad_config(touch_pad_t touch_num, uint16_t threshold);
/**
*/
esp_err_t touch_pad_read(touch_pad_t touch_num, uint16_t *touch_value);
/**
*/
esp_err_t touch_pad_read_filtered(touch_pad_t to... | 948 |
/*
*/
#pragma once
#include "driver/touch_sensor_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
esp_err_t touch_pad_fsm_start(void);
/**
*/
esp_err_t touch_pad_fsm_stop(void);
/**
*/
esp_err_t touch_pad_sw_start(void);
/**
*/
esp_err_t touch_pad_set_charge_discharge_times(uint16_t charge_discharge_... | 949 |
/*
*/
#pragma once
#include "driver/touch_sensor_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
esp_err_t touch_pad_fsm_start(void);
/**
*/
esp_err_t touch_pad_fsm_stop(void);
/**
*/
esp_err_t touch_pad_sw_start(void);
/**
*/
esp_err_t touch_pad_set_charge_discharge_times(uint16_t charge_discharge_... | 950 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_err.h"
/**
*/
esp_err_t adc1_dma_mode_acquire(void);
/**
*/
esp_err_t adc1_rtc_mode_acquire(void);
/**
*/
esp_err_t adc1_lock_release(void);
#ifdef __cplusplus
}
#endif
| 951 |
/*
*/
#pragma once
#include "sdkconfig.h"
#include "esp_err.h"
#include "hal/adc_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_IDF_TARGET_ESP32
/**
*/
typedef enum {
ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal */
ADC_I2S_DATA_SRC_ADC = 1, /*!< I2S data from ADC */... | 952 |
/*
*/
/*
This file contains Deprecated ADC APIs
*/
#pragma once
#include "sdkconfig.h"
#include "esp_err.h"
#include "driver/gpio.h"
#include "driver/adc_types_legacy.h"
#include "hal/adc_types.h"
#if !CONFIG_ADC_SUPPRESS_DEPRECATE_WARN
#warning "legacy adc driver is deprecated, please migrate to use ... | 953 |
/*
*/
#pragma once
#include
#include
#include
#include
#include "sdkconfig.h"
#include "hal/dac_types.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include "hal/adc_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
DAC_CW_SCALE_1 = 0x0, /*!< 1/1. Default. */
DAC_CW_SCALE_2 = 0x1, /*... | 954 |
See ``dac_digi_convert_mode_t``. */
uint32_t interval; /*!<The number of interval clock cycles for the DAC digital controller to output voltage.
The unit is the divided clock. Range: 1 ~ 4095.
Expression: `dac_output_freq`... | 954 |
*/
dac_cw_phase_t phase; /*!< Set the phase of the cosine wave generator output. */
uint32_t freq; /*!< Set frequency of cosine wave generator output. Range: 130(130Hz) ~ 55000(100KHz). */
int8_t offset; /*!< Set the voltage value of the DC component of the cosine wave generator output.... | 954 |
/*
*/
#pragma once
#include
#include "esp_err.h"
#include "sdkconfig.h"
#include "driver/gpio.h"
#include "driver/dac_types_legacy.h"
#if !CONFIG_DAC_SUPPRESS_DEPRECATE_WARN
#warning "The legacy DAC driver is deprecated, please use `driver/dac_oneshot.h`, `driver/dac_cosine.h` or `driver/dac_continuous.h` instead"... | 955 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "hal/timer_types.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
TIMER_GROUP_0 = 0, /*! 1
TIMER_GROUP_1 = 1, /*! 1
TIMER_1 = 1, /*! 1
TIMER_INTR_T1... | 956 |
< Disable timer alarm*/
TIMER_ALARM_EN = 1, /*!< Enable timer alarm*/
TIMER_ALARM_MAX
} timer_alarm_t;
/**
*/
typedef enum {
TIMER_INTR_LEVEL = 0, /*!< Interrupt mode: level mode*/
TIMER_INTR_MAX
} timer_intr_mode_t;
/**
*/
typedef enum {
TIMER_AUTORELOAD_DIS = 0, /*!< Disable auto-reload: hard... | 956 |
< Counter direction */
timer_autoreload_t auto_reload; /*!< Timer auto-reload */
timer_src_clk_t clk_src; /*!< Selects source clock. */
uint32_t divider; /*!< Counter clock divider */
} timer_config_t;
#ifdef __cplusplus
}
#endif
| 956 |
/*
*/
#pragma once
#include
#include
#include "esp_err.h"
#include "driver/mcpwm_types_legacy.h"
#if !CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN
#warning "legacy MCPWM driver is deprecated, please migrate to the new driver (include driver/mcpwm_prelude.h)"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
esp_err... | 957 |
/*
*/
#pragma once
#include "esp_intr_alloc.h"
#include "soc/soc_caps.h"
#include "hal/pcnt_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PCNT_PIN_NOT_USED (-1) /*! 4
PCNT_UNIT_4, /*! decrease, decrease -> increase) */
#define PCNT_MODE_DISABLE PCNT_CHANNEL_LEVEL_ACTION_HOLD /*!< Control mode... | 958 |
< Control signal input GPIO number, a negative value will be ignored */
pcnt_ctrl_mode_t lctrl_mode; /*!< PCNT low control mode */
pcnt_ctrl_mode_t hctrl_mode; /*!< PCNT high control mode */
pcnt_count_mode_t pos_mode; /*!< PCNT positive edge count mode */
pcnt_count_mode_t neg_mode; /*!< PCNT negativ... | 958 |
/*
*/
#pragma once
#include
#include "sdkconfig.h"
#include "esp_err.h"
#include "driver/temp_sensor_types_legacy.h"
#if !CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN
#warning "legacy temperature sensor driver is deprecated, please migrate to driver/temperature_sensor.h"
#endif
#ifdef __cplusplus
extern "C" {
#endi... | 959 |
/*
*/
/**
*/
#pragma once
#include "esp_types.h"
#include "esp_err.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "driver/i2s_types_legacy.h"
#if SOC_I2S_SUPPORTS_ADC
#include "driver/adc.h"
#endif
#if !CONFIG_I2S_SUPPRESS_DEPRECATE_WARN
#warning "This set of I2S APIs has been deprecated... | 960 |
/*
*/
#pragma once
#include
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
TSENS_DAC_L0 = 0, /*!< offset = -2, measure range: 50℃ ~ 125℃, error < 3℃. */
TSENS_DAC_L1, /*!< offset = -1, measure range: 20℃ ~ 100℃, error < 2℃. */
TSENS_DAC_L2, /*!< offset = 0, measure... | 961 |
/*
*/
#pragma once
#include
#include
#include "sdkconfig.h"
#include "esp_err.h"
#include "freertos/FreeRTOS.h"
#include "freertos/ringbuf.h"
#include "driver/rmt_types_legacy.h"
#if !CONFIG_RMT_SUPPRESS_DEPRECATE_WARN
#warning "The legacy RMT driver is deprecated, please use driver/rmt_tx.h and/or driver/rmt_rx.... | 962 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "driver/gpio.h" // for gpio_num_t type define
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
SIGMADELTA_PORT_0, /*! 4
SIGMADELTA_CHANNEL_4, /*!< Sigma-delta channel 4 */
SIGMADELTA_CHANNEL_5, /*!< Sigma-delta channe... | 963 |
/*
*/
/**
*/
#pragma once
#include "hal/i2s_types.h"
#include "driver/i2s_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/ Deprecated Types /
#define I2S_PIN_NO_CHANGE (-1) /*! 0, then the clock output for i2s is fixed and equal to the fixed_mclk value. If fixed_mclk set, mclk_multiple won't take effect */
i2... | 964 |
*/
bool left_align; /*!< Set to enable left alignment */
bool big_edin; /*!< Set to enable big endian */
bool bit_order_msb; /*!< Set to enable msb order */
bool skip_msk; ... | 964 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "driver/gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RMT_CHANNEL_FLAGS_AWARE_DFS (1 4
RMT_CHANNEL_4, /*!< RMT channel number 4 */
RMT_CHANNEL_5, /*!< RMT channel number 5 */
RMT_CHANNEL_6, /*!< ... | 965 |
< RMT TX mode */
RMT_MODE_RX, /*!< RMT RX mode */
RMT_MODE_MAX
} rmt_mode_t;
/**
typedef enum {
RMT_IDLE_LEVEL_LOW, /*!< RMT TX idle level: low Level */
RMT_IDLE_LEVEL_HIGH, /*!< RMT TX idle level: high Level */
RMT_IDLE_LEVEL_MAX,
} rmt_idle_level_t;
/**
*/
typedef enum {
RMT_CARRIER_LEVEL_... | 965 |
< Level of the RMT output, when the carrier is applied */
rmt_idle_level_t idle_level; /*!< RMT idle level */
uint8_t carrier_duty_percent; /*!< RMT carrier duty (%) */
uint32_t loop_count; /*!< Maximum loop count, only take effect for chips that is capable of `SOC_RMT_SUPPORT_TX_LO... | 965 |
< RMT carrier duty (%) */
rmt_carrier_level_t carrier_level; /*!< The level to remove the carrier */
#endif
} rmt_rx_config_t;
/**
*/
typedef struct {
rmt_mode_t rmt_mode; /*!< RMT mode: transmitter or receiver */
rmt_channel_t channel; /*!< RMT channel */
gpio_num_t gpio_num; /*!< RMT GPIO number... | 965 |
gpio_num = gpio, \
.clk_div = RMT_DEFAULT_CLK_DIV, \
.mem_block_num = 1, \
.flags = 0, \
.tx_config = { \
.carrier_freq_hz = 38000, \... | 965 |
clk_div = RMT_DEFAULT_CLK_DIV, \
.mem_block_num = 1, \
.flags = 0, \
.rx_config = { \
.idle_threshold = 12000, \
.filter_ticks_thresh = 100, \
.filter_en = true... | 965 |
/*
*/
#pragma once
#include
#include
#include "sdkconfig.h"
#include "esp_err.h"
#include "driver/timer_types_legacy.h"
#if !CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN
#warning "legacy timer group driver is deprecated, please migrate to driver/gptimer.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
esp_err... | 966 |
*/
esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer_config_t *config);
/** @brief Deinitializes the timer.
*/
esp_err_t timer_deinit(timer_group_t group_num, timer_idx_t timer_num);
/** @brief Get timer configure value.
*/
esp_err_t timer_get_config(timer_group_t group_num, timer_i... | 966 |
/*
*/
#pragma once
#warning driver/rtc_cntl.h header is no longer used, and will be removed in future versions.
#include "esp_private/rtc_ctrl.h"
| 967 |
/*
*/
#pragma once
#include "hal/adc_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
#if CONFIG_IDF_TARGET_ESP32
ADC_WIDTH_BIT_9 = 9, /*!< ADC capture width is 9Bit. */
ADC_WIDTH_BIT_10 = 10, /*!< ADC capture width is 10Bit. */
ADC_WIDTH_BIT_11 = 11, /*!< ADC capture width is 11B... | 968 |
< ADC1 channel 5 is GPIO33 */
ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO34 */
ADC1_CHANNEL_7, /*!< ADC1 channel 7 is GPIO35 */
ADC1_CHANNEL_MAX,
} adc1_channel_t;
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
typedef enum {
ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO1 */
... | 968 |
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