text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define MODEM_CLKRST_DATE 0x0FFFFFFF
#define MODEM_CLKRST_DATE_M ((MODEM_CLKRST_DATE_V)<<(MODEM_CLKRST_DATE_S))
#define MODEM_CLKRST_DATE_V 0xFFFFFFF
#define MODEM_CLKRST_DATE_S 0
#ifdef __cplusplus
}
#endif
| 1,021 |
/*
*/
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
#define IS_01XX(v) (((v)&0x0c)==0x04)
/*Download Boot, USB/SPI(or SDIO_V2)/UART... | 1,023 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x1E)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x1F)
#ifdef __cplusplus
}
#endif
| 1,024 |
/*
*/
#ifndef _SOC_DPORT_REG_H_
#define _SOC_DPORT_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#ifndef __ASSEMBLER__
#include "dport_access.h"
#endif
#ifdef __cplusplus
}
#endif
#endif /*_SOC_DPORT_REG_H_ */
| 1,026 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct syscon_dev_s{
union {
struct {
uint32_t pre_div : 10; /*reg_pre_div_cnt*/
uint32_t clk_320m_en : 1; /*reg_clk_320m_en*/
uint32_t... | 1,027 |
*/
};
uint32_t val;
} clk_out_en;
uint32_t wifi_bb_cfg;
uint32_t wifi_bb_cfg_2;
uint32_t wifi_clk_en;
uint32_t wifi_rst_en;
union {
struct {
uint32_t peri_io_swap : 8; /*reg_peri_io_swap*/
uint32_t reserved8 ... | 1,027 |
*/
};
uint32_t val;
} flash_ace1_attr;
union {
struct {
uint32_t flash_ace2_attr : 2; /*reg_flash_ace2_attr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} flash_ace2_attr;
union {
... | 1,027 |
*/
};
uint32_t val;
} flash_ace1_size;
union {
struct {
uint32_t flash_ace2_size : 13; /*reg_flash_ace2_size*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} flash_ace2_size;
union {
... | 1,027 |
*/
};
uint32_t val;
} spi_mem_pms_ctrl;
uint32_t spi_mem_reject_addr;
union {
struct {
uint32_t sdio_win_access_en : 1; /*reg_sdio_win_access_en*/
uint32_t reserved1 : 31; /*Reserved.*/
};
uint32_t val;
... | 1,027 |
*/
};
uint32_t val;
} front_end_mem_pd;
union {
struct {
uint32_t retention_link_addr : 27; /*reg_retention_link_addr*/
uint32_t nobypass_cpu_iso_rst : 1; /*reg_nobypass_cpu_iso_rst*/
uint32_t reserved28 : ... | 1,027 |
*/
};
uint32_t val;
} mem_power_down;
union {
struct {
uint32_t rom_power_up : 3; /*Set 1 to let rom power up*/
uint32_t sram_power_up : 4; /*Set 1 to let sram power up*/
uint32_t reserved7 :... | 1,027 |
*/
};
uint32_t val;
} peri_backup_int_raw;
union {
struct {
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_st*/
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_st*/
uint32_t reserved2 ... | 1,027 |
*/
};
uint32_t val;
} peri_backup_int_clr;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f... | 1,027 |
/*
*/
#pragma once
/**
*/
#define I2C_BOD 0x61
#define I2C_BOD_HOSTID 0
#define I2C_BOD_THRESHOLD 0x5
#define I2C_BOD_THRESHOLD_MSB 2
#define I2C_BOD_THRESHOLD_LSB 0
| 1,028 |
/*
*/
#pragma once
#include
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
/*IRAM0 is connected with Cache IBUS0*/
#define SOC_IRAM0_ADDRESS_LOW 0x4037C000
#define SOC_IRAM0_ADDRESS_HIGH ... | 1,031 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32C2 Root Clock Source
*/
/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!, F
/**
*/
typedef enum {
// For CPU doma... | 1,034 |
< PLL_F40M_CLK is derived from PLL, and has a fixed frequency of 40MHz */
SOC_MOD_CLK_PLL_F60M, /*!< PLL_F60M_CLK is derived from PLL, and has a fixed frequency of 60MHz */
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz *... | 1,034 |
< SYSTIMER source clock is XTAL */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t;
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
/**
*/
#define SOC_GPTI... | 1,034 |
< Select XTAL as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
} soc_periph_temperature_sensor_clk_src_t;
//////////////////////////////... | 1,034 |
< Select PLL_40M as SPI source clock */
SPI_CLK_SRC_PLL_F40M = SOC_MOD_CLK_PLL_F40M, /*!< Select PLL_40M as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
} soc_periph_spi_clk_src_t;
/**
*/
#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_... | 1,034 |
< Select PLL_F80M as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
} soc_periph_adc_digi_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
*/
#define... | 1,034 |
< Select PLL 40 Mhz as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F60M, SOC_MOD_CLK_RC_FAST}
/**
*/
typedef enum {
... | 1,034 |
< PLL_CLK is the output of crystal oscillator frequency multiplier */
CLKOUT_SIG_RC_SLOW = 4, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
CLKOUT_SIG_RC... | 1,034 |
/*
*/
#ifndef _SOC_SPI_REG_H_
#define _SOC_SPI_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
/*description: User define command enable. An operation will be triggered when the bit is se... | 1,035 |
.*/
#define SPI_CONF_BITLEN 0x0003FFFF
#define SPI_CONF_BITLEN_M ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
#define SPI_CONF_BITLEN_V 0x3FFFF
#define SPI_CONF_BITLEN_S 0
#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Address... | 1,035 |
Can be configured in CONF s
tate..*/
#define SPI_RD_BIT_ORDER 0x00000003
#define SPI_RD_BIT_ORDER_M ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S))
#define SPI_RD_BIT_ORDER_V 0x3
#define SPI_RD_BIT_ORDER_S 23
/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
/*description: Write protect signal output when SPI is... | 1,035 |
Can be configured in
CONF state..*/
#define SPI_Q_POL (BIT(18))
#define SPI_Q_POL_M (BIT(18))
#define SPI_Q_POL_V 0x1
#define SPI_Q_POL_S 18
/* SPI_FREAD_OCT : HRO ;bitpos:[16] ;default: 1'b0 ; */
/*description: In the read operations read-data phase apply 8 signals. 1: enable 0: disable. C
an be configured in ... | 1,035 |
Can be configured in C
ONF state..*/
#define SPI_FCMD_OCT (BIT(10))
#define SPI_FCMD_OCT_M (BIT(10))
#define SPI_FCMD_OCT_V 0x1
#define SPI_FCMD_OCT_S 10
/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C
ONF stat... | 1,035 |
Can be configured in CONF
state..*/
#define SPI_FADDR_QUAD (BIT(6))
#define SPI_FADDR_QUAD_M (BIT(6))
#define SPI_FADDR_QUAD_V 0x1
#define SPI_FADDR_QUAD_S 6
/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
s... | 1,035 |
Can be configured in CONF state..*/
#define SPI_CLK_EQU_SYSCLK (BIT(31))
#define SPI_CLK_EQU_SYSCLK_M (BIT(31))
#define SPI_CLK_EQU_SYSCLK_V 0x1
#define SPI_CLK_EQU_SYSCLK_S 31
/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
/*description: In the master mode it is pre-divider of spi_clk. Can be conf... | 1,035 |
In the slave mode it
must be 0. Can be configured in CONF state..*/
#define SPI_CLKCNT_H 0x0000003F
#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
#define SPI_CLKCNT_H_V 0x3F
#define SPI_CLKCNT_H_S 6
/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
/*description: In the master mode it must be... | 1,035 |
Can be configured in CONF sta
te..*/
#define SPI_USR_ADDR (BIT(30))
#define SPI_USR_ADDR_M (BIT(30))
#define SPI_USR_ADDR_V 0x1
#define SPI_USR_ADDR_S 30
/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
..*/
#d... | 1,035 |
Can be configured in
CONF state..*/
#define SPI_USR_DUMMY_IDLE (BIT(26))
#define SPI_USR_DUMMY_IDLE_M (BIT(26))
#define SPI_USR_DUMMY_IDLE_V 0x1
#define SPI_USR_DUMMY_IDLE_S 26
/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: write-data phase only access to high-part of the buffer ... | 1,035 |
1: enable 0: disable. Can be configured in CONF state..*/
#define SPI_SIO (BIT(17))
#define SPI_SIO_M (BIT(17))
#define SPI_SIO_V 0x1
#define SPI_SIO_S 17
/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
will... | 1,035 |
Can be configured in CO
NF state..*/
#define SPI_FWRITE_QUAD (BIT(13))
#define SPI_FWRITE_QUAD_M (BIT(13))
#define SPI_FWRITE_QUAD_V 0x1
#define SPI_FWRITE_QUAD_S 13
/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: In the write operations read-data phase apply 2 signals. Can be configured... | 1,035 |
1: enable 0: disable. Can be co
nfigured in CONF state..*/
#define SPI_CS_SETUP (BIT(7))
#define SPI_CS_SETUP_M (BIT(7))
#define SPI_CS_SETUP_V 0x1
#define SPI_CS_SETUP_S 7
/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable. Can b... | 1,035 |
1: spi controller is in QPI mode. 0: others
. Can be configured in CONF state..*/
#define SPI_QPI_MODE (BIT(3))
#define SPI_QPI_MODE_M (BIT(3))
#define SPI_QPI_MODE_V 0x1
#define SPI_QPI_MODE_S 3
/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set the bit to enable full duplex communication. ... | 1,035 |
Can be configured in CONF state..*/
#define SPI_CS_HOLD_TIME 0x0000001F
#define SPI_CS_HOLD_TIME_M ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
#define SPI_CS_HOLD_TIME_V 0x1F
#define SPI_CS_HOLD_TIME_S 22
/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
/*description: (cycles+1) of prepare phase ... | 1,035 |
The register value shall be (cycle_
num-1). Can be configured in CONF state..*/
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
#define SPI_USR_DUMMY_CYCLELEN_V 0xFF
#define SPI_USR_DUMMY_CYCLELEN_S 0
#define SPI_USER2_REG(i) ... | 1,035 |
.*/
#define SPI_MST_REMPTY_ERR_END_EN (BIT(27))
#define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27))
#define SPI_MST_REMPTY_ERR_END_EN_V 0x1
#define SPI_MST_REMPTY_ERR_END_EN_S 27
/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
/*description: The value of command. Can be configured in CONF state..*/
... | 1,035 |
0
: spi quad input swap disable. Can be configured in CONF state..*/
#define SPI_QUAD_DIN_PIN_SWAP (BIT(31))
#define SPI_QUAD_DIN_PIN_SWAP_M (BIT(31))
#define SPI_QUAD_DIN_PIN_SWAP_V 0x1
#define SPI_QUAD_DIN_PIN_SWAP_S 31
/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: spi cs line ke... | 1,035 |
1: inv 0: not change. Can be configured in
CONF state..*/
#define SPI_SLAVE_CS_POL (BIT(23))
#define SPI_SLAVE_CS_POL_M (BIT(23))
#define SPI_SLAVE_CS_POL_V 0x1
#define SPI_SLAVE_CS_POL_S 23
/* SPI_CMD_DTR_EN : HRO ;bitpos:[19] ;default: 1'b0 ; */
/*description: 1: SPI clk and data of SPI_SEND_CMD state are in ... | 1,035 |
0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR m
ode. Can be configured in CONF state..*/
#define SPI_DATA_DTR_EN (BIT(17))
#define SPI_DATA_DTR_EN_M (BIT(17))
#define SPI_DATA_DTR_EN_V 0x1
#define SPI_DATA_DTR_EN_S 17
/* SPI_CLK_DATA_DTR_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
/*description: 1... | 1,035 |
Can be configured in CONF state..*/
#define SPI_CK_DIS (BIT(6))
#define SPI_CK_DIS_M (BIT(6))
#define SPI_CK_DIS_V 0x1
#define SPI_CK_DIS_S 6
/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
n be configured in CON... | 1,035 |
Ca
n be configured in CONF state..*/
#define SPI_CS2_DIS (BIT(2))
#define SPI_CS2_DIS_M (BIT(2))
#define SPI_CS2_DIS_V 0x1
#define SPI_CS2_DIS_S 2
/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
n be configured i... | 1,035 |
Can be configured in CONF state..*/
#define SPI_DIN7_MODE 0x00000003
#define SPI_DIN7_MODE_M ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S))
#define SPI_DIN7_MODE_V 0x3
#define SPI_DIN7_MODE_S 14
/* SPI_DIN6_MODE : HRO ;bitpos:[13:12] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cy... | 1,035 |
Can be configured in CONF state..*/
#define SPI_DIN4_MODE 0x00000003
#define SPI_DIN4_MODE_M ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S))
#define SPI_DIN4_MODE_V 0x3
#define SPI_DIN4_MODE_S 8
/* SPI_DIN3_MODE : HRO ;bitpos:[7:6] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycle... | 1,035 |
Can be configured in CONF state..*/
#define SPI_DIN1_MODE 0x00000003
#define SPI_DIN1_MODE_M ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
#define SPI_DIN1_MODE_V 0x3
#define SPI_DIN1_MODE_S 2
/* SPI_DIN0_MODE : HRO ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycle... | 1,035 |
.. Can be configured in CONF state..*/
#define SPI_DIN6_NUM 0x00000003
#define SPI_DIN6_NUM_M ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S))
#define SPI_DIN6_NUM_V 0x3
#define SPI_DIN6_NUM_S 12
/* SPI_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycles... | 1,035 |
.. Can be configured in CONF state..*/
#define SPI_DIN3_NUM 0x00000003
#define SPI_DIN3_NUM_M ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
#define SPI_DIN3_NUM_V 0x3
#define SPI_DIN3_NUM_S 6
/* SPI_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycles, 0... | 1,035 |
.. Can be configured in CONF state..*/
#define SPI_DIN0_NUM 0x00000003
#define SPI_DIN0_NUM_M ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
#define SPI_DIN0_NUM_V 0x3
#define SPI_DIN0_NUM_S 0
#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2C)
/* SPI_D_DQS_MODE : HRO ;bitpos:[8] ;default: 1'b0 ; */
/*descript... | 1,035 |
Can be co
nfigured in CONF state..*/
#define SPI_DOUT6_MODE (BIT(6))
#define SPI_DOUT6_MODE_M (BIT(6))
#define SPI_DOUT6_MODE_V 0x1
#define SPI_DOUT6_MODE_S 6
/* SPI_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
ed... | 1,035 |
Can be co
nfigured in CONF state..*/
#define SPI_DOUT3_MODE (BIT(3))
#define SPI_DOUT3_MODE_M (BIT(3))
#define SPI_DOUT3_MODE_V 0x1
#define SPI_DOUT3_MODE_S 3
/* SPI_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
ed... | 1,035 |
Can be co
nfigured in CONF state..*/
#define SPI_DOUT0_MODE (BIT(0))
#define SPI_DOUT0_MODE_M (BIT(0))
#define SPI_DOUT0_MODE_V 0x1
#define SPI_DOUT0_MODE_S 0
#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
/*description: Set this bit to r... | 1,035 |
.*/
#define SPI_RX_AFIFO_RST (BIT(29))
#define SPI_RX_AFIFO_RST_M (BIT(29))
#define SPI_RX_AFIFO_RST_V 0x1
#define SPI_RX_AFIFO_RST_S 29
/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: Set this bit to enable SPI DMA controlled send data mode..*/
#define SPI_DMA_TX_ENA (BIT(28))
#define ... | 1,035 |
.*/
#define SPI_RX_EOF_EN (BIT(21))
#define SPI_RX_EOF_EN_M (BIT(21))
#define SPI_RX_EOF_EN_V 0x1
#define SPI_RX_EOF_EN_S 21
/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
mpty_vld is cleared by ... | 1,035 |
1: enable. 0: disable..*/
#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18))
#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18))
#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1
#define SPI_DMA_SLV_SEG_TRANS_EN_S 18
/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: Records the status of DMA RX FIFO. 1: DMA RX FI... | 1,035 |
.*/
#define SPI_APP1_INT_ENA (BIT(20))
#define SPI_APP1_INT_ENA_M (BIT(20))
#define SPI_APP1_INT_ENA_V 0x1
#define SPI_APP1_INT_ENA_S 20
/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: The enable bit for SPI_APP2_INT interrupt..*/
#define SPI_APP2_INT_ENA (BIT(19))
#define SPI_APP2_IN... | 1,035 |
.*/
#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16))
#define SPI_SLV_CMD_ERR_INT_ENA_M (BIT(16))
#define SPI_SLV_CMD_ERR_INT_ENA_V 0x1
#define SPI_SLV_CMD_ERR_INT_ENA_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
#defi... | 1,035 |
.*/
#define SPI_TRANS_DONE_INT_ENA (BIT(12))
#define SPI_TRANS_DONE_INT_ENA_M (BIT(12))
#define SPI_TRANS_DONE_INT_ENA_V 0x1
#define SPI_TRANS_DONE_INT_ENA_S 12
/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
#define SPI... | 1,035 |
.*/
#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x1
#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8
/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave CMDA interrupt..*/
#define SPI... | 1,035 |
.*/
#define SPI_SLV_CMD7_INT_ENA (BIT(4))
#define SPI_SLV_CMD7_INT_ENA_M (BIT(4))
#define SPI_SLV_CMD7_INT_ENA_V 0x1
#define SPI_SLV_CMD7_INT_ENA_S 4
/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave En_QPI interrupt..*/
#define SPI_SLV_EN_QPI_INT_ENA (... | 1,035 |
.*/
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x1
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0
#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ;... | 1,035 |
.*/
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17))
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (BIT(17))
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x1
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17
/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
/*description: The clear bit for SPI_SLV... | 1,035 |
.*/
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x1
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13
/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
/*description: The clear bit for SPI_TRANS_DONE_INT inter... | 1,035 |
.*/
#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9))
#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (BIT(9))
#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x1
#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9
/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..... | 1,035 |
.*/
#define SPI_SLV_CMD8_INT_CLR (BIT(5))
#define SPI_SLV_CMD8_INT_CLR_M (BIT(5))
#define SPI_SLV_CMD8_INT_CLR_V 0x1
#define SPI_SLV_CMD8_INT_CLR_S 5
/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The clear bit for SPI slave CMD7 interrupt..*/
#define SPI_SLV_CMD7_INT_CLR (BIT(4))
... | 1,035 |
.*/
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1
/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: The clear bit for SPI_DMA... | 1,035 |
The value is only controlled by software
..*/
#define SPI_APP2_INT_RAW (BIT(19))
#define SPI_APP2_INT_RAW_M (BIT(19))
#define SPI_APP2_INT_RAW_V 0x1
#define SPI_APP2_INT_RAW_S 19
/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
/*description: The raw bit for SPI_MST_TX_AFIFO_REM... | 1,035 |
1: The slave command value in the
current SPI slave HD mode transmission is not supported. 0: Others..*/
#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16))
#define SPI_SLV_CMD_ERR_INT_RAW_M (BIT(16))
#define SPI_SLV_CMD_ERR_INT_RAW_V 0x1
#define SPI_SLV_CMD_ERR_INT_RAW_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bi... | 1,035 |
1: spi master DMA full-du
plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
ta has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is
not ended or not occurred..*/
#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (BIT(13... | 1,035 |
1: SPI slave mode Rd_BUF tran
smission is ended. 0: Others..*/
#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10))
#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (BIT(10))
#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x1
#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10
/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */... | 1,035 |
1: SPI slave mode CMDA transmission is
ended. 0: Others..*/
#define SPI_SLV_CMDA_INT_RAW (BIT(7))
#define SPI_SLV_CMDA_INT_RAW_M (BIT(7))
#define SPI_SLV_CMDA_INT_RAW_V 0x1
#define SPI_SLV_CMDA_INT_RAW_S 7
/* SPI_SLV_CMD9_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw bit for SPI slav... | 1,035 |
1: SPI slave mode CMD7 transmission is
ended. 0: Others..*/
#define SPI_SLV_CMD7_INT_RAW (BIT(4))
#define SPI_SLV_CMD7_INT_RAW_M (BIT(4))
#define SPI_SLV_CMD7_INT_RAW_V 0x1
#define SPI_SLV_CMD7_INT_RAW_S 4
/* SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw bit for SPI sl... | 1,035 |
SPI will stop in
master mode and send out all 0 in slave mode. 0: Others..*/
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1
/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW :... | 1,035 |
.*/
#define SPI_APP2_INT_ST (BIT(19))
#define SPI_APP2_INT_ST_M (BIT(19))
#define SPI_APP2_INT_ST_V 0x1
#define SPI_APP2_INT_ST_S 19
/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
#define SPI_MST_TX_AFIFO_... | 1,035 |
.*/
#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15))
#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (BIT(15))
#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x1
#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15
/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..... | 1,035 |
.*/
#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11))
#define SPI_SLV_WR_BUF_DONE_INT_ST_M (BIT(11))
#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x1
#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11
/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..... | 1,035 |
.*/
#define SPI_SLV_CMDA_INT_ST (BIT(7))
#define SPI_SLV_CMDA_INT_ST_M (BIT(7))
#define SPI_SLV_CMDA_INT_ST_V 0x1
#define SPI_SLV_CMDA_INT_ST_S 7
/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The status bit for SPI slave CMD9 interrupt..*/
#define SPI_SLV_CMD9_INT_ST (BIT(6))
#defi... | 1,035 |
.*/
#define SPI_SLV_EN_QPI_INT_ST (BIT(3))
#define SPI_SLV_EN_QPI_INT_ST_M (BIT(3))
#define SPI_SLV_EN_QPI_INT_ST_V 0x1
#define SPI_SLV_EN_QPI_INT_ST_S 3
/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The status bit for SPI slave Ex_QPI interrupt..*/
#define SPI_SLV_EX_QPI_INT_ST ... | 1,035 |
.*/
#define SPI_APP1_INT_SET (BIT(20))
#define SPI_APP1_INT_SET_M (BIT(20))
#define SPI_APP1_INT_SET_V 0x1
#define SPI_APP1_INT_SET_S 20
/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */
/*description: The software set bit for SPI_APP2_INT interrupt..*/
#define SPI_APP2_INT_SET (BIT(19))
#define SPI_AP... | 1,035 |
.*/
#define SPI_SLV_CMD_ERR_INT_SET (BIT(16))
#define SPI_SLV_CMD_ERR_INT_SET_M (BIT(16))
#define SPI_SLV_CMD_ERR_INT_SET_V 0x1
#define SPI_SLV_CMD_ERR_INT_SET_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
... | 1,035 |
.*/
#define SPI_TRANS_DONE_INT_SET (BIT(12))
#define SPI_TRANS_DONE_INT_SET_M (BIT(12))
#define SPI_TRANS_DONE_INT_SET_V 0x1
#define SPI_TRANS_DONE_INT_SET_S 12
/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
#defin... | 1,035 |
.*/
#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_SET_M (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x1
#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8
/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave CMDA interrupt..*/
#defin... | 1,035 |
.*/
#define SPI_SLV_CMD7_INT_SET (BIT(4))
#define SPI_SLV_CMD7_INT_SET_M (BIT(4))
#define SPI_SLV_CMD7_INT_SET_V 0x1
#define SPI_SLV_CMD7_INT_SET_S 4
/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave En_QPI interrupt..*/
#define SPI_SLV_EN_QPI_INT_SET... | 1,035 |
.*/
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x1
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0
#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*desc... | 1,035 |
*/
#define SPI_BUF3 0xFFFFFFFF
#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S))
#define SPI_BUF3_V 0xFFFFFFFF
#define SPI_BUF3_S 0
#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xA8)
/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF4 0xFFFFFFFF
#define S... | 1,035 |
*/
#define SPI_BUF7 0xFFFFFFFF
#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S))
#define SPI_BUF7_V 0xFFFFFFFF
#define SPI_BUF7_S 0
#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xB8)
/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF8 0xFFFFFFFF
#define S... | 1,035 |
*/
#define SPI_BUF11 0xFFFFFFFF
#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S))
#define SPI_BUF11_V 0xFFFFFFFF
#define SPI_BUF11_S 0
#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xC8)
/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF12 0xFFFFFFFF
... | 1,035 |
*/
#define SPI_BUF15 0xFFFFFFFF
#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S))
#define SPI_BUF15_V 0xFFFFFFFF
#define SPI_BUF15_S 0
#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xE0)
/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: 1: Enable the DMA CONF phase of current seg-tran... | 1,035 |
.*/
#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F
#define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
#define SPI_DMA_SEG_MAGIC_VALUE_V 0xF
#define SPI_DMA_SEG_MAGIC_VALUE_S 22
/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: 1: SPI_SLV_DATA_BI... | 1,035 |
0: others.*/
#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9))
#define SPI_SLV_WRDMA_BITLEN_EN_M (BIT(9))
#define SPI_SLV_WRDMA_BITLEN_EN_V 0x1
#define SPI_SLV_WRDMA_BITLEN_EN_S 9
/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-s... | 1,035 |
0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
#define SPI_CLK_MODE_13 (BIT(2))
#define SPI_CLK_MODE_13_M (BIT(2))
#define SPI_CLK_MODE_13_V 0x1
#define SPI_CLK_MODE_13_S 2
/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: SPI clock mode bits. 0: SPI clock is off when... | 1,035 |
.*/
#define SPI_SLV_LAST_COMMAND 0x000000FF
#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
#define SPI_SLV_LAST_COMMAND_V 0xFF
#define SPI_SLV_LAST_COMMAND_S 18
/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
/*description: The transferred data bit length i... | 1,035 |
.*/
#define SPI_MST_CLK_ACTIVE (BIT(1))
#define SPI_MST_CLK_ACTIVE_M (BIT(1))
#define SPI_MST_CLK_ACTIVE_V 0x1
#define SPI_MST_CLK_ACTIVE_S 1
/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to enable clk gate.*/
#define SPI_CLK_EN (BIT(0))
#define SPI_CLK_EN_M (BIT(0))
#define ... | 1,035 |
/*
*/
#define DR_REG_SYSTEM_BASE 0x600c0000
#define DR_REG_SENSITIVE_BASE 0x600c1000
#define DR_REG_INTERRUPT_BASE 0x600c2000
#define DR_REG_EXTMEM_BASE 0x600c4000 // CACHE_CONFIG
#define DR_REG_MMU_TABLE 0x600c5000
#d... | 1,036 |
/*
*/
#pragma once
#ifndef __ASSEMBLER__
#include
#include "esp_assert.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
#define DR_REG_RTC_BLE_TIMER_BASE( i ) ( \
( (i) == 0 ) ? ( 0x6004E000 ) : \
... | 1,037 |
(DR_REG_SPI2_BASE) : (0)) // only one GPSPI
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
//write value to register
#define REG_WRITE(_r, _v) do { ... | 1,037 |
__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader sys... | 1,037 |
#define SOC_DIRAM_IRAM_LOW 0x40380000
#define SOC_DIRAM_IRAM_HIGH 0x403C0000
#define SOC_DIRAM_DRAM_LOW 0x3FCA0000
#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
#define MAP_IRAM_TO_DRAM(addr) (ad... | 1,037 |
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